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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
139 } else if (ctx
->program
->chip_class
<= GFX7
) {
140 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
143 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
148 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
150 Builder
bld(ctx
->program
, ctx
->block
);
153 dst
= bld
.tmp(src
.regClass());
155 assert(src
.size() == dst
.size());
157 if (ctx
->stage
!= fragment_fs
) {
161 bld
.copy(Definition(dst
), src
);
165 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
166 ctx
->program
->needs_wqm
|= program_needs_wqm
;
170 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
172 if (index
.regClass() == s1
)
173 return bld
.readlane(bld
.def(s1
), data
, index
);
175 if (ctx
->options
->chip_class
<= GFX7
) {
176 /* GFX6-7: there is no bpermute instruction */
177 Operand
index_op(index
);
178 Operand
input_data(data
);
179 index_op
.setLateKill(true);
180 input_data
.setLateKill(true);
182 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
183 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
184 /* GFX10 wave64 mode: emulate full-wave bpermute */
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
192 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
193 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
194 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
195 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
196 Operand
input_data(data
);
198 index_x4
.setLateKill(true);
199 input_data
.setLateKill(true);
200 same_half
.setLateKill(true);
202 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
204 /* GFX8-9 or GFX10 wave32: bpermute works normally */
205 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
206 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
210 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
212 if (ctx
->options
->chip_class
>= GFX8
) {
213 unsigned and_mask
= mask
& 0x1f;
214 unsigned or_mask
= (mask
>> 5) & 0x1f;
215 unsigned xor_mask
= (mask
>> 10) & 0x1f;
217 uint16_t dpp_ctrl
= 0xffff;
219 // TODO: we could use DPP8 for some swizzles
220 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
221 unsigned res
[4] = {0, 1, 2, 3};
222 for (unsigned i
= 0; i
< 4; i
++)
223 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
224 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
225 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
226 dpp_ctrl
= dpp_row_rr(8);
227 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
228 dpp_ctrl
= dpp_row_mirror
;
229 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
230 dpp_ctrl
= dpp_row_half_mirror
;
233 if (dpp_ctrl
!= 0xffff)
234 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
237 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
240 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
242 if (val
.type() == RegType::sgpr
) {
243 Builder
bld(ctx
->program
, ctx
->block
);
244 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
246 assert(val
.type() == RegType::vgpr
);
250 //assumes a != 0xffffffff
251 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
254 Builder
bld(ctx
->program
, ctx
->block
);
256 if (util_is_power_of_two_or_zero(b
)) {
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
261 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
263 assert(info
.multiplier
<= 0xffffffff);
265 bool pre_shift
= info
.pre_shift
!= 0;
266 bool increment
= info
.increment
!= 0;
267 bool multiply
= true;
268 bool post_shift
= info
.post_shift
!= 0;
270 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
271 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
275 Temp pre_shift_dst
= a
;
277 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
278 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
281 Temp increment_dst
= pre_shift_dst
;
283 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
284 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
287 Temp multiply_dst
= increment_dst
;
289 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
290 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
291 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
299 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
301 Builder
bld(ctx
->program
, ctx
->block
);
302 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
306 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
308 /* no need to extract the whole vector */
309 if (src
.regClass() == dst_rc
) {
314 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
315 Builder
bld(ctx
->program
, ctx
->block
);
316 auto it
= ctx
->allocated_vec
.find(src
.id());
317 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
318 if (it
->second
[idx
].regClass() == dst_rc
) {
319 return it
->second
[idx
];
321 assert(!dst_rc
.is_subdword());
322 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
323 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
327 if (dst_rc
.is_subdword())
328 src
= as_vgpr(ctx
, src
);
330 if (src
.bytes() == dst_rc
.bytes()) {
332 return bld
.copy(bld
.def(dst_rc
), src
);
334 Temp dst
= bld
.tmp(dst_rc
);
335 emit_extract_vector(ctx
, src
, idx
, dst
);
340 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
342 if (num_components
== 1)
344 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
347 if (num_components
> vec_src
.size()) {
348 if (vec_src
.type() == RegType::sgpr
) {
349 /* should still help get_alu_src() */
350 emit_split_vector(ctx
, vec_src
, vec_src
.size());
353 /* sub-dword split */
354 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
356 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
358 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
359 split
->operands
[0] = Operand(vec_src
);
360 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
361 for (unsigned i
= 0; i
< num_components
; i
++) {
362 elems
[i
] = {ctx
->program
->allocateId(), rc
};
363 split
->definitions
[i
] = Definition(elems
[i
]);
365 ctx
->block
->instructions
.emplace_back(std::move(split
));
366 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
369 /* This vector expansion uses a mask to determine which elements in the new vector
370 * come from the original vector. The other elements are undefined. */
371 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
373 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
378 Builder
bld(ctx
->program
, ctx
->block
);
379 if (num_components
== 1) {
380 if (dst
.type() == RegType::sgpr
)
381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
383 bld
.copy(Definition(dst
), vec_src
);
387 unsigned component_size
= dst
.size() / num_components
;
388 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
390 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
391 vec
->definitions
[0] = Definition(dst
);
393 for (unsigned i
= 0; i
< num_components
; i
++) {
394 if (mask
& (1 << i
)) {
395 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
396 if (dst
.type() == RegType::sgpr
)
397 src
= bld
.as_uniform(src
);
398 vec
->operands
[i
] = Operand(src
);
400 vec
->operands
[i
] = Operand(0u);
402 elems
[i
] = vec
->operands
[i
].getTemp();
404 ctx
->block
->instructions
.emplace_back(std::move(vec
));
405 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
408 /* adjust misaligned small bit size loads */
409 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
411 Builder
bld(ctx
->program
, ctx
->block
);
413 Temp select
= Temp();
414 if (offset
.isConstant()) {
415 assert(offset
.constantValue() && offset
.constantValue() < 4);
416 shift
= Operand(offset
.constantValue() * 8);
418 /* bit_offset = 8 * (offset & 0x3) */
419 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
420 select
= bld
.tmp(s1
);
421 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
424 if (vec
.size() == 1) {
425 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
426 } else if (vec
.size() == 2) {
427 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
428 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
430 emit_split_vector(ctx
, dst
, 2);
432 emit_extract_vector(ctx
, tmp
, 0, dst
);
433 } else if (vec
.size() == 4) {
434 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
435 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
436 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
437 if (select
!= Temp())
438 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
439 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
440 Temp mid
= bld
.tmp(s1
);
441 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
442 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
443 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
444 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
445 emit_split_vector(ctx
, dst
, 2);
449 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
451 Builder
bld(ctx
->program
, ctx
->block
);
452 if (offset
.isTemp()) {
453 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
455 if (vec
.size() == 4) {
456 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
458 } else if (vec
.size() == 3) {
459 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
461 } else if (vec
.size() == 2) {
462 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
465 for (unsigned i
= 0; i
< dst
.size(); i
++)
466 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
470 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
472 offset
= Operand(0u);
475 unsigned num_components
= vec
.bytes() / component_size
;
476 if (vec
.regClass() == dst
.regClass()) {
477 assert(offset
.constantValue() == 0);
478 bld
.copy(Definition(dst
), vec
);
479 emit_split_vector(ctx
, dst
, num_components
);
483 emit_split_vector(ctx
, vec
, num_components
);
484 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
485 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
487 assert(offset
.constantValue() % component_size
== 0);
488 unsigned skip
= offset
.constantValue() / component_size
;
489 for (unsigned i
= skip
; i
< num_components
; i
++)
490 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
492 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
493 if (dst
.type() == RegType::vgpr
) {
494 num_components
= dst
.bytes() / component_size
;
495 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
496 for (unsigned i
= 0; i
< num_components
; i
++)
497 create_vec
->operands
[i
] = Operand(elems
[i
]);
498 create_vec
->definitions
[0] = Definition(dst
);
499 bld
.insert(std::move(create_vec
));
501 /* if dst is sgpr - split the src, but move the original to sgpr. */
503 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
504 byte_align_scalar(ctx
, vec
, offset
, dst
);
506 assert(dst
.size() == vec
.size());
507 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
510 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
513 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
515 Builder
bld(ctx
->program
, ctx
->block
);
517 dst
= bld
.tmp(bld
.lm
);
519 assert(val
.regClass() == s1
);
520 assert(dst
.regClass() == bld
.lm
);
522 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
525 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
527 Builder
bld(ctx
->program
, ctx
->block
);
531 assert(val
.regClass() == bld
.lm
);
532 assert(dst
.regClass() == s1
);
534 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
535 Temp tmp
= bld
.tmp(s1
);
536 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
537 return emit_wqm(ctx
, tmp
, dst
);
540 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
542 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
543 return get_ssa_temp(ctx
, src
.src
.ssa
);
545 if (src
.src
.ssa
->num_components
== size
) {
546 bool identity_swizzle
= true;
547 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
548 if (src
.swizzle
[i
] != i
)
549 identity_swizzle
= false;
551 if (identity_swizzle
)
552 return get_ssa_temp(ctx
, src
.src
.ssa
);
555 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
556 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
557 assert(elem_size
> 0);
558 assert(vec
.bytes() % elem_size
== 0);
560 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
561 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
563 unsigned swizzle
= src
.swizzle
[0];
564 if (vec
.size() > 1) {
565 assert(src
.src
.ssa
->bit_size
== 16);
566 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
567 swizzle
= swizzle
& 1;
572 Temp dst
{ctx
->program
->allocateId(), s1
};
573 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
574 bfe
->operands
[0] = Operand(vec
);
575 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
576 bfe
->definitions
[0] = Definition(dst
);
577 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
578 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
582 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
584 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
587 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
588 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
589 for (unsigned i
= 0; i
< size
; ++i
) {
590 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
591 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
593 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
594 vec_instr
->definitions
[0] = Definition(dst
);
595 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
596 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
601 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
605 Builder
bld(ctx
->program
, ctx
->block
);
606 if (ptr
.type() == RegType::vgpr
)
607 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
608 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
609 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
612 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
614 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
615 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
616 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
617 sop2
->definitions
[0] = Definition(dst
);
618 if (instr
->no_unsigned_wrap
)
619 sop2
->definitions
[0].setNUW(true);
621 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
622 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
625 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
626 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
628 Builder
bld(ctx
->program
, ctx
->block
);
629 bld
.is_precise
= instr
->exact
;
631 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
632 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
633 if (src1
.type() == RegType::sgpr
) {
634 if (commutative
&& src0
.type() == RegType::vgpr
) {
639 src1
= as_vgpr(ctx
, src1
);
643 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
644 assert(dst
.size() == 1);
645 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
646 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
648 bld
.vop2(op
, Definition(dst
), src0
, src1
);
652 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
653 aco_opcode op
, Temp dst
)
655 Builder
bld(ctx
->program
, ctx
->block
);
656 bld
.is_precise
= instr
->exact
;
658 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
659 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
661 if (src1
.type() == RegType::sgpr
) {
662 assert(src0
.type() == RegType::vgpr
);
663 std::swap(src0
, src1
);
666 Temp src00
= bld
.tmp(src0
.type(), 1);
667 Temp src01
= bld
.tmp(src0
.type(), 1);
668 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
669 Temp src10
= bld
.tmp(v1
);
670 Temp src11
= bld
.tmp(v1
);
671 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
672 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
673 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
674 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
677 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
678 bool flush_denorms
= false)
680 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
681 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
682 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
684 /* ensure that the instruction has at most 1 sgpr operand
685 * The optimizer will inline constants for us */
686 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
687 src0
= as_vgpr(ctx
, src0
);
688 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
689 src1
= as_vgpr(ctx
, src1
);
690 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
691 src2
= as_vgpr(ctx
, src2
);
693 Builder
bld(ctx
->program
, ctx
->block
);
694 bld
.is_precise
= instr
->exact
;
695 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
696 assert(dst
.size() == 1);
697 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
698 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
700 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
704 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
706 Builder
bld(ctx
->program
, ctx
->block
);
707 bld
.is_precise
= instr
->exact
;
708 if (dst
.type() == RegType::sgpr
)
709 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
710 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
712 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
715 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
717 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
718 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
719 assert(src0
.size() == src1
.size());
721 aco_ptr
<Instruction
> vopc
;
722 if (src1
.type() == RegType::sgpr
) {
723 if (src0
.type() == RegType::vgpr
) {
724 /* to swap the operands, we might also have to change the opcode */
726 case aco_opcode::v_cmp_lt_f16
:
727 op
= aco_opcode::v_cmp_gt_f16
;
729 case aco_opcode::v_cmp_ge_f16
:
730 op
= aco_opcode::v_cmp_le_f16
;
732 case aco_opcode::v_cmp_lt_i16
:
733 op
= aco_opcode::v_cmp_gt_i16
;
735 case aco_opcode::v_cmp_ge_i16
:
736 op
= aco_opcode::v_cmp_le_i16
;
738 case aco_opcode::v_cmp_lt_u16
:
739 op
= aco_opcode::v_cmp_gt_u16
;
741 case aco_opcode::v_cmp_ge_u16
:
742 op
= aco_opcode::v_cmp_le_u16
;
744 case aco_opcode::v_cmp_lt_f32
:
745 op
= aco_opcode::v_cmp_gt_f32
;
747 case aco_opcode::v_cmp_ge_f32
:
748 op
= aco_opcode::v_cmp_le_f32
;
750 case aco_opcode::v_cmp_lt_i32
:
751 op
= aco_opcode::v_cmp_gt_i32
;
753 case aco_opcode::v_cmp_ge_i32
:
754 op
= aco_opcode::v_cmp_le_i32
;
756 case aco_opcode::v_cmp_lt_u32
:
757 op
= aco_opcode::v_cmp_gt_u32
;
759 case aco_opcode::v_cmp_ge_u32
:
760 op
= aco_opcode::v_cmp_le_u32
;
762 case aco_opcode::v_cmp_lt_f64
:
763 op
= aco_opcode::v_cmp_gt_f64
;
765 case aco_opcode::v_cmp_ge_f64
:
766 op
= aco_opcode::v_cmp_le_f64
;
768 case aco_opcode::v_cmp_lt_i64
:
769 op
= aco_opcode::v_cmp_gt_i64
;
771 case aco_opcode::v_cmp_ge_i64
:
772 op
= aco_opcode::v_cmp_le_i64
;
774 case aco_opcode::v_cmp_lt_u64
:
775 op
= aco_opcode::v_cmp_gt_u64
;
777 case aco_opcode::v_cmp_ge_u64
:
778 op
= aco_opcode::v_cmp_le_u64
;
780 default: /* eq and ne are commutative */
787 src1
= as_vgpr(ctx
, src1
);
791 Builder
bld(ctx
->program
, ctx
->block
);
792 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
795 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
797 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
798 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
799 Builder
bld(ctx
->program
, ctx
->block
);
801 assert(dst
.regClass() == bld
.lm
);
802 assert(src0
.type() == RegType::sgpr
);
803 assert(src1
.type() == RegType::sgpr
);
804 assert(src0
.regClass() == src1
.regClass());
806 /* Emit the SALU comparison instruction */
807 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
808 /* Turn the result into a per-lane bool */
809 bool_to_vector_condition(ctx
, cmp
, dst
);
812 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
813 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
815 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
816 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
817 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
818 nir_dest_is_divergent(instr
->dest
.dest
) ||
819 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
820 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
821 aco_opcode op
= use_valu
? v_op
: s_op
;
822 assert(op
!= aco_opcode::num_opcodes
);
823 assert(dst
.regClass() == ctx
->program
->lane_mask
);
826 emit_vopc_instruction(ctx
, instr
, op
, dst
);
828 emit_sopc_instruction(ctx
, instr
, op
, dst
);
831 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
833 Builder
bld(ctx
->program
, ctx
->block
);
834 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
835 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
837 assert(dst
.regClass() == bld
.lm
);
838 assert(src0
.regClass() == bld
.lm
);
839 assert(src1
.regClass() == bld
.lm
);
841 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
844 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
846 Builder
bld(ctx
->program
, ctx
->block
);
847 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
848 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
849 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
851 assert(cond
.regClass() == bld
.lm
);
853 if (dst
.type() == RegType::vgpr
) {
854 aco_ptr
<Instruction
> bcsel
;
855 if (dst
.size() == 1) {
856 then
= as_vgpr(ctx
, then
);
857 els
= as_vgpr(ctx
, els
);
859 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
860 } else if (dst
.size() == 2) {
861 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
863 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
864 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
866 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
867 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
872 nir_print_instr(&instr
->instr
, stderr
);
873 fprintf(stderr
, "\n");
878 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
879 assert(dst
.regClass() == bld
.lm
);
880 assert(then
.regClass() == bld
.lm
);
881 assert(els
.regClass() == bld
.lm
);
884 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
885 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
886 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
887 assert(dst
.size() == then
.size());
888 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
889 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
891 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
892 nir_print_instr(&instr
->instr
, stderr
);
893 fprintf(stderr
, "\n");
898 /* divergent boolean bcsel
899 * this implements bcsel on bools: dst = s0 ? s1 : s2
900 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
901 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
903 if (cond
.id() != then
.id())
904 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
906 if (cond
.id() == els
.id())
907 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
909 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
910 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
913 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
914 aco_opcode op
, uint32_t undo
)
916 /* multiply by 16777216 to handle denormals */
917 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
918 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
919 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
920 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
921 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
923 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
925 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
928 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
930 if (ctx
->block
->fp_mode
.denorm32
== 0) {
931 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
935 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
938 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
940 if (ctx
->block
->fp_mode
.denorm32
== 0) {
941 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
945 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
948 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
950 if (ctx
->block
->fp_mode
.denorm32
== 0) {
951 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
955 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
958 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
960 if (ctx
->block
->fp_mode
.denorm32
== 0) {
961 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
965 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
968 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
970 if (ctx
->options
->chip_class
>= GFX7
)
971 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
973 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
974 /* TODO: create more efficient code! */
975 if (val
.type() == RegType::sgpr
)
976 val
= as_vgpr(ctx
, val
);
978 /* Split the input value. */
979 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
980 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
982 /* Extract the exponent and compute the unbiased value. */
983 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
984 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
986 /* Extract the fractional part. */
987 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
988 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
990 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
991 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
993 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
994 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
995 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
996 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
997 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
999 /* Get the sign bit. */
1000 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1002 /* Decide the operation to apply depending on the unbiased exponent. */
1003 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1004 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1005 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1006 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1007 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1008 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1010 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1013 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1015 if (ctx
->options
->chip_class
>= GFX7
)
1016 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1018 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1019 * lowered at NIR level for precision reasons). */
1020 Temp src0
= as_vgpr(ctx
, val
);
1022 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1023 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1025 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1026 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1027 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1029 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1030 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1031 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1032 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1034 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1035 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1037 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1039 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1040 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1042 return add
->definitions
[0].getTemp();
1045 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1047 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1048 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1050 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1053 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1054 return bld
.copy(Definition(dst
), src
);
1055 else if (dst
.bytes() < src
.bytes())
1056 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1060 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1063 } else if (src
.regClass() == s1
) {
1065 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1067 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1068 } else if (ctx
->options
->chip_class
>= GFX8
) {
1069 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1070 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1071 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1072 sdwa
->operands
[0] = Operand(src
);
1073 sdwa
->definitions
[0] = Definition(tmp
);
1075 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1077 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1078 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1079 bld
.insert(std::move(sdwa
));
1081 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1082 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1083 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1086 if (dst_bits
== 64) {
1087 if (is_signed
&& dst
.regClass() == s2
) {
1088 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1089 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1090 } else if (is_signed
&& dst
.regClass() == v2
) {
1091 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1092 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1094 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1101 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1103 if (!instr
->dest
.dest
.is_ssa
) {
1104 fprintf(stderr
, "nir alu dst not in ssa: ");
1105 nir_print_instr(&instr
->instr
, stderr
);
1106 fprintf(stderr
, "\n");
1109 Builder
bld(ctx
->program
, ctx
->block
);
1110 bld
.is_precise
= instr
->exact
;
1111 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1116 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1117 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1118 for (unsigned i
= 0; i
< num
; ++i
)
1119 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1121 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1122 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1123 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1124 for (unsigned i
= 0; i
< num
; ++i
) {
1125 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1126 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1128 vec
->operands
[i
] = Operand
{elems
[i
]};
1130 vec
->definitions
[0] = Definition(dst
);
1131 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1132 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1134 // TODO: that is a bit suboptimal..
1135 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1136 for (unsigned i
= 0; i
< num
- 1; ++i
)
1137 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1138 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1139 for (unsigned i
= 0; i
< num
; ++i
) {
1140 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1141 if (bit
% 32 == 0) {
1142 elems
[bit
/ 32] = elems
[i
];
1144 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1145 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1146 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1149 if (dst
.size() == 1)
1150 bld
.copy(Definition(dst
), elems
[0]);
1152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1157 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1158 aco_ptr
<Instruction
> mov
;
1159 if (dst
.type() == RegType::sgpr
) {
1160 if (src
.type() == RegType::vgpr
)
1161 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1162 else if (src
.regClass() == s1
)
1163 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1164 else if (src
.regClass() == s2
)
1165 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1167 unreachable("wrong src register class for nir_op_imov");
1169 if (dst
.regClass() == v1
)
1170 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1171 else if (dst
.regClass() == v1b
||
1172 dst
.regClass() == v2b
||
1173 dst
.regClass() == v2
)
1174 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1176 unreachable("wrong src register class for nir_op_imov");
1181 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1182 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1183 assert(src
.regClass() == bld
.lm
);
1184 assert(dst
.regClass() == bld
.lm
);
1185 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1186 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1187 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1188 } else if (dst
.regClass() == v1
) {
1189 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1190 } else if (dst
.regClass() == v2
) {
1191 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1192 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1193 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1194 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1196 } else if (dst
.type() == RegType::sgpr
) {
1197 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1198 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1200 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1201 nir_print_instr(&instr
->instr
, stderr
);
1202 fprintf(stderr
, "\n");
1207 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1208 if (dst
.regClass() == v1
) {
1209 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1210 } else if (dst
.regClass() == s1
) {
1211 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1212 } else if (dst
.size() == 2) {
1213 Temp src0
= bld
.tmp(dst
.type(), 1);
1214 Temp src1
= bld
.tmp(dst
.type(), 1);
1215 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1217 if (dst
.regClass() == s2
) {
1218 Temp carry
= bld
.tmp(s1
);
1219 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1220 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1221 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1223 Temp lower
= bld
.tmp(v1
);
1224 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1225 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == s1
) {
1237 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1238 } else if (dst
.regClass() == v1
) {
1239 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1240 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1242 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1243 nir_print_instr(&instr
->instr
, stderr
);
1244 fprintf(stderr
, "\n");
1248 case nir_op_isign
: {
1249 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1250 if (dst
.regClass() == s1
) {
1251 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1252 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1253 } else if (dst
.regClass() == s2
) {
1254 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1256 if (ctx
->program
->chip_class
>= GFX8
)
1257 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1259 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1260 /* SCC gets zero-extended to 64 bit */
1261 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1262 } else if (dst
.regClass() == v1
) {
1263 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1264 } else if (dst
.regClass() == v2
) {
1265 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1266 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1267 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1268 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1269 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1270 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1272 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1273 nir_print_instr(&instr
->instr
, stderr
);
1274 fprintf(stderr
, "\n");
1279 if (dst
.regClass() == v1
) {
1280 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1281 } else if (dst
.regClass() == s1
) {
1282 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1291 if (dst
.regClass() == v1
) {
1292 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1293 } else if (dst
.regClass() == s1
) {
1294 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1296 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1297 nir_print_instr(&instr
->instr
, stderr
);
1298 fprintf(stderr
, "\n");
1303 if (dst
.regClass() == v1
) {
1304 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1305 } else if (dst
.regClass() == s1
) {
1306 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1308 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1309 nir_print_instr(&instr
->instr
, stderr
);
1310 fprintf(stderr
, "\n");
1315 if (dst
.regClass() == v1
) {
1316 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1317 } else if (dst
.regClass() == s1
) {
1318 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1320 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1321 nir_print_instr(&instr
->instr
, stderr
);
1322 fprintf(stderr
, "\n");
1327 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1328 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1329 } else if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1331 } else if (dst
.regClass() == v2
) {
1332 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1333 } else if (dst
.regClass() == s1
) {
1334 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1335 } else if (dst
.regClass() == s2
) {
1336 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1338 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1339 nir_print_instr(&instr
->instr
, stderr
);
1340 fprintf(stderr
, "\n");
1345 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1346 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1347 } else if (dst
.regClass() == v1
) {
1348 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1349 } else if (dst
.regClass() == v2
) {
1350 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1351 } else if (dst
.regClass() == s1
) {
1352 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1353 } else if (dst
.regClass() == s2
) {
1354 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1356 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1357 nir_print_instr(&instr
->instr
, stderr
);
1358 fprintf(stderr
, "\n");
1363 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1364 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1365 } else if (dst
.regClass() == v1
) {
1366 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1367 } else if (dst
.regClass() == v2
) {
1368 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1369 } else if (dst
.regClass() == s1
) {
1370 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1371 } else if (dst
.regClass() == s2
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1374 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1375 nir_print_instr(&instr
->instr
, stderr
);
1376 fprintf(stderr
, "\n");
1381 if (dst
.regClass() == v1
) {
1382 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1383 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1384 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1385 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1386 } else if (dst
.regClass() == v2
) {
1387 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1388 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1391 } else if (dst
.regClass() == s1
) {
1392 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1401 if (dst
.regClass() == v1
) {
1402 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1403 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1404 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1405 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1406 } else if (dst
.regClass() == v2
) {
1407 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1408 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1409 } else if (dst
.regClass() == s1
) {
1410 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1411 } else if (dst
.regClass() == s2
) {
1412 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1414 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1415 nir_print_instr(&instr
->instr
, stderr
);
1416 fprintf(stderr
, "\n");
1421 if (dst
.regClass() == v1
) {
1422 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1423 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1424 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1425 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1426 } else if (dst
.regClass() == v2
) {
1427 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1428 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1429 } else if (dst
.regClass() == s1
) {
1430 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1431 } else if (dst
.regClass() == s2
) {
1432 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1434 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1435 nir_print_instr(&instr
->instr
, stderr
);
1436 fprintf(stderr
, "\n");
1440 case nir_op_find_lsb
: {
1441 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1442 if (src
.regClass() == s1
) {
1443 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1444 } else if (src
.regClass() == v1
) {
1445 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1446 } else if (src
.regClass() == s2
) {
1447 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1449 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1450 nir_print_instr(&instr
->instr
, stderr
);
1451 fprintf(stderr
, "\n");
1455 case nir_op_ufind_msb
:
1456 case nir_op_ifind_msb
: {
1457 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1458 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1459 aco_opcode op
= src
.regClass() == s2
?
1460 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1461 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1462 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1464 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1465 Operand(src
.size() * 32u - 1u), msb_rev
);
1466 Temp msb
= sub
.def(0).getTemp();
1467 Temp carry
= sub
.def(1).getTemp();
1469 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1470 } else if (src
.regClass() == v1
) {
1471 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1472 Temp msb_rev
= bld
.tmp(v1
);
1473 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1474 Temp msb
= bld
.tmp(v1
);
1475 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1476 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1478 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1479 nir_print_instr(&instr
->instr
, stderr
);
1480 fprintf(stderr
, "\n");
1484 case nir_op_bitfield_reverse
: {
1485 if (dst
.regClass() == s1
) {
1486 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1487 } else if (dst
.regClass() == v1
) {
1488 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1497 if (dst
.regClass() == s1
) {
1498 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1502 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1503 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1504 if (dst
.regClass() == v1
) {
1505 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1509 assert(src0
.size() == 2 && src1
.size() == 2);
1510 Temp src00
= bld
.tmp(src0
.type(), 1);
1511 Temp src01
= bld
.tmp(dst
.type(), 1);
1512 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1513 Temp src10
= bld
.tmp(src1
.type(), 1);
1514 Temp src11
= bld
.tmp(dst
.type(), 1);
1515 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1517 if (dst
.regClass() == s2
) {
1518 Temp carry
= bld
.tmp(s1
);
1519 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1520 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1521 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1522 } else if (dst
.regClass() == v2
) {
1523 Temp dst0
= bld
.tmp(v1
);
1524 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1525 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1526 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1528 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1529 nir_print_instr(&instr
->instr
, stderr
);
1530 fprintf(stderr
, "\n");
1534 case nir_op_uadd_sat
: {
1535 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1536 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1537 if (dst
.regClass() == s1
) {
1538 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1539 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1541 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1542 } else if (dst
.regClass() == v1
) {
1543 if (ctx
->options
->chip_class
>= GFX9
) {
1544 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1545 add
->operands
[0] = Operand(src0
);
1546 add
->operands
[1] = Operand(src1
);
1547 add
->definitions
[0] = Definition(dst
);
1549 ctx
->block
->instructions
.emplace_back(std::move(add
));
1551 if (src1
.regClass() != v1
)
1552 std::swap(src0
, src1
);
1553 assert(src1
.regClass() == v1
);
1554 Temp tmp
= bld
.tmp(v1
);
1555 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1556 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1560 nir_print_instr(&instr
->instr
, stderr
);
1561 fprintf(stderr
, "\n");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1596 nir_print_instr(&instr
->instr
, stderr
);
1597 fprintf(stderr
, "\n");
1602 if (dst
.regClass() == s1
) {
1603 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1607 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1608 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1609 if (dst
.regClass() == v1
) {
1610 bld
.vsub32(Definition(dst
), src0
, src1
);
1614 Temp src00
= bld
.tmp(src0
.type(), 1);
1615 Temp src01
= bld
.tmp(dst
.type(), 1);
1616 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1617 Temp src10
= bld
.tmp(src1
.type(), 1);
1618 Temp src11
= bld
.tmp(dst
.type(), 1);
1619 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1620 if (dst
.regClass() == s2
) {
1621 Temp carry
= bld
.tmp(s1
);
1622 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1623 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1625 } else if (dst
.regClass() == v2
) {
1626 Temp lower
= bld
.tmp(v1
);
1627 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1628 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1629 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_usub_borrow
: {
1638 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1639 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1640 if (dst
.regClass() == s1
) {
1641 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1643 } else if (dst
.regClass() == v1
) {
1644 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1645 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1649 Temp src00
= bld
.tmp(src0
.type(), 1);
1650 Temp src01
= bld
.tmp(dst
.type(), 1);
1651 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1652 Temp src10
= bld
.tmp(src1
.type(), 1);
1653 Temp src11
= bld
.tmp(dst
.type(), 1);
1654 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1655 if (dst
.regClass() == s2
) {
1656 Temp borrow
= bld
.tmp(s1
);
1657 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1658 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1659 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1660 } else if (dst
.regClass() == v2
) {
1661 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1662 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1663 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1664 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1666 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1667 nir_print_instr(&instr
->instr
, stderr
);
1668 fprintf(stderr
, "\n");
1673 if (dst
.regClass() == v1
) {
1674 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1675 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1676 } else if (dst
.regClass() == s1
) {
1677 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1685 case nir_op_umul_high
: {
1686 if (dst
.regClass() == v1
) {
1687 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1688 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1689 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1690 } else if (dst
.regClass() == s1
) {
1691 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1692 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1693 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1695 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1696 nir_print_instr(&instr
->instr
, stderr
);
1697 fprintf(stderr
, "\n");
1701 case nir_op_imul_high
: {
1702 if (dst
.regClass() == v1
) {
1703 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1704 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1705 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1706 } else if (dst
.regClass() == s1
) {
1707 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1708 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1709 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1711 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1712 nir_print_instr(&instr
->instr
, stderr
);
1713 fprintf(stderr
, "\n");
1718 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1719 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1720 if (dst
.regClass() == v2b
) {
1721 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1722 } else if (dst
.regClass() == v1
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1724 } else if (dst
.regClass() == v2
) {
1725 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1727 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1728 nir_print_instr(&instr
->instr
, stderr
);
1729 fprintf(stderr
, "\n");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1736 if (dst
.regClass() == v2b
) {
1737 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1738 } else if (dst
.regClass() == v1
) {
1739 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1740 } else if (dst
.regClass() == v2
) {
1741 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1743 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1744 nir_print_instr(&instr
->instr
, stderr
);
1745 fprintf(stderr
, "\n");
1750 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1751 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1752 if (dst
.regClass() == v2b
) {
1753 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1754 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1756 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1757 } else if (dst
.regClass() == v1
) {
1758 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1759 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1762 } else if (dst
.regClass() == v2
) {
1763 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1764 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1765 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1769 nir_print_instr(&instr
->instr
, stderr
);
1770 fprintf(stderr
, "\n");
1775 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1776 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1777 if (dst
.regClass() == v2b
) {
1778 // TODO: check fp_mode.must_flush_denorms16_64
1779 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1780 } else if (dst
.regClass() == v1
) {
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1782 } else if (dst
.regClass() == v2
) {
1783 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1784 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1785 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1787 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1791 nir_print_instr(&instr
->instr
, stderr
);
1792 fprintf(stderr
, "\n");
1797 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1798 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1799 if (dst
.regClass() == v2b
) {
1800 // TODO: check fp_mode.must_flush_denorms16_64
1801 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1802 } else if (dst
.regClass() == v1
) {
1803 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1804 } else if (dst
.regClass() == v2
) {
1805 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1806 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1807 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1809 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1812 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1813 nir_print_instr(&instr
->instr
, stderr
);
1814 fprintf(stderr
, "\n");
1818 case nir_op_fmax3
: {
1819 if (dst
.regClass() == v2b
) {
1820 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1821 } else if (dst
.regClass() == v1
) {
1822 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1830 case nir_op_fmin3
: {
1831 if (dst
.regClass() == v2b
) {
1832 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1833 } else if (dst
.regClass() == v1
) {
1834 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1836 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1837 nir_print_instr(&instr
->instr
, stderr
);
1838 fprintf(stderr
, "\n");
1842 case nir_op_fmed3
: {
1843 if (dst
.regClass() == v2b
) {
1844 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1845 } else if (dst
.regClass() == v1
) {
1846 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1848 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1849 nir_print_instr(&instr
->instr
, stderr
);
1850 fprintf(stderr
, "\n");
1854 case nir_op_umax3
: {
1855 if (dst
.size() == 1) {
1856 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1858 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1859 nir_print_instr(&instr
->instr
, stderr
);
1860 fprintf(stderr
, "\n");
1864 case nir_op_umin3
: {
1865 if (dst
.size() == 1) {
1866 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1868 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1869 nir_print_instr(&instr
->instr
, stderr
);
1870 fprintf(stderr
, "\n");
1874 case nir_op_umed3
: {
1875 if (dst
.size() == 1) {
1876 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1878 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1879 nir_print_instr(&instr
->instr
, stderr
);
1880 fprintf(stderr
, "\n");
1884 case nir_op_imax3
: {
1885 if (dst
.size() == 1) {
1886 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1894 case nir_op_imin3
: {
1895 if (dst
.size() == 1) {
1896 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1898 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1899 nir_print_instr(&instr
->instr
, stderr
);
1900 fprintf(stderr
, "\n");
1904 case nir_op_imed3
: {
1905 if (dst
.size() == 1) {
1906 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_cube_face_coord
: {
1915 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1916 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1917 emit_extract_vector(ctx
, in
, 1, v1
),
1918 emit_extract_vector(ctx
, in
, 2, v1
) };
1919 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1920 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1921 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1922 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1923 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1924 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1925 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1928 case nir_op_cube_face_index
: {
1929 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1930 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1931 emit_extract_vector(ctx
, in
, 1, v1
),
1932 emit_extract_vector(ctx
, in
, 2, v1
) };
1933 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1936 case nir_op_bcsel
: {
1937 emit_bcsel(ctx
, instr
, dst
);
1941 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1942 if (dst
.regClass() == v2b
) {
1943 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1944 } else if (dst
.regClass() == v1
) {
1945 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1946 } else if (dst
.regClass() == v2
) {
1947 /* Lowered at NIR level for precision reasons. */
1948 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1950 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1951 nir_print_instr(&instr
->instr
, stderr
);
1952 fprintf(stderr
, "\n");
1957 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1958 if (dst
.regClass() == v2b
) {
1959 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1960 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1961 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1962 } else if (dst
.regClass() == v1
) {
1963 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1964 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1965 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1966 } else if (dst
.regClass() == v2
) {
1967 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1968 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1969 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1970 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1971 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1972 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1974 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1975 nir_print_instr(&instr
->instr
, stderr
);
1976 fprintf(stderr
, "\n");
1981 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1982 if (dst
.regClass() == v2b
) {
1983 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1984 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1985 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1986 } else if (dst
.regClass() == v1
) {
1987 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1988 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1989 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1990 } else if (dst
.regClass() == v2
) {
1991 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1992 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1993 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1995 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1996 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1998 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1999 nir_print_instr(&instr
->instr
, stderr
);
2000 fprintf(stderr
, "\n");
2005 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2006 if (dst
.regClass() == v2b
) {
2007 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
2008 } else if (dst
.regClass() == v1
) {
2009 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2010 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
2011 // TODO: confirm that this holds under any circumstances
2012 } else if (dst
.regClass() == v2
) {
2013 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
2014 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
2017 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2018 nir_print_instr(&instr
->instr
, stderr
);
2019 fprintf(stderr
, "\n");
2023 case nir_op_flog2
: {
2024 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2025 if (dst
.regClass() == v2b
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
2027 } else if (dst
.regClass() == v1
) {
2028 emit_log2(ctx
, bld
, Definition(dst
), src
);
2030 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2031 nir_print_instr(&instr
->instr
, stderr
);
2032 fprintf(stderr
, "\n");
2037 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2038 if (dst
.regClass() == v2b
) {
2039 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2040 } else if (dst
.regClass() == v1
) {
2041 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2042 } else if (dst
.regClass() == v2
) {
2043 /* Lowered at NIR level for precision reasons. */
2044 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2046 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2047 nir_print_instr(&instr
->instr
, stderr
);
2048 fprintf(stderr
, "\n");
2052 case nir_op_fexp2
: {
2053 if (dst
.regClass() == v2b
) {
2054 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2055 } else if (dst
.regClass() == v1
) {
2056 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2058 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2059 nir_print_instr(&instr
->instr
, stderr
);
2060 fprintf(stderr
, "\n");
2064 case nir_op_fsqrt
: {
2065 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2066 if (dst
.regClass() == v2b
) {
2067 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2068 } else if (dst
.regClass() == v1
) {
2069 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2070 } else if (dst
.regClass() == v2
) {
2071 /* Lowered at NIR level for precision reasons. */
2072 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2074 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2075 nir_print_instr(&instr
->instr
, stderr
);
2076 fprintf(stderr
, "\n");
2080 case nir_op_ffract
: {
2081 if (dst
.regClass() == v2b
) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2083 } else if (dst
.regClass() == v1
) {
2084 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2085 } else if (dst
.regClass() == v2
) {
2086 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2088 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2089 nir_print_instr(&instr
->instr
, stderr
);
2090 fprintf(stderr
, "\n");
2094 case nir_op_ffloor
: {
2095 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2096 if (dst
.regClass() == v2b
) {
2097 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2098 } else if (dst
.regClass() == v1
) {
2099 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2100 } else if (dst
.regClass() == v2
) {
2101 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2103 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2104 nir_print_instr(&instr
->instr
, stderr
);
2105 fprintf(stderr
, "\n");
2109 case nir_op_fceil
: {
2110 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2111 if (dst
.regClass() == v2b
) {
2112 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2113 } else if (dst
.regClass() == v1
) {
2114 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2115 } else if (dst
.regClass() == v2
) {
2116 if (ctx
->options
->chip_class
>= GFX7
) {
2117 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2119 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2120 /* trunc = trunc(src0)
2121 * if (src0 > 0.0 && src0 != trunc)
2124 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2125 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2126 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2127 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2128 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2129 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2130 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2133 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2134 nir_print_instr(&instr
->instr
, stderr
);
2135 fprintf(stderr
, "\n");
2139 case nir_op_ftrunc
: {
2140 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2141 if (dst
.regClass() == v2b
) {
2142 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2143 } else if (dst
.regClass() == v1
) {
2144 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2145 } else if (dst
.regClass() == v2
) {
2146 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_fround_even
: {
2155 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (dst
.regClass() == v2b
) {
2157 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2158 } else if (dst
.regClass() == v1
) {
2159 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2160 } else if (dst
.regClass() == v2
) {
2161 if (ctx
->options
->chip_class
>= GFX7
) {
2162 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2164 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2165 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2166 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2168 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2169 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2170 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2171 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2172 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2173 tmp
= sub
->definitions
[0].getTemp();
2175 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2176 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2177 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2178 Temp cond
= vop3
->definitions
[0].getTemp();
2180 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2181 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2182 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2183 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2185 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2188 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2189 nir_print_instr(&instr
->instr
, stderr
);
2190 fprintf(stderr
, "\n");
2196 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2197 aco_ptr
<Instruction
> norm
;
2198 if (dst
.regClass() == v2b
) {
2199 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2200 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2201 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2202 bld
.vop1(opcode
, Definition(dst
), tmp
);
2203 } else if (dst
.regClass() == v1
) {
2204 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2205 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2207 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2208 if (ctx
->options
->chip_class
< GFX9
)
2209 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2211 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2212 bld
.vop1(opcode
, Definition(dst
), tmp
);
2214 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2215 nir_print_instr(&instr
->instr
, stderr
);
2216 fprintf(stderr
, "\n");
2220 case nir_op_ldexp
: {
2221 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2222 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2223 if (dst
.regClass() == v2b
) {
2224 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2225 } else if (dst
.regClass() == v1
) {
2226 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2227 } else if (dst
.regClass() == v2
) {
2228 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2230 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2231 nir_print_instr(&instr
->instr
, stderr
);
2232 fprintf(stderr
, "\n");
2236 case nir_op_frexp_sig
: {
2237 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2238 if (dst
.regClass() == v2b
) {
2239 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2240 } else if (dst
.regClass() == v1
) {
2241 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2242 } else if (dst
.regClass() == v2
) {
2243 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2246 nir_print_instr(&instr
->instr
, stderr
);
2247 fprintf(stderr
, "\n");
2251 case nir_op_frexp_exp
: {
2252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2253 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2254 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2255 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2256 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2257 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2258 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2259 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2260 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2262 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2263 nir_print_instr(&instr
->instr
, stderr
);
2264 fprintf(stderr
, "\n");
2268 case nir_op_fsign
: {
2269 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2270 if (dst
.regClass() == v2b
) {
2271 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2272 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2273 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2274 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2275 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2276 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2277 } else if (dst
.regClass() == v1
) {
2278 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2279 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2280 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2281 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2282 } else if (dst
.regClass() == v2
) {
2283 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2284 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2285 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2287 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2288 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2289 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2291 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2293 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2294 nir_print_instr(&instr
->instr
, stderr
);
2295 fprintf(stderr
, "\n");
2300 case nir_op_f2f16_rtne
: {
2301 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2302 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2303 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2304 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2305 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2306 * keep value numbering and the scheduler simpler.
2308 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2310 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2313 case nir_op_f2f16_rtz
: {
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2316 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2317 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2320 case nir_op_f2f32
: {
2321 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2322 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2323 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2324 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2326 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2327 nir_print_instr(&instr
->instr
, stderr
);
2328 fprintf(stderr
, "\n");
2332 case nir_op_f2f64
: {
2333 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2334 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2335 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2336 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2339 case nir_op_i2f16
: {
2340 assert(dst
.regClass() == v2b
);
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2343 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2344 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2345 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2346 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2349 case nir_op_i2f32
: {
2350 assert(dst
.size() == 1);
2351 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2352 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2353 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2354 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2357 case nir_op_i2f64
: {
2358 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2359 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2360 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2361 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2362 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2363 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2364 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2365 RegClass rc
= RegClass(src
.type(), 1);
2366 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2367 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2368 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2369 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2370 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2371 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2374 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2375 nir_print_instr(&instr
->instr
, stderr
);
2376 fprintf(stderr
, "\n");
2380 case nir_op_u2f16
: {
2381 assert(dst
.regClass() == v2b
);
2382 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2383 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2384 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2385 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2386 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2387 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2390 case nir_op_u2f32
: {
2391 assert(dst
.size() == 1);
2392 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2393 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2394 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2396 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2397 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2398 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2402 case nir_op_u2f64
: {
2403 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2404 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2405 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2406 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2407 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2408 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2409 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2410 RegClass rc
= RegClass(src
.type(), 1);
2411 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2412 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2413 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2414 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2415 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2416 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2418 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2419 nir_print_instr(&instr
->instr
, stderr
);
2420 fprintf(stderr
, "\n");
2425 case nir_op_f2i16
: {
2426 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2427 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2428 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2429 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2431 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2435 case nir_op_f2u16
: {
2436 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2437 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2438 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2439 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2441 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2444 case nir_op_f2i32
: {
2445 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2446 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2447 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2448 if (dst
.type() == RegType::vgpr
) {
2449 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2451 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2452 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2454 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2456 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2457 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2459 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2460 nir_print_instr(&instr
->instr
, stderr
);
2461 fprintf(stderr
, "\n");
2465 case nir_op_f2u32
: {
2466 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2467 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2468 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2469 if (dst
.type() == RegType::vgpr
) {
2470 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2472 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2473 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2475 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2476 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2477 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2478 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2480 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2481 nir_print_instr(&instr
->instr
, stderr
);
2482 fprintf(stderr
, "\n");
2486 case nir_op_f2i64
: {
2487 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2488 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2489 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2491 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2492 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2493 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2494 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2495 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2496 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2497 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2498 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2499 Temp new_exponent
= bld
.tmp(v1
);
2500 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2501 if (ctx
->program
->chip_class
>= GFX8
)
2502 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2504 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2505 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2506 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2507 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2508 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2509 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2510 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2511 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2512 Temp new_lower
= bld
.tmp(v1
);
2513 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2514 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2515 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2517 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2518 if (src
.type() == RegType::vgpr
)
2519 src
= bld
.as_uniform(src
);
2520 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2521 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2522 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2523 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2524 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2525 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2526 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2527 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2528 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2529 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2530 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2531 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2532 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2533 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2534 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2535 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2536 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2537 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2538 Temp borrow
= bld
.tmp(s1
);
2539 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2540 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2543 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2544 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2545 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2546 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2547 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2548 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2549 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2550 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2551 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2552 if (dst
.type() == RegType::sgpr
) {
2553 lower
= bld
.as_uniform(lower
);
2554 upper
= bld
.as_uniform(upper
);
2556 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2560 nir_print_instr(&instr
->instr
, stderr
);
2561 fprintf(stderr
, "\n");
2565 case nir_op_f2u64
: {
2566 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2567 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2568 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2570 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2571 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2572 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2573 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2574 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2575 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2576 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2577 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2578 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2579 Temp new_exponent
= bld
.tmp(v1
);
2580 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2581 if (ctx
->program
->chip_class
>= GFX8
)
2582 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2584 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2585 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2586 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2587 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2588 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2589 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2590 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2591 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2593 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2594 if (src
.type() == RegType::vgpr
)
2595 src
= bld
.as_uniform(src
);
2596 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2597 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2598 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2599 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2600 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2601 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2602 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2603 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2604 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2605 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2606 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2607 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2608 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2609 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2610 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2611 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2612 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2613 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2615 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2616 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2617 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2618 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2619 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2620 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2621 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2622 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2623 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2624 if (dst
.type() == RegType::sgpr
) {
2625 lower
= bld
.as_uniform(lower
);
2626 upper
= bld
.as_uniform(upper
);
2628 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2632 nir_print_instr(&instr
->instr
, stderr
);
2633 fprintf(stderr
, "\n");
2637 case nir_op_b2f16
: {
2638 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2639 assert(src
.regClass() == bld
.lm
);
2641 if (dst
.regClass() == s1
) {
2642 src
= bool_to_scalar_condition(ctx
, src
);
2643 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2644 } else if (dst
.regClass() == v2b
) {
2645 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2646 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2648 unreachable("Wrong destination register class for nir_op_b2f16.");
2652 case nir_op_b2f32
: {
2653 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2654 assert(src
.regClass() == bld
.lm
);
2656 if (dst
.regClass() == s1
) {
2657 src
= bool_to_scalar_condition(ctx
, src
);
2658 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2659 } else if (dst
.regClass() == v1
) {
2660 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2662 unreachable("Wrong destination register class for nir_op_b2f32.");
2666 case nir_op_b2f64
: {
2667 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2668 assert(src
.regClass() == bld
.lm
);
2670 if (dst
.regClass() == s2
) {
2671 src
= bool_to_scalar_condition(ctx
, src
);
2672 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2673 } else if (dst
.regClass() == v2
) {
2674 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2675 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2676 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2678 unreachable("Wrong destination register class for nir_op_b2f64.");
2685 case nir_op_i2i64
: {
2686 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2687 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2693 case nir_op_u2u64
: {
2694 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2695 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2702 case nir_op_b2i64
: {
2703 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2704 assert(src
.regClass() == bld
.lm
);
2706 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2707 if (tmp
.regClass() == s1
) {
2708 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2709 bool_to_scalar_condition(ctx
, src
, tmp
);
2710 } else if (tmp
.type() == RegType::vgpr
) {
2711 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2713 unreachable("Invalid register class for b2i32");
2717 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2722 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2723 assert(dst
.regClass() == bld
.lm
);
2725 if (src
.type() == RegType::vgpr
) {
2726 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2727 assert(dst
.regClass() == bld
.lm
);
2728 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2729 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2731 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2733 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2734 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2736 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2737 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2739 bool_to_vector_condition(ctx
, tmp
, dst
);
2743 case nir_op_pack_64_2x32_split
: {
2744 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2745 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2747 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2750 case nir_op_unpack_64_2x32_split_x
:
2751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2753 case nir_op_unpack_64_2x32_split_y
:
2754 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2756 case nir_op_unpack_32_2x16_split_x
:
2757 if (dst
.type() == RegType::vgpr
) {
2758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2760 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2763 case nir_op_unpack_32_2x16_split_y
:
2764 if (dst
.type() == RegType::vgpr
) {
2765 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2767 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2770 case nir_op_pack_32_2x16_split
: {
2771 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2772 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2773 if (dst
.regClass() == v1
) {
2774 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2775 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2778 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2779 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2780 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2784 case nir_op_pack_half_2x16
: {
2785 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2787 if (dst
.regClass() == v1
) {
2788 Temp src0
= bld
.tmp(v1
);
2789 Temp src1
= bld
.tmp(v1
);
2790 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2791 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2792 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2794 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2795 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2796 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2798 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2799 nir_print_instr(&instr
->instr
, stderr
);
2800 fprintf(stderr
, "\n");
2804 case nir_op_unpack_half_2x16_split_x
: {
2805 if (dst
.regClass() == v1
) {
2806 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2808 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2809 nir_print_instr(&instr
->instr
, stderr
);
2810 fprintf(stderr
, "\n");
2814 case nir_op_unpack_half_2x16_split_y
: {
2815 if (dst
.regClass() == v1
) {
2816 /* TODO: use SDWA here */
2817 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2818 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2820 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2821 nir_print_instr(&instr
->instr
, stderr
);
2822 fprintf(stderr
, "\n");
2826 case nir_op_fquantize2f16
: {
2827 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2828 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2831 if (ctx
->program
->chip_class
>= GFX8
) {
2832 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2833 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2834 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2836 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2837 * so compare the result and flush to 0 if it's smaller.
2839 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2840 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2841 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2842 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2843 cmp_res
= vop3
->definitions
[0].getTemp();
2846 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2847 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2848 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2850 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2855 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2856 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2858 if (dst
.regClass() == s1
) {
2859 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2860 } else if (dst
.regClass() == v1
) {
2861 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2863 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2864 nir_print_instr(&instr
->instr
, stderr
);
2865 fprintf(stderr
, "\n");
2869 case nir_op_bitfield_select
: {
2870 /* (mask & insert) | (~mask & base) */
2871 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2872 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2873 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2875 /* dst = (insert & bitmask) | (base & ~bitmask) */
2876 if (dst
.regClass() == s1
) {
2877 aco_ptr
<Instruction
> sop2
;
2878 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2879 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2881 if (const_insert
&& const_bitmask
) {
2882 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2884 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2885 lhs
= Operand(insert
);
2889 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2890 if (const_base
&& const_bitmask
) {
2891 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2893 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2894 rhs
= Operand(base
);
2897 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2899 } else if (dst
.regClass() == v1
) {
2900 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2901 base
= as_vgpr(ctx
, base
);
2902 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2903 insert
= as_vgpr(ctx
, insert
);
2905 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2909 nir_print_instr(&instr
->instr
, stderr
);
2910 fprintf(stderr
, "\n");
2916 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2917 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2918 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2920 if (dst
.type() == RegType::sgpr
) {
2922 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2923 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2924 if (const_offset
&& const_bits
) {
2925 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2926 extract
= Operand(const_extract
);
2930 width
= Operand(const_bits
->u32
<< 16);
2932 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2934 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2938 if (dst
.regClass() == s1
) {
2939 if (instr
->op
== nir_op_ubfe
)
2940 opcode
= aco_opcode::s_bfe_u32
;
2942 opcode
= aco_opcode::s_bfe_i32
;
2943 } else if (dst
.regClass() == s2
) {
2944 if (instr
->op
== nir_op_ubfe
)
2945 opcode
= aco_opcode::s_bfe_u64
;
2947 opcode
= aco_opcode::s_bfe_i64
;
2949 unreachable("Unsupported BFE bit size");
2952 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2956 if (dst
.regClass() == v1
) {
2957 if (instr
->op
== nir_op_ubfe
)
2958 opcode
= aco_opcode::v_bfe_u32
;
2960 opcode
= aco_opcode::v_bfe_i32
;
2962 unreachable("Unsupported BFE bit size");
2965 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2969 case nir_op_bit_count
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 if (src
.regClass() == s1
) {
2972 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2973 } else if (src
.regClass() == v1
) {
2974 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2975 } else if (src
.regClass() == v2
) {
2976 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2977 emit_extract_vector(ctx
, src
, 1, v1
),
2978 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2979 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2980 } else if (src
.regClass() == s2
) {
2981 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2983 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2984 nir_print_instr(&instr
->instr
, stderr
);
2985 fprintf(stderr
, "\n");
2990 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2994 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2998 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
3002 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3006 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3010 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3014 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3015 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3017 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3018 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3022 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3023 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3025 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3026 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3030 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3034 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3039 case nir_op_fddx_fine
:
3040 case nir_op_fddy_fine
:
3041 case nir_op_fddx_coarse
:
3042 case nir_op_fddy_coarse
: {
3043 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3044 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3045 if (instr
->op
== nir_op_fddx_fine
) {
3046 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3047 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3048 } else if (instr
->op
== nir_op_fddy_fine
) {
3049 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3050 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3052 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3053 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3054 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3056 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3060 if (ctx
->program
->chip_class
>= GFX8
) {
3061 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3062 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3064 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3065 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3066 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3068 emit_wqm(ctx
, tmp
, dst
, true);
3072 fprintf(stderr
, "Unknown NIR ALU instr: ");
3073 nir_print_instr(&instr
->instr
, stderr
);
3074 fprintf(stderr
, "\n");
3078 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3080 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3082 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3083 // which get truncated the lsb if double and msb if int
3084 // for now, we only use s_mov_b64 with 64bit inline constants
3085 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3086 assert(dst
.type() == RegType::sgpr
);
3088 Builder
bld(ctx
->program
, ctx
->block
);
3090 if (instr
->def
.bit_size
== 1) {
3091 assert(dst
.regClass() == bld
.lm
);
3092 int val
= instr
->value
[0].b
? -1 : 0;
3093 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3094 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3095 } else if (instr
->def
.bit_size
== 8) {
3096 /* ensure that the value is correctly represented in the low byte of the register */
3097 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3098 } else if (instr
->def
.bit_size
== 16) {
3099 /* ensure that the value is correctly represented in the low half of the register */
3100 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3101 } else if (dst
.size() == 1) {
3102 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3104 assert(dst
.size() != 1);
3105 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3106 if (instr
->def
.bit_size
== 64)
3107 for (unsigned i
= 0; i
< dst
.size(); i
++)
3108 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3110 for (unsigned i
= 0; i
< dst
.size(); i
++)
3111 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3113 vec
->definitions
[0] = Definition(dst
);
3114 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3118 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3120 uint32_t new_mask
= 0;
3121 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3122 if (mask
& (1u << i
))
3123 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3127 struct LoadEmitInfo
{
3130 unsigned num_components
;
3131 unsigned component_size
;
3132 Temp resource
= Temp(0, s1
);
3133 unsigned component_stride
= 0;
3134 unsigned const_offset
= 0;
3135 unsigned align_mul
= 0;
3136 unsigned align_offset
= 0;
3139 unsigned swizzle_component_size
= 0;
3140 memory_sync_info sync
;
3141 Temp soffset
= Temp(0, s1
);
3144 using LoadCallback
= Temp(*)(
3145 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3146 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3148 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3149 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3151 unsigned load_size
= info
->num_components
* info
->component_size
;
3152 unsigned component_size
= info
->component_size
;
3154 unsigned num_vals
= 0;
3155 Temp vals
[info
->dst
.bytes()];
3157 unsigned const_offset
= info
->const_offset
;
3159 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3160 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3162 unsigned bytes_read
= 0;
3163 while (bytes_read
< load_size
) {
3164 unsigned bytes_needed
= load_size
- bytes_read
;
3166 /* add buffer for unaligned loads */
3167 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3170 if ((bytes_needed
> 2 ||
3171 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3172 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3173 if (info
->component_stride
) {
3174 assert(supports_8bit_16bit_loads
&& "unimplemented");
3178 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3179 bytes_needed
= align(bytes_needed
, 4);
3186 if (info
->swizzle_component_size
)
3187 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3188 if (info
->component_stride
)
3189 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3191 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3193 /* reduce constant offset */
3194 Operand offset
= info
->offset
;
3195 unsigned reduced_const_offset
= const_offset
;
3196 bool remove_const_offset_completely
= need_to_align_offset
;
3197 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3198 unsigned to_add
= const_offset
;
3199 if (remove_const_offset_completely
) {
3200 reduced_const_offset
= 0;
3202 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3203 reduced_const_offset
%= max_const_offset_plus_one
;
3205 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3206 if (offset
.isConstant()) {
3207 offset
= Operand(offset
.constantValue() + to_add
);
3208 } else if (offset_tmp
.regClass() == s1
) {
3209 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3210 offset_tmp
, Operand(to_add
));
3211 } else if (offset_tmp
.regClass() == v1
) {
3212 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3214 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3215 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3218 if (offset_tmp
.regClass() == s2
) {
3219 Temp carry
= bld
.tmp(s1
);
3220 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3221 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3222 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3224 Temp new_lo
= bld
.tmp(v1
);
3225 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3226 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3227 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3232 /* align offset down if needed */
3233 Operand aligned_offset
= offset
;
3234 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3235 if (need_to_align_offset
) {
3237 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3238 if (offset
.isConstant()) {
3239 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3240 } else if (offset_tmp
.regClass() == s1
) {
3241 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3242 } else if (offset_tmp
.regClass() == s2
) {
3243 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3244 } else if (offset_tmp
.regClass() == v1
) {
3245 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3246 } else if (offset_tmp
.regClass() == v2
) {
3247 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3248 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3249 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3250 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3253 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3254 bld
.copy(bld
.def(s1
), aligned_offset
);
3256 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3257 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3259 /* the callback wrote directly to dst */
3260 if (val
== info
->dst
) {
3261 assert(num_vals
== 0);
3262 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3266 /* shift result right if needed */
3267 if (info
->component_size
< 4 && byte_align_loads
) {
3268 Operand
align((uint32_t)byte_align
);
3269 if (byte_align
== -1) {
3270 if (offset
.isConstant())
3271 align
= Operand(offset
.constantValue() % 4u);
3272 else if (offset
.size() == 2)
3273 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3278 assert(val
.bytes() >= load_size
&& "unimplemented");
3279 if (val
.type() == RegType::sgpr
)
3280 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3282 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3286 /* add result to list and advance */
3287 if (info
->component_stride
) {
3288 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3289 const_offset
+= info
->component_stride
;
3290 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3292 const_offset
+= val
.bytes();
3293 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3295 bytes_read
+= val
.bytes();
3296 vals
[num_vals
++] = val
;
3299 /* create array of components */
3300 unsigned components_split
= 0;
3301 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3302 bool has_vgprs
= false;
3303 for (unsigned i
= 0; i
< num_vals
;) {
3305 unsigned num_tmps
= 0;
3306 unsigned tmp_size
= 0;
3307 RegType reg_type
= RegType::sgpr
;
3308 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3309 if (vals
[i
].type() == RegType::vgpr
)
3310 reg_type
= RegType::vgpr
;
3311 tmp_size
+= vals
[i
].bytes();
3312 tmp
[num_tmps
++] = vals
[i
++];
3315 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3316 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3317 for (unsigned i
= 0; i
< num_tmps
; i
++)
3318 vec
->operands
[i
] = Operand(tmp
[i
]);
3319 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3320 vec
->definitions
[0] = Definition(tmp
[0]);
3321 bld
.insert(std::move(vec
));
3324 if (tmp
[0].bytes() % component_size
) {
3326 assert(i
== num_vals
);
3327 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3328 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3331 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3333 unsigned start
= components_split
;
3335 if (tmp_size
== elem_rc
.bytes()) {
3336 allocated_vec
[components_split
++] = tmp
[0];
3338 assert(tmp_size
% elem_rc
.bytes() == 0);
3339 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3340 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3341 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3342 Temp component
= bld
.tmp(elem_rc
);
3343 allocated_vec
[components_split
++] = component
;
3344 split
->definitions
[i
] = Definition(component
);
3346 split
->operands
[0] = Operand(tmp
[0]);
3347 bld
.insert(std::move(split
));
3350 /* try to p_as_uniform early so we can create more optimizable code and
3351 * also update allocated_vec */
3352 for (unsigned j
= start
; j
< components_split
; j
++) {
3353 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3354 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3355 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3359 /* concatenate components and p_as_uniform() result if needed */
3360 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3361 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3363 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3365 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3366 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3367 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3368 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3370 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3371 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3372 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3373 vec
->definitions
[0] = Definition(tmp
);
3374 bld
.insert(std::move(vec
));
3375 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3377 vec
->definitions
[0] = Definition(info
->dst
);
3378 bld
.insert(std::move(vec
));
3382 Operand
load_lds_size_m0(Builder
& bld
)
3384 /* TODO: m0 does not need to be initialized on GFX9+ */
3385 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3388 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3389 Temp offset
, unsigned bytes_needed
,
3390 unsigned align
, unsigned const_offset
,
3393 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3395 Operand m
= load_lds_size_m0(bld
);
3397 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3398 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3403 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3404 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3406 op
= aco_opcode::ds_read_b128
;
3407 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3410 op
= aco_opcode::ds_read2_b64
;
3411 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3413 op
= aco_opcode::ds_read_b96
;
3414 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3416 op
= aco_opcode::ds_read_b64
;
3417 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3420 op
= aco_opcode::ds_read2_b32
;
3421 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3423 op
= aco_opcode::ds_read_b32
;
3424 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3426 op
= aco_opcode::ds_read_u16
;
3429 op
= aco_opcode::ds_read_u8
;
3432 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3433 if (const_offset
>= max_offset_plus_one
) {
3434 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3435 const_offset
%= max_offset_plus_one
;
3439 const_offset
/= (size
/ 2u);
3441 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3442 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3445 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3447 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3448 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3451 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3456 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3458 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3459 Temp offset
, unsigned bytes_needed
,
3460 unsigned align
, unsigned const_offset
,
3465 if (bytes_needed
<= 4) {
3467 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3468 } else if (bytes_needed
<= 8) {
3470 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3471 } else if (bytes_needed
<= 16) {
3473 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3474 } else if (bytes_needed
<= 32) {
3476 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3479 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3481 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3482 if (info
->resource
.id()) {
3483 load
->operands
[0] = Operand(info
->resource
);
3484 load
->operands
[1] = Operand(offset
);
3486 load
->operands
[0] = Operand(offset
);
3487 load
->operands
[1] = Operand(0u);
3489 RegClass
rc(RegType::sgpr
, size
);
3490 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3491 load
->definitions
[0] = Definition(val
);
3492 load
->glc
= info
->glc
;
3493 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3494 load
->sync
= info
->sync
;
3495 bld
.insert(std::move(load
));
3499 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3501 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3502 Temp offset
, unsigned bytes_needed
,
3503 unsigned align_
, unsigned const_offset
,
3506 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3507 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3509 if (info
->soffset
.id()) {
3510 if (soffset
.isTemp())
3511 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3512 soffset
= Operand(info
->soffset
);
3515 unsigned bytes_size
= 0;
3517 if (bytes_needed
== 1 || align_
% 2) {
3519 op
= aco_opcode::buffer_load_ubyte
;
3520 } else if (bytes_needed
== 2 || align_
% 4) {
3522 op
= aco_opcode::buffer_load_ushort
;
3523 } else if (bytes_needed
<= 4) {
3525 op
= aco_opcode::buffer_load_dword
;
3526 } else if (bytes_needed
<= 8) {
3528 op
= aco_opcode::buffer_load_dwordx2
;
3529 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3531 op
= aco_opcode::buffer_load_dwordx3
;
3534 op
= aco_opcode::buffer_load_dwordx4
;
3536 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3537 mubuf
->operands
[0] = Operand(info
->resource
);
3538 mubuf
->operands
[1] = vaddr
;
3539 mubuf
->operands
[2] = soffset
;
3540 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3541 mubuf
->glc
= info
->glc
;
3542 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3543 mubuf
->sync
= info
->sync
;
3544 mubuf
->offset
= const_offset
;
3545 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3546 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3547 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3548 mubuf
->definitions
[0] = Definition(val
);
3549 bld
.insert(std::move(mubuf
));
3554 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3555 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3557 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3559 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3560 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3562 if (addr
.type() == RegType::vgpr
)
3563 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3564 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3567 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3568 Temp offset
, unsigned bytes_needed
,
3569 unsigned align_
, unsigned const_offset
,
3572 unsigned bytes_size
= 0;
3573 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3574 bool global
= bld
.program
->chip_class
>= GFX9
;
3576 if (bytes_needed
== 1) {
3578 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3579 } else if (bytes_needed
== 2) {
3581 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3582 } else if (bytes_needed
<= 4) {
3584 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3585 } else if (bytes_needed
<= 8) {
3587 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3588 } else if (bytes_needed
<= 12 && !mubuf
) {
3590 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3593 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3595 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3596 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3598 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3599 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3600 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3601 mubuf
->operands
[2] = Operand(0u);
3602 mubuf
->glc
= info
->glc
;
3605 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3606 mubuf
->disable_wqm
= false;
3607 mubuf
->sync
= info
->sync
;
3608 mubuf
->definitions
[0] = Definition(val
);
3609 bld
.insert(std::move(mubuf
));
3611 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3613 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3614 flat
->operands
[0] = Operand(offset
);
3615 flat
->operands
[1] = Operand(s1
);
3616 flat
->glc
= info
->glc
;
3617 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3618 flat
->sync
= info
->sync
;
3620 flat
->definitions
[0] = Definition(val
);
3621 bld
.insert(std::move(flat
));
3627 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3629 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3630 Temp address
, unsigned base_offset
, unsigned align
)
3632 assert(util_is_power_of_two_nonzero(align
));
3634 Builder
bld(ctx
->program
, ctx
->block
);
3636 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3637 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3638 info
.align_mul
= align
;
3639 info
.align_offset
= 0;
3640 info
.sync
= memory_sync_info(storage_shared
);
3641 info
.const_offset
= base_offset
;
3642 emit_lds_load(ctx
, bld
, &info
);
3647 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3652 Builder
bld(ctx
->program
, ctx
->block
);
3654 ASSERTED
bool is_subdword
= false;
3655 for (unsigned i
= 0; i
< count
; i
++)
3656 is_subdword
|= offsets
[i
] % 4;
3657 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3658 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3660 /* count == 1 fast path */
3662 if (dst_type
== RegType::sgpr
)
3663 dst
[0] = bld
.as_uniform(src
);
3665 dst
[0] = as_vgpr(ctx
, src
);
3669 for (unsigned i
= 0; i
< count
- 1; i
++)
3670 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3671 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3673 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3674 src
= as_vgpr(ctx
, src
);
3676 /* use allocated_vec if possible */
3677 auto it
= ctx
->allocated_vec
.find(src
.id());
3678 if (it
!= ctx
->allocated_vec
.end()) {
3679 if (!it
->second
[0].id())
3681 unsigned elem_size
= it
->second
[0].bytes();
3682 assert(src
.bytes() % elem_size
== 0);
3684 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3685 if (!it
->second
[i
].id())
3689 for (unsigned i
= 0; i
< count
; i
++) {
3690 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3694 for (unsigned i
= 0; i
< count
; i
++) {
3695 unsigned start_idx
= offsets
[i
] / elem_size
;
3696 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3697 if (op_count
== 1) {
3698 if (dst_type
== RegType::sgpr
)
3699 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3701 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3705 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3706 for (unsigned j
= 0; j
< op_count
; j
++) {
3707 Temp tmp
= it
->second
[start_idx
+ j
];
3708 if (dst_type
== RegType::sgpr
)
3709 tmp
= bld
.as_uniform(tmp
);
3710 vec
->operands
[j
] = Operand(tmp
);
3712 vec
->definitions
[0] = Definition(dst
[i
]);
3713 bld
.insert(std::move(vec
));
3721 if (dst_type
== RegType::sgpr
)
3722 src
= bld
.as_uniform(src
);
3725 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3726 split
->operands
[0] = Operand(src
);
3727 for (unsigned i
= 0; i
< count
; i
++)
3728 split
->definitions
[i
] = Definition(dst
[i
]);
3729 bld
.insert(std::move(split
));
3732 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3733 int *start
, int *count
)
3735 unsigned start_elem
= ffs(todo_mask
) - 1;
3736 bool skip
= !(mask
& (1 << start_elem
));
3738 mask
= ~mask
& todo_mask
;
3742 u_bit_scan_consecutive_range(&mask
, start
, count
);
3747 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3749 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3752 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3753 Temp address
, unsigned base_offset
, unsigned align
)
3755 assert(util_is_power_of_two_nonzero(align
));
3756 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3758 Builder
bld(ctx
->program
, ctx
->block
);
3759 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3760 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3762 unsigned write_count
= 0;
3763 Temp write_datas
[32];
3764 unsigned offsets
[32];
3765 aco_opcode opcodes
[32];
3767 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3769 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3772 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3773 offsets
[write_count
] = offset
;
3774 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3776 advance_write_mask(&todo
, offset
, bytes
);
3780 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3781 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3782 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3783 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3785 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3786 aco_opcode op
= aco_opcode::num_opcodes
;
3787 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3788 op
= aco_opcode::ds_write_b128
;
3790 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3791 op
= aco_opcode::ds_write_b96
;
3793 } else if (bytes
>= 8 && aligned8
) {
3794 op
= aco_opcode::ds_write_b64
;
3796 } else if (bytes
>= 4 && aligned4
) {
3797 op
= aco_opcode::ds_write_b32
;
3799 } else if (bytes
>= 2 && aligned2
) {
3800 op
= aco_opcode::ds_write_b16
;
3802 } else if (bytes
>= 1) {
3803 op
= aco_opcode::ds_write_b8
;
3809 offsets
[write_count
] = offset
;
3810 opcodes
[write_count
] = op
;
3812 advance_write_mask(&todo
, offset
, bytes
);
3815 Operand m
= load_lds_size_m0(bld
);
3817 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3819 for (unsigned i
= 0; i
< write_count
; i
++) {
3820 aco_opcode op
= opcodes
[i
];
3821 if (op
== aco_opcode::num_opcodes
)
3824 Temp data
= write_datas
[i
];
3826 unsigned second
= write_count
;
3827 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3828 for (second
= i
+ 1; second
< write_count
; second
++) {
3829 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3830 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3831 opcodes
[second
] = aco_opcode::num_opcodes
;
3837 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3838 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3840 unsigned inline_offset
= base_offset
+ offsets
[i
];
3841 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3842 Temp address_offset
= address
;
3843 if (inline_offset
> max_offset
) {
3844 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3845 inline_offset
= offsets
[i
];
3847 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3851 Temp second_data
= write_datas
[second
];
3852 inline_offset
/= data
.bytes();
3853 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3855 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3857 static_cast<DS_instruction
*>(instr
)->sync
=
3858 memory_sync_info(storage_shared
);
3862 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3864 unsigned align
= 16;
3866 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3872 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3877 return aco_opcode::buffer_store_byte
;
3880 return aco_opcode::buffer_store_short
;
3882 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3884 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3887 return aco_opcode::buffer_store_dwordx3
;
3889 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3891 unreachable("Unexpected store size");
3892 return aco_opcode::num_opcodes
;
3895 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3896 Temp data
, unsigned writemask
, int swizzle_element_size
,
3897 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3899 unsigned write_count_with_skips
= 0;
3902 /* determine how to split the data */
3903 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3906 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3907 offsets
[write_count_with_skips
] = offset
;
3908 if (skips
[write_count_with_skips
]) {
3909 advance_write_mask(&todo
, offset
, bytes
);
3910 write_count_with_skips
++;
3914 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3915 * larger than swizzle_element_size */
3916 bytes
= MIN2(bytes
, swizzle_element_size
);
3918 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3920 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3921 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3924 /* dword or larger stores have to be dword-aligned */
3925 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3926 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3927 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3929 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3931 advance_write_mask(&todo
, offset
, bytes
);
3932 write_count_with_skips
++;
3935 /* actually split data */
3936 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3939 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3942 write_datas
[*write_count
] = write_datas
[i
];
3943 offsets
[*write_count
] = offsets
[i
];
3948 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3949 unsigned split_cnt
= 0u, Temp dst
= Temp())
3951 Builder
bld(ctx
->program
, ctx
->block
);
3952 unsigned dword_size
= elem_size_bytes
/ 4;
3955 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3957 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3958 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3959 instr
->definitions
[0] = Definition(dst
);
3961 for (unsigned i
= 0; i
< cnt
; ++i
) {
3963 assert(arr
[i
].size() == dword_size
);
3964 allocated_vec
[i
] = arr
[i
];
3965 instr
->operands
[i
] = Operand(arr
[i
]);
3967 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3968 allocated_vec
[i
] = zero
;
3969 instr
->operands
[i
] = Operand(zero
);
3973 bld
.insert(std::move(instr
));
3976 emit_split_vector(ctx
, dst
, split_cnt
);
3978 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3983 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3985 if (const_offset
>= 4096) {
3986 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3987 const_offset
%= 4096u;
3990 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3991 else if (unlikely(voffset
.regClass() == s1
))
3992 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3993 else if (likely(voffset
.regClass() == v1
))
3994 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3996 unreachable("Unsupported register class of voffset");
3999 return const_offset
;
4002 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
4003 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
4004 bool slc
= false, bool swizzled
= false)
4007 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
4008 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
4010 Builder
bld(ctx
->program
, ctx
->block
);
4011 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
4012 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
4014 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
4015 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
4016 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
4017 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
4018 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
4019 /* dlc*/ false, /* slc */ slc
);
4021 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
4024 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
4025 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
4026 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
4028 Builder
bld(ctx
->program
, ctx
->block
);
4029 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4031 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
4033 unsigned write_count
= 0;
4034 Temp write_datas
[32];
4035 unsigned offsets
[32];
4036 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
4037 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4039 for (unsigned i
= 0; i
< write_count
; i
++) {
4040 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4041 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
4045 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4046 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4047 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4049 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4050 assert((num_components
* elem_size_bytes
) == dst
.bytes());
4051 assert(!!stride
!= allow_combining
);
4053 Builder
bld(ctx
->program
, ctx
->block
);
4055 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4056 info
.component_stride
= allow_combining
? 0 : stride
;
4058 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4059 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4060 info
.align_offset
= 0;
4061 info
.soffset
= soffset
;
4062 info
.const_offset
= base_const_offset
;
4063 emit_mubuf_load(ctx
, bld
, &info
);
4066 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4068 Builder
bld(ctx
->program
, ctx
->block
);
4069 Temp offset
= base_offset
.first
;
4070 unsigned const_offset
= base_offset
.second
;
4072 if (!nir_src_is_const(*off_src
)) {
4073 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4076 /* Calculate indirect offset with stride */
4077 if (likely(indirect_offset_arg
.regClass() == v1
))
4078 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4079 else if (indirect_offset_arg
.regClass() == s1
)
4080 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4082 unreachable("Unsupported register class of indirect offset");
4084 /* Add to the supplied base offset */
4085 if (offset
.id() == 0)
4086 offset
= with_stride
;
4087 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4088 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4089 else if (offset
.size() == 1 && with_stride
.size() == 1)
4090 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4092 unreachable("Unsupported register class of indirect offset");
4094 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4095 const_offset
+= const_offset_arg
* stride
;
4098 return std::make_pair(offset
, const_offset
);
4101 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4103 Builder
bld(ctx
->program
, ctx
->block
);
4106 if (off1
.first
.id() && off2
.first
.id()) {
4107 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4108 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4109 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4110 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4112 unreachable("Unsupported register class of indirect offset");
4114 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4117 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4120 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4122 Builder
bld(ctx
->program
, ctx
->block
);
4123 unsigned const_offset
= offs
.second
* multiplier
;
4125 if (!offs
.first
.id())
4126 return std::make_pair(offs
.first
, const_offset
);
4128 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4129 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4130 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4132 return std::make_pair(offset
, const_offset
);
4135 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4137 Builder
bld(ctx
->program
, ctx
->block
);
4139 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4140 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4141 /* component is in bytes */
4142 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4144 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4145 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4146 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4149 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4151 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4154 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4156 Builder
bld(ctx
->program
, ctx
->block
);
4158 switch (ctx
->shader
->info
.stage
) {
4159 case MESA_SHADER_TESS_CTRL
:
4160 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4161 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4162 case MESA_SHADER_TESS_EVAL
:
4163 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4165 unreachable("Unsupported stage in get_tess_rel_patch_id");
4169 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4171 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4172 Builder
bld(ctx
->program
, ctx
->block
);
4174 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4175 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4177 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4179 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4180 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4182 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4183 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4184 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4186 return offset_mul(ctx
, offs
, 4u);
4189 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4191 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4192 Builder
bld(ctx
->program
, ctx
->block
);
4194 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4195 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4196 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4197 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4199 std::pair
<Temp
, unsigned> offs
= instr
4200 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4201 : std::make_pair(Temp(), 0u);
4203 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4204 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4209 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4210 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4212 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4213 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4215 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4216 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4222 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4224 Builder
bld(ctx
->program
, ctx
->block
);
4226 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4227 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4229 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4231 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4232 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4233 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4235 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4236 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4241 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4243 Builder
bld(ctx
->program
, ctx
->block
);
4245 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4246 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4247 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4248 unsigned attr_stride
= ctx
->tcs_num_patches
;
4250 std::pair
<Temp
, unsigned> offs
= instr
4251 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4252 : std::make_pair(Temp(), 0u);
4254 if (const_base_offset
)
4255 offs
.second
+= const_base_offset
* attr_stride
;
4257 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4258 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4259 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4264 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4266 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4271 unsigned drv_loc
= nir_intrinsic_base(instr
);
4272 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4274 if (!nir_src_is_const(*off_src
)) {
4280 uint64_t slot
= per_vertex
4281 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4282 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4283 return (((uint64_t) 1) << slot
) & mask
;
4286 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4288 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4289 unsigned component
= nir_intrinsic_component(instr
);
4290 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4292 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4293 if (off_instr
->type
!= nir_instr_type_load_const
)
4296 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4297 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4299 if (instr
->src
[0].ssa
->bit_size
== 64)
4300 write_mask
= widen_mask(write_mask
, 2);
4302 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4304 for (unsigned i
= 0; i
< 8; ++i
) {
4305 if (write_mask
& (1 << i
)) {
4306 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4307 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4315 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4317 /* Only TCS per-vertex inputs are supported by this function.
4318 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4320 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4323 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4324 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4325 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4326 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4327 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4328 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4333 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4334 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4335 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4340 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4342 Builder
bld(ctx
->program
, ctx
->block
);
4344 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4345 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4346 bool indirect_write
;
4347 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4348 if (temp_only_input
&& !indirect_write
)
4352 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4353 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4354 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4355 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4357 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4358 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4359 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4360 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4361 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4365 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4366 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4367 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4368 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4369 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4370 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4371 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4372 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4373 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4374 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4375 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4376 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4377 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4379 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4380 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4382 unreachable("Invalid LS or ES stage");
4385 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4386 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4387 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4391 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4396 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4397 return off
== ctx
->tcs_tess_lvl_out_loc
||
4398 off
== ctx
->tcs_tess_lvl_in_loc
;
4402 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4404 uint64_t mask
= per_vertex
4405 ? ctx
->program
->info
->tcs
.tes_inputs_read
4406 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4408 bool indirect_write
= false;
4409 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4410 return indirect_write
|| output_read_by_tes
;
4413 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4415 uint64_t mask
= per_vertex
4416 ? ctx
->shader
->info
.outputs_read
4417 : ctx
->shader
->info
.patch_outputs_read
;
4419 bool indirect_write
= false;
4420 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4421 return indirect_write
|| output_read
;
4424 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4426 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4427 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4429 Builder
bld(ctx
->program
, ctx
->block
);
4431 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4432 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4433 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4435 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4436 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4437 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4439 if (write_to_vmem
) {
4440 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4441 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4442 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4444 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4445 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4446 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4450 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4451 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4452 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4456 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4458 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4459 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4461 Builder
bld(ctx
->program
, ctx
->block
);
4463 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4464 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4465 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4466 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4468 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4471 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4473 if (ctx
->stage
== vertex_vs
||
4474 ctx
->stage
== tess_eval_vs
||
4475 ctx
->stage
== fragment_fs
||
4476 ctx
->stage
== ngg_vertex_gs
||
4477 ctx
->stage
== ngg_tess_eval_gs
||
4478 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4479 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4480 if (!stored_to_temps
) {
4481 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4482 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4483 fprintf(stderr
, "\n");
4486 } else if (ctx
->stage
== vertex_es
||
4487 ctx
->stage
== vertex_ls
||
4488 ctx
->stage
== tess_eval_es
||
4489 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4490 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4491 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4492 visit_store_ls_or_es_output(ctx
, instr
);
4493 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4494 visit_store_tcs_output(ctx
, instr
, false);
4496 unreachable("Shader stage not implemented");
4500 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4502 visit_load_tcs_output(ctx
, instr
, false);
4505 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4507 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4508 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4510 Builder
bld(ctx
->program
, ctx
->block
);
4512 if (dst
.regClass() == v2b
) {
4513 if (ctx
->program
->has_16bank_lds
) {
4514 assert(ctx
->options
->chip_class
<= GFX8
);
4515 Builder::Result interp_p1
=
4516 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4517 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4518 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4519 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4520 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4521 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4523 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4525 if (ctx
->options
->chip_class
== GFX8
)
4526 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4528 Builder::Result interp_p1
=
4529 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4530 coord1
, bld
.m0(prim_mask
), idx
, component
);
4531 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4532 interp_p1
, idx
, component
);
4535 Builder::Result interp_p1
=
4536 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4537 bld
.m0(prim_mask
), idx
, component
);
4539 if (ctx
->program
->has_16bank_lds
)
4540 interp_p1
.instr
->operands
[0].setLateKill(true);
4542 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4543 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4547 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4549 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4550 for (unsigned i
= 0; i
< num_components
; i
++)
4551 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4552 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4553 assert(num_components
== 4);
4554 Builder
bld(ctx
->program
, ctx
->block
);
4555 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4558 for (Operand
& op
: vec
->operands
)
4559 op
= op
.isUndefined() ? Operand(0u) : op
;
4561 vec
->definitions
[0] = Definition(dst
);
4562 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4563 emit_split_vector(ctx
, dst
, num_components
);
4567 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4569 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4570 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4571 unsigned idx
= nir_intrinsic_base(instr
);
4572 unsigned component
= nir_intrinsic_component(instr
);
4573 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4575 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4577 assert(offset
->u32
== 0);
4579 /* the lower 15bit of the prim_mask contain the offset into LDS
4580 * while the upper bits contain the number of prims */
4581 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4582 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4583 Builder
bld(ctx
->program
, ctx
->block
);
4584 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4585 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4586 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4587 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4588 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4591 if (instr
->dest
.ssa
.num_components
== 1) {
4592 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4594 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4595 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4597 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4598 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4599 vec
->operands
[i
] = Operand(tmp
);
4601 vec
->definitions
[0] = Definition(dst
);
4602 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4606 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4607 unsigned offset
, unsigned stride
, unsigned channels
)
4609 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4610 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4612 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4613 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4616 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4617 unsigned offset
, unsigned stride
, unsigned *channels
)
4619 if (!vtx_info
->chan_byte_size
) {
4620 *channels
= vtx_info
->num_channels
;
4621 return vtx_info
->chan_format
;
4624 unsigned num_channels
= *channels
;
4625 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4626 unsigned new_channels
= num_channels
+ 1;
4627 /* first, assume more loads is worse and try using a larger data format */
4628 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4630 /* don't make the attribute potentially out-of-bounds */
4631 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4635 if (new_channels
== 5) {
4636 /* then try decreasing load size (at the cost of more loads) */
4637 new_channels
= *channels
;
4638 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4642 if (new_channels
< *channels
)
4643 *channels
= new_channels
;
4644 num_channels
= new_channels
;
4647 switch (vtx_info
->chan_format
) {
4648 case V_008F0C_BUF_DATA_FORMAT_8
:
4649 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4650 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4651 case V_008F0C_BUF_DATA_FORMAT_16
:
4652 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4653 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4654 case V_008F0C_BUF_DATA_FORMAT_32
:
4655 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4656 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4658 unreachable("shouldn't reach here");
4659 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4662 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4663 * so we may need to fix it up. */
4664 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4666 Builder
bld(ctx
->program
, ctx
->block
);
4668 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4669 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4671 /* For the integer-like cases, do a natural sign extension.
4673 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4674 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4677 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4678 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4680 /* Convert back to the right type. */
4681 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4682 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4683 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4684 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4685 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4686 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4692 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4694 Builder
bld(ctx
->program
, ctx
->block
);
4695 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4696 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4698 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4699 if (off_instr
->type
!= nir_instr_type_load_const
) {
4700 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4701 nir_print_instr(off_instr
, stderr
);
4702 fprintf(stderr
, "\n");
4704 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4706 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4708 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4709 unsigned component
= nir_intrinsic_component(instr
);
4710 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4711 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4712 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4713 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4714 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4716 unsigned dfmt
= attrib_format
& 0xf;
4717 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4718 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4720 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4721 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4722 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4723 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4725 num_channels
= MAX2(num_channels
, 3);
4727 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4728 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4731 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4732 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4733 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4735 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4737 Temp divided
= bld
.tmp(v1
);
4738 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4739 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4741 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4744 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4747 index
= bld
.vadd32(bld
.def(v1
),
4748 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4749 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4752 Temp channels
[num_channels
];
4753 unsigned channel_start
= 0;
4754 bool direct_fetch
= false;
4756 /* skip unused channels at the start */
4757 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4758 channel_start
= ffs(mask
) - 1;
4759 for (unsigned i
= 0; i
< channel_start
; i
++)
4760 channels
[i
] = Temp(0, s1
);
4761 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4762 num_channels
= 3 - (ffs(mask
) - 1);
4766 while (channel_start
< num_channels
) {
4767 unsigned fetch_component
= num_channels
- channel_start
;
4768 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4769 bool expanded
= false;
4771 /* use MUBUF when possible to avoid possible alignment issues */
4772 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4773 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4774 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4775 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4776 vtx_info
->chan_byte_size
== 4;
4777 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4779 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4781 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4782 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4783 fetch_component
= 4;
4788 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4790 Temp fetch_index
= index
;
4791 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4792 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4793 fetch_offset
= fetch_offset
% attrib_stride
;
4796 Operand
soffset(0u);
4797 if (fetch_offset
>= 4096) {
4798 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4799 fetch_offset
%= 4096;
4803 switch (fetch_bytes
) {
4805 assert(!use_mubuf
&& bitsize
== 16);
4806 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4809 if (bitsize
== 16) {
4811 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4813 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4817 assert(!use_mubuf
&& bitsize
== 16);
4818 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4821 if (bitsize
== 16) {
4823 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4825 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4829 assert(ctx
->options
->chip_class
>= GFX7
||
4830 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4831 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4834 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4837 unreachable("Unimplemented load_input vector size");
4841 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4842 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4843 num_channels
<= 3)) {
4844 direct_fetch
= true;
4847 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4852 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4853 fetch_offset
, false, false, true).instr
;
4856 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4857 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4860 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4862 if (fetch_component
== 1) {
4863 channels
[channel_start
] = fetch_dst
;
4865 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4866 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4867 bitsize
== 16 ? v2b
: v1
);
4870 channel_start
+= fetch_component
;
4873 if (!direct_fetch
) {
4874 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4875 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4877 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4878 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4879 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4881 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4882 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4883 unsigned num_temp
= 0;
4884 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4885 unsigned idx
= i
+ component
;
4886 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4887 Temp channel
= channels
[swizzle
[idx
]];
4888 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4889 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4890 vec
->operands
[i
] = Operand(channel
);
4894 } else if (is_float
&& idx
== 3) {
4895 vec
->operands
[i
] = Operand(0x3f800000u
);
4896 } else if (!is_float
&& idx
== 3) {
4897 vec
->operands
[i
] = Operand(1u);
4899 vec
->operands
[i
] = Operand(0u);
4902 vec
->definitions
[0] = Definition(dst
);
4903 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4904 emit_split_vector(ctx
, dst
, dst
.size());
4906 if (num_temp
== dst
.size())
4907 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4909 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4910 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4911 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4912 if (off_instr
->type
!= nir_instr_type_load_const
||
4913 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4914 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4915 nir_print_instr(off_instr
, stderr
);
4916 fprintf(stderr
, "\n");
4919 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4920 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4922 assert(offset
->u32
== 0);
4924 /* the lower 15bit of the prim_mask contain the offset into LDS
4925 * while the upper bits contain the number of prims */
4926 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4927 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4928 Builder
bld(ctx
->program
, ctx
->block
);
4929 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4930 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4931 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4932 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4933 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4936 unsigned idx
= nir_intrinsic_base(instr
);
4937 unsigned component
= nir_intrinsic_component(instr
);
4938 unsigned vertex_id
= 2; /* P0 */
4940 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4941 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4942 switch (src0
->u32
) {
4944 vertex_id
= 2; /* P0 */
4947 vertex_id
= 0; /* P10 */
4950 vertex_id
= 1; /* P20 */
4953 unreachable("invalid vertex index");
4957 if (dst
.size() == 1) {
4958 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4960 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4961 for (unsigned i
= 0; i
< dst
.size(); i
++)
4962 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4963 vec
->definitions
[0] = Definition(dst
);
4964 bld
.insert(std::move(vec
));
4967 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4968 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4969 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4970 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4971 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4973 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4975 unreachable("Shader stage not implemented");
4979 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4981 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4983 Builder
bld(ctx
->program
, ctx
->block
);
4984 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4987 if (!nir_src_is_const(*vertex_src
)) {
4988 /* better code could be created, but this case probably doesn't happen
4989 * much in practice */
4990 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4991 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4994 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4995 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4997 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4999 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
5002 if (vertex_offset
.id()) {
5003 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
5004 Operand(i
), indirect_vertex
);
5005 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
5007 vertex_offset
= elem
;
5011 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5012 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
5014 unsigned vertex
= nir_src_as_uint(*vertex_src
);
5015 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5016 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5017 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
5018 Operand((vertex
% 2u) * 16u), Operand(16u));
5020 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
5023 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
5024 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
5025 return offset_mul(ctx
, offs
, 4u);
5028 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5030 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5032 Builder
bld(ctx
->program
, ctx
->block
);
5033 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5034 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5036 if (ctx
->stage
== geometry_gs
) {
5037 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
5038 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
5039 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
5040 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5041 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
5042 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5043 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5045 unreachable("Unsupported GS stage.");
5049 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5051 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5053 Builder
bld(ctx
->program
, ctx
->block
);
5054 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5056 if (load_input_from_temps(ctx
, instr
, dst
))
5059 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5060 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5061 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5063 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5066 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5068 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5070 Builder
bld(ctx
->program
, ctx
->block
);
5072 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5073 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5074 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5076 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5077 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5079 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5082 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5084 switch (ctx
->shader
->info
.stage
) {
5085 case MESA_SHADER_GEOMETRY
:
5086 visit_load_gs_per_vertex_input(ctx
, instr
);
5088 case MESA_SHADER_TESS_CTRL
:
5089 visit_load_tcs_per_vertex_input(ctx
, instr
);
5091 case MESA_SHADER_TESS_EVAL
:
5092 visit_load_tes_per_vertex_input(ctx
, instr
);
5095 unreachable("Unimplemented shader stage");
5099 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5101 visit_load_tcs_output(ctx
, instr
, true);
5104 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5106 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5107 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5109 visit_store_tcs_output(ctx
, instr
, true);
5112 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5114 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5116 Builder
bld(ctx
->program
, ctx
->block
);
5117 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5119 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5120 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5123 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5124 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5125 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5126 tes_w
= Operand(tmp
);
5129 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5130 emit_split_vector(ctx
, tess_coord
, 3);
5133 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5135 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5136 Builder
bld(ctx
->program
, ctx
->block
);
5137 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5138 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5139 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5142 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5146 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5148 Builder
bld(ctx
->program
, ctx
->block
);
5149 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5150 if (!nir_dest_is_divergent(instr
->dest
))
5151 index
= bld
.as_uniform(index
);
5152 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5153 unsigned binding
= nir_intrinsic_binding(instr
);
5156 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5157 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5158 unsigned offset
= layout
->binding
[binding
].offset
;
5160 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5161 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5162 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5163 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5164 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5167 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5168 stride
= layout
->binding
[binding
].size
;
5171 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5172 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5174 if (nir_const_index
) {
5175 const_index
= const_index
* stride
;
5176 } else if (index
.type() == RegType::vgpr
) {
5177 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5178 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5180 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5184 if (nir_const_index
) {
5185 const_index
= const_index
+ offset
;
5186 } else if (index
.type() == RegType::vgpr
) {
5187 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5189 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5193 if (nir_const_index
&& const_index
== 0) {
5195 } else if (index
.type() == RegType::vgpr
) {
5196 index
= bld
.vadd32(bld
.def(v1
),
5197 nir_const_index
? Operand(const_index
) : Operand(index
),
5200 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5201 nir_const_index
? Operand(const_index
) : Operand(index
),
5205 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5208 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5209 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5210 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5212 Builder
bld(ctx
->program
, ctx
->block
);
5214 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5216 offset
= bld
.as_uniform(offset
);
5218 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5221 info
.align_mul
= align_mul
;
5222 info
.align_offset
= align_offset
;
5224 emit_smem_load(ctx
, bld
, &info
);
5226 emit_mubuf_load(ctx
, bld
, &info
);
5229 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5231 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5232 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5234 Builder
bld(ctx
->program
, ctx
->block
);
5236 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5237 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5238 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5239 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5241 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5242 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5246 if (ctx
->options
->chip_class
>= GFX10
) {
5247 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5248 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5249 S_008F0C_RESOURCE_LEVEL(1);
5251 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5252 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5254 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5255 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5256 Operand(0xFFFFFFFFu
),
5257 Operand(desc_type
));
5258 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5259 rsrc
, upper_dwords
);
5261 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5262 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5264 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5265 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5266 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5269 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5271 Builder
bld(ctx
->program
, ctx
->block
);
5272 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5273 unsigned offset
= nir_intrinsic_base(instr
);
5274 unsigned count
= instr
->dest
.ssa
.num_components
;
5275 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5277 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5278 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5279 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5280 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5281 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5282 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5283 for (unsigned i
= 0; i
< count
; ++i
) {
5284 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5285 vec
->operands
[i
] = Operand
{elems
[i
]};
5287 vec
->definitions
[0] = Definition(dst
);
5288 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5289 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5294 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5295 if (offset
!= 0) // TODO check if index != 0 as well
5296 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5297 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5300 bool aligned
= true;
5302 if (instr
->dest
.ssa
.bit_size
== 8) {
5303 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5304 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5306 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5307 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5308 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5310 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5315 switch (vec
.size()) {
5317 op
= aco_opcode::s_load_dword
;
5320 op
= aco_opcode::s_load_dwordx2
;
5326 op
= aco_opcode::s_load_dwordx4
;
5332 op
= aco_opcode::s_load_dwordx8
;
5335 unreachable("unimplemented or forbidden load_push_constant.");
5338 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5341 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5342 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5347 emit_split_vector(ctx
, vec
, 4);
5348 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5349 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5350 emit_extract_vector(ctx
, vec
, 0, rc
),
5351 emit_extract_vector(ctx
, vec
, 1, rc
),
5352 emit_extract_vector(ctx
, vec
, 2, rc
));
5355 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5358 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5360 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5362 Builder
bld(ctx
->program
, ctx
->block
);
5364 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5365 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5366 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5367 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5368 if (ctx
->options
->chip_class
>= GFX10
) {
5369 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5370 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5371 S_008F0C_RESOURCE_LEVEL(1);
5373 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5374 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5377 unsigned base
= nir_intrinsic_base(instr
);
5378 unsigned range
= nir_intrinsic_range(instr
);
5380 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5381 if (base
&& offset
.type() == RegType::sgpr
)
5382 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5383 else if (base
&& offset
.type() == RegType::vgpr
)
5384 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5386 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5387 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5388 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5389 Operand(desc_type
));
5390 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5391 // TODO: get alignment information for subdword constants
5392 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5395 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5397 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5398 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5400 ctx
->program
->needs_exact
= true;
5402 // TODO: optimize uniform conditions
5403 Builder
bld(ctx
->program
, ctx
->block
);
5404 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5405 assert(src
.regClass() == bld
.lm
);
5406 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5407 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5408 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5412 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5414 Builder
bld(ctx
->program
, ctx
->block
);
5416 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5417 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5419 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5420 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5422 if (ctx
->block
->loop_nest_depth
&&
5423 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5424 /* we handle discards the same way as jump instructions */
5425 append_logical_end(ctx
->block
);
5427 /* in loops, discard behaves like break */
5428 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5429 ctx
->block
->kind
|= block_kind_discard
;
5432 /* uniform discard - loop ends here */
5433 assert(nir_instr_is_last(&instr
->instr
));
5434 ctx
->block
->kind
|= block_kind_uniform
;
5435 ctx
->cf_info
.has_branch
= true;
5436 bld
.branch(aco_opcode::p_branch
);
5437 add_linear_edge(ctx
->block
->index
, linear_target
);
5441 /* we add a break right behind the discard() instructions */
5442 ctx
->block
->kind
|= block_kind_break
;
5443 unsigned idx
= ctx
->block
->index
;
5445 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5446 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5448 /* remove critical edges from linear CFG */
5449 bld
.branch(aco_opcode::p_branch
);
5450 Block
* break_block
= ctx
->program
->create_and_insert_block();
5451 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5452 break_block
->kind
|= block_kind_uniform
;
5453 add_linear_edge(idx
, break_block
);
5454 add_linear_edge(break_block
->index
, linear_target
);
5455 bld
.reset(break_block
);
5456 bld
.branch(aco_opcode::p_branch
);
5458 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5459 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5460 add_linear_edge(idx
, continue_block
);
5461 append_logical_start(continue_block
);
5462 ctx
->block
= continue_block
;
5467 /* it can currently happen that NIR doesn't remove the unreachable code */
5468 if (!nir_instr_is_last(&instr
->instr
)) {
5469 ctx
->program
->needs_exact
= true;
5470 /* save exec somewhere temporarily so that it doesn't get
5471 * overwritten before the discard from outer exec masks */
5472 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5473 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5474 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5478 /* This condition is incorrect for uniformly branched discards in a loop
5479 * predicated by a divergent condition, but the above code catches that case
5480 * and the discard would end up turning into a discard_if.
5490 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5491 /* program just ends here */
5492 ctx
->block
->kind
|= block_kind_uniform
;
5493 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5494 0 /* enabled mask */, 9 /* dest */,
5495 false /* compressed */, true/* done */, true /* valid mask */);
5496 bld
.sopp(aco_opcode::s_endpgm
);
5497 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5499 ctx
->block
->kind
|= block_kind_discard
;
5500 /* branch and linear edge is added by visit_if() */
5504 enum aco_descriptor_type
{
5515 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5516 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5518 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5519 return dim
== ac_image_cube
||
5520 dim
== ac_image_1darray
||
5521 dim
== ac_image_2darray
||
5522 dim
== ac_image_2darraymsaa
;
5525 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5526 enum aco_descriptor_type desc_type
,
5527 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5529 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5530 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5531 if (it != ctx->tex_desc.end())
5534 Temp index
= Temp();
5535 bool index_set
= false;
5536 unsigned constant_index
= 0;
5537 unsigned descriptor_set
;
5538 unsigned base_index
;
5539 Builder
bld(ctx
->program
, ctx
->block
);
5542 assert(tex_instr
&& !image
);
5544 base_index
= tex_instr
->sampler_index
;
5546 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5547 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5551 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5552 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5554 constant_index
+= array_size
* const_value
->u32
;
5556 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5557 if (indirect
.type() == RegType::vgpr
)
5558 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5560 if (array_size
!= 1)
5561 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5567 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5571 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5573 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5574 base_index
= deref_instr
->var
->data
.binding
;
5577 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5578 list
= convert_pointer_to_64_bit(ctx
, list
);
5580 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5581 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5582 unsigned offset
= binding
->offset
;
5583 unsigned stride
= binding
->size
;
5587 assert(base_index
< layout
->binding_count
);
5589 switch (desc_type
) {
5590 case ACO_DESC_IMAGE
:
5592 opcode
= aco_opcode::s_load_dwordx8
;
5594 case ACO_DESC_FMASK
:
5596 opcode
= aco_opcode::s_load_dwordx8
;
5599 case ACO_DESC_SAMPLER
:
5601 opcode
= aco_opcode::s_load_dwordx4
;
5602 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5603 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5605 case ACO_DESC_BUFFER
:
5607 opcode
= aco_opcode::s_load_dwordx4
;
5609 case ACO_DESC_PLANE_0
:
5610 case ACO_DESC_PLANE_1
:
5612 opcode
= aco_opcode::s_load_dwordx8
;
5613 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5615 case ACO_DESC_PLANE_2
:
5617 opcode
= aco_opcode::s_load_dwordx4
;
5621 unreachable("invalid desc_type\n");
5624 offset
+= constant_index
* stride
;
5626 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5627 (!index_set
|| binding
->immutable_samplers_equal
)) {
5628 if (binding
->immutable_samplers_equal
)
5631 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5632 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5633 Operand(samplers
[constant_index
* 4 + 0]),
5634 Operand(samplers
[constant_index
* 4 + 1]),
5635 Operand(samplers
[constant_index
* 4 + 2]),
5636 Operand(samplers
[constant_index
* 4 + 3]));
5641 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5643 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5644 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5647 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5649 if (desc_type
== ACO_DESC_PLANE_2
) {
5651 for (unsigned i
= 0; i
< 8; i
++)
5652 components
[i
] = bld
.tmp(s1
);
5653 bld
.pseudo(aco_opcode::p_split_vector
,
5654 Definition(components
[0]),
5655 Definition(components
[1]),
5656 Definition(components
[2]),
5657 Definition(components
[3]),
5660 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5661 bld
.pseudo(aco_opcode::p_split_vector
,
5662 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5663 Definition(components
[4]),
5664 Definition(components
[5]),
5665 Definition(components
[6]),
5666 Definition(components
[7]),
5669 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5670 components
[0], components
[1], components
[2], components
[3],
5671 components
[4], components
[5], components
[6], components
[7]);
5677 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5680 case GLSL_SAMPLER_DIM_BUF
:
5682 case GLSL_SAMPLER_DIM_1D
:
5683 return array
? 2 : 1;
5684 case GLSL_SAMPLER_DIM_2D
:
5685 return array
? 3 : 2;
5686 case GLSL_SAMPLER_DIM_MS
:
5687 return array
? 4 : 3;
5688 case GLSL_SAMPLER_DIM_3D
:
5689 case GLSL_SAMPLER_DIM_CUBE
:
5691 case GLSL_SAMPLER_DIM_RECT
:
5692 case GLSL_SAMPLER_DIM_SUBPASS
:
5694 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5703 /* Adjust the sample index according to FMASK.
5705 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5706 * which is the identity mapping. Each nibble says which physical sample
5707 * should be fetched to get that sample.
5709 * For example, 0x11111100 means there are only 2 samples stored and
5710 * the second sample covers 3/4 of the pixel. When reading samples 0
5711 * and 1, return physical sample 0 (determined by the first two 0s
5712 * in FMASK), otherwise return physical sample 1.
5714 * The sample index should be adjusted as follows:
5715 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5717 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5719 Builder
bld(ctx
->program
, ctx
->block
);
5720 Temp fmask
= bld
.tmp(v1
);
5721 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5722 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5725 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5726 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5727 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5728 load
->operands
[0] = Operand(fmask_desc_ptr
);
5729 load
->operands
[1] = Operand(s4
); /* no sampler */
5730 load
->operands
[2] = Operand(coord
);
5731 load
->definitions
[0] = Definition(fmask
);
5738 ctx
->block
->instructions
.emplace_back(std::move(load
));
5740 Operand sample_index4
;
5741 if (sample_index
.isConstant()) {
5742 if (sample_index
.constantValue() < 16) {
5743 sample_index4
= Operand(sample_index
.constantValue() << 2);
5745 sample_index4
= Operand(0u);
5747 } else if (sample_index
.regClass() == s1
) {
5748 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5750 assert(sample_index
.regClass() == v1
);
5751 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5755 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5756 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5757 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5758 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5760 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5762 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5763 * resource descriptor is 0 (invalid),
5765 Temp compare
= bld
.tmp(bld
.lm
);
5766 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5767 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5769 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5771 /* Replace the MSAA sample index. */
5772 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5775 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5778 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5779 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5780 bool is_array
= glsl_sampler_type_is_array(type
);
5781 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5782 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5783 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5784 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5785 int count
= image_type_to_components_count(dim
, is_array
);
5786 std::vector
<Temp
> coords(count
);
5787 Builder
bld(ctx
->program
, ctx
->block
);
5791 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5792 /* get sample index */
5793 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5794 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5795 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5796 std::vector
<Temp
> fmask_load_address
;
5797 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5798 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5800 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5801 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5803 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5808 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5809 coords
.resize(coords
.size() + 1);
5810 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5812 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5814 for (int i
= 0; i
< count
; i
++)
5815 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5818 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5819 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5820 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5821 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5824 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5827 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5828 for (unsigned i
= 0; i
< coords
.size(); i
++)
5829 vec
->operands
[i
] = Operand(coords
[i
]);
5830 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5831 vec
->definitions
[0] = Definition(res
);
5832 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5837 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5839 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5840 if (semantics
& semantic_atomicrmw
)
5841 return memory_sync_info(storage
, semantics
);
5843 unsigned access
= nir_intrinsic_access(instr
);
5845 if (access
& ACCESS_VOLATILE
)
5846 semantics
|= semantic_volatile
;
5847 if (access
& ACCESS_CAN_REORDER
)
5848 semantics
|= semantic_can_reorder
| semantic_private
;
5850 return memory_sync_info(storage
, semantics
);
5853 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5855 Builder
bld(ctx
->program
, ctx
->block
);
5856 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5857 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5858 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5859 bool is_array
= glsl_sampler_type_is_array(type
);
5860 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5862 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5863 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5865 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5866 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5867 unsigned num_channels
= util_last_bit(mask
);
5868 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5869 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5872 switch (num_channels
) {
5874 opcode
= aco_opcode::buffer_load_format_x
;
5877 opcode
= aco_opcode::buffer_load_format_xy
;
5880 opcode
= aco_opcode::buffer_load_format_xyz
;
5883 opcode
= aco_opcode::buffer_load_format_xyzw
;
5886 unreachable(">4 channel buffer image load");
5888 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5889 load
->operands
[0] = Operand(rsrc
);
5890 load
->operands
[1] = Operand(vindex
);
5891 load
->operands
[2] = Operand((uint32_t) 0);
5893 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5896 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5897 load
->definitions
[0] = Definition(tmp
);
5899 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5900 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5902 ctx
->block
->instructions
.emplace_back(std::move(load
));
5904 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5908 Temp coords
= get_image_coords(ctx
, instr
, type
);
5909 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5911 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5912 unsigned num_components
= util_bitcount(dmask
);
5914 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5917 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5919 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5920 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5922 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5923 load
->operands
[0] = Operand(resource
);
5924 load
->operands
[1] = Operand(s4
); /* no sampler */
5925 load
->operands
[2] = Operand(coords
);
5926 load
->definitions
[0] = Definition(tmp
);
5927 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5928 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5929 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5930 load
->dmask
= dmask
;
5932 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5934 ctx
->block
->instructions
.emplace_back(std::move(load
));
5936 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5940 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5942 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5943 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5944 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5945 bool is_array
= glsl_sampler_type_is_array(type
);
5946 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5948 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5949 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5950 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5952 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5953 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5954 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5956 switch (data
.size()) {
5958 opcode
= aco_opcode::buffer_store_format_x
;
5961 opcode
= aco_opcode::buffer_store_format_xy
;
5964 opcode
= aco_opcode::buffer_store_format_xyz
;
5967 opcode
= aco_opcode::buffer_store_format_xyzw
;
5970 unreachable(">4 channel buffer image store");
5972 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5973 store
->operands
[0] = Operand(rsrc
);
5974 store
->operands
[1] = Operand(vindex
);
5975 store
->operands
[2] = Operand((uint32_t) 0);
5976 store
->operands
[3] = Operand(data
);
5977 store
->idxen
= true;
5980 store
->disable_wqm
= true;
5982 ctx
->program
->needs_exact
= true;
5983 ctx
->block
->instructions
.emplace_back(std::move(store
));
5987 assert(data
.type() == RegType::vgpr
);
5988 Temp coords
= get_image_coords(ctx
, instr
, type
);
5989 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5991 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5992 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5994 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5995 store
->operands
[0] = Operand(resource
);
5996 store
->operands
[1] = Operand(data
);
5997 store
->operands
[2] = Operand(coords
);
6000 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6001 store
->dmask
= (1 << data
.size()) - 1;
6003 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6004 store
->disable_wqm
= true;
6006 ctx
->program
->needs_exact
= true;
6007 ctx
->block
->instructions
.emplace_back(std::move(store
));
6011 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6013 /* return the previous value if dest is ever used */
6014 bool return_previous
= false;
6015 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6016 return_previous
= true;
6019 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6020 return_previous
= true;
6024 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6025 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6026 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6027 bool is_array
= glsl_sampler_type_is_array(type
);
6028 Builder
bld(ctx
->program
, ctx
->block
);
6030 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
6031 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
6033 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
6034 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
6036 aco_opcode buf_op
, image_op
;
6037 switch (instr
->intrinsic
) {
6038 case nir_intrinsic_image_deref_atomic_add
:
6039 buf_op
= aco_opcode::buffer_atomic_add
;
6040 image_op
= aco_opcode::image_atomic_add
;
6042 case nir_intrinsic_image_deref_atomic_umin
:
6043 buf_op
= aco_opcode::buffer_atomic_umin
;
6044 image_op
= aco_opcode::image_atomic_umin
;
6046 case nir_intrinsic_image_deref_atomic_imin
:
6047 buf_op
= aco_opcode::buffer_atomic_smin
;
6048 image_op
= aco_opcode::image_atomic_smin
;
6050 case nir_intrinsic_image_deref_atomic_umax
:
6051 buf_op
= aco_opcode::buffer_atomic_umax
;
6052 image_op
= aco_opcode::image_atomic_umax
;
6054 case nir_intrinsic_image_deref_atomic_imax
:
6055 buf_op
= aco_opcode::buffer_atomic_smax
;
6056 image_op
= aco_opcode::image_atomic_smax
;
6058 case nir_intrinsic_image_deref_atomic_and
:
6059 buf_op
= aco_opcode::buffer_atomic_and
;
6060 image_op
= aco_opcode::image_atomic_and
;
6062 case nir_intrinsic_image_deref_atomic_or
:
6063 buf_op
= aco_opcode::buffer_atomic_or
;
6064 image_op
= aco_opcode::image_atomic_or
;
6066 case nir_intrinsic_image_deref_atomic_xor
:
6067 buf_op
= aco_opcode::buffer_atomic_xor
;
6068 image_op
= aco_opcode::image_atomic_xor
;
6070 case nir_intrinsic_image_deref_atomic_exchange
:
6071 buf_op
= aco_opcode::buffer_atomic_swap
;
6072 image_op
= aco_opcode::image_atomic_swap
;
6074 case nir_intrinsic_image_deref_atomic_comp_swap
:
6075 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
6076 image_op
= aco_opcode::image_atomic_cmpswap
;
6079 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6082 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6083 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
6085 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6086 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6087 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6088 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6089 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6090 mubuf
->operands
[0] = Operand(resource
);
6091 mubuf
->operands
[1] = Operand(vindex
);
6092 mubuf
->operands
[2] = Operand((uint32_t)0);
6093 mubuf
->operands
[3] = Operand(data
);
6094 if (return_previous
)
6095 mubuf
->definitions
[0] = Definition(dst
);
6097 mubuf
->idxen
= true;
6098 mubuf
->glc
= return_previous
;
6099 mubuf
->dlc
= false; /* Not needed for atomics */
6100 mubuf
->disable_wqm
= true;
6102 ctx
->program
->needs_exact
= true;
6103 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6107 Temp coords
= get_image_coords(ctx
, instr
, type
);
6108 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6109 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6110 mimg
->operands
[0] = Operand(resource
);
6111 mimg
->operands
[1] = Operand(data
);
6112 mimg
->operands
[2] = Operand(coords
);
6113 if (return_previous
)
6114 mimg
->definitions
[0] = Definition(dst
);
6115 mimg
->glc
= return_previous
;
6116 mimg
->dlc
= false; /* Not needed for atomics */
6117 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6118 mimg
->dmask
= (1 << data
.size()) - 1;
6120 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6121 mimg
->disable_wqm
= true;
6123 ctx
->program
->needs_exact
= true;
6124 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6128 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6130 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6131 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6132 Builder
bld(ctx
->program
, ctx
->block
);
6134 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6136 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6137 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6139 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6140 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6142 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6143 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6145 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6146 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6147 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6148 if (dst
.type() == RegType::vgpr
)
6149 bld
.copy(Definition(dst
), shr_dst
);
6151 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6153 emit_extract_vector(ctx
, desc
, 2, dst
);
6157 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6159 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6160 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6161 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6162 bool is_array
= glsl_sampler_type_is_array(type
);
6163 Builder
bld(ctx
->program
, ctx
->block
);
6165 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6166 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6167 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6171 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6174 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6176 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6178 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6179 mimg
->operands
[0] = Operand(resource
);
6180 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6181 mimg
->operands
[2] = Operand(lod
);
6182 uint8_t& dmask
= mimg
->dmask
;
6183 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6184 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6185 mimg
->da
= glsl_sampler_type_is_array(type
);
6186 Definition
& def
= mimg
->definitions
[0];
6187 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6189 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6190 glsl_sampler_type_is_array(type
)) {
6192 assert(instr
->dest
.ssa
.num_components
== 3);
6193 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6194 def
= Definition(tmp
);
6195 emit_split_vector(ctx
, tmp
, 3);
6197 /* divide 3rd value by 6 by multiplying with magic number */
6198 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6199 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6201 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6202 emit_extract_vector(ctx
, tmp
, 0, v1
),
6203 emit_extract_vector(ctx
, tmp
, 1, v1
),
6206 } else if (ctx
->options
->chip_class
== GFX9
&&
6207 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6208 glsl_sampler_type_is_array(type
)) {
6209 assert(instr
->dest
.ssa
.num_components
== 2);
6210 def
= Definition(dst
);
6213 def
= Definition(dst
);
6216 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6219 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6221 Builder
bld(ctx
->program
, ctx
->block
);
6222 unsigned num_components
= instr
->num_components
;
6224 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6225 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6226 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6228 unsigned access
= nir_intrinsic_access(instr
);
6229 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6230 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6232 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6233 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6234 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6236 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6237 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6239 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6240 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6241 get_memory_sync_info(instr
, storage_buffer
, 0));
6244 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6246 Builder
bld(ctx
->program
, ctx
->block
);
6247 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6248 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6249 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6250 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6252 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6253 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6255 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6256 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6257 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6258 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6259 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6261 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6263 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6264 ctx
->options
->chip_class
>= GFX8
&&
6265 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6268 offset
= bld
.as_uniform(offset
);
6269 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6271 unsigned write_count
= 0;
6272 Temp write_datas
[32];
6273 unsigned offsets
[32];
6274 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6275 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6277 for (unsigned i
= 0; i
< write_count
; i
++) {
6278 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6279 if (smem
&& ctx
->stage
== fragment_fs
)
6280 op
= aco_opcode::p_fs_buffer_store_smem
;
6283 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6284 store
->operands
[0] = Operand(rsrc
);
6286 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6287 offset
, Operand(offsets
[i
]));
6288 store
->operands
[1] = Operand(off
);
6290 store
->operands
[1] = Operand(offset
);
6292 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6293 store
->operands
[1].setFixed(m0
);
6294 store
->operands
[2] = Operand(write_datas
[i
]);
6297 store
->disable_wqm
= true;
6299 ctx
->block
->instructions
.emplace_back(std::move(store
));
6300 ctx
->program
->wb_smem_l1_on_end
= true;
6301 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6302 ctx
->block
->kind
|= block_kind_needs_lowering
;
6303 ctx
->program
->needs_exact
= true;
6306 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6307 store
->operands
[0] = Operand(rsrc
);
6308 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6309 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6310 store
->operands
[3] = Operand(write_datas
[i
]);
6311 store
->offset
= offsets
[i
];
6312 store
->offen
= (offset
.type() == RegType::vgpr
);
6315 store
->disable_wqm
= true;
6317 ctx
->program
->needs_exact
= true;
6318 ctx
->block
->instructions
.emplace_back(std::move(store
));
6323 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6325 /* return the previous value if dest is ever used */
6326 bool return_previous
= false;
6327 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6328 return_previous
= true;
6331 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6332 return_previous
= true;
6336 Builder
bld(ctx
->program
, ctx
->block
);
6337 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6339 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6340 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6341 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6343 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6344 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6345 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6347 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6349 aco_opcode op32
, op64
;
6350 switch (instr
->intrinsic
) {
6351 case nir_intrinsic_ssbo_atomic_add
:
6352 op32
= aco_opcode::buffer_atomic_add
;
6353 op64
= aco_opcode::buffer_atomic_add_x2
;
6355 case nir_intrinsic_ssbo_atomic_imin
:
6356 op32
= aco_opcode::buffer_atomic_smin
;
6357 op64
= aco_opcode::buffer_atomic_smin_x2
;
6359 case nir_intrinsic_ssbo_atomic_umin
:
6360 op32
= aco_opcode::buffer_atomic_umin
;
6361 op64
= aco_opcode::buffer_atomic_umin_x2
;
6363 case nir_intrinsic_ssbo_atomic_imax
:
6364 op32
= aco_opcode::buffer_atomic_smax
;
6365 op64
= aco_opcode::buffer_atomic_smax_x2
;
6367 case nir_intrinsic_ssbo_atomic_umax
:
6368 op32
= aco_opcode::buffer_atomic_umax
;
6369 op64
= aco_opcode::buffer_atomic_umax_x2
;
6371 case nir_intrinsic_ssbo_atomic_and
:
6372 op32
= aco_opcode::buffer_atomic_and
;
6373 op64
= aco_opcode::buffer_atomic_and_x2
;
6375 case nir_intrinsic_ssbo_atomic_or
:
6376 op32
= aco_opcode::buffer_atomic_or
;
6377 op64
= aco_opcode::buffer_atomic_or_x2
;
6379 case nir_intrinsic_ssbo_atomic_xor
:
6380 op32
= aco_opcode::buffer_atomic_xor
;
6381 op64
= aco_opcode::buffer_atomic_xor_x2
;
6383 case nir_intrinsic_ssbo_atomic_exchange
:
6384 op32
= aco_opcode::buffer_atomic_swap
;
6385 op64
= aco_opcode::buffer_atomic_swap_x2
;
6387 case nir_intrinsic_ssbo_atomic_comp_swap
:
6388 op32
= aco_opcode::buffer_atomic_cmpswap
;
6389 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6392 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6394 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6395 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6396 mubuf
->operands
[0] = Operand(rsrc
);
6397 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6398 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6399 mubuf
->operands
[3] = Operand(data
);
6400 if (return_previous
)
6401 mubuf
->definitions
[0] = Definition(dst
);
6403 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6404 mubuf
->glc
= return_previous
;
6405 mubuf
->dlc
= false; /* Not needed for atomics */
6406 mubuf
->disable_wqm
= true;
6407 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6408 ctx
->program
->needs_exact
= true;
6409 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6412 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6414 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6415 Builder
bld(ctx
->program
, ctx
->block
);
6416 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6417 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6420 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6422 Builder
bld(ctx
->program
, ctx
->block
);
6423 unsigned num_components
= instr
->num_components
;
6424 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6426 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6427 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6428 num_components
, component_size
};
6429 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6430 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6431 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6432 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6433 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6434 * it's safe to use SMEM */
6435 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6436 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6437 emit_global_load(ctx
, bld
, &info
);
6439 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6440 emit_smem_load(ctx
, bld
, &info
);
6444 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6446 Builder
bld(ctx
->program
, ctx
->block
);
6447 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6448 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6450 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6451 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6452 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6453 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6455 if (ctx
->options
->chip_class
>= GFX7
)
6456 addr
= as_vgpr(ctx
, addr
);
6458 unsigned write_count
= 0;
6459 Temp write_datas
[32];
6460 unsigned offsets
[32];
6461 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6462 16, &write_count
, write_datas
, offsets
);
6464 for (unsigned i
= 0; i
< write_count
; i
++) {
6465 if (ctx
->options
->chip_class
>= GFX7
) {
6466 unsigned offset
= offsets
[i
];
6467 Temp store_addr
= addr
;
6468 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6469 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6470 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6471 Temp carry
= bld
.tmp(bld
.lm
);
6472 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6474 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6475 Operand(offset
), addr0
);
6476 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6478 carry
).def(1).setHint(vcc
);
6480 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6485 bool global
= ctx
->options
->chip_class
>= GFX9
;
6487 switch (write_datas
[i
].bytes()) {
6489 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6492 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6495 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6498 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6501 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6504 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6507 unreachable("store_global not implemented for this size.");
6510 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6511 flat
->operands
[0] = Operand(store_addr
);
6512 flat
->operands
[1] = Operand(s1
);
6513 flat
->operands
[2] = Operand(write_datas
[i
]);
6516 flat
->offset
= offset
;
6517 flat
->disable_wqm
= true;
6519 ctx
->program
->needs_exact
= true;
6520 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6522 assert(ctx
->options
->chip_class
== GFX6
);
6524 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6526 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6528 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6529 mubuf
->operands
[0] = Operand(rsrc
);
6530 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6531 mubuf
->operands
[2] = Operand(0u);
6532 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6535 mubuf
->offset
= offsets
[i
];
6536 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6537 mubuf
->disable_wqm
= true;
6539 ctx
->program
->needs_exact
= true;
6540 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6545 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6547 /* return the previous value if dest is ever used */
6548 bool return_previous
= false;
6549 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6550 return_previous
= true;
6553 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6554 return_previous
= true;
6558 Builder
bld(ctx
->program
, ctx
->block
);
6559 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6560 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6562 if (ctx
->options
->chip_class
>= GFX7
)
6563 addr
= as_vgpr(ctx
, addr
);
6565 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6566 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6567 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6569 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6571 aco_opcode op32
, op64
;
6573 if (ctx
->options
->chip_class
>= GFX7
) {
6574 bool global
= ctx
->options
->chip_class
>= GFX9
;
6575 switch (instr
->intrinsic
) {
6576 case nir_intrinsic_global_atomic_add
:
6577 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6578 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6580 case nir_intrinsic_global_atomic_imin
:
6581 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6582 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6584 case nir_intrinsic_global_atomic_umin
:
6585 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6586 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6588 case nir_intrinsic_global_atomic_imax
:
6589 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6590 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6592 case nir_intrinsic_global_atomic_umax
:
6593 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6594 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6596 case nir_intrinsic_global_atomic_and
:
6597 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6598 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6600 case nir_intrinsic_global_atomic_or
:
6601 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6602 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6604 case nir_intrinsic_global_atomic_xor
:
6605 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6606 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6608 case nir_intrinsic_global_atomic_exchange
:
6609 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6610 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6612 case nir_intrinsic_global_atomic_comp_swap
:
6613 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6614 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6617 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6620 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6621 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6622 flat
->operands
[0] = Operand(addr
);
6623 flat
->operands
[1] = Operand(s1
);
6624 flat
->operands
[2] = Operand(data
);
6625 if (return_previous
)
6626 flat
->definitions
[0] = Definition(dst
);
6627 flat
->glc
= return_previous
;
6628 flat
->dlc
= false; /* Not needed for atomics */
6630 flat
->disable_wqm
= true;
6631 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6632 ctx
->program
->needs_exact
= true;
6633 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6635 assert(ctx
->options
->chip_class
== GFX6
);
6637 switch (instr
->intrinsic
) {
6638 case nir_intrinsic_global_atomic_add
:
6639 op32
= aco_opcode::buffer_atomic_add
;
6640 op64
= aco_opcode::buffer_atomic_add_x2
;
6642 case nir_intrinsic_global_atomic_imin
:
6643 op32
= aco_opcode::buffer_atomic_smin
;
6644 op64
= aco_opcode::buffer_atomic_smin_x2
;
6646 case nir_intrinsic_global_atomic_umin
:
6647 op32
= aco_opcode::buffer_atomic_umin
;
6648 op64
= aco_opcode::buffer_atomic_umin_x2
;
6650 case nir_intrinsic_global_atomic_imax
:
6651 op32
= aco_opcode::buffer_atomic_smax
;
6652 op64
= aco_opcode::buffer_atomic_smax_x2
;
6654 case nir_intrinsic_global_atomic_umax
:
6655 op32
= aco_opcode::buffer_atomic_umax
;
6656 op64
= aco_opcode::buffer_atomic_umax_x2
;
6658 case nir_intrinsic_global_atomic_and
:
6659 op32
= aco_opcode::buffer_atomic_and
;
6660 op64
= aco_opcode::buffer_atomic_and_x2
;
6662 case nir_intrinsic_global_atomic_or
:
6663 op32
= aco_opcode::buffer_atomic_or
;
6664 op64
= aco_opcode::buffer_atomic_or_x2
;
6666 case nir_intrinsic_global_atomic_xor
:
6667 op32
= aco_opcode::buffer_atomic_xor
;
6668 op64
= aco_opcode::buffer_atomic_xor_x2
;
6670 case nir_intrinsic_global_atomic_exchange
:
6671 op32
= aco_opcode::buffer_atomic_swap
;
6672 op64
= aco_opcode::buffer_atomic_swap_x2
;
6674 case nir_intrinsic_global_atomic_comp_swap
:
6675 op32
= aco_opcode::buffer_atomic_cmpswap
;
6676 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6679 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6682 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6684 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6686 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6687 mubuf
->operands
[0] = Operand(rsrc
);
6688 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6689 mubuf
->operands
[2] = Operand(0u);
6690 mubuf
->operands
[3] = Operand(data
);
6691 if (return_previous
)
6692 mubuf
->definitions
[0] = Definition(dst
);
6693 mubuf
->glc
= return_previous
;
6696 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6697 mubuf
->disable_wqm
= true;
6698 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6699 ctx
->program
->needs_exact
= true;
6700 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6704 sync_scope
translate_nir_scope(nir_scope scope
)
6707 case NIR_SCOPE_NONE
:
6708 case NIR_SCOPE_INVOCATION
:
6709 return scope_invocation
;
6710 case NIR_SCOPE_SUBGROUP
:
6711 return scope_subgroup
;
6712 case NIR_SCOPE_WORKGROUP
:
6713 return scope_workgroup
;
6714 case NIR_SCOPE_QUEUE_FAMILY
:
6715 return scope_queuefamily
;
6716 case NIR_SCOPE_DEVICE
:
6717 return scope_device
;
6719 unreachable("invalid scope");
6722 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6723 Builder
bld(ctx
->program
, ctx
->block
);
6724 storage_class all_mem
= (storage_class
)(storage_buffer
| storage_image
| storage_atomic_counter
| storage_shared
);
6725 switch(instr
->intrinsic
) {
6726 case nir_intrinsic_group_memory_barrier
:
6727 bld
.barrier(aco_opcode::p_barrier
,
6728 memory_sync_info(all_mem
, semantic_acqrel
, scope_workgroup
));
6730 case nir_intrinsic_memory_barrier
:
6731 bld
.barrier(aco_opcode::p_barrier
,
6732 memory_sync_info(all_mem
, semantic_acqrel
, scope_device
));
6734 case nir_intrinsic_memory_barrier_buffer
:
6735 bld
.barrier(aco_opcode::p_barrier
,
6736 memory_sync_info((storage_class
)storage_buffer
, semantic_acqrel
, scope_device
));
6737 case nir_intrinsic_memory_barrier_image
:
6738 bld
.barrier(aco_opcode::p_barrier
,
6739 memory_sync_info((storage_class
)storage_image
, semantic_acqrel
, scope_device
));
6741 case nir_intrinsic_memory_barrier_tcs_patch
:
6742 case nir_intrinsic_memory_barrier_shared
:
6743 bld
.barrier(aco_opcode::p_barrier
,
6744 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
));
6746 case nir_intrinsic_scoped_barrier
: {
6747 unsigned semantics
= 0;
6748 unsigned storage
= 0;
6749 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6750 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6752 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6753 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6754 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6755 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6756 storage
|= storage_shared
;
6757 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6758 storage
|= storage_shared
;
6760 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6761 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6762 semantics
|= semantic_acquire
| semantic_release
;
6763 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6764 semantics
|= semantic_acquire
| semantic_release
;
6766 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6768 bld
.barrier(aco_opcode::p_barrier
,
6769 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6774 unreachable("Unimplemented memory barrier intrinsic");
6779 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6781 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6782 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6783 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6784 Builder
bld(ctx
->program
, ctx
->block
);
6786 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6787 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6788 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6791 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6793 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6794 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6795 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6796 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6798 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6799 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6802 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6804 unsigned offset
= nir_intrinsic_base(instr
);
6805 Builder
bld(ctx
->program
, ctx
->block
);
6806 Operand m
= load_lds_size_m0(bld
);
6807 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6808 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6810 unsigned num_operands
= 3;
6811 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6812 switch(instr
->intrinsic
) {
6813 case nir_intrinsic_shared_atomic_add
:
6814 op32
= aco_opcode::ds_add_u32
;
6815 op64
= aco_opcode::ds_add_u64
;
6816 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6817 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6819 case nir_intrinsic_shared_atomic_imin
:
6820 op32
= aco_opcode::ds_min_i32
;
6821 op64
= aco_opcode::ds_min_i64
;
6822 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6823 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6825 case nir_intrinsic_shared_atomic_umin
:
6826 op32
= aco_opcode::ds_min_u32
;
6827 op64
= aco_opcode::ds_min_u64
;
6828 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6829 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6831 case nir_intrinsic_shared_atomic_imax
:
6832 op32
= aco_opcode::ds_max_i32
;
6833 op64
= aco_opcode::ds_max_i64
;
6834 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6835 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6837 case nir_intrinsic_shared_atomic_umax
:
6838 op32
= aco_opcode::ds_max_u32
;
6839 op64
= aco_opcode::ds_max_u64
;
6840 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6841 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6843 case nir_intrinsic_shared_atomic_and
:
6844 op32
= aco_opcode::ds_and_b32
;
6845 op64
= aco_opcode::ds_and_b64
;
6846 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6847 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6849 case nir_intrinsic_shared_atomic_or
:
6850 op32
= aco_opcode::ds_or_b32
;
6851 op64
= aco_opcode::ds_or_b64
;
6852 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6853 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6855 case nir_intrinsic_shared_atomic_xor
:
6856 op32
= aco_opcode::ds_xor_b32
;
6857 op64
= aco_opcode::ds_xor_b64
;
6858 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6859 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6861 case nir_intrinsic_shared_atomic_exchange
:
6862 op32
= aco_opcode::ds_write_b32
;
6863 op64
= aco_opcode::ds_write_b64
;
6864 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6865 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6867 case nir_intrinsic_shared_atomic_comp_swap
:
6868 op32
= aco_opcode::ds_cmpst_b32
;
6869 op64
= aco_opcode::ds_cmpst_b64
;
6870 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6871 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6874 case nir_intrinsic_shared_atomic_fadd
:
6875 op32
= aco_opcode::ds_add_f32
;
6876 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6877 op64
= aco_opcode::num_opcodes
;
6878 op64_rtn
= aco_opcode::num_opcodes
;
6881 unreachable("Unhandled shared atomic intrinsic");
6884 /* return the previous value if dest is ever used */
6885 bool return_previous
= false;
6886 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6887 return_previous
= true;
6890 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6891 return_previous
= true;
6896 if (data
.size() == 1) {
6897 assert(instr
->dest
.ssa
.bit_size
== 32);
6898 op
= return_previous
? op32_rtn
: op32
;
6900 assert(instr
->dest
.ssa
.bit_size
== 64);
6901 op
= return_previous
? op64_rtn
: op64
;
6904 if (offset
> 65535) {
6905 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6909 aco_ptr
<DS_instruction
> ds
;
6910 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6911 ds
->operands
[0] = Operand(address
);
6912 ds
->operands
[1] = Operand(data
);
6913 if (num_operands
== 4)
6914 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6915 ds
->operands
[num_operands
- 1] = m
;
6916 ds
->offset0
= offset
;
6917 if (return_previous
)
6918 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6919 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6920 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6923 Temp
get_scratch_resource(isel_context
*ctx
)
6925 Builder
bld(ctx
->program
, ctx
->block
);
6926 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6927 if (ctx
->stage
!= compute_cs
)
6928 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6930 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6931 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6933 if (ctx
->program
->chip_class
>= GFX10
) {
6934 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6935 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6936 S_008F0C_RESOURCE_LEVEL(1);
6937 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6938 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6939 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6942 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6943 if (ctx
->program
->chip_class
<= GFX8
)
6944 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6946 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6949 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6950 Builder
bld(ctx
->program
, ctx
->block
);
6951 Temp rsrc
= get_scratch_resource(ctx
);
6952 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6953 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6955 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6956 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6957 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6958 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6959 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6960 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6961 info
.soffset
= ctx
->program
->scratch_offset
;
6962 emit_scratch_load(ctx
, bld
, &info
);
6965 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6966 Builder
bld(ctx
->program
, ctx
->block
);
6967 Temp rsrc
= get_scratch_resource(ctx
);
6968 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6969 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6971 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6972 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6974 unsigned write_count
= 0;
6975 Temp write_datas
[32];
6976 unsigned offsets
[32];
6977 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6978 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6979 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6981 for (unsigned i
= 0; i
< write_count
; i
++) {
6982 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6983 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6984 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6988 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6989 uint8_t log2_ps_iter_samples
;
6990 if (ctx
->program
->info
->ps
.force_persample
) {
6991 log2_ps_iter_samples
=
6992 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6994 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6997 /* The bit pattern matches that used by fixed function fragment
6999 static const unsigned ps_iter_masks
[] = {
7000 0xffff, /* not used */
7006 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
7008 Builder
bld(ctx
->program
, ctx
->block
);
7010 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
7011 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7012 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
7013 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
7014 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7015 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
7018 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7019 Builder
bld(ctx
->program
, ctx
->block
);
7021 unsigned stream
= nir_intrinsic_stream_id(instr
);
7022 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7023 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
7024 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
7027 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
7029 unsigned num_components
=
7030 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
7031 assert(num_components
);
7033 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
7034 unsigned stream_offset
= 0;
7035 for (unsigned i
= 0; i
< stream
; i
++) {
7036 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
7037 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
7040 /* Limit on the stride field for <= GFX7. */
7041 assert(stride
< (1 << 14));
7043 Temp gsvs_dwords
[4];
7044 for (unsigned i
= 0; i
< 4; i
++)
7045 gsvs_dwords
[i
] = bld
.tmp(s1
);
7046 bld
.pseudo(aco_opcode::p_split_vector
,
7047 Definition(gsvs_dwords
[0]),
7048 Definition(gsvs_dwords
[1]),
7049 Definition(gsvs_dwords
[2]),
7050 Definition(gsvs_dwords
[3]),
7053 if (stream_offset
) {
7054 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
7056 Temp carry
= bld
.tmp(s1
);
7057 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
7058 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
7061 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
7062 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
7064 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7065 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
7067 unsigned offset
= 0;
7068 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
7069 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
7072 for (unsigned j
= 0; j
< 4; j
++) {
7073 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7076 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7077 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7078 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7079 if (const_offset
>= 4096u) {
7080 if (vaddr_offset
.isUndefined())
7081 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7083 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7084 const_offset
%= 4096u;
7087 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7088 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7089 mtbuf
->operands
[1] = vaddr_offset
;
7090 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7091 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7092 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7093 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7094 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7095 mtbuf
->offset
= const_offset
;
7098 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
7099 bld
.insert(std::move(mtbuf
));
7102 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7105 /* outputs for the next vertex are undefined and keeping them around can
7106 * create invalid IR with control flow */
7107 ctx
->outputs
.mask
[i
] = 0;
7110 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7113 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7115 Builder
bld(ctx
->program
, ctx
->block
);
7117 if (cluster_size
== 1) {
7119 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7120 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7121 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7122 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7123 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7124 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7125 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7126 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7127 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7128 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7129 //subgroupAnd(val) -> (exec & ~val) == 0
7130 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7131 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7132 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7133 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7134 //subgroupOr(val) -> (val & exec) != 0
7135 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7136 return bool_to_vector_condition(ctx
, tmp
);
7137 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7138 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7139 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7140 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7141 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7142 return bool_to_vector_condition(ctx
, tmp
);
7144 //subgroupClustered{And,Or,Xor}(val, n) ->
7145 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7146 //cluster_offset = ~(n - 1) & lane_id
7147 //cluster_mask = ((1 << n) - 1)
7148 //subgroupClusteredAnd():
7149 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7150 //subgroupClusteredOr():
7151 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7152 //subgroupClusteredXor():
7153 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7154 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7155 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7158 if (op
== nir_op_iand
)
7159 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7161 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7163 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7165 if (ctx
->program
->chip_class
<= GFX7
)
7166 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7167 else if (ctx
->program
->wave_size
== 64)
7168 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7170 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7171 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7172 if (cluster_mask
!= 0xffffffff)
7173 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7175 Definition cmp_def
= Definition();
7176 if (op
== nir_op_iand
) {
7177 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7178 } else if (op
== nir_op_ior
) {
7179 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7180 } else if (op
== nir_op_ixor
) {
7181 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7182 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7183 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7185 cmp_def
.setHint(vcc
);
7186 return cmp_def
.getTemp();
7190 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7192 Builder
bld(ctx
->program
, ctx
->block
);
7194 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7195 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7196 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7198 if (op
== nir_op_iand
)
7199 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7201 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7203 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7204 Temp lo
= lohi
.def(0).getTemp();
7205 Temp hi
= lohi
.def(1).getTemp();
7206 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7208 Definition cmp_def
= Definition();
7209 if (op
== nir_op_iand
)
7210 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7211 else if (op
== nir_op_ior
)
7212 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7213 else if (op
== nir_op_ixor
)
7214 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7215 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7216 cmp_def
.setHint(vcc
);
7217 return cmp_def
.getTemp();
7220 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7222 Builder
bld(ctx
->program
, ctx
->block
);
7224 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7225 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7226 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7227 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7228 if (op
== nir_op_iand
)
7229 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7230 else if (op
== nir_op_ior
)
7231 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7232 else if (op
== nir_op_ixor
)
7233 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7239 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7241 Builder
bld(ctx
->program
, ctx
->block
);
7242 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7243 if (src
.regClass().type() == RegType::vgpr
) {
7244 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7245 } else if (src
.regClass() == s1
) {
7246 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7247 } else if (src
.regClass() == s2
) {
7248 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7250 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7251 nir_print_instr(&instr
->instr
, stderr
);
7252 fprintf(stderr
, "\n");
7256 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7258 Builder
bld(ctx
->program
, ctx
->block
);
7259 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7260 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7261 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7263 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7264 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7265 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7266 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7269 if (ctx
->program
->chip_class
>= GFX8
) {
7270 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7271 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7272 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7273 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7274 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7275 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7277 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7278 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7279 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7280 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7281 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7282 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7283 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7284 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7285 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7286 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7289 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7290 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7291 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7292 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7293 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7294 Temp wqm1
= bld
.tmp(v1
);
7295 emit_wqm(ctx
, tmp1
, wqm1
, true);
7296 Temp wqm2
= bld
.tmp(v1
);
7297 emit_wqm(ctx
, tmp2
, wqm2
, true);
7298 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7302 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7304 Builder
bld(ctx
->program
, ctx
->block
);
7305 switch(instr
->intrinsic
) {
7306 case nir_intrinsic_load_barycentric_sample
:
7307 case nir_intrinsic_load_barycentric_pixel
:
7308 case nir_intrinsic_load_barycentric_centroid
: {
7309 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7310 Temp bary
= Temp(0, s2
);
7312 case INTERP_MODE_SMOOTH
:
7313 case INTERP_MODE_NONE
:
7314 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7315 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7316 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7317 bary
= ctx
->persp_centroid
;
7318 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7319 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7321 case INTERP_MODE_NOPERSPECTIVE
:
7322 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7323 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7324 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7325 bary
= ctx
->linear_centroid
;
7326 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7327 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7332 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7333 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7334 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7335 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7336 Operand(p1
), Operand(p2
));
7337 emit_split_vector(ctx
, dst
, 2);
7340 case nir_intrinsic_load_barycentric_model
: {
7341 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7343 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7344 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7345 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7346 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7347 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7348 Operand(p1
), Operand(p2
), Operand(p3
));
7349 emit_split_vector(ctx
, dst
, 3);
7352 case nir_intrinsic_load_barycentric_at_sample
: {
7353 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7354 switch (ctx
->options
->key
.fs
.num_samples
) {
7355 case 2: sample_pos_offset
+= 1 << 3; break;
7356 case 4: sample_pos_offset
+= 3 << 3; break;
7357 case 8: sample_pos_offset
+= 7 << 3; break;
7361 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7362 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7363 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7364 //TODO: bounds checking?
7365 if (addr
.type() == RegType::sgpr
) {
7368 sample_pos_offset
+= const_addr
->u32
<< 3;
7369 offset
= Operand(sample_pos_offset
);
7370 } else if (ctx
->options
->chip_class
>= GFX9
) {
7371 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7373 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7374 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7377 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7378 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7380 } else if (ctx
->options
->chip_class
>= GFX9
) {
7381 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7382 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7383 } else if (ctx
->options
->chip_class
>= GFX7
) {
7384 /* addr += private_segment_buffer + sample_pos_offset */
7385 Temp tmp0
= bld
.tmp(s1
);
7386 Temp tmp1
= bld
.tmp(s1
);
7387 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7388 Definition scc_tmp
= bld
.def(s1
, scc
);
7389 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7390 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7391 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7392 Temp pck0
= bld
.tmp(v1
);
7393 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7394 tmp1
= as_vgpr(ctx
, tmp1
);
7395 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7396 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7398 /* sample_pos = flat_load_dwordx2 addr */
7399 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7401 assert(ctx
->options
->chip_class
== GFX6
);
7403 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7404 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7405 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7407 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7408 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7410 sample_pos
= bld
.tmp(v2
);
7412 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7413 load
->definitions
[0] = Definition(sample_pos
);
7414 load
->operands
[0] = Operand(rsrc
);
7415 load
->operands
[1] = Operand(addr
);
7416 load
->operands
[2] = Operand(0u);
7417 load
->offset
= sample_pos_offset
;
7419 load
->addr64
= true;
7422 load
->disable_wqm
= false;
7423 ctx
->block
->instructions
.emplace_back(std::move(load
));
7426 /* sample_pos -= 0.5 */
7427 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7428 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7429 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7430 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7431 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7433 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7436 case nir_intrinsic_load_barycentric_at_offset
: {
7437 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7438 RegClass rc
= RegClass(offset
.type(), 1);
7439 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7440 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7441 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7444 case nir_intrinsic_load_front_face
: {
7445 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7446 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7449 case nir_intrinsic_load_view_index
: {
7450 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7451 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7452 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7458 case nir_intrinsic_load_layer_id
: {
7459 unsigned idx
= nir_intrinsic_base(instr
);
7460 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7461 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7464 case nir_intrinsic_load_frag_coord
: {
7465 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7468 case nir_intrinsic_load_sample_pos
: {
7469 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7470 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7471 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7472 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7473 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7476 case nir_intrinsic_load_tess_coord
:
7477 visit_load_tess_coord(ctx
, instr
);
7479 case nir_intrinsic_load_interpolated_input
:
7480 visit_load_interpolated_input(ctx
, instr
);
7482 case nir_intrinsic_store_output
:
7483 visit_store_output(ctx
, instr
);
7485 case nir_intrinsic_load_input
:
7486 case nir_intrinsic_load_input_vertex
:
7487 visit_load_input(ctx
, instr
);
7489 case nir_intrinsic_load_output
:
7490 visit_load_output(ctx
, instr
);
7492 case nir_intrinsic_load_per_vertex_input
:
7493 visit_load_per_vertex_input(ctx
, instr
);
7495 case nir_intrinsic_load_per_vertex_output
:
7496 visit_load_per_vertex_output(ctx
, instr
);
7498 case nir_intrinsic_store_per_vertex_output
:
7499 visit_store_per_vertex_output(ctx
, instr
);
7501 case nir_intrinsic_load_ubo
:
7502 visit_load_ubo(ctx
, instr
);
7504 case nir_intrinsic_load_push_constant
:
7505 visit_load_push_constant(ctx
, instr
);
7507 case nir_intrinsic_load_constant
:
7508 visit_load_constant(ctx
, instr
);
7510 case nir_intrinsic_vulkan_resource_index
:
7511 visit_load_resource(ctx
, instr
);
7513 case nir_intrinsic_discard
:
7514 visit_discard(ctx
, instr
);
7516 case nir_intrinsic_discard_if
:
7517 visit_discard_if(ctx
, instr
);
7519 case nir_intrinsic_load_shared
:
7520 visit_load_shared(ctx
, instr
);
7522 case nir_intrinsic_store_shared
:
7523 visit_store_shared(ctx
, instr
);
7525 case nir_intrinsic_shared_atomic_add
:
7526 case nir_intrinsic_shared_atomic_imin
:
7527 case nir_intrinsic_shared_atomic_umin
:
7528 case nir_intrinsic_shared_atomic_imax
:
7529 case nir_intrinsic_shared_atomic_umax
:
7530 case nir_intrinsic_shared_atomic_and
:
7531 case nir_intrinsic_shared_atomic_or
:
7532 case nir_intrinsic_shared_atomic_xor
:
7533 case nir_intrinsic_shared_atomic_exchange
:
7534 case nir_intrinsic_shared_atomic_comp_swap
:
7535 case nir_intrinsic_shared_atomic_fadd
:
7536 visit_shared_atomic(ctx
, instr
);
7538 case nir_intrinsic_image_deref_load
:
7539 visit_image_load(ctx
, instr
);
7541 case nir_intrinsic_image_deref_store
:
7542 visit_image_store(ctx
, instr
);
7544 case nir_intrinsic_image_deref_atomic_add
:
7545 case nir_intrinsic_image_deref_atomic_umin
:
7546 case nir_intrinsic_image_deref_atomic_imin
:
7547 case nir_intrinsic_image_deref_atomic_umax
:
7548 case nir_intrinsic_image_deref_atomic_imax
:
7549 case nir_intrinsic_image_deref_atomic_and
:
7550 case nir_intrinsic_image_deref_atomic_or
:
7551 case nir_intrinsic_image_deref_atomic_xor
:
7552 case nir_intrinsic_image_deref_atomic_exchange
:
7553 case nir_intrinsic_image_deref_atomic_comp_swap
:
7554 visit_image_atomic(ctx
, instr
);
7556 case nir_intrinsic_image_deref_size
:
7557 visit_image_size(ctx
, instr
);
7559 case nir_intrinsic_load_ssbo
:
7560 visit_load_ssbo(ctx
, instr
);
7562 case nir_intrinsic_store_ssbo
:
7563 visit_store_ssbo(ctx
, instr
);
7565 case nir_intrinsic_load_global
:
7566 visit_load_global(ctx
, instr
);
7568 case nir_intrinsic_store_global
:
7569 visit_store_global(ctx
, instr
);
7571 case nir_intrinsic_global_atomic_add
:
7572 case nir_intrinsic_global_atomic_imin
:
7573 case nir_intrinsic_global_atomic_umin
:
7574 case nir_intrinsic_global_atomic_imax
:
7575 case nir_intrinsic_global_atomic_umax
:
7576 case nir_intrinsic_global_atomic_and
:
7577 case nir_intrinsic_global_atomic_or
:
7578 case nir_intrinsic_global_atomic_xor
:
7579 case nir_intrinsic_global_atomic_exchange
:
7580 case nir_intrinsic_global_atomic_comp_swap
:
7581 visit_global_atomic(ctx
, instr
);
7583 case nir_intrinsic_ssbo_atomic_add
:
7584 case nir_intrinsic_ssbo_atomic_imin
:
7585 case nir_intrinsic_ssbo_atomic_umin
:
7586 case nir_intrinsic_ssbo_atomic_imax
:
7587 case nir_intrinsic_ssbo_atomic_umax
:
7588 case nir_intrinsic_ssbo_atomic_and
:
7589 case nir_intrinsic_ssbo_atomic_or
:
7590 case nir_intrinsic_ssbo_atomic_xor
:
7591 case nir_intrinsic_ssbo_atomic_exchange
:
7592 case nir_intrinsic_ssbo_atomic_comp_swap
:
7593 visit_atomic_ssbo(ctx
, instr
);
7595 case nir_intrinsic_load_scratch
:
7596 visit_load_scratch(ctx
, instr
);
7598 case nir_intrinsic_store_scratch
:
7599 visit_store_scratch(ctx
, instr
);
7601 case nir_intrinsic_get_buffer_size
:
7602 visit_get_buffer_size(ctx
, instr
);
7604 case nir_intrinsic_control_barrier
: {
7605 bld
.barrier(aco_opcode::p_barrier
, memory_sync_info(0, 0, scope_invocation
), scope_workgroup
);
7608 case nir_intrinsic_memory_barrier_tcs_patch
:
7609 case nir_intrinsic_group_memory_barrier
:
7610 case nir_intrinsic_memory_barrier
:
7611 case nir_intrinsic_memory_barrier_buffer
:
7612 case nir_intrinsic_memory_barrier_image
:
7613 case nir_intrinsic_memory_barrier_shared
:
7614 case nir_intrinsic_scoped_barrier
:
7615 emit_memory_barrier(ctx
, instr
);
7617 case nir_intrinsic_load_num_work_groups
: {
7618 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7619 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7620 emit_split_vector(ctx
, dst
, 3);
7623 case nir_intrinsic_load_local_invocation_id
: {
7624 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7625 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7626 emit_split_vector(ctx
, dst
, 3);
7629 case nir_intrinsic_load_work_group_id
: {
7630 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7631 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7632 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7633 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7634 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7635 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7636 emit_split_vector(ctx
, dst
, 3);
7639 case nir_intrinsic_load_local_invocation_index
: {
7640 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7642 /* The tg_size bits [6:11] contain the subgroup id,
7643 * we need this multiplied by the wave size, and then OR the thread id to it.
7645 if (ctx
->program
->wave_size
== 64) {
7646 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7647 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7648 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7649 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7651 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7652 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7653 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7654 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7658 case nir_intrinsic_load_subgroup_id
: {
7659 if (ctx
->stage
== compute_cs
) {
7660 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7661 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7663 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7667 case nir_intrinsic_load_subgroup_invocation
: {
7668 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7671 case nir_intrinsic_load_num_subgroups
: {
7672 if (ctx
->stage
== compute_cs
)
7673 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7674 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7676 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7679 case nir_intrinsic_ballot
: {
7680 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7681 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7682 Definition tmp
= bld
.def(dst
.regClass());
7683 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7684 if (instr
->src
[0].ssa
->bit_size
== 1) {
7685 assert(src
.regClass() == bld
.lm
);
7686 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7687 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7688 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7689 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7690 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7692 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7693 nir_print_instr(&instr
->instr
, stderr
);
7694 fprintf(stderr
, "\n");
7696 if (dst
.size() != bld
.lm
.size()) {
7697 /* Wave32 with ballot size set to 64 */
7698 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7700 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7703 case nir_intrinsic_shuffle
:
7704 case nir_intrinsic_read_invocation
: {
7705 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7706 if (!nir_src_is_divergent(instr
->src
[0])) {
7707 emit_uniform_subgroup(ctx
, instr
, src
);
7709 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7710 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7711 tid
= bld
.as_uniform(tid
);
7712 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7713 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7714 Temp tmp
= bld
.tmp(v1
);
7715 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7716 if (dst
.type() == RegType::vgpr
)
7717 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7719 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7720 } else if (src
.regClass() == v1
) {
7721 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7722 } else if (src
.regClass() == v2
) {
7723 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7724 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7725 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7726 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7727 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7728 emit_split_vector(ctx
, dst
, 2);
7729 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7730 assert(src
.regClass() == bld
.lm
);
7731 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7732 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7733 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7734 assert(src
.regClass() == bld
.lm
);
7736 if (ctx
->program
->chip_class
<= GFX7
)
7737 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7738 else if (ctx
->program
->wave_size
== 64)
7739 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7741 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7742 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7743 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7744 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7746 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7747 nir_print_instr(&instr
->instr
, stderr
);
7748 fprintf(stderr
, "\n");
7753 case nir_intrinsic_load_sample_id
: {
7754 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7755 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7758 case nir_intrinsic_load_sample_mask_in
: {
7759 visit_load_sample_mask_in(ctx
, instr
);
7762 case nir_intrinsic_read_first_invocation
: {
7763 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7764 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7765 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7767 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7769 } else if (src
.regClass() == v2
) {
7770 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7772 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7773 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7775 emit_split_vector(ctx
, dst
, 2);
7776 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7777 assert(src
.regClass() == bld
.lm
);
7778 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7779 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7780 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7781 } else if (src
.regClass() == s1
) {
7782 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7783 } else if (src
.regClass() == s2
) {
7784 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7786 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7787 nir_print_instr(&instr
->instr
, stderr
);
7788 fprintf(stderr
, "\n");
7792 case nir_intrinsic_vote_all
: {
7793 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7794 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7795 assert(src
.regClass() == bld
.lm
);
7796 assert(dst
.regClass() == bld
.lm
);
7798 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7799 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7800 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7803 case nir_intrinsic_vote_any
: {
7804 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7805 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7806 assert(src
.regClass() == bld
.lm
);
7807 assert(dst
.regClass() == bld
.lm
);
7809 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7810 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7813 case nir_intrinsic_reduce
:
7814 case nir_intrinsic_inclusive_scan
:
7815 case nir_intrinsic_exclusive_scan
: {
7816 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7817 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7818 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7819 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7820 nir_intrinsic_cluster_size(instr
) : 0;
7821 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7823 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7824 emit_uniform_subgroup(ctx
, instr
, src
);
7825 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7826 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7828 else if (op
== nir_op_iadd
)
7830 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7832 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7834 switch (instr
->intrinsic
) {
7835 case nir_intrinsic_reduce
:
7836 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7838 case nir_intrinsic_exclusive_scan
:
7839 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7841 case nir_intrinsic_inclusive_scan
:
7842 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7847 } else if (cluster_size
== 1) {
7848 bld
.copy(Definition(dst
), src
);
7850 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7852 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7856 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7857 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7872 unreachable("unknown reduction op");
7878 switch (instr
->intrinsic
) {
7879 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7880 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7881 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7883 unreachable("unknown reduce intrinsic");
7886 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7887 reduce
->operands
[0] = Operand(src
);
7888 // filled in by aco_reduce_assign.cpp, used internally as part of the
7890 assert(dst
.size() == 1 || dst
.size() == 2);
7891 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7892 reduce
->operands
[2] = Operand(v1
.as_linear());
7894 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7895 reduce
->definitions
[0] = Definition(tmp_dst
);
7896 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7897 reduce
->definitions
[2] = Definition();
7898 reduce
->definitions
[3] = Definition(scc
, s1
);
7899 reduce
->definitions
[4] = Definition();
7900 reduce
->reduce_op
= reduce_op
;
7901 reduce
->cluster_size
= cluster_size
;
7902 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7904 emit_wqm(ctx
, tmp_dst
, dst
);
7908 case nir_intrinsic_quad_broadcast
: {
7909 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7910 if (!nir_dest_is_divergent(instr
->dest
)) {
7911 emit_uniform_subgroup(ctx
, instr
, src
);
7913 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7914 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7915 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7917 if (instr
->dest
.ssa
.bit_size
== 1) {
7918 assert(src
.regClass() == bld
.lm
);
7919 assert(dst
.regClass() == bld
.lm
);
7920 uint32_t half_mask
= 0x11111111u
<< lane
;
7921 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7922 Temp tmp
= bld
.tmp(bld
.lm
);
7923 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7924 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7925 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7926 emit_wqm(ctx
, tmp
, dst
);
7927 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7928 Temp tmp
= bld
.tmp(v1
);
7929 if (ctx
->program
->chip_class
>= GFX8
)
7930 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7932 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7933 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7934 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7935 Temp tmp
= bld
.tmp(v1
);
7936 if (ctx
->program
->chip_class
>= GFX8
)
7937 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7939 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7941 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7942 if (ctx
->program
->chip_class
>= GFX8
)
7943 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7945 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7946 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7947 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7948 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7949 if (ctx
->program
->chip_class
>= GFX8
) {
7950 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7951 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7953 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7954 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7956 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7957 emit_split_vector(ctx
, dst
, 2);
7959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7960 nir_print_instr(&instr
->instr
, stderr
);
7961 fprintf(stderr
, "\n");
7966 case nir_intrinsic_quad_swap_horizontal
:
7967 case nir_intrinsic_quad_swap_vertical
:
7968 case nir_intrinsic_quad_swap_diagonal
:
7969 case nir_intrinsic_quad_swizzle_amd
: {
7970 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7971 if (!nir_dest_is_divergent(instr
->dest
)) {
7972 emit_uniform_subgroup(ctx
, instr
, src
);
7975 uint16_t dpp_ctrl
= 0;
7976 switch (instr
->intrinsic
) {
7977 case nir_intrinsic_quad_swap_horizontal
:
7978 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7980 case nir_intrinsic_quad_swap_vertical
:
7981 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7983 case nir_intrinsic_quad_swap_diagonal
:
7984 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7986 case nir_intrinsic_quad_swizzle_amd
:
7987 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7992 if (ctx
->program
->chip_class
< GFX8
)
7993 dpp_ctrl
|= (1 << 15);
7995 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7996 if (instr
->dest
.ssa
.bit_size
== 1) {
7997 assert(src
.regClass() == bld
.lm
);
7998 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7999 if (ctx
->program
->chip_class
>= GFX8
)
8000 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8002 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8003 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8004 emit_wqm(ctx
, tmp
, dst
);
8005 } else if (instr
->dest
.ssa
.bit_size
== 8) {
8006 Temp tmp
= bld
.tmp(v1
);
8007 if (ctx
->program
->chip_class
>= GFX8
)
8008 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8010 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8011 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
8012 } else if (instr
->dest
.ssa
.bit_size
== 16) {
8013 Temp tmp
= bld
.tmp(v1
);
8014 if (ctx
->program
->chip_class
>= GFX8
)
8015 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8017 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8018 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
8019 } else if (instr
->dest
.ssa
.bit_size
== 32) {
8021 if (ctx
->program
->chip_class
>= GFX8
)
8022 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8024 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8025 emit_wqm(ctx
, tmp
, dst
);
8026 } else if (instr
->dest
.ssa
.bit_size
== 64) {
8027 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8028 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8029 if (ctx
->program
->chip_class
>= GFX8
) {
8030 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8031 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8033 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8034 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8036 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8037 emit_split_vector(ctx
, dst
, 2);
8039 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8040 nir_print_instr(&instr
->instr
, stderr
);
8041 fprintf(stderr
, "\n");
8045 case nir_intrinsic_masked_swizzle_amd
: {
8046 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8047 if (!nir_dest_is_divergent(instr
->dest
)) {
8048 emit_uniform_subgroup(ctx
, instr
, src
);
8051 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8052 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
8053 if (instr
->dest
.ssa
.bit_size
== 1) {
8054 assert(src
.regClass() == bld
.lm
);
8055 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
8056 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
8057 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8058 emit_wqm(ctx
, tmp
, dst
);
8059 } else if (dst
.regClass() == v1b
) {
8060 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8061 emit_extract_vector(ctx
, tmp
, 0, dst
);
8062 } else if (dst
.regClass() == v2b
) {
8063 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8064 emit_extract_vector(ctx
, tmp
, 0, dst
);
8065 } else if (dst
.regClass() == v1
) {
8066 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
8067 } else if (dst
.regClass() == v2
) {
8068 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8069 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8070 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
8071 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
8072 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8073 emit_split_vector(ctx
, dst
, 2);
8075 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8076 nir_print_instr(&instr
->instr
, stderr
);
8077 fprintf(stderr
, "\n");
8081 case nir_intrinsic_write_invocation_amd
: {
8082 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8083 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8084 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8085 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8086 if (dst
.regClass() == v1
) {
8087 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8088 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8089 } else if (dst
.regClass() == v2
) {
8090 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8091 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8092 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8093 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8094 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8095 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8096 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8097 emit_split_vector(ctx
, dst
, 2);
8099 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8100 nir_print_instr(&instr
->instr
, stderr
);
8101 fprintf(stderr
, "\n");
8105 case nir_intrinsic_mbcnt_amd
: {
8106 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8107 RegClass rc
= RegClass(src
.type(), 1);
8108 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8109 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8110 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8111 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8112 emit_wqm(ctx
, wqm_tmp
, dst
);
8115 case nir_intrinsic_load_helper_invocation
: {
8116 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8117 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8118 ctx
->block
->kind
|= block_kind_needs_lowering
;
8119 ctx
->program
->needs_exact
= true;
8122 case nir_intrinsic_is_helper_invocation
: {
8123 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8124 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8125 ctx
->block
->kind
|= block_kind_needs_lowering
;
8126 ctx
->program
->needs_exact
= true;
8129 case nir_intrinsic_demote
:
8130 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8132 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8133 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8134 ctx
->block
->kind
|= block_kind_uses_demote
;
8135 ctx
->program
->needs_exact
= true;
8137 case nir_intrinsic_demote_if
: {
8138 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8139 assert(src
.regClass() == bld
.lm
);
8140 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8141 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8143 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8144 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8145 ctx
->block
->kind
|= block_kind_uses_demote
;
8146 ctx
->program
->needs_exact
= true;
8149 case nir_intrinsic_first_invocation
: {
8150 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8151 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8154 case nir_intrinsic_shader_clock
: {
8156 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8157 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8158 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), memory_sync_info(0, semantic_volatile
));
8159 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8162 case nir_intrinsic_load_vertex_id_zero_base
: {
8163 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8164 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8167 case nir_intrinsic_load_first_vertex
: {
8168 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8169 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8172 case nir_intrinsic_load_base_instance
: {
8173 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8174 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8177 case nir_intrinsic_load_instance_id
: {
8178 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8179 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8182 case nir_intrinsic_load_draw_id
: {
8183 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8184 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8187 case nir_intrinsic_load_invocation_id
: {
8188 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8190 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8191 if (ctx
->options
->chip_class
>= GFX10
)
8192 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8194 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8195 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8196 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8197 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8199 unreachable("Unsupported stage for load_invocation_id");
8204 case nir_intrinsic_load_primitive_id
: {
8205 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8207 switch (ctx
->shader
->info
.stage
) {
8208 case MESA_SHADER_GEOMETRY
:
8209 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8211 case MESA_SHADER_TESS_CTRL
:
8212 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8214 case MESA_SHADER_TESS_EVAL
:
8215 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8218 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8223 case nir_intrinsic_load_patch_vertices_in
: {
8224 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8225 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8227 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8228 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8231 case nir_intrinsic_emit_vertex_with_counter
: {
8232 visit_emit_vertex_with_counter(ctx
, instr
);
8235 case nir_intrinsic_end_primitive_with_counter
: {
8236 unsigned stream
= nir_intrinsic_stream_id(instr
);
8237 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8240 case nir_intrinsic_set_vertex_count
: {
8241 /* unused, the HW keeps track of this for us */
8245 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8246 nir_print_instr(&instr
->instr
, stderr
);
8247 fprintf(stderr
, "\n");
8255 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8256 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8257 enum glsl_base_type
*stype
)
8259 nir_deref_instr
*texture_deref_instr
= NULL
;
8260 nir_deref_instr
*sampler_deref_instr
= NULL
;
8263 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8264 switch (instr
->src
[i
].src_type
) {
8265 case nir_tex_src_texture_deref
:
8266 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8268 case nir_tex_src_sampler_deref
:
8269 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8271 case nir_tex_src_plane
:
8272 plane
= nir_src_as_int(instr
->src
[i
].src
);
8279 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8281 if (!sampler_deref_instr
)
8282 sampler_deref_instr
= texture_deref_instr
;
8285 assert(instr
->op
!= nir_texop_txf_ms
&&
8286 instr
->op
!= nir_texop_samples_identical
);
8287 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8288 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8289 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8290 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8291 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8292 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8294 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8297 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8299 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8300 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8301 Builder
bld(ctx
->program
, ctx
->block
);
8303 /* to avoid unnecessary moves, we split and recombine sampler and image */
8304 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8305 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8306 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8307 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8308 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8309 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8310 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8311 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8313 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8314 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8315 img
[0], img
[1], img
[2], img
[3],
8316 img
[4], img
[5], img
[6], img
[7]);
8317 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8318 samp
[0], samp
[1], samp
[2], samp
[3]);
8321 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8322 instr
->op
== nir_texop_samples_identical
))
8323 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8326 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8327 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8329 Builder
bld(ctx
->program
, ctx
->block
);
8331 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8332 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8333 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8335 Operand
neg_one(0xbf800000u
);
8336 Operand
one(0x3f800000u
);
8337 Operand
two(0x40000000u
);
8338 Operand
four(0x40800000u
);
8340 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8341 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8342 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8344 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8345 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8346 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8347 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8350 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8351 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8352 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8354 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8357 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8358 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8359 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8362 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8363 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8365 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8366 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8369 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8371 Builder
bld(ctx
->program
, ctx
->block
);
8372 Temp ma
, tc
, sc
, id
;
8375 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8377 // see comment in ac_prepare_cube_coords()
8378 if (ctx
->options
->chip_class
<= GFX8
)
8379 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8382 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8384 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8385 vop3a
->operands
[0] = Operand(ma
);
8386 vop3a
->abs
[0] = true;
8387 Temp invma
= bld
.tmp(v1
);
8388 vop3a
->definitions
[0] = Definition(invma
);
8389 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8391 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8393 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8395 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8397 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8399 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8402 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8403 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8405 for (unsigned i
= 0; i
< 2; i
++) {
8406 // see comment in ac_prepare_cube_coords()
8408 Temp deriv_sc
, deriv_tc
;
8409 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8410 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8412 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8414 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8415 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8416 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8417 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8418 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8419 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8420 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8423 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8424 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8428 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8435 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8437 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8439 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8440 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8443 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8444 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8445 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8449 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8451 Builder
bld(ctx
->program
, ctx
->block
);
8452 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8453 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8454 has_clamped_lod
= false;
8455 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8456 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8457 clamped_lod
= Temp();
8458 std::vector
<Temp
> coords
;
8459 std::vector
<Temp
> derivs
;
8460 nir_const_value
*sample_index_cv
= NULL
;
8461 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8462 enum glsl_base_type stype
;
8463 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8465 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8466 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8467 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8468 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8470 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8471 switch (instr
->src
[i
].src_type
) {
8472 case nir_tex_src_coord
: {
8473 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8474 for (unsigned i
= 0; i
< coord
.size(); i
++)
8475 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8478 case nir_tex_src_bias
:
8479 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8482 case nir_tex_src_lod
: {
8483 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8485 if (val
&& val
->f32
<= 0.0) {
8488 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8493 case nir_tex_src_min_lod
:
8494 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8495 has_clamped_lod
= true;
8497 case nir_tex_src_comparator
:
8498 if (instr
->is_shadow
) {
8499 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8503 case nir_tex_src_offset
:
8504 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8505 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8508 case nir_tex_src_ddx
:
8509 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8512 case nir_tex_src_ddy
:
8513 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8516 case nir_tex_src_ms_index
:
8517 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8518 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8519 has_sample_index
= true;
8521 case nir_tex_src_texture_offset
:
8522 case nir_tex_src_sampler_offset
:
8528 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8529 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8531 if (instr
->op
== nir_texop_texture_samples
) {
8532 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8534 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8535 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8536 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8538 Operand default_sample
= Operand(1u);
8539 if (ctx
->options
->robust_buffer_access
) {
8540 /* Extract the second dword of the descriptor, if it's
8541 * all zero, then it's a null descriptor.
8543 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8544 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8545 default_sample
= Operand(is_non_null_descriptor
);
8548 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8549 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8550 samples
, default_sample
, bld
.scc(is_msaa
));
8554 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8555 aco_ptr
<Instruction
> tmp_instr
;
8556 Temp acc
, pack
= Temp();
8558 uint32_t pack_const
= 0;
8559 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8560 if (!const_offset
[i
])
8562 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8565 if (offset
.type() == RegType::sgpr
) {
8566 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8567 if (const_offset
[i
])
8570 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8571 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8574 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8577 if (pack
== Temp()) {
8580 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8584 if (pack_const
&& pack
!= Temp())
8585 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8587 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8588 if (const_offset
[i
])
8591 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8592 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8595 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8598 if (pack
== Temp()) {
8601 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8605 if (pack_const
&& pack
!= Temp())
8606 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8608 if (pack_const
&& pack
== Temp())
8609 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8610 else if (pack
== Temp())
8616 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8617 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8619 /* pack derivatives */
8620 if (has_ddx
|| has_ddy
) {
8621 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8622 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8623 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8624 derivs
= {ddx
, zero
, ddy
, zero
};
8626 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8627 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8628 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8629 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8634 if (instr
->coord_components
> 1 &&
8635 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8637 instr
->op
!= nir_texop_txf
)
8638 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8640 if (instr
->coord_components
> 2 &&
8641 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8642 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8643 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8644 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8646 instr
->op
!= nir_texop_txf
&&
8647 instr
->op
!= nir_texop_txf_ms
&&
8648 instr
->op
!= nir_texop_fragment_fetch
&&
8649 instr
->op
!= nir_texop_fragment_mask_fetch
)
8650 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8652 if (ctx
->options
->chip_class
== GFX9
&&
8653 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8654 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8655 assert(coords
.size() > 0 && coords
.size() < 3);
8657 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8658 Operand((uint32_t) 0) :
8659 Operand((uint32_t) 0x3f000000)));
8662 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8664 if (instr
->op
== nir_texop_samples_identical
)
8665 resource
= fmask_ptr
;
8667 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8668 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8669 instr
->op
!= nir_texop_txs
&&
8670 instr
->op
!= nir_texop_fragment_fetch
&&
8671 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8672 assert(has_sample_index
);
8673 Operand
op(sample_index
);
8674 if (sample_index_cv
)
8675 op
= Operand(sample_index_cv
->u32
);
8676 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8679 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8680 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8681 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8682 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8687 /* Build tex instruction */
8688 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8689 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8690 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8692 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8695 /* gather4 selects the component by dmask and always returns vec4 */
8696 if (instr
->op
== nir_texop_tg4
) {
8697 assert(instr
->dest
.ssa
.num_components
== 4);
8698 if (instr
->is_shadow
)
8701 dmask
= 1 << instr
->component
;
8702 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8703 tmp_dst
= bld
.tmp(v4
);
8704 } else if (instr
->op
== nir_texop_samples_identical
) {
8705 tmp_dst
= bld
.tmp(v1
);
8706 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8707 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8710 aco_ptr
<MIMG_instruction
> tex
;
8711 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8713 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8715 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8716 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8719 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8720 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8722 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8723 tex
->operands
[0] = Operand(resource
);
8724 tex
->operands
[1] = Operand(s4
); /* no sampler */
8725 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8726 if (ctx
->options
->chip_class
== GFX9
&&
8727 instr
->op
== nir_texop_txs
&&
8728 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8730 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8731 } else if (instr
->op
== nir_texop_query_levels
) {
8732 tex
->dmask
= 1 << 3;
8737 tex
->definitions
[0] = Definition(tmp_dst
);
8739 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8742 /* divide 3rd value by 6 by multiplying with magic number */
8743 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8744 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8745 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8746 assert(instr
->dest
.ssa
.num_components
== 3);
8747 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8748 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8749 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8750 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8755 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8759 Temp tg4_compare_cube_wa64
= Temp();
8761 if (tg4_integer_workarounds
) {
8762 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8763 tex
->operands
[0] = Operand(resource
);
8764 tex
->operands
[1] = Operand(s4
); /* no sampler */
8765 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8769 Temp size
= bld
.tmp(v2
);
8770 tex
->definitions
[0] = Definition(size
);
8771 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8772 emit_split_vector(ctx
, size
, size
.size());
8775 for (unsigned i
= 0; i
< 2; i
++) {
8776 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8777 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8778 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8779 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8782 Temp new_coords
[2] = {
8783 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8784 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8787 if (tg4_integer_cube_workaround
) {
8788 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8789 Temp desc
[resource
.size()];
8790 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8791 Format::PSEUDO
, 1, resource
.size())};
8792 split
->operands
[0] = Operand(resource
);
8793 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8794 desc
[i
] = bld
.tmp(s1
);
8795 split
->definitions
[i
] = Definition(desc
[i
]);
8797 ctx
->block
->instructions
.emplace_back(std::move(split
));
8799 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8800 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8801 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8804 if (stype
== GLSL_TYPE_UINT
) {
8805 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8806 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8807 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8808 bld
.scc(compare_cube_wa
));
8810 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8811 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8812 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8813 bld
.scc(compare_cube_wa
));
8815 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8816 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8818 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8820 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8821 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8822 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8824 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8825 Format::PSEUDO
, resource
.size(), 1)};
8826 for (unsigned i
= 0; i
< resource
.size(); i
++)
8827 vec
->operands
[i
] = Operand(desc
[i
]);
8828 resource
= bld
.tmp(resource
.regClass());
8829 vec
->definitions
[0] = Definition(resource
);
8830 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8832 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8833 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8834 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8835 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8837 coords
[0] = new_coords
[0];
8838 coords
[1] = new_coords
[1];
8841 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8842 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8844 assert(coords
.size() == 1);
8845 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8849 op
= aco_opcode::buffer_load_format_x
; break;
8851 op
= aco_opcode::buffer_load_format_xy
; break;
8853 op
= aco_opcode::buffer_load_format_xyz
; break;
8855 op
= aco_opcode::buffer_load_format_xyzw
; break;
8857 unreachable("Tex instruction loads more than 4 components.");
8860 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8861 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8864 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8866 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8867 mubuf
->operands
[0] = Operand(resource
);
8868 mubuf
->operands
[1] = Operand(coords
[0]);
8869 mubuf
->operands
[2] = Operand((uint32_t) 0);
8870 mubuf
->definitions
[0] = Definition(tmp_dst
);
8871 mubuf
->idxen
= true;
8872 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8874 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8878 /* gather MIMG address components */
8879 std::vector
<Temp
> args
;
8881 args
.emplace_back(offset
);
8883 args
.emplace_back(bias
);
8885 args
.emplace_back(compare
);
8887 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8889 args
.insert(args
.end(), coords
.begin(), coords
.end());
8890 if (has_sample_index
)
8891 args
.emplace_back(sample_index
);
8893 args
.emplace_back(lod
);
8894 if (has_clamped_lod
)
8895 args
.emplace_back(clamped_lod
);
8897 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8898 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8899 vec
->definitions
[0] = Definition(arg
);
8900 for (unsigned i
= 0; i
< args
.size(); i
++)
8901 vec
->operands
[i
] = Operand(args
[i
]);
8902 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8905 if (instr
->op
== nir_texop_txf
||
8906 instr
->op
== nir_texop_txf_ms
||
8907 instr
->op
== nir_texop_samples_identical
||
8908 instr
->op
== nir_texop_fragment_fetch
||
8909 instr
->op
== nir_texop_fragment_mask_fetch
) {
8910 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8911 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8912 tex
->operands
[0] = Operand(resource
);
8913 tex
->operands
[1] = Operand(s4
); /* no sampler */
8914 tex
->operands
[2] = Operand(arg
);
8919 tex
->definitions
[0] = Definition(tmp_dst
);
8920 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8922 if (instr
->op
== nir_texop_samples_identical
) {
8923 assert(dmask
== 1 && dst
.regClass() == v1
);
8924 assert(dst
.id() != tmp_dst
.id());
8926 Temp tmp
= bld
.tmp(bld
.lm
);
8927 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8928 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8931 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8936 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8937 aco_opcode opcode
= aco_opcode::image_sample
;
8938 if (has_offset
) { /* image_sample_*_o */
8939 if (has_clamped_lod
) {
8941 opcode
= aco_opcode::image_sample_c_cl_o
;
8943 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8945 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8947 opcode
= aco_opcode::image_sample_cl_o
;
8949 opcode
= aco_opcode::image_sample_d_cl_o
;
8951 opcode
= aco_opcode::image_sample_b_cl_o
;
8953 } else if (has_compare
) {
8954 opcode
= aco_opcode::image_sample_c_o
;
8956 opcode
= aco_opcode::image_sample_c_d_o
;
8958 opcode
= aco_opcode::image_sample_c_b_o
;
8960 opcode
= aco_opcode::image_sample_c_lz_o
;
8962 opcode
= aco_opcode::image_sample_c_l_o
;
8964 opcode
= aco_opcode::image_sample_o
;
8966 opcode
= aco_opcode::image_sample_d_o
;
8968 opcode
= aco_opcode::image_sample_b_o
;
8970 opcode
= aco_opcode::image_sample_lz_o
;
8972 opcode
= aco_opcode::image_sample_l_o
;
8974 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8976 opcode
= aco_opcode::image_sample_c_cl
;
8978 opcode
= aco_opcode::image_sample_c_d_cl
;
8980 opcode
= aco_opcode::image_sample_c_b_cl
;
8982 opcode
= aco_opcode::image_sample_cl
;
8984 opcode
= aco_opcode::image_sample_d_cl
;
8986 opcode
= aco_opcode::image_sample_b_cl
;
8988 } else { /* no offset */
8990 opcode
= aco_opcode::image_sample_c
;
8992 opcode
= aco_opcode::image_sample_c_d
;
8994 opcode
= aco_opcode::image_sample_c_b
;
8996 opcode
= aco_opcode::image_sample_c_lz
;
8998 opcode
= aco_opcode::image_sample_c_l
;
9000 opcode
= aco_opcode::image_sample
;
9002 opcode
= aco_opcode::image_sample_d
;
9004 opcode
= aco_opcode::image_sample_b
;
9006 opcode
= aco_opcode::image_sample_lz
;
9008 opcode
= aco_opcode::image_sample_l
;
9012 if (instr
->op
== nir_texop_tg4
) {
9013 if (has_offset
) { /* image_gather4_*_o */
9015 opcode
= aco_opcode::image_gather4_c_lz_o
;
9017 opcode
= aco_opcode::image_gather4_c_l_o
;
9019 opcode
= aco_opcode::image_gather4_c_b_o
;
9021 opcode
= aco_opcode::image_gather4_lz_o
;
9023 opcode
= aco_opcode::image_gather4_l_o
;
9025 opcode
= aco_opcode::image_gather4_b_o
;
9029 opcode
= aco_opcode::image_gather4_c_lz
;
9031 opcode
= aco_opcode::image_gather4_c_l
;
9033 opcode
= aco_opcode::image_gather4_c_b
;
9035 opcode
= aco_opcode::image_gather4_lz
;
9037 opcode
= aco_opcode::image_gather4_l
;
9039 opcode
= aco_opcode::image_gather4_b
;
9042 } else if (instr
->op
== nir_texop_lod
) {
9043 opcode
= aco_opcode::image_get_lod
;
9046 /* we don't need the bias, sample index, compare value or offset to be
9047 * computed in WQM but if the p_create_vector copies the coordinates, then it
9048 * needs to be in WQM */
9049 if (ctx
->stage
== fragment_fs
&&
9050 !has_derivs
&& !has_lod
&& !level_zero
&&
9051 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
9052 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
9053 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
9055 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
9056 tex
->operands
[0] = Operand(resource
);
9057 tex
->operands
[1] = Operand(sampler
);
9058 tex
->operands
[2] = Operand(arg
);
9062 tex
->definitions
[0] = Definition(tmp_dst
);
9063 ctx
->block
->instructions
.emplace_back(std::move(tex
));
9065 if (tg4_integer_cube_workaround
) {
9066 assert(tmp_dst
.id() != dst
.id());
9067 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
9069 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
9071 for (unsigned i
= 0; i
< dst
.size(); i
++) {
9072 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
9074 if (stype
== GLSL_TYPE_UINT
)
9075 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
9077 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
9078 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
9080 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
9081 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
9082 val
[0], val
[1], val
[2], val
[3]);
9084 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
9085 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
9090 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
9092 Temp tmp
= get_ssa_temp(ctx
, ssa
);
9093 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
9095 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
9096 if (ctx
->program
->wave_size
== 64)
9097 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
9099 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
9101 return Operand(tmp
);
9105 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9107 aco_ptr
<Pseudo_instruction
> phi
;
9108 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9109 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9111 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
9112 logical
|= ctx
->block
->kind
& block_kind_merge
;
9113 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9115 /* we want a sorted list of sources, since the predecessor list is also sorted */
9116 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9117 nir_foreach_phi_src(src
, instr
)
9118 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9120 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9121 unsigned num_operands
= 0;
9122 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9123 unsigned num_defined
= 0;
9124 unsigned cur_pred_idx
= 0;
9125 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9126 if (cur_pred_idx
< preds
.size()) {
9127 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9128 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9129 unsigned skipped
= 0;
9130 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9132 if (cur_pred_idx
+ skipped
< preds
.size()) {
9133 for (unsigned i
= 0; i
< skipped
; i
++)
9134 operands
[num_operands
++] = Operand(dst
.regClass());
9135 cur_pred_idx
+= skipped
;
9140 /* Handle missing predecessors at the end. This shouldn't happen with loop
9141 * headers and we can't ignore these sources for loop header phis. */
9142 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9145 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9146 operands
[num_operands
++] = op
;
9147 num_defined
+= !op
.isUndefined();
9149 /* handle block_kind_continue_or_break at loop exit blocks */
9150 while (cur_pred_idx
++ < preds
.size())
9151 operands
[num_operands
++] = Operand(dst
.regClass());
9153 /* If the loop ends with a break, still add a linear continue edge in case
9154 * that break is divergent or continue_or_break is used. We'll either remove
9155 * this operand later in visit_loop() if it's not necessary or replace the
9156 * undef with something correct. */
9157 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9158 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9159 nir_block
*last
= nir_loop_last_block(loop
);
9160 if (last
->successors
[0] != instr
->instr
.block
)
9161 operands
[num_operands
++] = Operand(RegClass());
9164 if (num_defined
== 0) {
9165 Builder
bld(ctx
->program
, ctx
->block
);
9166 if (dst
.regClass() == s1
) {
9167 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9168 } else if (dst
.regClass() == v1
) {
9169 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9171 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9172 for (unsigned i
= 0; i
< dst
.size(); i
++)
9173 vec
->operands
[i
] = Operand(0u);
9174 vec
->definitions
[0] = Definition(dst
);
9175 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9180 /* we can use a linear phi in some cases if one src is undef */
9181 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9182 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9184 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9185 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9186 assert(invert
->kind
& block_kind_invert
);
9188 unsigned then_block
= invert
->linear_preds
[0];
9190 Block
* insert_block
= NULL
;
9191 for (unsigned i
= 0; i
< num_operands
; i
++) {
9192 Operand op
= operands
[i
];
9193 if (op
.isUndefined())
9195 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9196 phi
->operands
[0] = op
;
9199 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9200 phi
->operands
[1] = Operand(dst
.regClass());
9201 phi
->definitions
[0] = Definition(dst
);
9202 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9206 /* try to scalarize vector phis */
9207 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9208 // TODO: scalarize linear phis on divergent ifs
9209 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9210 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9211 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9212 Operand src
= operands
[i
];
9213 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9214 can_scalarize
= false;
9216 if (can_scalarize
) {
9217 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9218 assert(dst
.size() % num_components
== 0);
9219 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9221 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9222 for (unsigned k
= 0; k
< num_components
; k
++) {
9223 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9224 for (unsigned i
= 0; i
< num_operands
; i
++) {
9225 Operand src
= operands
[i
];
9226 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9228 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9229 phi
->definitions
[0] = Definition(phi_dst
);
9230 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9231 new_vec
[k
] = phi_dst
;
9232 vec
->operands
[k
] = Operand(phi_dst
);
9234 vec
->definitions
[0] = Definition(dst
);
9235 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9236 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9241 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9242 for (unsigned i
= 0; i
< num_operands
; i
++)
9243 phi
->operands
[i
] = operands
[i
];
9244 phi
->definitions
[0] = Definition(dst
);
9245 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9249 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9251 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9253 assert(dst
.type() == RegType::sgpr
);
9255 if (dst
.size() == 1) {
9256 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9258 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9259 for (unsigned i
= 0; i
< dst
.size(); i
++)
9260 vec
->operands
[i
] = Operand(0u);
9261 vec
->definitions
[0] = Definition(dst
);
9262 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9266 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9268 Builder
bld(ctx
->program
, ctx
->block
);
9269 Block
*logical_target
;
9270 append_logical_end(ctx
->block
);
9271 unsigned idx
= ctx
->block
->index
;
9273 switch (instr
->type
) {
9274 case nir_jump_break
:
9275 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9276 add_logical_edge(idx
, logical_target
);
9277 ctx
->block
->kind
|= block_kind_break
;
9279 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9280 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9281 /* uniform break - directly jump out of the loop */
9282 ctx
->block
->kind
|= block_kind_uniform
;
9283 ctx
->cf_info
.has_branch
= true;
9284 bld
.branch(aco_opcode::p_branch
);
9285 add_linear_edge(idx
, logical_target
);
9288 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9289 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9291 case nir_jump_continue
:
9292 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9293 add_logical_edge(idx
, logical_target
);
9294 ctx
->block
->kind
|= block_kind_continue
;
9296 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9297 /* for potential uniform breaks after this continue,
9298 we must ensure that they are handled correctly */
9299 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9300 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9301 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9303 /* uniform continue - directly jump to the loop header */
9304 ctx
->block
->kind
|= block_kind_uniform
;
9305 ctx
->cf_info
.has_branch
= true;
9306 bld
.branch(aco_opcode::p_branch
);
9307 add_linear_edge(idx
, logical_target
);
9312 fprintf(stderr
, "Unknown NIR jump instr: ");
9313 nir_print_instr(&instr
->instr
, stderr
);
9314 fprintf(stderr
, "\n");
9318 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9319 ctx
->cf_info
.exec_potentially_empty_break
= true;
9320 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9323 /* remove critical edges from linear CFG */
9324 bld
.branch(aco_opcode::p_branch
);
9325 Block
* break_block
= ctx
->program
->create_and_insert_block();
9326 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9327 break_block
->kind
|= block_kind_uniform
;
9328 add_linear_edge(idx
, break_block
);
9329 /* the loop_header pointer might be invalidated by this point */
9330 if (instr
->type
== nir_jump_continue
)
9331 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9332 add_linear_edge(break_block
->index
, logical_target
);
9333 bld
.reset(break_block
);
9334 bld
.branch(aco_opcode::p_branch
);
9336 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9337 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9338 add_linear_edge(idx
, continue_block
);
9339 append_logical_start(continue_block
);
9340 ctx
->block
= continue_block
;
9344 void visit_block(isel_context
*ctx
, nir_block
*block
)
9346 nir_foreach_instr(instr
, block
) {
9347 switch (instr
->type
) {
9348 case nir_instr_type_alu
:
9349 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9351 case nir_instr_type_load_const
:
9352 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9354 case nir_instr_type_intrinsic
:
9355 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9357 case nir_instr_type_tex
:
9358 visit_tex(ctx
, nir_instr_as_tex(instr
));
9360 case nir_instr_type_phi
:
9361 visit_phi(ctx
, nir_instr_as_phi(instr
));
9363 case nir_instr_type_ssa_undef
:
9364 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9366 case nir_instr_type_deref
:
9368 case nir_instr_type_jump
:
9369 visit_jump(ctx
, nir_instr_as_jump(instr
));
9372 fprintf(stderr
, "Unknown NIR instr type: ");
9373 nir_print_instr(instr
, stderr
);
9374 fprintf(stderr
, "\n");
9379 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9380 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9385 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9386 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9388 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9389 RegClass rc
= vals
[0].regClass();
9391 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9393 unsigned next_pred
= 1;
9395 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9396 Block
& block
= ctx
->program
->blocks
[idx
];
9397 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9398 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9402 if (block
.kind
& block_kind_continue
) {
9403 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9408 bool all_same
= true;
9409 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9410 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9414 val
= vals
[block
.linear_preds
[0] - first
];
9416 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9417 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9418 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9419 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9420 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9421 phi
->definitions
[0] = Definition(val
.getTemp());
9422 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9424 vals
[idx
- first
] = val
;
9427 return vals
[last
- first
];
9430 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9432 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9433 append_logical_end(ctx
->block
);
9434 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9435 Builder
bld(ctx
->program
, ctx
->block
);
9436 bld
.branch(aco_opcode::p_branch
);
9437 unsigned loop_preheader_idx
= ctx
->block
->index
;
9439 Block loop_exit
= Block();
9440 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9441 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9443 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9444 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9445 loop_header
->kind
|= block_kind_loop_header
;
9446 add_edge(loop_preheader_idx
, loop_header
);
9447 ctx
->block
= loop_header
;
9449 /* emit loop body */
9450 unsigned loop_header_idx
= loop_header
->index
;
9451 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9452 append_logical_start(ctx
->block
);
9453 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9455 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9456 if (!ctx
->cf_info
.has_branch
) {
9457 append_logical_end(ctx
->block
);
9458 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9459 /* Discards can result in code running with an empty exec mask.
9460 * This would result in divergent breaks not ever being taken. As a
9461 * workaround, break the loop when the loop mask is empty instead of
9462 * always continuing. */
9463 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9464 unsigned block_idx
= ctx
->block
->index
;
9466 /* create helper blocks to avoid critical edges */
9467 Block
*break_block
= ctx
->program
->create_and_insert_block();
9468 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9469 break_block
->kind
= block_kind_uniform
;
9470 bld
.reset(break_block
);
9471 bld
.branch(aco_opcode::p_branch
);
9472 add_linear_edge(block_idx
, break_block
);
9473 add_linear_edge(break_block
->index
, &loop_exit
);
9475 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9476 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9477 continue_block
->kind
= block_kind_uniform
;
9478 bld
.reset(continue_block
);
9479 bld
.branch(aco_opcode::p_branch
);
9480 add_linear_edge(block_idx
, continue_block
);
9481 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9483 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9484 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9485 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9487 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9488 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9489 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9491 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9494 bld
.reset(ctx
->block
);
9495 bld
.branch(aco_opcode::p_branch
);
9498 /* Fixup phis in loop header from unreachable blocks.
9499 * has_branch/has_divergent_branch also indicates if the loop ends with a
9500 * break/continue instruction, but we don't emit those if unreachable=true */
9502 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9503 bool linear
= ctx
->cf_info
.has_branch
;
9504 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9505 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9506 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9507 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9508 /* the last operand should be the one that needs to be removed */
9509 instr
->operands
.pop_back();
9510 } else if (!is_phi(instr
)) {
9516 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9517 * and the previous one shouldn't both happen at once because a break in the
9518 * merge block would get CSE'd */
9519 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9520 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9521 Operand vals
[num_vals
];
9522 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9523 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9524 if (ctx
->cf_info
.has_branch
)
9525 instr
->operands
.pop_back();
9527 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9528 } else if (!is_phi(instr
)) {
9534 ctx
->cf_info
.has_branch
= false;
9536 // TODO: if the loop has not a single exit, we must add one °°
9537 /* emit loop successor block */
9538 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9539 append_logical_start(ctx
->block
);
9542 // TODO: check if it is beneficial to not branch on continues
9543 /* trim linear phis in loop header */
9544 for (auto&& instr
: loop_entry
->instructions
) {
9545 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9546 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9547 new_phi
->definitions
[0] = instr
->definitions
[0];
9548 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9549 new_phi
->operands
[i
] = instr
->operands
[i
];
9550 /* check that the remaining operands are all the same */
9551 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9552 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9553 instr
.swap(new_phi
);
9554 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9563 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9567 append_logical_end(ctx
->block
);
9568 ctx
->block
->kind
|= block_kind_branch
;
9570 /* branch to linear then block */
9571 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9572 aco_ptr
<Pseudo_branch_instruction
> branch
;
9573 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9574 branch
->operands
[0] = Operand(cond
);
9575 ctx
->block
->instructions
.push_back(std::move(branch
));
9577 ic
->BB_if_idx
= ctx
->block
->index
;
9578 ic
->BB_invert
= Block();
9579 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9580 /* Invert blocks are intentionally not marked as top level because they
9581 * are not part of the logical cfg. */
9582 ic
->BB_invert
.kind
|= block_kind_invert
;
9583 ic
->BB_endif
= Block();
9584 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9585 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9587 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9588 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9589 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9590 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9591 ctx
->cf_info
.parent_if
.is_divergent
= true;
9593 /* divergent branches use cbranch_execz */
9594 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9595 ctx
->cf_info
.exec_potentially_empty_break
= false;
9596 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9598 /** emit logical then block */
9599 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9600 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9601 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9602 ctx
->block
= BB_then_logical
;
9603 append_logical_start(BB_then_logical
);
9606 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9608 Block
*BB_then_logical
= ctx
->block
;
9609 append_logical_end(BB_then_logical
);
9610 /* branch from logical then block to invert block */
9611 aco_ptr
<Pseudo_branch_instruction
> branch
;
9612 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9613 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9614 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9615 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9616 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9617 BB_then_logical
->kind
|= block_kind_uniform
;
9618 assert(!ctx
->cf_info
.has_branch
);
9619 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9620 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9622 /** emit linear then block */
9623 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9624 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9625 BB_then_linear
->kind
|= block_kind_uniform
;
9626 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9627 /* branch from linear then block to invert block */
9628 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9629 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9630 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9632 /** emit invert merge block */
9633 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9634 ic
->invert_idx
= ctx
->block
->index
;
9636 /* branch to linear else block (skip else) */
9637 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9638 branch
->operands
[0] = Operand(ic
->cond
);
9639 ctx
->block
->instructions
.push_back(std::move(branch
));
9641 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9642 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9643 ic
->exec_potentially_empty_break_depth_old
=
9644 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9645 /* divergent branches use cbranch_execz */
9646 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9647 ctx
->cf_info
.exec_potentially_empty_break
= false;
9648 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9650 /** emit logical else block */
9651 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9652 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9653 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9654 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9655 ctx
->block
= BB_else_logical
;
9656 append_logical_start(BB_else_logical
);
9659 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9661 Block
*BB_else_logical
= ctx
->block
;
9662 append_logical_end(BB_else_logical
);
9664 /* branch from logical else block to endif block */
9665 aco_ptr
<Pseudo_branch_instruction
> branch
;
9666 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9667 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9668 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9669 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9670 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9671 BB_else_logical
->kind
|= block_kind_uniform
;
9673 assert(!ctx
->cf_info
.has_branch
);
9674 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9677 /** emit linear else block */
9678 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9679 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9680 BB_else_linear
->kind
|= block_kind_uniform
;
9681 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9683 /* branch from linear else block to endif block */
9684 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9685 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9686 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9689 /** emit endif merge block */
9690 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9691 append_logical_start(ctx
->block
);
9694 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9695 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9696 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9697 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9698 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9699 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9700 !ctx
->cf_info
.parent_if
.is_divergent
) {
9701 ctx
->cf_info
.exec_potentially_empty_break
= false;
9702 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9704 /* uniform control flow never has an empty exec-mask */
9705 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9706 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9707 ctx
->cf_info
.exec_potentially_empty_break
= false;
9708 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9712 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9714 assert(cond
.regClass() == s1
);
9716 append_logical_end(ctx
->block
);
9717 ctx
->block
->kind
|= block_kind_uniform
;
9719 aco_ptr
<Pseudo_branch_instruction
> branch
;
9720 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9721 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9722 branch
->operands
[0] = Operand(cond
);
9723 branch
->operands
[0].setFixed(scc
);
9724 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9726 ic
->BB_if_idx
= ctx
->block
->index
;
9727 ic
->BB_endif
= Block();
9728 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9729 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9731 ctx
->cf_info
.has_branch
= false;
9732 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9734 /** emit then block */
9735 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9736 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9737 add_edge(ic
->BB_if_idx
, BB_then
);
9738 append_logical_start(BB_then
);
9739 ctx
->block
= BB_then
;
9742 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9744 Block
*BB_then
= ctx
->block
;
9746 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9747 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9749 if (!ic
->uniform_has_then_branch
) {
9750 append_logical_end(BB_then
);
9751 /* branch from then block to endif block */
9752 aco_ptr
<Pseudo_branch_instruction
> branch
;
9753 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9754 BB_then
->instructions
.emplace_back(std::move(branch
));
9755 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9756 if (!ic
->then_branch_divergent
)
9757 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9758 BB_then
->kind
|= block_kind_uniform
;
9761 ctx
->cf_info
.has_branch
= false;
9762 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9764 /** emit else block */
9765 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9766 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9767 add_edge(ic
->BB_if_idx
, BB_else
);
9768 append_logical_start(BB_else
);
9769 ctx
->block
= BB_else
;
9772 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9774 Block
*BB_else
= ctx
->block
;
9776 if (!ctx
->cf_info
.has_branch
) {
9777 append_logical_end(BB_else
);
9778 /* branch from then block to endif block */
9779 aco_ptr
<Pseudo_branch_instruction
> branch
;
9780 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9781 BB_else
->instructions
.emplace_back(std::move(branch
));
9782 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9783 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9784 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9785 BB_else
->kind
|= block_kind_uniform
;
9788 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9789 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9791 /** emit endif merge block */
9792 if (!ctx
->cf_info
.has_branch
) {
9793 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9794 append_logical_start(ctx
->block
);
9798 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9800 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9801 Builder
bld(ctx
->program
, ctx
->block
);
9802 aco_ptr
<Pseudo_branch_instruction
> branch
;
9805 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9807 * Uniform conditionals are represented in the following way*) :
9809 * The linear and logical CFG:
9812 * BB_THEN (logical) BB_ELSE (logical)
9816 * *) Exceptions may be due to break and continue statements within loops
9817 * If a break/continue happens within uniform control flow, it branches
9818 * to the loop exit/entry block. Otherwise, it branches to the next
9822 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9823 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9824 cond
= bool_to_scalar_condition(ctx
, cond
);
9826 begin_uniform_if_then(ctx
, &ic
, cond
);
9827 visit_cf_list(ctx
, &if_stmt
->then_list
);
9829 begin_uniform_if_else(ctx
, &ic
);
9830 visit_cf_list(ctx
, &if_stmt
->else_list
);
9832 end_uniform_if(ctx
, &ic
);
9833 } else { /* non-uniform condition */
9835 * To maintain a logical and linear CFG without critical edges,
9836 * non-uniform conditionals are represented in the following way*) :
9841 * BB_THEN (logical) BB_THEN (linear)
9843 * BB_INVERT (linear)
9845 * BB_ELSE (logical) BB_ELSE (linear)
9852 * BB_THEN (logical) BB_ELSE (logical)
9856 * *) Exceptions may be due to break and continue statements within loops
9859 begin_divergent_if_then(ctx
, &ic
, cond
);
9860 visit_cf_list(ctx
, &if_stmt
->then_list
);
9862 begin_divergent_if_else(ctx
, &ic
);
9863 visit_cf_list(ctx
, &if_stmt
->else_list
);
9865 end_divergent_if(ctx
, &ic
);
9868 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9871 static bool visit_cf_list(isel_context
*ctx
,
9872 struct exec_list
*list
)
9874 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9875 switch (node
->type
) {
9876 case nir_cf_node_block
:
9877 visit_block(ctx
, nir_cf_node_as_block(node
));
9879 case nir_cf_node_if
:
9880 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9883 case nir_cf_node_loop
:
9884 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9887 unreachable("unimplemented cf list type");
9893 static void create_null_export(isel_context
*ctx
)
9895 /* Some shader stages always need to have exports.
9896 * So when there is none, we need to add a null export.
9899 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9900 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9901 Builder
bld(ctx
->program
, ctx
->block
);
9902 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9903 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9906 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9908 assert(ctx
->stage
== vertex_vs
||
9909 ctx
->stage
== tess_eval_vs
||
9910 ctx
->stage
== gs_copy_vs
||
9911 ctx
->stage
== ngg_vertex_gs
||
9912 ctx
->stage
== ngg_tess_eval_gs
);
9914 int offset
= (ctx
->stage
& sw_tes
)
9915 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9916 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9917 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9918 if (!is_pos
&& !mask
)
9920 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9922 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9923 exp
->enabled_mask
= mask
;
9924 for (unsigned i
= 0; i
< 4; ++i
) {
9925 if (mask
& (1 << i
))
9926 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9928 exp
->operands
[i
] = Operand(v1
);
9930 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9931 * Setting valid_mask=1 prevents it and has no other effect.
9933 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9935 exp
->compressed
= false;
9937 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9939 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9940 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9945 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9947 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9948 exp
->enabled_mask
= 0;
9949 for (unsigned i
= 0; i
< 4; ++i
)
9950 exp
->operands
[i
] = Operand(v1
);
9951 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9952 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9953 exp
->enabled_mask
|= 0x1;
9955 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9956 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9957 exp
->enabled_mask
|= 0x4;
9959 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9960 if (ctx
->options
->chip_class
< GFX9
) {
9961 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9962 exp
->enabled_mask
|= 0x8;
9964 Builder
bld(ctx
->program
, ctx
->block
);
9966 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9967 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9968 if (exp
->operands
[2].isTemp())
9969 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9971 exp
->operands
[2] = Operand(out
);
9972 exp
->enabled_mask
|= 0x4;
9975 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9977 exp
->compressed
= false;
9978 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9979 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9982 static void create_export_phis(isel_context
*ctx
)
9984 /* Used when exports are needed, but the output temps are defined in a preceding block.
9985 * This function will set up phis in order to access the outputs in the next block.
9988 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9989 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9990 ctx
->block
->instructions
.pop_back();
9992 Builder
bld(ctx
->program
, ctx
->block
);
9994 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9995 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9996 for (unsigned i
= 0; i
< 4; ++i
) {
9997 if (!(mask
& (1 << i
)))
10000 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
10001 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
10002 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
10006 bld
.insert(std::move(logical_start
));
10009 static void create_vs_exports(isel_context
*ctx
)
10011 assert(ctx
->stage
== vertex_vs
||
10012 ctx
->stage
== tess_eval_vs
||
10013 ctx
->stage
== gs_copy_vs
||
10014 ctx
->stage
== ngg_vertex_gs
||
10015 ctx
->stage
== ngg_tess_eval_gs
);
10017 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
10018 ? &ctx
->program
->info
->tes
.outinfo
10019 : &ctx
->program
->info
->vs
.outinfo
;
10021 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
10022 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10023 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
10026 if (ctx
->options
->key
.has_multiview_view_index
) {
10027 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
10028 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
10031 /* the order these position exports are created is important */
10033 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
10034 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
10035 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
10036 exported_pos
= true;
10038 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10039 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
10040 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10041 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
10043 if (ctx
->export_clip_dists
) {
10044 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10045 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
10046 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10047 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
10050 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10051 if (i
< VARYING_SLOT_VAR0
&&
10052 i
!= VARYING_SLOT_LAYER
&&
10053 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
10054 i
!= VARYING_SLOT_VIEWPORT
)
10057 export_vs_varying(ctx
, i
, false, NULL
);
10061 create_null_export(ctx
);
10064 static bool export_fs_mrt_z(isel_context
*ctx
)
10066 Builder
bld(ctx
->program
, ctx
->block
);
10067 unsigned enabled_channels
= 0;
10068 bool compr
= false;
10071 for (unsigned i
= 0; i
< 4; ++i
) {
10072 values
[i
] = Operand(v1
);
10075 /* Both stencil and sample mask only need 16-bits. */
10076 if (!ctx
->program
->info
->ps
.writes_z
&&
10077 (ctx
->program
->info
->ps
.writes_stencil
||
10078 ctx
->program
->info
->ps
.writes_sample_mask
)) {
10079 compr
= true; /* COMPR flag */
10081 if (ctx
->program
->info
->ps
.writes_stencil
) {
10082 /* Stencil should be in X[23:16]. */
10083 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10084 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
10085 enabled_channels
|= 0x3;
10088 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10089 /* SampleMask should be in Y[15:0]. */
10090 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10091 enabled_channels
|= 0xc;
10094 if (ctx
->program
->info
->ps
.writes_z
) {
10095 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
10096 enabled_channels
|= 0x1;
10099 if (ctx
->program
->info
->ps
.writes_stencil
) {
10100 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10101 enabled_channels
|= 0x2;
10104 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10105 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10106 enabled_channels
|= 0x4;
10110 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10111 * writemask component.
10113 if (ctx
->options
->chip_class
== GFX6
&&
10114 ctx
->options
->family
!= CHIP_OLAND
&&
10115 ctx
->options
->family
!= CHIP_HAINAN
) {
10116 enabled_channels
|= 0x1;
10119 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10120 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10125 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10127 Builder
bld(ctx
->program
, ctx
->block
);
10128 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10131 for (unsigned i
= 0; i
< 4; ++i
) {
10132 if (write_mask
& (1 << i
)) {
10133 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10135 values
[i
] = Operand(v1
);
10139 unsigned target
, col_format
;
10140 unsigned enabled_channels
= 0;
10141 aco_opcode compr_op
= (aco_opcode
)0;
10143 slot
-= FRAG_RESULT_DATA0
;
10144 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10145 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10147 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10148 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10149 bool is_16bit
= values
[0].regClass() == v2b
;
10151 switch (col_format
)
10153 case V_028714_SPI_SHADER_ZERO
:
10154 enabled_channels
= 0; /* writemask */
10155 target
= V_008DFC_SQ_EXP_NULL
;
10158 case V_028714_SPI_SHADER_32_R
:
10159 enabled_channels
= 1;
10162 case V_028714_SPI_SHADER_32_GR
:
10163 enabled_channels
= 0x3;
10166 case V_028714_SPI_SHADER_32_AR
:
10167 if (ctx
->options
->chip_class
>= GFX10
) {
10168 /* Special case: on GFX10, the outputs are different for 32_AR */
10169 enabled_channels
= 0x3;
10170 values
[1] = values
[3];
10171 values
[3] = Operand(v1
);
10173 enabled_channels
= 0x9;
10177 case V_028714_SPI_SHADER_FP16_ABGR
:
10178 enabled_channels
= 0x5;
10179 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10181 if (ctx
->options
->chip_class
>= GFX9
) {
10182 /* Pack the FP16 values together instead of converting them to
10183 * FP32 and back to FP16.
10184 * TODO: use p_create_vector and let the compiler optimizes.
10186 compr_op
= aco_opcode::v_pack_b32_f16
;
10188 for (unsigned i
= 0; i
< 4; i
++) {
10189 if ((write_mask
>> i
) & 1)
10190 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10196 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10197 enabled_channels
= 0x5;
10198 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10199 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10201 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10205 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10206 enabled_channels
= 0x5;
10207 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10208 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10210 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10214 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10215 enabled_channels
= 0x5;
10216 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10217 if (is_int8
|| is_int10
) {
10219 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10220 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10222 for (unsigned i
= 0; i
< 4; i
++) {
10223 if ((write_mask
>> i
) & 1) {
10224 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10225 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10229 } else if (is_16bit
) {
10230 for (unsigned i
= 0; i
< 4; i
++) {
10231 if ((write_mask
>> i
) & 1) {
10232 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10233 values
[i
] = Operand(tmp
);
10240 case V_028714_SPI_SHADER_SINT16_ABGR
:
10241 enabled_channels
= 0x5;
10242 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10243 if (is_int8
|| is_int10
) {
10245 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10246 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10247 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10248 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10250 for (unsigned i
= 0; i
< 4; i
++) {
10251 if ((write_mask
>> i
) & 1) {
10252 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10253 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10255 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10256 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10260 } else if (is_16bit
) {
10261 for (unsigned i
= 0; i
< 4; i
++) {
10262 if ((write_mask
>> i
) & 1) {
10263 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10264 values
[i
] = Operand(tmp
);
10270 case V_028714_SPI_SHADER_32_ABGR
:
10271 enabled_channels
= 0xF;
10278 if (target
== V_008DFC_SQ_EXP_NULL
)
10281 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10282 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10284 (col_format
== V_028714_SPI_SHADER_32_R
||
10285 col_format
== V_028714_SPI_SHADER_32_GR
||
10286 col_format
== V_028714_SPI_SHADER_32_AR
||
10287 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10288 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10289 for (int i
= 0; i
< 4; i
++) {
10290 if (!(write_mask
& (1 << i
)))
10293 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10294 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10295 bld
.copy(bld
.def(v1
), Operand(3u)));
10296 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10297 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10301 if ((bool) compr_op
) {
10302 for (int i
= 0; i
< 2; i
++) {
10303 /* check if at least one of the values to be compressed is enabled */
10304 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10306 enabled_channels
|= enabled
<< (i
*2);
10307 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10308 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10309 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10311 values
[i
] = Operand(v1
);
10314 values
[2] = Operand(v1
);
10315 values
[3] = Operand(v1
);
10317 for (int i
= 0; i
< 4; i
++)
10318 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10321 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10322 enabled_channels
, target
, (bool) compr_op
);
10326 static void create_fs_exports(isel_context
*ctx
)
10328 bool exported
= false;
10330 /* Export depth, stencil and sample mask. */
10331 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10332 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10333 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10334 exported
|= export_fs_mrt_z(ctx
);
10336 /* Export all color render targets. */
10337 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10338 if (ctx
->outputs
.mask
[i
])
10339 exported
|= export_fs_mrt_color(ctx
, i
);
10342 create_null_export(ctx
);
10345 static void create_workgroup_barrier(Builder
& bld
)
10347 bld
.barrier(aco_opcode::p_barrier
,
10348 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10352 static void write_tcs_tess_factors(isel_context
*ctx
)
10354 unsigned outer_comps
;
10355 unsigned inner_comps
;
10357 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10374 Builder
bld(ctx
->program
, ctx
->block
);
10376 create_workgroup_barrier(bld
);
10378 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10379 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10381 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10382 if_context ic_invocation_id_is_zero
;
10383 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10384 bld
.reset(ctx
->block
);
10386 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10388 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10389 unsigned stride
= inner_comps
+ outer_comps
;
10390 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10394 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10396 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10398 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10399 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10400 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10402 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10403 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10405 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10406 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10407 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10408 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10411 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10412 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10413 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10414 unsigned tf_const_offset
= 0;
10416 if (ctx
->program
->chip_class
<= GFX8
) {
10417 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10418 if_context ic_rel_patch_id_is_zero
;
10419 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10420 bld
.reset(ctx
->block
);
10422 /* Store the dynamic HS control word. */
10423 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10424 bld
.mubuf(aco_opcode::buffer_store_dword
,
10425 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10426 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10427 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10428 tf_const_offset
+= 4;
10430 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10431 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10432 bld
.reset(ctx
->block
);
10435 assert(stride
== 2 || stride
== 4 || stride
== 6);
10436 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10437 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10439 /* Store to offchip for TES to read - only if TES reads them */
10440 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10441 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10442 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10444 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10445 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10447 if (likely(inner_comps
)) {
10448 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10449 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10453 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10454 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10457 static void emit_stream_output(isel_context
*ctx
,
10458 Temp
const *so_buffers
,
10459 Temp
const *so_write_offset
,
10460 const struct radv_stream_output
*output
)
10462 unsigned num_comps
= util_bitcount(output
->component_mask
);
10463 unsigned writemask
= (1 << num_comps
) - 1;
10464 unsigned loc
= output
->location
;
10465 unsigned buf
= output
->buffer
;
10467 assert(num_comps
&& num_comps
<= 4);
10468 if (!num_comps
|| num_comps
> 4)
10471 unsigned start
= ffs(output
->component_mask
) - 1;
10474 bool all_undef
= true;
10475 assert(ctx
->stage
& hw_vs
);
10476 for (unsigned i
= 0; i
< num_comps
; i
++) {
10477 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10478 all_undef
= all_undef
&& !out
[i
].id();
10483 while (writemask
) {
10485 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10486 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10487 /* GFX6 doesn't support storing vec3, split it. */
10488 writemask
|= 1u << (start
+ 2);
10492 unsigned offset
= output
->offset
+ start
* 4;
10494 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10495 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10496 for (int i
= 0; i
< count
; ++i
)
10497 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10498 vec
->definitions
[0] = Definition(write_data
);
10499 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10504 opcode
= aco_opcode::buffer_store_dword
;
10507 opcode
= aco_opcode::buffer_store_dwordx2
;
10510 opcode
= aco_opcode::buffer_store_dwordx3
;
10513 opcode
= aco_opcode::buffer_store_dwordx4
;
10516 unreachable("Unsupported dword count.");
10519 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10520 store
->operands
[0] = Operand(so_buffers
[buf
]);
10521 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10522 store
->operands
[2] = Operand((uint32_t) 0);
10523 store
->operands
[3] = Operand(write_data
);
10524 if (offset
> 4095) {
10525 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10526 Builder
bld(ctx
->program
, ctx
->block
);
10527 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10529 store
->offset
= offset
;
10531 store
->offen
= true;
10533 store
->dlc
= false;
10535 ctx
->block
->instructions
.emplace_back(std::move(store
));
10539 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10541 Builder
bld(ctx
->program
, ctx
->block
);
10543 Temp so_buffers
[4];
10544 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10545 for (unsigned i
= 0; i
< 4; i
++) {
10546 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10550 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10551 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10554 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10555 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10557 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10559 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10562 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10564 bld
.reset(ctx
->block
);
10566 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10568 Temp so_write_offset
[4];
10570 for (unsigned i
= 0; i
< 4; i
++) {
10571 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10576 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10577 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10578 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10579 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10581 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10583 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10584 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10585 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10586 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10590 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10591 struct radv_stream_output
*output
=
10592 &ctx
->program
->info
->so
.outputs
[i
];
10593 if (stream
!= output
->stream
)
10596 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10599 begin_divergent_if_else(ctx
, &ic
);
10600 end_divergent_if(ctx
, &ic
);
10603 } /* end namespace */
10605 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10607 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10608 Builder
bld(ctx
->program
, ctx
->block
);
10609 constexpr unsigned hs_idx
= 1u;
10610 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10611 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10612 Operand((8u << 16) | (hs_idx
* 8u)));
10613 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10615 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10617 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10618 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10619 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10620 ls_has_nonzero_hs_threads
);
10621 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10622 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10623 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10624 ls_has_nonzero_hs_threads
);
10625 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10626 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10627 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10628 ls_has_nonzero_hs_threads
);
10630 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10631 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10632 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10635 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10637 /* Split all arguments except for the first (ring_offsets) and the last
10638 * (exec) so that the dead channels don't stay live throughout the program.
10640 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10641 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10642 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10643 startpgm
->definitions
[i
].regClass().size());
10648 void handle_bc_optimize(isel_context
*ctx
)
10650 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10651 Builder
bld(ctx
->program
, ctx
->block
);
10652 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10653 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10654 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10655 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10656 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10657 if (uses_center
&& uses_centroid
) {
10658 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10659 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10661 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10663 for (unsigned i
= 0; i
< 2; i
++) {
10664 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10665 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10666 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10667 persp_centroid
, persp_center
, sel
);
10669 ctx
->persp_centroid
= bld
.tmp(v2
);
10670 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10671 Operand(new_coord
[0]), Operand(new_coord
[1]));
10672 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10675 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10677 for (unsigned i
= 0; i
< 2; i
++) {
10678 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10679 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10680 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10681 linear_centroid
, linear_center
, sel
);
10683 ctx
->linear_centroid
= bld
.tmp(v2
);
10684 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10685 Operand(new_coord
[0]), Operand(new_coord
[1]));
10686 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10691 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10693 Program
*program
= ctx
->program
;
10695 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10697 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10698 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10699 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10700 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10701 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10703 program
->next_fp_mode
.must_flush_denorms32
=
10704 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10705 program
->next_fp_mode
.must_flush_denorms16_64
=
10706 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10707 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10709 program
->next_fp_mode
.care_about_round32
=
10710 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10712 program
->next_fp_mode
.care_about_round16_64
=
10713 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10714 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10716 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10717 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10718 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10719 program
->next_fp_mode
.denorm16_64
= 0;
10721 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10723 /* preserving fp32 denorms is expensive, so only do it if asked */
10724 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10725 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10727 program
->next_fp_mode
.denorm32
= 0;
10729 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10730 program
->next_fp_mode
.round32
= fp_round_tz
;
10732 program
->next_fp_mode
.round32
= fp_round_ne
;
10734 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10735 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10737 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10739 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10742 void cleanup_cfg(Program
*program
)
10744 /* create linear_succs/logical_succs */
10745 for (Block
& BB
: program
->blocks
) {
10746 for (unsigned idx
: BB
.linear_preds
)
10747 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10748 for (unsigned idx
: BB
.logical_preds
)
10749 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10753 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10755 Builder
bld(ctx
->program
, ctx
->block
);
10757 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10758 Temp count
= i
== 0
10759 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10760 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10761 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10763 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10766 if (ctx
->program
->wave_size
== 64) {
10767 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10768 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10769 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10771 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10772 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10778 bool ngg_early_prim_export(isel_context
*ctx
)
10780 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10784 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10786 Builder
bld(ctx
->program
, ctx
->block
);
10788 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10789 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10791 /* Get the id of the current wave within the threadgroup (workgroup) */
10792 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10793 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10795 /* Execute the following code only on the first wave (wave id 0),
10796 * use the SCC def to tell if the wave id is zero or not.
10798 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10800 begin_uniform_if_then(ctx
, &ic
, cond
);
10801 begin_uniform_if_else(ctx
, &ic
);
10802 bld
.reset(ctx
->block
);
10804 /* Number of vertices output by VS/TES */
10805 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10806 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10807 /* Number of primitives output by VS/TES */
10808 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10809 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10811 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10812 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10813 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10815 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10816 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10818 end_uniform_if(ctx
, &ic
);
10820 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10821 bld
.reset(ctx
->block
);
10822 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10825 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10827 Builder
bld(ctx
->program
, ctx
->block
);
10829 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10830 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10833 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10836 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10837 assert(vtxindex
[i
].id());
10840 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10844 /* The initial edge flag is always false in tess eval shaders. */
10845 if (ctx
->stage
== ngg_vertex_gs
) {
10846 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10847 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10851 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10856 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10858 Builder
bld(ctx
->program
, ctx
->block
);
10859 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10861 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10862 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10863 false /* compressed */, true/* done */, false /* valid mask */);
10866 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10868 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10869 * These must always come before VS exports.
10871 * It is recommended to do these as early as possible. They can be at the beginning when
10872 * there is no SW GS and the shader doesn't write edge flags.
10876 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10877 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10879 Builder
bld(ctx
->program
, ctx
->block
);
10880 constexpr unsigned max_vertices_per_primitive
= 3;
10881 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10883 if (ctx
->stage
== ngg_vertex_gs
) {
10884 /* TODO: optimize for points & lines */
10885 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10886 if (ctx
->shader
->info
.tess
.point_mode
)
10887 num_vertices_per_primitive
= 1;
10888 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10889 num_vertices_per_primitive
= 2;
10891 unreachable("Unsupported NGG shader stage");
10894 Temp vtxindex
[max_vertices_per_primitive
];
10895 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10896 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10897 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10898 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10899 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10900 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10901 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10902 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10904 /* Export primitive data to the index buffer. */
10905 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10907 /* Export primitive ID. */
10908 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10909 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10910 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10911 Temp provoking_vtx_index
= vtxindex
[0];
10912 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10914 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10917 begin_divergent_if_else(ctx
, &ic
);
10918 end_divergent_if(ctx
, &ic
);
10921 void ngg_emit_nogs_output(isel_context
*ctx
)
10923 /* Emits NGG GS output, for stages that don't have SW GS. */
10926 Builder
bld(ctx
->program
, ctx
->block
);
10927 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10929 /* NGG streamout is currently disabled by default. */
10930 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10932 if (late_prim_export
) {
10933 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10934 create_export_phis(ctx
);
10935 /* Do what we need to do in the GS threads. */
10936 ngg_emit_nogs_gsthreads(ctx
);
10938 /* What comes next should be executed on ES threads. */
10939 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10940 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10941 bld
.reset(ctx
->block
);
10944 /* Export VS outputs */
10945 ctx
->block
->kind
|= block_kind_export_end
;
10946 create_vs_exports(ctx
);
10948 /* Export primitive ID */
10949 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10952 if (ctx
->stage
== ngg_vertex_gs
) {
10953 /* Wait for GS threads to store primitive ID in LDS. */
10954 create_workgroup_barrier(bld
);
10956 /* Calculate LDS address where the GS threads stored the primitive ID. */
10957 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10958 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10959 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10960 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10961 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10962 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10964 /* Load primitive ID from LDS. */
10965 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10966 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10967 /* TES: Just use the patch ID as the primitive ID. */
10968 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10970 unreachable("unsupported NGG shader stage.");
10973 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10974 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10976 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10979 if (late_prim_export
) {
10980 begin_divergent_if_else(ctx
, &ic
);
10981 end_divergent_if(ctx
, &ic
);
10982 bld
.reset(ctx
->block
);
10986 void select_program(Program
*program
,
10987 unsigned shader_count
,
10988 struct nir_shader
*const *shaders
,
10989 ac_shader_config
* config
,
10990 struct radv_shader_args
*args
)
10992 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10993 if_context ic_merged_wave_info
;
10994 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10996 for (unsigned i
= 0; i
< shader_count
; i
++) {
10997 nir_shader
*nir
= shaders
[i
];
10998 init_context(&ctx
, nir
);
11000 setup_fp_mode(&ctx
, nir
);
11003 /* needs to be after init_context() for FS */
11004 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
11005 append_logical_start(ctx
.block
);
11007 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
11008 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
11010 split_arguments(&ctx
, startpgm
);
11014 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
11016 if (ngg_early_prim_export(&ctx
))
11017 ngg_emit_nogs_gsthreads(&ctx
);
11020 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
11021 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
11022 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
11023 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
11024 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
11025 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
11026 ctx
.stage
== tess_eval_geometry_gs
));
11028 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
11029 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
11030 if (check_merged_wave_info
) {
11031 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
11032 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
11036 Builder
bld(ctx
.program
, ctx
.block
);
11038 create_workgroup_barrier(bld
);
11040 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
11041 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
11043 } else if (ctx
.stage
== geometry_gs
)
11044 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
11046 if (ctx
.stage
== fragment_fs
)
11047 handle_bc_optimize(&ctx
);
11049 visit_cf_list(&ctx
, &func
->body
);
11051 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
11052 emit_streamout(&ctx
, 0);
11054 if (ctx
.stage
& hw_vs
) {
11055 create_vs_exports(&ctx
);
11056 ctx
.block
->kind
|= block_kind_export_end
;
11057 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
11058 ngg_emit_nogs_output(&ctx
);
11059 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
11060 Builder
bld(ctx
.program
, ctx
.block
);
11061 bld
.barrier(aco_opcode::p_barrier
,
11062 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
11063 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
11064 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
11065 write_tcs_tess_factors(&ctx
);
11068 if (ctx
.stage
== fragment_fs
) {
11069 create_fs_exports(&ctx
);
11070 ctx
.block
->kind
|= block_kind_export_end
;
11073 if (endif_merged_wave_info
) {
11074 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
11075 end_divergent_if(&ctx
, &ic_merged_wave_info
);
11078 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
11079 ngg_emit_nogs_output(&ctx
);
11081 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
11082 /* Outputs of the previous stage are inputs to the next stage */
11083 ctx
.inputs
= ctx
.outputs
;
11084 ctx
.outputs
= shader_io_state();
11088 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11090 append_logical_end(ctx
.block
);
11091 ctx
.block
->kind
|= block_kind_uniform
;
11092 Builder
bld(ctx
.program
, ctx
.block
);
11093 if (ctx
.program
->wb_smem_l1_on_end
)
11094 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
11095 bld
.sopp(aco_opcode::s_endpgm
);
11097 cleanup_cfg(program
);
11100 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
11101 ac_shader_config
* config
,
11102 struct radv_shader_args
*args
)
11104 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
11106 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11108 add_startpgm(&ctx
);
11109 append_logical_start(ctx
.block
);
11111 Builder
bld(ctx
.program
, ctx
.block
);
11113 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11115 Operand
stream_id(0u);
11116 if (args
->shader_info
->so
.num_outputs
)
11117 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11118 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11120 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11122 std::stack
<Block
> endif_blocks
;
11124 for (unsigned stream
= 0; stream
< 4; stream
++) {
11125 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11128 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11129 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11132 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11134 unsigned BB_if_idx
= ctx
.block
->index
;
11135 Block BB_endif
= Block();
11136 if (!stream_id
.isConstant()) {
11138 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11139 append_logical_end(ctx
.block
);
11140 ctx
.block
->kind
|= block_kind_uniform
;
11141 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11143 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11145 ctx
.block
= ctx
.program
->create_and_insert_block();
11146 add_edge(BB_if_idx
, ctx
.block
);
11147 bld
.reset(ctx
.block
);
11148 append_logical_start(ctx
.block
);
11151 unsigned offset
= 0;
11152 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11153 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11156 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11157 unsigned length
= util_last_bit(output_usage_mask
);
11158 for (unsigned j
= 0; j
< length
; ++j
) {
11159 if (!(output_usage_mask
& (1 << j
)))
11162 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11163 Temp voffset
= vtx_offset
;
11164 if (const_offset
>= 4096u) {
11165 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11166 const_offset
%= 4096u;
11169 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11170 mubuf
->definitions
[0] = bld
.def(v1
);
11171 mubuf
->operands
[0] = Operand(gsvs_ring
);
11172 mubuf
->operands
[1] = Operand(voffset
);
11173 mubuf
->operands
[2] = Operand(0u);
11174 mubuf
->offen
= true;
11175 mubuf
->offset
= const_offset
;
11178 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11180 ctx
.outputs
.mask
[i
] |= 1 << j
;
11181 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11183 bld
.insert(std::move(mubuf
));
11189 if (args
->shader_info
->so
.num_outputs
) {
11190 emit_streamout(&ctx
, stream
);
11191 bld
.reset(ctx
.block
);
11195 create_vs_exports(&ctx
);
11196 ctx
.block
->kind
|= block_kind_export_end
;
11199 if (!stream_id
.isConstant()) {
11200 append_logical_end(ctx
.block
);
11202 /* branch from then block to endif block */
11203 bld
.branch(aco_opcode::p_branch
);
11204 add_edge(ctx
.block
->index
, &BB_endif
);
11205 ctx
.block
->kind
|= block_kind_uniform
;
11207 /* emit else block */
11208 ctx
.block
= ctx
.program
->create_and_insert_block();
11209 add_edge(BB_if_idx
, ctx
.block
);
11210 bld
.reset(ctx
.block
);
11211 append_logical_start(ctx
.block
);
11213 endif_blocks
.push(std::move(BB_endif
));
11217 while (!endif_blocks
.empty()) {
11218 Block BB_endif
= std::move(endif_blocks
.top());
11219 endif_blocks
.pop();
11221 Block
*BB_else
= ctx
.block
;
11223 append_logical_end(BB_else
);
11224 /* branch from else block to endif block */
11225 bld
.branch(aco_opcode::p_branch
);
11226 add_edge(BB_else
->index
, &BB_endif
);
11227 BB_else
->kind
|= block_kind_uniform
;
11229 /** emit endif merge block */
11230 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11231 bld
.reset(ctx
.block
);
11232 append_logical_start(ctx
.block
);
11235 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11237 append_logical_end(ctx
.block
);
11238 ctx
.block
->kind
|= block_kind_uniform
;
11239 bld
.sopp(aco_opcode::s_endpgm
);
11241 cleanup_cfg(program
);