2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 #define isel_err(...) _isel_err(ctx, __FILE__, __LINE__, __VA_ARGS__)
43 static void _isel_err(isel_context
*ctx
, const char *file
, unsigned line
,
44 const nir_instr
*instr
, const char *msg
)
48 FILE *memf
= open_memstream(&out
, &outsize
);
50 fprintf(memf
, "%s: ", msg
);
51 nir_print_instr(instr
, memf
);
54 _aco_err(ctx
->program
, file
, line
, out
);
58 class loop_info_RAII
{
60 unsigned header_idx_old
;
62 bool divergent_cont_old
;
63 bool divergent_branch_old
;
64 bool divergent_if_old
;
67 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
69 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
70 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
71 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
72 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
75 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
76 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
77 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
78 ctx
->cf_info
.parent_if
.is_divergent
= false;
79 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
84 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
85 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
86 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
87 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
88 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
89 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
90 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
91 ctx
->cf_info
.exec_potentially_empty_discard
= false;
99 bool exec_potentially_empty_discard_old
;
100 bool exec_potentially_empty_break_old
;
101 uint16_t exec_potentially_empty_break_depth_old
;
105 bool uniform_has_then_branch
;
106 bool then_branch_divergent
;
111 static bool visit_cf_list(struct isel_context
*ctx
,
112 struct exec_list
*list
);
114 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
116 succ
->logical_preds
.emplace_back(pred_idx
);
120 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
122 succ
->linear_preds
.emplace_back(pred_idx
);
125 static void add_edge(unsigned pred_idx
, Block
*succ
)
127 add_logical_edge(pred_idx
, succ
);
128 add_linear_edge(pred_idx
, succ
);
131 static void append_logical_start(Block
*b
)
133 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
136 static void append_logical_end(Block
*b
)
138 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
141 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
143 assert(ctx
->allocated
[def
->index
].id());
144 return ctx
->allocated
[def
->index
];
147 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
148 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
150 Builder
bld(ctx
->program
, ctx
->block
);
151 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
152 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
154 if (ctx
->program
->wave_size
== 32) {
156 } else if (ctx
->program
->chip_class
<= GFX7
) {
157 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
160 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
165 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
167 Builder
bld(ctx
->program
, ctx
->block
);
170 dst
= bld
.tmp(src
.regClass());
172 assert(src
.size() == dst
.size());
174 if (ctx
->stage
!= fragment_fs
) {
178 bld
.copy(Definition(dst
), src
);
182 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
183 ctx
->program
->needs_wqm
|= program_needs_wqm
;
187 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
189 if (index
.regClass() == s1
)
190 return bld
.readlane(bld
.def(s1
), data
, index
);
192 if (ctx
->options
->chip_class
<= GFX7
) {
193 /* GFX6-7: there is no bpermute instruction */
194 Operand
index_op(index
);
195 Operand
input_data(data
);
196 index_op
.setLateKill(true);
197 input_data
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
200 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
201 /* GFX10 wave64 mode: emulate full-wave bpermute */
202 if (!ctx
->has_gfx10_wave64_bpermute
) {
203 ctx
->has_gfx10_wave64_bpermute
= true;
204 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
205 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
208 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
209 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
210 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
211 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
212 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
213 Operand
input_data(data
);
215 index_x4
.setLateKill(true);
216 input_data
.setLateKill(true);
217 same_half
.setLateKill(true);
219 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
221 /* GFX8-9 or GFX10 wave32: bpermute works normally */
222 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
223 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
227 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
229 if (ctx
->options
->chip_class
>= GFX8
) {
230 unsigned and_mask
= mask
& 0x1f;
231 unsigned or_mask
= (mask
>> 5) & 0x1f;
232 unsigned xor_mask
= (mask
>> 10) & 0x1f;
234 uint16_t dpp_ctrl
= 0xffff;
236 // TODO: we could use DPP8 for some swizzles
237 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
238 unsigned res
[4] = {0, 1, 2, 3};
239 for (unsigned i
= 0; i
< 4; i
++)
240 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
241 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
242 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
243 dpp_ctrl
= dpp_row_rr(8);
244 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
245 dpp_ctrl
= dpp_row_mirror
;
246 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
247 dpp_ctrl
= dpp_row_half_mirror
;
250 if (dpp_ctrl
!= 0xffff)
251 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
254 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
257 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
259 if (val
.type() == RegType::sgpr
) {
260 Builder
bld(ctx
->program
, ctx
->block
);
261 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
263 assert(val
.type() == RegType::vgpr
);
267 //assumes a != 0xffffffff
268 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
271 Builder
bld(ctx
->program
, ctx
->block
);
273 if (util_is_power_of_two_or_zero(b
)) {
274 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
278 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
280 assert(info
.multiplier
<= 0xffffffff);
282 bool pre_shift
= info
.pre_shift
!= 0;
283 bool increment
= info
.increment
!= 0;
284 bool multiply
= true;
285 bool post_shift
= info
.post_shift
!= 0;
287 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
288 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
292 Temp pre_shift_dst
= a
;
294 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
298 Temp increment_dst
= pre_shift_dst
;
300 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
301 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
304 Temp multiply_dst
= increment_dst
;
306 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
307 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
308 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
312 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
316 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
318 Builder
bld(ctx
->program
, ctx
->block
);
319 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
323 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
325 /* no need to extract the whole vector */
326 if (src
.regClass() == dst_rc
) {
331 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
332 Builder
bld(ctx
->program
, ctx
->block
);
333 auto it
= ctx
->allocated_vec
.find(src
.id());
334 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
335 if (it
->second
[idx
].regClass() == dst_rc
) {
336 return it
->second
[idx
];
338 assert(!dst_rc
.is_subdword());
339 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
340 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
344 if (dst_rc
.is_subdword())
345 src
= as_vgpr(ctx
, src
);
347 if (src
.bytes() == dst_rc
.bytes()) {
349 return bld
.copy(bld
.def(dst_rc
), src
);
351 Temp dst
= bld
.tmp(dst_rc
);
352 emit_extract_vector(ctx
, src
, idx
, dst
);
357 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
359 if (num_components
== 1)
361 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
364 if (num_components
> vec_src
.size()) {
365 if (vec_src
.type() == RegType::sgpr
) {
366 /* should still help get_alu_src() */
367 emit_split_vector(ctx
, vec_src
, vec_src
.size());
370 /* sub-dword split */
371 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
373 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
375 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
376 split
->operands
[0] = Operand(vec_src
);
377 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
378 for (unsigned i
= 0; i
< num_components
; i
++) {
379 elems
[i
] = {ctx
->program
->allocateId(), rc
};
380 split
->definitions
[i
] = Definition(elems
[i
]);
382 ctx
->block
->instructions
.emplace_back(std::move(split
));
383 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
386 /* This vector expansion uses a mask to determine which elements in the new vector
387 * come from the original vector. The other elements are undefined. */
388 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
390 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
395 Builder
bld(ctx
->program
, ctx
->block
);
396 if (num_components
== 1) {
397 if (dst
.type() == RegType::sgpr
)
398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
400 bld
.copy(Definition(dst
), vec_src
);
404 unsigned component_size
= dst
.size() / num_components
;
405 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
407 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
408 vec
->definitions
[0] = Definition(dst
);
410 for (unsigned i
= 0; i
< num_components
; i
++) {
411 if (mask
& (1 << i
)) {
412 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
413 if (dst
.type() == RegType::sgpr
)
414 src
= bld
.as_uniform(src
);
415 vec
->operands
[i
] = Operand(src
);
417 vec
->operands
[i
] = Operand(0u);
419 elems
[i
] = vec
->operands
[i
].getTemp();
421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
422 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
425 /* adjust misaligned small bit size loads */
426 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
428 Builder
bld(ctx
->program
, ctx
->block
);
430 Temp select
= Temp();
431 if (offset
.isConstant()) {
432 assert(offset
.constantValue() && offset
.constantValue() < 4);
433 shift
= Operand(offset
.constantValue() * 8);
435 /* bit_offset = 8 * (offset & 0x3) */
436 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
437 select
= bld
.tmp(s1
);
438 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
441 if (vec
.size() == 1) {
442 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
443 } else if (vec
.size() == 2) {
444 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
445 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
447 emit_split_vector(ctx
, dst
, 2);
449 emit_extract_vector(ctx
, tmp
, 0, dst
);
450 } else if (vec
.size() == 4) {
451 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
453 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
454 if (select
!= Temp())
455 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
456 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
457 Temp mid
= bld
.tmp(s1
);
458 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
459 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
460 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
461 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
462 emit_split_vector(ctx
, dst
, 2);
466 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
468 Builder
bld(ctx
->program
, ctx
->block
);
469 if (offset
.isTemp()) {
470 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
472 if (vec
.size() == 4) {
473 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
474 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
475 } else if (vec
.size() == 3) {
476 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
477 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
478 } else if (vec
.size() == 2) {
479 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
480 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
482 for (unsigned i
= 0; i
< dst
.size(); i
++)
483 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
487 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
489 offset
= Operand(0u);
492 unsigned num_components
= vec
.bytes() / component_size
;
493 if (vec
.regClass() == dst
.regClass()) {
494 assert(offset
.constantValue() == 0);
495 bld
.copy(Definition(dst
), vec
);
496 emit_split_vector(ctx
, dst
, num_components
);
500 emit_split_vector(ctx
, vec
, num_components
);
501 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
502 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
504 assert(offset
.constantValue() % component_size
== 0);
505 unsigned skip
= offset
.constantValue() / component_size
;
506 for (unsigned i
= skip
; i
< num_components
; i
++)
507 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
509 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
510 if (dst
.type() == RegType::vgpr
) {
511 num_components
= dst
.bytes() / component_size
;
512 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
513 for (unsigned i
= 0; i
< num_components
; i
++)
514 create_vec
->operands
[i
] = Operand(elems
[i
]);
515 create_vec
->definitions
[0] = Definition(dst
);
516 bld
.insert(std::move(create_vec
));
518 /* if dst is sgpr - split the src, but move the original to sgpr. */
520 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
521 byte_align_scalar(ctx
, vec
, offset
, dst
);
523 assert(dst
.size() == vec
.size());
524 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
527 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
530 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
532 Builder
bld(ctx
->program
, ctx
->block
);
534 dst
= bld
.tmp(bld
.lm
);
536 assert(val
.regClass() == s1
);
537 assert(dst
.regClass() == bld
.lm
);
539 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
542 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
544 Builder
bld(ctx
->program
, ctx
->block
);
548 assert(val
.regClass() == bld
.lm
);
549 assert(dst
.regClass() == s1
);
551 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
552 Temp tmp
= bld
.tmp(s1
);
553 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
554 return emit_wqm(ctx
, tmp
, dst
);
557 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
560 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
561 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
563 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
566 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
567 return bld
.copy(Definition(dst
), src
);
568 else if (dst
.bytes() < src
.bytes())
569 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
573 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
576 } else if (src
.regClass() == s1
) {
578 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
580 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
581 } else if (ctx
->options
->chip_class
>= GFX8
) {
582 assert(src_bits
!= 8 || src
.regClass() == v1b
);
583 assert(src_bits
!= 16 || src
.regClass() == v2b
);
584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
585 sdwa
->operands
[0] = Operand(src
);
586 sdwa
->definitions
[0] = Definition(tmp
);
588 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
590 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
591 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
592 bld
.insert(std::move(sdwa
));
594 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
595 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
596 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
599 if (dst_bits
== 64) {
600 if (is_signed
&& dst
.regClass() == s2
) {
601 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
602 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
603 } else if (is_signed
&& dst
.regClass() == v2
) {
604 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
607 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
614 enum sgpr_extract_mode
{
620 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
622 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
623 unsigned src_size
= src
->src
.ssa
->bit_size
;
624 unsigned swizzle
= src
->swizzle
[0];
626 if (vec
.size() > 1) {
627 assert(src_size
== 16);
628 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
629 swizzle
= swizzle
& 1;
632 Builder
bld(ctx
->program
, ctx
->block
);
633 unsigned offset
= src_size
* swizzle
;
634 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
636 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
637 bld
.copy(Definition(tmp
), vec
);
638 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
639 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
640 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
641 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
642 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
643 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
645 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
646 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
649 if (dst
.regClass() == s2
)
650 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
655 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
657 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
658 return get_ssa_temp(ctx
, src
.src
.ssa
);
660 if (src
.src
.ssa
->num_components
== size
) {
661 bool identity_swizzle
= true;
662 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
663 if (src
.swizzle
[i
] != i
)
664 identity_swizzle
= false;
666 if (identity_swizzle
)
667 return get_ssa_temp(ctx
, src
.src
.ssa
);
670 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
671 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
672 assert(elem_size
> 0);
673 assert(vec
.bytes() % elem_size
== 0);
675 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
676 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
678 return extract_8_16_bit_sgpr_element(
679 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
682 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
684 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
687 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
688 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
689 for (unsigned i
= 0; i
< size
; ++i
) {
690 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
691 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
693 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
694 vec_instr
->definitions
[0] = Definition(dst
);
695 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
696 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
701 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
705 Builder
bld(ctx
->program
, ctx
->block
);
706 if (ptr
.type() == RegType::vgpr
)
707 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
708 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
709 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
712 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
714 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
715 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
716 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
717 sop2
->definitions
[0] = Definition(dst
);
718 if (instr
->no_unsigned_wrap
)
719 sop2
->definitions
[0].setNUW(true);
721 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
722 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
725 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
726 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
728 Builder
bld(ctx
->program
, ctx
->block
);
729 bld
.is_precise
= instr
->exact
;
731 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
733 if (src1
.type() == RegType::sgpr
) {
734 if (commutative
&& src0
.type() == RegType::vgpr
) {
739 src1
= as_vgpr(ctx
, src1
);
743 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
744 assert(dst
.size() == 1);
745 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
746 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
748 bld
.vop2(op
, Definition(dst
), src0
, src1
);
752 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
753 aco_opcode op
, Temp dst
)
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.is_precise
= instr
->exact
;
758 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
759 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
761 if (src1
.type() == RegType::sgpr
) {
762 assert(src0
.type() == RegType::vgpr
);
763 std::swap(src0
, src1
);
766 Temp src00
= bld
.tmp(src0
.type(), 1);
767 Temp src01
= bld
.tmp(src0
.type(), 1);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
769 Temp src10
= bld
.tmp(v1
);
770 Temp src11
= bld
.tmp(v1
);
771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
772 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
773 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
777 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
778 bool flush_denorms
= false)
780 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
781 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
782 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
784 /* ensure that the instruction has at most 1 sgpr operand
785 * The optimizer will inline constants for us */
786 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
787 src0
= as_vgpr(ctx
, src0
);
788 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
789 src1
= as_vgpr(ctx
, src1
);
790 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
791 src2
= as_vgpr(ctx
, src2
);
793 Builder
bld(ctx
->program
, ctx
->block
);
794 bld
.is_precise
= instr
->exact
;
795 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
796 assert(dst
.size() == 1);
797 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
798 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
800 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
804 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
806 Builder
bld(ctx
->program
, ctx
->block
);
807 bld
.is_precise
= instr
->exact
;
808 if (dst
.type() == RegType::sgpr
)
809 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
810 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
812 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
815 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
817 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
818 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
819 assert(src0
.size() == src1
.size());
821 aco_ptr
<Instruction
> vopc
;
822 if (src1
.type() == RegType::sgpr
) {
823 if (src0
.type() == RegType::vgpr
) {
824 /* to swap the operands, we might also have to change the opcode */
826 case aco_opcode::v_cmp_lt_f16
:
827 op
= aco_opcode::v_cmp_gt_f16
;
829 case aco_opcode::v_cmp_ge_f16
:
830 op
= aco_opcode::v_cmp_le_f16
;
832 case aco_opcode::v_cmp_lt_i16
:
833 op
= aco_opcode::v_cmp_gt_i16
;
835 case aco_opcode::v_cmp_ge_i16
:
836 op
= aco_opcode::v_cmp_le_i16
;
838 case aco_opcode::v_cmp_lt_u16
:
839 op
= aco_opcode::v_cmp_gt_u16
;
841 case aco_opcode::v_cmp_ge_u16
:
842 op
= aco_opcode::v_cmp_le_u16
;
844 case aco_opcode::v_cmp_lt_f32
:
845 op
= aco_opcode::v_cmp_gt_f32
;
847 case aco_opcode::v_cmp_ge_f32
:
848 op
= aco_opcode::v_cmp_le_f32
;
850 case aco_opcode::v_cmp_lt_i32
:
851 op
= aco_opcode::v_cmp_gt_i32
;
853 case aco_opcode::v_cmp_ge_i32
:
854 op
= aco_opcode::v_cmp_le_i32
;
856 case aco_opcode::v_cmp_lt_u32
:
857 op
= aco_opcode::v_cmp_gt_u32
;
859 case aco_opcode::v_cmp_ge_u32
:
860 op
= aco_opcode::v_cmp_le_u32
;
862 case aco_opcode::v_cmp_lt_f64
:
863 op
= aco_opcode::v_cmp_gt_f64
;
865 case aco_opcode::v_cmp_ge_f64
:
866 op
= aco_opcode::v_cmp_le_f64
;
868 case aco_opcode::v_cmp_lt_i64
:
869 op
= aco_opcode::v_cmp_gt_i64
;
871 case aco_opcode::v_cmp_ge_i64
:
872 op
= aco_opcode::v_cmp_le_i64
;
874 case aco_opcode::v_cmp_lt_u64
:
875 op
= aco_opcode::v_cmp_gt_u64
;
877 case aco_opcode::v_cmp_ge_u64
:
878 op
= aco_opcode::v_cmp_le_u64
;
880 default: /* eq and ne are commutative */
887 src1
= as_vgpr(ctx
, src1
);
891 Builder
bld(ctx
->program
, ctx
->block
);
892 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
895 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
897 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
898 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
899 Builder
bld(ctx
->program
, ctx
->block
);
901 assert(dst
.regClass() == bld
.lm
);
902 assert(src0
.type() == RegType::sgpr
);
903 assert(src1
.type() == RegType::sgpr
);
904 assert(src0
.regClass() == src1
.regClass());
906 /* Emit the SALU comparison instruction */
907 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
908 /* Turn the result into a per-lane bool */
909 bool_to_vector_condition(ctx
, cmp
, dst
);
912 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
913 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
915 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
916 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
917 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
918 nir_dest_is_divergent(instr
->dest
.dest
) ||
919 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
920 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
921 aco_opcode op
= use_valu
? v_op
: s_op
;
922 assert(op
!= aco_opcode::num_opcodes
);
923 assert(dst
.regClass() == ctx
->program
->lane_mask
);
926 emit_vopc_instruction(ctx
, instr
, op
, dst
);
928 emit_sopc_instruction(ctx
, instr
, op
, dst
);
931 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
933 Builder
bld(ctx
->program
, ctx
->block
);
934 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
935 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
937 assert(dst
.regClass() == bld
.lm
);
938 assert(src0
.regClass() == bld
.lm
);
939 assert(src1
.regClass() == bld
.lm
);
941 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
944 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
946 Builder
bld(ctx
->program
, ctx
->block
);
947 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
948 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
949 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
951 assert(cond
.regClass() == bld
.lm
);
953 if (dst
.type() == RegType::vgpr
) {
954 aco_ptr
<Instruction
> bcsel
;
955 if (dst
.size() == 1) {
956 then
= as_vgpr(ctx
, then
);
957 els
= as_vgpr(ctx
, els
);
959 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
960 } else if (dst
.size() == 2) {
961 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
963 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
966 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
967 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
971 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
976 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
977 assert(dst
.regClass() == bld
.lm
);
978 assert(then
.regClass() == bld
.lm
);
979 assert(els
.regClass() == bld
.lm
);
982 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
983 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
984 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
985 assert(dst
.size() == then
.size());
986 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
987 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
989 isel_err(&instr
->instr
, "Unimplemented uniform bcsel bit size");
994 /* divergent boolean bcsel
995 * this implements bcsel on bools: dst = s0 ? s1 : s2
996 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
997 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
999 if (cond
.id() != then
.id())
1000 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
1002 if (cond
.id() == els
.id())
1003 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
1005 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
1006 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
1009 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
1010 aco_opcode op
, uint32_t undo
)
1012 /* multiply by 16777216 to handle denormals */
1013 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1014 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1015 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1016 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1017 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1019 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1021 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1024 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1026 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1027 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1031 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1034 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1036 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1037 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1041 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1044 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1046 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1047 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1051 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1054 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1056 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1057 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1061 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1064 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1066 if (ctx
->options
->chip_class
>= GFX7
)
1067 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1069 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1070 /* TODO: create more efficient code! */
1071 if (val
.type() == RegType::sgpr
)
1072 val
= as_vgpr(ctx
, val
);
1074 /* Split the input value. */
1075 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1078 /* Extract the exponent and compute the unbiased value. */
1079 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1080 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1082 /* Extract the fractional part. */
1083 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1084 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1086 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1089 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1090 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1091 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1092 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1093 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1095 /* Get the sign bit. */
1096 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1098 /* Decide the operation to apply depending on the unbiased exponent. */
1099 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1100 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1101 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1102 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1103 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1104 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1106 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1109 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1111 if (ctx
->options
->chip_class
>= GFX7
)
1112 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1114 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1115 * lowered at NIR level for precision reasons). */
1116 Temp src0
= as_vgpr(ctx
, val
);
1118 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1119 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1121 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1122 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1123 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1125 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1127 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1128 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1130 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1131 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1133 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1135 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1136 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1138 return add
->definitions
[0].getTemp();
1141 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1143 if (!instr
->dest
.dest
.is_ssa
) {
1144 isel_err(&instr
->instr
, "nir alu dst not in ssa");
1147 Builder
bld(ctx
->program
, ctx
->block
);
1148 bld
.is_precise
= instr
->exact
;
1149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1154 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1155 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1156 for (unsigned i
= 0; i
< num
; ++i
)
1157 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1159 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1160 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1161 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1162 for (unsigned i
= 0; i
< num
; ++i
) {
1163 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1164 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1166 vec
->operands
[i
] = Operand
{elems
[i
]};
1168 vec
->definitions
[0] = Definition(dst
);
1169 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1170 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1172 // TODO: that is a bit suboptimal..
1173 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1174 for (unsigned i
= 0; i
< num
- 1; ++i
)
1175 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1176 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1177 for (unsigned i
= 0; i
< num
; ++i
) {
1178 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1179 if (bit
% 32 == 0) {
1180 elems
[bit
/ 32] = elems
[i
];
1182 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1183 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1184 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1187 if (dst
.size() == 1)
1188 bld
.copy(Definition(dst
), elems
[0]);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1195 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1196 aco_ptr
<Instruction
> mov
;
1197 if (dst
.type() == RegType::sgpr
) {
1198 if (src
.type() == RegType::vgpr
)
1199 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1200 else if (src
.regClass() == s1
)
1201 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1202 else if (src
.regClass() == s2
)
1203 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1205 unreachable("wrong src register class for nir_op_imov");
1207 if (dst
.regClass() == v1
)
1208 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1209 else if (dst
.regClass() == v1b
||
1210 dst
.regClass() == v2b
||
1211 dst
.regClass() == v2
)
1212 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1214 unreachable("wrong src register class for nir_op_imov");
1219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1220 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1221 assert(src
.regClass() == bld
.lm
);
1222 assert(dst
.regClass() == bld
.lm
);
1223 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1224 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1225 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1226 } else if (dst
.regClass() == v1
) {
1227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1228 } else if (dst
.regClass() == v2
) {
1229 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1230 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1231 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1232 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1234 } else if (dst
.type() == RegType::sgpr
) {
1235 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1236 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1238 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1243 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1244 if (dst
.regClass() == v1
) {
1245 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1246 } else if (dst
.regClass() == s1
) {
1247 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1248 } else if (dst
.size() == 2) {
1249 Temp src0
= bld
.tmp(dst
.type(), 1);
1250 Temp src1
= bld
.tmp(dst
.type(), 1);
1251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1253 if (dst
.regClass() == s2
) {
1254 Temp carry
= bld
.tmp(s1
);
1255 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1256 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1257 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1259 Temp lower
= bld
.tmp(v1
);
1260 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1261 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1265 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1270 if (dst
.regClass() == s1
) {
1271 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1272 } else if (dst
.regClass() == v1
) {
1273 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1274 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1276 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1280 case nir_op_isign
: {
1281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1282 if (dst
.regClass() == s1
) {
1283 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1284 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1285 } else if (dst
.regClass() == s2
) {
1286 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1288 if (ctx
->program
->chip_class
>= GFX8
)
1289 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1291 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1292 /* SCC gets zero-extended to 64 bit */
1293 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1294 } else if (dst
.regClass() == v1
) {
1295 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1296 } else if (dst
.regClass() == v2
) {
1297 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1298 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1299 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1300 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1301 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1304 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1309 if (dst
.regClass() == v1
) {
1310 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1311 } else if (dst
.regClass() == s1
) {
1312 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1314 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1319 if (dst
.regClass() == v1
) {
1320 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1321 } else if (dst
.regClass() == s1
) {
1322 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1324 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1329 if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1331 } else if (dst
.regClass() == s1
) {
1332 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1334 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1339 if (dst
.regClass() == v1
) {
1340 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1341 } else if (dst
.regClass() == s1
) {
1342 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1344 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1349 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1350 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1351 } else if (dst
.regClass() == v1
) {
1352 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1353 } else if (dst
.regClass() == v2
) {
1354 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1360 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1365 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1366 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1367 } else if (dst
.regClass() == v1
) {
1368 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1369 } else if (dst
.regClass() == v2
) {
1370 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1371 } else if (dst
.regClass() == s1
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1373 } else if (dst
.regClass() == s2
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1376 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1381 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1382 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1383 } else if (dst
.regClass() == v1
) {
1384 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1385 } else if (dst
.regClass() == v2
) {
1386 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1387 } else if (dst
.regClass() == s1
) {
1388 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1392 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1397 if (dst
.regClass() == v1
) {
1398 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1399 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1400 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1401 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1402 } else if (dst
.regClass() == v2
) {
1403 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1404 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1405 } else if (dst
.regClass() == s2
) {
1406 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1407 } else if (dst
.regClass() == s1
) {
1408 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1410 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1415 if (dst
.regClass() == v1
) {
1416 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1417 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1418 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1419 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1420 } else if (dst
.regClass() == v2
) {
1421 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1423 } else if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1425 } else if (dst
.regClass() == s2
) {
1426 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1428 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1433 if (dst
.regClass() == v1
) {
1434 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1435 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1436 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1437 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1438 } else if (dst
.regClass() == v2
) {
1439 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1440 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1441 } else if (dst
.regClass() == s1
) {
1442 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1443 } else if (dst
.regClass() == s2
) {
1444 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1446 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1450 case nir_op_find_lsb
: {
1451 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1452 if (src
.regClass() == s1
) {
1453 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1454 } else if (src
.regClass() == v1
) {
1455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1456 } else if (src
.regClass() == s2
) {
1457 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1459 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1463 case nir_op_ufind_msb
:
1464 case nir_op_ifind_msb
: {
1465 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1466 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1467 aco_opcode op
= src
.regClass() == s2
?
1468 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1469 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1470 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1472 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1473 Operand(src
.size() * 32u - 1u), msb_rev
);
1474 Temp msb
= sub
.def(0).getTemp();
1475 Temp carry
= sub
.def(1).getTemp();
1477 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1478 } else if (src
.regClass() == v1
) {
1479 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1480 Temp msb_rev
= bld
.tmp(v1
);
1481 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1482 Temp msb
= bld
.tmp(v1
);
1483 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1484 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1486 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1490 case nir_op_bitfield_reverse
: {
1491 if (dst
.regClass() == s1
) {
1492 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1493 } else if (dst
.regClass() == v1
) {
1494 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1496 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1501 if (dst
.regClass() == s1
) {
1502 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1506 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1507 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1508 if (dst
.regClass() == v1
) {
1509 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1513 assert(src0
.size() == 2 && src1
.size() == 2);
1514 Temp src00
= bld
.tmp(src0
.type(), 1);
1515 Temp src01
= bld
.tmp(dst
.type(), 1);
1516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1517 Temp src10
= bld
.tmp(src1
.type(), 1);
1518 Temp src11
= bld
.tmp(dst
.type(), 1);
1519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1521 if (dst
.regClass() == s2
) {
1522 Temp carry
= bld
.tmp(s1
);
1523 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1524 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1525 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1526 } else if (dst
.regClass() == v2
) {
1527 Temp dst0
= bld
.tmp(v1
);
1528 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1529 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1530 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1532 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1536 case nir_op_uadd_sat
: {
1537 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1538 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1539 if (dst
.regClass() == s1
) {
1540 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1541 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1543 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1544 } else if (dst
.regClass() == v1
) {
1545 if (ctx
->options
->chip_class
>= GFX9
) {
1546 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1547 add
->operands
[0] = Operand(src0
);
1548 add
->operands
[1] = Operand(src1
);
1549 add
->definitions
[0] = Definition(dst
);
1551 ctx
->block
->instructions
.emplace_back(std::move(add
));
1553 if (src1
.regClass() != v1
)
1554 std::swap(src0
, src1
);
1555 assert(src1
.regClass() == v1
);
1556 Temp tmp
= bld
.tmp(v1
);
1557 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1558 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1561 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1600 if (dst
.regClass() == s1
) {
1601 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1605 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1606 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1607 if (dst
.regClass() == v1
) {
1608 bld
.vsub32(Definition(dst
), src0
, src1
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp carry
= bld
.tmp(s1
);
1620 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1621 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1623 } else if (dst
.regClass() == v2
) {
1624 Temp lower
= bld
.tmp(v1
);
1625 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1626 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1629 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1633 case nir_op_usub_borrow
: {
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == s1
) {
1637 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1639 } else if (dst
.regClass() == v1
) {
1640 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1641 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1645 Temp src00
= bld
.tmp(src0
.type(), 1);
1646 Temp src01
= bld
.tmp(dst
.type(), 1);
1647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1648 Temp src10
= bld
.tmp(src1
.type(), 1);
1649 Temp src11
= bld
.tmp(dst
.type(), 1);
1650 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1651 if (dst
.regClass() == s2
) {
1652 Temp borrow
= bld
.tmp(s1
);
1653 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1654 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1656 } else if (dst
.regClass() == v2
) {
1657 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1658 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1659 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1660 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1662 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1667 if (dst
.regClass() == v1
) {
1668 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1669 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1670 } else if (dst
.regClass() == s1
) {
1671 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1673 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1677 case nir_op_umul_high
: {
1678 if (dst
.regClass() == v1
) {
1679 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1680 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1681 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1682 } else if (dst
.regClass() == s1
) {
1683 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1684 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1685 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1687 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1691 case nir_op_imul_high
: {
1692 if (dst
.regClass() == v1
) {
1693 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1694 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1695 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1696 } else if (dst
.regClass() == s1
) {
1697 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1698 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1699 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1701 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1706 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1707 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1712 } else if (dst
.regClass() == v2
) {
1713 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1715 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1721 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1722 if (dst
.regClass() == v2b
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1726 } else if (dst
.regClass() == v2
) {
1727 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1729 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1736 if (dst
.regClass() == v2b
) {
1737 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1738 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1740 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1741 } else if (dst
.regClass() == v1
) {
1742 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1743 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1746 } else if (dst
.regClass() == v2
) {
1747 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1748 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1749 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1752 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1757 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1758 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1759 if (dst
.regClass() == v2b
) {
1760 // TODO: check fp_mode.must_flush_denorms16_64
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1764 } else if (dst
.regClass() == v2
) {
1765 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1766 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1767 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1769 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1772 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1779 if (dst
.regClass() == v2b
) {
1780 // TODO: check fp_mode.must_flush_denorms16_64
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1782 } else if (dst
.regClass() == v1
) {
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1784 } else if (dst
.regClass() == v2
) {
1785 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1786 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1787 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1789 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1792 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1796 case nir_op_cube_face_coord
: {
1797 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1798 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1799 emit_extract_vector(ctx
, in
, 1, v1
),
1800 emit_extract_vector(ctx
, in
, 2, v1
) };
1801 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1802 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1803 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1804 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1805 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1806 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
), Operand(0x3f000000u
/*0.5*/));
1807 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1808 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
), Operand(0x3f000000u
/*0.5*/));
1809 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1812 case nir_op_cube_face_index
: {
1813 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1814 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1815 emit_extract_vector(ctx
, in
, 1, v1
),
1816 emit_extract_vector(ctx
, in
, 2, v1
) };
1817 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1820 case nir_op_bcsel
: {
1821 emit_bcsel(ctx
, instr
, dst
);
1825 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1826 if (dst
.regClass() == v2b
) {
1827 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1828 } else if (dst
.regClass() == v1
) {
1829 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1830 } else if (dst
.regClass() == v2
) {
1831 /* Lowered at NIR level for precision reasons. */
1832 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1834 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1839 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1840 if (dst
.regClass() == v2b
) {
1841 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1842 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1843 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1844 } else if (dst
.regClass() == v1
) {
1845 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1846 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1847 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1848 } else if (dst
.regClass() == v2
) {
1849 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1850 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1851 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1853 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1854 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1856 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1861 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1862 if (dst
.regClass() == v2b
) {
1863 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1864 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1865 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1866 } else if (dst
.regClass() == v1
) {
1867 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1868 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1869 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1870 } else if (dst
.regClass() == v2
) {
1871 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1872 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1873 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1874 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1875 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1876 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1878 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1883 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1884 if (dst
.regClass() == v2b
) {
1885 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1886 } else if (dst
.regClass() == v1
) {
1887 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1888 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1889 // TODO: confirm that this holds under any circumstances
1890 } else if (dst
.regClass() == v2
) {
1891 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1892 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1895 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1899 case nir_op_flog2
: {
1900 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1901 if (dst
.regClass() == v2b
) {
1902 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1903 } else if (dst
.regClass() == v1
) {
1904 emit_log2(ctx
, bld
, Definition(dst
), src
);
1906 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1911 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1912 if (dst
.regClass() == v2b
) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1914 } else if (dst
.regClass() == v1
) {
1915 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1916 } else if (dst
.regClass() == v2
) {
1917 /* Lowered at NIR level for precision reasons. */
1918 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1920 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1924 case nir_op_fexp2
: {
1925 if (dst
.regClass() == v2b
) {
1926 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1927 } else if (dst
.regClass() == v1
) {
1928 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1930 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1934 case nir_op_fsqrt
: {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 if (dst
.regClass() == v2b
) {
1937 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1940 } else if (dst
.regClass() == v2
) {
1941 /* Lowered at NIR level for precision reasons. */
1942 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1944 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1948 case nir_op_ffract
: {
1949 if (dst
.regClass() == v2b
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1951 } else if (dst
.regClass() == v1
) {
1952 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1953 } else if (dst
.regClass() == v2
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1956 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1960 case nir_op_ffloor
: {
1961 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1962 if (dst
.regClass() == v2b
) {
1963 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1964 } else if (dst
.regClass() == v1
) {
1965 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1966 } else if (dst
.regClass() == v2
) {
1967 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1969 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1973 case nir_op_fceil
: {
1974 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1975 if (dst
.regClass() == v2b
) {
1976 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1977 } else if (dst
.regClass() == v1
) {
1978 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1979 } else if (dst
.regClass() == v2
) {
1980 if (ctx
->options
->chip_class
>= GFX7
) {
1981 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1983 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1984 /* trunc = trunc(src0)
1985 * if (src0 > 0.0 && src0 != trunc)
1988 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1989 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1990 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1991 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1992 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1993 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1994 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1997 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2001 case nir_op_ftrunc
: {
2002 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2003 if (dst
.regClass() == v2b
) {
2004 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2005 } else if (dst
.regClass() == v1
) {
2006 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2007 } else if (dst
.regClass() == v2
) {
2008 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2010 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2014 case nir_op_fround_even
: {
2015 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2016 if (dst
.regClass() == v2b
) {
2017 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2018 } else if (dst
.regClass() == v1
) {
2019 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2020 } else if (dst
.regClass() == v2
) {
2021 if (ctx
->options
->chip_class
>= GFX7
) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2024 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2025 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2026 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2028 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2029 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2030 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2032 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2033 tmp
= sub
->definitions
[0].getTemp();
2035 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2036 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2037 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2038 Temp cond
= vop3
->definitions
[0].getTemp();
2040 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2041 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2042 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2043 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2045 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2048 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2054 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2055 aco_ptr
<Instruction
> norm
;
2056 if (dst
.regClass() == v2b
) {
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2058 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2059 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2060 bld
.vop1(opcode
, Definition(dst
), tmp
);
2061 } else if (dst
.regClass() == v1
) {
2062 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2063 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2065 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2066 if (ctx
->options
->chip_class
< GFX9
)
2067 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2069 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2070 bld
.vop1(opcode
, Definition(dst
), tmp
);
2072 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2076 case nir_op_ldexp
: {
2077 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2078 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2079 if (dst
.regClass() == v2b
) {
2080 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2081 } else if (dst
.regClass() == v1
) {
2082 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2083 } else if (dst
.regClass() == v2
) {
2084 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2086 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2090 case nir_op_frexp_sig
: {
2091 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2092 if (dst
.regClass() == v2b
) {
2093 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2094 } else if (dst
.regClass() == v1
) {
2095 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2096 } else if (dst
.regClass() == v2
) {
2097 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2099 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2103 case nir_op_frexp_exp
: {
2104 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2105 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2106 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2107 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2108 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2109 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2110 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2111 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2112 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2114 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2118 case nir_op_fsign
: {
2119 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2120 if (dst
.regClass() == v2b
) {
2121 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2122 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2123 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2124 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2125 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2126 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2127 } else if (dst
.regClass() == v1
) {
2128 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2129 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2130 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2131 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2132 } else if (dst
.regClass() == v2
) {
2133 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2134 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2135 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2137 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2138 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2139 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2141 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2143 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2148 case nir_op_f2f16_rtne
: {
2149 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2150 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2151 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2152 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2153 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2154 * keep value numbering and the scheduler simpler.
2156 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2158 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2161 case nir_op_f2f16_rtz
: {
2162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2163 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2164 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2165 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2168 case nir_op_f2f32
: {
2169 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2170 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2171 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2172 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2174 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2178 case nir_op_f2f64
: {
2179 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2180 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2181 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2182 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2185 case nir_op_i2f16
: {
2186 assert(dst
.regClass() == v2b
);
2187 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2188 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2189 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2190 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2191 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2192 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2195 case nir_op_i2f32
: {
2196 assert(dst
.size() == 1);
2197 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2198 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2199 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2200 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2203 case nir_op_i2f64
: {
2204 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2207 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2208 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2209 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2210 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2211 RegClass rc
= RegClass(src
.type(), 1);
2212 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2213 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2214 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2215 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2216 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2217 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2220 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2224 case nir_op_u2f16
: {
2225 assert(dst
.regClass() == v2b
);
2226 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2227 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2228 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2229 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2230 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2231 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2234 case nir_op_u2f32
: {
2235 assert(dst
.size() == 1);
2236 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2237 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2238 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2240 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2241 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2242 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2246 case nir_op_u2f64
: {
2247 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2248 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2249 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2250 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2251 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2252 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2253 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2254 RegClass rc
= RegClass(src
.type(), 1);
2255 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2256 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2257 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2258 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2259 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2260 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2262 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2267 case nir_op_f2i16
: {
2268 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2269 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2270 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2271 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2273 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2277 case nir_op_f2u16
: {
2278 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2279 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2280 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2281 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2283 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2286 case nir_op_f2i32
: {
2287 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2288 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2289 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2290 if (dst
.type() == RegType::vgpr
) {
2291 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2293 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2294 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2296 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2297 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2298 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2299 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2301 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2305 case nir_op_f2u32
: {
2306 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2307 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2308 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2309 if (dst
.type() == RegType::vgpr
) {
2310 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2312 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2313 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2315 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2316 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2317 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2318 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2320 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2324 case nir_op_f2i64
: {
2325 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2326 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2327 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2329 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2330 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2331 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2332 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2333 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2334 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2335 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2336 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2337 Temp new_exponent
= bld
.tmp(v1
);
2338 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2339 if (ctx
->program
->chip_class
>= GFX8
)
2340 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2342 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2343 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2344 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2345 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2346 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2347 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2348 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2349 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2350 Temp new_lower
= bld
.tmp(v1
);
2351 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2352 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2353 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2355 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2356 if (src
.type() == RegType::vgpr
)
2357 src
= bld
.as_uniform(src
);
2358 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2359 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2360 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2361 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2362 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2363 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2364 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2365 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2366 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2367 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2368 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2369 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2370 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2371 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2372 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2373 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2374 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2375 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2376 Temp borrow
= bld
.tmp(s1
);
2377 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2378 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2379 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2381 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2382 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2383 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2384 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2385 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2386 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2387 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2388 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2389 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2390 if (dst
.type() == RegType::sgpr
) {
2391 lower
= bld
.as_uniform(lower
);
2392 upper
= bld
.as_uniform(upper
);
2394 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2397 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2401 case nir_op_f2u64
: {
2402 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2403 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2404 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2406 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2407 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2408 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2409 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2410 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2411 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2412 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2413 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2414 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2415 Temp new_exponent
= bld
.tmp(v1
);
2416 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2417 if (ctx
->program
->chip_class
>= GFX8
)
2418 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2420 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2421 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2422 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2423 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2424 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2425 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2426 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2427 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2429 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2430 if (src
.type() == RegType::vgpr
)
2431 src
= bld
.as_uniform(src
);
2432 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2433 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2434 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2435 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2436 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2437 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2438 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2439 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2440 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2441 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2442 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2443 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2444 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2445 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2446 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2447 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2448 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2449 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2451 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2452 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2453 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2454 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2455 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2456 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2457 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2458 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2459 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2460 if (dst
.type() == RegType::sgpr
) {
2461 lower
= bld
.as_uniform(lower
);
2462 upper
= bld
.as_uniform(upper
);
2464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2467 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2471 case nir_op_b2f16
: {
2472 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2473 assert(src
.regClass() == bld
.lm
);
2475 if (dst
.regClass() == s1
) {
2476 src
= bool_to_scalar_condition(ctx
, src
);
2477 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2478 } else if (dst
.regClass() == v2b
) {
2479 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2480 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2482 unreachable("Wrong destination register class for nir_op_b2f16.");
2486 case nir_op_b2f32
: {
2487 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2488 assert(src
.regClass() == bld
.lm
);
2490 if (dst
.regClass() == s1
) {
2491 src
= bool_to_scalar_condition(ctx
, src
);
2492 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2493 } else if (dst
.regClass() == v1
) {
2494 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2496 unreachable("Wrong destination register class for nir_op_b2f32.");
2500 case nir_op_b2f64
: {
2501 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2502 assert(src
.regClass() == bld
.lm
);
2504 if (dst
.regClass() == s2
) {
2505 src
= bool_to_scalar_condition(ctx
, src
);
2506 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2507 } else if (dst
.regClass() == v2
) {
2508 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2509 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2510 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2512 unreachable("Wrong destination register class for nir_op_b2f64.");
2519 case nir_op_i2i64
: {
2520 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2521 /* no need to do the extract in get_alu_src() */
2522 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2523 sgpr_extract_sext
: sgpr_extract_undef
;
2524 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2526 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2527 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2534 case nir_op_u2u64
: {
2535 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2536 /* no need to do the extract in get_alu_src() */
2537 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2538 sgpr_extract_zext
: sgpr_extract_undef
;
2539 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2541 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2542 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2550 case nir_op_b2i64
: {
2551 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2552 assert(src
.regClass() == bld
.lm
);
2554 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2555 if (tmp
.regClass() == s1
) {
2556 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2557 bool_to_scalar_condition(ctx
, src
, tmp
);
2558 } else if (tmp
.type() == RegType::vgpr
) {
2559 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2561 unreachable("Invalid register class for b2i32");
2565 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2570 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2571 assert(dst
.regClass() == bld
.lm
);
2573 if (src
.type() == RegType::vgpr
) {
2574 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2575 assert(dst
.regClass() == bld
.lm
);
2576 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2577 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2579 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2581 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2582 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2584 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2585 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2587 bool_to_vector_condition(ctx
, tmp
, dst
);
2591 case nir_op_pack_64_2x32_split
: {
2592 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2593 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2595 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2598 case nir_op_unpack_64_2x32_split_x
:
2599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2601 case nir_op_unpack_64_2x32_split_y
:
2602 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2604 case nir_op_unpack_32_2x16_split_x
:
2605 if (dst
.type() == RegType::vgpr
) {
2606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2608 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2611 case nir_op_unpack_32_2x16_split_y
:
2612 if (dst
.type() == RegType::vgpr
) {
2613 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2615 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2618 case nir_op_pack_32_2x16_split
: {
2619 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2620 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2621 if (dst
.regClass() == v1
) {
2622 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2623 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2626 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2627 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2628 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2632 case nir_op_pack_half_2x16
: {
2633 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2635 if (dst
.regClass() == v1
) {
2636 Temp src0
= bld
.tmp(v1
);
2637 Temp src1
= bld
.tmp(v1
);
2638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2639 if (0 && (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)) {
2640 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2642 src0
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src0
);
2643 src1
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src1
);
2644 if (ctx
->program
->chip_class
>= GFX10
) {
2645 /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
2646 bld
.vop3(aco_opcode::v_pack_b32_f16
, Definition(dst
), src0
, src1
);
2648 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
), src0
, src1
);
2652 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2656 case nir_op_unpack_half_2x16_split_x
: {
2657 if (dst
.regClass() == v1
) {
2658 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2660 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2664 case nir_op_unpack_half_2x16_split_y
: {
2665 if (dst
.regClass() == v1
) {
2666 /* TODO: use SDWA here */
2667 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2668 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2670 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2674 case nir_op_fquantize2f16
: {
2675 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2676 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2679 if (ctx
->program
->chip_class
>= GFX8
) {
2680 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2681 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2682 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2684 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2685 * so compare the result and flush to 0 if it's smaller.
2687 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2688 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2689 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2690 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2691 cmp_res
= vop3
->definitions
[0].getTemp();
2694 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2695 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2696 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2698 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2703 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2704 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2706 if (dst
.regClass() == s1
) {
2707 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2708 } else if (dst
.regClass() == v1
) {
2709 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2711 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2715 case nir_op_bitfield_select
: {
2716 /* (mask & insert) | (~mask & base) */
2717 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2718 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2719 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2721 /* dst = (insert & bitmask) | (base & ~bitmask) */
2722 if (dst
.regClass() == s1
) {
2723 aco_ptr
<Instruction
> sop2
;
2724 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2725 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2727 if (const_insert
&& const_bitmask
) {
2728 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2730 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2731 lhs
= Operand(insert
);
2735 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2736 if (const_base
&& const_bitmask
) {
2737 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2739 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2740 rhs
= Operand(base
);
2743 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2745 } else if (dst
.regClass() == v1
) {
2746 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2747 base
= as_vgpr(ctx
, base
);
2748 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2749 insert
= as_vgpr(ctx
, insert
);
2751 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2754 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2760 if (dst
.bytes() != 4)
2761 unreachable("Unsupported BFE bit size");
2763 if (dst
.type() == RegType::sgpr
) {
2764 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2766 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2767 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2768 if (const_offset
&& const_bits
) {
2769 uint32_t extract
= (const_bits
->u32
<< 16) | (const_offset
->u32
& 0x1f);
2770 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
2771 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, Operand(extract
));
2775 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2776 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2777 if (instr
->op
== nir_op_ubfe
) {
2778 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b32
, bld
.def(s1
), bits
, offset
);
2779 Temp masked
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, mask
);
2780 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), masked
, offset
);
2782 Operand bits_op
= const_bits
? Operand(const_bits
->u32
<< 16) :
2783 bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2784 Operand offset_op
= const_offset
? Operand(const_offset
->u32
& 0x1fu
) :
2785 bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(0x1fu
));
2787 Temp extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits_op
, offset_op
);
2788 bld
.sop2(aco_opcode::s_bfe_i32
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2792 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::v_bfe_u32
: aco_opcode::v_bfe_i32
;
2793 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2797 case nir_op_bit_count
: {
2798 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2799 if (src
.regClass() == s1
) {
2800 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2801 } else if (src
.regClass() == v1
) {
2802 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2803 } else if (src
.regClass() == v2
) {
2804 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2805 emit_extract_vector(ctx
, src
, 1, v1
),
2806 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2807 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2808 } else if (src
.regClass() == s2
) {
2809 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2811 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2816 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2820 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2824 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2828 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2832 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2836 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2840 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2841 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2843 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2844 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2848 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2849 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2851 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2852 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2856 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2860 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2865 case nir_op_fddx_fine
:
2866 case nir_op_fddy_fine
:
2867 case nir_op_fddx_coarse
:
2868 case nir_op_fddy_coarse
: {
2869 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2870 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2871 if (instr
->op
== nir_op_fddx_fine
) {
2872 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2873 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2874 } else if (instr
->op
== nir_op_fddy_fine
) {
2875 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2876 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2878 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2879 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2880 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2882 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2886 if (ctx
->program
->chip_class
>= GFX8
) {
2887 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2888 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2890 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2891 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2892 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2894 emit_wqm(ctx
, tmp
, dst
, true);
2898 isel_err(&instr
->instr
, "Unknown NIR ALU instr");
2902 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2904 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2906 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2907 // which get truncated the lsb if double and msb if int
2908 // for now, we only use s_mov_b64 with 64bit inline constants
2909 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2910 assert(dst
.type() == RegType::sgpr
);
2912 Builder
bld(ctx
->program
, ctx
->block
);
2914 if (instr
->def
.bit_size
== 1) {
2915 assert(dst
.regClass() == bld
.lm
);
2916 int val
= instr
->value
[0].b
? -1 : 0;
2917 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2918 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2919 } else if (instr
->def
.bit_size
== 8) {
2920 /* ensure that the value is correctly represented in the low byte of the register */
2921 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2922 } else if (instr
->def
.bit_size
== 16) {
2923 /* ensure that the value is correctly represented in the low half of the register */
2924 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2925 } else if (dst
.size() == 1) {
2926 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2928 assert(dst
.size() != 1);
2929 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2930 if (instr
->def
.bit_size
== 64)
2931 for (unsigned i
= 0; i
< dst
.size(); i
++)
2932 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2934 for (unsigned i
= 0; i
< dst
.size(); i
++)
2935 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2937 vec
->definitions
[0] = Definition(dst
);
2938 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2942 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2944 uint32_t new_mask
= 0;
2945 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2946 if (mask
& (1u << i
))
2947 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2951 struct LoadEmitInfo
{
2954 unsigned num_components
;
2955 unsigned component_size
;
2956 Temp resource
= Temp(0, s1
);
2957 unsigned component_stride
= 0;
2958 unsigned const_offset
= 0;
2959 unsigned align_mul
= 0;
2960 unsigned align_offset
= 0;
2963 unsigned swizzle_component_size
= 0;
2964 memory_sync_info sync
;
2965 Temp soffset
= Temp(0, s1
);
2968 using LoadCallback
= Temp(*)(
2969 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
2970 unsigned align
, unsigned const_offset
, Temp dst_hint
);
2972 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
2973 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
2975 unsigned load_size
= info
->num_components
* info
->component_size
;
2976 unsigned component_size
= info
->component_size
;
2978 unsigned num_vals
= 0;
2979 Temp vals
[info
->dst
.bytes()];
2981 unsigned const_offset
= info
->const_offset
;
2983 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
2984 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
2986 unsigned bytes_read
= 0;
2987 while (bytes_read
< load_size
) {
2988 unsigned bytes_needed
= load_size
- bytes_read
;
2990 /* add buffer for unaligned loads */
2991 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
2994 if ((bytes_needed
> 2 ||
2995 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
2996 !supports_8bit_16bit_loads
) && byte_align_loads
) {
2997 if (info
->component_stride
) {
2998 assert(supports_8bit_16bit_loads
&& "unimplemented");
3002 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3003 bytes_needed
= align(bytes_needed
, 4);
3010 if (info
->swizzle_component_size
)
3011 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3012 if (info
->component_stride
)
3013 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3015 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3017 /* reduce constant offset */
3018 Operand offset
= info
->offset
;
3019 unsigned reduced_const_offset
= const_offset
;
3020 bool remove_const_offset_completely
= need_to_align_offset
;
3021 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3022 unsigned to_add
= const_offset
;
3023 if (remove_const_offset_completely
) {
3024 reduced_const_offset
= 0;
3026 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3027 reduced_const_offset
%= max_const_offset_plus_one
;
3029 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3030 if (offset
.isConstant()) {
3031 offset
= Operand(offset
.constantValue() + to_add
);
3032 } else if (offset_tmp
.regClass() == s1
) {
3033 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3034 offset_tmp
, Operand(to_add
));
3035 } else if (offset_tmp
.regClass() == v1
) {
3036 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3038 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3039 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3040 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3042 if (offset_tmp
.regClass() == s2
) {
3043 Temp carry
= bld
.tmp(s1
);
3044 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3045 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3046 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3048 Temp new_lo
= bld
.tmp(v1
);
3049 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3050 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3051 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3056 /* align offset down if needed */
3057 Operand aligned_offset
= offset
;
3058 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3059 if (need_to_align_offset
) {
3061 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3062 if (offset
.isConstant()) {
3063 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3064 } else if (offset_tmp
.regClass() == s1
) {
3065 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3066 } else if (offset_tmp
.regClass() == s2
) {
3067 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3068 } else if (offset_tmp
.regClass() == v1
) {
3069 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3070 } else if (offset_tmp
.regClass() == v2
) {
3071 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3072 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3073 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3074 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3077 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3078 bld
.copy(bld
.def(s1
), aligned_offset
);
3080 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3081 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3083 /* the callback wrote directly to dst */
3084 if (val
== info
->dst
) {
3085 assert(num_vals
== 0);
3086 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3090 /* shift result right if needed */
3091 if (info
->component_size
< 4 && byte_align_loads
) {
3092 Operand
align((uint32_t)byte_align
);
3093 if (byte_align
== -1) {
3094 if (offset
.isConstant())
3095 align
= Operand(offset
.constantValue() % 4u);
3096 else if (offset
.size() == 2)
3097 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3102 assert(val
.bytes() >= load_size
&& "unimplemented");
3103 if (val
.type() == RegType::sgpr
)
3104 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3106 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3110 /* add result to list and advance */
3111 if (info
->component_stride
) {
3112 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3113 const_offset
+= info
->component_stride
;
3114 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3116 const_offset
+= val
.bytes();
3117 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3119 bytes_read
+= val
.bytes();
3120 vals
[num_vals
++] = val
;
3123 /* create array of components */
3124 unsigned components_split
= 0;
3125 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3126 bool has_vgprs
= false;
3127 for (unsigned i
= 0; i
< num_vals
;) {
3129 unsigned num_tmps
= 0;
3130 unsigned tmp_size
= 0;
3131 RegType reg_type
= RegType::sgpr
;
3132 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3133 if (vals
[i
].type() == RegType::vgpr
)
3134 reg_type
= RegType::vgpr
;
3135 tmp_size
+= vals
[i
].bytes();
3136 tmp
[num_tmps
++] = vals
[i
++];
3139 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3140 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3141 for (unsigned i
= 0; i
< num_tmps
; i
++)
3142 vec
->operands
[i
] = Operand(tmp
[i
]);
3143 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3144 vec
->definitions
[0] = Definition(tmp
[0]);
3145 bld
.insert(std::move(vec
));
3148 if (tmp
[0].bytes() % component_size
) {
3150 assert(i
== num_vals
);
3151 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3152 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3155 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3157 unsigned start
= components_split
;
3159 if (tmp_size
== elem_rc
.bytes()) {
3160 allocated_vec
[components_split
++] = tmp
[0];
3162 assert(tmp_size
% elem_rc
.bytes() == 0);
3163 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3164 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3165 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3166 Temp component
= bld
.tmp(elem_rc
);
3167 allocated_vec
[components_split
++] = component
;
3168 split
->definitions
[i
] = Definition(component
);
3170 split
->operands
[0] = Operand(tmp
[0]);
3171 bld
.insert(std::move(split
));
3174 /* try to p_as_uniform early so we can create more optimizable code and
3175 * also update allocated_vec */
3176 for (unsigned j
= start
; j
< components_split
; j
++) {
3177 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3178 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3179 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3183 /* concatenate components and p_as_uniform() result if needed */
3184 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3185 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3187 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3189 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3190 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3191 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3192 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3194 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3195 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3196 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3197 vec
->definitions
[0] = Definition(tmp
);
3198 bld
.insert(std::move(vec
));
3199 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3201 vec
->definitions
[0] = Definition(info
->dst
);
3202 bld
.insert(std::move(vec
));
3206 Operand
load_lds_size_m0(Builder
& bld
)
3208 /* TODO: m0 does not need to be initialized on GFX9+ */
3209 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3212 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3213 Temp offset
, unsigned bytes_needed
,
3214 unsigned align
, unsigned const_offset
,
3217 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3219 Operand m
= load_lds_size_m0(bld
);
3221 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3222 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3227 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3228 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3230 op
= aco_opcode::ds_read_b128
;
3231 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3234 op
= aco_opcode::ds_read2_b64
;
3235 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3237 op
= aco_opcode::ds_read_b96
;
3238 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3240 op
= aco_opcode::ds_read_b64
;
3241 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3244 op
= aco_opcode::ds_read2_b32
;
3245 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3247 op
= aco_opcode::ds_read_b32
;
3248 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3250 op
= aco_opcode::ds_read_u16
;
3253 op
= aco_opcode::ds_read_u8
;
3256 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3257 if (const_offset
>= max_offset_plus_one
) {
3258 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3259 const_offset
%= max_offset_plus_one
;
3263 const_offset
/= (size
/ 2u);
3265 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3266 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3269 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3271 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3272 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3275 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3280 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3282 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3283 Temp offset
, unsigned bytes_needed
,
3284 unsigned align
, unsigned const_offset
,
3289 if (bytes_needed
<= 4) {
3291 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3292 } else if (bytes_needed
<= 8) {
3294 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3295 } else if (bytes_needed
<= 16) {
3297 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3298 } else if (bytes_needed
<= 32) {
3300 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3303 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3305 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3306 if (info
->resource
.id()) {
3307 load
->operands
[0] = Operand(info
->resource
);
3308 load
->operands
[1] = Operand(offset
);
3310 load
->operands
[0] = Operand(offset
);
3311 load
->operands
[1] = Operand(0u);
3313 RegClass
rc(RegType::sgpr
, size
);
3314 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3315 load
->definitions
[0] = Definition(val
);
3316 load
->glc
= info
->glc
;
3317 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3318 load
->sync
= info
->sync
;
3319 bld
.insert(std::move(load
));
3323 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3325 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3326 Temp offset
, unsigned bytes_needed
,
3327 unsigned align_
, unsigned const_offset
,
3330 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3331 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3333 if (info
->soffset
.id()) {
3334 if (soffset
.isTemp())
3335 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3336 soffset
= Operand(info
->soffset
);
3339 unsigned bytes_size
= 0;
3341 if (bytes_needed
== 1 || align_
% 2) {
3343 op
= aco_opcode::buffer_load_ubyte
;
3344 } else if (bytes_needed
== 2 || align_
% 4) {
3346 op
= aco_opcode::buffer_load_ushort
;
3347 } else if (bytes_needed
<= 4) {
3349 op
= aco_opcode::buffer_load_dword
;
3350 } else if (bytes_needed
<= 8) {
3352 op
= aco_opcode::buffer_load_dwordx2
;
3353 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3355 op
= aco_opcode::buffer_load_dwordx3
;
3358 op
= aco_opcode::buffer_load_dwordx4
;
3360 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3361 mubuf
->operands
[0] = Operand(info
->resource
);
3362 mubuf
->operands
[1] = vaddr
;
3363 mubuf
->operands
[2] = soffset
;
3364 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3365 mubuf
->glc
= info
->glc
;
3366 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3367 mubuf
->sync
= info
->sync
;
3368 mubuf
->offset
= const_offset
;
3369 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3370 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3371 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3372 mubuf
->definitions
[0] = Definition(val
);
3373 bld
.insert(std::move(mubuf
));
3378 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3379 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3381 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3383 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3384 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3386 if (addr
.type() == RegType::vgpr
)
3387 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3388 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3391 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3392 Temp offset
, unsigned bytes_needed
,
3393 unsigned align_
, unsigned const_offset
,
3396 unsigned bytes_size
= 0;
3397 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3398 bool global
= bld
.program
->chip_class
>= GFX9
;
3400 if (bytes_needed
== 1) {
3402 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3403 } else if (bytes_needed
== 2) {
3405 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3406 } else if (bytes_needed
<= 4) {
3408 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3409 } else if (bytes_needed
<= 8) {
3411 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3412 } else if (bytes_needed
<= 12 && !mubuf
) {
3414 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3417 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3419 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3420 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3422 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3423 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3424 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3425 mubuf
->operands
[2] = Operand(0u);
3426 mubuf
->glc
= info
->glc
;
3429 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3430 mubuf
->disable_wqm
= false;
3431 mubuf
->sync
= info
->sync
;
3432 mubuf
->definitions
[0] = Definition(val
);
3433 bld
.insert(std::move(mubuf
));
3435 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3437 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3438 flat
->operands
[0] = Operand(offset
);
3439 flat
->operands
[1] = Operand(s1
);
3440 flat
->glc
= info
->glc
;
3441 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3442 flat
->sync
= info
->sync
;
3444 flat
->definitions
[0] = Definition(val
);
3445 bld
.insert(std::move(flat
));
3451 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3453 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3454 Temp address
, unsigned base_offset
, unsigned align
)
3456 assert(util_is_power_of_two_nonzero(align
));
3458 Builder
bld(ctx
->program
, ctx
->block
);
3460 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3461 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3462 info
.align_mul
= align
;
3463 info
.align_offset
= 0;
3464 info
.sync
= memory_sync_info(storage_shared
);
3465 info
.const_offset
= base_offset
;
3466 emit_lds_load(ctx
, bld
, &info
);
3471 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3476 Builder
bld(ctx
->program
, ctx
->block
);
3478 ASSERTED
bool is_subdword
= false;
3479 for (unsigned i
= 0; i
< count
; i
++)
3480 is_subdword
|= offsets
[i
] % 4;
3481 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3482 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3484 /* count == 1 fast path */
3486 if (dst_type
== RegType::sgpr
)
3487 dst
[0] = bld
.as_uniform(src
);
3489 dst
[0] = as_vgpr(ctx
, src
);
3493 for (unsigned i
= 0; i
< count
- 1; i
++)
3494 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3495 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3497 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3498 src
= as_vgpr(ctx
, src
);
3500 /* use allocated_vec if possible */
3501 auto it
= ctx
->allocated_vec
.find(src
.id());
3502 if (it
!= ctx
->allocated_vec
.end()) {
3503 if (!it
->second
[0].id())
3505 unsigned elem_size
= it
->second
[0].bytes();
3506 assert(src
.bytes() % elem_size
== 0);
3508 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3509 if (!it
->second
[i
].id())
3513 for (unsigned i
= 0; i
< count
; i
++) {
3514 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3518 for (unsigned i
= 0; i
< count
; i
++) {
3519 unsigned start_idx
= offsets
[i
] / elem_size
;
3520 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3521 if (op_count
== 1) {
3522 if (dst_type
== RegType::sgpr
)
3523 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3525 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3529 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3530 for (unsigned j
= 0; j
< op_count
; j
++) {
3531 Temp tmp
= it
->second
[start_idx
+ j
];
3532 if (dst_type
== RegType::sgpr
)
3533 tmp
= bld
.as_uniform(tmp
);
3534 vec
->operands
[j
] = Operand(tmp
);
3536 vec
->definitions
[0] = Definition(dst
[i
]);
3537 bld
.insert(std::move(vec
));
3545 if (dst_type
== RegType::sgpr
)
3546 src
= bld
.as_uniform(src
);
3549 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3550 split
->operands
[0] = Operand(src
);
3551 for (unsigned i
= 0; i
< count
; i
++)
3552 split
->definitions
[i
] = Definition(dst
[i
]);
3553 bld
.insert(std::move(split
));
3556 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3557 int *start
, int *count
)
3559 unsigned start_elem
= ffs(todo_mask
) - 1;
3560 bool skip
= !(mask
& (1 << start_elem
));
3562 mask
= ~mask
& todo_mask
;
3566 u_bit_scan_consecutive_range(&mask
, start
, count
);
3571 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3573 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3576 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3577 Temp address
, unsigned base_offset
, unsigned align
)
3579 assert(util_is_power_of_two_nonzero(align
));
3580 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3582 Builder
bld(ctx
->program
, ctx
->block
);
3583 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3584 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3586 unsigned write_count
= 0;
3587 Temp write_datas
[32];
3588 unsigned offsets
[32];
3589 aco_opcode opcodes
[32];
3591 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3593 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3596 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3597 offsets
[write_count
] = offset
;
3598 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3600 advance_write_mask(&todo
, offset
, bytes
);
3604 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3605 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3606 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3607 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3609 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3610 aco_opcode op
= aco_opcode::num_opcodes
;
3611 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3612 op
= aco_opcode::ds_write_b128
;
3614 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3615 op
= aco_opcode::ds_write_b96
;
3617 } else if (bytes
>= 8 && aligned8
) {
3618 op
= aco_opcode::ds_write_b64
;
3620 } else if (bytes
>= 4 && aligned4
) {
3621 op
= aco_opcode::ds_write_b32
;
3623 } else if (bytes
>= 2 && aligned2
) {
3624 op
= aco_opcode::ds_write_b16
;
3626 } else if (bytes
>= 1) {
3627 op
= aco_opcode::ds_write_b8
;
3633 offsets
[write_count
] = offset
;
3634 opcodes
[write_count
] = op
;
3636 advance_write_mask(&todo
, offset
, bytes
);
3639 Operand m
= load_lds_size_m0(bld
);
3641 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3643 for (unsigned i
= 0; i
< write_count
; i
++) {
3644 aco_opcode op
= opcodes
[i
];
3645 if (op
== aco_opcode::num_opcodes
)
3648 Temp data
= write_datas
[i
];
3650 unsigned second
= write_count
;
3651 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3652 for (second
= i
+ 1; second
< write_count
; second
++) {
3653 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3654 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3655 opcodes
[second
] = aco_opcode::num_opcodes
;
3661 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3662 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3664 unsigned inline_offset
= base_offset
+ offsets
[i
];
3665 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3666 Temp address_offset
= address
;
3667 if (inline_offset
> max_offset
) {
3668 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3669 inline_offset
= offsets
[i
];
3671 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3675 Temp second_data
= write_datas
[second
];
3676 inline_offset
/= data
.bytes();
3677 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3679 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3681 static_cast<DS_instruction
*>(instr
)->sync
=
3682 memory_sync_info(storage_shared
);
3686 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3688 unsigned align
= 16;
3690 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3696 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3701 return aco_opcode::buffer_store_byte
;
3704 return aco_opcode::buffer_store_short
;
3706 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3708 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3711 return aco_opcode::buffer_store_dwordx3
;
3713 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3715 unreachable("Unexpected store size");
3716 return aco_opcode::num_opcodes
;
3719 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3720 Temp data
, unsigned writemask
, int swizzle_element_size
,
3721 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3723 unsigned write_count_with_skips
= 0;
3726 /* determine how to split the data */
3727 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3730 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3731 offsets
[write_count_with_skips
] = offset
;
3732 if (skips
[write_count_with_skips
]) {
3733 advance_write_mask(&todo
, offset
, bytes
);
3734 write_count_with_skips
++;
3738 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3739 * larger than swizzle_element_size */
3740 bytes
= MIN2(bytes
, swizzle_element_size
);
3742 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3744 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3745 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3748 /* dword or larger stores have to be dword-aligned */
3749 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3750 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3751 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3753 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3755 advance_write_mask(&todo
, offset
, bytes
);
3756 write_count_with_skips
++;
3759 /* actually split data */
3760 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3763 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3766 write_datas
[*write_count
] = write_datas
[i
];
3767 offsets
[*write_count
] = offsets
[i
];
3772 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3773 unsigned split_cnt
= 0u, Temp dst
= Temp())
3775 Builder
bld(ctx
->program
, ctx
->block
);
3776 unsigned dword_size
= elem_size_bytes
/ 4;
3779 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3781 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3782 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3783 instr
->definitions
[0] = Definition(dst
);
3785 for (unsigned i
= 0; i
< cnt
; ++i
) {
3787 assert(arr
[i
].size() == dword_size
);
3788 allocated_vec
[i
] = arr
[i
];
3789 instr
->operands
[i
] = Operand(arr
[i
]);
3791 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3792 allocated_vec
[i
] = zero
;
3793 instr
->operands
[i
] = Operand(zero
);
3797 bld
.insert(std::move(instr
));
3800 emit_split_vector(ctx
, dst
, split_cnt
);
3802 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3807 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3809 if (const_offset
>= 4096) {
3810 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3811 const_offset
%= 4096u;
3814 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3815 else if (unlikely(voffset
.regClass() == s1
))
3816 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3817 else if (likely(voffset
.regClass() == v1
))
3818 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3820 unreachable("Unsupported register class of voffset");
3823 return const_offset
;
3826 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3827 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
3828 bool slc
= false, bool swizzled
= false)
3831 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3832 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3834 Builder
bld(ctx
->program
, ctx
->block
);
3835 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3836 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3838 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3839 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3840 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3841 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
3842 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
3843 /* dlc*/ false, /* slc */ slc
);
3845 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
3848 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3849 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3850 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
3852 Builder
bld(ctx
->program
, ctx
->block
);
3853 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3855 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3857 unsigned write_count
= 0;
3858 Temp write_datas
[32];
3859 unsigned offsets
[32];
3860 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3861 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3863 for (unsigned i
= 0; i
< write_count
; i
++) {
3864 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3865 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
3869 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3870 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3871 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3873 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3874 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3875 assert(!!stride
!= allow_combining
);
3877 Builder
bld(ctx
->program
, ctx
->block
);
3879 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3880 info
.component_stride
= allow_combining
? 0 : stride
;
3882 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3883 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3884 info
.align_offset
= 0;
3885 info
.soffset
= soffset
;
3886 info
.const_offset
= base_const_offset
;
3887 emit_mubuf_load(ctx
, bld
, &info
);
3890 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3892 Builder
bld(ctx
->program
, ctx
->block
);
3893 Temp offset
= base_offset
.first
;
3894 unsigned const_offset
= base_offset
.second
;
3896 if (!nir_src_is_const(*off_src
)) {
3897 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3900 /* Calculate indirect offset with stride */
3901 if (likely(indirect_offset_arg
.regClass() == v1
))
3902 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3903 else if (indirect_offset_arg
.regClass() == s1
)
3904 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3906 unreachable("Unsupported register class of indirect offset");
3908 /* Add to the supplied base offset */
3909 if (offset
.id() == 0)
3910 offset
= with_stride
;
3911 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3912 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3913 else if (offset
.size() == 1 && with_stride
.size() == 1)
3914 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3916 unreachable("Unsupported register class of indirect offset");
3918 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3919 const_offset
+= const_offset_arg
* stride
;
3922 return std::make_pair(offset
, const_offset
);
3925 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3927 Builder
bld(ctx
->program
, ctx
->block
);
3930 if (off1
.first
.id() && off2
.first
.id()) {
3931 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3932 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3933 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3934 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3936 unreachable("Unsupported register class of indirect offset");
3938 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3941 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3944 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3946 Builder
bld(ctx
->program
, ctx
->block
);
3947 unsigned const_offset
= offs
.second
* multiplier
;
3949 if (!offs
.first
.id())
3950 return std::make_pair(offs
.first
, const_offset
);
3952 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3953 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3954 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
3956 return std::make_pair(offset
, const_offset
);
3959 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3961 Builder
bld(ctx
->program
, ctx
->block
);
3963 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3964 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3965 /* component is in bytes */
3966 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3968 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3969 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3970 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3973 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3975 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3978 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3980 Builder
bld(ctx
->program
, ctx
->block
);
3982 switch (ctx
->shader
->info
.stage
) {
3983 case MESA_SHADER_TESS_CTRL
:
3984 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3985 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3986 case MESA_SHADER_TESS_EVAL
:
3987 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3989 unreachable("Unsupported stage in get_tess_rel_patch_id");
3993 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3995 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3996 Builder
bld(ctx
->program
, ctx
->block
);
3998 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3999 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4001 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4003 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4004 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4006 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4007 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4008 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4010 return offset_mul(ctx
, offs
, 4u);
4013 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4015 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4016 Builder
bld(ctx
->program
, ctx
->block
);
4018 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4019 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4020 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4021 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4023 std::pair
<Temp
, unsigned> offs
= instr
4024 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4025 : std::make_pair(Temp(), 0u);
4027 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4028 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4033 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4034 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4036 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4037 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4039 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4040 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4046 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4048 Builder
bld(ctx
->program
, ctx
->block
);
4050 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4051 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4053 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4055 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4056 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4057 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4059 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4060 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4065 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4067 Builder
bld(ctx
->program
, ctx
->block
);
4069 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4070 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4071 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4072 unsigned attr_stride
= ctx
->tcs_num_patches
;
4074 std::pair
<Temp
, unsigned> offs
= instr
4075 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4076 : std::make_pair(Temp(), 0u);
4078 if (const_base_offset
)
4079 offs
.second
+= const_base_offset
* attr_stride
;
4081 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4082 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4083 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4088 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4090 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4095 unsigned drv_loc
= nir_intrinsic_base(instr
);
4096 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4098 if (!nir_src_is_const(*off_src
)) {
4104 uint64_t slot
= per_vertex
4105 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4106 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4107 return (((uint64_t) 1) << slot
) & mask
;
4110 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4112 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4113 unsigned component
= nir_intrinsic_component(instr
);
4114 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4116 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4117 if (off_instr
->type
!= nir_instr_type_load_const
)
4120 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4121 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4123 if (instr
->src
[0].ssa
->bit_size
== 64)
4124 write_mask
= widen_mask(write_mask
, 2);
4126 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4128 for (unsigned i
= 0; i
< 8; ++i
) {
4129 if (write_mask
& (1 << i
)) {
4130 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4131 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4139 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4141 /* Only TCS per-vertex inputs are supported by this function.
4142 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4144 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4147 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4148 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4149 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4150 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4151 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4152 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4157 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4158 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4159 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4164 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4166 Builder
bld(ctx
->program
, ctx
->block
);
4168 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4169 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4170 bool indirect_write
;
4171 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4172 if (temp_only_input
&& !indirect_write
)
4176 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4177 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4178 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4179 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4181 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4182 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4183 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4184 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4185 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4189 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4190 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4191 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4192 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4193 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4194 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4195 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4196 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4197 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4198 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4199 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4200 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4201 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4203 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4204 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4206 unreachable("Invalid LS or ES stage");
4209 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4210 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4211 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4215 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4220 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4221 return off
== ctx
->tcs_tess_lvl_out_loc
||
4222 off
== ctx
->tcs_tess_lvl_in_loc
;
4226 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4228 uint64_t mask
= per_vertex
4229 ? ctx
->program
->info
->tcs
.tes_inputs_read
4230 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4232 bool indirect_write
= false;
4233 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4234 return indirect_write
|| output_read_by_tes
;
4237 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4239 uint64_t mask
= per_vertex
4240 ? ctx
->shader
->info
.outputs_read
4241 : ctx
->shader
->info
.patch_outputs_read
;
4243 bool indirect_write
= false;
4244 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4245 return indirect_write
|| output_read
;
4248 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4250 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4251 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4253 Builder
bld(ctx
->program
, ctx
->block
);
4255 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4256 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4257 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4259 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4260 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4261 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4263 if (write_to_vmem
) {
4264 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4265 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4266 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4268 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4269 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4270 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4274 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4275 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4276 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4280 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4282 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4283 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4285 Builder
bld(ctx
->program
, ctx
->block
);
4287 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4288 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4289 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4290 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4292 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4295 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4297 if (ctx
->stage
== vertex_vs
||
4298 ctx
->stage
== tess_eval_vs
||
4299 ctx
->stage
== fragment_fs
||
4300 ctx
->stage
== ngg_vertex_gs
||
4301 ctx
->stage
== ngg_tess_eval_gs
||
4302 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4303 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4304 if (!stored_to_temps
) {
4305 isel_err(instr
->src
[1].ssa
->parent_instr
, "Unimplemented output offset instruction");
4308 } else if (ctx
->stage
== vertex_es
||
4309 ctx
->stage
== vertex_ls
||
4310 ctx
->stage
== tess_eval_es
||
4311 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4312 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4313 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4314 visit_store_ls_or_es_output(ctx
, instr
);
4315 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4316 visit_store_tcs_output(ctx
, instr
, false);
4318 unreachable("Shader stage not implemented");
4322 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4324 visit_load_tcs_output(ctx
, instr
, false);
4327 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4329 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4330 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4332 Builder
bld(ctx
->program
, ctx
->block
);
4334 if (dst
.regClass() == v2b
) {
4335 if (ctx
->program
->has_16bank_lds
) {
4336 assert(ctx
->options
->chip_class
<= GFX8
);
4337 Builder::Result interp_p1
=
4338 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4339 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4340 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4341 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4342 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4343 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4345 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4347 if (ctx
->options
->chip_class
== GFX8
)
4348 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4350 Builder::Result interp_p1
=
4351 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4352 coord1
, bld
.m0(prim_mask
), idx
, component
);
4353 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4354 interp_p1
, idx
, component
);
4357 Builder::Result interp_p1
=
4358 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4359 bld
.m0(prim_mask
), idx
, component
);
4361 if (ctx
->program
->has_16bank_lds
)
4362 interp_p1
.instr
->operands
[0].setLateKill(true);
4364 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4365 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4369 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4371 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4372 for (unsigned i
= 0; i
< num_components
; i
++)
4373 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4374 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4375 assert(num_components
== 4);
4376 Builder
bld(ctx
->program
, ctx
->block
);
4377 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4380 for (Operand
& op
: vec
->operands
)
4381 op
= op
.isUndefined() ? Operand(0u) : op
;
4383 vec
->definitions
[0] = Definition(dst
);
4384 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4385 emit_split_vector(ctx
, dst
, num_components
);
4389 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4391 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4392 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4393 unsigned idx
= nir_intrinsic_base(instr
);
4394 unsigned component
= nir_intrinsic_component(instr
);
4395 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4397 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4399 assert(offset
->u32
== 0);
4401 /* the lower 15bit of the prim_mask contain the offset into LDS
4402 * while the upper bits contain the number of prims */
4403 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4404 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4405 Builder
bld(ctx
->program
, ctx
->block
);
4406 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4407 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4408 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4409 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4410 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4413 if (instr
->dest
.ssa
.num_components
== 1) {
4414 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4416 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4417 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4419 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4420 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4421 vec
->operands
[i
] = Operand(tmp
);
4423 vec
->definitions
[0] = Definition(dst
);
4424 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4428 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4429 unsigned offset
, unsigned stride
, unsigned channels
)
4431 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4432 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4434 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4435 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4438 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4439 unsigned offset
, unsigned stride
, unsigned *channels
)
4441 if (!vtx_info
->chan_byte_size
) {
4442 *channels
= vtx_info
->num_channels
;
4443 return vtx_info
->chan_format
;
4446 unsigned num_channels
= *channels
;
4447 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4448 unsigned new_channels
= num_channels
+ 1;
4449 /* first, assume more loads is worse and try using a larger data format */
4450 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4452 /* don't make the attribute potentially out-of-bounds */
4453 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4457 if (new_channels
== 5) {
4458 /* then try decreasing load size (at the cost of more loads) */
4459 new_channels
= *channels
;
4460 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4464 if (new_channels
< *channels
)
4465 *channels
= new_channels
;
4466 num_channels
= new_channels
;
4469 switch (vtx_info
->chan_format
) {
4470 case V_008F0C_BUF_DATA_FORMAT_8
:
4471 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4472 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4473 case V_008F0C_BUF_DATA_FORMAT_16
:
4474 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4475 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4476 case V_008F0C_BUF_DATA_FORMAT_32
:
4477 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4478 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4480 unreachable("shouldn't reach here");
4481 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4484 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4485 * so we may need to fix it up. */
4486 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4488 Builder
bld(ctx
->program
, ctx
->block
);
4490 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4491 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4493 /* For the integer-like cases, do a natural sign extension.
4495 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4496 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4499 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4500 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4502 /* Convert back to the right type. */
4503 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4504 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4505 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4506 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4507 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4508 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4514 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4516 Builder
bld(ctx
->program
, ctx
->block
);
4517 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4518 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4520 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4521 if (off_instr
->type
!= nir_instr_type_load_const
) {
4522 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4524 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4526 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4528 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4529 unsigned component
= nir_intrinsic_component(instr
);
4530 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4531 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4532 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4533 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4534 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4536 unsigned dfmt
= attrib_format
& 0xf;
4537 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4538 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4540 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4541 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4542 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4543 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4545 num_channels
= MAX2(num_channels
, 3);
4547 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4548 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4551 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4552 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4553 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4555 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4557 Temp divided
= bld
.tmp(v1
);
4558 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4559 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4561 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4564 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4567 index
= bld
.vadd32(bld
.def(v1
),
4568 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4569 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4572 Temp channels
[num_channels
];
4573 unsigned channel_start
= 0;
4574 bool direct_fetch
= false;
4576 /* skip unused channels at the start */
4577 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4578 channel_start
= ffs(mask
) - 1;
4579 for (unsigned i
= 0; i
< channel_start
; i
++)
4580 channels
[i
] = Temp(0, s1
);
4581 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4582 num_channels
= 3 - (ffs(mask
) - 1);
4586 while (channel_start
< num_channels
) {
4587 unsigned fetch_component
= num_channels
- channel_start
;
4588 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4589 bool expanded
= false;
4591 /* use MUBUF when possible to avoid possible alignment issues */
4592 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4593 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4594 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4595 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4596 vtx_info
->chan_byte_size
== 4;
4597 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4599 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4601 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4602 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4603 fetch_component
= 4;
4608 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4610 Temp fetch_index
= index
;
4611 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4612 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4613 fetch_offset
= fetch_offset
% attrib_stride
;
4616 Operand
soffset(0u);
4617 if (fetch_offset
>= 4096) {
4618 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4619 fetch_offset
%= 4096;
4623 switch (fetch_bytes
) {
4625 assert(!use_mubuf
&& bitsize
== 16);
4626 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4629 if (bitsize
== 16) {
4631 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4633 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4637 assert(!use_mubuf
&& bitsize
== 16);
4638 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4641 if (bitsize
== 16) {
4643 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4645 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4649 assert(ctx
->options
->chip_class
>= GFX7
||
4650 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4651 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4654 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4657 unreachable("Unimplemented load_input vector size");
4661 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4662 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4663 num_channels
<= 3)) {
4664 direct_fetch
= true;
4667 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4672 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4673 fetch_offset
, false, false, true).instr
;
4676 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4677 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4680 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4682 if (fetch_component
== 1) {
4683 channels
[channel_start
] = fetch_dst
;
4685 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4686 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4687 bitsize
== 16 ? v2b
: v1
);
4690 channel_start
+= fetch_component
;
4693 if (!direct_fetch
) {
4694 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4695 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4697 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4698 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4699 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4701 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4702 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4703 unsigned num_temp
= 0;
4704 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4705 unsigned idx
= i
+ component
;
4706 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4707 Temp channel
= channels
[swizzle
[idx
]];
4708 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4709 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4710 vec
->operands
[i
] = Operand(channel
);
4714 } else if (is_float
&& idx
== 3) {
4715 vec
->operands
[i
] = Operand(0x3f800000u
);
4716 } else if (!is_float
&& idx
== 3) {
4717 vec
->operands
[i
] = Operand(1u);
4719 vec
->operands
[i
] = Operand(0u);
4722 vec
->definitions
[0] = Definition(dst
);
4723 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4724 emit_split_vector(ctx
, dst
, dst
.size());
4726 if (num_temp
== dst
.size())
4727 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4729 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4730 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4731 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4732 if (off_instr
->type
!= nir_instr_type_load_const
||
4733 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4734 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4737 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4738 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4740 assert(offset
->u32
== 0);
4742 /* the lower 15bit of the prim_mask contain the offset into LDS
4743 * while the upper bits contain the number of prims */
4744 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4745 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4746 Builder
bld(ctx
->program
, ctx
->block
);
4747 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4748 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4749 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4750 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4751 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4754 unsigned idx
= nir_intrinsic_base(instr
);
4755 unsigned component
= nir_intrinsic_component(instr
);
4756 unsigned vertex_id
= 2; /* P0 */
4758 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4759 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4760 switch (src0
->u32
) {
4762 vertex_id
= 2; /* P0 */
4765 vertex_id
= 0; /* P10 */
4768 vertex_id
= 1; /* P20 */
4771 unreachable("invalid vertex index");
4775 if (dst
.size() == 1) {
4776 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4778 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4779 for (unsigned i
= 0; i
< dst
.size(); i
++)
4780 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4781 vec
->definitions
[0] = Definition(dst
);
4782 bld
.insert(std::move(vec
));
4785 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4786 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4787 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4788 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4789 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4791 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4793 unreachable("Shader stage not implemented");
4797 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4799 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4801 Builder
bld(ctx
->program
, ctx
->block
);
4802 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4805 if (!nir_src_is_const(*vertex_src
)) {
4806 /* better code could be created, but this case probably doesn't happen
4807 * much in practice */
4808 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4809 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4812 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4813 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4815 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4817 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4820 if (vertex_offset
.id()) {
4821 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4822 Operand(i
), indirect_vertex
);
4823 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4825 vertex_offset
= elem
;
4829 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4830 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4832 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4833 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4834 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4835 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4836 Operand((vertex
% 2u) * 16u), Operand(16u));
4838 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4841 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4842 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4843 return offset_mul(ctx
, offs
, 4u);
4846 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4848 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4850 Builder
bld(ctx
->program
, ctx
->block
);
4851 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4852 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4854 if (ctx
->stage
== geometry_gs
) {
4855 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4856 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4857 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4858 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4859 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4860 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4861 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4863 unreachable("Unsupported GS stage.");
4867 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4869 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4871 Builder
bld(ctx
->program
, ctx
->block
);
4872 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4874 if (load_input_from_temps(ctx
, instr
, dst
))
4877 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4878 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4879 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4881 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4884 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4886 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4888 Builder
bld(ctx
->program
, ctx
->block
);
4890 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4891 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4892 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4894 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4895 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4897 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4900 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4902 switch (ctx
->shader
->info
.stage
) {
4903 case MESA_SHADER_GEOMETRY
:
4904 visit_load_gs_per_vertex_input(ctx
, instr
);
4906 case MESA_SHADER_TESS_CTRL
:
4907 visit_load_tcs_per_vertex_input(ctx
, instr
);
4909 case MESA_SHADER_TESS_EVAL
:
4910 visit_load_tes_per_vertex_input(ctx
, instr
);
4913 unreachable("Unimplemented shader stage");
4917 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4919 visit_load_tcs_output(ctx
, instr
, true);
4922 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4924 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4925 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4927 visit_store_tcs_output(ctx
, instr
, true);
4930 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4932 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4934 Builder
bld(ctx
->program
, ctx
->block
);
4935 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4937 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4938 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4941 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4942 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4943 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4944 tes_w
= Operand(tmp
);
4947 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4948 emit_split_vector(ctx
, tess_coord
, 3);
4951 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4953 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4954 Builder
bld(ctx
->program
, ctx
->block
);
4955 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4956 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4957 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4960 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4964 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4966 Builder
bld(ctx
->program
, ctx
->block
);
4967 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4968 if (!nir_dest_is_divergent(instr
->dest
))
4969 index
= bld
.as_uniform(index
);
4970 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4971 unsigned binding
= nir_intrinsic_binding(instr
);
4974 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4975 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4976 unsigned offset
= layout
->binding
[binding
].offset
;
4978 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4979 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4980 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4981 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4982 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4985 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4986 stride
= layout
->binding
[binding
].size
;
4989 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4990 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4992 if (nir_const_index
) {
4993 const_index
= const_index
* stride
;
4994 } else if (index
.type() == RegType::vgpr
) {
4995 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4996 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4998 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5002 if (nir_const_index
) {
5003 const_index
= const_index
+ offset
;
5004 } else if (index
.type() == RegType::vgpr
) {
5005 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5007 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5011 if (nir_const_index
&& const_index
== 0) {
5013 } else if (index
.type() == RegType::vgpr
) {
5014 index
= bld
.vadd32(bld
.def(v1
),
5015 nir_const_index
? Operand(const_index
) : Operand(index
),
5018 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5019 nir_const_index
? Operand(const_index
) : Operand(index
),
5023 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5026 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5027 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5028 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5030 Builder
bld(ctx
->program
, ctx
->block
);
5032 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5034 offset
= bld
.as_uniform(offset
);
5036 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5039 info
.align_mul
= align_mul
;
5040 info
.align_offset
= align_offset
;
5042 emit_smem_load(ctx
, bld
, &info
);
5044 emit_mubuf_load(ctx
, bld
, &info
);
5047 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5049 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5050 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5052 Builder
bld(ctx
->program
, ctx
->block
);
5054 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5055 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5056 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5057 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5059 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5060 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5061 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5062 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5063 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5064 if (ctx
->options
->chip_class
>= GFX10
) {
5065 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5066 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5067 S_008F0C_RESOURCE_LEVEL(1);
5069 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5070 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5072 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5073 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5074 Operand(0xFFFFFFFFu
),
5075 Operand(desc_type
));
5076 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5077 rsrc
, upper_dwords
);
5079 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5080 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5082 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5083 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5084 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5087 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5089 Builder
bld(ctx
->program
, ctx
->block
);
5090 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5091 unsigned offset
= nir_intrinsic_base(instr
);
5092 unsigned count
= instr
->dest
.ssa
.num_components
;
5093 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5095 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5096 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5097 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5098 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5099 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5100 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5101 for (unsigned i
= 0; i
< count
; ++i
) {
5102 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5103 vec
->operands
[i
] = Operand
{elems
[i
]};
5105 vec
->definitions
[0] = Definition(dst
);
5106 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5107 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5112 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5113 if (offset
!= 0) // TODO check if index != 0 as well
5114 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5115 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5118 bool aligned
= true;
5120 if (instr
->dest
.ssa
.bit_size
== 8) {
5121 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5122 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5124 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5125 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5126 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5128 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5133 switch (vec
.size()) {
5135 op
= aco_opcode::s_load_dword
;
5138 op
= aco_opcode::s_load_dwordx2
;
5144 op
= aco_opcode::s_load_dwordx4
;
5150 op
= aco_opcode::s_load_dwordx8
;
5153 unreachable("unimplemented or forbidden load_push_constant.");
5156 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5159 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5160 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5165 emit_split_vector(ctx
, vec
, 4);
5166 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5167 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5168 emit_extract_vector(ctx
, vec
, 0, rc
),
5169 emit_extract_vector(ctx
, vec
, 1, rc
),
5170 emit_extract_vector(ctx
, vec
, 2, rc
));
5173 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5176 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5178 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5180 Builder
bld(ctx
->program
, ctx
->block
);
5182 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5183 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5184 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5185 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5186 if (ctx
->options
->chip_class
>= GFX10
) {
5187 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5188 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5189 S_008F0C_RESOURCE_LEVEL(1);
5191 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5192 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5195 unsigned base
= nir_intrinsic_base(instr
);
5196 unsigned range
= nir_intrinsic_range(instr
);
5198 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5199 if (base
&& offset
.type() == RegType::sgpr
)
5200 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5201 else if (base
&& offset
.type() == RegType::vgpr
)
5202 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5204 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5205 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5206 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5207 Operand(desc_type
));
5208 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5209 // TODO: get alignment information for subdword constants
5210 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5213 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5215 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5216 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5218 ctx
->program
->needs_exact
= true;
5220 // TODO: optimize uniform conditions
5221 Builder
bld(ctx
->program
, ctx
->block
);
5222 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5223 assert(src
.regClass() == bld
.lm
);
5224 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5225 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5226 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5230 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5232 Builder
bld(ctx
->program
, ctx
->block
);
5234 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5235 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5237 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5238 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5240 if (ctx
->block
->loop_nest_depth
&&
5241 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5242 /* we handle discards the same way as jump instructions */
5243 append_logical_end(ctx
->block
);
5245 /* in loops, discard behaves like break */
5246 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5247 ctx
->block
->kind
|= block_kind_discard
;
5250 /* uniform discard - loop ends here */
5251 assert(nir_instr_is_last(&instr
->instr
));
5252 ctx
->block
->kind
|= block_kind_uniform
;
5253 ctx
->cf_info
.has_branch
= true;
5254 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5255 add_linear_edge(ctx
->block
->index
, linear_target
);
5259 /* we add a break right behind the discard() instructions */
5260 ctx
->block
->kind
|= block_kind_break
;
5261 unsigned idx
= ctx
->block
->index
;
5263 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5264 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5266 /* remove critical edges from linear CFG */
5267 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5268 Block
* break_block
= ctx
->program
->create_and_insert_block();
5269 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5270 break_block
->kind
|= block_kind_uniform
;
5271 add_linear_edge(idx
, break_block
);
5272 add_linear_edge(break_block
->index
, linear_target
);
5273 bld
.reset(break_block
);
5274 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5276 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5277 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5278 add_linear_edge(idx
, continue_block
);
5279 append_logical_start(continue_block
);
5280 ctx
->block
= continue_block
;
5285 /* it can currently happen that NIR doesn't remove the unreachable code */
5286 if (!nir_instr_is_last(&instr
->instr
)) {
5287 ctx
->program
->needs_exact
= true;
5288 /* save exec somewhere temporarily so that it doesn't get
5289 * overwritten before the discard from outer exec masks */
5290 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5291 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5292 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5296 /* This condition is incorrect for uniformly branched discards in a loop
5297 * predicated by a divergent condition, but the above code catches that case
5298 * and the discard would end up turning into a discard_if.
5308 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5309 /* program just ends here */
5310 ctx
->block
->kind
|= block_kind_uniform
;
5311 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5312 0 /* enabled mask */, 9 /* dest */,
5313 false /* compressed */, true/* done */, true /* valid mask */);
5314 bld
.sopp(aco_opcode::s_endpgm
);
5315 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5317 ctx
->block
->kind
|= block_kind_discard
;
5318 /* branch and linear edge is added by visit_if() */
5322 enum aco_descriptor_type
{
5333 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5334 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5336 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5337 return dim
== ac_image_cube
||
5338 dim
== ac_image_1darray
||
5339 dim
== ac_image_2darray
||
5340 dim
== ac_image_2darraymsaa
;
5343 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5344 enum aco_descriptor_type desc_type
,
5345 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5347 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5348 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5349 if (it != ctx->tex_desc.end())
5352 Temp index
= Temp();
5353 bool index_set
= false;
5354 unsigned constant_index
= 0;
5355 unsigned descriptor_set
;
5356 unsigned base_index
;
5357 Builder
bld(ctx
->program
, ctx
->block
);
5360 assert(tex_instr
&& !image
);
5362 base_index
= tex_instr
->sampler_index
;
5364 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5365 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5369 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5370 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5372 constant_index
+= array_size
* const_value
->u32
;
5374 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5375 if (indirect
.type() == RegType::vgpr
)
5376 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5378 if (array_size
!= 1)
5379 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5385 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5389 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5391 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5392 base_index
= deref_instr
->var
->data
.binding
;
5395 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5396 list
= convert_pointer_to_64_bit(ctx
, list
);
5398 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5399 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5400 unsigned offset
= binding
->offset
;
5401 unsigned stride
= binding
->size
;
5405 assert(base_index
< layout
->binding_count
);
5407 switch (desc_type
) {
5408 case ACO_DESC_IMAGE
:
5410 opcode
= aco_opcode::s_load_dwordx8
;
5412 case ACO_DESC_FMASK
:
5414 opcode
= aco_opcode::s_load_dwordx8
;
5417 case ACO_DESC_SAMPLER
:
5419 opcode
= aco_opcode::s_load_dwordx4
;
5420 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5421 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5423 case ACO_DESC_BUFFER
:
5425 opcode
= aco_opcode::s_load_dwordx4
;
5427 case ACO_DESC_PLANE_0
:
5428 case ACO_DESC_PLANE_1
:
5430 opcode
= aco_opcode::s_load_dwordx8
;
5431 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5433 case ACO_DESC_PLANE_2
:
5435 opcode
= aco_opcode::s_load_dwordx4
;
5439 unreachable("invalid desc_type\n");
5442 offset
+= constant_index
* stride
;
5444 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5445 (!index_set
|| binding
->immutable_samplers_equal
)) {
5446 if (binding
->immutable_samplers_equal
)
5449 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5450 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5451 Operand(samplers
[constant_index
* 4 + 0]),
5452 Operand(samplers
[constant_index
* 4 + 1]),
5453 Operand(samplers
[constant_index
* 4 + 2]),
5454 Operand(samplers
[constant_index
* 4 + 3]));
5459 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5461 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5462 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5465 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5467 if (desc_type
== ACO_DESC_PLANE_2
) {
5469 for (unsigned i
= 0; i
< 8; i
++)
5470 components
[i
] = bld
.tmp(s1
);
5471 bld
.pseudo(aco_opcode::p_split_vector
,
5472 Definition(components
[0]),
5473 Definition(components
[1]),
5474 Definition(components
[2]),
5475 Definition(components
[3]),
5478 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5479 bld
.pseudo(aco_opcode::p_split_vector
,
5480 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5481 Definition(components
[4]),
5482 Definition(components
[5]),
5483 Definition(components
[6]),
5484 Definition(components
[7]),
5487 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5488 components
[0], components
[1], components
[2], components
[3],
5489 components
[4], components
[5], components
[6], components
[7]);
5495 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5498 case GLSL_SAMPLER_DIM_BUF
:
5500 case GLSL_SAMPLER_DIM_1D
:
5501 return array
? 2 : 1;
5502 case GLSL_SAMPLER_DIM_2D
:
5503 return array
? 3 : 2;
5504 case GLSL_SAMPLER_DIM_MS
:
5505 return array
? 4 : 3;
5506 case GLSL_SAMPLER_DIM_3D
:
5507 case GLSL_SAMPLER_DIM_CUBE
:
5509 case GLSL_SAMPLER_DIM_RECT
:
5510 case GLSL_SAMPLER_DIM_SUBPASS
:
5512 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5521 /* Adjust the sample index according to FMASK.
5523 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5524 * which is the identity mapping. Each nibble says which physical sample
5525 * should be fetched to get that sample.
5527 * For example, 0x11111100 means there are only 2 samples stored and
5528 * the second sample covers 3/4 of the pixel. When reading samples 0
5529 * and 1, return physical sample 0 (determined by the first two 0s
5530 * in FMASK), otherwise return physical sample 1.
5532 * The sample index should be adjusted as follows:
5533 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5535 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5537 Builder
bld(ctx
->program
, ctx
->block
);
5538 Temp fmask
= bld
.tmp(v1
);
5539 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5540 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5543 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5544 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5545 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5546 load
->operands
[0] = Operand(fmask_desc_ptr
);
5547 load
->operands
[1] = Operand(s4
); /* no sampler */
5548 load
->operands
[2] = Operand(coord
);
5549 load
->definitions
[0] = Definition(fmask
);
5556 ctx
->block
->instructions
.emplace_back(std::move(load
));
5558 Operand sample_index4
;
5559 if (sample_index
.isConstant()) {
5560 if (sample_index
.constantValue() < 16) {
5561 sample_index4
= Operand(sample_index
.constantValue() << 2);
5563 sample_index4
= Operand(0u);
5565 } else if (sample_index
.regClass() == s1
) {
5566 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5568 assert(sample_index
.regClass() == v1
);
5569 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5573 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5574 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5575 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5576 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5578 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5580 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5581 * resource descriptor is 0 (invalid),
5583 Temp compare
= bld
.tmp(bld
.lm
);
5584 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5585 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5587 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5589 /* Replace the MSAA sample index. */
5590 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5593 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5596 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5597 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5598 bool is_array
= glsl_sampler_type_is_array(type
);
5599 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5600 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5601 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5602 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5603 int count
= image_type_to_components_count(dim
, is_array
);
5604 std::vector
<Temp
> coords(count
);
5605 Builder
bld(ctx
->program
, ctx
->block
);
5609 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5610 /* get sample index */
5611 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5612 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5613 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5614 std::vector
<Temp
> fmask_load_address
;
5615 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5616 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5618 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5619 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5621 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5626 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5627 coords
.resize(coords
.size() + 1);
5628 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5630 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5632 for (int i
= 0; i
< count
; i
++)
5633 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5636 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5637 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5638 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5639 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5642 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5645 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5646 for (unsigned i
= 0; i
< coords
.size(); i
++)
5647 vec
->operands
[i
] = Operand(coords
[i
]);
5648 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5649 vec
->definitions
[0] = Definition(res
);
5650 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5655 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5657 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5658 if (semantics
& semantic_atomicrmw
)
5659 return memory_sync_info(storage
, semantics
);
5661 unsigned access
= nir_intrinsic_access(instr
);
5663 if (access
& ACCESS_VOLATILE
)
5664 semantics
|= semantic_volatile
;
5665 if (access
& ACCESS_CAN_REORDER
)
5666 semantics
|= semantic_can_reorder
| semantic_private
;
5668 return memory_sync_info(storage
, semantics
);
5671 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5673 Builder
bld(ctx
->program
, ctx
->block
);
5674 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5675 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5676 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5677 bool is_array
= glsl_sampler_type_is_array(type
);
5678 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5680 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5681 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5683 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5684 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5685 unsigned num_channels
= util_last_bit(mask
);
5686 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5687 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5690 switch (num_channels
) {
5692 opcode
= aco_opcode::buffer_load_format_x
;
5695 opcode
= aco_opcode::buffer_load_format_xy
;
5698 opcode
= aco_opcode::buffer_load_format_xyz
;
5701 opcode
= aco_opcode::buffer_load_format_xyzw
;
5704 unreachable(">4 channel buffer image load");
5706 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5707 load
->operands
[0] = Operand(rsrc
);
5708 load
->operands
[1] = Operand(vindex
);
5709 load
->operands
[2] = Operand((uint32_t) 0);
5711 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5714 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5715 load
->definitions
[0] = Definition(tmp
);
5717 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5718 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5720 ctx
->block
->instructions
.emplace_back(std::move(load
));
5722 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5726 Temp coords
= get_image_coords(ctx
, instr
, type
);
5727 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5729 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5730 unsigned num_components
= util_bitcount(dmask
);
5732 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5735 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5737 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5738 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5740 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5741 load
->operands
[0] = Operand(resource
);
5742 load
->operands
[1] = Operand(s4
); /* no sampler */
5743 load
->operands
[2] = Operand(coords
);
5744 load
->definitions
[0] = Definition(tmp
);
5745 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5746 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5747 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5748 load
->dmask
= dmask
;
5750 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5752 ctx
->block
->instructions
.emplace_back(std::move(load
));
5754 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5758 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5760 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5761 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5762 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5763 bool is_array
= glsl_sampler_type_is_array(type
);
5764 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5766 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5767 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5768 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5770 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5771 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5772 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5774 switch (data
.size()) {
5776 opcode
= aco_opcode::buffer_store_format_x
;
5779 opcode
= aco_opcode::buffer_store_format_xy
;
5782 opcode
= aco_opcode::buffer_store_format_xyz
;
5785 opcode
= aco_opcode::buffer_store_format_xyzw
;
5788 unreachable(">4 channel buffer image store");
5790 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5791 store
->operands
[0] = Operand(rsrc
);
5792 store
->operands
[1] = Operand(vindex
);
5793 store
->operands
[2] = Operand((uint32_t) 0);
5794 store
->operands
[3] = Operand(data
);
5795 store
->idxen
= true;
5798 store
->disable_wqm
= true;
5800 ctx
->program
->needs_exact
= true;
5801 ctx
->block
->instructions
.emplace_back(std::move(store
));
5805 assert(data
.type() == RegType::vgpr
);
5806 Temp coords
= get_image_coords(ctx
, instr
, type
);
5807 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5809 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5810 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5812 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5813 store
->operands
[0] = Operand(resource
);
5814 store
->operands
[1] = Operand(data
);
5815 store
->operands
[2] = Operand(coords
);
5818 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5819 store
->dmask
= (1 << data
.size()) - 1;
5821 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5822 store
->disable_wqm
= true;
5824 ctx
->program
->needs_exact
= true;
5825 ctx
->block
->instructions
.emplace_back(std::move(store
));
5829 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5831 /* return the previous value if dest is ever used */
5832 bool return_previous
= false;
5833 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5834 return_previous
= true;
5837 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5838 return_previous
= true;
5842 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5843 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5844 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5845 bool is_array
= glsl_sampler_type_is_array(type
);
5846 Builder
bld(ctx
->program
, ctx
->block
);
5848 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5849 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5851 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5852 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5854 aco_opcode buf_op
, image_op
;
5855 switch (instr
->intrinsic
) {
5856 case nir_intrinsic_image_deref_atomic_add
:
5857 buf_op
= aco_opcode::buffer_atomic_add
;
5858 image_op
= aco_opcode::image_atomic_add
;
5860 case nir_intrinsic_image_deref_atomic_umin
:
5861 buf_op
= aco_opcode::buffer_atomic_umin
;
5862 image_op
= aco_opcode::image_atomic_umin
;
5864 case nir_intrinsic_image_deref_atomic_imin
:
5865 buf_op
= aco_opcode::buffer_atomic_smin
;
5866 image_op
= aco_opcode::image_atomic_smin
;
5868 case nir_intrinsic_image_deref_atomic_umax
:
5869 buf_op
= aco_opcode::buffer_atomic_umax
;
5870 image_op
= aco_opcode::image_atomic_umax
;
5872 case nir_intrinsic_image_deref_atomic_imax
:
5873 buf_op
= aco_opcode::buffer_atomic_smax
;
5874 image_op
= aco_opcode::image_atomic_smax
;
5876 case nir_intrinsic_image_deref_atomic_and
:
5877 buf_op
= aco_opcode::buffer_atomic_and
;
5878 image_op
= aco_opcode::image_atomic_and
;
5880 case nir_intrinsic_image_deref_atomic_or
:
5881 buf_op
= aco_opcode::buffer_atomic_or
;
5882 image_op
= aco_opcode::image_atomic_or
;
5884 case nir_intrinsic_image_deref_atomic_xor
:
5885 buf_op
= aco_opcode::buffer_atomic_xor
;
5886 image_op
= aco_opcode::image_atomic_xor
;
5888 case nir_intrinsic_image_deref_atomic_exchange
:
5889 buf_op
= aco_opcode::buffer_atomic_swap
;
5890 image_op
= aco_opcode::image_atomic_swap
;
5892 case nir_intrinsic_image_deref_atomic_comp_swap
:
5893 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5894 image_op
= aco_opcode::image_atomic_cmpswap
;
5897 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5900 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5901 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
5903 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5904 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5905 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5906 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5907 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5908 mubuf
->operands
[0] = Operand(resource
);
5909 mubuf
->operands
[1] = Operand(vindex
);
5910 mubuf
->operands
[2] = Operand((uint32_t)0);
5911 mubuf
->operands
[3] = Operand(data
);
5912 if (return_previous
)
5913 mubuf
->definitions
[0] = Definition(dst
);
5915 mubuf
->idxen
= true;
5916 mubuf
->glc
= return_previous
;
5917 mubuf
->dlc
= false; /* Not needed for atomics */
5918 mubuf
->disable_wqm
= true;
5920 ctx
->program
->needs_exact
= true;
5921 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5925 Temp coords
= get_image_coords(ctx
, instr
, type
);
5926 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5927 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5928 mimg
->operands
[0] = Operand(resource
);
5929 mimg
->operands
[1] = Operand(data
);
5930 mimg
->operands
[2] = Operand(coords
);
5931 if (return_previous
)
5932 mimg
->definitions
[0] = Definition(dst
);
5933 mimg
->glc
= return_previous
;
5934 mimg
->dlc
= false; /* Not needed for atomics */
5935 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5936 mimg
->dmask
= (1 << data
.size()) - 1;
5938 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5939 mimg
->disable_wqm
= true;
5941 ctx
->program
->needs_exact
= true;
5942 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5946 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5948 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5949 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5950 Builder
bld(ctx
->program
, ctx
->block
);
5952 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5954 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5955 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5957 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5958 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5960 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5961 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5963 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5964 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5965 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5966 if (dst
.type() == RegType::vgpr
)
5967 bld
.copy(Definition(dst
), shr_dst
);
5969 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5971 emit_extract_vector(ctx
, desc
, 2, dst
);
5975 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5977 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5978 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5979 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5980 bool is_array
= glsl_sampler_type_is_array(type
);
5981 Builder
bld(ctx
->program
, ctx
->block
);
5983 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5984 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5985 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5989 assert(nir_src_as_uint(instr
->src
[1]) == 0);
5990 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5993 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5995 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5997 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5998 mimg
->operands
[0] = Operand(resource
);
5999 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6000 mimg
->operands
[2] = Operand(lod
);
6001 uint8_t& dmask
= mimg
->dmask
;
6002 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6003 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6004 mimg
->da
= glsl_sampler_type_is_array(type
);
6005 Definition
& def
= mimg
->definitions
[0];
6006 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6008 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6009 glsl_sampler_type_is_array(type
)) {
6011 assert(instr
->dest
.ssa
.num_components
== 3);
6012 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6013 def
= Definition(tmp
);
6014 emit_split_vector(ctx
, tmp
, 3);
6016 /* divide 3rd value by 6 by multiplying with magic number */
6017 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6018 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6020 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6021 emit_extract_vector(ctx
, tmp
, 0, v1
),
6022 emit_extract_vector(ctx
, tmp
, 1, v1
),
6025 } else if (ctx
->options
->chip_class
== GFX9
&&
6026 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6027 glsl_sampler_type_is_array(type
)) {
6028 assert(instr
->dest
.ssa
.num_components
== 2);
6029 def
= Definition(dst
);
6032 def
= Definition(dst
);
6035 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6038 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6040 Builder
bld(ctx
->program
, ctx
->block
);
6041 unsigned num_components
= instr
->num_components
;
6043 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6044 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6045 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6047 unsigned access
= nir_intrinsic_access(instr
);
6048 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6049 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6051 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6052 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6053 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6055 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6056 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6058 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6059 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6060 get_memory_sync_info(instr
, storage_buffer
, 0));
6063 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6065 Builder
bld(ctx
->program
, ctx
->block
);
6066 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6067 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6068 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6069 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6071 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6072 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6074 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6075 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6076 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6077 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6078 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6080 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6082 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6083 ctx
->options
->chip_class
>= GFX8
&&
6084 ctx
->options
->chip_class
< GFX10_3
&&
6085 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6088 offset
= bld
.as_uniform(offset
);
6089 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6091 unsigned write_count
= 0;
6092 Temp write_datas
[32];
6093 unsigned offsets
[32];
6094 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6095 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6097 for (unsigned i
= 0; i
< write_count
; i
++) {
6098 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6099 if (smem
&& ctx
->stage
== fragment_fs
)
6100 op
= aco_opcode::p_fs_buffer_store_smem
;
6103 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6104 store
->operands
[0] = Operand(rsrc
);
6106 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6107 offset
, Operand(offsets
[i
]));
6108 store
->operands
[1] = Operand(off
);
6110 store
->operands
[1] = Operand(offset
);
6112 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6113 store
->operands
[1].setFixed(m0
);
6114 store
->operands
[2] = Operand(write_datas
[i
]);
6117 store
->disable_wqm
= true;
6119 ctx
->block
->instructions
.emplace_back(std::move(store
));
6120 ctx
->program
->wb_smem_l1_on_end
= true;
6121 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6122 ctx
->block
->kind
|= block_kind_needs_lowering
;
6123 ctx
->program
->needs_exact
= true;
6126 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6127 store
->operands
[0] = Operand(rsrc
);
6128 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6129 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6130 store
->operands
[3] = Operand(write_datas
[i
]);
6131 store
->offset
= offsets
[i
];
6132 store
->offen
= (offset
.type() == RegType::vgpr
);
6135 store
->disable_wqm
= true;
6137 ctx
->program
->needs_exact
= true;
6138 ctx
->block
->instructions
.emplace_back(std::move(store
));
6143 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6145 /* return the previous value if dest is ever used */
6146 bool return_previous
= false;
6147 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6148 return_previous
= true;
6151 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6152 return_previous
= true;
6156 Builder
bld(ctx
->program
, ctx
->block
);
6157 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6159 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6160 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6161 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6163 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6164 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6165 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6167 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6169 aco_opcode op32
, op64
;
6170 switch (instr
->intrinsic
) {
6171 case nir_intrinsic_ssbo_atomic_add
:
6172 op32
= aco_opcode::buffer_atomic_add
;
6173 op64
= aco_opcode::buffer_atomic_add_x2
;
6175 case nir_intrinsic_ssbo_atomic_imin
:
6176 op32
= aco_opcode::buffer_atomic_smin
;
6177 op64
= aco_opcode::buffer_atomic_smin_x2
;
6179 case nir_intrinsic_ssbo_atomic_umin
:
6180 op32
= aco_opcode::buffer_atomic_umin
;
6181 op64
= aco_opcode::buffer_atomic_umin_x2
;
6183 case nir_intrinsic_ssbo_atomic_imax
:
6184 op32
= aco_opcode::buffer_atomic_smax
;
6185 op64
= aco_opcode::buffer_atomic_smax_x2
;
6187 case nir_intrinsic_ssbo_atomic_umax
:
6188 op32
= aco_opcode::buffer_atomic_umax
;
6189 op64
= aco_opcode::buffer_atomic_umax_x2
;
6191 case nir_intrinsic_ssbo_atomic_and
:
6192 op32
= aco_opcode::buffer_atomic_and
;
6193 op64
= aco_opcode::buffer_atomic_and_x2
;
6195 case nir_intrinsic_ssbo_atomic_or
:
6196 op32
= aco_opcode::buffer_atomic_or
;
6197 op64
= aco_opcode::buffer_atomic_or_x2
;
6199 case nir_intrinsic_ssbo_atomic_xor
:
6200 op32
= aco_opcode::buffer_atomic_xor
;
6201 op64
= aco_opcode::buffer_atomic_xor_x2
;
6203 case nir_intrinsic_ssbo_atomic_exchange
:
6204 op32
= aco_opcode::buffer_atomic_swap
;
6205 op64
= aco_opcode::buffer_atomic_swap_x2
;
6207 case nir_intrinsic_ssbo_atomic_comp_swap
:
6208 op32
= aco_opcode::buffer_atomic_cmpswap
;
6209 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6212 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6214 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6215 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6216 mubuf
->operands
[0] = Operand(rsrc
);
6217 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6218 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6219 mubuf
->operands
[3] = Operand(data
);
6220 if (return_previous
)
6221 mubuf
->definitions
[0] = Definition(dst
);
6223 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6224 mubuf
->glc
= return_previous
;
6225 mubuf
->dlc
= false; /* Not needed for atomics */
6226 mubuf
->disable_wqm
= true;
6227 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6228 ctx
->program
->needs_exact
= true;
6229 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6232 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6234 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6235 Builder
bld(ctx
->program
, ctx
->block
);
6236 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6237 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6240 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6242 Builder
bld(ctx
->program
, ctx
->block
);
6243 unsigned num_components
= instr
->num_components
;
6244 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6246 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6247 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6248 num_components
, component_size
};
6249 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6250 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6251 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6252 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6253 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6254 * it's safe to use SMEM */
6255 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6256 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6257 emit_global_load(ctx
, bld
, &info
);
6259 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6260 emit_smem_load(ctx
, bld
, &info
);
6264 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6266 Builder
bld(ctx
->program
, ctx
->block
);
6267 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6268 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6270 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6271 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6272 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6273 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6275 if (ctx
->options
->chip_class
>= GFX7
)
6276 addr
= as_vgpr(ctx
, addr
);
6278 unsigned write_count
= 0;
6279 Temp write_datas
[32];
6280 unsigned offsets
[32];
6281 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6282 16, &write_count
, write_datas
, offsets
);
6284 for (unsigned i
= 0; i
< write_count
; i
++) {
6285 if (ctx
->options
->chip_class
>= GFX7
) {
6286 unsigned offset
= offsets
[i
];
6287 Temp store_addr
= addr
;
6288 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6289 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6290 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6291 Temp carry
= bld
.tmp(bld
.lm
);
6292 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6294 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6295 Operand(offset
), addr0
);
6296 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6298 carry
).def(1).setHint(vcc
);
6300 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6305 bool global
= ctx
->options
->chip_class
>= GFX9
;
6307 switch (write_datas
[i
].bytes()) {
6309 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6312 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6315 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6318 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6321 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6324 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6327 unreachable("store_global not implemented for this size.");
6330 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6331 flat
->operands
[0] = Operand(store_addr
);
6332 flat
->operands
[1] = Operand(s1
);
6333 flat
->operands
[2] = Operand(write_datas
[i
]);
6336 flat
->offset
= offset
;
6337 flat
->disable_wqm
= true;
6339 ctx
->program
->needs_exact
= true;
6340 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6342 assert(ctx
->options
->chip_class
== GFX6
);
6344 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6346 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6348 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6349 mubuf
->operands
[0] = Operand(rsrc
);
6350 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6351 mubuf
->operands
[2] = Operand(0u);
6352 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6355 mubuf
->offset
= offsets
[i
];
6356 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6357 mubuf
->disable_wqm
= true;
6359 ctx
->program
->needs_exact
= true;
6360 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6365 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6367 /* return the previous value if dest is ever used */
6368 bool return_previous
= false;
6369 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6370 return_previous
= true;
6373 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6374 return_previous
= true;
6378 Builder
bld(ctx
->program
, ctx
->block
);
6379 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6380 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6382 if (ctx
->options
->chip_class
>= GFX7
)
6383 addr
= as_vgpr(ctx
, addr
);
6385 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6386 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6387 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6389 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6391 aco_opcode op32
, op64
;
6393 if (ctx
->options
->chip_class
>= GFX7
) {
6394 bool global
= ctx
->options
->chip_class
>= GFX9
;
6395 switch (instr
->intrinsic
) {
6396 case nir_intrinsic_global_atomic_add
:
6397 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6398 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6400 case nir_intrinsic_global_atomic_imin
:
6401 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6402 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6404 case nir_intrinsic_global_atomic_umin
:
6405 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6406 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6408 case nir_intrinsic_global_atomic_imax
:
6409 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6410 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6412 case nir_intrinsic_global_atomic_umax
:
6413 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6414 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6416 case nir_intrinsic_global_atomic_and
:
6417 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6418 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6420 case nir_intrinsic_global_atomic_or
:
6421 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6422 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6424 case nir_intrinsic_global_atomic_xor
:
6425 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6426 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6428 case nir_intrinsic_global_atomic_exchange
:
6429 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6430 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6432 case nir_intrinsic_global_atomic_comp_swap
:
6433 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6434 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6437 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6440 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6441 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6442 flat
->operands
[0] = Operand(addr
);
6443 flat
->operands
[1] = Operand(s1
);
6444 flat
->operands
[2] = Operand(data
);
6445 if (return_previous
)
6446 flat
->definitions
[0] = Definition(dst
);
6447 flat
->glc
= return_previous
;
6448 flat
->dlc
= false; /* Not needed for atomics */
6450 flat
->disable_wqm
= true;
6451 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6452 ctx
->program
->needs_exact
= true;
6453 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6455 assert(ctx
->options
->chip_class
== GFX6
);
6457 switch (instr
->intrinsic
) {
6458 case nir_intrinsic_global_atomic_add
:
6459 op32
= aco_opcode::buffer_atomic_add
;
6460 op64
= aco_opcode::buffer_atomic_add_x2
;
6462 case nir_intrinsic_global_atomic_imin
:
6463 op32
= aco_opcode::buffer_atomic_smin
;
6464 op64
= aco_opcode::buffer_atomic_smin_x2
;
6466 case nir_intrinsic_global_atomic_umin
:
6467 op32
= aco_opcode::buffer_atomic_umin
;
6468 op64
= aco_opcode::buffer_atomic_umin_x2
;
6470 case nir_intrinsic_global_atomic_imax
:
6471 op32
= aco_opcode::buffer_atomic_smax
;
6472 op64
= aco_opcode::buffer_atomic_smax_x2
;
6474 case nir_intrinsic_global_atomic_umax
:
6475 op32
= aco_opcode::buffer_atomic_umax
;
6476 op64
= aco_opcode::buffer_atomic_umax_x2
;
6478 case nir_intrinsic_global_atomic_and
:
6479 op32
= aco_opcode::buffer_atomic_and
;
6480 op64
= aco_opcode::buffer_atomic_and_x2
;
6482 case nir_intrinsic_global_atomic_or
:
6483 op32
= aco_opcode::buffer_atomic_or
;
6484 op64
= aco_opcode::buffer_atomic_or_x2
;
6486 case nir_intrinsic_global_atomic_xor
:
6487 op32
= aco_opcode::buffer_atomic_xor
;
6488 op64
= aco_opcode::buffer_atomic_xor_x2
;
6490 case nir_intrinsic_global_atomic_exchange
:
6491 op32
= aco_opcode::buffer_atomic_swap
;
6492 op64
= aco_opcode::buffer_atomic_swap_x2
;
6494 case nir_intrinsic_global_atomic_comp_swap
:
6495 op32
= aco_opcode::buffer_atomic_cmpswap
;
6496 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6499 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6502 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6504 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6506 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6507 mubuf
->operands
[0] = Operand(rsrc
);
6508 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6509 mubuf
->operands
[2] = Operand(0u);
6510 mubuf
->operands
[3] = Operand(data
);
6511 if (return_previous
)
6512 mubuf
->definitions
[0] = Definition(dst
);
6513 mubuf
->glc
= return_previous
;
6516 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6517 mubuf
->disable_wqm
= true;
6518 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6519 ctx
->program
->needs_exact
= true;
6520 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6524 sync_scope
translate_nir_scope(nir_scope scope
)
6527 case NIR_SCOPE_NONE
:
6528 case NIR_SCOPE_INVOCATION
:
6529 return scope_invocation
;
6530 case NIR_SCOPE_SUBGROUP
:
6531 return scope_subgroup
;
6532 case NIR_SCOPE_WORKGROUP
:
6533 return scope_workgroup
;
6534 case NIR_SCOPE_QUEUE_FAMILY
:
6535 return scope_queuefamily
;
6536 case NIR_SCOPE_DEVICE
:
6537 return scope_device
;
6539 unreachable("invalid scope");
6542 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6543 Builder
bld(ctx
->program
, ctx
->block
);
6545 unsigned semantics
= 0;
6546 unsigned storage
= 0;
6547 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6548 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6550 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6551 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6552 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6553 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6554 storage
|= storage_shared
;
6555 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6556 storage
|= storage_shared
;
6558 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6559 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6560 semantics
|= semantic_acquire
| semantic_release
;
6561 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6562 semantics
|= semantic_acquire
| semantic_release
;
6564 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6566 bld
.barrier(aco_opcode::p_barrier
,
6567 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6571 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6573 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6574 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6575 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6576 Builder
bld(ctx
->program
, ctx
->block
);
6578 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6579 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6580 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6583 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6585 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6586 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6587 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6588 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6590 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6591 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6594 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6596 unsigned offset
= nir_intrinsic_base(instr
);
6597 Builder
bld(ctx
->program
, ctx
->block
);
6598 Operand m
= load_lds_size_m0(bld
);
6599 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6600 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6602 unsigned num_operands
= 3;
6603 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6604 switch(instr
->intrinsic
) {
6605 case nir_intrinsic_shared_atomic_add
:
6606 op32
= aco_opcode::ds_add_u32
;
6607 op64
= aco_opcode::ds_add_u64
;
6608 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6609 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6611 case nir_intrinsic_shared_atomic_imin
:
6612 op32
= aco_opcode::ds_min_i32
;
6613 op64
= aco_opcode::ds_min_i64
;
6614 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6615 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6617 case nir_intrinsic_shared_atomic_umin
:
6618 op32
= aco_opcode::ds_min_u32
;
6619 op64
= aco_opcode::ds_min_u64
;
6620 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6621 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6623 case nir_intrinsic_shared_atomic_imax
:
6624 op32
= aco_opcode::ds_max_i32
;
6625 op64
= aco_opcode::ds_max_i64
;
6626 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6627 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6629 case nir_intrinsic_shared_atomic_umax
:
6630 op32
= aco_opcode::ds_max_u32
;
6631 op64
= aco_opcode::ds_max_u64
;
6632 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6633 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6635 case nir_intrinsic_shared_atomic_and
:
6636 op32
= aco_opcode::ds_and_b32
;
6637 op64
= aco_opcode::ds_and_b64
;
6638 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6639 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6641 case nir_intrinsic_shared_atomic_or
:
6642 op32
= aco_opcode::ds_or_b32
;
6643 op64
= aco_opcode::ds_or_b64
;
6644 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6645 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6647 case nir_intrinsic_shared_atomic_xor
:
6648 op32
= aco_opcode::ds_xor_b32
;
6649 op64
= aco_opcode::ds_xor_b64
;
6650 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6651 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6653 case nir_intrinsic_shared_atomic_exchange
:
6654 op32
= aco_opcode::ds_write_b32
;
6655 op64
= aco_opcode::ds_write_b64
;
6656 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6657 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6659 case nir_intrinsic_shared_atomic_comp_swap
:
6660 op32
= aco_opcode::ds_cmpst_b32
;
6661 op64
= aco_opcode::ds_cmpst_b64
;
6662 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6663 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6666 case nir_intrinsic_shared_atomic_fadd
:
6667 op32
= aco_opcode::ds_add_f32
;
6668 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6669 op64
= aco_opcode::num_opcodes
;
6670 op64_rtn
= aco_opcode::num_opcodes
;
6673 unreachable("Unhandled shared atomic intrinsic");
6676 /* return the previous value if dest is ever used */
6677 bool return_previous
= false;
6678 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6679 return_previous
= true;
6682 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6683 return_previous
= true;
6688 if (data
.size() == 1) {
6689 assert(instr
->dest
.ssa
.bit_size
== 32);
6690 op
= return_previous
? op32_rtn
: op32
;
6692 assert(instr
->dest
.ssa
.bit_size
== 64);
6693 op
= return_previous
? op64_rtn
: op64
;
6696 if (offset
> 65535) {
6697 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6701 aco_ptr
<DS_instruction
> ds
;
6702 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6703 ds
->operands
[0] = Operand(address
);
6704 ds
->operands
[1] = Operand(data
);
6705 if (num_operands
== 4)
6706 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6707 ds
->operands
[num_operands
- 1] = m
;
6708 ds
->offset0
= offset
;
6709 if (return_previous
)
6710 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6711 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6712 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6715 Temp
get_scratch_resource(isel_context
*ctx
)
6717 Builder
bld(ctx
->program
, ctx
->block
);
6718 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6719 if (ctx
->stage
!= compute_cs
)
6720 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6722 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6723 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6725 if (ctx
->program
->chip_class
>= GFX10
) {
6726 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6727 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6728 S_008F0C_RESOURCE_LEVEL(1);
6729 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6730 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6731 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6734 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6735 if (ctx
->program
->chip_class
<= GFX8
)
6736 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6738 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6741 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6742 Builder
bld(ctx
->program
, ctx
->block
);
6743 Temp rsrc
= get_scratch_resource(ctx
);
6744 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6745 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6747 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6748 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6749 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6750 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6751 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6752 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6753 info
.soffset
= ctx
->program
->scratch_offset
;
6754 emit_scratch_load(ctx
, bld
, &info
);
6757 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6758 Builder
bld(ctx
->program
, ctx
->block
);
6759 Temp rsrc
= get_scratch_resource(ctx
);
6760 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6761 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6763 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6764 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6766 unsigned write_count
= 0;
6767 Temp write_datas
[32];
6768 unsigned offsets
[32];
6769 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6770 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6771 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6773 for (unsigned i
= 0; i
< write_count
; i
++) {
6774 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6775 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6776 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6780 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6781 uint8_t log2_ps_iter_samples
;
6782 if (ctx
->program
->info
->ps
.force_persample
) {
6783 log2_ps_iter_samples
=
6784 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6786 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6789 /* The bit pattern matches that used by fixed function fragment
6791 static const unsigned ps_iter_masks
[] = {
6792 0xffff, /* not used */
6798 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6800 Builder
bld(ctx
->program
, ctx
->block
);
6802 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6803 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6804 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6805 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6806 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6807 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6810 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6811 Builder
bld(ctx
->program
, ctx
->block
);
6813 unsigned stream
= nir_intrinsic_stream_id(instr
);
6814 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6815 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6816 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6819 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6821 unsigned num_components
=
6822 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6823 assert(num_components
);
6825 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6826 unsigned stream_offset
= 0;
6827 for (unsigned i
= 0; i
< stream
; i
++) {
6828 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6829 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6832 /* Limit on the stride field for <= GFX7. */
6833 assert(stride
< (1 << 14));
6835 Temp gsvs_dwords
[4];
6836 for (unsigned i
= 0; i
< 4; i
++)
6837 gsvs_dwords
[i
] = bld
.tmp(s1
);
6838 bld
.pseudo(aco_opcode::p_split_vector
,
6839 Definition(gsvs_dwords
[0]),
6840 Definition(gsvs_dwords
[1]),
6841 Definition(gsvs_dwords
[2]),
6842 Definition(gsvs_dwords
[3]),
6845 if (stream_offset
) {
6846 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6848 Temp carry
= bld
.tmp(s1
);
6849 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6850 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6853 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6854 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6856 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6857 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6859 unsigned offset
= 0;
6860 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6861 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6864 for (unsigned j
= 0; j
< 4; j
++) {
6865 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6868 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6869 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6870 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6871 if (const_offset
>= 4096u) {
6872 if (vaddr_offset
.isUndefined())
6873 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6875 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6876 const_offset
%= 4096u;
6879 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6880 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6881 mtbuf
->operands
[1] = vaddr_offset
;
6882 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6883 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6884 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6885 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6886 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6887 mtbuf
->offset
= const_offset
;
6890 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
6891 bld
.insert(std::move(mtbuf
));
6894 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6897 /* outputs for the next vertex are undefined and keeping them around can
6898 * create invalid IR with control flow */
6899 ctx
->outputs
.mask
[i
] = 0;
6902 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6905 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6907 Builder
bld(ctx
->program
, ctx
->block
);
6909 if (cluster_size
== 1) {
6911 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6912 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6913 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6914 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6915 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6916 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6917 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6918 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6919 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6920 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6921 //subgroupAnd(val) -> (exec & ~val) == 0
6922 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6923 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6924 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6925 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6926 //subgroupOr(val) -> (val & exec) != 0
6927 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6928 return bool_to_vector_condition(ctx
, tmp
);
6929 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6930 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6931 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6932 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6933 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6934 return bool_to_vector_condition(ctx
, tmp
);
6936 //subgroupClustered{And,Or,Xor}(val, n) ->
6937 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6938 //cluster_offset = ~(n - 1) & lane_id
6939 //cluster_mask = ((1 << n) - 1)
6940 //subgroupClusteredAnd():
6941 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6942 //subgroupClusteredOr():
6943 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6944 //subgroupClusteredXor():
6945 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6946 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6947 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6950 if (op
== nir_op_iand
)
6951 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6953 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6955 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6957 if (ctx
->program
->chip_class
<= GFX7
)
6958 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6959 else if (ctx
->program
->wave_size
== 64)
6960 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6962 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6963 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6964 if (cluster_mask
!= 0xffffffff)
6965 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6967 Definition cmp_def
= Definition();
6968 if (op
== nir_op_iand
) {
6969 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6970 } else if (op
== nir_op_ior
) {
6971 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6972 } else if (op
== nir_op_ixor
) {
6973 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6974 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6975 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6977 cmp_def
.setHint(vcc
);
6978 return cmp_def
.getTemp();
6982 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6984 Builder
bld(ctx
->program
, ctx
->block
);
6986 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6987 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6988 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6990 if (op
== nir_op_iand
)
6991 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6993 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6995 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6996 Temp lo
= lohi
.def(0).getTemp();
6997 Temp hi
= lohi
.def(1).getTemp();
6998 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7000 Definition cmp_def
= Definition();
7001 if (op
== nir_op_iand
)
7002 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7003 else if (op
== nir_op_ior
)
7004 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7005 else if (op
== nir_op_ixor
)
7006 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7007 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7008 cmp_def
.setHint(vcc
);
7009 return cmp_def
.getTemp();
7012 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7014 Builder
bld(ctx
->program
, ctx
->block
);
7016 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7017 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7018 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7019 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7020 if (op
== nir_op_iand
)
7021 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7022 else if (op
== nir_op_ior
)
7023 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7024 else if (op
== nir_op_ixor
)
7025 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7031 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7033 Builder
bld(ctx
->program
, ctx
->block
);
7034 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7035 if (src
.regClass().type() == RegType::vgpr
) {
7036 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7037 } else if (src
.regClass() == s1
) {
7038 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7039 } else if (src
.regClass() == s2
) {
7040 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7042 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7046 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7048 Builder
bld(ctx
->program
, ctx
->block
);
7049 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7050 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7051 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7053 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7054 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7055 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7056 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7059 if (ctx
->program
->chip_class
>= GFX8
) {
7060 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7061 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7062 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7063 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7064 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7065 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7067 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7068 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7069 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7070 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7071 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7072 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7073 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7074 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7075 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7076 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7079 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7080 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7081 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7082 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7083 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7084 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7085 Temp wqm1
= bld
.tmp(v1
);
7086 emit_wqm(ctx
, tmp1
, wqm1
, true);
7087 Temp wqm2
= bld
.tmp(v1
);
7088 emit_wqm(ctx
, tmp2
, wqm2
, true);
7089 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7093 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7095 Builder
bld(ctx
->program
, ctx
->block
);
7096 switch(instr
->intrinsic
) {
7097 case nir_intrinsic_load_barycentric_sample
:
7098 case nir_intrinsic_load_barycentric_pixel
:
7099 case nir_intrinsic_load_barycentric_centroid
: {
7100 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7101 Temp bary
= Temp(0, s2
);
7103 case INTERP_MODE_SMOOTH
:
7104 case INTERP_MODE_NONE
:
7105 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7106 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7107 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7108 bary
= ctx
->persp_centroid
;
7109 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7110 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7112 case INTERP_MODE_NOPERSPECTIVE
:
7113 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7114 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7115 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7116 bary
= ctx
->linear_centroid
;
7117 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7118 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7123 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7124 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7125 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7126 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7127 Operand(p1
), Operand(p2
));
7128 emit_split_vector(ctx
, dst
, 2);
7131 case nir_intrinsic_load_barycentric_model
: {
7132 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7134 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7135 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7136 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7137 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7138 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7139 Operand(p1
), Operand(p2
), Operand(p3
));
7140 emit_split_vector(ctx
, dst
, 3);
7143 case nir_intrinsic_load_barycentric_at_sample
: {
7144 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7145 switch (ctx
->options
->key
.fs
.num_samples
) {
7146 case 2: sample_pos_offset
+= 1 << 3; break;
7147 case 4: sample_pos_offset
+= 3 << 3; break;
7148 case 8: sample_pos_offset
+= 7 << 3; break;
7152 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7153 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7154 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7155 //TODO: bounds checking?
7156 if (addr
.type() == RegType::sgpr
) {
7159 sample_pos_offset
+= const_addr
->u32
<< 3;
7160 offset
= Operand(sample_pos_offset
);
7161 } else if (ctx
->options
->chip_class
>= GFX9
) {
7162 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7164 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7165 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7168 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7169 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7171 } else if (ctx
->options
->chip_class
>= GFX9
) {
7172 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7173 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7174 } else if (ctx
->options
->chip_class
>= GFX7
) {
7175 /* addr += private_segment_buffer + sample_pos_offset */
7176 Temp tmp0
= bld
.tmp(s1
);
7177 Temp tmp1
= bld
.tmp(s1
);
7178 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7179 Definition scc_tmp
= bld
.def(s1
, scc
);
7180 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7181 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7182 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7183 Temp pck0
= bld
.tmp(v1
);
7184 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7185 tmp1
= as_vgpr(ctx
, tmp1
);
7186 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7187 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7189 /* sample_pos = flat_load_dwordx2 addr */
7190 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7192 assert(ctx
->options
->chip_class
== GFX6
);
7194 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7195 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7196 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7198 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7199 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7201 sample_pos
= bld
.tmp(v2
);
7203 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7204 load
->definitions
[0] = Definition(sample_pos
);
7205 load
->operands
[0] = Operand(rsrc
);
7206 load
->operands
[1] = Operand(addr
);
7207 load
->operands
[2] = Operand(0u);
7208 load
->offset
= sample_pos_offset
;
7210 load
->addr64
= true;
7213 load
->disable_wqm
= false;
7214 ctx
->block
->instructions
.emplace_back(std::move(load
));
7217 /* sample_pos -= 0.5 */
7218 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7219 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7220 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7221 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7222 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7224 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7227 case nir_intrinsic_load_barycentric_at_offset
: {
7228 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7229 RegClass rc
= RegClass(offset
.type(), 1);
7230 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7231 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7232 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7235 case nir_intrinsic_load_front_face
: {
7236 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7237 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7240 case nir_intrinsic_load_view_index
: {
7241 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7242 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7243 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7249 case nir_intrinsic_load_layer_id
: {
7250 unsigned idx
= nir_intrinsic_base(instr
);
7251 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7252 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7255 case nir_intrinsic_load_frag_coord
: {
7256 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7259 case nir_intrinsic_load_sample_pos
: {
7260 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7261 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7263 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7264 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7267 case nir_intrinsic_load_tess_coord
:
7268 visit_load_tess_coord(ctx
, instr
);
7270 case nir_intrinsic_load_interpolated_input
:
7271 visit_load_interpolated_input(ctx
, instr
);
7273 case nir_intrinsic_store_output
:
7274 visit_store_output(ctx
, instr
);
7276 case nir_intrinsic_load_input
:
7277 case nir_intrinsic_load_input_vertex
:
7278 visit_load_input(ctx
, instr
);
7280 case nir_intrinsic_load_output
:
7281 visit_load_output(ctx
, instr
);
7283 case nir_intrinsic_load_per_vertex_input
:
7284 visit_load_per_vertex_input(ctx
, instr
);
7286 case nir_intrinsic_load_per_vertex_output
:
7287 visit_load_per_vertex_output(ctx
, instr
);
7289 case nir_intrinsic_store_per_vertex_output
:
7290 visit_store_per_vertex_output(ctx
, instr
);
7292 case nir_intrinsic_load_ubo
:
7293 visit_load_ubo(ctx
, instr
);
7295 case nir_intrinsic_load_push_constant
:
7296 visit_load_push_constant(ctx
, instr
);
7298 case nir_intrinsic_load_constant
:
7299 visit_load_constant(ctx
, instr
);
7301 case nir_intrinsic_vulkan_resource_index
:
7302 visit_load_resource(ctx
, instr
);
7304 case nir_intrinsic_discard
:
7305 visit_discard(ctx
, instr
);
7307 case nir_intrinsic_discard_if
:
7308 visit_discard_if(ctx
, instr
);
7310 case nir_intrinsic_load_shared
:
7311 visit_load_shared(ctx
, instr
);
7313 case nir_intrinsic_store_shared
:
7314 visit_store_shared(ctx
, instr
);
7316 case nir_intrinsic_shared_atomic_add
:
7317 case nir_intrinsic_shared_atomic_imin
:
7318 case nir_intrinsic_shared_atomic_umin
:
7319 case nir_intrinsic_shared_atomic_imax
:
7320 case nir_intrinsic_shared_atomic_umax
:
7321 case nir_intrinsic_shared_atomic_and
:
7322 case nir_intrinsic_shared_atomic_or
:
7323 case nir_intrinsic_shared_atomic_xor
:
7324 case nir_intrinsic_shared_atomic_exchange
:
7325 case nir_intrinsic_shared_atomic_comp_swap
:
7326 case nir_intrinsic_shared_atomic_fadd
:
7327 visit_shared_atomic(ctx
, instr
);
7329 case nir_intrinsic_image_deref_load
:
7330 visit_image_load(ctx
, instr
);
7332 case nir_intrinsic_image_deref_store
:
7333 visit_image_store(ctx
, instr
);
7335 case nir_intrinsic_image_deref_atomic_add
:
7336 case nir_intrinsic_image_deref_atomic_umin
:
7337 case nir_intrinsic_image_deref_atomic_imin
:
7338 case nir_intrinsic_image_deref_atomic_umax
:
7339 case nir_intrinsic_image_deref_atomic_imax
:
7340 case nir_intrinsic_image_deref_atomic_and
:
7341 case nir_intrinsic_image_deref_atomic_or
:
7342 case nir_intrinsic_image_deref_atomic_xor
:
7343 case nir_intrinsic_image_deref_atomic_exchange
:
7344 case nir_intrinsic_image_deref_atomic_comp_swap
:
7345 visit_image_atomic(ctx
, instr
);
7347 case nir_intrinsic_image_deref_size
:
7348 visit_image_size(ctx
, instr
);
7350 case nir_intrinsic_load_ssbo
:
7351 visit_load_ssbo(ctx
, instr
);
7353 case nir_intrinsic_store_ssbo
:
7354 visit_store_ssbo(ctx
, instr
);
7356 case nir_intrinsic_load_global
:
7357 visit_load_global(ctx
, instr
);
7359 case nir_intrinsic_store_global
:
7360 visit_store_global(ctx
, instr
);
7362 case nir_intrinsic_global_atomic_add
:
7363 case nir_intrinsic_global_atomic_imin
:
7364 case nir_intrinsic_global_atomic_umin
:
7365 case nir_intrinsic_global_atomic_imax
:
7366 case nir_intrinsic_global_atomic_umax
:
7367 case nir_intrinsic_global_atomic_and
:
7368 case nir_intrinsic_global_atomic_or
:
7369 case nir_intrinsic_global_atomic_xor
:
7370 case nir_intrinsic_global_atomic_exchange
:
7371 case nir_intrinsic_global_atomic_comp_swap
:
7372 visit_global_atomic(ctx
, instr
);
7374 case nir_intrinsic_ssbo_atomic_add
:
7375 case nir_intrinsic_ssbo_atomic_imin
:
7376 case nir_intrinsic_ssbo_atomic_umin
:
7377 case nir_intrinsic_ssbo_atomic_imax
:
7378 case nir_intrinsic_ssbo_atomic_umax
:
7379 case nir_intrinsic_ssbo_atomic_and
:
7380 case nir_intrinsic_ssbo_atomic_or
:
7381 case nir_intrinsic_ssbo_atomic_xor
:
7382 case nir_intrinsic_ssbo_atomic_exchange
:
7383 case nir_intrinsic_ssbo_atomic_comp_swap
:
7384 visit_atomic_ssbo(ctx
, instr
);
7386 case nir_intrinsic_load_scratch
:
7387 visit_load_scratch(ctx
, instr
);
7389 case nir_intrinsic_store_scratch
:
7390 visit_store_scratch(ctx
, instr
);
7392 case nir_intrinsic_get_buffer_size
:
7393 visit_get_buffer_size(ctx
, instr
);
7395 case nir_intrinsic_scoped_barrier
:
7396 emit_scoped_barrier(ctx
, instr
);
7398 case nir_intrinsic_load_num_work_groups
: {
7399 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7400 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7401 emit_split_vector(ctx
, dst
, 3);
7404 case nir_intrinsic_load_local_invocation_id
: {
7405 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7406 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7407 emit_split_vector(ctx
, dst
, 3);
7410 case nir_intrinsic_load_work_group_id
: {
7411 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7412 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7413 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7414 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7415 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7416 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7417 emit_split_vector(ctx
, dst
, 3);
7420 case nir_intrinsic_load_local_invocation_index
: {
7421 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7423 /* The tg_size bits [6:11] contain the subgroup id,
7424 * we need this multiplied by the wave size, and then OR the thread id to it.
7426 if (ctx
->program
->wave_size
== 64) {
7427 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7428 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7429 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7430 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7432 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7433 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7434 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7435 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7439 case nir_intrinsic_load_subgroup_id
: {
7440 if (ctx
->stage
== compute_cs
) {
7441 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7442 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7444 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7448 case nir_intrinsic_load_subgroup_invocation
: {
7449 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7452 case nir_intrinsic_load_num_subgroups
: {
7453 if (ctx
->stage
== compute_cs
)
7454 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7455 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7457 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7460 case nir_intrinsic_ballot
: {
7461 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7462 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7463 Definition tmp
= bld
.def(dst
.regClass());
7464 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7465 if (instr
->src
[0].ssa
->bit_size
== 1) {
7466 assert(src
.regClass() == bld
.lm
);
7467 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7468 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7469 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7470 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7471 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7473 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7475 if (dst
.size() != bld
.lm
.size()) {
7476 /* Wave32 with ballot size set to 64 */
7477 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7479 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7482 case nir_intrinsic_shuffle
:
7483 case nir_intrinsic_read_invocation
: {
7484 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7485 if (!nir_src_is_divergent(instr
->src
[0])) {
7486 emit_uniform_subgroup(ctx
, instr
, src
);
7488 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7489 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7490 tid
= bld
.as_uniform(tid
);
7491 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7492 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7493 Temp tmp
= bld
.tmp(v1
);
7494 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7495 if (dst
.type() == RegType::vgpr
)
7496 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7498 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7499 } else if (src
.regClass() == v1
) {
7500 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7501 } else if (src
.regClass() == v2
) {
7502 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7503 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7504 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7505 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7506 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7507 emit_split_vector(ctx
, dst
, 2);
7508 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7509 assert(src
.regClass() == bld
.lm
);
7510 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7511 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7512 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7513 assert(src
.regClass() == bld
.lm
);
7515 if (ctx
->program
->chip_class
<= GFX7
)
7516 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7517 else if (ctx
->program
->wave_size
== 64)
7518 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7520 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7521 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7522 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7523 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7525 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7530 case nir_intrinsic_load_sample_id
: {
7531 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7532 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7535 case nir_intrinsic_load_sample_mask_in
: {
7536 visit_load_sample_mask_in(ctx
, instr
);
7539 case nir_intrinsic_read_first_invocation
: {
7540 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7541 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7542 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7544 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7546 } else if (src
.regClass() == v2
) {
7547 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7548 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7549 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7550 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7551 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7552 emit_split_vector(ctx
, dst
, 2);
7553 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7554 assert(src
.regClass() == bld
.lm
);
7555 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7556 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7557 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7558 } else if (src
.regClass() == s1
) {
7559 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7560 } else if (src
.regClass() == s2
) {
7561 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7563 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7567 case nir_intrinsic_vote_all
: {
7568 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7569 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7570 assert(src
.regClass() == bld
.lm
);
7571 assert(dst
.regClass() == bld
.lm
);
7573 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7574 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7575 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7578 case nir_intrinsic_vote_any
: {
7579 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7580 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7581 assert(src
.regClass() == bld
.lm
);
7582 assert(dst
.regClass() == bld
.lm
);
7584 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7585 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7588 case nir_intrinsic_reduce
:
7589 case nir_intrinsic_inclusive_scan
:
7590 case nir_intrinsic_exclusive_scan
: {
7591 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7592 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7593 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7594 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7595 nir_intrinsic_cluster_size(instr
) : 0;
7596 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7598 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7599 emit_uniform_subgroup(ctx
, instr
, src
);
7600 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7601 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7603 else if (op
== nir_op_iadd
)
7605 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7607 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7609 switch (instr
->intrinsic
) {
7610 case nir_intrinsic_reduce
:
7611 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7613 case nir_intrinsic_exclusive_scan
:
7614 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7616 case nir_intrinsic_inclusive_scan
:
7617 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7622 } else if (cluster_size
== 1) {
7623 bld
.copy(Definition(dst
), src
);
7625 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7627 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7631 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7632 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7647 unreachable("unknown reduction op");
7653 switch (instr
->intrinsic
) {
7654 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7655 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7656 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7658 unreachable("unknown reduce intrinsic");
7661 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7662 reduce
->operands
[0] = Operand(src
);
7663 // filled in by aco_reduce_assign.cpp, used internally as part of the
7665 assert(dst
.size() == 1 || dst
.size() == 2);
7666 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7667 reduce
->operands
[2] = Operand(v1
.as_linear());
7669 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7670 reduce
->definitions
[0] = Definition(tmp_dst
);
7671 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7672 reduce
->definitions
[2] = Definition();
7673 reduce
->definitions
[3] = Definition(scc
, s1
);
7674 reduce
->definitions
[4] = Definition();
7675 reduce
->reduce_op
= reduce_op
;
7676 reduce
->cluster_size
= cluster_size
;
7677 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7679 emit_wqm(ctx
, tmp_dst
, dst
);
7683 case nir_intrinsic_quad_broadcast
: {
7684 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7685 if (!nir_dest_is_divergent(instr
->dest
)) {
7686 emit_uniform_subgroup(ctx
, instr
, src
);
7688 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7689 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7690 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7692 if (instr
->dest
.ssa
.bit_size
== 1) {
7693 assert(src
.regClass() == bld
.lm
);
7694 assert(dst
.regClass() == bld
.lm
);
7695 uint32_t half_mask
= 0x11111111u
<< lane
;
7696 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7697 Temp tmp
= bld
.tmp(bld
.lm
);
7698 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7699 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7700 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7701 emit_wqm(ctx
, tmp
, dst
);
7702 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7703 Temp tmp
= bld
.tmp(v1
);
7704 if (ctx
->program
->chip_class
>= GFX8
)
7705 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7707 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7708 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7709 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7710 Temp tmp
= bld
.tmp(v1
);
7711 if (ctx
->program
->chip_class
>= GFX8
)
7712 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7714 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7716 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7717 if (ctx
->program
->chip_class
>= GFX8
)
7718 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7720 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7721 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7722 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7723 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7724 if (ctx
->program
->chip_class
>= GFX8
) {
7725 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7726 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7728 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7729 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7731 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7732 emit_split_vector(ctx
, dst
, 2);
7734 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7739 case nir_intrinsic_quad_swap_horizontal
:
7740 case nir_intrinsic_quad_swap_vertical
:
7741 case nir_intrinsic_quad_swap_diagonal
:
7742 case nir_intrinsic_quad_swizzle_amd
: {
7743 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7744 if (!nir_dest_is_divergent(instr
->dest
)) {
7745 emit_uniform_subgroup(ctx
, instr
, src
);
7748 uint16_t dpp_ctrl
= 0;
7749 switch (instr
->intrinsic
) {
7750 case nir_intrinsic_quad_swap_horizontal
:
7751 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7753 case nir_intrinsic_quad_swap_vertical
:
7754 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7756 case nir_intrinsic_quad_swap_diagonal
:
7757 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7759 case nir_intrinsic_quad_swizzle_amd
:
7760 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7765 if (ctx
->program
->chip_class
< GFX8
)
7766 dpp_ctrl
|= (1 << 15);
7768 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7769 if (instr
->dest
.ssa
.bit_size
== 1) {
7770 assert(src
.regClass() == bld
.lm
);
7771 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7772 if (ctx
->program
->chip_class
>= GFX8
)
7773 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7775 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7776 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7777 emit_wqm(ctx
, tmp
, dst
);
7778 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7779 Temp tmp
= bld
.tmp(v1
);
7780 if (ctx
->program
->chip_class
>= GFX8
)
7781 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7783 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7784 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7785 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7786 Temp tmp
= bld
.tmp(v1
);
7787 if (ctx
->program
->chip_class
>= GFX8
)
7788 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7790 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7791 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7792 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7794 if (ctx
->program
->chip_class
>= GFX8
)
7795 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7797 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7798 emit_wqm(ctx
, tmp
, dst
);
7799 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7800 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7801 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7802 if (ctx
->program
->chip_class
>= GFX8
) {
7803 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7804 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7806 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7807 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7809 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7810 emit_split_vector(ctx
, dst
, 2);
7812 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7816 case nir_intrinsic_masked_swizzle_amd
: {
7817 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7818 if (!nir_dest_is_divergent(instr
->dest
)) {
7819 emit_uniform_subgroup(ctx
, instr
, src
);
7822 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7823 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7824 if (instr
->dest
.ssa
.bit_size
== 1) {
7825 assert(src
.regClass() == bld
.lm
);
7826 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7827 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7828 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7829 emit_wqm(ctx
, tmp
, dst
);
7830 } else if (dst
.regClass() == v1b
) {
7831 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7832 emit_extract_vector(ctx
, tmp
, 0, dst
);
7833 } else if (dst
.regClass() == v2b
) {
7834 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7835 emit_extract_vector(ctx
, tmp
, 0, dst
);
7836 } else if (dst
.regClass() == v1
) {
7837 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7838 } else if (dst
.regClass() == v2
) {
7839 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7840 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7841 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7842 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7843 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7844 emit_split_vector(ctx
, dst
, 2);
7846 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7850 case nir_intrinsic_write_invocation_amd
: {
7851 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7852 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7853 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7854 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7855 if (dst
.regClass() == v1
) {
7856 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7857 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7858 } else if (dst
.regClass() == v2
) {
7859 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7860 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7863 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7864 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7865 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7866 emit_split_vector(ctx
, dst
, 2);
7868 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7872 case nir_intrinsic_mbcnt_amd
: {
7873 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7874 RegClass rc
= RegClass(src
.type(), 1);
7875 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7877 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7878 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7879 emit_wqm(ctx
, wqm_tmp
, dst
);
7882 case nir_intrinsic_load_helper_invocation
: {
7883 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7884 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7885 ctx
->block
->kind
|= block_kind_needs_lowering
;
7886 ctx
->program
->needs_exact
= true;
7889 case nir_intrinsic_is_helper_invocation
: {
7890 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7891 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7892 ctx
->block
->kind
|= block_kind_needs_lowering
;
7893 ctx
->program
->needs_exact
= true;
7896 case nir_intrinsic_demote
:
7897 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7899 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7900 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7901 ctx
->block
->kind
|= block_kind_uses_demote
;
7902 ctx
->program
->needs_exact
= true;
7904 case nir_intrinsic_demote_if
: {
7905 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7906 assert(src
.regClass() == bld
.lm
);
7907 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7908 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7910 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7911 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7912 ctx
->block
->kind
|= block_kind_uses_demote
;
7913 ctx
->program
->needs_exact
= true;
7916 case nir_intrinsic_first_invocation
: {
7917 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7918 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7921 case nir_intrinsic_shader_clock
: {
7922 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7923 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
7924 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
7925 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
7926 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
7929 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7930 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7931 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
7933 emit_split_vector(ctx
, dst
, 2);
7936 case nir_intrinsic_load_vertex_id_zero_base
: {
7937 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7938 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7941 case nir_intrinsic_load_first_vertex
: {
7942 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7943 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7946 case nir_intrinsic_load_base_instance
: {
7947 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7948 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7951 case nir_intrinsic_load_instance_id
: {
7952 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7953 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7956 case nir_intrinsic_load_draw_id
: {
7957 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7958 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7961 case nir_intrinsic_load_invocation_id
: {
7962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7964 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7965 if (ctx
->options
->chip_class
>= GFX10
)
7966 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7968 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7969 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7970 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7971 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7973 unreachable("Unsupported stage for load_invocation_id");
7978 case nir_intrinsic_load_primitive_id
: {
7979 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7981 switch (ctx
->shader
->info
.stage
) {
7982 case MESA_SHADER_GEOMETRY
:
7983 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7985 case MESA_SHADER_TESS_CTRL
:
7986 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7988 case MESA_SHADER_TESS_EVAL
:
7989 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7992 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7997 case nir_intrinsic_load_patch_vertices_in
: {
7998 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7999 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8001 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8002 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8005 case nir_intrinsic_emit_vertex_with_counter
: {
8006 visit_emit_vertex_with_counter(ctx
, instr
);
8009 case nir_intrinsic_end_primitive_with_counter
: {
8010 unsigned stream
= nir_intrinsic_stream_id(instr
);
8011 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8014 case nir_intrinsic_set_vertex_count
: {
8015 /* unused, the HW keeps track of this for us */
8019 isel_err(&instr
->instr
, "Unimplemented intrinsic instr");
8027 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8028 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8029 enum glsl_base_type
*stype
)
8031 nir_deref_instr
*texture_deref_instr
= NULL
;
8032 nir_deref_instr
*sampler_deref_instr
= NULL
;
8035 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8036 switch (instr
->src
[i
].src_type
) {
8037 case nir_tex_src_texture_deref
:
8038 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8040 case nir_tex_src_sampler_deref
:
8041 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8043 case nir_tex_src_plane
:
8044 plane
= nir_src_as_int(instr
->src
[i
].src
);
8051 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8053 if (!sampler_deref_instr
)
8054 sampler_deref_instr
= texture_deref_instr
;
8057 assert(instr
->op
!= nir_texop_txf_ms
&&
8058 instr
->op
!= nir_texop_samples_identical
);
8059 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8060 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8061 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8062 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8063 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8064 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8066 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8069 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8071 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8072 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8073 Builder
bld(ctx
->program
, ctx
->block
);
8075 /* to avoid unnecessary moves, we split and recombine sampler and image */
8076 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8077 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8078 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8079 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8080 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8081 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8082 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8083 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8085 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8086 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8087 img
[0], img
[1], img
[2], img
[3],
8088 img
[4], img
[5], img
[6], img
[7]);
8089 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8090 samp
[0], samp
[1], samp
[2], samp
[3]);
8093 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8094 instr
->op
== nir_texop_samples_identical
))
8095 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8098 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8099 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8101 Builder
bld(ctx
->program
, ctx
->block
);
8103 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8104 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8105 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8107 Operand
neg_one(0xbf800000u
);
8108 Operand
one(0x3f800000u
);
8109 Operand
two(0x40000000u
);
8110 Operand
four(0x40800000u
);
8112 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8113 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8114 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8116 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8117 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8118 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8119 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8122 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8123 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8124 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8126 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8129 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8130 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8131 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8134 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8135 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8137 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8138 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8141 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8143 Builder
bld(ctx
->program
, ctx
->block
);
8144 Temp ma
, tc
, sc
, id
;
8145 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8146 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8149 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8151 // see comment in ac_prepare_cube_coords()
8152 if (ctx
->options
->chip_class
<= GFX8
)
8153 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8156 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8158 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8159 vop3a
->operands
[0] = Operand(ma
);
8160 vop3a
->abs
[0] = true;
8161 Temp invma
= bld
.tmp(v1
);
8162 vop3a
->definitions
[0] = Definition(invma
);
8163 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8165 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8167 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8169 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8171 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8173 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8176 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8177 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8179 for (unsigned i
= 0; i
< 2; i
++) {
8180 // see comment in ac_prepare_cube_coords()
8182 Temp deriv_sc
, deriv_tc
;
8183 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8184 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8186 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8188 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8189 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8190 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8191 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8192 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8193 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8194 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8197 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8198 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8202 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8209 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8211 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8213 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8214 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8217 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8218 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8219 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8223 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8225 Builder
bld(ctx
->program
, ctx
->block
);
8226 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8227 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8228 has_clamped_lod
= false;
8229 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8230 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8231 clamped_lod
= Temp();
8232 std::vector
<Temp
> coords
;
8233 std::vector
<Temp
> derivs
;
8234 nir_const_value
*sample_index_cv
= NULL
;
8235 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8236 enum glsl_base_type stype
;
8237 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8239 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8240 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8241 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8242 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8244 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8245 switch (instr
->src
[i
].src_type
) {
8246 case nir_tex_src_coord
: {
8247 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8248 for (unsigned i
= 0; i
< coord
.size(); i
++)
8249 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8252 case nir_tex_src_bias
:
8253 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8256 case nir_tex_src_lod
: {
8257 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8259 if (val
&& val
->f32
<= 0.0) {
8262 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8267 case nir_tex_src_min_lod
:
8268 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8269 has_clamped_lod
= true;
8271 case nir_tex_src_comparator
:
8272 if (instr
->is_shadow
) {
8273 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8277 case nir_tex_src_offset
:
8278 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8279 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8282 case nir_tex_src_ddx
:
8283 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8286 case nir_tex_src_ddy
:
8287 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8290 case nir_tex_src_ms_index
:
8291 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8292 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8293 has_sample_index
= true;
8295 case nir_tex_src_texture_offset
:
8296 case nir_tex_src_sampler_offset
:
8302 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8303 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8305 if (instr
->op
== nir_texop_texture_samples
) {
8306 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8308 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8309 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8310 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8312 Operand default_sample
= Operand(1u);
8313 if (ctx
->options
->robust_buffer_access
) {
8314 /* Extract the second dword of the descriptor, if it's
8315 * all zero, then it's a null descriptor.
8317 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8318 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8319 default_sample
= Operand(is_non_null_descriptor
);
8322 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8323 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8324 samples
, default_sample
, bld
.scc(is_msaa
));
8328 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8329 aco_ptr
<Instruction
> tmp_instr
;
8330 Temp acc
, pack
= Temp();
8332 uint32_t pack_const
= 0;
8333 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8334 if (!const_offset
[i
])
8336 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8339 if (offset
.type() == RegType::sgpr
) {
8340 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8341 if (const_offset
[i
])
8344 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8345 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8348 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8351 if (pack
== Temp()) {
8354 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8358 if (pack_const
&& pack
!= Temp())
8359 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8361 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8362 if (const_offset
[i
])
8365 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8366 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8369 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8372 if (pack
== Temp()) {
8375 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8379 if (pack_const
&& pack
!= Temp())
8380 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8382 if (pack_const
&& pack
== Temp())
8383 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8384 else if (pack
== Temp())
8390 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8391 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8393 /* pack derivatives */
8394 if (has_ddx
|| has_ddy
) {
8395 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8396 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8397 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8398 derivs
= {ddx
, zero
, ddy
, zero
};
8400 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8401 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8402 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8403 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8408 if (instr
->coord_components
> 1 &&
8409 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8411 instr
->op
!= nir_texop_txf
)
8412 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8414 if (instr
->coord_components
> 2 &&
8415 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8416 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8417 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8418 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8420 instr
->op
!= nir_texop_txf
&&
8421 instr
->op
!= nir_texop_txf_ms
&&
8422 instr
->op
!= nir_texop_fragment_fetch
&&
8423 instr
->op
!= nir_texop_fragment_mask_fetch
)
8424 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8426 if (ctx
->options
->chip_class
== GFX9
&&
8427 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8428 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8429 assert(coords
.size() > 0 && coords
.size() < 3);
8431 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8432 Operand((uint32_t) 0) :
8433 Operand((uint32_t) 0x3f000000)));
8436 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8438 if (instr
->op
== nir_texop_samples_identical
)
8439 resource
= fmask_ptr
;
8441 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8442 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8443 instr
->op
!= nir_texop_txs
&&
8444 instr
->op
!= nir_texop_fragment_fetch
&&
8445 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8446 assert(has_sample_index
);
8447 Operand
op(sample_index
);
8448 if (sample_index_cv
)
8449 op
= Operand(sample_index_cv
->u32
);
8450 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8453 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8454 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8455 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8456 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8461 /* Build tex instruction */
8462 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8463 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8464 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8466 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8469 /* gather4 selects the component by dmask and always returns vec4 */
8470 if (instr
->op
== nir_texop_tg4
) {
8471 assert(instr
->dest
.ssa
.num_components
== 4);
8472 if (instr
->is_shadow
)
8475 dmask
= 1 << instr
->component
;
8476 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8477 tmp_dst
= bld
.tmp(v4
);
8478 } else if (instr
->op
== nir_texop_samples_identical
) {
8479 tmp_dst
= bld
.tmp(v1
);
8480 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8481 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8484 aco_ptr
<MIMG_instruction
> tex
;
8485 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8487 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8489 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8490 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8493 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8494 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8496 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8497 tex
->operands
[0] = Operand(resource
);
8498 tex
->operands
[1] = Operand(s4
); /* no sampler */
8499 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8500 if (ctx
->options
->chip_class
== GFX9
&&
8501 instr
->op
== nir_texop_txs
&&
8502 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8504 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8505 } else if (instr
->op
== nir_texop_query_levels
) {
8506 tex
->dmask
= 1 << 3;
8511 tex
->definitions
[0] = Definition(tmp_dst
);
8513 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8516 /* divide 3rd value by 6 by multiplying with magic number */
8517 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8518 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8519 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8520 assert(instr
->dest
.ssa
.num_components
== 3);
8521 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8522 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8523 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8524 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8529 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8533 Temp tg4_compare_cube_wa64
= Temp();
8535 if (tg4_integer_workarounds
) {
8536 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8537 tex
->operands
[0] = Operand(resource
);
8538 tex
->operands
[1] = Operand(s4
); /* no sampler */
8539 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8543 Temp size
= bld
.tmp(v2
);
8544 tex
->definitions
[0] = Definition(size
);
8545 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8546 emit_split_vector(ctx
, size
, size
.size());
8549 for (unsigned i
= 0; i
< 2; i
++) {
8550 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8551 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8552 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8553 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8556 Temp new_coords
[2] = {
8557 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8558 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8561 if (tg4_integer_cube_workaround
) {
8562 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8563 Temp desc
[resource
.size()];
8564 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8565 Format::PSEUDO
, 1, resource
.size())};
8566 split
->operands
[0] = Operand(resource
);
8567 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8568 desc
[i
] = bld
.tmp(s1
);
8569 split
->definitions
[i
] = Definition(desc
[i
]);
8571 ctx
->block
->instructions
.emplace_back(std::move(split
));
8573 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8574 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8575 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8578 if (stype
== GLSL_TYPE_UINT
) {
8579 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8580 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8581 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8582 bld
.scc(compare_cube_wa
));
8584 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8585 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8586 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8587 bld
.scc(compare_cube_wa
));
8589 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8590 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8592 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8594 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8595 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8596 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8598 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8599 Format::PSEUDO
, resource
.size(), 1)};
8600 for (unsigned i
= 0; i
< resource
.size(); i
++)
8601 vec
->operands
[i
] = Operand(desc
[i
]);
8602 resource
= bld
.tmp(resource
.regClass());
8603 vec
->definitions
[0] = Definition(resource
);
8604 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8606 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8607 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8608 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8609 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8611 coords
[0] = new_coords
[0];
8612 coords
[1] = new_coords
[1];
8615 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8616 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8618 assert(coords
.size() == 1);
8619 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8623 op
= aco_opcode::buffer_load_format_x
; break;
8625 op
= aco_opcode::buffer_load_format_xy
; break;
8627 op
= aco_opcode::buffer_load_format_xyz
; break;
8629 op
= aco_opcode::buffer_load_format_xyzw
; break;
8631 unreachable("Tex instruction loads more than 4 components.");
8634 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8635 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8638 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8640 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8641 mubuf
->operands
[0] = Operand(resource
);
8642 mubuf
->operands
[1] = Operand(coords
[0]);
8643 mubuf
->operands
[2] = Operand((uint32_t) 0);
8644 mubuf
->definitions
[0] = Definition(tmp_dst
);
8645 mubuf
->idxen
= true;
8646 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8648 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8652 /* gather MIMG address components */
8653 std::vector
<Temp
> args
;
8655 args
.emplace_back(offset
);
8657 args
.emplace_back(bias
);
8659 args
.emplace_back(compare
);
8661 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8663 args
.insert(args
.end(), coords
.begin(), coords
.end());
8664 if (has_sample_index
)
8665 args
.emplace_back(sample_index
);
8667 args
.emplace_back(lod
);
8668 if (has_clamped_lod
)
8669 args
.emplace_back(clamped_lod
);
8671 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8672 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8673 vec
->definitions
[0] = Definition(arg
);
8674 for (unsigned i
= 0; i
< args
.size(); i
++)
8675 vec
->operands
[i
] = Operand(args
[i
]);
8676 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8679 if (instr
->op
== nir_texop_txf
||
8680 instr
->op
== nir_texop_txf_ms
||
8681 instr
->op
== nir_texop_samples_identical
||
8682 instr
->op
== nir_texop_fragment_fetch
||
8683 instr
->op
== nir_texop_fragment_mask_fetch
) {
8684 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8685 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8686 tex
->operands
[0] = Operand(resource
);
8687 tex
->operands
[1] = Operand(s4
); /* no sampler */
8688 tex
->operands
[2] = Operand(arg
);
8693 tex
->definitions
[0] = Definition(tmp_dst
);
8694 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8696 if (instr
->op
== nir_texop_samples_identical
) {
8697 assert(dmask
== 1 && dst
.regClass() == v1
);
8698 assert(dst
.id() != tmp_dst
.id());
8700 Temp tmp
= bld
.tmp(bld
.lm
);
8701 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8702 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8705 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8710 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8711 aco_opcode opcode
= aco_opcode::image_sample
;
8712 if (has_offset
) { /* image_sample_*_o */
8713 if (has_clamped_lod
) {
8715 opcode
= aco_opcode::image_sample_c_cl_o
;
8717 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8719 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8721 opcode
= aco_opcode::image_sample_cl_o
;
8723 opcode
= aco_opcode::image_sample_d_cl_o
;
8725 opcode
= aco_opcode::image_sample_b_cl_o
;
8727 } else if (has_compare
) {
8728 opcode
= aco_opcode::image_sample_c_o
;
8730 opcode
= aco_opcode::image_sample_c_d_o
;
8732 opcode
= aco_opcode::image_sample_c_b_o
;
8734 opcode
= aco_opcode::image_sample_c_lz_o
;
8736 opcode
= aco_opcode::image_sample_c_l_o
;
8738 opcode
= aco_opcode::image_sample_o
;
8740 opcode
= aco_opcode::image_sample_d_o
;
8742 opcode
= aco_opcode::image_sample_b_o
;
8744 opcode
= aco_opcode::image_sample_lz_o
;
8746 opcode
= aco_opcode::image_sample_l_o
;
8748 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8750 opcode
= aco_opcode::image_sample_c_cl
;
8752 opcode
= aco_opcode::image_sample_c_d_cl
;
8754 opcode
= aco_opcode::image_sample_c_b_cl
;
8756 opcode
= aco_opcode::image_sample_cl
;
8758 opcode
= aco_opcode::image_sample_d_cl
;
8760 opcode
= aco_opcode::image_sample_b_cl
;
8762 } else { /* no offset */
8764 opcode
= aco_opcode::image_sample_c
;
8766 opcode
= aco_opcode::image_sample_c_d
;
8768 opcode
= aco_opcode::image_sample_c_b
;
8770 opcode
= aco_opcode::image_sample_c_lz
;
8772 opcode
= aco_opcode::image_sample_c_l
;
8774 opcode
= aco_opcode::image_sample
;
8776 opcode
= aco_opcode::image_sample_d
;
8778 opcode
= aco_opcode::image_sample_b
;
8780 opcode
= aco_opcode::image_sample_lz
;
8782 opcode
= aco_opcode::image_sample_l
;
8786 if (instr
->op
== nir_texop_tg4
) {
8787 if (has_offset
) { /* image_gather4_*_o */
8789 opcode
= aco_opcode::image_gather4_c_lz_o
;
8791 opcode
= aco_opcode::image_gather4_c_l_o
;
8793 opcode
= aco_opcode::image_gather4_c_b_o
;
8795 opcode
= aco_opcode::image_gather4_lz_o
;
8797 opcode
= aco_opcode::image_gather4_l_o
;
8799 opcode
= aco_opcode::image_gather4_b_o
;
8803 opcode
= aco_opcode::image_gather4_c_lz
;
8805 opcode
= aco_opcode::image_gather4_c_l
;
8807 opcode
= aco_opcode::image_gather4_c_b
;
8809 opcode
= aco_opcode::image_gather4_lz
;
8811 opcode
= aco_opcode::image_gather4_l
;
8813 opcode
= aco_opcode::image_gather4_b
;
8816 } else if (instr
->op
== nir_texop_lod
) {
8817 opcode
= aco_opcode::image_get_lod
;
8820 /* we don't need the bias, sample index, compare value or offset to be
8821 * computed in WQM but if the p_create_vector copies the coordinates, then it
8822 * needs to be in WQM */
8823 if (ctx
->stage
== fragment_fs
&&
8824 !has_derivs
&& !has_lod
&& !level_zero
&&
8825 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8826 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8827 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8829 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8830 tex
->operands
[0] = Operand(resource
);
8831 tex
->operands
[1] = Operand(sampler
);
8832 tex
->operands
[2] = Operand(arg
);
8836 tex
->definitions
[0] = Definition(tmp_dst
);
8837 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8839 if (tg4_integer_cube_workaround
) {
8840 assert(tmp_dst
.id() != dst
.id());
8841 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8843 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8845 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8846 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8848 if (stype
== GLSL_TYPE_UINT
)
8849 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8851 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8852 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8854 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8855 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8856 val
[0], val
[1], val
[2], val
[3]);
8858 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8859 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8864 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8866 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8867 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8869 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8870 if (ctx
->program
->wave_size
== 64)
8871 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8873 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8875 return Operand(tmp
);
8879 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8881 aco_ptr
<Pseudo_instruction
> phi
;
8882 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8883 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8885 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8886 logical
|= ctx
->block
->kind
& block_kind_merge
;
8887 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8889 /* we want a sorted list of sources, since the predecessor list is also sorted */
8890 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8891 nir_foreach_phi_src(src
, instr
)
8892 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8894 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8895 unsigned num_operands
= 0;
8896 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8897 unsigned num_defined
= 0;
8898 unsigned cur_pred_idx
= 0;
8899 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8900 if (cur_pred_idx
< preds
.size()) {
8901 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8902 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8903 unsigned skipped
= 0;
8904 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8906 if (cur_pred_idx
+ skipped
< preds
.size()) {
8907 for (unsigned i
= 0; i
< skipped
; i
++)
8908 operands
[num_operands
++] = Operand(dst
.regClass());
8909 cur_pred_idx
+= skipped
;
8914 /* Handle missing predecessors at the end. This shouldn't happen with loop
8915 * headers and we can't ignore these sources for loop header phis. */
8916 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8919 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
8920 operands
[num_operands
++] = op
;
8921 num_defined
+= !op
.isUndefined();
8923 /* handle block_kind_continue_or_break at loop exit blocks */
8924 while (cur_pred_idx
++ < preds
.size())
8925 operands
[num_operands
++] = Operand(dst
.regClass());
8927 /* If the loop ends with a break, still add a linear continue edge in case
8928 * that break is divergent or continue_or_break is used. We'll either remove
8929 * this operand later in visit_loop() if it's not necessary or replace the
8930 * undef with something correct. */
8931 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8932 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8933 nir_block
*last
= nir_loop_last_block(loop
);
8934 if (last
->successors
[0] != instr
->instr
.block
)
8935 operands
[num_operands
++] = Operand(RegClass());
8938 if (num_defined
== 0) {
8939 Builder
bld(ctx
->program
, ctx
->block
);
8940 if (dst
.regClass() == s1
) {
8941 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8942 } else if (dst
.regClass() == v1
) {
8943 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8945 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8946 for (unsigned i
= 0; i
< dst
.size(); i
++)
8947 vec
->operands
[i
] = Operand(0u);
8948 vec
->definitions
[0] = Definition(dst
);
8949 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8954 /* we can use a linear phi in some cases if one src is undef */
8955 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8956 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8958 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8959 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8960 assert(invert
->kind
& block_kind_invert
);
8962 unsigned then_block
= invert
->linear_preds
[0];
8964 Block
* insert_block
= NULL
;
8965 for (unsigned i
= 0; i
< num_operands
; i
++) {
8966 Operand op
= operands
[i
];
8967 if (op
.isUndefined())
8969 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8970 phi
->operands
[0] = op
;
8973 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8974 phi
->operands
[1] = Operand(dst
.regClass());
8975 phi
->definitions
[0] = Definition(dst
);
8976 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8980 /* try to scalarize vector phis */
8981 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8982 // TODO: scalarize linear phis on divergent ifs
8983 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8984 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8985 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8986 Operand src
= operands
[i
];
8987 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8988 can_scalarize
= false;
8990 if (can_scalarize
) {
8991 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8992 assert(dst
.size() % num_components
== 0);
8993 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8995 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8996 for (unsigned k
= 0; k
< num_components
; k
++) {
8997 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8998 for (unsigned i
= 0; i
< num_operands
; i
++) {
8999 Operand src
= operands
[i
];
9000 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9002 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9003 phi
->definitions
[0] = Definition(phi_dst
);
9004 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9005 new_vec
[k
] = phi_dst
;
9006 vec
->operands
[k
] = Operand(phi_dst
);
9008 vec
->definitions
[0] = Definition(dst
);
9009 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9010 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9015 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9016 for (unsigned i
= 0; i
< num_operands
; i
++)
9017 phi
->operands
[i
] = operands
[i
];
9018 phi
->definitions
[0] = Definition(dst
);
9019 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9023 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9025 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9027 assert(dst
.type() == RegType::sgpr
);
9029 if (dst
.size() == 1) {
9030 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9032 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9033 for (unsigned i
= 0; i
< dst
.size(); i
++)
9034 vec
->operands
[i
] = Operand(0u);
9035 vec
->definitions
[0] = Definition(dst
);
9036 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9040 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9042 Builder
bld(ctx
->program
, ctx
->block
);
9043 Block
*logical_target
;
9044 append_logical_end(ctx
->block
);
9045 unsigned idx
= ctx
->block
->index
;
9047 switch (instr
->type
) {
9048 case nir_jump_break
:
9049 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9050 add_logical_edge(idx
, logical_target
);
9051 ctx
->block
->kind
|= block_kind_break
;
9053 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9054 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9055 /* uniform break - directly jump out of the loop */
9056 ctx
->block
->kind
|= block_kind_uniform
;
9057 ctx
->cf_info
.has_branch
= true;
9058 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9059 add_linear_edge(idx
, logical_target
);
9062 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9063 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9065 case nir_jump_continue
:
9066 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9067 add_logical_edge(idx
, logical_target
);
9068 ctx
->block
->kind
|= block_kind_continue
;
9070 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9071 /* for potential uniform breaks after this continue,
9072 we must ensure that they are handled correctly */
9073 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9074 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9075 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9077 /* uniform continue - directly jump to the loop header */
9078 ctx
->block
->kind
|= block_kind_uniform
;
9079 ctx
->cf_info
.has_branch
= true;
9080 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9081 add_linear_edge(idx
, logical_target
);
9086 isel_err(&instr
->instr
, "Unknown NIR jump instr");
9090 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9091 ctx
->cf_info
.exec_potentially_empty_break
= true;
9092 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9095 /* remove critical edges from linear CFG */
9096 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9097 Block
* break_block
= ctx
->program
->create_and_insert_block();
9098 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9099 break_block
->kind
|= block_kind_uniform
;
9100 add_linear_edge(idx
, break_block
);
9101 /* the loop_header pointer might be invalidated by this point */
9102 if (instr
->type
== nir_jump_continue
)
9103 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9104 add_linear_edge(break_block
->index
, logical_target
);
9105 bld
.reset(break_block
);
9106 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9108 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9109 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9110 add_linear_edge(idx
, continue_block
);
9111 append_logical_start(continue_block
);
9112 ctx
->block
= continue_block
;
9116 void visit_block(isel_context
*ctx
, nir_block
*block
)
9118 nir_foreach_instr(instr
, block
) {
9119 switch (instr
->type
) {
9120 case nir_instr_type_alu
:
9121 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9123 case nir_instr_type_load_const
:
9124 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9126 case nir_instr_type_intrinsic
:
9127 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9129 case nir_instr_type_tex
:
9130 visit_tex(ctx
, nir_instr_as_tex(instr
));
9132 case nir_instr_type_phi
:
9133 visit_phi(ctx
, nir_instr_as_phi(instr
));
9135 case nir_instr_type_ssa_undef
:
9136 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9138 case nir_instr_type_deref
:
9140 case nir_instr_type_jump
:
9141 visit_jump(ctx
, nir_instr_as_jump(instr
));
9144 isel_err(instr
, "Unknown NIR instr type");
9149 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9150 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9155 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9156 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9158 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9159 RegClass rc
= vals
[0].regClass();
9161 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9163 unsigned next_pred
= 1;
9165 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9166 Block
& block
= ctx
->program
->blocks
[idx
];
9167 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9168 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9172 if (block
.kind
& block_kind_continue
) {
9173 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9178 bool all_same
= true;
9179 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9180 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9184 val
= vals
[block
.linear_preds
[0] - first
];
9186 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9187 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9188 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9189 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9190 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9191 phi
->definitions
[0] = Definition(val
.getTemp());
9192 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9194 vals
[idx
- first
] = val
;
9197 return vals
[last
- first
];
9200 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9202 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9203 append_logical_end(ctx
->block
);
9204 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9205 Builder
bld(ctx
->program
, ctx
->block
);
9206 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9207 unsigned loop_preheader_idx
= ctx
->block
->index
;
9209 Block loop_exit
= Block();
9210 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9211 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9213 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9214 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9215 loop_header
->kind
|= block_kind_loop_header
;
9216 add_edge(loop_preheader_idx
, loop_header
);
9217 ctx
->block
= loop_header
;
9219 /* emit loop body */
9220 unsigned loop_header_idx
= loop_header
->index
;
9221 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9222 append_logical_start(ctx
->block
);
9223 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9225 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9226 if (!ctx
->cf_info
.has_branch
) {
9227 append_logical_end(ctx
->block
);
9228 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9229 /* Discards can result in code running with an empty exec mask.
9230 * This would result in divergent breaks not ever being taken. As a
9231 * workaround, break the loop when the loop mask is empty instead of
9232 * always continuing. */
9233 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9234 unsigned block_idx
= ctx
->block
->index
;
9236 /* create helper blocks to avoid critical edges */
9237 Block
*break_block
= ctx
->program
->create_and_insert_block();
9238 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9239 break_block
->kind
= block_kind_uniform
;
9240 bld
.reset(break_block
);
9241 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9242 add_linear_edge(block_idx
, break_block
);
9243 add_linear_edge(break_block
->index
, &loop_exit
);
9245 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9246 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9247 continue_block
->kind
= block_kind_uniform
;
9248 bld
.reset(continue_block
);
9249 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9250 add_linear_edge(block_idx
, continue_block
);
9251 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9253 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9254 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9255 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9257 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9258 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9259 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9261 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9264 bld
.reset(ctx
->block
);
9265 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9268 /* Fixup phis in loop header from unreachable blocks.
9269 * has_branch/has_divergent_branch also indicates if the loop ends with a
9270 * break/continue instruction, but we don't emit those if unreachable=true */
9272 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9273 bool linear
= ctx
->cf_info
.has_branch
;
9274 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9275 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9276 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9277 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9278 /* the last operand should be the one that needs to be removed */
9279 instr
->operands
.pop_back();
9280 } else if (!is_phi(instr
)) {
9286 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9287 * and the previous one shouldn't both happen at once because a break in the
9288 * merge block would get CSE'd */
9289 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9290 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9291 Operand vals
[num_vals
];
9292 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9293 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9294 if (ctx
->cf_info
.has_branch
)
9295 instr
->operands
.pop_back();
9297 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9298 } else if (!is_phi(instr
)) {
9304 ctx
->cf_info
.has_branch
= false;
9306 // TODO: if the loop has not a single exit, we must add one °°
9307 /* emit loop successor block */
9308 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9309 append_logical_start(ctx
->block
);
9312 // TODO: check if it is beneficial to not branch on continues
9313 /* trim linear phis in loop header */
9314 for (auto&& instr
: loop_entry
->instructions
) {
9315 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9316 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9317 new_phi
->definitions
[0] = instr
->definitions
[0];
9318 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9319 new_phi
->operands
[i
] = instr
->operands
[i
];
9320 /* check that the remaining operands are all the same */
9321 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9322 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9323 instr
.swap(new_phi
);
9324 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9333 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9337 append_logical_end(ctx
->block
);
9338 ctx
->block
->kind
|= block_kind_branch
;
9340 /* branch to linear then block */
9341 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9342 aco_ptr
<Pseudo_branch_instruction
> branch
;
9343 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 1));
9344 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9345 branch
->definitions
[0].setHint(vcc
);
9346 branch
->operands
[0] = Operand(cond
);
9347 ctx
->block
->instructions
.push_back(std::move(branch
));
9349 ic
->BB_if_idx
= ctx
->block
->index
;
9350 ic
->BB_invert
= Block();
9351 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9352 /* Invert blocks are intentionally not marked as top level because they
9353 * are not part of the logical cfg. */
9354 ic
->BB_invert
.kind
|= block_kind_invert
;
9355 ic
->BB_endif
= Block();
9356 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9357 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9359 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9360 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9361 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9362 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9363 ctx
->cf_info
.parent_if
.is_divergent
= true;
9365 /* divergent branches use cbranch_execz */
9366 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9367 ctx
->cf_info
.exec_potentially_empty_break
= false;
9368 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9370 /** emit logical then block */
9371 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9372 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9373 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9374 ctx
->block
= BB_then_logical
;
9375 append_logical_start(BB_then_logical
);
9378 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9380 Block
*BB_then_logical
= ctx
->block
;
9381 append_logical_end(BB_then_logical
);
9382 /* branch from logical then block to invert block */
9383 aco_ptr
<Pseudo_branch_instruction
> branch
;
9384 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9385 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9386 branch
->definitions
[0].setHint(vcc
);
9387 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9388 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9389 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9390 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9391 BB_then_logical
->kind
|= block_kind_uniform
;
9392 assert(!ctx
->cf_info
.has_branch
);
9393 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9394 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9396 /** emit linear then block */
9397 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9398 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9399 BB_then_linear
->kind
|= block_kind_uniform
;
9400 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9401 /* branch from linear then block to invert block */
9402 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9403 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9404 branch
->definitions
[0].setHint(vcc
);
9405 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9406 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9408 /** emit invert merge block */
9409 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9410 ic
->invert_idx
= ctx
->block
->index
;
9412 /* branch to linear else block (skip else) */
9413 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 1));
9414 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9415 branch
->definitions
[0].setHint(vcc
);
9416 branch
->operands
[0] = Operand(ic
->cond
);
9417 ctx
->block
->instructions
.push_back(std::move(branch
));
9419 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9420 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9421 ic
->exec_potentially_empty_break_depth_old
=
9422 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9423 /* divergent branches use cbranch_execz */
9424 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9425 ctx
->cf_info
.exec_potentially_empty_break
= false;
9426 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9428 /** emit logical else block */
9429 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9430 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9431 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9432 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9433 ctx
->block
= BB_else_logical
;
9434 append_logical_start(BB_else_logical
);
9437 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9439 Block
*BB_else_logical
= ctx
->block
;
9440 append_logical_end(BB_else_logical
);
9442 /* branch from logical else block to endif block */
9443 aco_ptr
<Pseudo_branch_instruction
> branch
;
9444 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9445 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9446 branch
->definitions
[0].setHint(vcc
);
9447 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9448 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9449 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9450 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9451 BB_else_logical
->kind
|= block_kind_uniform
;
9453 assert(!ctx
->cf_info
.has_branch
);
9454 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9457 /** emit linear else block */
9458 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9459 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9460 BB_else_linear
->kind
|= block_kind_uniform
;
9461 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9463 /* branch from linear else block to endif block */
9464 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9465 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9466 branch
->definitions
[0].setHint(vcc
);
9467 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9468 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9471 /** emit endif merge block */
9472 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9473 append_logical_start(ctx
->block
);
9476 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9477 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9478 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9479 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9480 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9481 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9482 !ctx
->cf_info
.parent_if
.is_divergent
) {
9483 ctx
->cf_info
.exec_potentially_empty_break
= false;
9484 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9486 /* uniform control flow never has an empty exec-mask */
9487 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9488 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9489 ctx
->cf_info
.exec_potentially_empty_break
= false;
9490 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9494 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9496 assert(cond
.regClass() == s1
);
9498 append_logical_end(ctx
->block
);
9499 ctx
->block
->kind
|= block_kind_uniform
;
9501 aco_ptr
<Pseudo_branch_instruction
> branch
;
9502 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9503 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 1));
9504 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9505 branch
->definitions
[0].setHint(vcc
);
9506 branch
->operands
[0] = Operand(cond
);
9507 branch
->operands
[0].setFixed(scc
);
9508 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9510 ic
->BB_if_idx
= ctx
->block
->index
;
9511 ic
->BB_endif
= Block();
9512 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9513 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9515 ctx
->cf_info
.has_branch
= false;
9516 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9518 /** emit then block */
9519 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9520 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9521 add_edge(ic
->BB_if_idx
, BB_then
);
9522 append_logical_start(BB_then
);
9523 ctx
->block
= BB_then
;
9526 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9528 Block
*BB_then
= ctx
->block
;
9530 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9531 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9533 if (!ic
->uniform_has_then_branch
) {
9534 append_logical_end(BB_then
);
9535 /* branch from then block to endif block */
9536 aco_ptr
<Pseudo_branch_instruction
> branch
;
9537 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9538 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9539 branch
->definitions
[0].setHint(vcc
);
9540 BB_then
->instructions
.emplace_back(std::move(branch
));
9541 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9542 if (!ic
->then_branch_divergent
)
9543 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9544 BB_then
->kind
|= block_kind_uniform
;
9547 ctx
->cf_info
.has_branch
= false;
9548 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9550 /** emit else block */
9551 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9552 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9553 add_edge(ic
->BB_if_idx
, BB_else
);
9554 append_logical_start(BB_else
);
9555 ctx
->block
= BB_else
;
9558 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9560 Block
*BB_else
= ctx
->block
;
9562 if (!ctx
->cf_info
.has_branch
) {
9563 append_logical_end(BB_else
);
9564 /* branch from then block to endif block */
9565 aco_ptr
<Pseudo_branch_instruction
> branch
;
9566 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9567 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9568 branch
->definitions
[0].setHint(vcc
);
9569 BB_else
->instructions
.emplace_back(std::move(branch
));
9570 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9571 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9572 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9573 BB_else
->kind
|= block_kind_uniform
;
9576 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9577 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9579 /** emit endif merge block */
9580 if (!ctx
->cf_info
.has_branch
) {
9581 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9582 append_logical_start(ctx
->block
);
9586 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9588 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9589 Builder
bld(ctx
->program
, ctx
->block
);
9590 aco_ptr
<Pseudo_branch_instruction
> branch
;
9593 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9595 * Uniform conditionals are represented in the following way*) :
9597 * The linear and logical CFG:
9600 * BB_THEN (logical) BB_ELSE (logical)
9604 * *) Exceptions may be due to break and continue statements within loops
9605 * If a break/continue happens within uniform control flow, it branches
9606 * to the loop exit/entry block. Otherwise, it branches to the next
9610 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9611 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9612 cond
= bool_to_scalar_condition(ctx
, cond
);
9614 begin_uniform_if_then(ctx
, &ic
, cond
);
9615 visit_cf_list(ctx
, &if_stmt
->then_list
);
9617 begin_uniform_if_else(ctx
, &ic
);
9618 visit_cf_list(ctx
, &if_stmt
->else_list
);
9620 end_uniform_if(ctx
, &ic
);
9621 } else { /* non-uniform condition */
9623 * To maintain a logical and linear CFG without critical edges,
9624 * non-uniform conditionals are represented in the following way*) :
9629 * BB_THEN (logical) BB_THEN (linear)
9631 * BB_INVERT (linear)
9633 * BB_ELSE (logical) BB_ELSE (linear)
9640 * BB_THEN (logical) BB_ELSE (logical)
9644 * *) Exceptions may be due to break and continue statements within loops
9647 begin_divergent_if_then(ctx
, &ic
, cond
);
9648 visit_cf_list(ctx
, &if_stmt
->then_list
);
9650 begin_divergent_if_else(ctx
, &ic
);
9651 visit_cf_list(ctx
, &if_stmt
->else_list
);
9653 end_divergent_if(ctx
, &ic
);
9656 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9659 static bool visit_cf_list(isel_context
*ctx
,
9660 struct exec_list
*list
)
9662 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9663 switch (node
->type
) {
9664 case nir_cf_node_block
:
9665 visit_block(ctx
, nir_cf_node_as_block(node
));
9667 case nir_cf_node_if
:
9668 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9671 case nir_cf_node_loop
:
9672 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9675 unreachable("unimplemented cf list type");
9681 static void create_null_export(isel_context
*ctx
)
9683 /* Some shader stages always need to have exports.
9684 * So when there is none, we need to add a null export.
9687 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9688 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9689 Builder
bld(ctx
->program
, ctx
->block
);
9690 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9691 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9694 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9696 assert(ctx
->stage
== vertex_vs
||
9697 ctx
->stage
== tess_eval_vs
||
9698 ctx
->stage
== gs_copy_vs
||
9699 ctx
->stage
== ngg_vertex_gs
||
9700 ctx
->stage
== ngg_tess_eval_gs
);
9702 int offset
= (ctx
->stage
& sw_tes
)
9703 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9704 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9705 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9706 if (!is_pos
&& !mask
)
9708 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9710 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9711 exp
->enabled_mask
= mask
;
9712 for (unsigned i
= 0; i
< 4; ++i
) {
9713 if (mask
& (1 << i
))
9714 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9716 exp
->operands
[i
] = Operand(v1
);
9718 /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9719 * Setting valid_mask=1 prevents it and has no other effect.
9721 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& is_pos
&& *next_pos
== 0;
9723 exp
->compressed
= false;
9725 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9727 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9728 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9733 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9735 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9736 exp
->enabled_mask
= 0;
9737 for (unsigned i
= 0; i
< 4; ++i
)
9738 exp
->operands
[i
] = Operand(v1
);
9739 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9740 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9741 exp
->enabled_mask
|= 0x1;
9743 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9744 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9745 exp
->enabled_mask
|= 0x4;
9747 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9748 if (ctx
->options
->chip_class
< GFX9
) {
9749 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9750 exp
->enabled_mask
|= 0x8;
9752 Builder
bld(ctx
->program
, ctx
->block
);
9754 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9755 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9756 if (exp
->operands
[2].isTemp())
9757 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9759 exp
->operands
[2] = Operand(out
);
9760 exp
->enabled_mask
|= 0x4;
9763 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& *next_pos
== 0;
9765 exp
->compressed
= false;
9766 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9767 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9770 static void create_export_phis(isel_context
*ctx
)
9772 /* Used when exports are needed, but the output temps are defined in a preceding block.
9773 * This function will set up phis in order to access the outputs in the next block.
9776 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9777 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9778 ctx
->block
->instructions
.pop_back();
9780 Builder
bld(ctx
->program
, ctx
->block
);
9782 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9783 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9784 for (unsigned i
= 0; i
< 4; ++i
) {
9785 if (!(mask
& (1 << i
)))
9788 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9789 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9790 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9794 bld
.insert(std::move(logical_start
));
9797 static void create_vs_exports(isel_context
*ctx
)
9799 assert(ctx
->stage
== vertex_vs
||
9800 ctx
->stage
== tess_eval_vs
||
9801 ctx
->stage
== gs_copy_vs
||
9802 ctx
->stage
== ngg_vertex_gs
||
9803 ctx
->stage
== ngg_tess_eval_gs
);
9805 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9806 ? &ctx
->program
->info
->tes
.outinfo
9807 : &ctx
->program
->info
->vs
.outinfo
;
9809 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9810 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9811 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9814 if (ctx
->options
->key
.has_multiview_view_index
) {
9815 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9816 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9819 /* the order these position exports are created is important */
9821 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9822 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9823 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9824 exported_pos
= true;
9826 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9827 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9828 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9829 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9831 if (ctx
->export_clip_dists
) {
9832 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9833 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9834 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9835 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9838 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9839 if (i
< VARYING_SLOT_VAR0
&&
9840 i
!= VARYING_SLOT_LAYER
&&
9841 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9842 i
!= VARYING_SLOT_VIEWPORT
)
9845 export_vs_varying(ctx
, i
, false, NULL
);
9849 create_null_export(ctx
);
9852 static bool export_fs_mrt_z(isel_context
*ctx
)
9854 Builder
bld(ctx
->program
, ctx
->block
);
9855 unsigned enabled_channels
= 0;
9859 for (unsigned i
= 0; i
< 4; ++i
) {
9860 values
[i
] = Operand(v1
);
9863 /* Both stencil and sample mask only need 16-bits. */
9864 if (!ctx
->program
->info
->ps
.writes_z
&&
9865 (ctx
->program
->info
->ps
.writes_stencil
||
9866 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9867 compr
= true; /* COMPR flag */
9869 if (ctx
->program
->info
->ps
.writes_stencil
) {
9870 /* Stencil should be in X[23:16]. */
9871 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9872 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9873 enabled_channels
|= 0x3;
9876 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9877 /* SampleMask should be in Y[15:0]. */
9878 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9879 enabled_channels
|= 0xc;
9882 if (ctx
->program
->info
->ps
.writes_z
) {
9883 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9884 enabled_channels
|= 0x1;
9887 if (ctx
->program
->info
->ps
.writes_stencil
) {
9888 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9889 enabled_channels
|= 0x2;
9892 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9893 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9894 enabled_channels
|= 0x4;
9898 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9899 * writemask component.
9901 if (ctx
->options
->chip_class
== GFX6
&&
9902 ctx
->options
->family
!= CHIP_OLAND
&&
9903 ctx
->options
->family
!= CHIP_HAINAN
) {
9904 enabled_channels
|= 0x1;
9907 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9908 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9913 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9915 Builder
bld(ctx
->program
, ctx
->block
);
9916 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9919 for (unsigned i
= 0; i
< 4; ++i
) {
9920 if (write_mask
& (1 << i
)) {
9921 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9923 values
[i
] = Operand(v1
);
9927 unsigned target
, col_format
;
9928 unsigned enabled_channels
= 0;
9929 aco_opcode compr_op
= (aco_opcode
)0;
9931 slot
-= FRAG_RESULT_DATA0
;
9932 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9933 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9935 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9936 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9937 bool is_16bit
= values
[0].regClass() == v2b
;
9941 case V_028714_SPI_SHADER_ZERO
:
9942 enabled_channels
= 0; /* writemask */
9943 target
= V_008DFC_SQ_EXP_NULL
;
9946 case V_028714_SPI_SHADER_32_R
:
9947 enabled_channels
= 1;
9950 case V_028714_SPI_SHADER_32_GR
:
9951 enabled_channels
= 0x3;
9954 case V_028714_SPI_SHADER_32_AR
:
9955 if (ctx
->options
->chip_class
>= GFX10
) {
9956 /* Special case: on GFX10, the outputs are different for 32_AR */
9957 enabled_channels
= 0x3;
9958 values
[1] = values
[3];
9959 values
[3] = Operand(v1
);
9961 enabled_channels
= 0x9;
9965 case V_028714_SPI_SHADER_FP16_ABGR
:
9966 enabled_channels
= 0x5;
9967 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9969 if (ctx
->options
->chip_class
>= GFX9
) {
9970 /* Pack the FP16 values together instead of converting them to
9971 * FP32 and back to FP16.
9972 * TODO: use p_create_vector and let the compiler optimizes.
9974 compr_op
= aco_opcode::v_pack_b32_f16
;
9976 for (unsigned i
= 0; i
< 4; i
++) {
9977 if ((write_mask
>> i
) & 1)
9978 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9984 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9985 enabled_channels
= 0x5;
9986 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9987 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9989 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9993 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9994 enabled_channels
= 0x5;
9995 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9996 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
9998 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10002 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10003 enabled_channels
= 0x5;
10004 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10005 if (is_int8
|| is_int10
) {
10007 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10008 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10010 for (unsigned i
= 0; i
< 4; i
++) {
10011 if ((write_mask
>> i
) & 1) {
10012 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10013 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10017 } else if (is_16bit
) {
10018 for (unsigned i
= 0; i
< 4; i
++) {
10019 if ((write_mask
>> i
) & 1) {
10020 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10021 values
[i
] = Operand(tmp
);
10028 case V_028714_SPI_SHADER_SINT16_ABGR
:
10029 enabled_channels
= 0x5;
10030 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10031 if (is_int8
|| is_int10
) {
10033 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10034 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10035 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10036 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10038 for (unsigned i
= 0; i
< 4; i
++) {
10039 if ((write_mask
>> i
) & 1) {
10040 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10041 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10043 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10044 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10048 } else if (is_16bit
) {
10049 for (unsigned i
= 0; i
< 4; i
++) {
10050 if ((write_mask
>> i
) & 1) {
10051 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10052 values
[i
] = Operand(tmp
);
10058 case V_028714_SPI_SHADER_32_ABGR
:
10059 enabled_channels
= 0xF;
10066 if (target
== V_008DFC_SQ_EXP_NULL
)
10069 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10070 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10072 (col_format
== V_028714_SPI_SHADER_32_R
||
10073 col_format
== V_028714_SPI_SHADER_32_GR
||
10074 col_format
== V_028714_SPI_SHADER_32_AR
||
10075 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10076 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10077 for (int i
= 0; i
< 4; i
++) {
10078 if (!(write_mask
& (1 << i
)))
10081 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10082 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10083 bld
.copy(bld
.def(v1
), Operand(3u)));
10084 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10085 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10089 if ((bool) compr_op
) {
10090 for (int i
= 0; i
< 2; i
++) {
10091 /* check if at least one of the values to be compressed is enabled */
10092 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10094 enabled_channels
|= enabled
<< (i
*2);
10095 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10096 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10097 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10099 values
[i
] = Operand(v1
);
10102 values
[2] = Operand(v1
);
10103 values
[3] = Operand(v1
);
10105 for (int i
= 0; i
< 4; i
++)
10106 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10109 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10110 enabled_channels
, target
, (bool) compr_op
);
10114 static void create_fs_exports(isel_context
*ctx
)
10116 bool exported
= false;
10118 /* Export depth, stencil and sample mask. */
10119 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10120 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10121 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10122 exported
|= export_fs_mrt_z(ctx
);
10124 /* Export all color render targets. */
10125 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10126 if (ctx
->outputs
.mask
[i
])
10127 exported
|= export_fs_mrt_color(ctx
, i
);
10130 create_null_export(ctx
);
10133 static void create_workgroup_barrier(Builder
& bld
)
10135 bld
.barrier(aco_opcode::p_barrier
,
10136 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10140 static void write_tcs_tess_factors(isel_context
*ctx
)
10142 unsigned outer_comps
;
10143 unsigned inner_comps
;
10145 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10162 Builder
bld(ctx
->program
, ctx
->block
);
10164 create_workgroup_barrier(bld
);
10166 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10167 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10169 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10170 if_context ic_invocation_id_is_zero
;
10171 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10172 bld
.reset(ctx
->block
);
10174 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10176 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10177 unsigned stride
= inner_comps
+ outer_comps
;
10178 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10182 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10184 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10186 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10187 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10188 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10190 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10191 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10193 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10194 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10195 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10196 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10199 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10200 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10201 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10202 unsigned tf_const_offset
= 0;
10204 if (ctx
->program
->chip_class
<= GFX8
) {
10205 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10206 if_context ic_rel_patch_id_is_zero
;
10207 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10208 bld
.reset(ctx
->block
);
10210 /* Store the dynamic HS control word. */
10211 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10212 bld
.mubuf(aco_opcode::buffer_store_dword
,
10213 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10214 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10215 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10216 tf_const_offset
+= 4;
10218 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10219 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10220 bld
.reset(ctx
->block
);
10223 assert(stride
== 2 || stride
== 4 || stride
== 6);
10224 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10225 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10227 /* Store to offchip for TES to read - only if TES reads them */
10228 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10229 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10230 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10232 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10233 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10235 if (likely(inner_comps
)) {
10236 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10237 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10241 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10242 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10245 static void emit_stream_output(isel_context
*ctx
,
10246 Temp
const *so_buffers
,
10247 Temp
const *so_write_offset
,
10248 const struct radv_stream_output
*output
)
10250 unsigned num_comps
= util_bitcount(output
->component_mask
);
10251 unsigned writemask
= (1 << num_comps
) - 1;
10252 unsigned loc
= output
->location
;
10253 unsigned buf
= output
->buffer
;
10255 assert(num_comps
&& num_comps
<= 4);
10256 if (!num_comps
|| num_comps
> 4)
10259 unsigned start
= ffs(output
->component_mask
) - 1;
10262 bool all_undef
= true;
10263 assert(ctx
->stage
& hw_vs
);
10264 for (unsigned i
= 0; i
< num_comps
; i
++) {
10265 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10266 all_undef
= all_undef
&& !out
[i
].id();
10271 while (writemask
) {
10273 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10274 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10275 /* GFX6 doesn't support storing vec3, split it. */
10276 writemask
|= 1u << (start
+ 2);
10280 unsigned offset
= output
->offset
+ start
* 4;
10282 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10283 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10284 for (int i
= 0; i
< count
; ++i
)
10285 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10286 vec
->definitions
[0] = Definition(write_data
);
10287 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10292 opcode
= aco_opcode::buffer_store_dword
;
10295 opcode
= aco_opcode::buffer_store_dwordx2
;
10298 opcode
= aco_opcode::buffer_store_dwordx3
;
10301 opcode
= aco_opcode::buffer_store_dwordx4
;
10304 unreachable("Unsupported dword count.");
10307 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10308 store
->operands
[0] = Operand(so_buffers
[buf
]);
10309 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10310 store
->operands
[2] = Operand((uint32_t) 0);
10311 store
->operands
[3] = Operand(write_data
);
10312 if (offset
> 4095) {
10313 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10314 Builder
bld(ctx
->program
, ctx
->block
);
10315 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10317 store
->offset
= offset
;
10319 store
->offen
= true;
10321 store
->dlc
= false;
10323 ctx
->block
->instructions
.emplace_back(std::move(store
));
10327 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10329 Builder
bld(ctx
->program
, ctx
->block
);
10331 Temp so_buffers
[4];
10332 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10333 for (unsigned i
= 0; i
< 4; i
++) {
10334 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10338 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10339 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10342 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10343 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10345 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10347 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10350 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10352 bld
.reset(ctx
->block
);
10354 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10356 Temp so_write_offset
[4];
10358 for (unsigned i
= 0; i
< 4; i
++) {
10359 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10364 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10365 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10366 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10367 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10369 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10371 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10372 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10373 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10374 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10378 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10379 struct radv_stream_output
*output
=
10380 &ctx
->program
->info
->so
.outputs
[i
];
10381 if (stream
!= output
->stream
)
10384 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10387 begin_divergent_if_else(ctx
, &ic
);
10388 end_divergent_if(ctx
, &ic
);
10391 } /* end namespace */
10393 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10395 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10396 Builder
bld(ctx
->program
, ctx
->block
);
10397 constexpr unsigned hs_idx
= 1u;
10398 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10399 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10400 Operand((8u << 16) | (hs_idx
* 8u)));
10401 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10403 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10405 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10406 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10407 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10408 ls_has_nonzero_hs_threads
);
10409 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10410 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10411 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10412 ls_has_nonzero_hs_threads
);
10413 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10414 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10415 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10416 ls_has_nonzero_hs_threads
);
10418 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10419 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10420 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10423 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10425 /* Split all arguments except for the first (ring_offsets) and the last
10426 * (exec) so that the dead channels don't stay live throughout the program.
10428 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10429 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10430 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10431 startpgm
->definitions
[i
].regClass().size());
10436 void handle_bc_optimize(isel_context
*ctx
)
10438 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10439 Builder
bld(ctx
->program
, ctx
->block
);
10440 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10441 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10442 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10443 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10444 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10445 if (uses_center
&& uses_centroid
) {
10446 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10447 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10449 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10451 for (unsigned i
= 0; i
< 2; i
++) {
10452 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10453 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10454 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10455 persp_centroid
, persp_center
, sel
);
10457 ctx
->persp_centroid
= bld
.tmp(v2
);
10458 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10459 Operand(new_coord
[0]), Operand(new_coord
[1]));
10460 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10463 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10465 for (unsigned i
= 0; i
< 2; i
++) {
10466 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10467 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10468 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10469 linear_centroid
, linear_center
, sel
);
10471 ctx
->linear_centroid
= bld
.tmp(v2
);
10472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10473 Operand(new_coord
[0]), Operand(new_coord
[1]));
10474 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10479 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10481 Program
*program
= ctx
->program
;
10483 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10485 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10486 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10487 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10488 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10489 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10491 program
->next_fp_mode
.must_flush_denorms32
=
10492 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10493 program
->next_fp_mode
.must_flush_denorms16_64
=
10494 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10495 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10497 program
->next_fp_mode
.care_about_round32
=
10498 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10500 program
->next_fp_mode
.care_about_round16_64
=
10501 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10502 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10504 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10505 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10506 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10507 program
->next_fp_mode
.denorm16_64
= 0;
10509 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10511 /* preserving fp32 denorms is expensive, so only do it if asked */
10512 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10513 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10515 program
->next_fp_mode
.denorm32
= 0;
10517 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10518 program
->next_fp_mode
.round32
= fp_round_tz
;
10520 program
->next_fp_mode
.round32
= fp_round_ne
;
10522 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10523 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10525 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10527 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10530 void cleanup_cfg(Program
*program
)
10532 /* create linear_succs/logical_succs */
10533 for (Block
& BB
: program
->blocks
) {
10534 for (unsigned idx
: BB
.linear_preds
)
10535 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10536 for (unsigned idx
: BB
.logical_preds
)
10537 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10541 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10543 Builder
bld(ctx
->program
, ctx
->block
);
10545 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10546 Temp count
= i
== 0
10547 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10548 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10549 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10551 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10554 if (ctx
->program
->wave_size
== 64) {
10555 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10556 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10557 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10559 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10560 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10566 bool ngg_early_prim_export(isel_context
*ctx
)
10568 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10572 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10574 Builder
bld(ctx
->program
, ctx
->block
);
10576 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10577 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10579 /* Get the id of the current wave within the threadgroup (workgroup) */
10580 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10581 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10583 /* Execute the following code only on the first wave (wave id 0),
10584 * use the SCC def to tell if the wave id is zero or not.
10586 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10588 begin_uniform_if_then(ctx
, &ic
, cond
);
10589 begin_uniform_if_else(ctx
, &ic
);
10590 bld
.reset(ctx
->block
);
10592 /* Number of vertices output by VS/TES */
10593 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10594 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10595 /* Number of primitives output by VS/TES */
10596 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10597 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10599 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10600 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10601 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10603 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10604 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10606 end_uniform_if(ctx
, &ic
);
10608 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10609 bld
.reset(ctx
->block
);
10610 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10613 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10615 Builder
bld(ctx
->program
, ctx
->block
);
10617 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10618 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10621 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10624 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10625 assert(vtxindex
[i
].id());
10628 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10632 /* The initial edge flag is always false in tess eval shaders. */
10633 if (ctx
->stage
== ngg_vertex_gs
) {
10634 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10635 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10639 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10644 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10646 Builder
bld(ctx
->program
, ctx
->block
);
10647 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10649 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10650 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10651 false /* compressed */, true/* done */, false /* valid mask */);
10654 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10656 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10657 * These must always come before VS exports.
10659 * It is recommended to do these as early as possible. They can be at the beginning when
10660 * there is no SW GS and the shader doesn't write edge flags.
10664 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10665 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10667 Builder
bld(ctx
->program
, ctx
->block
);
10668 constexpr unsigned max_vertices_per_primitive
= 3;
10669 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10671 if (ctx
->stage
== ngg_vertex_gs
) {
10672 /* TODO: optimize for points & lines */
10673 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10674 if (ctx
->shader
->info
.tess
.point_mode
)
10675 num_vertices_per_primitive
= 1;
10676 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10677 num_vertices_per_primitive
= 2;
10679 unreachable("Unsupported NGG shader stage");
10682 Temp vtxindex
[max_vertices_per_primitive
];
10683 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10684 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10685 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10686 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10687 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10688 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10689 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10690 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10692 /* Export primitive data to the index buffer. */
10693 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10695 /* Export primitive ID. */
10696 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10697 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10698 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10699 Temp provoking_vtx_index
= vtxindex
[0];
10700 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10702 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10705 begin_divergent_if_else(ctx
, &ic
);
10706 end_divergent_if(ctx
, &ic
);
10709 void ngg_emit_nogs_output(isel_context
*ctx
)
10711 /* Emits NGG GS output, for stages that don't have SW GS. */
10714 Builder
bld(ctx
->program
, ctx
->block
);
10715 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10717 /* NGG streamout is currently disabled by default. */
10718 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10720 if (late_prim_export
) {
10721 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10722 create_export_phis(ctx
);
10723 /* Do what we need to do in the GS threads. */
10724 ngg_emit_nogs_gsthreads(ctx
);
10726 /* What comes next should be executed on ES threads. */
10727 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10728 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10729 bld
.reset(ctx
->block
);
10732 /* Export VS outputs */
10733 ctx
->block
->kind
|= block_kind_export_end
;
10734 create_vs_exports(ctx
);
10736 /* Export primitive ID */
10737 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10740 if (ctx
->stage
== ngg_vertex_gs
) {
10741 /* Wait for GS threads to store primitive ID in LDS. */
10742 create_workgroup_barrier(bld
);
10744 /* Calculate LDS address where the GS threads stored the primitive ID. */
10745 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10746 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10747 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10748 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10749 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10750 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10752 /* Load primitive ID from LDS. */
10753 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10754 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10755 /* TES: Just use the patch ID as the primitive ID. */
10756 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10758 unreachable("unsupported NGG shader stage.");
10761 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10762 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10764 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10767 if (late_prim_export
) {
10768 begin_divergent_if_else(ctx
, &ic
);
10769 end_divergent_if(ctx
, &ic
);
10770 bld
.reset(ctx
->block
);
10774 void select_program(Program
*program
,
10775 unsigned shader_count
,
10776 struct nir_shader
*const *shaders
,
10777 ac_shader_config
* config
,
10778 struct radv_shader_args
*args
)
10780 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10781 if_context ic_merged_wave_info
;
10782 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10784 for (unsigned i
= 0; i
< shader_count
; i
++) {
10785 nir_shader
*nir
= shaders
[i
];
10786 init_context(&ctx
, nir
);
10788 setup_fp_mode(&ctx
, nir
);
10791 /* needs to be after init_context() for FS */
10792 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10793 append_logical_start(ctx
.block
);
10795 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10796 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10798 split_arguments(&ctx
, startpgm
);
10802 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10804 if (ngg_early_prim_export(&ctx
))
10805 ngg_emit_nogs_gsthreads(&ctx
);
10808 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10809 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10810 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10811 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10812 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10813 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10814 ctx
.stage
== tess_eval_geometry_gs
));
10816 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10817 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10818 if (check_merged_wave_info
) {
10819 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10820 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10824 Builder
bld(ctx
.program
, ctx
.block
);
10826 create_workgroup_barrier(bld
);
10828 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10829 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10831 } else if (ctx
.stage
== geometry_gs
)
10832 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10834 if (ctx
.stage
== fragment_fs
)
10835 handle_bc_optimize(&ctx
);
10837 visit_cf_list(&ctx
, &func
->body
);
10839 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10840 emit_streamout(&ctx
, 0);
10842 if (ctx
.stage
& hw_vs
) {
10843 create_vs_exports(&ctx
);
10844 ctx
.block
->kind
|= block_kind_export_end
;
10845 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10846 ngg_emit_nogs_output(&ctx
);
10847 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10848 Builder
bld(ctx
.program
, ctx
.block
);
10849 bld
.barrier(aco_opcode::p_barrier
,
10850 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
10851 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10852 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10853 write_tcs_tess_factors(&ctx
);
10856 if (ctx
.stage
== fragment_fs
) {
10857 create_fs_exports(&ctx
);
10858 ctx
.block
->kind
|= block_kind_export_end
;
10861 if (endif_merged_wave_info
) {
10862 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10863 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10866 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10867 ngg_emit_nogs_output(&ctx
);
10869 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10870 /* Outputs of the previous stage are inputs to the next stage */
10871 ctx
.inputs
= ctx
.outputs
;
10872 ctx
.outputs
= shader_io_state();
10876 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10878 append_logical_end(ctx
.block
);
10879 ctx
.block
->kind
|= block_kind_uniform
;
10880 Builder
bld(ctx
.program
, ctx
.block
);
10881 if (ctx
.program
->wb_smem_l1_on_end
)
10882 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
10883 bld
.sopp(aco_opcode::s_endpgm
);
10885 cleanup_cfg(program
);
10888 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10889 ac_shader_config
* config
,
10890 struct radv_shader_args
*args
)
10892 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10894 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10896 add_startpgm(&ctx
);
10897 append_logical_start(ctx
.block
);
10899 Builder
bld(ctx
.program
, ctx
.block
);
10901 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10903 Operand
stream_id(0u);
10904 if (args
->shader_info
->so
.num_outputs
)
10905 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10906 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10908 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10910 std::stack
<Block
> endif_blocks
;
10912 for (unsigned stream
= 0; stream
< 4; stream
++) {
10913 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10916 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10917 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10920 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10922 unsigned BB_if_idx
= ctx
.block
->index
;
10923 Block BB_endif
= Block();
10924 if (!stream_id
.isConstant()) {
10926 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10927 append_logical_end(ctx
.block
);
10928 ctx
.block
->kind
|= block_kind_uniform
;
10929 bld
.branch(aco_opcode::p_cbranch_z
, bld
.hint_vcc(bld
.def(s2
)), cond
);
10931 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10933 ctx
.block
= ctx
.program
->create_and_insert_block();
10934 add_edge(BB_if_idx
, ctx
.block
);
10935 bld
.reset(ctx
.block
);
10936 append_logical_start(ctx
.block
);
10939 unsigned offset
= 0;
10940 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10941 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10944 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10945 unsigned length
= util_last_bit(output_usage_mask
);
10946 for (unsigned j
= 0; j
< length
; ++j
) {
10947 if (!(output_usage_mask
& (1 << j
)))
10950 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10951 Temp voffset
= vtx_offset
;
10952 if (const_offset
>= 4096u) {
10953 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10954 const_offset
%= 4096u;
10957 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10958 mubuf
->definitions
[0] = bld
.def(v1
);
10959 mubuf
->operands
[0] = Operand(gsvs_ring
);
10960 mubuf
->operands
[1] = Operand(voffset
);
10961 mubuf
->operands
[2] = Operand(0u);
10962 mubuf
->offen
= true;
10963 mubuf
->offset
= const_offset
;
10966 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10968 ctx
.outputs
.mask
[i
] |= 1 << j
;
10969 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10971 bld
.insert(std::move(mubuf
));
10977 if (args
->shader_info
->so
.num_outputs
) {
10978 emit_streamout(&ctx
, stream
);
10979 bld
.reset(ctx
.block
);
10983 create_vs_exports(&ctx
);
10984 ctx
.block
->kind
|= block_kind_export_end
;
10987 if (!stream_id
.isConstant()) {
10988 append_logical_end(ctx
.block
);
10990 /* branch from then block to endif block */
10991 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
10992 add_edge(ctx
.block
->index
, &BB_endif
);
10993 ctx
.block
->kind
|= block_kind_uniform
;
10995 /* emit else block */
10996 ctx
.block
= ctx
.program
->create_and_insert_block();
10997 add_edge(BB_if_idx
, ctx
.block
);
10998 bld
.reset(ctx
.block
);
10999 append_logical_start(ctx
.block
);
11001 endif_blocks
.push(std::move(BB_endif
));
11005 while (!endif_blocks
.empty()) {
11006 Block BB_endif
= std::move(endif_blocks
.top());
11007 endif_blocks
.pop();
11009 Block
*BB_else
= ctx
.block
;
11011 append_logical_end(BB_else
);
11012 /* branch from else block to endif block */
11013 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
11014 add_edge(BB_else
->index
, &BB_endif
);
11015 BB_else
->kind
|= block_kind_uniform
;
11017 /** emit endif merge block */
11018 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11019 bld
.reset(ctx
.block
);
11020 append_logical_start(ctx
.block
);
11023 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11025 append_logical_end(ctx
.block
);
11026 ctx
.block
->kind
|= block_kind_uniform
;
11027 bld
.sopp(aco_opcode::s_endpgm
);
11029 cleanup_cfg(program
);
11032 void select_trap_handler_shader(Program
*program
, struct nir_shader
*shader
,
11033 ac_shader_config
* config
,
11034 struct radv_shader_args
*args
)
11036 assert(args
->options
->chip_class
== GFX8
);
11038 init_program(program
, compute_cs
, args
->shader_info
,
11039 args
->options
->chip_class
, args
->options
->family
, config
);
11041 isel_context ctx
= {};
11042 ctx
.program
= program
;
11044 ctx
.options
= args
->options
;
11045 ctx
.stage
= program
->stage
;
11047 ctx
.block
= ctx
.program
->create_and_insert_block();
11048 ctx
.block
->loop_nest_depth
= 0;
11049 ctx
.block
->kind
= block_kind_top_level
;
11051 program
->workgroup_size
= 1; /* XXX */
11053 add_startpgm(&ctx
);
11054 append_logical_start(ctx
.block
);
11056 Builder
bld(ctx
.program
, ctx
.block
);
11058 /* Load the buffer descriptor from TMA. */
11059 bld
.smem(aco_opcode::s_load_dwordx4
, Definition(PhysReg
{ttmp4
}, s4
),
11060 Operand(PhysReg
{tma
}, s2
), Operand(0u));
11062 /* Store TTMP0-TTMP1. */
11063 bld
.smem(aco_opcode::s_buffer_store_dwordx2
, Operand(PhysReg
{ttmp4
}, s4
),
11064 Operand(0u), Operand(PhysReg
{ttmp0
}, s2
), memory_sync_info(), true);
11066 uint32_t hw_regs_idx
[] = {
11067 2, /* HW_REG_STATUS */
11068 3, /* HW_REG_TRAP_STS */
11069 4, /* HW_REG_HW_ID */
11070 7, /* HW_REG_IB_STS */
11073 /* Store some hardware registers. */
11074 for (unsigned i
= 0; i
< ARRAY_SIZE(hw_regs_idx
); i
++) {
11075 /* "((size - 1) << 11) | register" */
11076 bld
.sopk(aco_opcode::s_getreg_b32
, Definition(PhysReg
{ttmp8
}, s1
),
11077 ((20 - 1) << 11) | hw_regs_idx
[i
]);
11079 bld
.smem(aco_opcode::s_buffer_store_dword
, Operand(PhysReg
{ttmp4
}, s4
),
11080 Operand(8u + i
* 4), Operand(PhysReg
{ttmp8
}, s1
), memory_sync_info(), true);
11083 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11085 append_logical_end(ctx
.block
);
11086 ctx
.block
->kind
|= block_kind_uniform
;
11087 bld
.sopp(aco_opcode::s_endpgm
);
11089 cleanup_cfg(program
);