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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
139 } else if (ctx
->program
->chip_class
<= GFX7
) {
140 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
143 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
148 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
150 Builder
bld(ctx
->program
, ctx
->block
);
153 dst
= bld
.tmp(src
.regClass());
155 assert(src
.size() == dst
.size());
157 if (ctx
->stage
!= fragment_fs
) {
161 bld
.copy(Definition(dst
), src
);
165 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
166 ctx
->program
->needs_wqm
|= program_needs_wqm
;
170 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
172 if (index
.regClass() == s1
)
173 return bld
.readlane(bld
.def(s1
), data
, index
);
175 if (ctx
->options
->chip_class
<= GFX7
) {
176 /* GFX6-7: there is no bpermute instruction */
177 Operand
index_op(index
);
178 Operand
input_data(data
);
179 index_op
.setLateKill(true);
180 input_data
.setLateKill(true);
182 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
183 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
184 /* GFX10 wave64 mode: emulate full-wave bpermute */
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
192 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
193 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
194 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
195 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
196 Operand
input_data(data
);
198 index_x4
.setLateKill(true);
199 input_data
.setLateKill(true);
200 same_half
.setLateKill(true);
202 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
204 /* GFX8-9 or GFX10 wave32: bpermute works normally */
205 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
206 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
210 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
212 if (ctx
->options
->chip_class
>= GFX8
) {
213 unsigned and_mask
= mask
& 0x1f;
214 unsigned or_mask
= (mask
>> 5) & 0x1f;
215 unsigned xor_mask
= (mask
>> 10) & 0x1f;
217 uint16_t dpp_ctrl
= 0xffff;
219 // TODO: we could use DPP8 for some swizzles
220 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
221 unsigned res
[4] = {0, 1, 2, 3};
222 for (unsigned i
= 0; i
< 4; i
++)
223 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
224 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
225 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
226 dpp_ctrl
= dpp_row_rr(8);
227 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
228 dpp_ctrl
= dpp_row_mirror
;
229 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
230 dpp_ctrl
= dpp_row_half_mirror
;
233 if (dpp_ctrl
!= 0xffff)
234 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
237 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
240 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
242 if (val
.type() == RegType::sgpr
) {
243 Builder
bld(ctx
->program
, ctx
->block
);
244 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
246 assert(val
.type() == RegType::vgpr
);
250 //assumes a != 0xffffffff
251 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
254 Builder
bld(ctx
->program
, ctx
->block
);
256 if (util_is_power_of_two_or_zero(b
)) {
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
261 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
263 assert(info
.multiplier
<= 0xffffffff);
265 bool pre_shift
= info
.pre_shift
!= 0;
266 bool increment
= info
.increment
!= 0;
267 bool multiply
= true;
268 bool post_shift
= info
.post_shift
!= 0;
270 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
271 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
275 Temp pre_shift_dst
= a
;
277 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
278 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
281 Temp increment_dst
= pre_shift_dst
;
283 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
284 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
287 Temp multiply_dst
= increment_dst
;
289 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
290 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
291 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
299 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
301 Builder
bld(ctx
->program
, ctx
->block
);
302 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
306 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
308 /* no need to extract the whole vector */
309 if (src
.regClass() == dst_rc
) {
314 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
315 Builder
bld(ctx
->program
, ctx
->block
);
316 auto it
= ctx
->allocated_vec
.find(src
.id());
317 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
318 if (it
->second
[idx
].regClass() == dst_rc
) {
319 return it
->second
[idx
];
321 assert(!dst_rc
.is_subdword());
322 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
323 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
327 if (dst_rc
.is_subdword())
328 src
= as_vgpr(ctx
, src
);
330 if (src
.bytes() == dst_rc
.bytes()) {
332 return bld
.copy(bld
.def(dst_rc
), src
);
334 Temp dst
= bld
.tmp(dst_rc
);
335 emit_extract_vector(ctx
, src
, idx
, dst
);
340 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
342 if (num_components
== 1)
344 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
347 if (num_components
> vec_src
.size()) {
348 if (vec_src
.type() == RegType::sgpr
) {
349 /* should still help get_alu_src() */
350 emit_split_vector(ctx
, vec_src
, vec_src
.size());
353 /* sub-dword split */
354 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
356 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
358 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
359 split
->operands
[0] = Operand(vec_src
);
360 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
361 for (unsigned i
= 0; i
< num_components
; i
++) {
362 elems
[i
] = {ctx
->program
->allocateId(), rc
};
363 split
->definitions
[i
] = Definition(elems
[i
]);
365 ctx
->block
->instructions
.emplace_back(std::move(split
));
366 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
369 /* This vector expansion uses a mask to determine which elements in the new vector
370 * come from the original vector. The other elements are undefined. */
371 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
373 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
378 Builder
bld(ctx
->program
, ctx
->block
);
379 if (num_components
== 1) {
380 if (dst
.type() == RegType::sgpr
)
381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
383 bld
.copy(Definition(dst
), vec_src
);
387 unsigned component_size
= dst
.size() / num_components
;
388 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
390 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
391 vec
->definitions
[0] = Definition(dst
);
393 for (unsigned i
= 0; i
< num_components
; i
++) {
394 if (mask
& (1 << i
)) {
395 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
396 if (dst
.type() == RegType::sgpr
)
397 src
= bld
.as_uniform(src
);
398 vec
->operands
[i
] = Operand(src
);
400 vec
->operands
[i
] = Operand(0u);
402 elems
[i
] = vec
->operands
[i
].getTemp();
404 ctx
->block
->instructions
.emplace_back(std::move(vec
));
405 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
408 /* adjust misaligned small bit size loads */
409 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
411 Builder
bld(ctx
->program
, ctx
->block
);
413 Temp select
= Temp();
414 if (offset
.isConstant()) {
415 assert(offset
.constantValue() && offset
.constantValue() < 4);
416 shift
= Operand(offset
.constantValue() * 8);
418 /* bit_offset = 8 * (offset & 0x3) */
419 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
420 select
= bld
.tmp(s1
);
421 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
424 if (vec
.size() == 1) {
425 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
426 } else if (vec
.size() == 2) {
427 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
428 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
430 emit_split_vector(ctx
, dst
, 2);
432 emit_extract_vector(ctx
, tmp
, 0, dst
);
433 } else if (vec
.size() == 4) {
434 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
435 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
436 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
437 if (select
!= Temp())
438 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
439 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
440 Temp mid
= bld
.tmp(s1
);
441 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
442 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
443 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
444 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
445 emit_split_vector(ctx
, dst
, 2);
449 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
451 Builder
bld(ctx
->program
, ctx
->block
);
452 if (offset
.isTemp()) {
453 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
455 if (vec
.size() == 4) {
456 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
458 } else if (vec
.size() == 3) {
459 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
461 } else if (vec
.size() == 2) {
462 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
465 for (unsigned i
= 0; i
< dst
.size(); i
++)
466 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
470 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
472 offset
= Operand(0u);
475 unsigned num_components
= dst
.bytes() / component_size
;
476 if (vec
.regClass() == dst
.regClass()) {
477 assert(offset
.constantValue() == 0);
478 bld
.copy(Definition(dst
), vec
);
479 emit_split_vector(ctx
, dst
, num_components
);
483 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
484 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
485 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
487 assert(offset
.constantValue() % component_size
== 0);
488 unsigned skip
= offset
.constantValue() / component_size
;
489 for (unsigned i
= 0; i
< num_components
; i
++)
490 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
492 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
493 if (dst
.type() == RegType::vgpr
) {
494 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
495 for (unsigned i
= 0; i
< num_components
; i
++)
496 create_vec
->operands
[i
] = Operand(elems
[i
]);
497 create_vec
->definitions
[0] = Definition(dst
);
498 bld
.insert(std::move(create_vec
));
500 /* if dst is sgpr - split the src, but move the original to sgpr. */
502 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
503 byte_align_scalar(ctx
, vec
, offset
, dst
);
505 assert(dst
.size() == vec
.size());
506 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
509 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
512 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
514 Builder
bld(ctx
->program
, ctx
->block
);
516 dst
= bld
.tmp(bld
.lm
);
518 assert(val
.regClass() == s1
);
519 assert(dst
.regClass() == bld
.lm
);
521 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
524 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
526 Builder
bld(ctx
->program
, ctx
->block
);
530 assert(val
.regClass() == bld
.lm
);
531 assert(dst
.regClass() == s1
);
533 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
534 Temp tmp
= bld
.tmp(s1
);
535 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
536 return emit_wqm(ctx
, tmp
, dst
);
539 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
541 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
542 return get_ssa_temp(ctx
, src
.src
.ssa
);
544 if (src
.src
.ssa
->num_components
== size
) {
545 bool identity_swizzle
= true;
546 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
547 if (src
.swizzle
[i
] != i
)
548 identity_swizzle
= false;
550 if (identity_swizzle
)
551 return get_ssa_temp(ctx
, src
.src
.ssa
);
554 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
555 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
556 assert(elem_size
> 0);
557 assert(vec
.bytes() % elem_size
== 0);
559 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
560 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
562 unsigned swizzle
= src
.swizzle
[0];
563 if (vec
.size() > 1) {
564 assert(src
.src
.ssa
->bit_size
== 16);
565 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
566 swizzle
= swizzle
& 1;
571 Temp dst
{ctx
->program
->allocateId(), s1
};
572 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
573 bfe
->operands
[0] = Operand(vec
);
574 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
575 bfe
->definitions
[0] = Definition(dst
);
576 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
577 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
581 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
583 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
586 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
587 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
588 for (unsigned i
= 0; i
< size
; ++i
) {
589 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
590 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
592 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
593 vec_instr
->definitions
[0] = Definition(dst
);
594 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
595 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
600 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
604 Builder
bld(ctx
->program
, ctx
->block
);
605 if (ptr
.type() == RegType::vgpr
)
606 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
607 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
608 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
611 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
613 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
614 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
615 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
616 sop2
->definitions
[0] = Definition(dst
);
618 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
619 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
622 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
623 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
625 Builder
bld(ctx
->program
, ctx
->block
);
626 bld
.is_precise
= instr
->exact
;
628 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
629 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
630 if (src1
.type() == RegType::sgpr
) {
631 if (commutative
&& src0
.type() == RegType::vgpr
) {
636 src1
= as_vgpr(ctx
, src1
);
640 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
641 assert(dst
.size() == 1);
642 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
643 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
645 bld
.vop2(op
, Definition(dst
), src0
, src1
);
649 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
650 aco_opcode op
, Temp dst
)
652 Builder
bld(ctx
->program
, ctx
->block
);
653 bld
.is_precise
= instr
->exact
;
655 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
656 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
658 if (src1
.type() == RegType::sgpr
) {
659 assert(src0
.type() == RegType::vgpr
);
660 std::swap(src0
, src1
);
663 Temp src00
= bld
.tmp(src0
.type(), 1);
664 Temp src01
= bld
.tmp(src0
.type(), 1);
665 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
666 Temp src10
= bld
.tmp(v1
);
667 Temp src11
= bld
.tmp(v1
);
668 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
669 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
670 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
671 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
674 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
675 bool flush_denorms
= false)
677 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
678 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
679 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
681 /* ensure that the instruction has at most 1 sgpr operand
682 * The optimizer will inline constants for us */
683 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
684 src0
= as_vgpr(ctx
, src0
);
685 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
686 src1
= as_vgpr(ctx
, src1
);
687 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
688 src2
= as_vgpr(ctx
, src2
);
690 Builder
bld(ctx
->program
, ctx
->block
);
691 bld
.is_precise
= instr
->exact
;
692 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
693 assert(dst
.size() == 1);
694 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
695 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
697 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
701 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
703 Builder
bld(ctx
->program
, ctx
->block
);
704 bld
.is_precise
= instr
->exact
;
705 if (dst
.type() == RegType::sgpr
)
706 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
707 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
709 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
712 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
714 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
715 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
716 assert(src0
.size() == src1
.size());
718 aco_ptr
<Instruction
> vopc
;
719 if (src1
.type() == RegType::sgpr
) {
720 if (src0
.type() == RegType::vgpr
) {
721 /* to swap the operands, we might also have to change the opcode */
723 case aco_opcode::v_cmp_lt_f16
:
724 op
= aco_opcode::v_cmp_gt_f16
;
726 case aco_opcode::v_cmp_ge_f16
:
727 op
= aco_opcode::v_cmp_le_f16
;
729 case aco_opcode::v_cmp_lt_i16
:
730 op
= aco_opcode::v_cmp_gt_i16
;
732 case aco_opcode::v_cmp_ge_i16
:
733 op
= aco_opcode::v_cmp_le_i16
;
735 case aco_opcode::v_cmp_lt_u16
:
736 op
= aco_opcode::v_cmp_gt_u16
;
738 case aco_opcode::v_cmp_ge_u16
:
739 op
= aco_opcode::v_cmp_le_u16
;
741 case aco_opcode::v_cmp_lt_f32
:
742 op
= aco_opcode::v_cmp_gt_f32
;
744 case aco_opcode::v_cmp_ge_f32
:
745 op
= aco_opcode::v_cmp_le_f32
;
747 case aco_opcode::v_cmp_lt_i32
:
748 op
= aco_opcode::v_cmp_gt_i32
;
750 case aco_opcode::v_cmp_ge_i32
:
751 op
= aco_opcode::v_cmp_le_i32
;
753 case aco_opcode::v_cmp_lt_u32
:
754 op
= aco_opcode::v_cmp_gt_u32
;
756 case aco_opcode::v_cmp_ge_u32
:
757 op
= aco_opcode::v_cmp_le_u32
;
759 case aco_opcode::v_cmp_lt_f64
:
760 op
= aco_opcode::v_cmp_gt_f64
;
762 case aco_opcode::v_cmp_ge_f64
:
763 op
= aco_opcode::v_cmp_le_f64
;
765 case aco_opcode::v_cmp_lt_i64
:
766 op
= aco_opcode::v_cmp_gt_i64
;
768 case aco_opcode::v_cmp_ge_i64
:
769 op
= aco_opcode::v_cmp_le_i64
;
771 case aco_opcode::v_cmp_lt_u64
:
772 op
= aco_opcode::v_cmp_gt_u64
;
774 case aco_opcode::v_cmp_ge_u64
:
775 op
= aco_opcode::v_cmp_le_u64
;
777 default: /* eq and ne are commutative */
784 src1
= as_vgpr(ctx
, src1
);
788 Builder
bld(ctx
->program
, ctx
->block
);
789 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
792 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
794 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
795 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
796 Builder
bld(ctx
->program
, ctx
->block
);
798 assert(dst
.regClass() == bld
.lm
);
799 assert(src0
.type() == RegType::sgpr
);
800 assert(src1
.type() == RegType::sgpr
);
801 assert(src0
.regClass() == src1
.regClass());
803 /* Emit the SALU comparison instruction */
804 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
805 /* Turn the result into a per-lane bool */
806 bool_to_vector_condition(ctx
, cmp
, dst
);
809 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
810 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
812 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
813 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
814 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
815 nir_dest_is_divergent(instr
->dest
.dest
) ||
816 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
817 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
818 aco_opcode op
= use_valu
? v_op
: s_op
;
819 assert(op
!= aco_opcode::num_opcodes
);
820 assert(dst
.regClass() == ctx
->program
->lane_mask
);
823 emit_vopc_instruction(ctx
, instr
, op
, dst
);
825 emit_sopc_instruction(ctx
, instr
, op
, dst
);
828 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
830 Builder
bld(ctx
->program
, ctx
->block
);
831 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
832 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
834 assert(dst
.regClass() == bld
.lm
);
835 assert(src0
.regClass() == bld
.lm
);
836 assert(src1
.regClass() == bld
.lm
);
838 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
841 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
843 Builder
bld(ctx
->program
, ctx
->block
);
844 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
845 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
846 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
848 assert(cond
.regClass() == bld
.lm
);
850 if (dst
.type() == RegType::vgpr
) {
851 aco_ptr
<Instruction
> bcsel
;
852 if (dst
.size() == 1) {
853 then
= as_vgpr(ctx
, then
);
854 els
= as_vgpr(ctx
, els
);
856 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
857 } else if (dst
.size() == 2) {
858 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
859 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
860 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
863 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
864 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
866 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
868 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
869 nir_print_instr(&instr
->instr
, stderr
);
870 fprintf(stderr
, "\n");
875 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
876 assert(dst
.regClass() == bld
.lm
);
877 assert(then
.regClass() == bld
.lm
);
878 assert(els
.regClass() == bld
.lm
);
881 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
882 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
883 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
884 assert(dst
.size() == then
.size());
885 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
886 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
888 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
889 nir_print_instr(&instr
->instr
, stderr
);
890 fprintf(stderr
, "\n");
895 /* divergent boolean bcsel
896 * this implements bcsel on bools: dst = s0 ? s1 : s2
897 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
898 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
900 if (cond
.id() != then
.id())
901 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
903 if (cond
.id() == els
.id())
904 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
906 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
907 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
910 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
911 aco_opcode op
, uint32_t undo
)
913 /* multiply by 16777216 to handle denormals */
914 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
915 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
916 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
917 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
918 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
920 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
922 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
925 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
927 if (ctx
->block
->fp_mode
.denorm32
== 0) {
928 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
932 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
935 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
937 if (ctx
->block
->fp_mode
.denorm32
== 0) {
938 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
942 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
945 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
947 if (ctx
->block
->fp_mode
.denorm32
== 0) {
948 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
952 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
955 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
957 if (ctx
->block
->fp_mode
.denorm32
== 0) {
958 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
962 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
965 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
967 if (ctx
->options
->chip_class
>= GFX7
)
968 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
970 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
971 /* TODO: create more efficient code! */
972 if (val
.type() == RegType::sgpr
)
973 val
= as_vgpr(ctx
, val
);
975 /* Split the input value. */
976 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
977 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
979 /* Extract the exponent and compute the unbiased value. */
980 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
981 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
983 /* Extract the fractional part. */
984 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
985 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
987 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
988 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
990 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
991 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
992 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
993 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
994 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
996 /* Get the sign bit. */
997 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
999 /* Decide the operation to apply depending on the unbiased exponent. */
1000 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1001 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1002 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1003 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1004 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1005 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1007 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1010 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1012 if (ctx
->options
->chip_class
>= GFX7
)
1013 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1015 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1016 * lowered at NIR level for precision reasons). */
1017 Temp src0
= as_vgpr(ctx
, val
);
1019 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1020 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1022 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1023 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1024 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1026 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1027 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1028 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1031 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1032 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1034 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1036 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1037 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1039 return add
->definitions
[0].getTemp();
1042 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1044 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1045 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1047 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1050 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1051 return bld
.copy(Definition(dst
), src
);
1052 else if (dst
.bytes() < src
.bytes())
1053 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1057 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1060 } else if (src
.regClass() == s1
) {
1062 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1064 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1065 } else if (ctx
->options
->chip_class
>= GFX8
) {
1066 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1067 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1068 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1069 sdwa
->operands
[0] = Operand(src
);
1070 sdwa
->definitions
[0] = Definition(tmp
);
1072 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1074 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1075 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1076 bld
.insert(std::move(sdwa
));
1078 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1079 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1080 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1083 if (dst_bits
== 64) {
1084 if (is_signed
&& dst
.regClass() == s2
) {
1085 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1086 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1087 } else if (is_signed
&& dst
.regClass() == v2
) {
1088 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1089 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1091 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1098 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1100 if (!instr
->dest
.dest
.is_ssa
) {
1101 fprintf(stderr
, "nir alu dst not in ssa: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1106 Builder
bld(ctx
->program
, ctx
->block
);
1107 bld
.is_precise
= instr
->exact
;
1108 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1113 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1114 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1115 for (unsigned i
= 0; i
< num
; ++i
)
1116 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1118 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1119 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1120 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1121 for (unsigned i
= 0; i
< num
; ++i
) {
1122 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1123 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1125 vec
->operands
[i
] = Operand
{elems
[i
]};
1127 vec
->definitions
[0] = Definition(dst
);
1128 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1129 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1131 // TODO: that is a bit suboptimal..
1132 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1133 for (unsigned i
= 0; i
< num
- 1; ++i
)
1134 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1135 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1136 for (unsigned i
= 0; i
< num
; ++i
) {
1137 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1138 if (bit
% 32 == 0) {
1139 elems
[bit
/ 32] = elems
[i
];
1141 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1142 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1143 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1146 if (dst
.size() == 1)
1147 bld
.copy(Definition(dst
), elems
[0]);
1149 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1154 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1155 aco_ptr
<Instruction
> mov
;
1156 if (dst
.type() == RegType::sgpr
) {
1157 if (src
.type() == RegType::vgpr
)
1158 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1159 else if (src
.regClass() == s1
)
1160 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1161 else if (src
.regClass() == s2
)
1162 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1164 unreachable("wrong src register class for nir_op_imov");
1166 if (dst
.regClass() == v1
)
1167 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1168 else if (dst
.regClass() == v1b
||
1169 dst
.regClass() == v2b
||
1170 dst
.regClass() == v2
)
1171 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1173 unreachable("wrong src register class for nir_op_imov");
1178 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1179 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1180 assert(src
.regClass() == bld
.lm
);
1181 assert(dst
.regClass() == bld
.lm
);
1182 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1183 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1184 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1185 } else if (dst
.regClass() == v1
) {
1186 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1187 } else if (dst
.regClass() == v2
) {
1188 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1189 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1190 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1191 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1192 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1193 } else if (dst
.type() == RegType::sgpr
) {
1194 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1195 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1198 nir_print_instr(&instr
->instr
, stderr
);
1199 fprintf(stderr
, "\n");
1204 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1205 if (dst
.regClass() == v1
) {
1206 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1207 } else if (dst
.regClass() == s1
) {
1208 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1209 } else if (dst
.size() == 2) {
1210 Temp src0
= bld
.tmp(dst
.type(), 1);
1211 Temp src1
= bld
.tmp(dst
.type(), 1);
1212 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1214 if (dst
.regClass() == s2
) {
1215 Temp carry
= bld
.tmp(s1
);
1216 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1217 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1218 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1220 Temp lower
= bld
.tmp(v1
);
1221 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1222 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1223 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1226 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1227 nir_print_instr(&instr
->instr
, stderr
);
1228 fprintf(stderr
, "\n");
1233 if (dst
.regClass() == s1
) {
1234 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1235 } else if (dst
.regClass() == v1
) {
1236 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1237 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1239 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1240 nir_print_instr(&instr
->instr
, stderr
);
1241 fprintf(stderr
, "\n");
1245 case nir_op_isign
: {
1246 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1247 if (dst
.regClass() == s1
) {
1248 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1249 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1250 } else if (dst
.regClass() == s2
) {
1251 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1253 if (ctx
->program
->chip_class
>= GFX8
)
1254 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1256 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1257 /* SCC gets zero-extended to 64 bit */
1258 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1259 } else if (dst
.regClass() == v1
) {
1260 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1261 } else if (dst
.regClass() == v2
) {
1262 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1263 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1264 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1265 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1266 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1267 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1276 if (dst
.regClass() == v1
) {
1277 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1278 } else if (dst
.regClass() == s1
) {
1279 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1281 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1282 nir_print_instr(&instr
->instr
, stderr
);
1283 fprintf(stderr
, "\n");
1288 if (dst
.regClass() == v1
) {
1289 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1290 } else if (dst
.regClass() == s1
) {
1291 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1293 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1294 nir_print_instr(&instr
->instr
, stderr
);
1295 fprintf(stderr
, "\n");
1300 if (dst
.regClass() == v1
) {
1301 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1302 } else if (dst
.regClass() == s1
) {
1303 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1305 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1306 nir_print_instr(&instr
->instr
, stderr
);
1307 fprintf(stderr
, "\n");
1312 if (dst
.regClass() == v1
) {
1313 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1314 } else if (dst
.regClass() == s1
) {
1315 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1318 nir_print_instr(&instr
->instr
, stderr
);
1319 fprintf(stderr
, "\n");
1324 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1325 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1326 } else if (dst
.regClass() == v1
) {
1327 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1328 } else if (dst
.regClass() == v2
) {
1329 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1330 } else if (dst
.regClass() == s1
) {
1331 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1332 } else if (dst
.regClass() == s2
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1335 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1336 nir_print_instr(&instr
->instr
, stderr
);
1337 fprintf(stderr
, "\n");
1342 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1343 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1344 } else if (dst
.regClass() == v1
) {
1345 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1346 } else if (dst
.regClass() == v2
) {
1347 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1348 } else if (dst
.regClass() == s1
) {
1349 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1350 } else if (dst
.regClass() == s2
) {
1351 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1353 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1354 nir_print_instr(&instr
->instr
, stderr
);
1355 fprintf(stderr
, "\n");
1360 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1361 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1362 } else if (dst
.regClass() == v1
) {
1363 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1364 } else if (dst
.regClass() == v2
) {
1365 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1366 } else if (dst
.regClass() == s1
) {
1367 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1368 } else if (dst
.regClass() == s2
) {
1369 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1371 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1372 nir_print_instr(&instr
->instr
, stderr
);
1373 fprintf(stderr
, "\n");
1378 if (dst
.regClass() == v1
) {
1379 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1380 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1381 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1382 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1383 } else if (dst
.regClass() == v2
) {
1384 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1385 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1386 } else if (dst
.regClass() == s2
) {
1387 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1388 } else if (dst
.regClass() == s1
) {
1389 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1391 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1392 nir_print_instr(&instr
->instr
, stderr
);
1393 fprintf(stderr
, "\n");
1398 if (dst
.regClass() == v1
) {
1399 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1400 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1401 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1402 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1403 } else if (dst
.regClass() == v2
) {
1404 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1405 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1406 } else if (dst
.regClass() == s1
) {
1407 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1408 } else if (dst
.regClass() == s2
) {
1409 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1412 nir_print_instr(&instr
->instr
, stderr
);
1413 fprintf(stderr
, "\n");
1418 if (dst
.regClass() == v1
) {
1419 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1420 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1421 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1423 } else if (dst
.regClass() == v2
) {
1424 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1425 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1426 } else if (dst
.regClass() == s1
) {
1427 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1428 } else if (dst
.regClass() == s2
) {
1429 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1431 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1432 nir_print_instr(&instr
->instr
, stderr
);
1433 fprintf(stderr
, "\n");
1437 case nir_op_find_lsb
: {
1438 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1439 if (src
.regClass() == s1
) {
1440 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1441 } else if (src
.regClass() == v1
) {
1442 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1443 } else if (src
.regClass() == s2
) {
1444 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1446 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1447 nir_print_instr(&instr
->instr
, stderr
);
1448 fprintf(stderr
, "\n");
1452 case nir_op_ufind_msb
:
1453 case nir_op_ifind_msb
: {
1454 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1455 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1456 aco_opcode op
= src
.regClass() == s2
?
1457 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1458 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1459 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1461 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1462 Operand(src
.size() * 32u - 1u), msb_rev
);
1463 Temp msb
= sub
.def(0).getTemp();
1464 Temp carry
= sub
.def(1).getTemp();
1466 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1467 } else if (src
.regClass() == v1
) {
1468 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1469 Temp msb_rev
= bld
.tmp(v1
);
1470 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1471 Temp msb
= bld
.tmp(v1
);
1472 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1473 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1475 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1476 nir_print_instr(&instr
->instr
, stderr
);
1477 fprintf(stderr
, "\n");
1481 case nir_op_bitfield_reverse
: {
1482 if (dst
.regClass() == s1
) {
1483 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1484 } else if (dst
.regClass() == v1
) {
1485 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1487 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1488 nir_print_instr(&instr
->instr
, stderr
);
1489 fprintf(stderr
, "\n");
1494 if (dst
.regClass() == s1
) {
1495 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1499 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1500 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1501 if (dst
.regClass() == v1
) {
1502 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1506 assert(src0
.size() == 2 && src1
.size() == 2);
1507 Temp src00
= bld
.tmp(src0
.type(), 1);
1508 Temp src01
= bld
.tmp(dst
.type(), 1);
1509 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1510 Temp src10
= bld
.tmp(src1
.type(), 1);
1511 Temp src11
= bld
.tmp(dst
.type(), 1);
1512 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1514 if (dst
.regClass() == s2
) {
1515 Temp carry
= bld
.tmp(s1
);
1516 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1517 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1518 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1519 } else if (dst
.regClass() == v2
) {
1520 Temp dst0
= bld
.tmp(v1
);
1521 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1522 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1526 nir_print_instr(&instr
->instr
, stderr
);
1527 fprintf(stderr
, "\n");
1531 case nir_op_uadd_sat
: {
1532 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1533 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1534 if (dst
.regClass() == s1
) {
1535 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1536 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1538 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1539 } else if (dst
.regClass() == v1
) {
1540 if (ctx
->options
->chip_class
>= GFX9
) {
1541 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1542 add
->operands
[0] = Operand(src0
);
1543 add
->operands
[1] = Operand(src1
);
1544 add
->definitions
[0] = Definition(dst
);
1546 ctx
->block
->instructions
.emplace_back(std::move(add
));
1548 if (src1
.regClass() != v1
)
1549 std::swap(src0
, src1
);
1550 assert(src1
.regClass() == v1
);
1551 Temp tmp
= bld
.tmp(v1
);
1552 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1553 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1556 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1557 nir_print_instr(&instr
->instr
, stderr
);
1558 fprintf(stderr
, "\n");
1562 case nir_op_uadd_carry
: {
1563 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1564 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1565 if (dst
.regClass() == s1
) {
1566 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1569 if (dst
.regClass() == v1
) {
1570 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1571 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1575 Temp src00
= bld
.tmp(src0
.type(), 1);
1576 Temp src01
= bld
.tmp(dst
.type(), 1);
1577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1578 Temp src10
= bld
.tmp(src1
.type(), 1);
1579 Temp src11
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1581 if (dst
.regClass() == s2
) {
1582 Temp carry
= bld
.tmp(s1
);
1583 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1584 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1586 } else if (dst
.regClass() == v2
) {
1587 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1588 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1589 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1592 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1593 nir_print_instr(&instr
->instr
, stderr
);
1594 fprintf(stderr
, "\n");
1599 if (dst
.regClass() == s1
) {
1600 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1604 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1605 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1606 if (dst
.regClass() == v1
) {
1607 bld
.vsub32(Definition(dst
), src0
, src1
);
1611 Temp src00
= bld
.tmp(src0
.type(), 1);
1612 Temp src01
= bld
.tmp(dst
.type(), 1);
1613 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1614 Temp src10
= bld
.tmp(src1
.type(), 1);
1615 Temp src11
= bld
.tmp(dst
.type(), 1);
1616 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1617 if (dst
.regClass() == s2
) {
1618 Temp carry
= bld
.tmp(s1
);
1619 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1620 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1621 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1622 } else if (dst
.regClass() == v2
) {
1623 Temp lower
= bld
.tmp(v1
);
1624 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1625 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1626 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1628 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1629 nir_print_instr(&instr
->instr
, stderr
);
1630 fprintf(stderr
, "\n");
1634 case nir_op_usub_borrow
: {
1635 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1636 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1637 if (dst
.regClass() == s1
) {
1638 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1640 } else if (dst
.regClass() == v1
) {
1641 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1642 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1646 Temp src00
= bld
.tmp(src0
.type(), 1);
1647 Temp src01
= bld
.tmp(dst
.type(), 1);
1648 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1649 Temp src10
= bld
.tmp(src1
.type(), 1);
1650 Temp src11
= bld
.tmp(dst
.type(), 1);
1651 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1652 if (dst
.regClass() == s2
) {
1653 Temp borrow
= bld
.tmp(s1
);
1654 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1655 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1656 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1657 } else if (dst
.regClass() == v2
) {
1658 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1659 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1660 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1661 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1663 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1664 nir_print_instr(&instr
->instr
, stderr
);
1665 fprintf(stderr
, "\n");
1670 if (dst
.regClass() == v1
) {
1671 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1672 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1673 } else if (dst
.regClass() == s1
) {
1674 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1676 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1677 nir_print_instr(&instr
->instr
, stderr
);
1678 fprintf(stderr
, "\n");
1682 case nir_op_umul_high
: {
1683 if (dst
.regClass() == v1
) {
1684 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1685 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1686 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1687 } else if (dst
.regClass() == s1
) {
1688 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1689 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1690 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1692 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1693 nir_print_instr(&instr
->instr
, stderr
);
1694 fprintf(stderr
, "\n");
1698 case nir_op_imul_high
: {
1699 if (dst
.regClass() == v1
) {
1700 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1701 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1702 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1703 } else if (dst
.regClass() == s1
) {
1704 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1705 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1706 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1708 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1709 nir_print_instr(&instr
->instr
, stderr
);
1710 fprintf(stderr
, "\n");
1715 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1716 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1717 if (dst
.regClass() == v2b
) {
1718 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1719 } else if (dst
.regClass() == v1
) {
1720 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1721 } else if (dst
.regClass() == v2
) {
1722 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1724 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1725 nir_print_instr(&instr
->instr
, stderr
);
1726 fprintf(stderr
, "\n");
1731 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1732 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1733 if (dst
.regClass() == v2b
) {
1734 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1735 } else if (dst
.regClass() == v1
) {
1736 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1737 } else if (dst
.regClass() == v2
) {
1738 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1740 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1741 nir_print_instr(&instr
->instr
, stderr
);
1742 fprintf(stderr
, "\n");
1747 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1748 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1749 if (dst
.regClass() == v2b
) {
1750 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1751 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1753 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1754 } else if (dst
.regClass() == v1
) {
1755 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1756 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1758 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1759 } else if (dst
.regClass() == v2
) {
1760 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1761 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1762 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1765 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1766 nir_print_instr(&instr
->instr
, stderr
);
1767 fprintf(stderr
, "\n");
1772 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1773 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1774 if (dst
.regClass() == v2b
) {
1775 // TODO: check fp_mode.must_flush_denorms16_64
1776 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1777 } else if (dst
.regClass() == v1
) {
1778 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1779 } else if (dst
.regClass() == v2
) {
1780 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1781 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1782 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1784 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1794 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1795 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1796 if (dst
.regClass() == v2b
) {
1797 // TODO: check fp_mode.must_flush_denorms16_64
1798 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1799 } else if (dst
.regClass() == v1
) {
1800 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1801 } else if (dst
.regClass() == v2
) {
1802 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1803 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1804 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1806 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1809 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1810 nir_print_instr(&instr
->instr
, stderr
);
1811 fprintf(stderr
, "\n");
1815 case nir_op_fmax3
: {
1816 if (dst
.regClass() == v2b
) {
1817 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1818 } else if (dst
.regClass() == v1
) {
1819 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1821 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1822 nir_print_instr(&instr
->instr
, stderr
);
1823 fprintf(stderr
, "\n");
1827 case nir_op_fmin3
: {
1828 if (dst
.regClass() == v2b
) {
1829 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1830 } else if (dst
.regClass() == v1
) {
1831 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1833 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1834 nir_print_instr(&instr
->instr
, stderr
);
1835 fprintf(stderr
, "\n");
1839 case nir_op_fmed3
: {
1840 if (dst
.regClass() == v2b
) {
1841 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1842 } else if (dst
.regClass() == v1
) {
1843 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1845 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1846 nir_print_instr(&instr
->instr
, stderr
);
1847 fprintf(stderr
, "\n");
1851 case nir_op_umax3
: {
1852 if (dst
.size() == 1) {
1853 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1855 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1856 nir_print_instr(&instr
->instr
, stderr
);
1857 fprintf(stderr
, "\n");
1861 case nir_op_umin3
: {
1862 if (dst
.size() == 1) {
1863 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1865 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1866 nir_print_instr(&instr
->instr
, stderr
);
1867 fprintf(stderr
, "\n");
1871 case nir_op_umed3
: {
1872 if (dst
.size() == 1) {
1873 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1875 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1876 nir_print_instr(&instr
->instr
, stderr
);
1877 fprintf(stderr
, "\n");
1881 case nir_op_imax3
: {
1882 if (dst
.size() == 1) {
1883 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1885 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1886 nir_print_instr(&instr
->instr
, stderr
);
1887 fprintf(stderr
, "\n");
1891 case nir_op_imin3
: {
1892 if (dst
.size() == 1) {
1893 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1895 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1896 nir_print_instr(&instr
->instr
, stderr
);
1897 fprintf(stderr
, "\n");
1901 case nir_op_imed3
: {
1902 if (dst
.size() == 1) {
1903 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_cube_face_coord
: {
1912 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1913 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1914 emit_extract_vector(ctx
, in
, 1, v1
),
1915 emit_extract_vector(ctx
, in
, 2, v1
) };
1916 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1917 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1918 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1919 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1920 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1921 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1922 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1925 case nir_op_cube_face_index
: {
1926 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1927 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1928 emit_extract_vector(ctx
, in
, 1, v1
),
1929 emit_extract_vector(ctx
, in
, 2, v1
) };
1930 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1933 case nir_op_bcsel
: {
1934 emit_bcsel(ctx
, instr
, dst
);
1938 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1939 if (dst
.regClass() == v2b
) {
1940 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1941 } else if (dst
.regClass() == v1
) {
1942 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1943 } else if (dst
.regClass() == v2
) {
1944 /* Lowered at NIR level for precision reasons. */
1945 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1947 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1948 nir_print_instr(&instr
->instr
, stderr
);
1949 fprintf(stderr
, "\n");
1954 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1955 if (dst
.regClass() == v2b
) {
1956 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1957 } else if (dst
.regClass() == v1
) {
1958 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1959 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1960 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1961 } else if (dst
.regClass() == v2
) {
1962 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1963 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1964 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1965 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1966 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1967 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1969 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1970 nir_print_instr(&instr
->instr
, stderr
);
1971 fprintf(stderr
, "\n");
1976 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1977 if (dst
.regClass() == v2b
) {
1978 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1979 } else if (dst
.regClass() == v1
) {
1980 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1981 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1982 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1983 } else if (dst
.regClass() == v2
) {
1984 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1985 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1986 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1987 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1988 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1989 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1991 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1992 nir_print_instr(&instr
->instr
, stderr
);
1993 fprintf(stderr
, "\n");
1998 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1999 if (dst
.regClass() == v2b
) {
2000 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
2001 } else if (dst
.regClass() == v1
) {
2002 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2003 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
2004 // TODO: confirm that this holds under any circumstances
2005 } else if (dst
.regClass() == v2
) {
2006 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
2007 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
2010 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2011 nir_print_instr(&instr
->instr
, stderr
);
2012 fprintf(stderr
, "\n");
2016 case nir_op_flog2
: {
2017 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2018 if (dst
.regClass() == v2b
) {
2019 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
2020 } else if (dst
.regClass() == v1
) {
2021 emit_log2(ctx
, bld
, Definition(dst
), src
);
2023 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2024 nir_print_instr(&instr
->instr
, stderr
);
2025 fprintf(stderr
, "\n");
2030 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2031 if (dst
.regClass() == v2b
) {
2032 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2033 } else if (dst
.regClass() == v1
) {
2034 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2035 } else if (dst
.regClass() == v2
) {
2036 /* Lowered at NIR level for precision reasons. */
2037 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2039 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2040 nir_print_instr(&instr
->instr
, stderr
);
2041 fprintf(stderr
, "\n");
2045 case nir_op_fexp2
: {
2046 if (dst
.regClass() == v2b
) {
2047 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2048 } else if (dst
.regClass() == v1
) {
2049 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2051 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2052 nir_print_instr(&instr
->instr
, stderr
);
2053 fprintf(stderr
, "\n");
2057 case nir_op_fsqrt
: {
2058 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2059 if (dst
.regClass() == v2b
) {
2060 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2061 } else if (dst
.regClass() == v1
) {
2062 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2063 } else if (dst
.regClass() == v2
) {
2064 /* Lowered at NIR level for precision reasons. */
2065 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2068 nir_print_instr(&instr
->instr
, stderr
);
2069 fprintf(stderr
, "\n");
2073 case nir_op_ffract
: {
2074 if (dst
.regClass() == v2b
) {
2075 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2076 } else if (dst
.regClass() == v1
) {
2077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2078 } else if (dst
.regClass() == v2
) {
2079 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2081 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2082 nir_print_instr(&instr
->instr
, stderr
);
2083 fprintf(stderr
, "\n");
2087 case nir_op_ffloor
: {
2088 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2089 if (dst
.regClass() == v2b
) {
2090 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2091 } else if (dst
.regClass() == v1
) {
2092 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2093 } else if (dst
.regClass() == v2
) {
2094 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2096 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2097 nir_print_instr(&instr
->instr
, stderr
);
2098 fprintf(stderr
, "\n");
2102 case nir_op_fceil
: {
2103 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2104 if (dst
.regClass() == v2b
) {
2105 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2106 } else if (dst
.regClass() == v1
) {
2107 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2108 } else if (dst
.regClass() == v2
) {
2109 if (ctx
->options
->chip_class
>= GFX7
) {
2110 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2112 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2113 /* trunc = trunc(src0)
2114 * if (src0 > 0.0 && src0 != trunc)
2117 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2118 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2119 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2120 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2121 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2122 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2123 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2126 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2127 nir_print_instr(&instr
->instr
, stderr
);
2128 fprintf(stderr
, "\n");
2132 case nir_op_ftrunc
: {
2133 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2134 if (dst
.regClass() == v2b
) {
2135 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2136 } else if (dst
.regClass() == v1
) {
2137 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2138 } else if (dst
.regClass() == v2
) {
2139 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2141 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2142 nir_print_instr(&instr
->instr
, stderr
);
2143 fprintf(stderr
, "\n");
2147 case nir_op_fround_even
: {
2148 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2149 if (dst
.regClass() == v2b
) {
2150 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2151 } else if (dst
.regClass() == v1
) {
2152 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2153 } else if (dst
.regClass() == v2
) {
2154 if (ctx
->options
->chip_class
>= GFX7
) {
2155 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2157 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2158 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2159 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2161 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2162 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2163 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2164 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2165 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2166 tmp
= sub
->definitions
[0].getTemp();
2168 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2169 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2170 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2171 Temp cond
= vop3
->definitions
[0].getTemp();
2173 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2174 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2175 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2176 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2178 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2181 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2182 nir_print_instr(&instr
->instr
, stderr
);
2183 fprintf(stderr
, "\n");
2189 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2190 aco_ptr
<Instruction
> norm
;
2191 if (dst
.regClass() == v2b
) {
2192 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2193 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2194 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2195 bld
.vop1(opcode
, Definition(dst
), tmp
);
2196 } else if (dst
.regClass() == v1
) {
2197 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2198 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2200 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2201 if (ctx
->options
->chip_class
< GFX9
)
2202 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2204 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2205 bld
.vop1(opcode
, Definition(dst
), tmp
);
2207 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2208 nir_print_instr(&instr
->instr
, stderr
);
2209 fprintf(stderr
, "\n");
2213 case nir_op_ldexp
: {
2214 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2215 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2216 if (dst
.regClass() == v2b
) {
2217 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2218 } else if (dst
.regClass() == v1
) {
2219 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2220 } else if (dst
.regClass() == v2
) {
2221 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2223 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2224 nir_print_instr(&instr
->instr
, stderr
);
2225 fprintf(stderr
, "\n");
2229 case nir_op_frexp_sig
: {
2230 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2231 if (dst
.regClass() == v2b
) {
2232 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2233 } else if (dst
.regClass() == v1
) {
2234 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2235 } else if (dst
.regClass() == v2
) {
2236 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2238 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2239 nir_print_instr(&instr
->instr
, stderr
);
2240 fprintf(stderr
, "\n");
2244 case nir_op_frexp_exp
: {
2245 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2246 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2247 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2248 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2249 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2250 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2251 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2252 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2253 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2255 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2256 nir_print_instr(&instr
->instr
, stderr
);
2257 fprintf(stderr
, "\n");
2261 case nir_op_fsign
: {
2262 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2263 if (dst
.regClass() == v2b
) {
2264 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2265 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2266 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2267 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2268 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2269 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2270 } else if (dst
.regClass() == v1
) {
2271 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2272 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2273 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2274 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2275 } else if (dst
.regClass() == v2
) {
2276 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2277 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2278 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2280 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2281 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2282 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2284 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2286 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2287 nir_print_instr(&instr
->instr
, stderr
);
2288 fprintf(stderr
, "\n");
2293 case nir_op_f2f16_rtne
: {
2294 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2295 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2296 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2297 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2300 case nir_op_f2f16_rtz
: {
2301 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2302 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2303 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2304 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2307 case nir_op_f2f32
: {
2308 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2309 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2310 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2311 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2314 nir_print_instr(&instr
->instr
, stderr
);
2315 fprintf(stderr
, "\n");
2319 case nir_op_f2f64
: {
2320 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2321 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2322 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2323 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2326 case nir_op_i2f16
: {
2327 assert(dst
.regClass() == v2b
);
2328 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2329 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2330 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2331 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2332 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2333 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2336 case nir_op_i2f32
: {
2337 assert(dst
.size() == 1);
2338 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2339 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2340 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2341 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2344 case nir_op_i2f64
: {
2345 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2347 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2348 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2349 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2350 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2351 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2352 RegClass rc
= RegClass(src
.type(), 1);
2353 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2354 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2355 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2356 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2357 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2358 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2361 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2362 nir_print_instr(&instr
->instr
, stderr
);
2363 fprintf(stderr
, "\n");
2367 case nir_op_u2f16
: {
2368 assert(dst
.regClass() == v2b
);
2369 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2370 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2371 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2372 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2373 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2374 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2377 case nir_op_u2f32
: {
2378 assert(dst
.size() == 1);
2379 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2380 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2381 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2383 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2384 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2385 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2389 case nir_op_u2f64
: {
2390 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2391 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2392 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2393 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2394 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2395 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2396 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2397 RegClass rc
= RegClass(src
.type(), 1);
2398 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2399 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2400 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2401 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2402 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2403 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2405 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2406 nir_print_instr(&instr
->instr
, stderr
);
2407 fprintf(stderr
, "\n");
2412 case nir_op_f2i16
: {
2413 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2414 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2415 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2416 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2418 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2422 case nir_op_f2u16
: {
2423 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2424 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2425 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2426 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2428 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2431 case nir_op_f2i32
: {
2432 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2433 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2434 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2435 if (dst
.type() == RegType::vgpr
) {
2436 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2438 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2439 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2441 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2442 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2443 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2444 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2446 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2447 nir_print_instr(&instr
->instr
, stderr
);
2448 fprintf(stderr
, "\n");
2452 case nir_op_f2u32
: {
2453 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2454 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2455 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2456 if (dst
.type() == RegType::vgpr
) {
2457 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2459 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2460 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2462 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2463 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2464 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2465 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2467 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2468 nir_print_instr(&instr
->instr
, stderr
);
2469 fprintf(stderr
, "\n");
2473 case nir_op_f2i64
: {
2474 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2475 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2476 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2478 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2479 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2480 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2481 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2482 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2483 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2484 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2485 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2486 Temp new_exponent
= bld
.tmp(v1
);
2487 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2488 if (ctx
->program
->chip_class
>= GFX8
)
2489 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2491 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2492 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2493 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2494 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2495 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2496 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2497 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2498 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2499 Temp new_lower
= bld
.tmp(v1
);
2500 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2501 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2502 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2504 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2505 if (src
.type() == RegType::vgpr
)
2506 src
= bld
.as_uniform(src
);
2507 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2508 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2509 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2510 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2511 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2512 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2513 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2514 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2515 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2516 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2517 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2518 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2519 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2520 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2521 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2522 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2523 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2524 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2525 Temp borrow
= bld
.tmp(s1
);
2526 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2527 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2528 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2530 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2531 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2532 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2533 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2534 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2535 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2536 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2537 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2538 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2539 if (dst
.type() == RegType::sgpr
) {
2540 lower
= bld
.as_uniform(lower
);
2541 upper
= bld
.as_uniform(upper
);
2543 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2547 nir_print_instr(&instr
->instr
, stderr
);
2548 fprintf(stderr
, "\n");
2552 case nir_op_f2u64
: {
2553 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2554 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2555 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2557 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2558 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2559 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2560 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2561 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2562 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2563 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2564 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2565 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2566 Temp new_exponent
= bld
.tmp(v1
);
2567 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2568 if (ctx
->program
->chip_class
>= GFX8
)
2569 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2571 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2572 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2573 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2574 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2575 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2576 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2577 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2578 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2580 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2581 if (src
.type() == RegType::vgpr
)
2582 src
= bld
.as_uniform(src
);
2583 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2584 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2585 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2586 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2587 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2588 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2589 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2590 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2591 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2592 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2593 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2594 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2595 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2596 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2597 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2598 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2599 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2602 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2603 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2604 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2605 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2606 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2607 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2608 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2609 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2610 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2611 if (dst
.type() == RegType::sgpr
) {
2612 lower
= bld
.as_uniform(lower
);
2613 upper
= bld
.as_uniform(upper
);
2615 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2618 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2619 nir_print_instr(&instr
->instr
, stderr
);
2620 fprintf(stderr
, "\n");
2624 case nir_op_b2f16
: {
2625 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2626 assert(src
.regClass() == bld
.lm
);
2628 if (dst
.regClass() == s1
) {
2629 src
= bool_to_scalar_condition(ctx
, src
);
2630 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2631 } else if (dst
.regClass() == v2b
) {
2632 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2633 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2635 unreachable("Wrong destination register class for nir_op_b2f16.");
2639 case nir_op_b2f32
: {
2640 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2641 assert(src
.regClass() == bld
.lm
);
2643 if (dst
.regClass() == s1
) {
2644 src
= bool_to_scalar_condition(ctx
, src
);
2645 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2646 } else if (dst
.regClass() == v1
) {
2647 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2649 unreachable("Wrong destination register class for nir_op_b2f32.");
2653 case nir_op_b2f64
: {
2654 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2655 assert(src
.regClass() == bld
.lm
);
2657 if (dst
.regClass() == s2
) {
2658 src
= bool_to_scalar_condition(ctx
, src
);
2659 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2660 } else if (dst
.regClass() == v2
) {
2661 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2662 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2663 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2665 unreachable("Wrong destination register class for nir_op_b2f64.");
2672 case nir_op_i2i64
: {
2673 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2674 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2680 case nir_op_u2u64
: {
2681 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2682 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2686 case nir_op_b2i32
: {
2687 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2688 assert(src
.regClass() == bld
.lm
);
2690 if (dst
.regClass() == s1
) {
2691 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2692 bool_to_scalar_condition(ctx
, src
, dst
);
2693 } else if (dst
.regClass() == v1
) {
2694 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2696 unreachable("Invalid register class for b2i32");
2702 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2703 assert(dst
.regClass() == bld
.lm
);
2705 if (src
.type() == RegType::vgpr
) {
2706 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2707 assert(dst
.regClass() == bld
.lm
);
2708 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2709 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2711 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2713 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2714 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2716 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2717 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2719 bool_to_vector_condition(ctx
, tmp
, dst
);
2723 case nir_op_pack_64_2x32_split
: {
2724 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2725 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2727 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2730 case nir_op_unpack_64_2x32_split_x
:
2731 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2733 case nir_op_unpack_64_2x32_split_y
:
2734 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2736 case nir_op_unpack_32_2x16_split_x
:
2737 if (dst
.type() == RegType::vgpr
) {
2738 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2740 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2743 case nir_op_unpack_32_2x16_split_y
:
2744 if (dst
.type() == RegType::vgpr
) {
2745 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2747 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2750 case nir_op_pack_32_2x16_split
: {
2751 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2752 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2753 if (dst
.regClass() == v1
) {
2754 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2755 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2756 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2758 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2759 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2760 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2764 case nir_op_pack_half_2x16
: {
2765 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2767 if (dst
.regClass() == v1
) {
2768 Temp src0
= bld
.tmp(v1
);
2769 Temp src1
= bld
.tmp(v1
);
2770 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2771 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2772 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2774 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2775 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2776 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2778 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2779 nir_print_instr(&instr
->instr
, stderr
);
2780 fprintf(stderr
, "\n");
2784 case nir_op_unpack_half_2x16_split_x
: {
2785 if (dst
.regClass() == v1
) {
2786 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2788 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2789 nir_print_instr(&instr
->instr
, stderr
);
2790 fprintf(stderr
, "\n");
2794 case nir_op_unpack_half_2x16_split_y
: {
2795 if (dst
.regClass() == v1
) {
2796 /* TODO: use SDWA here */
2797 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2798 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2801 nir_print_instr(&instr
->instr
, stderr
);
2802 fprintf(stderr
, "\n");
2806 case nir_op_fquantize2f16
: {
2807 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2808 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2811 if (ctx
->program
->chip_class
>= GFX8
) {
2812 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2813 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2814 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2816 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2817 * so compare the result and flush to 0 if it's smaller.
2819 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2820 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2821 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2822 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2823 cmp_res
= vop3
->definitions
[0].getTemp();
2826 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2827 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2828 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2830 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2835 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2836 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2838 if (dst
.regClass() == s1
) {
2839 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2840 } else if (dst
.regClass() == v1
) {
2841 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2843 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2844 nir_print_instr(&instr
->instr
, stderr
);
2845 fprintf(stderr
, "\n");
2849 case nir_op_bitfield_select
: {
2850 /* (mask & insert) | (~mask & base) */
2851 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2852 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2853 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2855 /* dst = (insert & bitmask) | (base & ~bitmask) */
2856 if (dst
.regClass() == s1
) {
2857 aco_ptr
<Instruction
> sop2
;
2858 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2859 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2861 if (const_insert
&& const_bitmask
) {
2862 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2864 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2865 lhs
= Operand(insert
);
2869 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2870 if (const_base
&& const_bitmask
) {
2871 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2873 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2874 rhs
= Operand(base
);
2877 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2879 } else if (dst
.regClass() == v1
) {
2880 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2881 base
= as_vgpr(ctx
, base
);
2882 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2883 insert
= as_vgpr(ctx
, insert
);
2885 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2889 nir_print_instr(&instr
->instr
, stderr
);
2890 fprintf(stderr
, "\n");
2896 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2897 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2898 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2900 if (dst
.type() == RegType::sgpr
) {
2902 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2903 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2904 if (const_offset
&& const_bits
) {
2905 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2906 extract
= Operand(const_extract
);
2910 width
= Operand(const_bits
->u32
<< 16);
2912 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2914 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2918 if (dst
.regClass() == s1
) {
2919 if (instr
->op
== nir_op_ubfe
)
2920 opcode
= aco_opcode::s_bfe_u32
;
2922 opcode
= aco_opcode::s_bfe_i32
;
2923 } else if (dst
.regClass() == s2
) {
2924 if (instr
->op
== nir_op_ubfe
)
2925 opcode
= aco_opcode::s_bfe_u64
;
2927 opcode
= aco_opcode::s_bfe_i64
;
2929 unreachable("Unsupported BFE bit size");
2932 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2936 if (dst
.regClass() == v1
) {
2937 if (instr
->op
== nir_op_ubfe
)
2938 opcode
= aco_opcode::v_bfe_u32
;
2940 opcode
= aco_opcode::v_bfe_i32
;
2942 unreachable("Unsupported BFE bit size");
2945 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2949 case nir_op_bit_count
: {
2950 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2951 if (src
.regClass() == s1
) {
2952 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2953 } else if (src
.regClass() == v1
) {
2954 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2955 } else if (src
.regClass() == v2
) {
2956 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2957 emit_extract_vector(ctx
, src
, 1, v1
),
2958 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2959 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2960 } else if (src
.regClass() == s2
) {
2961 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2963 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2964 nir_print_instr(&instr
->instr
, stderr
);
2965 fprintf(stderr
, "\n");
2970 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2974 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2978 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2982 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2986 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2990 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2994 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2995 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2997 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2998 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3002 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3003 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3005 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3006 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3010 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3014 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3019 case nir_op_fddx_fine
:
3020 case nir_op_fddy_fine
:
3021 case nir_op_fddx_coarse
:
3022 case nir_op_fddy_coarse
: {
3023 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3024 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3025 if (instr
->op
== nir_op_fddx_fine
) {
3026 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3027 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3028 } else if (instr
->op
== nir_op_fddy_fine
) {
3029 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3030 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3032 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3033 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3034 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3036 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3040 if (ctx
->program
->chip_class
>= GFX8
) {
3041 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3042 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3044 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3045 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3046 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3048 emit_wqm(ctx
, tmp
, dst
, true);
3052 fprintf(stderr
, "Unknown NIR ALU instr: ");
3053 nir_print_instr(&instr
->instr
, stderr
);
3054 fprintf(stderr
, "\n");
3058 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3060 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3062 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3063 // which get truncated the lsb if double and msb if int
3064 // for now, we only use s_mov_b64 with 64bit inline constants
3065 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3066 assert(dst
.type() == RegType::sgpr
);
3068 Builder
bld(ctx
->program
, ctx
->block
);
3070 if (instr
->def
.bit_size
== 1) {
3071 assert(dst
.regClass() == bld
.lm
);
3072 int val
= instr
->value
[0].b
? -1 : 0;
3073 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3074 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3075 } else if (instr
->def
.bit_size
== 8) {
3076 /* ensure that the value is correctly represented in the low byte of the register */
3077 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3078 } else if (instr
->def
.bit_size
== 16) {
3079 /* ensure that the value is correctly represented in the low half of the register */
3080 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3081 } else if (dst
.size() == 1) {
3082 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3084 assert(dst
.size() != 1);
3085 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3086 if (instr
->def
.bit_size
== 64)
3087 for (unsigned i
= 0; i
< dst
.size(); i
++)
3088 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3090 for (unsigned i
= 0; i
< dst
.size(); i
++)
3091 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3093 vec
->definitions
[0] = Definition(dst
);
3094 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3098 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3100 uint32_t new_mask
= 0;
3101 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3102 if (mask
& (1u << i
))
3103 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3107 struct LoadEmitInfo
{
3110 unsigned num_components
;
3111 unsigned component_size
;
3112 Temp resource
= Temp(0, s1
);
3113 unsigned component_stride
= 0;
3114 unsigned const_offset
= 0;
3115 unsigned align_mul
= 0;
3116 unsigned align_offset
= 0;
3119 unsigned swizzle_component_size
= 0;
3120 barrier_interaction barrier
= barrier_none
;
3121 bool can_reorder
= true;
3122 Temp soffset
= Temp(0, s1
);
3125 using LoadCallback
= Temp(*)(
3126 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3127 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3129 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3130 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3132 unsigned load_size
= info
->num_components
* info
->component_size
;
3133 unsigned component_size
= info
->component_size
;
3135 unsigned num_vals
= 0;
3136 Temp vals
[info
->dst
.bytes()];
3138 unsigned const_offset
= info
->const_offset
;
3140 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3141 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3143 unsigned bytes_read
= 0;
3144 while (bytes_read
< load_size
) {
3145 unsigned bytes_needed
= load_size
- bytes_read
;
3147 /* add buffer for unaligned loads */
3148 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3151 if ((bytes_needed
> 2 ||
3152 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3153 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3154 if (info
->component_stride
) {
3155 assert(supports_8bit_16bit_loads
&& "unimplemented");
3159 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3160 bytes_needed
= align(bytes_needed
, 4);
3167 if (info
->swizzle_component_size
)
3168 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3169 if (info
->component_stride
)
3170 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3172 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3174 /* reduce constant offset */
3175 Operand offset
= info
->offset
;
3176 unsigned reduced_const_offset
= const_offset
;
3177 bool remove_const_offset_completely
= need_to_align_offset
;
3178 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3179 unsigned to_add
= const_offset
;
3180 if (remove_const_offset_completely
) {
3181 reduced_const_offset
= 0;
3183 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3184 reduced_const_offset
%= max_const_offset_plus_one
;
3186 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3187 if (offset
.isConstant()) {
3188 offset
= Operand(offset
.constantValue() + to_add
);
3189 } else if (offset_tmp
.regClass() == s1
) {
3190 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3191 offset_tmp
, Operand(to_add
));
3192 } else if (offset_tmp
.regClass() == v1
) {
3193 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3195 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3196 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3197 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3199 if (offset_tmp
.regClass() == s2
) {
3200 Temp carry
= bld
.tmp(s1
);
3201 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3202 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3203 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3205 Temp new_lo
= bld
.tmp(v1
);
3206 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3207 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3208 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3213 /* align offset down if needed */
3214 Operand aligned_offset
= offset
;
3215 if (need_to_align_offset
) {
3216 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3217 if (offset
.isConstant()) {
3218 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3219 } else if (offset_tmp
.regClass() == s1
) {
3220 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3221 } else if (offset_tmp
.regClass() == s2
) {
3222 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3223 } else if (offset_tmp
.regClass() == v1
) {
3224 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3225 } else if (offset_tmp
.regClass() == v2
) {
3226 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3227 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3228 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3229 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3232 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3233 bld
.copy(bld
.def(s1
), aligned_offset
);
3235 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3236 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3237 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3239 /* the callback wrote directly to dst */
3240 if (val
== info
->dst
) {
3241 assert(num_vals
== 0);
3242 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3246 /* shift result right if needed */
3247 if (info
->component_size
< 4 && byte_align_loads
) {
3248 Operand
align((uint32_t)byte_align
);
3249 if (byte_align
== -1) {
3250 if (offset
.isConstant())
3251 align
= Operand(offset
.constantValue() % 4u);
3252 else if (offset
.size() == 2)
3253 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3258 assert(val
.bytes() >= load_size
&& "unimplemented");
3259 if (val
.type() == RegType::sgpr
)
3260 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3262 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3266 /* add result to list and advance */
3267 if (info
->component_stride
) {
3268 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3269 const_offset
+= info
->component_stride
;
3270 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3272 const_offset
+= val
.bytes();
3273 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3275 bytes_read
+= val
.bytes();
3276 vals
[num_vals
++] = val
;
3279 /* create array of components */
3280 unsigned components_split
= 0;
3281 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3282 bool has_vgprs
= false;
3283 for (unsigned i
= 0; i
< num_vals
;) {
3285 unsigned num_tmps
= 0;
3286 unsigned tmp_size
= 0;
3287 RegType reg_type
= RegType::sgpr
;
3288 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3289 if (vals
[i
].type() == RegType::vgpr
)
3290 reg_type
= RegType::vgpr
;
3291 tmp_size
+= vals
[i
].bytes();
3292 tmp
[num_tmps
++] = vals
[i
++];
3295 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3296 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3297 for (unsigned i
= 0; i
< num_vals
; i
++)
3298 vec
->operands
[i
] = Operand(tmp
[i
]);
3299 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3300 vec
->definitions
[0] = Definition(tmp
[0]);
3301 bld
.insert(std::move(vec
));
3304 if (tmp
[0].bytes() % component_size
) {
3306 assert(i
== num_vals
);
3307 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3308 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3311 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3313 unsigned start
= components_split
;
3315 if (tmp_size
== elem_rc
.bytes()) {
3316 allocated_vec
[components_split
++] = tmp
[0];
3318 assert(tmp_size
% elem_rc
.bytes() == 0);
3319 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3320 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3321 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3322 Temp component
= bld
.tmp(elem_rc
);
3323 allocated_vec
[components_split
++] = component
;
3324 split
->definitions
[i
] = Definition(component
);
3326 split
->operands
[0] = Operand(tmp
[0]);
3327 bld
.insert(std::move(split
));
3330 /* try to p_as_uniform early so we can create more optimizable code and
3331 * also update allocated_vec */
3332 for (unsigned j
= start
; j
< components_split
; j
++) {
3333 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3334 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3335 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3339 /* concatenate components and p_as_uniform() result if needed */
3340 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3341 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3343 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3345 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3346 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3347 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3348 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3350 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3351 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3352 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3353 vec
->definitions
[0] = Definition(tmp
);
3354 bld
.insert(std::move(vec
));
3355 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3357 vec
->definitions
[0] = Definition(info
->dst
);
3358 bld
.insert(std::move(vec
));
3362 Operand
load_lds_size_m0(Builder
& bld
)
3364 /* TODO: m0 does not need to be initialized on GFX9+ */
3365 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3368 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3369 Temp offset
, unsigned bytes_needed
,
3370 unsigned align
, unsigned const_offset
,
3373 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3375 Operand m
= load_lds_size_m0(bld
);
3377 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3378 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3383 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3384 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3386 op
= aco_opcode::ds_read_b128
;
3387 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3390 op
= aco_opcode::ds_read2_b64
;
3391 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3393 op
= aco_opcode::ds_read_b96
;
3394 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3396 op
= aco_opcode::ds_read_b64
;
3397 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3400 op
= aco_opcode::ds_read2_b32
;
3401 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3403 op
= aco_opcode::ds_read_b32
;
3404 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3406 op
= aco_opcode::ds_read_u16
;
3409 op
= aco_opcode::ds_read_u8
;
3412 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3413 if (const_offset
>= max_offset_plus_one
) {
3414 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3415 const_offset
%= max_offset_plus_one
;
3419 const_offset
/= (size
/ 2u);
3421 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3422 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3424 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3426 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3429 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3434 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3436 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3437 Temp offset
, unsigned bytes_needed
,
3438 unsigned align
, unsigned const_offset
,
3443 if (bytes_needed
<= 4) {
3445 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3446 } else if (bytes_needed
<= 8) {
3448 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3449 } else if (bytes_needed
<= 16) {
3451 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3452 } else if (bytes_needed
<= 32) {
3454 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3457 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3459 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3460 if (info
->resource
.id()) {
3461 load
->operands
[0] = Operand(info
->resource
);
3462 load
->operands
[1] = Operand(offset
);
3464 load
->operands
[0] = Operand(offset
);
3465 load
->operands
[1] = Operand(0u);
3467 RegClass
rc(RegType::sgpr
, size
);
3468 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3469 load
->definitions
[0] = Definition(val
);
3470 load
->glc
= info
->glc
;
3471 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3472 load
->barrier
= info
->barrier
;
3473 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3474 bld
.insert(std::move(load
));
3478 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3480 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3481 Temp offset
, unsigned bytes_needed
,
3482 unsigned align_
, unsigned const_offset
,
3485 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3486 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3488 if (info
->soffset
.id()) {
3489 if (soffset
.isTemp())
3490 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3491 soffset
= Operand(info
->soffset
);
3494 unsigned bytes_size
= 0;
3496 if (bytes_needed
== 1) {
3498 op
= aco_opcode::buffer_load_ubyte
;
3499 } else if (bytes_needed
== 2) {
3501 op
= aco_opcode::buffer_load_ushort
;
3502 } else if (bytes_needed
<= 4) {
3504 op
= aco_opcode::buffer_load_dword
;
3505 } else if (bytes_needed
<= 8) {
3507 op
= aco_opcode::buffer_load_dwordx2
;
3508 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3510 op
= aco_opcode::buffer_load_dwordx3
;
3513 op
= aco_opcode::buffer_load_dwordx4
;
3515 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3516 mubuf
->operands
[0] = Operand(info
->resource
);
3517 mubuf
->operands
[1] = vaddr
;
3518 mubuf
->operands
[2] = soffset
;
3519 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3520 mubuf
->glc
= info
->glc
;
3521 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3522 mubuf
->barrier
= info
->barrier
;
3523 mubuf
->can_reorder
= info
->can_reorder
;
3524 mubuf
->offset
= const_offset
;
3525 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3526 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3527 mubuf
->definitions
[0] = Definition(val
);
3528 bld
.insert(std::move(mubuf
));
3533 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3535 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3537 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3538 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3540 if (addr
.type() == RegType::vgpr
)
3541 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3542 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3545 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3546 Temp offset
, unsigned bytes_needed
,
3547 unsigned align_
, unsigned const_offset
,
3550 unsigned bytes_size
= 0;
3551 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3552 bool global
= bld
.program
->chip_class
>= GFX9
;
3554 if (bytes_needed
== 1) {
3556 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3557 } else if (bytes_needed
== 2) {
3559 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3560 } else if (bytes_needed
<= 4) {
3562 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3563 } else if (bytes_needed
<= 8) {
3565 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3566 } else if (bytes_needed
<= 12 && !mubuf
) {
3568 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3571 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3573 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3574 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3576 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3577 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3578 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3579 mubuf
->operands
[2] = Operand(0u);
3580 mubuf
->glc
= info
->glc
;
3583 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3584 mubuf
->disable_wqm
= false;
3585 mubuf
->barrier
= info
->barrier
;
3586 mubuf
->definitions
[0] = Definition(val
);
3587 bld
.insert(std::move(mubuf
));
3589 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3591 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3592 flat
->operands
[0] = Operand(offset
);
3593 flat
->operands
[1] = Operand(s1
);
3594 flat
->glc
= info
->glc
;
3595 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3596 flat
->barrier
= info
->barrier
;
3598 flat
->definitions
[0] = Definition(val
);
3599 bld
.insert(std::move(flat
));
3605 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3607 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3608 Temp address
, unsigned base_offset
, unsigned align
)
3610 assert(util_is_power_of_two_nonzero(align
));
3612 Builder
bld(ctx
->program
, ctx
->block
);
3614 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3615 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3616 info
.align_mul
= align
;
3617 info
.align_offset
= 0;
3618 info
.barrier
= barrier_shared
;
3619 info
.can_reorder
= false;
3620 info
.const_offset
= base_offset
;
3621 emit_lds_load(ctx
, bld
, &info
);
3626 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3631 Builder
bld(ctx
->program
, ctx
->block
);
3633 ASSERTED
bool is_subdword
= false;
3634 for (unsigned i
= 0; i
< count
; i
++)
3635 is_subdword
|= offsets
[i
] % 4;
3636 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3637 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3639 /* count == 1 fast path */
3641 if (dst_type
== RegType::sgpr
)
3642 dst
[0] = bld
.as_uniform(src
);
3644 dst
[0] = as_vgpr(ctx
, src
);
3648 for (unsigned i
= 0; i
< count
- 1; i
++)
3649 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3650 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3652 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3653 src
= as_vgpr(ctx
, src
);
3655 /* use allocated_vec if possible */
3656 auto it
= ctx
->allocated_vec
.find(src
.id());
3657 if (it
!= ctx
->allocated_vec
.end()) {
3658 unsigned total_size
= 0;
3659 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3660 total_size
+= it
->second
[i
].bytes();
3661 if (total_size
!= src
.bytes())
3664 unsigned elem_size
= it
->second
[0].bytes();
3666 for (unsigned i
= 0; i
< count
; i
++) {
3667 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3671 for (unsigned i
= 0; i
< count
; i
++) {
3672 unsigned start_idx
= offsets
[i
] / elem_size
;
3673 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3674 if (op_count
== 1) {
3675 if (dst_type
== RegType::sgpr
)
3676 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3678 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3682 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3683 for (unsigned j
= 0; j
< op_count
; j
++) {
3684 Temp tmp
= it
->second
[start_idx
+ j
];
3685 if (dst_type
== RegType::sgpr
)
3686 tmp
= bld
.as_uniform(tmp
);
3687 vec
->operands
[j
] = Operand(tmp
);
3689 vec
->definitions
[0] = Definition(dst
[i
]);
3690 bld
.insert(std::move(vec
));
3696 if (dst_type
== RegType::sgpr
)
3697 src
= bld
.as_uniform(src
);
3701 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3702 split
->operands
[0] = Operand(src
);
3703 for (unsigned i
= 0; i
< count
; i
++)
3704 split
->definitions
[i
] = Definition(dst
[i
]);
3705 bld
.insert(std::move(split
));
3708 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3709 int *start
, int *count
)
3711 unsigned start_elem
= ffs(todo_mask
) - 1;
3712 bool skip
= !(mask
& (1 << start_elem
));
3714 mask
= ~mask
& todo_mask
;
3718 u_bit_scan_consecutive_range(&mask
, start
, count
);
3723 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3725 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3728 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3729 Temp address
, unsigned base_offset
, unsigned align
)
3731 assert(util_is_power_of_two_nonzero(align
));
3732 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3734 Builder
bld(ctx
->program
, ctx
->block
);
3735 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3736 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3738 unsigned write_count
= 0;
3739 Temp write_datas
[32];
3740 unsigned offsets
[32];
3741 aco_opcode opcodes
[32];
3743 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3745 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3748 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3749 offsets
[write_count
] = offset
;
3750 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3752 advance_write_mask(&todo
, offset
, bytes
);
3756 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3757 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3758 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3759 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3761 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3762 aco_opcode op
= aco_opcode::num_opcodes
;
3763 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3764 op
= aco_opcode::ds_write_b128
;
3766 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3767 op
= aco_opcode::ds_write_b96
;
3769 } else if (bytes
>= 8 && aligned8
) {
3770 op
= aco_opcode::ds_write_b64
;
3772 } else if (bytes
>= 4 && aligned4
) {
3773 op
= aco_opcode::ds_write_b32
;
3775 } else if (bytes
>= 2 && aligned2
) {
3776 op
= aco_opcode::ds_write_b16
;
3778 } else if (bytes
>= 1) {
3779 op
= aco_opcode::ds_write_b8
;
3785 offsets
[write_count
] = offset
;
3786 opcodes
[write_count
] = op
;
3788 advance_write_mask(&todo
, offset
, bytes
);
3791 Operand m
= load_lds_size_m0(bld
);
3793 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3795 for (unsigned i
= 0; i
< write_count
; i
++) {
3796 aco_opcode op
= opcodes
[i
];
3797 if (op
== aco_opcode::num_opcodes
)
3800 Temp data
= write_datas
[i
];
3802 unsigned second
= write_count
;
3803 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3804 for (second
= i
+ 1; second
< write_count
; second
++) {
3805 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3806 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3807 opcodes
[second
] = aco_opcode::num_opcodes
;
3813 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3814 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3816 unsigned inline_offset
= base_offset
+ offsets
[i
];
3817 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3818 Temp address_offset
= address
;
3819 if (inline_offset
> max_offset
) {
3820 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3821 inline_offset
= offsets
[i
];
3823 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3826 Temp second_data
= write_datas
[second
];
3827 inline_offset
/= data
.bytes();
3828 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3830 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3835 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3837 unsigned align
= 16;
3839 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3845 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3850 return aco_opcode::buffer_store_byte
;
3853 return aco_opcode::buffer_store_short
;
3855 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3857 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3860 return aco_opcode::buffer_store_dwordx3
;
3862 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3864 unreachable("Unexpected store size");
3865 return aco_opcode::num_opcodes
;
3868 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3869 Temp data
, unsigned writemask
, int swizzle_element_size
,
3870 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3872 unsigned write_count_with_skips
= 0;
3875 /* determine how to split the data */
3876 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3879 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3880 offsets
[write_count_with_skips
] = offset
;
3881 if (skips
[write_count_with_skips
]) {
3882 advance_write_mask(&todo
, offset
, bytes
);
3883 write_count_with_skips
++;
3887 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3888 * larger than swizzle_element_size */
3889 bytes
= MIN2(bytes
, swizzle_element_size
);
3891 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3893 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3894 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3897 /* dword or larger stores have to be dword-aligned */
3898 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3899 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3900 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3902 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3904 advance_write_mask(&todo
, offset
, bytes
);
3905 write_count_with_skips
++;
3908 /* actually split data */
3909 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3912 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3915 write_datas
[*write_count
] = write_datas
[i
];
3916 offsets
[*write_count
] = offsets
[i
];
3921 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3922 unsigned split_cnt
= 0u, Temp dst
= Temp())
3924 Builder
bld(ctx
->program
, ctx
->block
);
3925 unsigned dword_size
= elem_size_bytes
/ 4;
3928 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3930 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3931 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3932 instr
->definitions
[0] = Definition(dst
);
3934 for (unsigned i
= 0; i
< cnt
; ++i
) {
3936 assert(arr
[i
].size() == dword_size
);
3937 allocated_vec
[i
] = arr
[i
];
3938 instr
->operands
[i
] = Operand(arr
[i
]);
3940 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3941 allocated_vec
[i
] = zero
;
3942 instr
->operands
[i
] = Operand(zero
);
3946 bld
.insert(std::move(instr
));
3949 emit_split_vector(ctx
, dst
, split_cnt
);
3951 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3956 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3958 if (const_offset
>= 4096) {
3959 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3960 const_offset
%= 4096u;
3963 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3964 else if (unlikely(voffset
.regClass() == s1
))
3965 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3966 else if (likely(voffset
.regClass() == v1
))
3967 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3969 unreachable("Unsupported register class of voffset");
3972 return const_offset
;
3975 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3976 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3979 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3980 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3982 Builder
bld(ctx
->program
, ctx
->block
);
3983 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3984 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3986 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3987 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3988 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3989 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3990 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3992 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3995 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3996 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3997 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3999 Builder
bld(ctx
->program
, ctx
->block
);
4000 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4002 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
4004 unsigned write_count
= 0;
4005 Temp write_datas
[32];
4006 unsigned offsets
[32];
4007 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
4008 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4010 for (unsigned i
= 0; i
< write_count
; i
++) {
4011 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4012 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
4016 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4017 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4018 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4020 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4021 assert((num_components
* elem_size_bytes
) == dst
.bytes());
4022 assert(!!stride
!= allow_combining
);
4024 Builder
bld(ctx
->program
, ctx
->block
);
4026 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4027 info
.component_stride
= allow_combining
? 0 : stride
;
4029 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4030 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4031 info
.align_offset
= 0;
4032 info
.soffset
= soffset
;
4033 info
.const_offset
= base_const_offset
;
4034 emit_mubuf_load(ctx
, bld
, &info
);
4037 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4039 Builder
bld(ctx
->program
, ctx
->block
);
4040 Temp offset
= base_offset
.first
;
4041 unsigned const_offset
= base_offset
.second
;
4043 if (!nir_src_is_const(*off_src
)) {
4044 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4047 /* Calculate indirect offset with stride */
4048 if (likely(indirect_offset_arg
.regClass() == v1
))
4049 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4050 else if (indirect_offset_arg
.regClass() == s1
)
4051 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4053 unreachable("Unsupported register class of indirect offset");
4055 /* Add to the supplied base offset */
4056 if (offset
.id() == 0)
4057 offset
= with_stride
;
4058 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4059 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4060 else if (offset
.size() == 1 && with_stride
.size() == 1)
4061 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4063 unreachable("Unsupported register class of indirect offset");
4065 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4066 const_offset
+= const_offset_arg
* stride
;
4069 return std::make_pair(offset
, const_offset
);
4072 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4074 Builder
bld(ctx
->program
, ctx
->block
);
4077 if (off1
.first
.id() && off2
.first
.id()) {
4078 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4079 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4080 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4081 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4083 unreachable("Unsupported register class of indirect offset");
4085 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4088 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4091 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4093 Builder
bld(ctx
->program
, ctx
->block
);
4094 unsigned const_offset
= offs
.second
* multiplier
;
4096 if (!offs
.first
.id())
4097 return std::make_pair(offs
.first
, const_offset
);
4099 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4100 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4101 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4103 return std::make_pair(offset
, const_offset
);
4106 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4108 Builder
bld(ctx
->program
, ctx
->block
);
4110 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4111 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4112 /* component is in bytes */
4113 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4115 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4116 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4117 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4120 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4122 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4125 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4127 Builder
bld(ctx
->program
, ctx
->block
);
4129 switch (ctx
->shader
->info
.stage
) {
4130 case MESA_SHADER_TESS_CTRL
:
4131 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4132 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4133 case MESA_SHADER_TESS_EVAL
:
4134 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4136 unreachable("Unsupported stage in get_tess_rel_patch_id");
4140 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4142 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4143 Builder
bld(ctx
->program
, ctx
->block
);
4145 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4146 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4148 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4150 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4151 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4153 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4154 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4155 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4157 return offset_mul(ctx
, offs
, 4u);
4160 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4162 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4163 Builder
bld(ctx
->program
, ctx
->block
);
4165 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4166 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4167 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4168 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4170 std::pair
<Temp
, unsigned> offs
= instr
4171 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4172 : std::make_pair(Temp(), 0u);
4174 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4175 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4180 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4181 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4183 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4184 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4186 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4187 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4193 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4195 Builder
bld(ctx
->program
, ctx
->block
);
4197 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4198 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4200 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4202 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4203 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4204 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4206 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4207 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4212 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4214 Builder
bld(ctx
->program
, ctx
->block
);
4216 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4217 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4218 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4219 unsigned attr_stride
= ctx
->tcs_num_patches
;
4221 std::pair
<Temp
, unsigned> offs
= instr
4222 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4223 : std::make_pair(Temp(), 0u);
4225 if (const_base_offset
)
4226 offs
.second
+= const_base_offset
* attr_stride
;
4228 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4229 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4230 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4235 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4237 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4242 unsigned drv_loc
= nir_intrinsic_base(instr
);
4243 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4245 if (!nir_src_is_const(*off_src
)) {
4251 uint64_t slot
= per_vertex
4252 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4253 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4254 return (((uint64_t) 1) << slot
) & mask
;
4257 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4259 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4260 unsigned component
= nir_intrinsic_component(instr
);
4261 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4263 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4264 if (off_instr
->type
!= nir_instr_type_load_const
)
4267 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4268 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4270 if (instr
->src
[0].ssa
->bit_size
== 64)
4271 write_mask
= widen_mask(write_mask
, 2);
4273 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4275 for (unsigned i
= 0; i
< 8; ++i
) {
4276 if (write_mask
& (1 << i
)) {
4277 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4278 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4286 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4288 /* Only TCS per-vertex inputs are supported by this function.
4289 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4291 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4294 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4295 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4296 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4297 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4298 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4299 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4304 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4305 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4306 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4311 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4313 Builder
bld(ctx
->program
, ctx
->block
);
4315 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4316 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4317 bool indirect_write
;
4318 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4319 if (temp_only_input
&& !indirect_write
)
4323 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4324 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4325 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4326 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4328 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4329 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4330 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4331 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4332 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4336 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4337 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4338 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4339 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4340 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4341 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4342 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4343 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4344 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4345 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4346 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4347 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4348 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4350 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4351 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4353 unreachable("Invalid LS or ES stage");
4356 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4357 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4358 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4362 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4367 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4368 return off
== ctx
->tcs_tess_lvl_out_loc
||
4369 off
== ctx
->tcs_tess_lvl_in_loc
;
4373 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4375 uint64_t mask
= per_vertex
4376 ? ctx
->program
->info
->tcs
.tes_inputs_read
4377 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4379 bool indirect_write
= false;
4380 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4381 return indirect_write
|| output_read_by_tes
;
4384 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4386 uint64_t mask
= per_vertex
4387 ? ctx
->shader
->info
.outputs_read
4388 : ctx
->shader
->info
.patch_outputs_read
;
4390 bool indirect_write
= false;
4391 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4392 return indirect_write
|| output_read
;
4395 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4397 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4398 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4400 Builder
bld(ctx
->program
, ctx
->block
);
4402 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4403 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4404 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4406 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4407 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4408 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4410 if (write_to_vmem
) {
4411 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4412 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4413 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4415 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4416 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4417 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4421 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4422 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4423 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4427 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4429 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4430 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4432 Builder
bld(ctx
->program
, ctx
->block
);
4434 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4435 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4436 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4437 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4439 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4442 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4444 if (ctx
->stage
== vertex_vs
||
4445 ctx
->stage
== tess_eval_vs
||
4446 ctx
->stage
== fragment_fs
||
4447 ctx
->stage
== ngg_vertex_gs
||
4448 ctx
->stage
== ngg_tess_eval_gs
||
4449 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4450 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4451 if (!stored_to_temps
) {
4452 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4453 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4454 fprintf(stderr
, "\n");
4457 } else if (ctx
->stage
== vertex_es
||
4458 ctx
->stage
== vertex_ls
||
4459 ctx
->stage
== tess_eval_es
||
4460 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4461 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4462 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4463 visit_store_ls_or_es_output(ctx
, instr
);
4464 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4465 visit_store_tcs_output(ctx
, instr
, false);
4467 unreachable("Shader stage not implemented");
4471 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4473 visit_load_tcs_output(ctx
, instr
, false);
4476 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4478 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4479 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4481 Builder
bld(ctx
->program
, ctx
->block
);
4483 if (dst
.regClass() == v2b
) {
4484 if (ctx
->program
->has_16bank_lds
) {
4485 assert(ctx
->options
->chip_class
<= GFX8
);
4486 Builder::Result interp_p1
=
4487 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4488 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4489 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4490 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4491 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4492 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4494 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4496 if (ctx
->options
->chip_class
== GFX8
)
4497 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4499 Builder::Result interp_p1
=
4500 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4501 coord1
, bld
.m0(prim_mask
), idx
, component
);
4502 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4503 interp_p1
, idx
, component
);
4506 Builder::Result interp_p1
=
4507 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4508 bld
.m0(prim_mask
), idx
, component
);
4510 if (ctx
->program
->has_16bank_lds
)
4511 interp_p1
.instr
->operands
[0].setLateKill(true);
4513 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4514 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4518 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4520 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4521 for (unsigned i
= 0; i
< num_components
; i
++)
4522 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4523 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4524 assert(num_components
== 4);
4525 Builder
bld(ctx
->program
, ctx
->block
);
4526 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4529 for (Operand
& op
: vec
->operands
)
4530 op
= op
.isUndefined() ? Operand(0u) : op
;
4532 vec
->definitions
[0] = Definition(dst
);
4533 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4534 emit_split_vector(ctx
, dst
, num_components
);
4538 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4540 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4541 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4542 unsigned idx
= nir_intrinsic_base(instr
);
4543 unsigned component
= nir_intrinsic_component(instr
);
4544 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4546 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4548 assert(offset
->u32
== 0);
4550 /* the lower 15bit of the prim_mask contain the offset into LDS
4551 * while the upper bits contain the number of prims */
4552 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4553 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4554 Builder
bld(ctx
->program
, ctx
->block
);
4555 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4556 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4557 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4558 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4559 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4562 if (instr
->dest
.ssa
.num_components
== 1) {
4563 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4565 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4566 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4568 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4569 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4570 vec
->operands
[i
] = Operand(tmp
);
4572 vec
->definitions
[0] = Definition(dst
);
4573 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4577 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4578 unsigned offset
, unsigned stride
, unsigned channels
)
4580 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4581 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4583 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4584 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4587 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4588 unsigned offset
, unsigned stride
, unsigned *channels
)
4590 if (!vtx_info
->chan_byte_size
) {
4591 *channels
= vtx_info
->num_channels
;
4592 return vtx_info
->chan_format
;
4595 unsigned num_channels
= *channels
;
4596 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4597 unsigned new_channels
= num_channels
+ 1;
4598 /* first, assume more loads is worse and try using a larger data format */
4599 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4601 /* don't make the attribute potentially out-of-bounds */
4602 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4606 if (new_channels
== 5) {
4607 /* then try decreasing load size (at the cost of more loads) */
4608 new_channels
= *channels
;
4609 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4613 if (new_channels
< *channels
)
4614 *channels
= new_channels
;
4615 num_channels
= new_channels
;
4618 switch (vtx_info
->chan_format
) {
4619 case V_008F0C_BUF_DATA_FORMAT_8
:
4620 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4621 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4622 case V_008F0C_BUF_DATA_FORMAT_16
:
4623 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4624 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4625 case V_008F0C_BUF_DATA_FORMAT_32
:
4626 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4627 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4629 unreachable("shouldn't reach here");
4630 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4633 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4634 * so we may need to fix it up. */
4635 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4637 Builder
bld(ctx
->program
, ctx
->block
);
4639 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4640 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4642 /* For the integer-like cases, do a natural sign extension.
4644 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4645 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4648 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4649 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4651 /* Convert back to the right type. */
4652 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4653 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4654 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4655 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4656 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4657 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4663 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4665 Builder
bld(ctx
->program
, ctx
->block
);
4666 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4667 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4669 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4670 if (off_instr
->type
!= nir_instr_type_load_const
) {
4671 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4672 nir_print_instr(off_instr
, stderr
);
4673 fprintf(stderr
, "\n");
4675 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4677 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4679 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4680 unsigned component
= nir_intrinsic_component(instr
);
4681 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4682 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4683 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4684 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4685 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4687 unsigned dfmt
= attrib_format
& 0xf;
4688 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4689 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4691 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4692 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4693 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4694 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4696 num_channels
= MAX2(num_channels
, 3);
4698 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4699 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4702 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4703 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4704 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4706 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4708 Temp divided
= bld
.tmp(v1
);
4709 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4710 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4712 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4715 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4718 index
= bld
.vadd32(bld
.def(v1
),
4719 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4720 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4723 Temp channels
[num_channels
];
4724 unsigned channel_start
= 0;
4725 bool direct_fetch
= false;
4727 /* skip unused channels at the start */
4728 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4729 channel_start
= ffs(mask
) - 1;
4730 for (unsigned i
= 0; i
< channel_start
; i
++)
4731 channels
[i
] = Temp(0, s1
);
4732 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4733 num_channels
= 3 - (ffs(mask
) - 1);
4737 while (channel_start
< num_channels
) {
4738 unsigned fetch_component
= num_channels
- channel_start
;
4739 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4740 bool expanded
= false;
4742 /* use MUBUF when possible to avoid possible alignment issues */
4743 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4744 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4745 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4746 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4747 vtx_info
->chan_byte_size
== 4;
4748 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4750 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4752 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4753 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4754 fetch_component
= 4;
4759 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4761 Temp fetch_index
= index
;
4762 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4763 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4764 fetch_offset
= fetch_offset
% attrib_stride
;
4767 Operand
soffset(0u);
4768 if (fetch_offset
>= 4096) {
4769 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4770 fetch_offset
%= 4096;
4774 switch (fetch_bytes
) {
4776 assert(!use_mubuf
&& bitsize
== 16);
4777 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4780 if (bitsize
== 16) {
4782 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4784 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4788 assert(!use_mubuf
&& bitsize
== 16);
4789 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4792 if (bitsize
== 16) {
4794 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4796 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4800 assert(ctx
->options
->chip_class
>= GFX7
||
4801 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4802 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4805 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4808 unreachable("Unimplemented load_input vector size");
4812 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4813 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4814 num_channels
<= 3)) {
4815 direct_fetch
= true;
4818 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4822 Instruction
*mubuf
= bld
.mubuf(opcode
,
4823 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4824 fetch_offset
, false, true).instr
;
4825 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4827 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4828 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4829 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4830 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4833 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4835 if (fetch_component
== 1) {
4836 channels
[channel_start
] = fetch_dst
;
4838 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4839 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4840 bitsize
== 16 ? v2b
: v1
);
4843 channel_start
+= fetch_component
;
4846 if (!direct_fetch
) {
4847 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4848 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4850 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4851 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4852 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4854 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4855 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4856 unsigned num_temp
= 0;
4857 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4858 unsigned idx
= i
+ component
;
4859 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4860 Temp channel
= channels
[swizzle
[idx
]];
4861 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4862 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4863 vec
->operands
[i
] = Operand(channel
);
4867 } else if (is_float
&& idx
== 3) {
4868 vec
->operands
[i
] = Operand(0x3f800000u
);
4869 } else if (!is_float
&& idx
== 3) {
4870 vec
->operands
[i
] = Operand(1u);
4872 vec
->operands
[i
] = Operand(0u);
4875 vec
->definitions
[0] = Definition(dst
);
4876 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4877 emit_split_vector(ctx
, dst
, dst
.size());
4879 if (num_temp
== dst
.size())
4880 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4882 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4883 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4884 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4885 if (off_instr
->type
!= nir_instr_type_load_const
||
4886 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4887 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4888 nir_print_instr(off_instr
, stderr
);
4889 fprintf(stderr
, "\n");
4892 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4893 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4895 assert(offset
->u32
== 0);
4897 /* the lower 15bit of the prim_mask contain the offset into LDS
4898 * while the upper bits contain the number of prims */
4899 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4900 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4901 Builder
bld(ctx
->program
, ctx
->block
);
4902 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4903 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4904 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4905 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4906 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4909 unsigned idx
= nir_intrinsic_base(instr
);
4910 unsigned component
= nir_intrinsic_component(instr
);
4911 unsigned vertex_id
= 2; /* P0 */
4913 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4914 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4915 switch (src0
->u32
) {
4917 vertex_id
= 2; /* P0 */
4920 vertex_id
= 0; /* P10 */
4923 vertex_id
= 1; /* P20 */
4926 unreachable("invalid vertex index");
4930 if (dst
.size() == 1) {
4931 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4933 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4934 for (unsigned i
= 0; i
< dst
.size(); i
++)
4935 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4936 vec
->definitions
[0] = Definition(dst
);
4937 bld
.insert(std::move(vec
));
4940 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4941 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4942 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4943 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4944 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4946 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4948 unreachable("Shader stage not implemented");
4952 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4954 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4956 Builder
bld(ctx
->program
, ctx
->block
);
4957 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4960 if (!nir_src_is_const(*vertex_src
)) {
4961 /* better code could be created, but this case probably doesn't happen
4962 * much in practice */
4963 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4964 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4967 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4968 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4970 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4972 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4975 if (vertex_offset
.id()) {
4976 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4977 Operand(i
), indirect_vertex
);
4978 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4980 vertex_offset
= elem
;
4984 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4985 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4987 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4988 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4989 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4990 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4991 Operand((vertex
% 2u) * 16u), Operand(16u));
4993 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4996 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4997 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4998 return offset_mul(ctx
, offs
, 4u);
5001 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5003 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5005 Builder
bld(ctx
->program
, ctx
->block
);
5006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5007 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5009 if (ctx
->stage
== geometry_gs
) {
5010 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
5011 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
5012 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
5013 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5014 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
5015 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5016 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5018 unreachable("Unsupported GS stage.");
5022 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5024 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5026 Builder
bld(ctx
->program
, ctx
->block
);
5027 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5029 if (load_input_from_temps(ctx
, instr
, dst
))
5032 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5033 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5034 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5036 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5039 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5041 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5043 Builder
bld(ctx
->program
, ctx
->block
);
5045 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5046 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5047 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5049 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5050 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5052 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5055 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5057 switch (ctx
->shader
->info
.stage
) {
5058 case MESA_SHADER_GEOMETRY
:
5059 visit_load_gs_per_vertex_input(ctx
, instr
);
5061 case MESA_SHADER_TESS_CTRL
:
5062 visit_load_tcs_per_vertex_input(ctx
, instr
);
5064 case MESA_SHADER_TESS_EVAL
:
5065 visit_load_tes_per_vertex_input(ctx
, instr
);
5068 unreachable("Unimplemented shader stage");
5072 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5074 visit_load_tcs_output(ctx
, instr
, true);
5077 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5079 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5080 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5082 visit_store_tcs_output(ctx
, instr
, true);
5085 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5087 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5089 Builder
bld(ctx
->program
, ctx
->block
);
5090 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5092 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5093 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5096 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5097 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5098 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5099 tes_w
= Operand(tmp
);
5102 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5103 emit_split_vector(ctx
, tess_coord
, 3);
5106 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5108 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5109 Builder
bld(ctx
->program
, ctx
->block
);
5110 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5111 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5112 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5115 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5119 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5121 Builder
bld(ctx
->program
, ctx
->block
);
5122 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5123 if (!nir_dest_is_divergent(instr
->dest
))
5124 index
= bld
.as_uniform(index
);
5125 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5126 unsigned binding
= nir_intrinsic_binding(instr
);
5129 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5130 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5131 unsigned offset
= layout
->binding
[binding
].offset
;
5133 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5134 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5135 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5136 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5137 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5140 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5141 stride
= layout
->binding
[binding
].size
;
5144 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5145 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5147 if (nir_const_index
) {
5148 const_index
= const_index
* stride
;
5149 } else if (index
.type() == RegType::vgpr
) {
5150 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5151 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5153 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5157 if (nir_const_index
) {
5158 const_index
= const_index
+ offset
;
5159 } else if (index
.type() == RegType::vgpr
) {
5160 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5162 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5166 if (nir_const_index
&& const_index
== 0) {
5168 } else if (index
.type() == RegType::vgpr
) {
5169 index
= bld
.vadd32(bld
.def(v1
),
5170 nir_const_index
? Operand(const_index
) : Operand(index
),
5173 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5174 nir_const_index
? Operand(const_index
) : Operand(index
),
5178 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5181 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5182 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5183 bool glc
=false, bool readonly
=true, bool allow_smem
=true)
5185 Builder
bld(ctx
->program
, ctx
->block
);
5187 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5189 offset
= bld
.as_uniform(offset
);
5191 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5193 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5194 info
.can_reorder
= readonly
;
5195 info
.align_mul
= align_mul
;
5196 info
.align_offset
= align_offset
;
5198 emit_smem_load(ctx
, bld
, &info
);
5200 emit_mubuf_load(ctx
, bld
, &info
);
5203 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5205 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5206 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5208 Builder
bld(ctx
->program
, ctx
->block
);
5210 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5211 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5212 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5213 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5215 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5216 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5217 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5218 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5219 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5220 if (ctx
->options
->chip_class
>= GFX10
) {
5221 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5222 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5223 S_008F0C_RESOURCE_LEVEL(1);
5225 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5226 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5228 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5229 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5230 Operand(0xFFFFFFFFu
),
5231 Operand(desc_type
));
5232 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5233 rsrc
, upper_dwords
);
5235 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5236 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5238 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5239 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5240 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5243 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5245 Builder
bld(ctx
->program
, ctx
->block
);
5246 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5247 unsigned offset
= nir_intrinsic_base(instr
);
5248 unsigned count
= instr
->dest
.ssa
.num_components
;
5249 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5251 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5252 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5253 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5254 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5255 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5256 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5257 for (unsigned i
= 0; i
< count
; ++i
) {
5258 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5259 vec
->operands
[i
] = Operand
{elems
[i
]};
5261 vec
->definitions
[0] = Definition(dst
);
5262 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5263 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5268 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5269 if (offset
!= 0) // TODO check if index != 0 as well
5270 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5271 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5274 bool aligned
= true;
5276 if (instr
->dest
.ssa
.bit_size
== 8) {
5277 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5278 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5280 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5281 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5282 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5284 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5289 switch (vec
.size()) {
5291 op
= aco_opcode::s_load_dword
;
5294 op
= aco_opcode::s_load_dwordx2
;
5300 op
= aco_opcode::s_load_dwordx4
;
5306 op
= aco_opcode::s_load_dwordx8
;
5309 unreachable("unimplemented or forbidden load_push_constant.");
5312 bld
.smem(op
, Definition(vec
), ptr
, index
);
5315 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5316 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5321 emit_split_vector(ctx
, vec
, 4);
5322 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5323 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5324 emit_extract_vector(ctx
, vec
, 0, rc
),
5325 emit_extract_vector(ctx
, vec
, 1, rc
),
5326 emit_extract_vector(ctx
, vec
, 2, rc
));
5329 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5332 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5334 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5336 Builder
bld(ctx
->program
, ctx
->block
);
5338 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5339 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5340 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5341 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5342 if (ctx
->options
->chip_class
>= GFX10
) {
5343 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5344 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5345 S_008F0C_RESOURCE_LEVEL(1);
5347 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5348 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5351 unsigned base
= nir_intrinsic_base(instr
);
5352 unsigned range
= nir_intrinsic_range(instr
);
5354 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5355 if (base
&& offset
.type() == RegType::sgpr
)
5356 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5357 else if (base
&& offset
.type() == RegType::vgpr
)
5358 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5360 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5361 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5362 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5363 Operand(desc_type
));
5364 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5365 // TODO: get alignment information for subdword constants
5366 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5369 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5371 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5372 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5374 ctx
->program
->needs_exact
= true;
5376 // TODO: optimize uniform conditions
5377 Builder
bld(ctx
->program
, ctx
->block
);
5378 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5379 assert(src
.regClass() == bld
.lm
);
5380 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5381 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5382 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5386 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5388 Builder
bld(ctx
->program
, ctx
->block
);
5390 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5391 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5393 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5394 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5396 if (ctx
->block
->loop_nest_depth
&&
5397 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5398 /* we handle discards the same way as jump instructions */
5399 append_logical_end(ctx
->block
);
5401 /* in loops, discard behaves like break */
5402 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5403 ctx
->block
->kind
|= block_kind_discard
;
5406 /* uniform discard - loop ends here */
5407 assert(nir_instr_is_last(&instr
->instr
));
5408 ctx
->block
->kind
|= block_kind_uniform
;
5409 ctx
->cf_info
.has_branch
= true;
5410 bld
.branch(aco_opcode::p_branch
);
5411 add_linear_edge(ctx
->block
->index
, linear_target
);
5415 /* we add a break right behind the discard() instructions */
5416 ctx
->block
->kind
|= block_kind_break
;
5417 unsigned idx
= ctx
->block
->index
;
5419 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5420 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5422 /* remove critical edges from linear CFG */
5423 bld
.branch(aco_opcode::p_branch
);
5424 Block
* break_block
= ctx
->program
->create_and_insert_block();
5425 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5426 break_block
->kind
|= block_kind_uniform
;
5427 add_linear_edge(idx
, break_block
);
5428 add_linear_edge(break_block
->index
, linear_target
);
5429 bld
.reset(break_block
);
5430 bld
.branch(aco_opcode::p_branch
);
5432 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5433 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5434 add_linear_edge(idx
, continue_block
);
5435 append_logical_start(continue_block
);
5436 ctx
->block
= continue_block
;
5441 /* it can currently happen that NIR doesn't remove the unreachable code */
5442 if (!nir_instr_is_last(&instr
->instr
)) {
5443 ctx
->program
->needs_exact
= true;
5444 /* save exec somewhere temporarily so that it doesn't get
5445 * overwritten before the discard from outer exec masks */
5446 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5447 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5448 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5452 /* This condition is incorrect for uniformly branched discards in a loop
5453 * predicated by a divergent condition, but the above code catches that case
5454 * and the discard would end up turning into a discard_if.
5464 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5465 /* program just ends here */
5466 ctx
->block
->kind
|= block_kind_uniform
;
5467 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5468 0 /* enabled mask */, 9 /* dest */,
5469 false /* compressed */, true/* done */, true /* valid mask */);
5470 bld
.sopp(aco_opcode::s_endpgm
);
5471 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5473 ctx
->block
->kind
|= block_kind_discard
;
5474 /* branch and linear edge is added by visit_if() */
5478 enum aco_descriptor_type
{
5489 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5490 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5492 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5493 return dim
== ac_image_cube
||
5494 dim
== ac_image_1darray
||
5495 dim
== ac_image_2darray
||
5496 dim
== ac_image_2darraymsaa
;
5499 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5500 enum aco_descriptor_type desc_type
,
5501 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5503 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5504 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5505 if (it != ctx->tex_desc.end())
5508 Temp index
= Temp();
5509 bool index_set
= false;
5510 unsigned constant_index
= 0;
5511 unsigned descriptor_set
;
5512 unsigned base_index
;
5513 Builder
bld(ctx
->program
, ctx
->block
);
5516 assert(tex_instr
&& !image
);
5518 base_index
= tex_instr
->sampler_index
;
5520 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5521 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5525 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5526 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5528 constant_index
+= array_size
* const_value
->u32
;
5530 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5531 if (indirect
.type() == RegType::vgpr
)
5532 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5534 if (array_size
!= 1)
5535 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5541 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5545 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5547 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5548 base_index
= deref_instr
->var
->data
.binding
;
5551 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5552 list
= convert_pointer_to_64_bit(ctx
, list
);
5554 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5555 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5556 unsigned offset
= binding
->offset
;
5557 unsigned stride
= binding
->size
;
5561 assert(base_index
< layout
->binding_count
);
5563 switch (desc_type
) {
5564 case ACO_DESC_IMAGE
:
5566 opcode
= aco_opcode::s_load_dwordx8
;
5568 case ACO_DESC_FMASK
:
5570 opcode
= aco_opcode::s_load_dwordx8
;
5573 case ACO_DESC_SAMPLER
:
5575 opcode
= aco_opcode::s_load_dwordx4
;
5576 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5577 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5579 case ACO_DESC_BUFFER
:
5581 opcode
= aco_opcode::s_load_dwordx4
;
5583 case ACO_DESC_PLANE_0
:
5584 case ACO_DESC_PLANE_1
:
5586 opcode
= aco_opcode::s_load_dwordx8
;
5587 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5589 case ACO_DESC_PLANE_2
:
5591 opcode
= aco_opcode::s_load_dwordx4
;
5595 unreachable("invalid desc_type\n");
5598 offset
+= constant_index
* stride
;
5600 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5601 (!index_set
|| binding
->immutable_samplers_equal
)) {
5602 if (binding
->immutable_samplers_equal
)
5605 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5606 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5607 Operand(samplers
[constant_index
* 4 + 0]),
5608 Operand(samplers
[constant_index
* 4 + 1]),
5609 Operand(samplers
[constant_index
* 4 + 2]),
5610 Operand(samplers
[constant_index
* 4 + 3]));
5615 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5617 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5618 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5621 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5623 if (desc_type
== ACO_DESC_PLANE_2
) {
5625 for (unsigned i
= 0; i
< 8; i
++)
5626 components
[i
] = bld
.tmp(s1
);
5627 bld
.pseudo(aco_opcode::p_split_vector
,
5628 Definition(components
[0]),
5629 Definition(components
[1]),
5630 Definition(components
[2]),
5631 Definition(components
[3]),
5634 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5635 bld
.pseudo(aco_opcode::p_split_vector
,
5636 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5637 Definition(components
[4]),
5638 Definition(components
[5]),
5639 Definition(components
[6]),
5640 Definition(components
[7]),
5643 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5644 components
[0], components
[1], components
[2], components
[3],
5645 components
[4], components
[5], components
[6], components
[7]);
5651 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5654 case GLSL_SAMPLER_DIM_BUF
:
5656 case GLSL_SAMPLER_DIM_1D
:
5657 return array
? 2 : 1;
5658 case GLSL_SAMPLER_DIM_2D
:
5659 return array
? 3 : 2;
5660 case GLSL_SAMPLER_DIM_MS
:
5661 return array
? 4 : 3;
5662 case GLSL_SAMPLER_DIM_3D
:
5663 case GLSL_SAMPLER_DIM_CUBE
:
5665 case GLSL_SAMPLER_DIM_RECT
:
5666 case GLSL_SAMPLER_DIM_SUBPASS
:
5668 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5677 /* Adjust the sample index according to FMASK.
5679 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5680 * which is the identity mapping. Each nibble says which physical sample
5681 * should be fetched to get that sample.
5683 * For example, 0x11111100 means there are only 2 samples stored and
5684 * the second sample covers 3/4 of the pixel. When reading samples 0
5685 * and 1, return physical sample 0 (determined by the first two 0s
5686 * in FMASK), otherwise return physical sample 1.
5688 * The sample index should be adjusted as follows:
5689 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5691 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5693 Builder
bld(ctx
->program
, ctx
->block
);
5694 Temp fmask
= bld
.tmp(v1
);
5695 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5696 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5699 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5700 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5701 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5702 load
->operands
[0] = Operand(fmask_desc_ptr
);
5703 load
->operands
[1] = Operand(s4
); /* no sampler */
5704 load
->operands
[2] = Operand(coord
);
5705 load
->definitions
[0] = Definition(fmask
);
5712 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5713 ctx
->block
->instructions
.emplace_back(std::move(load
));
5715 Operand sample_index4
;
5716 if (sample_index
.isConstant()) {
5717 if (sample_index
.constantValue() < 16) {
5718 sample_index4
= Operand(sample_index
.constantValue() << 2);
5720 sample_index4
= Operand(0u);
5722 } else if (sample_index
.regClass() == s1
) {
5723 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5725 assert(sample_index
.regClass() == v1
);
5726 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5730 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5731 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5732 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5733 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5735 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5737 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5738 * resource descriptor is 0 (invalid),
5740 Temp compare
= bld
.tmp(bld
.lm
);
5741 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5742 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5744 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5746 /* Replace the MSAA sample index. */
5747 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5750 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5753 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5754 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5755 bool is_array
= glsl_sampler_type_is_array(type
);
5756 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5757 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5758 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5759 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5760 int count
= image_type_to_components_count(dim
, is_array
);
5761 std::vector
<Temp
> coords(count
);
5762 Builder
bld(ctx
->program
, ctx
->block
);
5766 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5767 /* get sample index */
5768 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5769 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5770 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5771 std::vector
<Temp
> fmask_load_address
;
5772 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5773 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5775 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5776 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5778 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5783 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5784 coords
.resize(coords
.size() + 1);
5785 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5787 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5789 for (int i
= 0; i
< count
; i
++)
5790 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5793 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5794 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5795 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5796 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5799 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5802 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5803 for (unsigned i
= 0; i
< coords
.size(); i
++)
5804 vec
->operands
[i
] = Operand(coords
[i
]);
5805 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5806 vec
->definitions
[0] = Definition(res
);
5807 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5812 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5814 Builder
bld(ctx
->program
, ctx
->block
);
5815 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5816 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5817 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5818 bool is_array
= glsl_sampler_type_is_array(type
);
5819 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5821 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5822 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5823 unsigned num_channels
= util_last_bit(mask
);
5824 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5825 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5828 switch (num_channels
) {
5830 opcode
= aco_opcode::buffer_load_format_x
;
5833 opcode
= aco_opcode::buffer_load_format_xy
;
5836 opcode
= aco_opcode::buffer_load_format_xyz
;
5839 opcode
= aco_opcode::buffer_load_format_xyzw
;
5842 unreachable(">4 channel buffer image load");
5844 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5845 load
->operands
[0] = Operand(rsrc
);
5846 load
->operands
[1] = Operand(vindex
);
5847 load
->operands
[2] = Operand((uint32_t) 0);
5849 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5852 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5853 load
->definitions
[0] = Definition(tmp
);
5855 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5856 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5857 load
->barrier
= barrier_image
;
5858 ctx
->block
->instructions
.emplace_back(std::move(load
));
5860 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5864 Temp coords
= get_image_coords(ctx
, instr
, type
);
5865 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5867 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5868 unsigned num_components
= util_bitcount(dmask
);
5870 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5873 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5875 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5876 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5878 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5879 load
->operands
[0] = Operand(resource
);
5880 load
->operands
[1] = Operand(s4
); /* no sampler */
5881 load
->operands
[2] = Operand(coords
);
5882 load
->definitions
[0] = Definition(tmp
);
5883 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5884 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5885 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5886 load
->dmask
= dmask
;
5888 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5889 load
->barrier
= barrier_image
;
5890 ctx
->block
->instructions
.emplace_back(std::move(load
));
5892 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5896 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5898 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5899 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5900 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5901 bool is_array
= glsl_sampler_type_is_array(type
);
5902 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5904 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5906 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5907 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5908 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5910 switch (data
.size()) {
5912 opcode
= aco_opcode::buffer_store_format_x
;
5915 opcode
= aco_opcode::buffer_store_format_xy
;
5918 opcode
= aco_opcode::buffer_store_format_xyz
;
5921 opcode
= aco_opcode::buffer_store_format_xyzw
;
5924 unreachable(">4 channel buffer image store");
5926 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5927 store
->operands
[0] = Operand(rsrc
);
5928 store
->operands
[1] = Operand(vindex
);
5929 store
->operands
[2] = Operand((uint32_t) 0);
5930 store
->operands
[3] = Operand(data
);
5931 store
->idxen
= true;
5934 store
->disable_wqm
= true;
5935 store
->barrier
= barrier_image
;
5936 ctx
->program
->needs_exact
= true;
5937 ctx
->block
->instructions
.emplace_back(std::move(store
));
5941 assert(data
.type() == RegType::vgpr
);
5942 Temp coords
= get_image_coords(ctx
, instr
, type
);
5943 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5945 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5946 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5948 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5949 store
->operands
[0] = Operand(resource
);
5950 store
->operands
[1] = Operand(data
);
5951 store
->operands
[2] = Operand(coords
);
5954 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5955 store
->dmask
= (1 << data
.size()) - 1;
5957 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5958 store
->disable_wqm
= true;
5959 store
->barrier
= barrier_image
;
5960 ctx
->program
->needs_exact
= true;
5961 ctx
->block
->instructions
.emplace_back(std::move(store
));
5965 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5967 /* return the previous value if dest is ever used */
5968 bool return_previous
= false;
5969 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5970 return_previous
= true;
5973 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5974 return_previous
= true;
5978 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5979 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5980 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5981 bool is_array
= glsl_sampler_type_is_array(type
);
5982 Builder
bld(ctx
->program
, ctx
->block
);
5984 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5985 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5987 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5988 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5990 aco_opcode buf_op
, image_op
;
5991 switch (instr
->intrinsic
) {
5992 case nir_intrinsic_image_deref_atomic_add
:
5993 buf_op
= aco_opcode::buffer_atomic_add
;
5994 image_op
= aco_opcode::image_atomic_add
;
5996 case nir_intrinsic_image_deref_atomic_umin
:
5997 buf_op
= aco_opcode::buffer_atomic_umin
;
5998 image_op
= aco_opcode::image_atomic_umin
;
6000 case nir_intrinsic_image_deref_atomic_imin
:
6001 buf_op
= aco_opcode::buffer_atomic_smin
;
6002 image_op
= aco_opcode::image_atomic_smin
;
6004 case nir_intrinsic_image_deref_atomic_umax
:
6005 buf_op
= aco_opcode::buffer_atomic_umax
;
6006 image_op
= aco_opcode::image_atomic_umax
;
6008 case nir_intrinsic_image_deref_atomic_imax
:
6009 buf_op
= aco_opcode::buffer_atomic_smax
;
6010 image_op
= aco_opcode::image_atomic_smax
;
6012 case nir_intrinsic_image_deref_atomic_and
:
6013 buf_op
= aco_opcode::buffer_atomic_and
;
6014 image_op
= aco_opcode::image_atomic_and
;
6016 case nir_intrinsic_image_deref_atomic_or
:
6017 buf_op
= aco_opcode::buffer_atomic_or
;
6018 image_op
= aco_opcode::image_atomic_or
;
6020 case nir_intrinsic_image_deref_atomic_xor
:
6021 buf_op
= aco_opcode::buffer_atomic_xor
;
6022 image_op
= aco_opcode::image_atomic_xor
;
6024 case nir_intrinsic_image_deref_atomic_exchange
:
6025 buf_op
= aco_opcode::buffer_atomic_swap
;
6026 image_op
= aco_opcode::image_atomic_swap
;
6028 case nir_intrinsic_image_deref_atomic_comp_swap
:
6029 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
6030 image_op
= aco_opcode::image_atomic_cmpswap
;
6033 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6038 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6039 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6040 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6041 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6042 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6043 mubuf
->operands
[0] = Operand(resource
);
6044 mubuf
->operands
[1] = Operand(vindex
);
6045 mubuf
->operands
[2] = Operand((uint32_t)0);
6046 mubuf
->operands
[3] = Operand(data
);
6047 if (return_previous
)
6048 mubuf
->definitions
[0] = Definition(dst
);
6050 mubuf
->idxen
= true;
6051 mubuf
->glc
= return_previous
;
6052 mubuf
->dlc
= false; /* Not needed for atomics */
6053 mubuf
->disable_wqm
= true;
6054 mubuf
->barrier
= barrier_image
;
6055 ctx
->program
->needs_exact
= true;
6056 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6060 Temp coords
= get_image_coords(ctx
, instr
, type
);
6061 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6062 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6063 mimg
->operands
[0] = Operand(resource
);
6064 mimg
->operands
[1] = Operand(data
);
6065 mimg
->operands
[2] = Operand(coords
);
6066 if (return_previous
)
6067 mimg
->definitions
[0] = Definition(dst
);
6068 mimg
->glc
= return_previous
;
6069 mimg
->dlc
= false; /* Not needed for atomics */
6070 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6071 mimg
->dmask
= (1 << data
.size()) - 1;
6073 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6074 mimg
->disable_wqm
= true;
6075 mimg
->barrier
= barrier_image
;
6076 ctx
->program
->needs_exact
= true;
6077 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6081 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6083 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6084 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6085 Builder
bld(ctx
->program
, ctx
->block
);
6087 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6089 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6090 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6092 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6093 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6095 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6096 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6098 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6099 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6100 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6101 if (dst
.type() == RegType::vgpr
)
6102 bld
.copy(Definition(dst
), shr_dst
);
6104 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6106 emit_extract_vector(ctx
, desc
, 2, dst
);
6110 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6112 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6113 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6114 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6115 bool is_array
= glsl_sampler_type_is_array(type
);
6116 Builder
bld(ctx
->program
, ctx
->block
);
6118 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6119 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6120 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6124 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6127 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6129 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6131 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6132 mimg
->operands
[0] = Operand(resource
);
6133 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6134 mimg
->operands
[2] = Operand(lod
);
6135 uint8_t& dmask
= mimg
->dmask
;
6136 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6137 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6138 mimg
->da
= glsl_sampler_type_is_array(type
);
6139 mimg
->can_reorder
= true;
6140 Definition
& def
= mimg
->definitions
[0];
6141 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6143 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6144 glsl_sampler_type_is_array(type
)) {
6146 assert(instr
->dest
.ssa
.num_components
== 3);
6147 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6148 def
= Definition(tmp
);
6149 emit_split_vector(ctx
, tmp
, 3);
6151 /* divide 3rd value by 6 by multiplying with magic number */
6152 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6153 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6155 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6156 emit_extract_vector(ctx
, tmp
, 0, v1
),
6157 emit_extract_vector(ctx
, tmp
, 1, v1
),
6160 } else if (ctx
->options
->chip_class
== GFX9
&&
6161 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6162 glsl_sampler_type_is_array(type
)) {
6163 assert(instr
->dest
.ssa
.num_components
== 2);
6164 def
= Definition(dst
);
6167 def
= Definition(dst
);
6170 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6173 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6175 Builder
bld(ctx
->program
, ctx
->block
);
6176 unsigned num_components
= instr
->num_components
;
6178 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6179 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6180 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6182 unsigned access
= nir_intrinsic_access(instr
);
6183 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6184 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6186 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6187 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6188 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6190 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6191 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6193 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6194 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false, allow_smem
);
6197 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6199 Builder
bld(ctx
->program
, ctx
->block
);
6200 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6201 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6202 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6203 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6205 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6206 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6208 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6209 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6210 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6211 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6213 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6215 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6216 ctx
->options
->chip_class
>= GFX8
&&
6217 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6220 offset
= bld
.as_uniform(offset
);
6221 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6223 unsigned write_count
= 0;
6224 Temp write_datas
[32];
6225 unsigned offsets
[32];
6226 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6227 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6229 for (unsigned i
= 0; i
< write_count
; i
++) {
6230 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6231 if (smem
&& ctx
->stage
== fragment_fs
)
6232 op
= aco_opcode::p_fs_buffer_store_smem
;
6235 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6236 store
->operands
[0] = Operand(rsrc
);
6238 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6239 offset
, Operand(offsets
[i
]));
6240 store
->operands
[1] = Operand(off
);
6242 store
->operands
[1] = Operand(offset
);
6244 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6245 store
->operands
[1].setFixed(m0
);
6246 store
->operands
[2] = Operand(write_datas
[i
]);
6249 store
->disable_wqm
= true;
6250 store
->barrier
= barrier_buffer
;
6251 ctx
->block
->instructions
.emplace_back(std::move(store
));
6252 ctx
->program
->wb_smem_l1_on_end
= true;
6253 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6254 ctx
->block
->kind
|= block_kind_needs_lowering
;
6255 ctx
->program
->needs_exact
= true;
6258 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6259 store
->operands
[0] = Operand(rsrc
);
6260 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6261 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6262 store
->operands
[3] = Operand(write_datas
[i
]);
6263 store
->offset
= offsets
[i
];
6264 store
->offen
= (offset
.type() == RegType::vgpr
);
6267 store
->disable_wqm
= true;
6268 store
->barrier
= barrier_buffer
;
6269 ctx
->program
->needs_exact
= true;
6270 ctx
->block
->instructions
.emplace_back(std::move(store
));
6275 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6277 /* return the previous value if dest is ever used */
6278 bool return_previous
= false;
6279 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6280 return_previous
= true;
6283 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6284 return_previous
= true;
6288 Builder
bld(ctx
->program
, ctx
->block
);
6289 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6291 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6292 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6293 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6295 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6296 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6297 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6299 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6301 aco_opcode op32
, op64
;
6302 switch (instr
->intrinsic
) {
6303 case nir_intrinsic_ssbo_atomic_add
:
6304 op32
= aco_opcode::buffer_atomic_add
;
6305 op64
= aco_opcode::buffer_atomic_add_x2
;
6307 case nir_intrinsic_ssbo_atomic_imin
:
6308 op32
= aco_opcode::buffer_atomic_smin
;
6309 op64
= aco_opcode::buffer_atomic_smin_x2
;
6311 case nir_intrinsic_ssbo_atomic_umin
:
6312 op32
= aco_opcode::buffer_atomic_umin
;
6313 op64
= aco_opcode::buffer_atomic_umin_x2
;
6315 case nir_intrinsic_ssbo_atomic_imax
:
6316 op32
= aco_opcode::buffer_atomic_smax
;
6317 op64
= aco_opcode::buffer_atomic_smax_x2
;
6319 case nir_intrinsic_ssbo_atomic_umax
:
6320 op32
= aco_opcode::buffer_atomic_umax
;
6321 op64
= aco_opcode::buffer_atomic_umax_x2
;
6323 case nir_intrinsic_ssbo_atomic_and
:
6324 op32
= aco_opcode::buffer_atomic_and
;
6325 op64
= aco_opcode::buffer_atomic_and_x2
;
6327 case nir_intrinsic_ssbo_atomic_or
:
6328 op32
= aco_opcode::buffer_atomic_or
;
6329 op64
= aco_opcode::buffer_atomic_or_x2
;
6331 case nir_intrinsic_ssbo_atomic_xor
:
6332 op32
= aco_opcode::buffer_atomic_xor
;
6333 op64
= aco_opcode::buffer_atomic_xor_x2
;
6335 case nir_intrinsic_ssbo_atomic_exchange
:
6336 op32
= aco_opcode::buffer_atomic_swap
;
6337 op64
= aco_opcode::buffer_atomic_swap_x2
;
6339 case nir_intrinsic_ssbo_atomic_comp_swap
:
6340 op32
= aco_opcode::buffer_atomic_cmpswap
;
6341 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6344 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6346 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6347 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6348 mubuf
->operands
[0] = Operand(rsrc
);
6349 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6350 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6351 mubuf
->operands
[3] = Operand(data
);
6352 if (return_previous
)
6353 mubuf
->definitions
[0] = Definition(dst
);
6355 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6356 mubuf
->glc
= return_previous
;
6357 mubuf
->dlc
= false; /* Not needed for atomics */
6358 mubuf
->disable_wqm
= true;
6359 mubuf
->barrier
= barrier_buffer
;
6360 ctx
->program
->needs_exact
= true;
6361 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6364 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6366 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6367 Builder
bld(ctx
->program
, ctx
->block
);
6368 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6369 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6372 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6374 Builder
bld(ctx
->program
, ctx
->block
);
6375 unsigned num_components
= instr
->num_components
;
6376 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6378 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6379 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6380 num_components
, component_size
};
6381 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6382 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6383 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6384 info
.barrier
= barrier_buffer
;
6385 info
.can_reorder
= false;
6386 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6387 * it's safe to use SMEM */
6388 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6389 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6390 emit_global_load(ctx
, bld
, &info
);
6392 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6393 emit_smem_load(ctx
, bld
, &info
);
6397 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6399 Builder
bld(ctx
->program
, ctx
->block
);
6400 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6401 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6403 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6404 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6405 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6407 if (ctx
->options
->chip_class
>= GFX7
)
6408 addr
= as_vgpr(ctx
, addr
);
6410 unsigned write_count
= 0;
6411 Temp write_datas
[32];
6412 unsigned offsets
[32];
6413 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6414 16, &write_count
, write_datas
, offsets
);
6416 for (unsigned i
= 0; i
< write_count
; i
++) {
6417 if (ctx
->options
->chip_class
>= GFX7
) {
6418 unsigned offset
= offsets
[i
];
6419 Temp store_addr
= addr
;
6420 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6421 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6422 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6423 Temp carry
= bld
.tmp(bld
.lm
);
6424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6426 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6427 Operand(offset
), addr0
);
6428 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6430 carry
).def(1).setHint(vcc
);
6432 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6437 bool global
= ctx
->options
->chip_class
>= GFX9
;
6439 switch (write_datas
[i
].bytes()) {
6441 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6444 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6447 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6450 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6453 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6456 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6459 unreachable("store_global not implemented for this size.");
6462 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6463 flat
->operands
[0] = Operand(store_addr
);
6464 flat
->operands
[1] = Operand(s1
);
6465 flat
->operands
[2] = Operand(write_datas
[i
]);
6468 flat
->offset
= offset
;
6469 flat
->disable_wqm
= true;
6470 flat
->barrier
= barrier_buffer
;
6471 ctx
->program
->needs_exact
= true;
6472 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6474 assert(ctx
->options
->chip_class
== GFX6
);
6476 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6478 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6480 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6481 mubuf
->operands
[0] = Operand(rsrc
);
6482 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6483 mubuf
->operands
[2] = Operand(0u);
6484 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6487 mubuf
->offset
= offsets
[i
];
6488 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6489 mubuf
->disable_wqm
= true;
6490 mubuf
->barrier
= barrier_buffer
;
6491 ctx
->program
->needs_exact
= true;
6492 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6497 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6499 /* return the previous value if dest is ever used */
6500 bool return_previous
= false;
6501 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6502 return_previous
= true;
6505 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6506 return_previous
= true;
6510 Builder
bld(ctx
->program
, ctx
->block
);
6511 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6512 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6514 if (ctx
->options
->chip_class
>= GFX7
)
6515 addr
= as_vgpr(ctx
, addr
);
6517 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6518 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6519 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6521 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6523 aco_opcode op32
, op64
;
6525 if (ctx
->options
->chip_class
>= GFX7
) {
6526 bool global
= ctx
->options
->chip_class
>= GFX9
;
6527 switch (instr
->intrinsic
) {
6528 case nir_intrinsic_global_atomic_add
:
6529 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6530 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6532 case nir_intrinsic_global_atomic_imin
:
6533 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6534 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6536 case nir_intrinsic_global_atomic_umin
:
6537 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6538 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6540 case nir_intrinsic_global_atomic_imax
:
6541 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6542 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6544 case nir_intrinsic_global_atomic_umax
:
6545 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6546 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6548 case nir_intrinsic_global_atomic_and
:
6549 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6550 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6552 case nir_intrinsic_global_atomic_or
:
6553 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6554 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6556 case nir_intrinsic_global_atomic_xor
:
6557 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6558 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6560 case nir_intrinsic_global_atomic_exchange
:
6561 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6562 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6564 case nir_intrinsic_global_atomic_comp_swap
:
6565 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6566 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6569 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6572 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6573 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6574 flat
->operands
[0] = Operand(addr
);
6575 flat
->operands
[1] = Operand(s1
);
6576 flat
->operands
[2] = Operand(data
);
6577 if (return_previous
)
6578 flat
->definitions
[0] = Definition(dst
);
6579 flat
->glc
= return_previous
;
6580 flat
->dlc
= false; /* Not needed for atomics */
6582 flat
->disable_wqm
= true;
6583 flat
->barrier
= barrier_buffer
;
6584 ctx
->program
->needs_exact
= true;
6585 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6587 assert(ctx
->options
->chip_class
== GFX6
);
6589 switch (instr
->intrinsic
) {
6590 case nir_intrinsic_global_atomic_add
:
6591 op32
= aco_opcode::buffer_atomic_add
;
6592 op64
= aco_opcode::buffer_atomic_add_x2
;
6594 case nir_intrinsic_global_atomic_imin
:
6595 op32
= aco_opcode::buffer_atomic_smin
;
6596 op64
= aco_opcode::buffer_atomic_smin_x2
;
6598 case nir_intrinsic_global_atomic_umin
:
6599 op32
= aco_opcode::buffer_atomic_umin
;
6600 op64
= aco_opcode::buffer_atomic_umin_x2
;
6602 case nir_intrinsic_global_atomic_imax
:
6603 op32
= aco_opcode::buffer_atomic_smax
;
6604 op64
= aco_opcode::buffer_atomic_smax_x2
;
6606 case nir_intrinsic_global_atomic_umax
:
6607 op32
= aco_opcode::buffer_atomic_umax
;
6608 op64
= aco_opcode::buffer_atomic_umax_x2
;
6610 case nir_intrinsic_global_atomic_and
:
6611 op32
= aco_opcode::buffer_atomic_and
;
6612 op64
= aco_opcode::buffer_atomic_and_x2
;
6614 case nir_intrinsic_global_atomic_or
:
6615 op32
= aco_opcode::buffer_atomic_or
;
6616 op64
= aco_opcode::buffer_atomic_or_x2
;
6618 case nir_intrinsic_global_atomic_xor
:
6619 op32
= aco_opcode::buffer_atomic_xor
;
6620 op64
= aco_opcode::buffer_atomic_xor_x2
;
6622 case nir_intrinsic_global_atomic_exchange
:
6623 op32
= aco_opcode::buffer_atomic_swap
;
6624 op64
= aco_opcode::buffer_atomic_swap_x2
;
6626 case nir_intrinsic_global_atomic_comp_swap
:
6627 op32
= aco_opcode::buffer_atomic_cmpswap
;
6628 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6631 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6634 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6636 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6638 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6639 mubuf
->operands
[0] = Operand(rsrc
);
6640 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6641 mubuf
->operands
[2] = Operand(0u);
6642 mubuf
->operands
[3] = Operand(data
);
6643 if (return_previous
)
6644 mubuf
->definitions
[0] = Definition(dst
);
6645 mubuf
->glc
= return_previous
;
6648 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6649 mubuf
->disable_wqm
= true;
6650 mubuf
->barrier
= barrier_buffer
;
6651 ctx
->program
->needs_exact
= true;
6652 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6656 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6657 Builder
bld(ctx
->program
, ctx
->block
);
6658 switch(instr
->intrinsic
) {
6659 case nir_intrinsic_group_memory_barrier
:
6660 case nir_intrinsic_memory_barrier
:
6661 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6663 case nir_intrinsic_memory_barrier_buffer
:
6664 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6666 case nir_intrinsic_memory_barrier_image
:
6667 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6669 case nir_intrinsic_memory_barrier_tcs_patch
:
6670 case nir_intrinsic_memory_barrier_shared
:
6671 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6674 unreachable("Unimplemented memory barrier intrinsic");
6679 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6681 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6682 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6683 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6684 Builder
bld(ctx
->program
, ctx
->block
);
6686 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6687 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6688 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6691 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6693 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6694 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6695 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6696 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6698 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6699 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6702 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6704 unsigned offset
= nir_intrinsic_base(instr
);
6705 Builder
bld(ctx
->program
, ctx
->block
);
6706 Operand m
= load_lds_size_m0(bld
);
6707 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6708 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6710 unsigned num_operands
= 3;
6711 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6712 switch(instr
->intrinsic
) {
6713 case nir_intrinsic_shared_atomic_add
:
6714 op32
= aco_opcode::ds_add_u32
;
6715 op64
= aco_opcode::ds_add_u64
;
6716 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6717 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6719 case nir_intrinsic_shared_atomic_imin
:
6720 op32
= aco_opcode::ds_min_i32
;
6721 op64
= aco_opcode::ds_min_i64
;
6722 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6723 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6725 case nir_intrinsic_shared_atomic_umin
:
6726 op32
= aco_opcode::ds_min_u32
;
6727 op64
= aco_opcode::ds_min_u64
;
6728 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6729 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6731 case nir_intrinsic_shared_atomic_imax
:
6732 op32
= aco_opcode::ds_max_i32
;
6733 op64
= aco_opcode::ds_max_i64
;
6734 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6735 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6737 case nir_intrinsic_shared_atomic_umax
:
6738 op32
= aco_opcode::ds_max_u32
;
6739 op64
= aco_opcode::ds_max_u64
;
6740 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6741 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6743 case nir_intrinsic_shared_atomic_and
:
6744 op32
= aco_opcode::ds_and_b32
;
6745 op64
= aco_opcode::ds_and_b64
;
6746 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6747 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6749 case nir_intrinsic_shared_atomic_or
:
6750 op32
= aco_opcode::ds_or_b32
;
6751 op64
= aco_opcode::ds_or_b64
;
6752 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6753 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6755 case nir_intrinsic_shared_atomic_xor
:
6756 op32
= aco_opcode::ds_xor_b32
;
6757 op64
= aco_opcode::ds_xor_b64
;
6758 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6759 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6761 case nir_intrinsic_shared_atomic_exchange
:
6762 op32
= aco_opcode::ds_write_b32
;
6763 op64
= aco_opcode::ds_write_b64
;
6764 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6765 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6767 case nir_intrinsic_shared_atomic_comp_swap
:
6768 op32
= aco_opcode::ds_cmpst_b32
;
6769 op64
= aco_opcode::ds_cmpst_b64
;
6770 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6771 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6775 unreachable("Unhandled shared atomic intrinsic");
6778 /* return the previous value if dest is ever used */
6779 bool return_previous
= false;
6780 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6781 return_previous
= true;
6784 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6785 return_previous
= true;
6790 if (data
.size() == 1) {
6791 assert(instr
->dest
.ssa
.bit_size
== 32);
6792 op
= return_previous
? op32_rtn
: op32
;
6794 assert(instr
->dest
.ssa
.bit_size
== 64);
6795 op
= return_previous
? op64_rtn
: op64
;
6798 if (offset
> 65535) {
6799 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6803 aco_ptr
<DS_instruction
> ds
;
6804 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6805 ds
->operands
[0] = Operand(address
);
6806 ds
->operands
[1] = Operand(data
);
6807 if (num_operands
== 4)
6808 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6809 ds
->operands
[num_operands
- 1] = m
;
6810 ds
->offset0
= offset
;
6811 if (return_previous
)
6812 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6813 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6816 Temp
get_scratch_resource(isel_context
*ctx
)
6818 Builder
bld(ctx
->program
, ctx
->block
);
6819 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6820 if (ctx
->stage
!= compute_cs
)
6821 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6823 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6824 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6826 if (ctx
->program
->chip_class
>= GFX10
) {
6827 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6828 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6829 S_008F0C_RESOURCE_LEVEL(1);
6830 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6831 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6832 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6835 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6836 if (ctx
->program
->chip_class
<= GFX8
)
6837 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6839 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6842 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6843 Builder
bld(ctx
->program
, ctx
->block
);
6844 Temp rsrc
= get_scratch_resource(ctx
);
6845 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6846 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6848 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6849 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6850 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6851 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6852 info
.swizzle_component_size
= 16;
6853 info
.can_reorder
= false;
6854 info
.soffset
= ctx
->program
->scratch_offset
;
6855 emit_mubuf_load(ctx
, bld
, &info
);
6858 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6859 Builder
bld(ctx
->program
, ctx
->block
);
6860 Temp rsrc
= get_scratch_resource(ctx
);
6861 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6862 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6864 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6865 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6867 unsigned write_count
= 0;
6868 Temp write_datas
[32];
6869 unsigned offsets
[32];
6870 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6871 16, &write_count
, write_datas
, offsets
);
6873 for (unsigned i
= 0; i
< write_count
; i
++) {
6874 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6875 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6879 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6880 uint8_t log2_ps_iter_samples
;
6881 if (ctx
->program
->info
->ps
.force_persample
) {
6882 log2_ps_iter_samples
=
6883 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6885 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6888 /* The bit pattern matches that used by fixed function fragment
6890 static const unsigned ps_iter_masks
[] = {
6891 0xffff, /* not used */
6897 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6899 Builder
bld(ctx
->program
, ctx
->block
);
6901 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6902 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6903 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6904 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6905 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6906 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6909 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6910 Builder
bld(ctx
->program
, ctx
->block
);
6912 unsigned stream
= nir_intrinsic_stream_id(instr
);
6913 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6914 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6915 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6918 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6920 unsigned num_components
=
6921 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6922 assert(num_components
);
6924 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6925 unsigned stream_offset
= 0;
6926 for (unsigned i
= 0; i
< stream
; i
++) {
6927 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6928 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6931 /* Limit on the stride field for <= GFX7. */
6932 assert(stride
< (1 << 14));
6934 Temp gsvs_dwords
[4];
6935 for (unsigned i
= 0; i
< 4; i
++)
6936 gsvs_dwords
[i
] = bld
.tmp(s1
);
6937 bld
.pseudo(aco_opcode::p_split_vector
,
6938 Definition(gsvs_dwords
[0]),
6939 Definition(gsvs_dwords
[1]),
6940 Definition(gsvs_dwords
[2]),
6941 Definition(gsvs_dwords
[3]),
6944 if (stream_offset
) {
6945 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6947 Temp carry
= bld
.tmp(s1
);
6948 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6949 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6952 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6953 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6955 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6956 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6958 unsigned offset
= 0;
6959 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6960 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6963 for (unsigned j
= 0; j
< 4; j
++) {
6964 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6967 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6968 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6969 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6970 if (const_offset
>= 4096u) {
6971 if (vaddr_offset
.isUndefined())
6972 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6974 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6975 const_offset
%= 4096u;
6978 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6979 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6980 mtbuf
->operands
[1] = vaddr_offset
;
6981 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6982 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6983 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6984 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6985 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6986 mtbuf
->offset
= const_offset
;
6989 mtbuf
->barrier
= barrier_gs_data
;
6990 mtbuf
->can_reorder
= true;
6991 bld
.insert(std::move(mtbuf
));
6994 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6997 /* outputs for the next vertex are undefined and keeping them around can
6998 * create invalid IR with control flow */
6999 ctx
->outputs
.mask
[i
] = 0;
7002 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7005 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7007 Builder
bld(ctx
->program
, ctx
->block
);
7009 if (cluster_size
== 1) {
7011 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7012 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7013 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7014 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7015 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7016 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7017 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7018 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7019 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7020 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7021 //subgroupAnd(val) -> (exec & ~val) == 0
7022 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7023 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7024 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7025 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7026 //subgroupOr(val) -> (val & exec) != 0
7027 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7028 return bool_to_vector_condition(ctx
, tmp
);
7029 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7030 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7031 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7032 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7033 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7034 return bool_to_vector_condition(ctx
, tmp
);
7036 //subgroupClustered{And,Or,Xor}(val, n) ->
7037 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7038 //cluster_offset = ~(n - 1) & lane_id
7039 //cluster_mask = ((1 << n) - 1)
7040 //subgroupClusteredAnd():
7041 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7042 //subgroupClusteredOr():
7043 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7044 //subgroupClusteredXor():
7045 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7046 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7047 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7050 if (op
== nir_op_iand
)
7051 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7053 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7055 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7057 if (ctx
->program
->chip_class
<= GFX7
)
7058 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7059 else if (ctx
->program
->wave_size
== 64)
7060 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7062 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7063 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7064 if (cluster_mask
!= 0xffffffff)
7065 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7067 Definition cmp_def
= Definition();
7068 if (op
== nir_op_iand
) {
7069 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7070 } else if (op
== nir_op_ior
) {
7071 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7072 } else if (op
== nir_op_ixor
) {
7073 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7074 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7075 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7077 cmp_def
.setHint(vcc
);
7078 return cmp_def
.getTemp();
7082 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7084 Builder
bld(ctx
->program
, ctx
->block
);
7086 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7087 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7088 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7090 if (op
== nir_op_iand
)
7091 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7093 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7095 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7096 Temp lo
= lohi
.def(0).getTemp();
7097 Temp hi
= lohi
.def(1).getTemp();
7098 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7100 Definition cmp_def
= Definition();
7101 if (op
== nir_op_iand
)
7102 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7103 else if (op
== nir_op_ior
)
7104 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7105 else if (op
== nir_op_ixor
)
7106 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7107 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7108 cmp_def
.setHint(vcc
);
7109 return cmp_def
.getTemp();
7112 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7114 Builder
bld(ctx
->program
, ctx
->block
);
7116 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7117 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7118 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7119 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7120 if (op
== nir_op_iand
)
7121 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7122 else if (op
== nir_op_ior
)
7123 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7124 else if (op
== nir_op_ixor
)
7125 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7131 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7133 Builder
bld(ctx
->program
, ctx
->block
);
7134 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7135 if (src
.regClass().type() == RegType::vgpr
) {
7136 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7137 } else if (src
.regClass() == s1
) {
7138 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7139 } else if (src
.regClass() == s2
) {
7140 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7142 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7143 nir_print_instr(&instr
->instr
, stderr
);
7144 fprintf(stderr
, "\n");
7148 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7150 Builder
bld(ctx
->program
, ctx
->block
);
7151 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7152 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7153 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7155 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7156 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7157 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7158 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7161 if (ctx
->program
->chip_class
>= GFX8
) {
7162 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7163 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7164 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7165 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7166 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7167 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7169 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7170 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7171 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7172 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7173 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7174 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7175 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7176 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7177 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7178 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7181 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7182 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7183 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7184 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7185 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7186 Temp wqm1
= bld
.tmp(v1
);
7187 emit_wqm(ctx
, tmp1
, wqm1
, true);
7188 Temp wqm2
= bld
.tmp(v1
);
7189 emit_wqm(ctx
, tmp2
, wqm2
, true);
7190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7194 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7196 Builder
bld(ctx
->program
, ctx
->block
);
7197 switch(instr
->intrinsic
) {
7198 case nir_intrinsic_load_barycentric_sample
:
7199 case nir_intrinsic_load_barycentric_pixel
:
7200 case nir_intrinsic_load_barycentric_centroid
: {
7201 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7202 Temp bary
= Temp(0, s2
);
7204 case INTERP_MODE_SMOOTH
:
7205 case INTERP_MODE_NONE
:
7206 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7207 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7208 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7209 bary
= ctx
->persp_centroid
;
7210 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7211 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7213 case INTERP_MODE_NOPERSPECTIVE
:
7214 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7215 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7216 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7217 bary
= ctx
->linear_centroid
;
7218 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7219 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7224 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7225 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7226 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7227 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7228 Operand(p1
), Operand(p2
));
7229 emit_split_vector(ctx
, dst
, 2);
7232 case nir_intrinsic_load_barycentric_model
: {
7233 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7235 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7236 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7237 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7238 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7239 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7240 Operand(p1
), Operand(p2
), Operand(p3
));
7241 emit_split_vector(ctx
, dst
, 3);
7244 case nir_intrinsic_load_barycentric_at_sample
: {
7245 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7246 switch (ctx
->options
->key
.fs
.num_samples
) {
7247 case 2: sample_pos_offset
+= 1 << 3; break;
7248 case 4: sample_pos_offset
+= 3 << 3; break;
7249 case 8: sample_pos_offset
+= 7 << 3; break;
7253 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7254 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7255 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7256 if (addr
.type() == RegType::sgpr
) {
7259 sample_pos_offset
+= const_addr
->u32
<< 3;
7260 offset
= Operand(sample_pos_offset
);
7261 } else if (ctx
->options
->chip_class
>= GFX9
) {
7262 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7264 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7265 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7268 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7269 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7271 } else if (ctx
->options
->chip_class
>= GFX9
) {
7272 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7273 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7274 } else if (ctx
->options
->chip_class
>= GFX7
) {
7275 /* addr += private_segment_buffer + sample_pos_offset */
7276 Temp tmp0
= bld
.tmp(s1
);
7277 Temp tmp1
= bld
.tmp(s1
);
7278 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7279 Definition scc_tmp
= bld
.def(s1
, scc
);
7280 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7281 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7282 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7283 Temp pck0
= bld
.tmp(v1
);
7284 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7285 tmp1
= as_vgpr(ctx
, tmp1
);
7286 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7287 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7289 /* sample_pos = flat_load_dwordx2 addr */
7290 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7292 assert(ctx
->options
->chip_class
== GFX6
);
7294 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7295 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7296 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7298 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7299 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7301 sample_pos
= bld
.tmp(v2
);
7303 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7304 load
->definitions
[0] = Definition(sample_pos
);
7305 load
->operands
[0] = Operand(rsrc
);
7306 load
->operands
[1] = Operand(addr
);
7307 load
->operands
[2] = Operand(0u);
7308 load
->offset
= sample_pos_offset
;
7310 load
->addr64
= true;
7313 load
->disable_wqm
= false;
7314 load
->barrier
= barrier_none
;
7315 load
->can_reorder
= true;
7316 ctx
->block
->instructions
.emplace_back(std::move(load
));
7319 /* sample_pos -= 0.5 */
7320 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7321 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7322 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7323 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7324 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7326 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7329 case nir_intrinsic_load_barycentric_at_offset
: {
7330 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7331 RegClass rc
= RegClass(offset
.type(), 1);
7332 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7333 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7334 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7337 case nir_intrinsic_load_front_face
: {
7338 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7339 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7342 case nir_intrinsic_load_view_index
: {
7343 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7344 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7345 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7351 case nir_intrinsic_load_layer_id
: {
7352 unsigned idx
= nir_intrinsic_base(instr
);
7353 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7354 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7357 case nir_intrinsic_load_frag_coord
: {
7358 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7361 case nir_intrinsic_load_sample_pos
: {
7362 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7363 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7364 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7365 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7366 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7369 case nir_intrinsic_load_tess_coord
:
7370 visit_load_tess_coord(ctx
, instr
);
7372 case nir_intrinsic_load_interpolated_input
:
7373 visit_load_interpolated_input(ctx
, instr
);
7375 case nir_intrinsic_store_output
:
7376 visit_store_output(ctx
, instr
);
7378 case nir_intrinsic_load_input
:
7379 case nir_intrinsic_load_input_vertex
:
7380 visit_load_input(ctx
, instr
);
7382 case nir_intrinsic_load_output
:
7383 visit_load_output(ctx
, instr
);
7385 case nir_intrinsic_load_per_vertex_input
:
7386 visit_load_per_vertex_input(ctx
, instr
);
7388 case nir_intrinsic_load_per_vertex_output
:
7389 visit_load_per_vertex_output(ctx
, instr
);
7391 case nir_intrinsic_store_per_vertex_output
:
7392 visit_store_per_vertex_output(ctx
, instr
);
7394 case nir_intrinsic_load_ubo
:
7395 visit_load_ubo(ctx
, instr
);
7397 case nir_intrinsic_load_push_constant
:
7398 visit_load_push_constant(ctx
, instr
);
7400 case nir_intrinsic_load_constant
:
7401 visit_load_constant(ctx
, instr
);
7403 case nir_intrinsic_vulkan_resource_index
:
7404 visit_load_resource(ctx
, instr
);
7406 case nir_intrinsic_discard
:
7407 visit_discard(ctx
, instr
);
7409 case nir_intrinsic_discard_if
:
7410 visit_discard_if(ctx
, instr
);
7412 case nir_intrinsic_load_shared
:
7413 visit_load_shared(ctx
, instr
);
7415 case nir_intrinsic_store_shared
:
7416 visit_store_shared(ctx
, instr
);
7418 case nir_intrinsic_shared_atomic_add
:
7419 case nir_intrinsic_shared_atomic_imin
:
7420 case nir_intrinsic_shared_atomic_umin
:
7421 case nir_intrinsic_shared_atomic_imax
:
7422 case nir_intrinsic_shared_atomic_umax
:
7423 case nir_intrinsic_shared_atomic_and
:
7424 case nir_intrinsic_shared_atomic_or
:
7425 case nir_intrinsic_shared_atomic_xor
:
7426 case nir_intrinsic_shared_atomic_exchange
:
7427 case nir_intrinsic_shared_atomic_comp_swap
:
7428 visit_shared_atomic(ctx
, instr
);
7430 case nir_intrinsic_image_deref_load
:
7431 visit_image_load(ctx
, instr
);
7433 case nir_intrinsic_image_deref_store
:
7434 visit_image_store(ctx
, instr
);
7436 case nir_intrinsic_image_deref_atomic_add
:
7437 case nir_intrinsic_image_deref_atomic_umin
:
7438 case nir_intrinsic_image_deref_atomic_imin
:
7439 case nir_intrinsic_image_deref_atomic_umax
:
7440 case nir_intrinsic_image_deref_atomic_imax
:
7441 case nir_intrinsic_image_deref_atomic_and
:
7442 case nir_intrinsic_image_deref_atomic_or
:
7443 case nir_intrinsic_image_deref_atomic_xor
:
7444 case nir_intrinsic_image_deref_atomic_exchange
:
7445 case nir_intrinsic_image_deref_atomic_comp_swap
:
7446 visit_image_atomic(ctx
, instr
);
7448 case nir_intrinsic_image_deref_size
:
7449 visit_image_size(ctx
, instr
);
7451 case nir_intrinsic_load_ssbo
:
7452 visit_load_ssbo(ctx
, instr
);
7454 case nir_intrinsic_store_ssbo
:
7455 visit_store_ssbo(ctx
, instr
);
7457 case nir_intrinsic_load_global
:
7458 visit_load_global(ctx
, instr
);
7460 case nir_intrinsic_store_global
:
7461 visit_store_global(ctx
, instr
);
7463 case nir_intrinsic_global_atomic_add
:
7464 case nir_intrinsic_global_atomic_imin
:
7465 case nir_intrinsic_global_atomic_umin
:
7466 case nir_intrinsic_global_atomic_imax
:
7467 case nir_intrinsic_global_atomic_umax
:
7468 case nir_intrinsic_global_atomic_and
:
7469 case nir_intrinsic_global_atomic_or
:
7470 case nir_intrinsic_global_atomic_xor
:
7471 case nir_intrinsic_global_atomic_exchange
:
7472 case nir_intrinsic_global_atomic_comp_swap
:
7473 visit_global_atomic(ctx
, instr
);
7475 case nir_intrinsic_ssbo_atomic_add
:
7476 case nir_intrinsic_ssbo_atomic_imin
:
7477 case nir_intrinsic_ssbo_atomic_umin
:
7478 case nir_intrinsic_ssbo_atomic_imax
:
7479 case nir_intrinsic_ssbo_atomic_umax
:
7480 case nir_intrinsic_ssbo_atomic_and
:
7481 case nir_intrinsic_ssbo_atomic_or
:
7482 case nir_intrinsic_ssbo_atomic_xor
:
7483 case nir_intrinsic_ssbo_atomic_exchange
:
7484 case nir_intrinsic_ssbo_atomic_comp_swap
:
7485 visit_atomic_ssbo(ctx
, instr
);
7487 case nir_intrinsic_load_scratch
:
7488 visit_load_scratch(ctx
, instr
);
7490 case nir_intrinsic_store_scratch
:
7491 visit_store_scratch(ctx
, instr
);
7493 case nir_intrinsic_get_buffer_size
:
7494 visit_get_buffer_size(ctx
, instr
);
7496 case nir_intrinsic_control_barrier
: {
7497 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7498 /* GFX6 only (thanks to a hw bug workaround):
7499 * The real barrier instruction isn’t needed, because an entire patch
7500 * always fits into a single wave.
7505 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7506 bld
.sopp(aco_opcode::s_barrier
);
7510 case nir_intrinsic_memory_barrier_tcs_patch
:
7511 case nir_intrinsic_group_memory_barrier
:
7512 case nir_intrinsic_memory_barrier
:
7513 case nir_intrinsic_memory_barrier_buffer
:
7514 case nir_intrinsic_memory_barrier_image
:
7515 case nir_intrinsic_memory_barrier_shared
:
7516 emit_memory_barrier(ctx
, instr
);
7518 case nir_intrinsic_load_num_work_groups
: {
7519 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7520 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7521 emit_split_vector(ctx
, dst
, 3);
7524 case nir_intrinsic_load_local_invocation_id
: {
7525 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7526 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7527 emit_split_vector(ctx
, dst
, 3);
7530 case nir_intrinsic_load_work_group_id
: {
7531 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7532 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7533 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7534 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7535 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7536 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7537 emit_split_vector(ctx
, dst
, 3);
7540 case nir_intrinsic_load_local_invocation_index
: {
7541 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7543 /* The tg_size bits [6:11] contain the subgroup id,
7544 * we need this multiplied by the wave size, and then OR the thread id to it.
7546 if (ctx
->program
->wave_size
== 64) {
7547 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7548 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7549 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7550 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7552 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7553 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7554 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7555 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7559 case nir_intrinsic_load_subgroup_id
: {
7560 if (ctx
->stage
== compute_cs
) {
7561 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7562 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7564 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7568 case nir_intrinsic_load_subgroup_invocation
: {
7569 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7572 case nir_intrinsic_load_num_subgroups
: {
7573 if (ctx
->stage
== compute_cs
)
7574 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7575 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7577 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7580 case nir_intrinsic_ballot
: {
7581 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7582 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7583 Definition tmp
= bld
.def(dst
.regClass());
7584 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7585 if (instr
->src
[0].ssa
->bit_size
== 1) {
7586 assert(src
.regClass() == bld
.lm
);
7587 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7588 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7589 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7590 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7591 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7593 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7594 nir_print_instr(&instr
->instr
, stderr
);
7595 fprintf(stderr
, "\n");
7597 if (dst
.size() != bld
.lm
.size()) {
7598 /* Wave32 with ballot size set to 64 */
7599 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7601 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7604 case nir_intrinsic_shuffle
:
7605 case nir_intrinsic_read_invocation
: {
7606 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7607 if (!nir_src_is_divergent(instr
->src
[0])) {
7608 emit_uniform_subgroup(ctx
, instr
, src
);
7610 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7611 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7612 tid
= bld
.as_uniform(tid
);
7613 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7614 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7615 Temp tmp
= bld
.tmp(v1
);
7616 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7617 if (dst
.type() == RegType::vgpr
)
7618 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7620 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7621 } else if (src
.regClass() == v1
) {
7622 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7623 } else if (src
.regClass() == v2
) {
7624 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7625 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7626 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7627 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7628 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7629 emit_split_vector(ctx
, dst
, 2);
7630 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7631 assert(src
.regClass() == bld
.lm
);
7632 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7633 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7634 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7635 assert(src
.regClass() == bld
.lm
);
7637 if (ctx
->program
->chip_class
<= GFX7
)
7638 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7639 else if (ctx
->program
->wave_size
== 64)
7640 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7642 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7643 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7644 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7645 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7647 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7648 nir_print_instr(&instr
->instr
, stderr
);
7649 fprintf(stderr
, "\n");
7654 case nir_intrinsic_load_sample_id
: {
7655 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7656 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7659 case nir_intrinsic_load_sample_mask_in
: {
7660 visit_load_sample_mask_in(ctx
, instr
);
7663 case nir_intrinsic_read_first_invocation
: {
7664 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7665 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7666 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7668 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7670 } else if (src
.regClass() == v2
) {
7671 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7672 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7673 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7674 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7675 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7676 emit_split_vector(ctx
, dst
, 2);
7677 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7678 assert(src
.regClass() == bld
.lm
);
7679 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7680 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7681 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7682 } else if (src
.regClass() == s1
) {
7683 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7684 } else if (src
.regClass() == s2
) {
7685 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7687 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7688 nir_print_instr(&instr
->instr
, stderr
);
7689 fprintf(stderr
, "\n");
7693 case nir_intrinsic_vote_all
: {
7694 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7695 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7696 assert(src
.regClass() == bld
.lm
);
7697 assert(dst
.regClass() == bld
.lm
);
7699 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7700 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7701 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7704 case nir_intrinsic_vote_any
: {
7705 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7706 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7707 assert(src
.regClass() == bld
.lm
);
7708 assert(dst
.regClass() == bld
.lm
);
7710 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7711 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7714 case nir_intrinsic_reduce
:
7715 case nir_intrinsic_inclusive_scan
:
7716 case nir_intrinsic_exclusive_scan
: {
7717 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7718 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7719 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7720 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7721 nir_intrinsic_cluster_size(instr
) : 0;
7722 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7724 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7725 emit_uniform_subgroup(ctx
, instr
, src
);
7726 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7727 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7729 else if (op
== nir_op_iadd
)
7731 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7733 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7735 switch (instr
->intrinsic
) {
7736 case nir_intrinsic_reduce
:
7737 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7739 case nir_intrinsic_exclusive_scan
:
7740 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7742 case nir_intrinsic_inclusive_scan
:
7743 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7748 } else if (cluster_size
== 1) {
7749 bld
.copy(Definition(dst
), src
);
7751 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7753 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7757 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7758 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7773 unreachable("unknown reduction op");
7779 switch (instr
->intrinsic
) {
7780 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7781 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7782 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7784 unreachable("unknown reduce intrinsic");
7787 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7788 reduce
->operands
[0] = Operand(src
);
7789 // filled in by aco_reduce_assign.cpp, used internally as part of the
7791 assert(dst
.size() == 1 || dst
.size() == 2);
7792 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7793 reduce
->operands
[2] = Operand(v1
.as_linear());
7795 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7796 reduce
->definitions
[0] = Definition(tmp_dst
);
7797 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7798 reduce
->definitions
[2] = Definition();
7799 reduce
->definitions
[3] = Definition(scc
, s1
);
7800 reduce
->definitions
[4] = Definition();
7801 reduce
->reduce_op
= reduce_op
;
7802 reduce
->cluster_size
= cluster_size
;
7803 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7805 emit_wqm(ctx
, tmp_dst
, dst
);
7809 case nir_intrinsic_quad_broadcast
: {
7810 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7811 if (!nir_dest_is_divergent(instr
->dest
)) {
7812 emit_uniform_subgroup(ctx
, instr
, src
);
7814 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7815 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7816 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7818 if (instr
->dest
.ssa
.bit_size
== 1) {
7819 assert(src
.regClass() == bld
.lm
);
7820 assert(dst
.regClass() == bld
.lm
);
7821 uint32_t half_mask
= 0x11111111u
<< lane
;
7822 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7823 Temp tmp
= bld
.tmp(bld
.lm
);
7824 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7825 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7826 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7827 emit_wqm(ctx
, tmp
, dst
);
7828 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7829 Temp tmp
= bld
.tmp(v1
);
7830 if (ctx
->program
->chip_class
>= GFX8
)
7831 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7833 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7834 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7835 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7836 Temp tmp
= bld
.tmp(v1
);
7837 if (ctx
->program
->chip_class
>= GFX8
)
7838 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7840 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7841 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7842 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7843 if (ctx
->program
->chip_class
>= GFX8
)
7844 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7846 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7847 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7848 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7849 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7850 if (ctx
->program
->chip_class
>= GFX8
) {
7851 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7852 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7854 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7855 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7857 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7858 emit_split_vector(ctx
, dst
, 2);
7860 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7861 nir_print_instr(&instr
->instr
, stderr
);
7862 fprintf(stderr
, "\n");
7867 case nir_intrinsic_quad_swap_horizontal
:
7868 case nir_intrinsic_quad_swap_vertical
:
7869 case nir_intrinsic_quad_swap_diagonal
:
7870 case nir_intrinsic_quad_swizzle_amd
: {
7871 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7872 if (!nir_dest_is_divergent(instr
->dest
)) {
7873 emit_uniform_subgroup(ctx
, instr
, src
);
7876 uint16_t dpp_ctrl
= 0;
7877 switch (instr
->intrinsic
) {
7878 case nir_intrinsic_quad_swap_horizontal
:
7879 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7881 case nir_intrinsic_quad_swap_vertical
:
7882 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7884 case nir_intrinsic_quad_swap_diagonal
:
7885 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7887 case nir_intrinsic_quad_swizzle_amd
:
7888 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7893 if (ctx
->program
->chip_class
< GFX8
)
7894 dpp_ctrl
|= (1 << 15);
7896 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7897 if (instr
->dest
.ssa
.bit_size
== 1) {
7898 assert(src
.regClass() == bld
.lm
);
7899 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7900 if (ctx
->program
->chip_class
>= GFX8
)
7901 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7903 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7904 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7905 emit_wqm(ctx
, tmp
, dst
);
7906 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7907 Temp tmp
= bld
.tmp(v1
);
7908 if (ctx
->program
->chip_class
>= GFX8
)
7909 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7911 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7912 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7913 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7914 Temp tmp
= bld
.tmp(v1
);
7915 if (ctx
->program
->chip_class
>= GFX8
)
7916 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7918 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7919 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7920 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7922 if (ctx
->program
->chip_class
>= GFX8
)
7923 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7925 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7926 emit_wqm(ctx
, tmp
, dst
);
7927 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7928 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7929 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7930 if (ctx
->program
->chip_class
>= GFX8
) {
7931 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7932 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7934 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7935 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7937 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7938 emit_split_vector(ctx
, dst
, 2);
7940 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7941 nir_print_instr(&instr
->instr
, stderr
);
7942 fprintf(stderr
, "\n");
7946 case nir_intrinsic_masked_swizzle_amd
: {
7947 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7948 if (!nir_dest_is_divergent(instr
->dest
)) {
7949 emit_uniform_subgroup(ctx
, instr
, src
);
7952 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7953 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7954 if (dst
.regClass() == v1
) {
7956 emit_masked_swizzle(ctx
, bld
, src
, mask
),
7958 } else if (dst
.regClass() == v2
) {
7959 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7960 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7961 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7962 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7963 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7964 emit_split_vector(ctx
, dst
, 2);
7966 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7967 nir_print_instr(&instr
->instr
, stderr
);
7968 fprintf(stderr
, "\n");
7972 case nir_intrinsic_write_invocation_amd
: {
7973 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7974 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7975 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7977 if (dst
.regClass() == v1
) {
7978 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7979 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7980 } else if (dst
.regClass() == v2
) {
7981 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7982 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7983 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7984 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7985 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7986 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7987 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7988 emit_split_vector(ctx
, dst
, 2);
7990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7991 nir_print_instr(&instr
->instr
, stderr
);
7992 fprintf(stderr
, "\n");
7996 case nir_intrinsic_mbcnt_amd
: {
7997 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7998 RegClass rc
= RegClass(src
.type(), 1);
7999 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8000 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8001 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8002 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8003 emit_wqm(ctx
, wqm_tmp
, dst
);
8006 case nir_intrinsic_load_helper_invocation
: {
8007 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8008 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8009 ctx
->block
->kind
|= block_kind_needs_lowering
;
8010 ctx
->program
->needs_exact
= true;
8013 case nir_intrinsic_is_helper_invocation
: {
8014 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8015 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8016 ctx
->block
->kind
|= block_kind_needs_lowering
;
8017 ctx
->program
->needs_exact
= true;
8020 case nir_intrinsic_demote
:
8021 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8023 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8024 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8025 ctx
->block
->kind
|= block_kind_uses_demote
;
8026 ctx
->program
->needs_exact
= true;
8028 case nir_intrinsic_demote_if
: {
8029 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8030 assert(src
.regClass() == bld
.lm
);
8031 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8032 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8034 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8035 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8036 ctx
->block
->kind
|= block_kind_uses_demote
;
8037 ctx
->program
->needs_exact
= true;
8040 case nir_intrinsic_first_invocation
: {
8041 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8042 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8045 case nir_intrinsic_shader_clock
: {
8047 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8048 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8049 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8050 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8053 case nir_intrinsic_load_vertex_id_zero_base
: {
8054 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8055 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8058 case nir_intrinsic_load_first_vertex
: {
8059 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8060 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8063 case nir_intrinsic_load_base_instance
: {
8064 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8065 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8068 case nir_intrinsic_load_instance_id
: {
8069 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8070 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8073 case nir_intrinsic_load_draw_id
: {
8074 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8075 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8078 case nir_intrinsic_load_invocation_id
: {
8079 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8081 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8082 if (ctx
->options
->chip_class
>= GFX10
)
8083 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8085 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8086 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8087 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8088 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8090 unreachable("Unsupported stage for load_invocation_id");
8095 case nir_intrinsic_load_primitive_id
: {
8096 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8098 switch (ctx
->shader
->info
.stage
) {
8099 case MESA_SHADER_GEOMETRY
:
8100 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8102 case MESA_SHADER_TESS_CTRL
:
8103 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8105 case MESA_SHADER_TESS_EVAL
:
8106 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8109 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8114 case nir_intrinsic_load_patch_vertices_in
: {
8115 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8116 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8118 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8119 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8122 case nir_intrinsic_emit_vertex_with_counter
: {
8123 visit_emit_vertex_with_counter(ctx
, instr
);
8126 case nir_intrinsic_end_primitive_with_counter
: {
8127 unsigned stream
= nir_intrinsic_stream_id(instr
);
8128 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8131 case nir_intrinsic_set_vertex_count
: {
8132 /* unused, the HW keeps track of this for us */
8136 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8137 nir_print_instr(&instr
->instr
, stderr
);
8138 fprintf(stderr
, "\n");
8146 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8147 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8148 enum glsl_base_type
*stype
)
8150 nir_deref_instr
*texture_deref_instr
= NULL
;
8151 nir_deref_instr
*sampler_deref_instr
= NULL
;
8154 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8155 switch (instr
->src
[i
].src_type
) {
8156 case nir_tex_src_texture_deref
:
8157 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8159 case nir_tex_src_sampler_deref
:
8160 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8162 case nir_tex_src_plane
:
8163 plane
= nir_src_as_int(instr
->src
[i
].src
);
8170 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8172 if (!sampler_deref_instr
)
8173 sampler_deref_instr
= texture_deref_instr
;
8176 assert(instr
->op
!= nir_texop_txf_ms
&&
8177 instr
->op
!= nir_texop_samples_identical
);
8178 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8179 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8180 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8181 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8182 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8183 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8185 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8188 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8190 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8191 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8192 Builder
bld(ctx
->program
, ctx
->block
);
8194 /* to avoid unnecessary moves, we split and recombine sampler and image */
8195 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8196 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8197 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8198 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8199 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8200 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8202 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8204 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8205 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8206 img
[0], img
[1], img
[2], img
[3],
8207 img
[4], img
[5], img
[6], img
[7]);
8208 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8209 samp
[0], samp
[1], samp
[2], samp
[3]);
8212 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8213 instr
->op
== nir_texop_samples_identical
))
8214 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8217 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8218 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8220 Builder
bld(ctx
->program
, ctx
->block
);
8222 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8223 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8224 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8226 Operand
neg_one(0xbf800000u
);
8227 Operand
one(0x3f800000u
);
8228 Operand
two(0x40000000u
);
8229 Operand
four(0x40800000u
);
8231 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8232 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8233 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8235 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8236 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8237 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8238 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8241 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8242 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8243 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8245 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8248 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8249 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8250 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8253 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8254 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8256 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8257 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8260 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8262 Builder
bld(ctx
->program
, ctx
->block
);
8263 Temp ma
, tc
, sc
, id
;
8266 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8268 // see comment in ac_prepare_cube_coords()
8269 if (ctx
->options
->chip_class
<= GFX8
)
8270 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8273 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8275 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8276 vop3a
->operands
[0] = Operand(ma
);
8277 vop3a
->abs
[0] = true;
8278 Temp invma
= bld
.tmp(v1
);
8279 vop3a
->definitions
[0] = Definition(invma
);
8280 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8282 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8284 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8286 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8288 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8290 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8293 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8294 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8296 for (unsigned i
= 0; i
< 2; i
++) {
8297 // see comment in ac_prepare_cube_coords()
8299 Temp deriv_sc
, deriv_tc
;
8300 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8301 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8303 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8305 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8306 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8307 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8308 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8309 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8310 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8311 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8314 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8315 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8319 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8326 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8328 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8330 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8331 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8334 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8335 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8336 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8340 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8342 Builder
bld(ctx
->program
, ctx
->block
);
8343 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8344 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8345 has_clamped_lod
= false;
8346 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8347 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8348 clamped_lod
= Temp();
8349 std::vector
<Temp
> coords
;
8350 std::vector
<Temp
> derivs
;
8351 nir_const_value
*sample_index_cv
= NULL
;
8352 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8353 enum glsl_base_type stype
;
8354 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8356 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8357 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8358 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8359 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8361 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8362 switch (instr
->src
[i
].src_type
) {
8363 case nir_tex_src_coord
: {
8364 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8365 for (unsigned i
= 0; i
< coord
.size(); i
++)
8366 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8369 case nir_tex_src_bias
:
8370 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8373 case nir_tex_src_lod
: {
8374 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8376 if (val
&& val
->f32
<= 0.0) {
8379 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8384 case nir_tex_src_min_lod
:
8385 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8386 has_clamped_lod
= true;
8388 case nir_tex_src_comparator
:
8389 if (instr
->is_shadow
) {
8390 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8394 case nir_tex_src_offset
:
8395 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8396 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8399 case nir_tex_src_ddx
:
8400 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8403 case nir_tex_src_ddy
:
8404 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8407 case nir_tex_src_ms_index
:
8408 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8409 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8410 has_sample_index
= true;
8412 case nir_tex_src_texture_offset
:
8413 case nir_tex_src_sampler_offset
:
8419 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8420 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8422 if (instr
->op
== nir_texop_texture_samples
) {
8423 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8425 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8426 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8427 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8429 Operand default_sample
= Operand(1u);
8430 if (ctx
->options
->robust_buffer_access
) {
8431 /* Extract the second dword of the descriptor, if it's
8432 * all zero, then it's a null descriptor.
8434 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8435 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8436 default_sample
= Operand(is_non_null_descriptor
);
8439 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8440 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8441 samples
, default_sample
, bld
.scc(is_msaa
));
8445 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8446 aco_ptr
<Instruction
> tmp_instr
;
8447 Temp acc
, pack
= Temp();
8449 uint32_t pack_const
= 0;
8450 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8451 if (!const_offset
[i
])
8453 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8456 if (offset
.type() == RegType::sgpr
) {
8457 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8458 if (const_offset
[i
])
8461 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8462 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8465 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8468 if (pack
== Temp()) {
8471 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8475 if (pack_const
&& pack
!= Temp())
8476 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8478 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8479 if (const_offset
[i
])
8482 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8483 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8486 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8489 if (pack
== Temp()) {
8492 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8496 if (pack_const
&& pack
!= Temp())
8497 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8499 if (pack_const
&& pack
== Temp())
8500 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8501 else if (pack
== Temp())
8507 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8508 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8510 /* pack derivatives */
8511 if (has_ddx
|| has_ddy
) {
8512 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8513 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8514 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8515 derivs
= {ddx
, zero
, ddy
, zero
};
8517 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8518 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8519 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8520 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8525 if (instr
->coord_components
> 1 &&
8526 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8528 instr
->op
!= nir_texop_txf
)
8529 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8531 if (instr
->coord_components
> 2 &&
8532 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8533 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8534 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8535 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8537 instr
->op
!= nir_texop_txf
&&
8538 instr
->op
!= nir_texop_txf_ms
&&
8539 instr
->op
!= nir_texop_fragment_fetch
&&
8540 instr
->op
!= nir_texop_fragment_mask_fetch
)
8541 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8543 if (ctx
->options
->chip_class
== GFX9
&&
8544 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8545 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8546 assert(coords
.size() > 0 && coords
.size() < 3);
8548 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8549 Operand((uint32_t) 0) :
8550 Operand((uint32_t) 0x3f000000)));
8553 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8555 if (instr
->op
== nir_texop_samples_identical
)
8556 resource
= fmask_ptr
;
8558 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8559 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8560 instr
->op
!= nir_texop_txs
&&
8561 instr
->op
!= nir_texop_fragment_fetch
&&
8562 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8563 assert(has_sample_index
);
8564 Operand
op(sample_index
);
8565 if (sample_index_cv
)
8566 op
= Operand(sample_index_cv
->u32
);
8567 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8570 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8571 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8572 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8573 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8578 /* Build tex instruction */
8579 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8580 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8581 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8583 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8586 /* gather4 selects the component by dmask and always returns vec4 */
8587 if (instr
->op
== nir_texop_tg4
) {
8588 assert(instr
->dest
.ssa
.num_components
== 4);
8589 if (instr
->is_shadow
)
8592 dmask
= 1 << instr
->component
;
8593 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8594 tmp_dst
= bld
.tmp(v4
);
8595 } else if (instr
->op
== nir_texop_samples_identical
) {
8596 tmp_dst
= bld
.tmp(v1
);
8597 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8598 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8601 aco_ptr
<MIMG_instruction
> tex
;
8602 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8604 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8606 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8607 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8610 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8611 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8613 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8614 tex
->operands
[0] = Operand(resource
);
8615 tex
->operands
[1] = Operand(s4
); /* no sampler */
8616 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8617 if (ctx
->options
->chip_class
== GFX9
&&
8618 instr
->op
== nir_texop_txs
&&
8619 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8621 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8622 } else if (instr
->op
== nir_texop_query_levels
) {
8623 tex
->dmask
= 1 << 3;
8628 tex
->definitions
[0] = Definition(tmp_dst
);
8630 tex
->can_reorder
= true;
8631 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8634 /* divide 3rd value by 6 by multiplying with magic number */
8635 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8636 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8637 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8638 assert(instr
->dest
.ssa
.num_components
== 3);
8639 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8640 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8641 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8642 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8647 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8651 Temp tg4_compare_cube_wa64
= Temp();
8653 if (tg4_integer_workarounds
) {
8654 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8655 tex
->operands
[0] = Operand(resource
);
8656 tex
->operands
[1] = Operand(s4
); /* no sampler */
8657 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8661 Temp size
= bld
.tmp(v2
);
8662 tex
->definitions
[0] = Definition(size
);
8663 tex
->can_reorder
= true;
8664 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8665 emit_split_vector(ctx
, size
, size
.size());
8668 for (unsigned i
= 0; i
< 2; i
++) {
8669 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8670 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8671 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8672 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8675 Temp new_coords
[2] = {
8676 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8677 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8680 if (tg4_integer_cube_workaround
) {
8681 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8682 Temp desc
[resource
.size()];
8683 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8684 Format::PSEUDO
, 1, resource
.size())};
8685 split
->operands
[0] = Operand(resource
);
8686 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8687 desc
[i
] = bld
.tmp(s1
);
8688 split
->definitions
[i
] = Definition(desc
[i
]);
8690 ctx
->block
->instructions
.emplace_back(std::move(split
));
8692 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8693 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8694 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8697 if (stype
== GLSL_TYPE_UINT
) {
8698 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8699 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8700 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8701 bld
.scc(compare_cube_wa
));
8703 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8704 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8705 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8706 bld
.scc(compare_cube_wa
));
8708 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8709 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8711 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8713 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8714 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8715 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8717 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8718 Format::PSEUDO
, resource
.size(), 1)};
8719 for (unsigned i
= 0; i
< resource
.size(); i
++)
8720 vec
->operands
[i
] = Operand(desc
[i
]);
8721 resource
= bld
.tmp(resource
.regClass());
8722 vec
->definitions
[0] = Definition(resource
);
8723 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8725 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8726 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8727 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8728 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8730 coords
[0] = new_coords
[0];
8731 coords
[1] = new_coords
[1];
8734 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8735 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8737 assert(coords
.size() == 1);
8738 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8742 op
= aco_opcode::buffer_load_format_x
; break;
8744 op
= aco_opcode::buffer_load_format_xy
; break;
8746 op
= aco_opcode::buffer_load_format_xyz
; break;
8748 op
= aco_opcode::buffer_load_format_xyzw
; break;
8750 unreachable("Tex instruction loads more than 4 components.");
8753 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8754 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8757 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8759 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8760 mubuf
->operands
[0] = Operand(resource
);
8761 mubuf
->operands
[1] = Operand(coords
[0]);
8762 mubuf
->operands
[2] = Operand((uint32_t) 0);
8763 mubuf
->definitions
[0] = Definition(tmp_dst
);
8764 mubuf
->idxen
= true;
8765 mubuf
->can_reorder
= true;
8766 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8768 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8772 /* gather MIMG address components */
8773 std::vector
<Temp
> args
;
8775 args
.emplace_back(offset
);
8777 args
.emplace_back(bias
);
8779 args
.emplace_back(compare
);
8781 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8783 args
.insert(args
.end(), coords
.begin(), coords
.end());
8784 if (has_sample_index
)
8785 args
.emplace_back(sample_index
);
8787 args
.emplace_back(lod
);
8788 if (has_clamped_lod
)
8789 args
.emplace_back(clamped_lod
);
8791 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8792 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8793 vec
->definitions
[0] = Definition(arg
);
8794 for (unsigned i
= 0; i
< args
.size(); i
++)
8795 vec
->operands
[i
] = Operand(args
[i
]);
8796 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8799 if (instr
->op
== nir_texop_txf
||
8800 instr
->op
== nir_texop_txf_ms
||
8801 instr
->op
== nir_texop_samples_identical
||
8802 instr
->op
== nir_texop_fragment_fetch
||
8803 instr
->op
== nir_texop_fragment_mask_fetch
) {
8804 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8805 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8806 tex
->operands
[0] = Operand(resource
);
8807 tex
->operands
[1] = Operand(s4
); /* no sampler */
8808 tex
->operands
[2] = Operand(arg
);
8813 tex
->definitions
[0] = Definition(tmp_dst
);
8814 tex
->can_reorder
= true;
8815 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8817 if (instr
->op
== nir_texop_samples_identical
) {
8818 assert(dmask
== 1 && dst
.regClass() == v1
);
8819 assert(dst
.id() != tmp_dst
.id());
8821 Temp tmp
= bld
.tmp(bld
.lm
);
8822 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8823 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8826 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8831 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8832 aco_opcode opcode
= aco_opcode::image_sample
;
8833 if (has_offset
) { /* image_sample_*_o */
8834 if (has_clamped_lod
) {
8836 opcode
= aco_opcode::image_sample_c_cl_o
;
8838 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8840 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8842 opcode
= aco_opcode::image_sample_cl_o
;
8844 opcode
= aco_opcode::image_sample_d_cl_o
;
8846 opcode
= aco_opcode::image_sample_b_cl_o
;
8848 } else if (has_compare
) {
8849 opcode
= aco_opcode::image_sample_c_o
;
8851 opcode
= aco_opcode::image_sample_c_d_o
;
8853 opcode
= aco_opcode::image_sample_c_b_o
;
8855 opcode
= aco_opcode::image_sample_c_lz_o
;
8857 opcode
= aco_opcode::image_sample_c_l_o
;
8859 opcode
= aco_opcode::image_sample_o
;
8861 opcode
= aco_opcode::image_sample_d_o
;
8863 opcode
= aco_opcode::image_sample_b_o
;
8865 opcode
= aco_opcode::image_sample_lz_o
;
8867 opcode
= aco_opcode::image_sample_l_o
;
8869 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8871 opcode
= aco_opcode::image_sample_c_cl
;
8873 opcode
= aco_opcode::image_sample_c_d_cl
;
8875 opcode
= aco_opcode::image_sample_c_b_cl
;
8877 opcode
= aco_opcode::image_sample_cl
;
8879 opcode
= aco_opcode::image_sample_d_cl
;
8881 opcode
= aco_opcode::image_sample_b_cl
;
8883 } else { /* no offset */
8885 opcode
= aco_opcode::image_sample_c
;
8887 opcode
= aco_opcode::image_sample_c_d
;
8889 opcode
= aco_opcode::image_sample_c_b
;
8891 opcode
= aco_opcode::image_sample_c_lz
;
8893 opcode
= aco_opcode::image_sample_c_l
;
8895 opcode
= aco_opcode::image_sample
;
8897 opcode
= aco_opcode::image_sample_d
;
8899 opcode
= aco_opcode::image_sample_b
;
8901 opcode
= aco_opcode::image_sample_lz
;
8903 opcode
= aco_opcode::image_sample_l
;
8907 if (instr
->op
== nir_texop_tg4
) {
8908 if (has_offset
) { /* image_gather4_*_o */
8910 opcode
= aco_opcode::image_gather4_c_lz_o
;
8912 opcode
= aco_opcode::image_gather4_c_l_o
;
8914 opcode
= aco_opcode::image_gather4_c_b_o
;
8916 opcode
= aco_opcode::image_gather4_lz_o
;
8918 opcode
= aco_opcode::image_gather4_l_o
;
8920 opcode
= aco_opcode::image_gather4_b_o
;
8924 opcode
= aco_opcode::image_gather4_c_lz
;
8926 opcode
= aco_opcode::image_gather4_c_l
;
8928 opcode
= aco_opcode::image_gather4_c_b
;
8930 opcode
= aco_opcode::image_gather4_lz
;
8932 opcode
= aco_opcode::image_gather4_l
;
8934 opcode
= aco_opcode::image_gather4_b
;
8937 } else if (instr
->op
== nir_texop_lod
) {
8938 opcode
= aco_opcode::image_get_lod
;
8941 /* we don't need the bias, sample index, compare value or offset to be
8942 * computed in WQM but if the p_create_vector copies the coordinates, then it
8943 * needs to be in WQM */
8944 if (ctx
->stage
== fragment_fs
&&
8945 !has_derivs
&& !has_lod
&& !level_zero
&&
8946 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8947 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8948 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8950 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8951 tex
->operands
[0] = Operand(resource
);
8952 tex
->operands
[1] = Operand(sampler
);
8953 tex
->operands
[2] = Operand(arg
);
8957 tex
->definitions
[0] = Definition(tmp_dst
);
8958 tex
->can_reorder
= true;
8959 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8961 if (tg4_integer_cube_workaround
) {
8962 assert(tmp_dst
.id() != dst
.id());
8963 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8965 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8967 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8968 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8970 if (stype
== GLSL_TYPE_UINT
)
8971 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8973 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8974 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8976 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8977 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8978 val
[0], val
[1], val
[2], val
[3]);
8980 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8981 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8986 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8988 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8989 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8991 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8992 if (ctx
->program
->wave_size
== 64)
8993 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8995 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8997 return Operand(tmp
);
9001 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9003 aco_ptr
<Pseudo_instruction
> phi
;
9004 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9005 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9007 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
9008 logical
|= ctx
->block
->kind
& block_kind_merge
;
9009 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9011 /* we want a sorted list of sources, since the predecessor list is also sorted */
9012 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9013 nir_foreach_phi_src(src
, instr
)
9014 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9016 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9017 unsigned num_operands
= 0;
9018 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9019 unsigned num_defined
= 0;
9020 unsigned cur_pred_idx
= 0;
9021 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9022 if (cur_pred_idx
< preds
.size()) {
9023 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9024 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9025 unsigned skipped
= 0;
9026 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9028 if (cur_pred_idx
+ skipped
< preds
.size()) {
9029 for (unsigned i
= 0; i
< skipped
; i
++)
9030 operands
[num_operands
++] = Operand(dst
.regClass());
9031 cur_pred_idx
+= skipped
;
9036 /* Handle missing predecessors at the end. This shouldn't happen with loop
9037 * headers and we can't ignore these sources for loop header phis. */
9038 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9041 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9042 operands
[num_operands
++] = op
;
9043 num_defined
+= !op
.isUndefined();
9045 /* handle block_kind_continue_or_break at loop exit blocks */
9046 while (cur_pred_idx
++ < preds
.size())
9047 operands
[num_operands
++] = Operand(dst
.regClass());
9049 /* If the loop ends with a break, still add a linear continue edge in case
9050 * that break is divergent or continue_or_break is used. We'll either remove
9051 * this operand later in visit_loop() if it's not necessary or replace the
9052 * undef with something correct. */
9053 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9054 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9055 nir_block
*last
= nir_loop_last_block(loop
);
9056 if (last
->successors
[0] != instr
->instr
.block
)
9057 operands
[num_operands
++] = Operand(RegClass());
9060 if (num_defined
== 0) {
9061 Builder
bld(ctx
->program
, ctx
->block
);
9062 if (dst
.regClass() == s1
) {
9063 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9064 } else if (dst
.regClass() == v1
) {
9065 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9067 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9068 for (unsigned i
= 0; i
< dst
.size(); i
++)
9069 vec
->operands
[i
] = Operand(0u);
9070 vec
->definitions
[0] = Definition(dst
);
9071 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9076 /* we can use a linear phi in some cases if one src is undef */
9077 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9078 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9080 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9081 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9082 assert(invert
->kind
& block_kind_invert
);
9084 unsigned then_block
= invert
->linear_preds
[0];
9086 Block
* insert_block
= NULL
;
9087 for (unsigned i
= 0; i
< num_operands
; i
++) {
9088 Operand op
= operands
[i
];
9089 if (op
.isUndefined())
9091 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9092 phi
->operands
[0] = op
;
9095 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9096 phi
->operands
[1] = Operand(dst
.regClass());
9097 phi
->definitions
[0] = Definition(dst
);
9098 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9102 /* try to scalarize vector phis */
9103 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9104 // TODO: scalarize linear phis on divergent ifs
9105 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9106 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9107 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9108 Operand src
= operands
[i
];
9109 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9110 can_scalarize
= false;
9112 if (can_scalarize
) {
9113 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9114 assert(dst
.size() % num_components
== 0);
9115 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9117 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9118 for (unsigned k
= 0; k
< num_components
; k
++) {
9119 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9120 for (unsigned i
= 0; i
< num_operands
; i
++) {
9121 Operand src
= operands
[i
];
9122 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9124 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9125 phi
->definitions
[0] = Definition(phi_dst
);
9126 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9127 new_vec
[k
] = phi_dst
;
9128 vec
->operands
[k
] = Operand(phi_dst
);
9130 vec
->definitions
[0] = Definition(dst
);
9131 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9132 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9137 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9138 for (unsigned i
= 0; i
< num_operands
; i
++)
9139 phi
->operands
[i
] = operands
[i
];
9140 phi
->definitions
[0] = Definition(dst
);
9141 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9145 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9147 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9149 assert(dst
.type() == RegType::sgpr
);
9151 if (dst
.size() == 1) {
9152 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9154 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9155 for (unsigned i
= 0; i
< dst
.size(); i
++)
9156 vec
->operands
[i
] = Operand(0u);
9157 vec
->definitions
[0] = Definition(dst
);
9158 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9162 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9164 Builder
bld(ctx
->program
, ctx
->block
);
9165 Block
*logical_target
;
9166 append_logical_end(ctx
->block
);
9167 unsigned idx
= ctx
->block
->index
;
9169 switch (instr
->type
) {
9170 case nir_jump_break
:
9171 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9172 add_logical_edge(idx
, logical_target
);
9173 ctx
->block
->kind
|= block_kind_break
;
9175 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9176 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9177 /* uniform break - directly jump out of the loop */
9178 ctx
->block
->kind
|= block_kind_uniform
;
9179 ctx
->cf_info
.has_branch
= true;
9180 bld
.branch(aco_opcode::p_branch
);
9181 add_linear_edge(idx
, logical_target
);
9184 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9185 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9187 case nir_jump_continue
:
9188 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9189 add_logical_edge(idx
, logical_target
);
9190 ctx
->block
->kind
|= block_kind_continue
;
9192 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9193 /* for potential uniform breaks after this continue,
9194 we must ensure that they are handled correctly */
9195 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9196 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9197 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9199 /* uniform continue - directly jump to the loop header */
9200 ctx
->block
->kind
|= block_kind_uniform
;
9201 ctx
->cf_info
.has_branch
= true;
9202 bld
.branch(aco_opcode::p_branch
);
9203 add_linear_edge(idx
, logical_target
);
9208 fprintf(stderr
, "Unknown NIR jump instr: ");
9209 nir_print_instr(&instr
->instr
, stderr
);
9210 fprintf(stderr
, "\n");
9214 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9215 ctx
->cf_info
.exec_potentially_empty_break
= true;
9216 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9219 /* remove critical edges from linear CFG */
9220 bld
.branch(aco_opcode::p_branch
);
9221 Block
* break_block
= ctx
->program
->create_and_insert_block();
9222 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9223 break_block
->kind
|= block_kind_uniform
;
9224 add_linear_edge(idx
, break_block
);
9225 /* the loop_header pointer might be invalidated by this point */
9226 if (instr
->type
== nir_jump_continue
)
9227 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9228 add_linear_edge(break_block
->index
, logical_target
);
9229 bld
.reset(break_block
);
9230 bld
.branch(aco_opcode::p_branch
);
9232 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9233 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9234 add_linear_edge(idx
, continue_block
);
9235 append_logical_start(continue_block
);
9236 ctx
->block
= continue_block
;
9240 void visit_block(isel_context
*ctx
, nir_block
*block
)
9242 nir_foreach_instr(instr
, block
) {
9243 switch (instr
->type
) {
9244 case nir_instr_type_alu
:
9245 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9247 case nir_instr_type_load_const
:
9248 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9250 case nir_instr_type_intrinsic
:
9251 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9253 case nir_instr_type_tex
:
9254 visit_tex(ctx
, nir_instr_as_tex(instr
));
9256 case nir_instr_type_phi
:
9257 visit_phi(ctx
, nir_instr_as_phi(instr
));
9259 case nir_instr_type_ssa_undef
:
9260 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9262 case nir_instr_type_deref
:
9264 case nir_instr_type_jump
:
9265 visit_jump(ctx
, nir_instr_as_jump(instr
));
9268 fprintf(stderr
, "Unknown NIR instr type: ");
9269 nir_print_instr(instr
, stderr
);
9270 fprintf(stderr
, "\n");
9275 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9276 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9281 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9282 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9284 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9285 RegClass rc
= vals
[0].regClass();
9287 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9289 unsigned next_pred
= 1;
9291 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9292 Block
& block
= ctx
->program
->blocks
[idx
];
9293 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9294 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9298 if (block
.kind
& block_kind_continue
) {
9299 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9304 bool all_same
= true;
9305 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9306 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9310 val
= vals
[block
.linear_preds
[0] - first
];
9312 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9313 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9314 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9315 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9316 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9317 phi
->definitions
[0] = Definition(val
.getTemp());
9318 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9320 vals
[idx
- first
] = val
;
9323 return vals
[last
- first
];
9326 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9328 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9329 append_logical_end(ctx
->block
);
9330 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9331 Builder
bld(ctx
->program
, ctx
->block
);
9332 bld
.branch(aco_opcode::p_branch
);
9333 unsigned loop_preheader_idx
= ctx
->block
->index
;
9335 Block loop_exit
= Block();
9336 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9337 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9339 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9340 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9341 loop_header
->kind
|= block_kind_loop_header
;
9342 add_edge(loop_preheader_idx
, loop_header
);
9343 ctx
->block
= loop_header
;
9345 /* emit loop body */
9346 unsigned loop_header_idx
= loop_header
->index
;
9347 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9348 append_logical_start(ctx
->block
);
9349 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9351 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9352 if (!ctx
->cf_info
.has_branch
) {
9353 append_logical_end(ctx
->block
);
9354 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9355 /* Discards can result in code running with an empty exec mask.
9356 * This would result in divergent breaks not ever being taken. As a
9357 * workaround, break the loop when the loop mask is empty instead of
9358 * always continuing. */
9359 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9360 unsigned block_idx
= ctx
->block
->index
;
9362 /* create helper blocks to avoid critical edges */
9363 Block
*break_block
= ctx
->program
->create_and_insert_block();
9364 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9365 break_block
->kind
= block_kind_uniform
;
9366 bld
.reset(break_block
);
9367 bld
.branch(aco_opcode::p_branch
);
9368 add_linear_edge(block_idx
, break_block
);
9369 add_linear_edge(break_block
->index
, &loop_exit
);
9371 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9372 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9373 continue_block
->kind
= block_kind_uniform
;
9374 bld
.reset(continue_block
);
9375 bld
.branch(aco_opcode::p_branch
);
9376 add_linear_edge(block_idx
, continue_block
);
9377 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9379 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9380 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9381 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9383 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9384 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9385 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9387 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9390 bld
.reset(ctx
->block
);
9391 bld
.branch(aco_opcode::p_branch
);
9394 /* Fixup phis in loop header from unreachable blocks.
9395 * has_branch/has_divergent_branch also indicates if the loop ends with a
9396 * break/continue instruction, but we don't emit those if unreachable=true */
9398 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9399 bool linear
= ctx
->cf_info
.has_branch
;
9400 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9401 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9402 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9403 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9404 /* the last operand should be the one that needs to be removed */
9405 instr
->operands
.pop_back();
9406 } else if (!is_phi(instr
)) {
9412 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9413 * and the previous one shouldn't both happen at once because a break in the
9414 * merge block would get CSE'd */
9415 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9416 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9417 Operand vals
[num_vals
];
9418 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9419 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9420 if (ctx
->cf_info
.has_branch
)
9421 instr
->operands
.pop_back();
9423 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9424 } else if (!is_phi(instr
)) {
9430 ctx
->cf_info
.has_branch
= false;
9432 // TODO: if the loop has not a single exit, we must add one °°
9433 /* emit loop successor block */
9434 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9435 append_logical_start(ctx
->block
);
9438 // TODO: check if it is beneficial to not branch on continues
9439 /* trim linear phis in loop header */
9440 for (auto&& instr
: loop_entry
->instructions
) {
9441 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9442 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9443 new_phi
->definitions
[0] = instr
->definitions
[0];
9444 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9445 new_phi
->operands
[i
] = instr
->operands
[i
];
9446 /* check that the remaining operands are all the same */
9447 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9448 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9449 instr
.swap(new_phi
);
9450 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9459 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9463 append_logical_end(ctx
->block
);
9464 ctx
->block
->kind
|= block_kind_branch
;
9466 /* branch to linear then block */
9467 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9468 aco_ptr
<Pseudo_branch_instruction
> branch
;
9469 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9470 branch
->operands
[0] = Operand(cond
);
9471 ctx
->block
->instructions
.push_back(std::move(branch
));
9473 ic
->BB_if_idx
= ctx
->block
->index
;
9474 ic
->BB_invert
= Block();
9475 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9476 /* Invert blocks are intentionally not marked as top level because they
9477 * are not part of the logical cfg. */
9478 ic
->BB_invert
.kind
|= block_kind_invert
;
9479 ic
->BB_endif
= Block();
9480 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9481 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9483 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9484 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9485 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9486 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9487 ctx
->cf_info
.parent_if
.is_divergent
= true;
9489 /* divergent branches use cbranch_execz */
9490 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9491 ctx
->cf_info
.exec_potentially_empty_break
= false;
9492 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9494 /** emit logical then block */
9495 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9496 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9497 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9498 ctx
->block
= BB_then_logical
;
9499 append_logical_start(BB_then_logical
);
9502 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9504 Block
*BB_then_logical
= ctx
->block
;
9505 append_logical_end(BB_then_logical
);
9506 /* branch from logical then block to invert block */
9507 aco_ptr
<Pseudo_branch_instruction
> branch
;
9508 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9509 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9510 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9511 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9512 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9513 BB_then_logical
->kind
|= block_kind_uniform
;
9514 assert(!ctx
->cf_info
.has_branch
);
9515 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9516 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9518 /** emit linear then block */
9519 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9520 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9521 BB_then_linear
->kind
|= block_kind_uniform
;
9522 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9523 /* branch from linear then block to invert block */
9524 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9525 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9526 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9528 /** emit invert merge block */
9529 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9530 ic
->invert_idx
= ctx
->block
->index
;
9532 /* branch to linear else block (skip else) */
9533 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9534 branch
->operands
[0] = Operand(ic
->cond
);
9535 ctx
->block
->instructions
.push_back(std::move(branch
));
9537 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9538 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9539 ic
->exec_potentially_empty_break_depth_old
=
9540 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9541 /* divergent branches use cbranch_execz */
9542 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9543 ctx
->cf_info
.exec_potentially_empty_break
= false;
9544 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9546 /** emit logical else block */
9547 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9548 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9549 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9550 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9551 ctx
->block
= BB_else_logical
;
9552 append_logical_start(BB_else_logical
);
9555 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9557 Block
*BB_else_logical
= ctx
->block
;
9558 append_logical_end(BB_else_logical
);
9560 /* branch from logical else block to endif block */
9561 aco_ptr
<Pseudo_branch_instruction
> branch
;
9562 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9563 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9564 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9565 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9566 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9567 BB_else_logical
->kind
|= block_kind_uniform
;
9569 assert(!ctx
->cf_info
.has_branch
);
9570 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9573 /** emit linear else block */
9574 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9575 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9576 BB_else_linear
->kind
|= block_kind_uniform
;
9577 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9579 /* branch from linear else block to endif block */
9580 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9581 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9582 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9585 /** emit endif merge block */
9586 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9587 append_logical_start(ctx
->block
);
9590 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9591 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9592 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9593 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9594 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9595 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9596 !ctx
->cf_info
.parent_if
.is_divergent
) {
9597 ctx
->cf_info
.exec_potentially_empty_break
= false;
9598 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9600 /* uniform control flow never has an empty exec-mask */
9601 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9602 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9603 ctx
->cf_info
.exec_potentially_empty_break
= false;
9604 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9608 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9610 assert(cond
.regClass() == s1
);
9612 append_logical_end(ctx
->block
);
9613 ctx
->block
->kind
|= block_kind_uniform
;
9615 aco_ptr
<Pseudo_branch_instruction
> branch
;
9616 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9617 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9618 branch
->operands
[0] = Operand(cond
);
9619 branch
->operands
[0].setFixed(scc
);
9620 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9622 ic
->BB_if_idx
= ctx
->block
->index
;
9623 ic
->BB_endif
= Block();
9624 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9625 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9627 ctx
->cf_info
.has_branch
= false;
9628 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9630 /** emit then block */
9631 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9632 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9633 add_edge(ic
->BB_if_idx
, BB_then
);
9634 append_logical_start(BB_then
);
9635 ctx
->block
= BB_then
;
9638 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9640 Block
*BB_then
= ctx
->block
;
9642 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9643 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9645 if (!ic
->uniform_has_then_branch
) {
9646 append_logical_end(BB_then
);
9647 /* branch from then block to endif block */
9648 aco_ptr
<Pseudo_branch_instruction
> branch
;
9649 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9650 BB_then
->instructions
.emplace_back(std::move(branch
));
9651 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9652 if (!ic
->then_branch_divergent
)
9653 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9654 BB_then
->kind
|= block_kind_uniform
;
9657 ctx
->cf_info
.has_branch
= false;
9658 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9660 /** emit else block */
9661 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9662 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9663 add_edge(ic
->BB_if_idx
, BB_else
);
9664 append_logical_start(BB_else
);
9665 ctx
->block
= BB_else
;
9668 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9670 Block
*BB_else
= ctx
->block
;
9672 if (!ctx
->cf_info
.has_branch
) {
9673 append_logical_end(BB_else
);
9674 /* branch from then block to endif block */
9675 aco_ptr
<Pseudo_branch_instruction
> branch
;
9676 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9677 BB_else
->instructions
.emplace_back(std::move(branch
));
9678 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9679 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9680 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9681 BB_else
->kind
|= block_kind_uniform
;
9684 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9685 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9687 /** emit endif merge block */
9688 if (!ctx
->cf_info
.has_branch
) {
9689 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9690 append_logical_start(ctx
->block
);
9694 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9696 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9697 Builder
bld(ctx
->program
, ctx
->block
);
9698 aco_ptr
<Pseudo_branch_instruction
> branch
;
9701 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9703 * Uniform conditionals are represented in the following way*) :
9705 * The linear and logical CFG:
9708 * BB_THEN (logical) BB_ELSE (logical)
9712 * *) Exceptions may be due to break and continue statements within loops
9713 * If a break/continue happens within uniform control flow, it branches
9714 * to the loop exit/entry block. Otherwise, it branches to the next
9718 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9719 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9720 cond
= bool_to_scalar_condition(ctx
, cond
);
9722 begin_uniform_if_then(ctx
, &ic
, cond
);
9723 visit_cf_list(ctx
, &if_stmt
->then_list
);
9725 begin_uniform_if_else(ctx
, &ic
);
9726 visit_cf_list(ctx
, &if_stmt
->else_list
);
9728 end_uniform_if(ctx
, &ic
);
9729 } else { /* non-uniform condition */
9731 * To maintain a logical and linear CFG without critical edges,
9732 * non-uniform conditionals are represented in the following way*) :
9737 * BB_THEN (logical) BB_THEN (linear)
9739 * BB_INVERT (linear)
9741 * BB_ELSE (logical) BB_ELSE (linear)
9748 * BB_THEN (logical) BB_ELSE (logical)
9752 * *) Exceptions may be due to break and continue statements within loops
9755 begin_divergent_if_then(ctx
, &ic
, cond
);
9756 visit_cf_list(ctx
, &if_stmt
->then_list
);
9758 begin_divergent_if_else(ctx
, &ic
);
9759 visit_cf_list(ctx
, &if_stmt
->else_list
);
9761 end_divergent_if(ctx
, &ic
);
9764 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9767 static bool visit_cf_list(isel_context
*ctx
,
9768 struct exec_list
*list
)
9770 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9771 switch (node
->type
) {
9772 case nir_cf_node_block
:
9773 visit_block(ctx
, nir_cf_node_as_block(node
));
9775 case nir_cf_node_if
:
9776 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9779 case nir_cf_node_loop
:
9780 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9783 unreachable("unimplemented cf list type");
9789 static void create_null_export(isel_context
*ctx
)
9791 /* Some shader stages always need to have exports.
9792 * So when there is none, we need to add a null export.
9795 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9796 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9797 Builder
bld(ctx
->program
, ctx
->block
);
9798 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9799 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9802 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9804 assert(ctx
->stage
== vertex_vs
||
9805 ctx
->stage
== tess_eval_vs
||
9806 ctx
->stage
== gs_copy_vs
||
9807 ctx
->stage
== ngg_vertex_gs
||
9808 ctx
->stage
== ngg_tess_eval_gs
);
9810 int offset
= (ctx
->stage
& sw_tes
)
9811 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9812 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9813 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9814 if (!is_pos
&& !mask
)
9816 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9818 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9819 exp
->enabled_mask
= mask
;
9820 for (unsigned i
= 0; i
< 4; ++i
) {
9821 if (mask
& (1 << i
))
9822 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9824 exp
->operands
[i
] = Operand(v1
);
9826 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9827 * Setting valid_mask=1 prevents it and has no other effect.
9829 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9831 exp
->compressed
= false;
9833 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9835 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9836 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9841 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9843 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9844 exp
->enabled_mask
= 0;
9845 for (unsigned i
= 0; i
< 4; ++i
)
9846 exp
->operands
[i
] = Operand(v1
);
9847 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9848 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9849 exp
->enabled_mask
|= 0x1;
9851 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9852 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9853 exp
->enabled_mask
|= 0x4;
9855 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9856 if (ctx
->options
->chip_class
< GFX9
) {
9857 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9858 exp
->enabled_mask
|= 0x8;
9860 Builder
bld(ctx
->program
, ctx
->block
);
9862 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9863 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9864 if (exp
->operands
[2].isTemp())
9865 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9867 exp
->operands
[2] = Operand(out
);
9868 exp
->enabled_mask
|= 0x4;
9871 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9873 exp
->compressed
= false;
9874 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9875 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9878 static void create_export_phis(isel_context
*ctx
)
9880 /* Used when exports are needed, but the output temps are defined in a preceding block.
9881 * This function will set up phis in order to access the outputs in the next block.
9884 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9885 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9886 ctx
->block
->instructions
.pop_back();
9888 Builder
bld(ctx
->program
, ctx
->block
);
9890 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9891 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9892 for (unsigned i
= 0; i
< 4; ++i
) {
9893 if (!(mask
& (1 << i
)))
9896 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9897 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9898 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9902 bld
.insert(std::move(logical_start
));
9905 static void create_vs_exports(isel_context
*ctx
)
9907 assert(ctx
->stage
== vertex_vs
||
9908 ctx
->stage
== tess_eval_vs
||
9909 ctx
->stage
== gs_copy_vs
||
9910 ctx
->stage
== ngg_vertex_gs
||
9911 ctx
->stage
== ngg_tess_eval_gs
);
9913 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9914 ? &ctx
->program
->info
->tes
.outinfo
9915 : &ctx
->program
->info
->vs
.outinfo
;
9917 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9918 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9919 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9922 if (ctx
->options
->key
.has_multiview_view_index
) {
9923 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9924 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9927 /* the order these position exports are created is important */
9929 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9930 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9931 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9932 exported_pos
= true;
9934 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9935 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9936 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9937 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9939 if (ctx
->export_clip_dists
) {
9940 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9941 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9942 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9943 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9946 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9947 if (i
< VARYING_SLOT_VAR0
&&
9948 i
!= VARYING_SLOT_LAYER
&&
9949 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9950 i
!= VARYING_SLOT_VIEWPORT
)
9953 export_vs_varying(ctx
, i
, false, NULL
);
9957 create_null_export(ctx
);
9960 static bool export_fs_mrt_z(isel_context
*ctx
)
9962 Builder
bld(ctx
->program
, ctx
->block
);
9963 unsigned enabled_channels
= 0;
9967 for (unsigned i
= 0; i
< 4; ++i
) {
9968 values
[i
] = Operand(v1
);
9971 /* Both stencil and sample mask only need 16-bits. */
9972 if (!ctx
->program
->info
->ps
.writes_z
&&
9973 (ctx
->program
->info
->ps
.writes_stencil
||
9974 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9975 compr
= true; /* COMPR flag */
9977 if (ctx
->program
->info
->ps
.writes_stencil
) {
9978 /* Stencil should be in X[23:16]. */
9979 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9980 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9981 enabled_channels
|= 0x3;
9984 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9985 /* SampleMask should be in Y[15:0]. */
9986 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9987 enabled_channels
|= 0xc;
9990 if (ctx
->program
->info
->ps
.writes_z
) {
9991 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9992 enabled_channels
|= 0x1;
9995 if (ctx
->program
->info
->ps
.writes_stencil
) {
9996 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9997 enabled_channels
|= 0x2;
10000 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10001 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10002 enabled_channels
|= 0x4;
10006 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10007 * writemask component.
10009 if (ctx
->options
->chip_class
== GFX6
&&
10010 ctx
->options
->family
!= CHIP_OLAND
&&
10011 ctx
->options
->family
!= CHIP_HAINAN
) {
10012 enabled_channels
|= 0x1;
10015 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10016 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10021 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10023 Builder
bld(ctx
->program
, ctx
->block
);
10024 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10027 for (unsigned i
= 0; i
< 4; ++i
) {
10028 if (write_mask
& (1 << i
)) {
10029 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10031 values
[i
] = Operand(v1
);
10035 unsigned target
, col_format
;
10036 unsigned enabled_channels
= 0;
10037 aco_opcode compr_op
= (aco_opcode
)0;
10039 slot
-= FRAG_RESULT_DATA0
;
10040 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10041 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10043 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10044 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10045 bool is_16bit
= values
[0].regClass() == v2b
;
10047 switch (col_format
)
10049 case V_028714_SPI_SHADER_ZERO
:
10050 enabled_channels
= 0; /* writemask */
10051 target
= V_008DFC_SQ_EXP_NULL
;
10054 case V_028714_SPI_SHADER_32_R
:
10055 enabled_channels
= 1;
10058 case V_028714_SPI_SHADER_32_GR
:
10059 enabled_channels
= 0x3;
10062 case V_028714_SPI_SHADER_32_AR
:
10063 if (ctx
->options
->chip_class
>= GFX10
) {
10064 /* Special case: on GFX10, the outputs are different for 32_AR */
10065 enabled_channels
= 0x3;
10066 values
[1] = values
[3];
10067 values
[3] = Operand(v1
);
10069 enabled_channels
= 0x9;
10073 case V_028714_SPI_SHADER_FP16_ABGR
:
10074 enabled_channels
= 0x5;
10075 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10077 if (ctx
->options
->chip_class
>= GFX9
) {
10078 /* Pack the FP16 values together instead of converting them to
10079 * FP32 and back to FP16.
10080 * TODO: use p_create_vector and let the compiler optimizes.
10082 compr_op
= aco_opcode::v_pack_b32_f16
;
10084 for (unsigned i
= 0; i
< 4; i
++) {
10085 if ((write_mask
>> i
) & 1)
10086 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10092 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10093 enabled_channels
= 0x5;
10094 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10095 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10097 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10101 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10102 enabled_channels
= 0x5;
10103 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10104 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10106 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10110 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10111 enabled_channels
= 0x5;
10112 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10113 if (is_int8
|| is_int10
) {
10115 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10116 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10118 for (unsigned i
= 0; i
< 4; i
++) {
10119 if ((write_mask
>> i
) & 1) {
10120 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10121 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10125 } else if (is_16bit
) {
10126 for (unsigned i
= 0; i
< 4; i
++) {
10127 if ((write_mask
>> i
) & 1) {
10128 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10129 values
[i
] = Operand(tmp
);
10136 case V_028714_SPI_SHADER_SINT16_ABGR
:
10137 enabled_channels
= 0x5;
10138 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10139 if (is_int8
|| is_int10
) {
10141 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10142 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10143 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10144 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10146 for (unsigned i
= 0; i
< 4; i
++) {
10147 if ((write_mask
>> i
) & 1) {
10148 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10149 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10151 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10152 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10156 } else if (is_16bit
) {
10157 for (unsigned i
= 0; i
< 4; i
++) {
10158 if ((write_mask
>> i
) & 1) {
10159 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10160 values
[i
] = Operand(tmp
);
10166 case V_028714_SPI_SHADER_32_ABGR
:
10167 enabled_channels
= 0xF;
10174 if (target
== V_008DFC_SQ_EXP_NULL
)
10177 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10178 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10180 (col_format
== V_028714_SPI_SHADER_32_R
||
10181 col_format
== V_028714_SPI_SHADER_32_GR
||
10182 col_format
== V_028714_SPI_SHADER_32_AR
||
10183 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10184 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10185 for (int i
= 0; i
< 4; i
++) {
10186 if (!(write_mask
& (1 << i
)))
10189 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10190 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10191 bld
.copy(bld
.def(v1
), Operand(3u)));
10192 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10193 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10197 if ((bool) compr_op
) {
10198 for (int i
= 0; i
< 2; i
++) {
10199 /* check if at least one of the values to be compressed is enabled */
10200 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10202 enabled_channels
|= enabled
<< (i
*2);
10203 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10204 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10205 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10207 values
[i
] = Operand(v1
);
10210 values
[2] = Operand(v1
);
10211 values
[3] = Operand(v1
);
10213 for (int i
= 0; i
< 4; i
++)
10214 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10217 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10218 enabled_channels
, target
, (bool) compr_op
);
10222 static void create_fs_exports(isel_context
*ctx
)
10224 bool exported
= false;
10226 /* Export depth, stencil and sample mask. */
10227 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10228 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10229 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10230 exported
|= export_fs_mrt_z(ctx
);
10232 /* Export all color render targets. */
10233 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10234 if (ctx
->outputs
.mask
[i
])
10235 exported
|= export_fs_mrt_color(ctx
, i
);
10238 create_null_export(ctx
);
10241 static void write_tcs_tess_factors(isel_context
*ctx
)
10243 unsigned outer_comps
;
10244 unsigned inner_comps
;
10246 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10263 Builder
bld(ctx
->program
, ctx
->block
);
10265 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10266 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10267 bld
.sopp(aco_opcode::s_barrier
);
10269 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10270 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10272 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10273 if_context ic_invocation_id_is_zero
;
10274 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10275 bld
.reset(ctx
->block
);
10277 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10279 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10280 unsigned stride
= inner_comps
+ outer_comps
;
10281 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10285 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10287 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10289 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10290 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10291 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10293 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10294 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10296 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10297 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10298 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10299 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10302 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10303 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10304 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10305 unsigned tf_const_offset
= 0;
10307 if (ctx
->program
->chip_class
<= GFX8
) {
10308 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10309 if_context ic_rel_patch_id_is_zero
;
10310 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10311 bld
.reset(ctx
->block
);
10313 /* Store the dynamic HS control word. */
10314 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10315 bld
.mubuf(aco_opcode::buffer_store_dword
,
10316 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10317 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10318 /* disable_wqm */ false, /* glc */ true);
10319 tf_const_offset
+= 4;
10321 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10322 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10323 bld
.reset(ctx
->block
);
10326 assert(stride
== 2 || stride
== 4 || stride
== 6);
10327 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10328 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10330 /* Store to offchip for TES to read - only if TES reads them */
10331 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10332 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10333 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10335 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10336 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10338 if (likely(inner_comps
)) {
10339 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10340 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10344 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10345 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10348 static void emit_stream_output(isel_context
*ctx
,
10349 Temp
const *so_buffers
,
10350 Temp
const *so_write_offset
,
10351 const struct radv_stream_output
*output
)
10353 unsigned num_comps
= util_bitcount(output
->component_mask
);
10354 unsigned writemask
= (1 << num_comps
) - 1;
10355 unsigned loc
= output
->location
;
10356 unsigned buf
= output
->buffer
;
10358 assert(num_comps
&& num_comps
<= 4);
10359 if (!num_comps
|| num_comps
> 4)
10362 unsigned start
= ffs(output
->component_mask
) - 1;
10365 bool all_undef
= true;
10366 assert(ctx
->stage
& hw_vs
);
10367 for (unsigned i
= 0; i
< num_comps
; i
++) {
10368 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10369 all_undef
= all_undef
&& !out
[i
].id();
10374 while (writemask
) {
10376 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10377 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10378 /* GFX6 doesn't support storing vec3, split it. */
10379 writemask
|= 1u << (start
+ 2);
10383 unsigned offset
= output
->offset
+ start
* 4;
10385 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10386 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10387 for (int i
= 0; i
< count
; ++i
)
10388 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10389 vec
->definitions
[0] = Definition(write_data
);
10390 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10395 opcode
= aco_opcode::buffer_store_dword
;
10398 opcode
= aco_opcode::buffer_store_dwordx2
;
10401 opcode
= aco_opcode::buffer_store_dwordx3
;
10404 opcode
= aco_opcode::buffer_store_dwordx4
;
10407 unreachable("Unsupported dword count.");
10410 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10411 store
->operands
[0] = Operand(so_buffers
[buf
]);
10412 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10413 store
->operands
[2] = Operand((uint32_t) 0);
10414 store
->operands
[3] = Operand(write_data
);
10415 if (offset
> 4095) {
10416 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10417 Builder
bld(ctx
->program
, ctx
->block
);
10418 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10420 store
->offset
= offset
;
10422 store
->offen
= true;
10424 store
->dlc
= false;
10426 store
->can_reorder
= true;
10427 ctx
->block
->instructions
.emplace_back(std::move(store
));
10431 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10433 Builder
bld(ctx
->program
, ctx
->block
);
10435 Temp so_buffers
[4];
10436 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10437 for (unsigned i
= 0; i
< 4; i
++) {
10438 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10442 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10443 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10446 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10447 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10449 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10451 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10454 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10456 bld
.reset(ctx
->block
);
10458 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10460 Temp so_write_offset
[4];
10462 for (unsigned i
= 0; i
< 4; i
++) {
10463 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10468 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10469 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10470 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10471 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10473 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10475 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10476 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10477 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10478 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10482 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10483 struct radv_stream_output
*output
=
10484 &ctx
->program
->info
->so
.outputs
[i
];
10485 if (stream
!= output
->stream
)
10488 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10491 begin_divergent_if_else(ctx
, &ic
);
10492 end_divergent_if(ctx
, &ic
);
10495 } /* end namespace */
10497 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10499 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10500 Builder
bld(ctx
->program
, ctx
->block
);
10501 constexpr unsigned hs_idx
= 1u;
10502 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10503 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10504 Operand((8u << 16) | (hs_idx
* 8u)));
10505 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10507 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10509 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10510 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10511 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10512 ls_has_nonzero_hs_threads
);
10513 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10514 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10515 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10516 ls_has_nonzero_hs_threads
);
10517 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10518 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10519 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10520 ls_has_nonzero_hs_threads
);
10522 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10523 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10524 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10527 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10529 /* Split all arguments except for the first (ring_offsets) and the last
10530 * (exec) so that the dead channels don't stay live throughout the program.
10532 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10533 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10534 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10535 startpgm
->definitions
[i
].regClass().size());
10540 void handle_bc_optimize(isel_context
*ctx
)
10542 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10543 Builder
bld(ctx
->program
, ctx
->block
);
10544 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10545 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10546 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10547 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10548 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10549 if (uses_center
&& uses_centroid
) {
10550 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10551 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10553 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10555 for (unsigned i
= 0; i
< 2; i
++) {
10556 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10557 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10558 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10559 persp_centroid
, persp_center
, sel
);
10561 ctx
->persp_centroid
= bld
.tmp(v2
);
10562 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10563 Operand(new_coord
[0]), Operand(new_coord
[1]));
10564 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10567 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10569 for (unsigned i
= 0; i
< 2; i
++) {
10570 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10571 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10572 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10573 linear_centroid
, linear_center
, sel
);
10575 ctx
->linear_centroid
= bld
.tmp(v2
);
10576 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10577 Operand(new_coord
[0]), Operand(new_coord
[1]));
10578 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10583 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10585 Program
*program
= ctx
->program
;
10587 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10589 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10590 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10591 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10592 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10593 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10595 program
->next_fp_mode
.must_flush_denorms32
=
10596 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10597 program
->next_fp_mode
.must_flush_denorms16_64
=
10598 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10599 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10601 program
->next_fp_mode
.care_about_round32
=
10602 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10604 program
->next_fp_mode
.care_about_round16_64
=
10605 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10606 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10608 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10609 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10610 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10611 program
->next_fp_mode
.denorm16_64
= 0;
10613 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10615 /* preserving fp32 denorms is expensive, so only do it if asked */
10616 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10617 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10619 program
->next_fp_mode
.denorm32
= 0;
10621 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10622 program
->next_fp_mode
.round32
= fp_round_tz
;
10624 program
->next_fp_mode
.round32
= fp_round_ne
;
10626 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10627 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10629 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10631 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10634 void cleanup_cfg(Program
*program
)
10636 /* create linear_succs/logical_succs */
10637 for (Block
& BB
: program
->blocks
) {
10638 for (unsigned idx
: BB
.linear_preds
)
10639 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10640 for (unsigned idx
: BB
.logical_preds
)
10641 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10645 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10647 Builder
bld(ctx
->program
, ctx
->block
);
10649 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10650 Temp count
= i
== 0
10651 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10652 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10653 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10655 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10658 if (ctx
->program
->wave_size
== 64) {
10659 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10660 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10661 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10663 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10664 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10670 bool ngg_early_prim_export(isel_context
*ctx
)
10672 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10676 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10678 Builder
bld(ctx
->program
, ctx
->block
);
10680 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10681 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10683 /* Get the id of the current wave within the threadgroup (workgroup) */
10684 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10685 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10687 /* Execute the following code only on the first wave (wave id 0),
10688 * use the SCC def to tell if the wave id is zero or not.
10690 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10692 begin_uniform_if_then(ctx
, &ic
, cond
);
10693 begin_uniform_if_else(ctx
, &ic
);
10694 bld
.reset(ctx
->block
);
10696 /* Number of vertices output by VS/TES */
10697 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10698 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10699 /* Number of primitives output by VS/TES */
10700 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10701 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10703 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10704 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10705 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10707 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10708 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10710 end_uniform_if(ctx
, &ic
);
10712 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10713 bld
.reset(ctx
->block
);
10714 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10717 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10719 Builder
bld(ctx
->program
, ctx
->block
);
10721 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10722 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10725 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10728 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10729 assert(vtxindex
[i
].id());
10732 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10736 /* The initial edge flag is always false in tess eval shaders. */
10737 if (ctx
->stage
== ngg_vertex_gs
) {
10738 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10739 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10743 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10748 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10750 Builder
bld(ctx
->program
, ctx
->block
);
10751 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10753 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10754 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10755 false /* compressed */, true/* done */, false /* valid mask */);
10758 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10760 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10761 * These must always come before VS exports.
10763 * It is recommended to do these as early as possible. They can be at the beginning when
10764 * there is no SW GS and the shader doesn't write edge flags.
10768 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10769 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10771 Builder
bld(ctx
->program
, ctx
->block
);
10772 constexpr unsigned max_vertices_per_primitive
= 3;
10773 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10775 if (ctx
->stage
== ngg_vertex_gs
) {
10776 /* TODO: optimize for points & lines */
10777 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10778 if (ctx
->shader
->info
.tess
.point_mode
)
10779 num_vertices_per_primitive
= 1;
10780 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10781 num_vertices_per_primitive
= 2;
10783 unreachable("Unsupported NGG shader stage");
10786 Temp vtxindex
[max_vertices_per_primitive
];
10787 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10788 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10789 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10790 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10791 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10792 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10793 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10794 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10796 /* Export primitive data to the index buffer. */
10797 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10799 /* Export primitive ID. */
10800 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10801 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10802 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10803 Temp provoking_vtx_index
= vtxindex
[0];
10804 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10806 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10809 begin_divergent_if_else(ctx
, &ic
);
10810 end_divergent_if(ctx
, &ic
);
10813 void ngg_emit_nogs_output(isel_context
*ctx
)
10815 /* Emits NGG GS output, for stages that don't have SW GS. */
10818 Builder
bld(ctx
->program
, ctx
->block
);
10819 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10821 /* NGG streamout is currently disabled by default. */
10822 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10824 if (late_prim_export
) {
10825 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10826 create_export_phis(ctx
);
10827 /* Do what we need to do in the GS threads. */
10828 ngg_emit_nogs_gsthreads(ctx
);
10830 /* What comes next should be executed on ES threads. */
10831 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10832 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10833 bld
.reset(ctx
->block
);
10836 /* Export VS outputs */
10837 ctx
->block
->kind
|= block_kind_export_end
;
10838 create_vs_exports(ctx
);
10840 /* Export primitive ID */
10841 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10844 if (ctx
->stage
== ngg_vertex_gs
) {
10845 /* Wait for GS threads to store primitive ID in LDS. */
10846 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10847 bld
.sopp(aco_opcode::s_barrier
);
10849 /* Calculate LDS address where the GS threads stored the primitive ID. */
10850 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10851 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10852 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10853 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10854 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10855 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10857 /* Load primitive ID from LDS. */
10858 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10859 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10860 /* TES: Just use the patch ID as the primitive ID. */
10861 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10863 unreachable("unsupported NGG shader stage.");
10866 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10867 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10869 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10872 if (late_prim_export
) {
10873 begin_divergent_if_else(ctx
, &ic
);
10874 end_divergent_if(ctx
, &ic
);
10875 bld
.reset(ctx
->block
);
10879 void select_program(Program
*program
,
10880 unsigned shader_count
,
10881 struct nir_shader
*const *shaders
,
10882 ac_shader_config
* config
,
10883 struct radv_shader_args
*args
)
10885 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10886 if_context ic_merged_wave_info
;
10887 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10889 for (unsigned i
= 0; i
< shader_count
; i
++) {
10890 nir_shader
*nir
= shaders
[i
];
10891 init_context(&ctx
, nir
);
10893 setup_fp_mode(&ctx
, nir
);
10896 /* needs to be after init_context() for FS */
10897 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10898 append_logical_start(ctx
.block
);
10900 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10901 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10903 split_arguments(&ctx
, startpgm
);
10907 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10909 if (ngg_early_prim_export(&ctx
))
10910 ngg_emit_nogs_gsthreads(&ctx
);
10913 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10914 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10915 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10916 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10917 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10918 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10919 ctx
.stage
== tess_eval_geometry_gs
));
10921 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10922 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10923 if (check_merged_wave_info
) {
10924 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10925 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10929 Builder
bld(ctx
.program
, ctx
.block
);
10931 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10932 bld
.sopp(aco_opcode::s_barrier
);
10934 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10935 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10937 } else if (ctx
.stage
== geometry_gs
)
10938 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10940 if (ctx
.stage
== fragment_fs
)
10941 handle_bc_optimize(&ctx
);
10943 visit_cf_list(&ctx
, &func
->body
);
10945 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10946 emit_streamout(&ctx
, 0);
10948 if (ctx
.stage
& hw_vs
) {
10949 create_vs_exports(&ctx
);
10950 ctx
.block
->kind
|= block_kind_export_end
;
10951 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10952 ngg_emit_nogs_output(&ctx
);
10953 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10954 Builder
bld(ctx
.program
, ctx
.block
);
10955 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10956 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10957 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10958 write_tcs_tess_factors(&ctx
);
10961 if (ctx
.stage
== fragment_fs
) {
10962 create_fs_exports(&ctx
);
10963 ctx
.block
->kind
|= block_kind_export_end
;
10966 if (endif_merged_wave_info
) {
10967 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10968 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10971 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10972 ngg_emit_nogs_output(&ctx
);
10974 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10975 /* Outputs of the previous stage are inputs to the next stage */
10976 ctx
.inputs
= ctx
.outputs
;
10977 ctx
.outputs
= shader_io_state();
10981 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10983 append_logical_end(ctx
.block
);
10984 ctx
.block
->kind
|= block_kind_uniform
;
10985 Builder
bld(ctx
.program
, ctx
.block
);
10986 if (ctx
.program
->wb_smem_l1_on_end
)
10987 bld
.smem(aco_opcode::s_dcache_wb
, false);
10988 bld
.sopp(aco_opcode::s_endpgm
);
10990 cleanup_cfg(program
);
10993 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10994 ac_shader_config
* config
,
10995 struct radv_shader_args
*args
)
10997 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10999 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
11000 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
11001 program
->next_fp_mode
.must_flush_denorms32
= false;
11002 program
->next_fp_mode
.must_flush_denorms16_64
= false;
11003 program
->next_fp_mode
.care_about_round32
= false;
11004 program
->next_fp_mode
.care_about_round16_64
= false;
11005 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
11006 program
->next_fp_mode
.denorm32
= 0;
11007 program
->next_fp_mode
.round32
= fp_round_ne
;
11008 program
->next_fp_mode
.round16_64
= fp_round_ne
;
11009 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11011 add_startpgm(&ctx
);
11012 append_logical_start(ctx
.block
);
11014 Builder
bld(ctx
.program
, ctx
.block
);
11016 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11018 Operand
stream_id(0u);
11019 if (args
->shader_info
->so
.num_outputs
)
11020 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11021 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11023 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11025 std::stack
<Block
> endif_blocks
;
11027 for (unsigned stream
= 0; stream
< 4; stream
++) {
11028 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11031 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11032 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11035 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11037 unsigned BB_if_idx
= ctx
.block
->index
;
11038 Block BB_endif
= Block();
11039 if (!stream_id
.isConstant()) {
11041 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11042 append_logical_end(ctx
.block
);
11043 ctx
.block
->kind
|= block_kind_uniform
;
11044 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11046 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11048 ctx
.block
= ctx
.program
->create_and_insert_block();
11049 add_edge(BB_if_idx
, ctx
.block
);
11050 bld
.reset(ctx
.block
);
11051 append_logical_start(ctx
.block
);
11054 unsigned offset
= 0;
11055 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11056 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11059 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11060 unsigned length
= util_last_bit(output_usage_mask
);
11061 for (unsigned j
= 0; j
< length
; ++j
) {
11062 if (!(output_usage_mask
& (1 << j
)))
11065 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11066 Temp voffset
= vtx_offset
;
11067 if (const_offset
>= 4096u) {
11068 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11069 const_offset
%= 4096u;
11072 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11073 mubuf
->definitions
[0] = bld
.def(v1
);
11074 mubuf
->operands
[0] = Operand(gsvs_ring
);
11075 mubuf
->operands
[1] = Operand(voffset
);
11076 mubuf
->operands
[2] = Operand(0u);
11077 mubuf
->offen
= true;
11078 mubuf
->offset
= const_offset
;
11081 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11082 mubuf
->barrier
= barrier_none
;
11083 mubuf
->can_reorder
= true;
11085 ctx
.outputs
.mask
[i
] |= 1 << j
;
11086 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11088 bld
.insert(std::move(mubuf
));
11094 if (args
->shader_info
->so
.num_outputs
) {
11095 emit_streamout(&ctx
, stream
);
11096 bld
.reset(ctx
.block
);
11100 create_vs_exports(&ctx
);
11101 ctx
.block
->kind
|= block_kind_export_end
;
11104 if (!stream_id
.isConstant()) {
11105 append_logical_end(ctx
.block
);
11107 /* branch from then block to endif block */
11108 bld
.branch(aco_opcode::p_branch
);
11109 add_edge(ctx
.block
->index
, &BB_endif
);
11110 ctx
.block
->kind
|= block_kind_uniform
;
11112 /* emit else block */
11113 ctx
.block
= ctx
.program
->create_and_insert_block();
11114 add_edge(BB_if_idx
, ctx
.block
);
11115 bld
.reset(ctx
.block
);
11116 append_logical_start(ctx
.block
);
11118 endif_blocks
.push(std::move(BB_endif
));
11122 while (!endif_blocks
.empty()) {
11123 Block BB_endif
= std::move(endif_blocks
.top());
11124 endif_blocks
.pop();
11126 Block
*BB_else
= ctx
.block
;
11128 append_logical_end(BB_else
);
11129 /* branch from else block to endif block */
11130 bld
.branch(aco_opcode::p_branch
);
11131 add_edge(BB_else
->index
, &BB_endif
);
11132 BB_else
->kind
|= block_kind_uniform
;
11134 /** emit endif merge block */
11135 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11136 bld
.reset(ctx
.block
);
11137 append_logical_start(ctx
.block
);
11140 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11142 append_logical_end(ctx
.block
);
11143 ctx
.block
->kind
|= block_kind_uniform
;
11144 bld
.sopp(aco_opcode::s_endpgm
);
11146 cleanup_cfg(program
);