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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
139 } else if (ctx
->program
->chip_class
<= GFX7
) {
140 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
143 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
148 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
150 Builder
bld(ctx
->program
, ctx
->block
);
153 dst
= bld
.tmp(src
.regClass());
155 assert(src
.size() == dst
.size());
157 if (ctx
->stage
!= fragment_fs
) {
161 bld
.copy(Definition(dst
), src
);
165 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
166 ctx
->program
->needs_wqm
|= program_needs_wqm
;
170 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
172 if (index
.regClass() == s1
)
173 return bld
.readlane(bld
.def(s1
), data
, index
);
175 if (ctx
->options
->chip_class
<= GFX7
) {
176 /* GFX6-7: there is no bpermute instruction */
177 Operand
index_op(index
);
178 Operand
input_data(data
);
179 index_op
.setLateKill(true);
180 input_data
.setLateKill(true);
182 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
183 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
184 /* GFX10 wave64 mode: emulate full-wave bpermute */
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
192 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
193 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
194 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
195 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
196 Operand
input_data(data
);
198 index_x4
.setLateKill(true);
199 input_data
.setLateKill(true);
200 same_half
.setLateKill(true);
202 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
204 /* GFX8-9 or GFX10 wave32: bpermute works normally */
205 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
206 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
210 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
212 if (ctx
->options
->chip_class
>= GFX8
) {
213 unsigned and_mask
= mask
& 0x1f;
214 unsigned or_mask
= (mask
>> 5) & 0x1f;
215 unsigned xor_mask
= (mask
>> 10) & 0x1f;
217 uint16_t dpp_ctrl
= 0xffff;
219 // TODO: we could use DPP8 for some swizzles
220 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
221 unsigned res
[4] = {0, 1, 2, 3};
222 for (unsigned i
= 0; i
< 4; i
++)
223 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
224 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
225 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
226 dpp_ctrl
= dpp_row_rr(8);
227 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
228 dpp_ctrl
= dpp_row_mirror
;
229 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
230 dpp_ctrl
= dpp_row_half_mirror
;
233 if (dpp_ctrl
!= 0xffff)
234 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
237 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
240 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
242 if (val
.type() == RegType::sgpr
) {
243 Builder
bld(ctx
->program
, ctx
->block
);
244 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
246 assert(val
.type() == RegType::vgpr
);
250 //assumes a != 0xffffffff
251 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
254 Builder
bld(ctx
->program
, ctx
->block
);
256 if (util_is_power_of_two_or_zero(b
)) {
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
261 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
263 assert(info
.multiplier
<= 0xffffffff);
265 bool pre_shift
= info
.pre_shift
!= 0;
266 bool increment
= info
.increment
!= 0;
267 bool multiply
= true;
268 bool post_shift
= info
.post_shift
!= 0;
270 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
271 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
275 Temp pre_shift_dst
= a
;
277 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
278 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
281 Temp increment_dst
= pre_shift_dst
;
283 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
284 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
287 Temp multiply_dst
= increment_dst
;
289 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
290 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
291 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
299 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
301 Builder
bld(ctx
->program
, ctx
->block
);
302 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
306 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
308 /* no need to extract the whole vector */
309 if (src
.regClass() == dst_rc
) {
314 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
315 Builder
bld(ctx
->program
, ctx
->block
);
316 auto it
= ctx
->allocated_vec
.find(src
.id());
317 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
318 if (it
->second
[idx
].regClass() == dst_rc
) {
319 return it
->second
[idx
];
321 assert(!dst_rc
.is_subdword());
322 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
323 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
327 if (dst_rc
.is_subdword())
328 src
= as_vgpr(ctx
, src
);
330 if (src
.bytes() == dst_rc
.bytes()) {
332 return bld
.copy(bld
.def(dst_rc
), src
);
334 Temp dst
= bld
.tmp(dst_rc
);
335 emit_extract_vector(ctx
, src
, idx
, dst
);
340 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
342 if (num_components
== 1)
344 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
347 if (num_components
> vec_src
.size()) {
348 if (vec_src
.type() == RegType::sgpr
) {
349 /* should still help get_alu_src() */
350 emit_split_vector(ctx
, vec_src
, vec_src
.size());
353 /* sub-dword split */
354 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
356 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
358 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
359 split
->operands
[0] = Operand(vec_src
);
360 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
361 for (unsigned i
= 0; i
< num_components
; i
++) {
362 elems
[i
] = {ctx
->program
->allocateId(), rc
};
363 split
->definitions
[i
] = Definition(elems
[i
]);
365 ctx
->block
->instructions
.emplace_back(std::move(split
));
366 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
369 /* This vector expansion uses a mask to determine which elements in the new vector
370 * come from the original vector. The other elements are undefined. */
371 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
373 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
378 Builder
bld(ctx
->program
, ctx
->block
);
379 if (num_components
== 1) {
380 if (dst
.type() == RegType::sgpr
)
381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
383 bld
.copy(Definition(dst
), vec_src
);
387 unsigned component_size
= dst
.size() / num_components
;
388 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
390 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
391 vec
->definitions
[0] = Definition(dst
);
393 for (unsigned i
= 0; i
< num_components
; i
++) {
394 if (mask
& (1 << i
)) {
395 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
396 if (dst
.type() == RegType::sgpr
)
397 src
= bld
.as_uniform(src
);
398 vec
->operands
[i
] = Operand(src
);
400 vec
->operands
[i
] = Operand(0u);
402 elems
[i
] = vec
->operands
[i
].getTemp();
404 ctx
->block
->instructions
.emplace_back(std::move(vec
));
405 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
408 /* adjust misaligned small bit size loads */
409 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
411 Builder
bld(ctx
->program
, ctx
->block
);
413 Temp select
= Temp();
414 if (offset
.isConstant()) {
415 assert(offset
.constantValue() && offset
.constantValue() < 4);
416 shift
= Operand(offset
.constantValue() * 8);
418 /* bit_offset = 8 * (offset & 0x3) */
419 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
420 select
= bld
.tmp(s1
);
421 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
424 if (vec
.size() == 1) {
425 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
426 } else if (vec
.size() == 2) {
427 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
428 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
430 emit_split_vector(ctx
, dst
, 2);
432 emit_extract_vector(ctx
, tmp
, 0, dst
);
433 } else if (vec
.size() == 4) {
434 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
435 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
436 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
437 if (select
!= Temp())
438 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
439 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
440 Temp mid
= bld
.tmp(s1
);
441 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
442 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
443 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
444 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
445 emit_split_vector(ctx
, dst
, 2);
449 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
451 Builder
bld(ctx
->program
, ctx
->block
);
452 if (offset
.isTemp()) {
453 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
455 if (vec
.size() == 4) {
456 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
458 } else if (vec
.size() == 3) {
459 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
461 } else if (vec
.size() == 2) {
462 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
465 for (unsigned i
= 0; i
< dst
.size(); i
++)
466 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
470 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
472 offset
= Operand(0u);
475 unsigned num_components
= vec
.bytes() / component_size
;
476 if (vec
.regClass() == dst
.regClass()) {
477 assert(offset
.constantValue() == 0);
478 bld
.copy(Definition(dst
), vec
);
479 emit_split_vector(ctx
, dst
, num_components
);
483 emit_split_vector(ctx
, vec
, num_components
);
484 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
485 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
487 assert(offset
.constantValue() % component_size
== 0);
488 unsigned skip
= offset
.constantValue() / component_size
;
489 for (unsigned i
= skip
; i
< num_components
; i
++)
490 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
492 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
493 if (dst
.type() == RegType::vgpr
) {
494 num_components
= dst
.bytes() / component_size
;
495 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
496 for (unsigned i
= 0; i
< num_components
; i
++)
497 create_vec
->operands
[i
] = Operand(elems
[i
]);
498 create_vec
->definitions
[0] = Definition(dst
);
499 bld
.insert(std::move(create_vec
));
501 /* if dst is sgpr - split the src, but move the original to sgpr. */
503 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
504 byte_align_scalar(ctx
, vec
, offset
, dst
);
506 assert(dst
.size() == vec
.size());
507 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
510 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
513 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
515 Builder
bld(ctx
->program
, ctx
->block
);
517 dst
= bld
.tmp(bld
.lm
);
519 assert(val
.regClass() == s1
);
520 assert(dst
.regClass() == bld
.lm
);
522 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
525 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
527 Builder
bld(ctx
->program
, ctx
->block
);
531 assert(val
.regClass() == bld
.lm
);
532 assert(dst
.regClass() == s1
);
534 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
535 Temp tmp
= bld
.tmp(s1
);
536 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
537 return emit_wqm(ctx
, tmp
, dst
);
540 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
543 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
544 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
546 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
549 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
550 return bld
.copy(Definition(dst
), src
);
551 else if (dst
.bytes() < src
.bytes())
552 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
556 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
559 } else if (src
.regClass() == s1
) {
561 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
563 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
564 } else if (ctx
->options
->chip_class
>= GFX8
) {
565 assert(src_bits
!= 8 || src
.regClass() == v1b
);
566 assert(src_bits
!= 16 || src
.regClass() == v2b
);
567 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
568 sdwa
->operands
[0] = Operand(src
);
569 sdwa
->definitions
[0] = Definition(tmp
);
571 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
573 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
574 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
575 bld
.insert(std::move(sdwa
));
577 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
578 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
579 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
582 if (dst_bits
== 64) {
583 if (is_signed
&& dst
.regClass() == s2
) {
584 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
586 } else if (is_signed
&& dst
.regClass() == v2
) {
587 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
597 enum sgpr_extract_mode
{
603 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
605 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
606 unsigned src_size
= src
->src
.ssa
->bit_size
;
607 unsigned swizzle
= src
->swizzle
[0];
609 if (vec
.size() > 1) {
610 assert(src_size
== 16);
611 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
612 swizzle
= swizzle
& 1;
615 Builder
bld(ctx
->program
, ctx
->block
);
616 unsigned offset
= src_size
* swizzle
;
617 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
619 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
620 bld
.copy(Definition(tmp
), vec
);
621 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
622 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
623 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
624 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
625 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
626 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
628 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
629 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
632 if (dst
.regClass() == s2
)
633 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
638 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
640 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
641 return get_ssa_temp(ctx
, src
.src
.ssa
);
643 if (src
.src
.ssa
->num_components
== size
) {
644 bool identity_swizzle
= true;
645 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
646 if (src
.swizzle
[i
] != i
)
647 identity_swizzle
= false;
649 if (identity_swizzle
)
650 return get_ssa_temp(ctx
, src
.src
.ssa
);
653 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
654 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
655 assert(elem_size
> 0);
656 assert(vec
.bytes() % elem_size
== 0);
658 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
659 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
661 return extract_8_16_bit_sgpr_element(
662 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
665 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
667 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
670 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
671 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
672 for (unsigned i
= 0; i
< size
; ++i
) {
673 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
674 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
676 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
677 vec_instr
->definitions
[0] = Definition(dst
);
678 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
679 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
684 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
688 Builder
bld(ctx
->program
, ctx
->block
);
689 if (ptr
.type() == RegType::vgpr
)
690 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
691 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
692 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
695 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
697 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
698 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
699 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
700 sop2
->definitions
[0] = Definition(dst
);
701 if (instr
->no_unsigned_wrap
)
702 sop2
->definitions
[0].setNUW(true);
704 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
705 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
708 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
709 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
711 Builder
bld(ctx
->program
, ctx
->block
);
712 bld
.is_precise
= instr
->exact
;
714 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
715 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
716 if (src1
.type() == RegType::sgpr
) {
717 if (commutative
&& src0
.type() == RegType::vgpr
) {
722 src1
= as_vgpr(ctx
, src1
);
726 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
727 assert(dst
.size() == 1);
728 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
729 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
731 bld
.vop2(op
, Definition(dst
), src0
, src1
);
735 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
736 aco_opcode op
, Temp dst
)
738 Builder
bld(ctx
->program
, ctx
->block
);
739 bld
.is_precise
= instr
->exact
;
741 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
742 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
744 if (src1
.type() == RegType::sgpr
) {
745 assert(src0
.type() == RegType::vgpr
);
746 std::swap(src0
, src1
);
749 Temp src00
= bld
.tmp(src0
.type(), 1);
750 Temp src01
= bld
.tmp(src0
.type(), 1);
751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
752 Temp src10
= bld
.tmp(v1
);
753 Temp src11
= bld
.tmp(v1
);
754 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
755 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
756 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
760 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
761 bool flush_denorms
= false)
763 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
764 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
765 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
767 /* ensure that the instruction has at most 1 sgpr operand
768 * The optimizer will inline constants for us */
769 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
770 src0
= as_vgpr(ctx
, src0
);
771 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
772 src1
= as_vgpr(ctx
, src1
);
773 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
774 src2
= as_vgpr(ctx
, src2
);
776 Builder
bld(ctx
->program
, ctx
->block
);
777 bld
.is_precise
= instr
->exact
;
778 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
779 assert(dst
.size() == 1);
780 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
781 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
783 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
787 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
789 Builder
bld(ctx
->program
, ctx
->block
);
790 bld
.is_precise
= instr
->exact
;
791 if (dst
.type() == RegType::sgpr
)
792 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
793 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
795 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
798 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
800 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
801 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
802 assert(src0
.size() == src1
.size());
804 aco_ptr
<Instruction
> vopc
;
805 if (src1
.type() == RegType::sgpr
) {
806 if (src0
.type() == RegType::vgpr
) {
807 /* to swap the operands, we might also have to change the opcode */
809 case aco_opcode::v_cmp_lt_f16
:
810 op
= aco_opcode::v_cmp_gt_f16
;
812 case aco_opcode::v_cmp_ge_f16
:
813 op
= aco_opcode::v_cmp_le_f16
;
815 case aco_opcode::v_cmp_lt_i16
:
816 op
= aco_opcode::v_cmp_gt_i16
;
818 case aco_opcode::v_cmp_ge_i16
:
819 op
= aco_opcode::v_cmp_le_i16
;
821 case aco_opcode::v_cmp_lt_u16
:
822 op
= aco_opcode::v_cmp_gt_u16
;
824 case aco_opcode::v_cmp_ge_u16
:
825 op
= aco_opcode::v_cmp_le_u16
;
827 case aco_opcode::v_cmp_lt_f32
:
828 op
= aco_opcode::v_cmp_gt_f32
;
830 case aco_opcode::v_cmp_ge_f32
:
831 op
= aco_opcode::v_cmp_le_f32
;
833 case aco_opcode::v_cmp_lt_i32
:
834 op
= aco_opcode::v_cmp_gt_i32
;
836 case aco_opcode::v_cmp_ge_i32
:
837 op
= aco_opcode::v_cmp_le_i32
;
839 case aco_opcode::v_cmp_lt_u32
:
840 op
= aco_opcode::v_cmp_gt_u32
;
842 case aco_opcode::v_cmp_ge_u32
:
843 op
= aco_opcode::v_cmp_le_u32
;
845 case aco_opcode::v_cmp_lt_f64
:
846 op
= aco_opcode::v_cmp_gt_f64
;
848 case aco_opcode::v_cmp_ge_f64
:
849 op
= aco_opcode::v_cmp_le_f64
;
851 case aco_opcode::v_cmp_lt_i64
:
852 op
= aco_opcode::v_cmp_gt_i64
;
854 case aco_opcode::v_cmp_ge_i64
:
855 op
= aco_opcode::v_cmp_le_i64
;
857 case aco_opcode::v_cmp_lt_u64
:
858 op
= aco_opcode::v_cmp_gt_u64
;
860 case aco_opcode::v_cmp_ge_u64
:
861 op
= aco_opcode::v_cmp_le_u64
;
863 default: /* eq and ne are commutative */
870 src1
= as_vgpr(ctx
, src1
);
874 Builder
bld(ctx
->program
, ctx
->block
);
875 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
878 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
880 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
881 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
882 Builder
bld(ctx
->program
, ctx
->block
);
884 assert(dst
.regClass() == bld
.lm
);
885 assert(src0
.type() == RegType::sgpr
);
886 assert(src1
.type() == RegType::sgpr
);
887 assert(src0
.regClass() == src1
.regClass());
889 /* Emit the SALU comparison instruction */
890 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
891 /* Turn the result into a per-lane bool */
892 bool_to_vector_condition(ctx
, cmp
, dst
);
895 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
896 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
898 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
899 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
900 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
901 nir_dest_is_divergent(instr
->dest
.dest
) ||
902 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
903 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
904 aco_opcode op
= use_valu
? v_op
: s_op
;
905 assert(op
!= aco_opcode::num_opcodes
);
906 assert(dst
.regClass() == ctx
->program
->lane_mask
);
909 emit_vopc_instruction(ctx
, instr
, op
, dst
);
911 emit_sopc_instruction(ctx
, instr
, op
, dst
);
914 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
916 Builder
bld(ctx
->program
, ctx
->block
);
917 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
918 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
920 assert(dst
.regClass() == bld
.lm
);
921 assert(src0
.regClass() == bld
.lm
);
922 assert(src1
.regClass() == bld
.lm
);
924 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
927 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
929 Builder
bld(ctx
->program
, ctx
->block
);
930 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
931 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
932 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
934 assert(cond
.regClass() == bld
.lm
);
936 if (dst
.type() == RegType::vgpr
) {
937 aco_ptr
<Instruction
> bcsel
;
938 if (dst
.size() == 1) {
939 then
= as_vgpr(ctx
, then
);
940 els
= as_vgpr(ctx
, els
);
942 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
943 } else if (dst
.size() == 2) {
944 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
945 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
946 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
947 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
949 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
950 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
952 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
954 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
955 nir_print_instr(&instr
->instr
, stderr
);
956 fprintf(stderr
, "\n");
961 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
962 assert(dst
.regClass() == bld
.lm
);
963 assert(then
.regClass() == bld
.lm
);
964 assert(els
.regClass() == bld
.lm
);
967 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
968 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
969 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
970 assert(dst
.size() == then
.size());
971 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
972 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
974 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
975 nir_print_instr(&instr
->instr
, stderr
);
976 fprintf(stderr
, "\n");
981 /* divergent boolean bcsel
982 * this implements bcsel on bools: dst = s0 ? s1 : s2
983 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
984 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
986 if (cond
.id() != then
.id())
987 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
989 if (cond
.id() == els
.id())
990 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
992 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
993 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
996 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
997 aco_opcode op
, uint32_t undo
)
999 /* multiply by 16777216 to handle denormals */
1000 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1001 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1002 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1003 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1004 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1006 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1008 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1011 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1013 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1014 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1018 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1021 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1023 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1024 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1028 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1031 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1033 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1034 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1038 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1041 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1043 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1044 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1048 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1051 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1053 if (ctx
->options
->chip_class
>= GFX7
)
1054 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1056 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1057 /* TODO: create more efficient code! */
1058 if (val
.type() == RegType::sgpr
)
1059 val
= as_vgpr(ctx
, val
);
1061 /* Split the input value. */
1062 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1063 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1065 /* Extract the exponent and compute the unbiased value. */
1066 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1067 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1069 /* Extract the fractional part. */
1070 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1071 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1073 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1074 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1076 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1077 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1078 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1079 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1080 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1082 /* Get the sign bit. */
1083 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1085 /* Decide the operation to apply depending on the unbiased exponent. */
1086 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1087 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1088 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1089 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1090 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1091 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1093 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1096 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1098 if (ctx
->options
->chip_class
>= GFX7
)
1099 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1101 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1102 * lowered at NIR level for precision reasons). */
1103 Temp src0
= as_vgpr(ctx
, val
);
1105 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1106 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1108 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1109 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1110 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1112 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1113 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1114 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1115 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1117 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1118 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1120 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1122 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1123 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1125 return add
->definitions
[0].getTemp();
1128 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1130 if (!instr
->dest
.dest
.is_ssa
) {
1131 fprintf(stderr
, "nir alu dst not in ssa: ");
1132 nir_print_instr(&instr
->instr
, stderr
);
1133 fprintf(stderr
, "\n");
1136 Builder
bld(ctx
->program
, ctx
->block
);
1137 bld
.is_precise
= instr
->exact
;
1138 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1143 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1144 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1145 for (unsigned i
= 0; i
< num
; ++i
)
1146 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1148 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1149 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1150 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1151 for (unsigned i
= 0; i
< num
; ++i
) {
1152 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1153 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1155 vec
->operands
[i
] = Operand
{elems
[i
]};
1157 vec
->definitions
[0] = Definition(dst
);
1158 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1159 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1161 // TODO: that is a bit suboptimal..
1162 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1163 for (unsigned i
= 0; i
< num
- 1; ++i
)
1164 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1165 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1166 for (unsigned i
= 0; i
< num
; ++i
) {
1167 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1168 if (bit
% 32 == 0) {
1169 elems
[bit
/ 32] = elems
[i
];
1171 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1172 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1173 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1176 if (dst
.size() == 1)
1177 bld
.copy(Definition(dst
), elems
[0]);
1179 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1184 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1185 aco_ptr
<Instruction
> mov
;
1186 if (dst
.type() == RegType::sgpr
) {
1187 if (src
.type() == RegType::vgpr
)
1188 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1189 else if (src
.regClass() == s1
)
1190 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1191 else if (src
.regClass() == s2
)
1192 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1194 unreachable("wrong src register class for nir_op_imov");
1196 if (dst
.regClass() == v1
)
1197 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1198 else if (dst
.regClass() == v1b
||
1199 dst
.regClass() == v2b
||
1200 dst
.regClass() == v2
)
1201 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1203 unreachable("wrong src register class for nir_op_imov");
1208 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1209 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1210 assert(src
.regClass() == bld
.lm
);
1211 assert(dst
.regClass() == bld
.lm
);
1212 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1213 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1214 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1215 } else if (dst
.regClass() == v1
) {
1216 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1217 } else if (dst
.regClass() == v2
) {
1218 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1219 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1220 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1221 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1222 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1223 } else if (dst
.type() == RegType::sgpr
) {
1224 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1225 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1227 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1228 nir_print_instr(&instr
->instr
, stderr
);
1229 fprintf(stderr
, "\n");
1234 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1235 if (dst
.regClass() == v1
) {
1236 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1237 } else if (dst
.regClass() == s1
) {
1238 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1239 } else if (dst
.size() == 2) {
1240 Temp src0
= bld
.tmp(dst
.type(), 1);
1241 Temp src1
= bld
.tmp(dst
.type(), 1);
1242 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1244 if (dst
.regClass() == s2
) {
1245 Temp carry
= bld
.tmp(s1
);
1246 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1247 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1248 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1250 Temp lower
= bld
.tmp(v1
);
1251 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1252 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1253 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1256 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1257 nir_print_instr(&instr
->instr
, stderr
);
1258 fprintf(stderr
, "\n");
1263 if (dst
.regClass() == s1
) {
1264 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1265 } else if (dst
.regClass() == v1
) {
1266 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1267 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1275 case nir_op_isign
: {
1276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1277 if (dst
.regClass() == s1
) {
1278 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1279 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1280 } else if (dst
.regClass() == s2
) {
1281 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1283 if (ctx
->program
->chip_class
>= GFX8
)
1284 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1286 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1287 /* SCC gets zero-extended to 64 bit */
1288 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1289 } else if (dst
.regClass() == v1
) {
1290 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1291 } else if (dst
.regClass() == v2
) {
1292 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1293 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1294 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1295 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1296 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1297 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1299 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1300 nir_print_instr(&instr
->instr
, stderr
);
1301 fprintf(stderr
, "\n");
1306 if (dst
.regClass() == v1
) {
1307 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1308 } else if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1311 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1312 nir_print_instr(&instr
->instr
, stderr
);
1313 fprintf(stderr
, "\n");
1318 if (dst
.regClass() == v1
) {
1319 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1320 } else if (dst
.regClass() == s1
) {
1321 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1323 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1324 nir_print_instr(&instr
->instr
, stderr
);
1325 fprintf(stderr
, "\n");
1330 if (dst
.regClass() == v1
) {
1331 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1332 } else if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1335 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1336 nir_print_instr(&instr
->instr
, stderr
);
1337 fprintf(stderr
, "\n");
1342 if (dst
.regClass() == v1
) {
1343 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1344 } else if (dst
.regClass() == s1
) {
1345 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1347 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1348 nir_print_instr(&instr
->instr
, stderr
);
1349 fprintf(stderr
, "\n");
1354 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1355 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1356 } else if (dst
.regClass() == v1
) {
1357 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1358 } else if (dst
.regClass() == v2
) {
1359 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1360 } else if (dst
.regClass() == s1
) {
1361 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1362 } else if (dst
.regClass() == s2
) {
1363 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1365 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1366 nir_print_instr(&instr
->instr
, stderr
);
1367 fprintf(stderr
, "\n");
1372 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1373 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1374 } else if (dst
.regClass() == v1
) {
1375 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1376 } else if (dst
.regClass() == v2
) {
1377 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1378 } else if (dst
.regClass() == s1
) {
1379 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1380 } else if (dst
.regClass() == s2
) {
1381 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1383 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1384 nir_print_instr(&instr
->instr
, stderr
);
1385 fprintf(stderr
, "\n");
1390 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1391 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1392 } else if (dst
.regClass() == v1
) {
1393 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1394 } else if (dst
.regClass() == v2
) {
1395 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1396 } else if (dst
.regClass() == s1
) {
1397 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1398 } else if (dst
.regClass() == s2
) {
1399 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1401 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1402 nir_print_instr(&instr
->instr
, stderr
);
1403 fprintf(stderr
, "\n");
1408 if (dst
.regClass() == v1
) {
1409 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1410 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1411 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1412 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1413 } else if (dst
.regClass() == v2
) {
1414 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1415 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1416 } else if (dst
.regClass() == s2
) {
1417 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1418 } else if (dst
.regClass() == s1
) {
1419 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1421 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1422 nir_print_instr(&instr
->instr
, stderr
);
1423 fprintf(stderr
, "\n");
1428 if (dst
.regClass() == v1
) {
1429 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1430 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1431 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1432 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1433 } else if (dst
.regClass() == v2
) {
1434 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1435 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1436 } else if (dst
.regClass() == s1
) {
1437 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1438 } else if (dst
.regClass() == s2
) {
1439 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1441 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1442 nir_print_instr(&instr
->instr
, stderr
);
1443 fprintf(stderr
, "\n");
1448 if (dst
.regClass() == v1
) {
1449 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1450 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1451 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1452 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1453 } else if (dst
.regClass() == v2
) {
1454 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1455 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1456 } else if (dst
.regClass() == s1
) {
1457 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1458 } else if (dst
.regClass() == s2
) {
1459 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1461 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1462 nir_print_instr(&instr
->instr
, stderr
);
1463 fprintf(stderr
, "\n");
1467 case nir_op_find_lsb
: {
1468 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1469 if (src
.regClass() == s1
) {
1470 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1471 } else if (src
.regClass() == v1
) {
1472 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1473 } else if (src
.regClass() == s2
) {
1474 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1476 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1477 nir_print_instr(&instr
->instr
, stderr
);
1478 fprintf(stderr
, "\n");
1482 case nir_op_ufind_msb
:
1483 case nir_op_ifind_msb
: {
1484 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1485 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1486 aco_opcode op
= src
.regClass() == s2
?
1487 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1488 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1489 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1491 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1492 Operand(src
.size() * 32u - 1u), msb_rev
);
1493 Temp msb
= sub
.def(0).getTemp();
1494 Temp carry
= sub
.def(1).getTemp();
1496 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1497 } else if (src
.regClass() == v1
) {
1498 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1499 Temp msb_rev
= bld
.tmp(v1
);
1500 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1501 Temp msb
= bld
.tmp(v1
);
1502 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1503 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1505 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1506 nir_print_instr(&instr
->instr
, stderr
);
1507 fprintf(stderr
, "\n");
1511 case nir_op_bitfield_reverse
: {
1512 if (dst
.regClass() == s1
) {
1513 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1514 } else if (dst
.regClass() == v1
) {
1515 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1517 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1518 nir_print_instr(&instr
->instr
, stderr
);
1519 fprintf(stderr
, "\n");
1524 if (dst
.regClass() == s1
) {
1525 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1529 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1530 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1531 if (dst
.regClass() == v1
) {
1532 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1536 assert(src0
.size() == 2 && src1
.size() == 2);
1537 Temp src00
= bld
.tmp(src0
.type(), 1);
1538 Temp src01
= bld
.tmp(dst
.type(), 1);
1539 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1540 Temp src10
= bld
.tmp(src1
.type(), 1);
1541 Temp src11
= bld
.tmp(dst
.type(), 1);
1542 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1544 if (dst
.regClass() == s2
) {
1545 Temp carry
= bld
.tmp(s1
);
1546 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1547 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1548 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1549 } else if (dst
.regClass() == v2
) {
1550 Temp dst0
= bld
.tmp(v1
);
1551 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1552 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1561 case nir_op_uadd_sat
: {
1562 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1563 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1564 if (dst
.regClass() == s1
) {
1565 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1566 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1568 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1569 } else if (dst
.regClass() == v1
) {
1570 if (ctx
->options
->chip_class
>= GFX9
) {
1571 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1572 add
->operands
[0] = Operand(src0
);
1573 add
->operands
[1] = Operand(src1
);
1574 add
->definitions
[0] = Definition(dst
);
1576 ctx
->block
->instructions
.emplace_back(std::move(add
));
1578 if (src1
.regClass() != v1
)
1579 std::swap(src0
, src1
);
1580 assert(src1
.regClass() == v1
);
1581 Temp tmp
= bld
.tmp(v1
);
1582 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1583 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1586 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1587 nir_print_instr(&instr
->instr
, stderr
);
1588 fprintf(stderr
, "\n");
1592 case nir_op_uadd_carry
: {
1593 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1594 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1595 if (dst
.regClass() == s1
) {
1596 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1599 if (dst
.regClass() == v1
) {
1600 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1601 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1605 Temp src00
= bld
.tmp(src0
.type(), 1);
1606 Temp src01
= bld
.tmp(dst
.type(), 1);
1607 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1608 Temp src10
= bld
.tmp(src1
.type(), 1);
1609 Temp src11
= bld
.tmp(dst
.type(), 1);
1610 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1611 if (dst
.regClass() == s2
) {
1612 Temp carry
= bld
.tmp(s1
);
1613 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1614 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1615 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1616 } else if (dst
.regClass() == v2
) {
1617 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1618 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1619 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1620 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1622 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1623 nir_print_instr(&instr
->instr
, stderr
);
1624 fprintf(stderr
, "\n");
1629 if (dst
.regClass() == s1
) {
1630 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == v1
) {
1637 bld
.vsub32(Definition(dst
), src0
, src1
);
1641 Temp src00
= bld
.tmp(src0
.type(), 1);
1642 Temp src01
= bld
.tmp(dst
.type(), 1);
1643 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1644 Temp src10
= bld
.tmp(src1
.type(), 1);
1645 Temp src11
= bld
.tmp(dst
.type(), 1);
1646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1647 if (dst
.regClass() == s2
) {
1648 Temp carry
= bld
.tmp(s1
);
1649 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1650 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1651 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1652 } else if (dst
.regClass() == v2
) {
1653 Temp lower
= bld
.tmp(v1
);
1654 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1655 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1656 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1658 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1659 nir_print_instr(&instr
->instr
, stderr
);
1660 fprintf(stderr
, "\n");
1664 case nir_op_usub_borrow
: {
1665 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1666 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1667 if (dst
.regClass() == s1
) {
1668 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1670 } else if (dst
.regClass() == v1
) {
1671 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1672 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1676 Temp src00
= bld
.tmp(src0
.type(), 1);
1677 Temp src01
= bld
.tmp(dst
.type(), 1);
1678 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1679 Temp src10
= bld
.tmp(src1
.type(), 1);
1680 Temp src11
= bld
.tmp(dst
.type(), 1);
1681 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1682 if (dst
.regClass() == s2
) {
1683 Temp borrow
= bld
.tmp(s1
);
1684 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1685 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1686 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1687 } else if (dst
.regClass() == v2
) {
1688 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1689 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1690 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1691 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1693 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1694 nir_print_instr(&instr
->instr
, stderr
);
1695 fprintf(stderr
, "\n");
1700 if (dst
.regClass() == v1
) {
1701 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1702 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1703 } else if (dst
.regClass() == s1
) {
1704 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1706 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1707 nir_print_instr(&instr
->instr
, stderr
);
1708 fprintf(stderr
, "\n");
1712 case nir_op_umul_high
: {
1713 if (dst
.regClass() == v1
) {
1714 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1715 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1716 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1717 } else if (dst
.regClass() == s1
) {
1718 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1719 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1720 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1722 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1723 nir_print_instr(&instr
->instr
, stderr
);
1724 fprintf(stderr
, "\n");
1728 case nir_op_imul_high
: {
1729 if (dst
.regClass() == v1
) {
1730 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1731 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1732 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1733 } else if (dst
.regClass() == s1
) {
1734 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1735 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1736 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1738 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1739 nir_print_instr(&instr
->instr
, stderr
);
1740 fprintf(stderr
, "\n");
1745 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1746 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1747 if (dst
.regClass() == v2b
) {
1748 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1749 } else if (dst
.regClass() == v1
) {
1750 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1751 } else if (dst
.regClass() == v2
) {
1752 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1754 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1755 nir_print_instr(&instr
->instr
, stderr
);
1756 fprintf(stderr
, "\n");
1761 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1762 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1763 if (dst
.regClass() == v2b
) {
1764 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1765 } else if (dst
.regClass() == v1
) {
1766 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1767 } else if (dst
.regClass() == v2
) {
1768 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1770 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1771 nir_print_instr(&instr
->instr
, stderr
);
1772 fprintf(stderr
, "\n");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1779 if (dst
.regClass() == v2b
) {
1780 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1784 } else if (dst
.regClass() == v1
) {
1785 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1786 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1788 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1789 } else if (dst
.regClass() == v2
) {
1790 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1791 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1792 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1796 nir_print_instr(&instr
->instr
, stderr
);
1797 fprintf(stderr
, "\n");
1802 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1803 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1804 if (dst
.regClass() == v2b
) {
1805 // TODO: check fp_mode.must_flush_denorms16_64
1806 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1807 } else if (dst
.regClass() == v1
) {
1808 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1809 } else if (dst
.regClass() == v2
) {
1810 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1811 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1812 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1814 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1817 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1818 nir_print_instr(&instr
->instr
, stderr
);
1819 fprintf(stderr
, "\n");
1824 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1825 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1826 if (dst
.regClass() == v2b
) {
1827 // TODO: check fp_mode.must_flush_denorms16_64
1828 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1829 } else if (dst
.regClass() == v1
) {
1830 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1831 } else if (dst
.regClass() == v2
) {
1832 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1833 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1834 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1836 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1839 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1840 nir_print_instr(&instr
->instr
, stderr
);
1841 fprintf(stderr
, "\n");
1845 case nir_op_fmax3
: {
1846 if (dst
.regClass() == v2b
) {
1847 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1848 } else if (dst
.regClass() == v1
) {
1849 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1851 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1852 nir_print_instr(&instr
->instr
, stderr
);
1853 fprintf(stderr
, "\n");
1857 case nir_op_fmin3
: {
1858 if (dst
.regClass() == v2b
) {
1859 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1860 } else if (dst
.regClass() == v1
) {
1861 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1863 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1864 nir_print_instr(&instr
->instr
, stderr
);
1865 fprintf(stderr
, "\n");
1869 case nir_op_fmed3
: {
1870 if (dst
.regClass() == v2b
) {
1871 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1872 } else if (dst
.regClass() == v1
) {
1873 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1875 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1876 nir_print_instr(&instr
->instr
, stderr
);
1877 fprintf(stderr
, "\n");
1881 case nir_op_umax3
: {
1882 if (dst
.size() == 1) {
1883 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1885 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1886 nir_print_instr(&instr
->instr
, stderr
);
1887 fprintf(stderr
, "\n");
1891 case nir_op_umin3
: {
1892 if (dst
.size() == 1) {
1893 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1895 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1896 nir_print_instr(&instr
->instr
, stderr
);
1897 fprintf(stderr
, "\n");
1901 case nir_op_umed3
: {
1902 if (dst
.size() == 1) {
1903 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_imax3
: {
1912 if (dst
.size() == 1) {
1913 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1915 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1916 nir_print_instr(&instr
->instr
, stderr
);
1917 fprintf(stderr
, "\n");
1921 case nir_op_imin3
: {
1922 if (dst
.size() == 1) {
1923 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1925 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1926 nir_print_instr(&instr
->instr
, stderr
);
1927 fprintf(stderr
, "\n");
1931 case nir_op_imed3
: {
1932 if (dst
.size() == 1) {
1933 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1935 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1936 nir_print_instr(&instr
->instr
, stderr
);
1937 fprintf(stderr
, "\n");
1941 case nir_op_cube_face_coord
: {
1942 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1943 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1944 emit_extract_vector(ctx
, in
, 1, v1
),
1945 emit_extract_vector(ctx
, in
, 2, v1
) };
1946 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1947 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1948 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1949 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1950 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1951 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
), Operand(0x3f000000u
/*0.5*/));
1952 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1953 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
), Operand(0x3f000000u
/*0.5*/));
1954 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1957 case nir_op_cube_face_index
: {
1958 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1959 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1960 emit_extract_vector(ctx
, in
, 1, v1
),
1961 emit_extract_vector(ctx
, in
, 2, v1
) };
1962 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1965 case nir_op_bcsel
: {
1966 emit_bcsel(ctx
, instr
, dst
);
1970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1971 if (dst
.regClass() == v2b
) {
1972 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1973 } else if (dst
.regClass() == v1
) {
1974 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1975 } else if (dst
.regClass() == v2
) {
1976 /* Lowered at NIR level for precision reasons. */
1977 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1979 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1980 nir_print_instr(&instr
->instr
, stderr
);
1981 fprintf(stderr
, "\n");
1986 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1987 if (dst
.regClass() == v2b
) {
1988 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1989 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1990 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1991 } else if (dst
.regClass() == v1
) {
1992 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1993 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1994 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1995 } else if (dst
.regClass() == v2
) {
1996 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1997 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1998 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1999 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2000 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
2001 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2003 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2004 nir_print_instr(&instr
->instr
, stderr
);
2005 fprintf(stderr
, "\n");
2010 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2011 if (dst
.regClass() == v2b
) {
2012 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
2013 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
2014 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
2015 } else if (dst
.regClass() == v1
) {
2016 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
2017 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
2018 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
2019 } else if (dst
.regClass() == v2
) {
2020 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
2021 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
2022 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
2023 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2024 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
2025 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2027 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2028 nir_print_instr(&instr
->instr
, stderr
);
2029 fprintf(stderr
, "\n");
2034 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2035 if (dst
.regClass() == v2b
) {
2036 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
2037 } else if (dst
.regClass() == v1
) {
2038 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2039 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
2040 // TODO: confirm that this holds under any circumstances
2041 } else if (dst
.regClass() == v2
) {
2042 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
2043 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
2046 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2047 nir_print_instr(&instr
->instr
, stderr
);
2048 fprintf(stderr
, "\n");
2052 case nir_op_flog2
: {
2053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2054 if (dst
.regClass() == v2b
) {
2055 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
2056 } else if (dst
.regClass() == v1
) {
2057 emit_log2(ctx
, bld
, Definition(dst
), src
);
2059 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2060 nir_print_instr(&instr
->instr
, stderr
);
2061 fprintf(stderr
, "\n");
2066 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2067 if (dst
.regClass() == v2b
) {
2068 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2069 } else if (dst
.regClass() == v1
) {
2070 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2071 } else if (dst
.regClass() == v2
) {
2072 /* Lowered at NIR level for precision reasons. */
2073 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2075 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2076 nir_print_instr(&instr
->instr
, stderr
);
2077 fprintf(stderr
, "\n");
2081 case nir_op_fexp2
: {
2082 if (dst
.regClass() == v2b
) {
2083 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2084 } else if (dst
.regClass() == v1
) {
2085 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2087 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2088 nir_print_instr(&instr
->instr
, stderr
);
2089 fprintf(stderr
, "\n");
2093 case nir_op_fsqrt
: {
2094 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2095 if (dst
.regClass() == v2b
) {
2096 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2097 } else if (dst
.regClass() == v1
) {
2098 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2099 } else if (dst
.regClass() == v2
) {
2100 /* Lowered at NIR level for precision reasons. */
2101 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2103 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2104 nir_print_instr(&instr
->instr
, stderr
);
2105 fprintf(stderr
, "\n");
2109 case nir_op_ffract
: {
2110 if (dst
.regClass() == v2b
) {
2111 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2112 } else if (dst
.regClass() == v1
) {
2113 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2114 } else if (dst
.regClass() == v2
) {
2115 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2117 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2118 nir_print_instr(&instr
->instr
, stderr
);
2119 fprintf(stderr
, "\n");
2123 case nir_op_ffloor
: {
2124 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2125 if (dst
.regClass() == v2b
) {
2126 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2127 } else if (dst
.regClass() == v1
) {
2128 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2129 } else if (dst
.regClass() == v2
) {
2130 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2133 nir_print_instr(&instr
->instr
, stderr
);
2134 fprintf(stderr
, "\n");
2138 case nir_op_fceil
: {
2139 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2140 if (dst
.regClass() == v2b
) {
2141 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2142 } else if (dst
.regClass() == v1
) {
2143 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2144 } else if (dst
.regClass() == v2
) {
2145 if (ctx
->options
->chip_class
>= GFX7
) {
2146 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2148 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2149 /* trunc = trunc(src0)
2150 * if (src0 > 0.0 && src0 != trunc)
2153 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2154 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2155 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2156 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2157 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2158 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2159 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2162 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2163 nir_print_instr(&instr
->instr
, stderr
);
2164 fprintf(stderr
, "\n");
2168 case nir_op_ftrunc
: {
2169 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2170 if (dst
.regClass() == v2b
) {
2171 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2172 } else if (dst
.regClass() == v1
) {
2173 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2174 } else if (dst
.regClass() == v2
) {
2175 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2177 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2178 nir_print_instr(&instr
->instr
, stderr
);
2179 fprintf(stderr
, "\n");
2183 case nir_op_fround_even
: {
2184 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2185 if (dst
.regClass() == v2b
) {
2186 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2187 } else if (dst
.regClass() == v1
) {
2188 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2189 } else if (dst
.regClass() == v2
) {
2190 if (ctx
->options
->chip_class
>= GFX7
) {
2191 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2193 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2194 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2195 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2197 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2198 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2199 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2200 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2201 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2202 tmp
= sub
->definitions
[0].getTemp();
2204 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2205 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2206 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2207 Temp cond
= vop3
->definitions
[0].getTemp();
2209 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2210 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2211 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2212 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2214 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2217 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2218 nir_print_instr(&instr
->instr
, stderr
);
2219 fprintf(stderr
, "\n");
2225 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2226 aco_ptr
<Instruction
> norm
;
2227 if (dst
.regClass() == v2b
) {
2228 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2229 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2230 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2231 bld
.vop1(opcode
, Definition(dst
), tmp
);
2232 } else if (dst
.regClass() == v1
) {
2233 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2234 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2236 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2237 if (ctx
->options
->chip_class
< GFX9
)
2238 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2240 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2241 bld
.vop1(opcode
, Definition(dst
), tmp
);
2243 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2244 nir_print_instr(&instr
->instr
, stderr
);
2245 fprintf(stderr
, "\n");
2249 case nir_op_ldexp
: {
2250 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2251 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2252 if (dst
.regClass() == v2b
) {
2253 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2254 } else if (dst
.regClass() == v1
) {
2255 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2256 } else if (dst
.regClass() == v2
) {
2257 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2259 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2260 nir_print_instr(&instr
->instr
, stderr
);
2261 fprintf(stderr
, "\n");
2265 case nir_op_frexp_sig
: {
2266 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2267 if (dst
.regClass() == v2b
) {
2268 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2269 } else if (dst
.regClass() == v1
) {
2270 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2271 } else if (dst
.regClass() == v2
) {
2272 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2274 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2275 nir_print_instr(&instr
->instr
, stderr
);
2276 fprintf(stderr
, "\n");
2280 case nir_op_frexp_exp
: {
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2283 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2284 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2285 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2286 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2287 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2288 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2289 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2291 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2292 nir_print_instr(&instr
->instr
, stderr
);
2293 fprintf(stderr
, "\n");
2297 case nir_op_fsign
: {
2298 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2299 if (dst
.regClass() == v2b
) {
2300 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2301 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2302 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2303 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2304 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2305 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2306 } else if (dst
.regClass() == v1
) {
2307 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2308 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2309 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2310 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2311 } else if (dst
.regClass() == v2
) {
2312 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2313 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2314 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2316 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2317 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2318 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2320 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2322 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2323 nir_print_instr(&instr
->instr
, stderr
);
2324 fprintf(stderr
, "\n");
2329 case nir_op_f2f16_rtne
: {
2330 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2331 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2332 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2333 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2334 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2335 * keep value numbering and the scheduler simpler.
2337 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2339 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2342 case nir_op_f2f16_rtz
: {
2343 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2344 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2345 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2346 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2349 case nir_op_f2f32
: {
2350 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2351 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2352 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2353 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2355 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2356 nir_print_instr(&instr
->instr
, stderr
);
2357 fprintf(stderr
, "\n");
2361 case nir_op_f2f64
: {
2362 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2363 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2364 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2365 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2368 case nir_op_i2f16
: {
2369 assert(dst
.regClass() == v2b
);
2370 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2371 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2372 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2373 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2374 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2375 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2378 case nir_op_i2f32
: {
2379 assert(dst
.size() == 1);
2380 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2381 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2382 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2383 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2386 case nir_op_i2f64
: {
2387 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2388 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2389 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2390 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2391 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2392 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2393 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2394 RegClass rc
= RegClass(src
.type(), 1);
2395 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2396 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2397 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2398 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2399 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2400 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2403 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2404 nir_print_instr(&instr
->instr
, stderr
);
2405 fprintf(stderr
, "\n");
2409 case nir_op_u2f16
: {
2410 assert(dst
.regClass() == v2b
);
2411 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2412 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2413 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2414 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2415 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2416 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2419 case nir_op_u2f32
: {
2420 assert(dst
.size() == 1);
2421 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2422 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2423 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2425 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2426 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2427 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2431 case nir_op_u2f64
: {
2432 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2433 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2434 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2435 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2436 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2437 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2438 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2439 RegClass rc
= RegClass(src
.type(), 1);
2440 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2441 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2442 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2443 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2444 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2445 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2447 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2448 nir_print_instr(&instr
->instr
, stderr
);
2449 fprintf(stderr
, "\n");
2454 case nir_op_f2i16
: {
2455 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2456 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2457 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2458 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2460 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2464 case nir_op_f2u16
: {
2465 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2466 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2467 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2468 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2470 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2473 case nir_op_f2i32
: {
2474 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2475 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2476 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2477 if (dst
.type() == RegType::vgpr
) {
2478 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2480 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2481 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2483 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2484 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2485 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2486 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2488 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2489 nir_print_instr(&instr
->instr
, stderr
);
2490 fprintf(stderr
, "\n");
2494 case nir_op_f2u32
: {
2495 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2496 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2497 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2498 if (dst
.type() == RegType::vgpr
) {
2499 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2501 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2502 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2504 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2505 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2506 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2507 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2509 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2510 nir_print_instr(&instr
->instr
, stderr
);
2511 fprintf(stderr
, "\n");
2515 case nir_op_f2i64
: {
2516 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2517 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2518 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2520 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2521 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2522 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2523 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2524 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2525 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2526 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2527 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2528 Temp new_exponent
= bld
.tmp(v1
);
2529 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2530 if (ctx
->program
->chip_class
>= GFX8
)
2531 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2533 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2534 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2535 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2536 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2537 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2538 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2539 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2540 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2541 Temp new_lower
= bld
.tmp(v1
);
2542 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2543 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2544 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2546 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2547 if (src
.type() == RegType::vgpr
)
2548 src
= bld
.as_uniform(src
);
2549 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2550 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2551 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2552 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2553 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2554 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2555 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2556 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2557 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2558 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2559 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2560 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2561 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2562 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2563 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2564 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2565 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2566 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2567 Temp borrow
= bld
.tmp(s1
);
2568 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2569 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2570 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2572 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2573 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2574 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2575 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2576 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2577 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2578 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2579 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2580 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2581 if (dst
.type() == RegType::sgpr
) {
2582 lower
= bld
.as_uniform(lower
);
2583 upper
= bld
.as_uniform(upper
);
2585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2588 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2589 nir_print_instr(&instr
->instr
, stderr
);
2590 fprintf(stderr
, "\n");
2594 case nir_op_f2u64
: {
2595 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2596 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2597 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2599 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2600 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2601 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2602 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2603 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2604 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2605 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2606 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2607 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2608 Temp new_exponent
= bld
.tmp(v1
);
2609 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2610 if (ctx
->program
->chip_class
>= GFX8
)
2611 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2613 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2614 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2615 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2616 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2617 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2618 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2619 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2620 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2622 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2623 if (src
.type() == RegType::vgpr
)
2624 src
= bld
.as_uniform(src
);
2625 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2626 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2627 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2628 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2629 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2630 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2631 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2632 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2633 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2634 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2635 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2636 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2637 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2639 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2640 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2641 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2642 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2644 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2645 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2646 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2647 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2648 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2649 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2650 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2651 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2652 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2653 if (dst
.type() == RegType::sgpr
) {
2654 lower
= bld
.as_uniform(lower
);
2655 upper
= bld
.as_uniform(upper
);
2657 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2660 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2661 nir_print_instr(&instr
->instr
, stderr
);
2662 fprintf(stderr
, "\n");
2666 case nir_op_b2f16
: {
2667 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2668 assert(src
.regClass() == bld
.lm
);
2670 if (dst
.regClass() == s1
) {
2671 src
= bool_to_scalar_condition(ctx
, src
);
2672 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2673 } else if (dst
.regClass() == v2b
) {
2674 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2675 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2677 unreachable("Wrong destination register class for nir_op_b2f16.");
2681 case nir_op_b2f32
: {
2682 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2683 assert(src
.regClass() == bld
.lm
);
2685 if (dst
.regClass() == s1
) {
2686 src
= bool_to_scalar_condition(ctx
, src
);
2687 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2688 } else if (dst
.regClass() == v1
) {
2689 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2691 unreachable("Wrong destination register class for nir_op_b2f32.");
2695 case nir_op_b2f64
: {
2696 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2697 assert(src
.regClass() == bld
.lm
);
2699 if (dst
.regClass() == s2
) {
2700 src
= bool_to_scalar_condition(ctx
, src
);
2701 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2702 } else if (dst
.regClass() == v2
) {
2703 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2704 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2705 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2707 unreachable("Wrong destination register class for nir_op_b2f64.");
2714 case nir_op_i2i64
: {
2715 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2716 /* no need to do the extract in get_alu_src() */
2717 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2718 sgpr_extract_sext
: sgpr_extract_undef
;
2719 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2721 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2722 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2729 case nir_op_u2u64
: {
2730 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2731 /* no need to do the extract in get_alu_src() */
2732 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2733 sgpr_extract_zext
: sgpr_extract_undef
;
2734 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2736 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2737 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2745 case nir_op_b2i64
: {
2746 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2747 assert(src
.regClass() == bld
.lm
);
2749 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2750 if (tmp
.regClass() == s1
) {
2751 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2752 bool_to_scalar_condition(ctx
, src
, tmp
);
2753 } else if (tmp
.type() == RegType::vgpr
) {
2754 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2756 unreachable("Invalid register class for b2i32");
2760 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2765 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2766 assert(dst
.regClass() == bld
.lm
);
2768 if (src
.type() == RegType::vgpr
) {
2769 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2770 assert(dst
.regClass() == bld
.lm
);
2771 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2772 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2774 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2776 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2777 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2779 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2780 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2782 bool_to_vector_condition(ctx
, tmp
, dst
);
2786 case nir_op_pack_64_2x32_split
: {
2787 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2788 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2790 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2793 case nir_op_unpack_64_2x32_split_x
:
2794 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2796 case nir_op_unpack_64_2x32_split_y
:
2797 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2799 case nir_op_unpack_32_2x16_split_x
:
2800 if (dst
.type() == RegType::vgpr
) {
2801 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2803 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2806 case nir_op_unpack_32_2x16_split_y
:
2807 if (dst
.type() == RegType::vgpr
) {
2808 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2810 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2813 case nir_op_pack_32_2x16_split
: {
2814 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2815 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2816 if (dst
.regClass() == v1
) {
2817 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2818 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2819 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2821 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2822 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2823 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2827 case nir_op_pack_half_2x16
: {
2828 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2830 if (dst
.regClass() == v1
) {
2831 Temp src0
= bld
.tmp(v1
);
2832 Temp src1
= bld
.tmp(v1
);
2833 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2834 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2835 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2837 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2838 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2839 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2841 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2842 nir_print_instr(&instr
->instr
, stderr
);
2843 fprintf(stderr
, "\n");
2847 case nir_op_unpack_half_2x16_split_x
: {
2848 if (dst
.regClass() == v1
) {
2849 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2851 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2852 nir_print_instr(&instr
->instr
, stderr
);
2853 fprintf(stderr
, "\n");
2857 case nir_op_unpack_half_2x16_split_y
: {
2858 if (dst
.regClass() == v1
) {
2859 /* TODO: use SDWA here */
2860 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2861 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2863 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2864 nir_print_instr(&instr
->instr
, stderr
);
2865 fprintf(stderr
, "\n");
2869 case nir_op_fquantize2f16
: {
2870 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2871 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2874 if (ctx
->program
->chip_class
>= GFX8
) {
2875 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2876 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2877 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2879 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2880 * so compare the result and flush to 0 if it's smaller.
2882 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2883 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2884 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2885 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2886 cmp_res
= vop3
->definitions
[0].getTemp();
2889 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2890 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2891 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2893 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2898 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2899 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2901 if (dst
.regClass() == s1
) {
2902 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2903 } else if (dst
.regClass() == v1
) {
2904 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2906 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2907 nir_print_instr(&instr
->instr
, stderr
);
2908 fprintf(stderr
, "\n");
2912 case nir_op_bitfield_select
: {
2913 /* (mask & insert) | (~mask & base) */
2914 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2915 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2916 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2918 /* dst = (insert & bitmask) | (base & ~bitmask) */
2919 if (dst
.regClass() == s1
) {
2920 aco_ptr
<Instruction
> sop2
;
2921 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2922 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2924 if (const_insert
&& const_bitmask
) {
2925 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2927 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2928 lhs
= Operand(insert
);
2932 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2933 if (const_base
&& const_bitmask
) {
2934 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2936 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2937 rhs
= Operand(base
);
2940 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2942 } else if (dst
.regClass() == v1
) {
2943 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2944 base
= as_vgpr(ctx
, base
);
2945 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2946 insert
= as_vgpr(ctx
, insert
);
2948 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2951 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2952 nir_print_instr(&instr
->instr
, stderr
);
2953 fprintf(stderr
, "\n");
2959 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2960 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2961 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2963 if (dst
.type() == RegType::sgpr
) {
2965 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2966 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2967 if (const_offset
&& const_bits
) {
2968 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2969 extract
= Operand(const_extract
);
2973 width
= Operand(const_bits
->u32
<< 16);
2975 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2977 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2981 if (dst
.regClass() == s1
) {
2982 if (instr
->op
== nir_op_ubfe
)
2983 opcode
= aco_opcode::s_bfe_u32
;
2985 opcode
= aco_opcode::s_bfe_i32
;
2986 } else if (dst
.regClass() == s2
) {
2987 if (instr
->op
== nir_op_ubfe
)
2988 opcode
= aco_opcode::s_bfe_u64
;
2990 opcode
= aco_opcode::s_bfe_i64
;
2992 unreachable("Unsupported BFE bit size");
2995 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2999 if (dst
.regClass() == v1
) {
3000 if (instr
->op
== nir_op_ubfe
)
3001 opcode
= aco_opcode::v_bfe_u32
;
3003 opcode
= aco_opcode::v_bfe_i32
;
3005 unreachable("Unsupported BFE bit size");
3008 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
3012 case nir_op_bit_count
: {
3013 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3014 if (src
.regClass() == s1
) {
3015 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
3016 } else if (src
.regClass() == v1
) {
3017 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
3018 } else if (src
.regClass() == v2
) {
3019 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
3020 emit_extract_vector(ctx
, src
, 1, v1
),
3021 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
3022 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
3023 } else if (src
.regClass() == s2
) {
3024 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
3026 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
3027 nir_print_instr(&instr
->instr
, stderr
);
3028 fprintf(stderr
, "\n");
3033 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
3037 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
3041 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
3045 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3049 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3053 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3057 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3058 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3060 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3061 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3065 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3066 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3068 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3069 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3073 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3077 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3082 case nir_op_fddx_fine
:
3083 case nir_op_fddy_fine
:
3084 case nir_op_fddx_coarse
:
3085 case nir_op_fddy_coarse
: {
3086 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3087 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3088 if (instr
->op
== nir_op_fddx_fine
) {
3089 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3090 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3091 } else if (instr
->op
== nir_op_fddy_fine
) {
3092 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3093 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3095 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3096 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3097 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3099 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3103 if (ctx
->program
->chip_class
>= GFX8
) {
3104 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3105 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3107 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3108 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3109 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3111 emit_wqm(ctx
, tmp
, dst
, true);
3115 fprintf(stderr
, "Unknown NIR ALU instr: ");
3116 nir_print_instr(&instr
->instr
, stderr
);
3117 fprintf(stderr
, "\n");
3121 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3123 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3125 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3126 // which get truncated the lsb if double and msb if int
3127 // for now, we only use s_mov_b64 with 64bit inline constants
3128 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3129 assert(dst
.type() == RegType::sgpr
);
3131 Builder
bld(ctx
->program
, ctx
->block
);
3133 if (instr
->def
.bit_size
== 1) {
3134 assert(dst
.regClass() == bld
.lm
);
3135 int val
= instr
->value
[0].b
? -1 : 0;
3136 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3137 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3138 } else if (instr
->def
.bit_size
== 8) {
3139 /* ensure that the value is correctly represented in the low byte of the register */
3140 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3141 } else if (instr
->def
.bit_size
== 16) {
3142 /* ensure that the value is correctly represented in the low half of the register */
3143 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3144 } else if (dst
.size() == 1) {
3145 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3147 assert(dst
.size() != 1);
3148 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3149 if (instr
->def
.bit_size
== 64)
3150 for (unsigned i
= 0; i
< dst
.size(); i
++)
3151 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3153 for (unsigned i
= 0; i
< dst
.size(); i
++)
3154 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3156 vec
->definitions
[0] = Definition(dst
);
3157 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3161 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3163 uint32_t new_mask
= 0;
3164 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3165 if (mask
& (1u << i
))
3166 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3170 struct LoadEmitInfo
{
3173 unsigned num_components
;
3174 unsigned component_size
;
3175 Temp resource
= Temp(0, s1
);
3176 unsigned component_stride
= 0;
3177 unsigned const_offset
= 0;
3178 unsigned align_mul
= 0;
3179 unsigned align_offset
= 0;
3182 unsigned swizzle_component_size
= 0;
3183 memory_sync_info sync
;
3184 Temp soffset
= Temp(0, s1
);
3187 using LoadCallback
= Temp(*)(
3188 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3189 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3191 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3192 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3194 unsigned load_size
= info
->num_components
* info
->component_size
;
3195 unsigned component_size
= info
->component_size
;
3197 unsigned num_vals
= 0;
3198 Temp vals
[info
->dst
.bytes()];
3200 unsigned const_offset
= info
->const_offset
;
3202 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3203 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3205 unsigned bytes_read
= 0;
3206 while (bytes_read
< load_size
) {
3207 unsigned bytes_needed
= load_size
- bytes_read
;
3209 /* add buffer for unaligned loads */
3210 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3213 if ((bytes_needed
> 2 ||
3214 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3215 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3216 if (info
->component_stride
) {
3217 assert(supports_8bit_16bit_loads
&& "unimplemented");
3221 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3222 bytes_needed
= align(bytes_needed
, 4);
3229 if (info
->swizzle_component_size
)
3230 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3231 if (info
->component_stride
)
3232 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3234 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3236 /* reduce constant offset */
3237 Operand offset
= info
->offset
;
3238 unsigned reduced_const_offset
= const_offset
;
3239 bool remove_const_offset_completely
= need_to_align_offset
;
3240 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3241 unsigned to_add
= const_offset
;
3242 if (remove_const_offset_completely
) {
3243 reduced_const_offset
= 0;
3245 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3246 reduced_const_offset
%= max_const_offset_plus_one
;
3248 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3249 if (offset
.isConstant()) {
3250 offset
= Operand(offset
.constantValue() + to_add
);
3251 } else if (offset_tmp
.regClass() == s1
) {
3252 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3253 offset_tmp
, Operand(to_add
));
3254 } else if (offset_tmp
.regClass() == v1
) {
3255 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3257 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3258 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3259 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3261 if (offset_tmp
.regClass() == s2
) {
3262 Temp carry
= bld
.tmp(s1
);
3263 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3264 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3265 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3267 Temp new_lo
= bld
.tmp(v1
);
3268 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3269 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3270 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3275 /* align offset down if needed */
3276 Operand aligned_offset
= offset
;
3277 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3278 if (need_to_align_offset
) {
3280 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3281 if (offset
.isConstant()) {
3282 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3283 } else if (offset_tmp
.regClass() == s1
) {
3284 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3285 } else if (offset_tmp
.regClass() == s2
) {
3286 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3287 } else if (offset_tmp
.regClass() == v1
) {
3288 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3289 } else if (offset_tmp
.regClass() == v2
) {
3290 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3291 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3292 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3293 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3296 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3297 bld
.copy(bld
.def(s1
), aligned_offset
);
3299 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3300 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3302 /* the callback wrote directly to dst */
3303 if (val
== info
->dst
) {
3304 assert(num_vals
== 0);
3305 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3309 /* shift result right if needed */
3310 if (info
->component_size
< 4 && byte_align_loads
) {
3311 Operand
align((uint32_t)byte_align
);
3312 if (byte_align
== -1) {
3313 if (offset
.isConstant())
3314 align
= Operand(offset
.constantValue() % 4u);
3315 else if (offset
.size() == 2)
3316 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3321 assert(val
.bytes() >= load_size
&& "unimplemented");
3322 if (val
.type() == RegType::sgpr
)
3323 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3325 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3329 /* add result to list and advance */
3330 if (info
->component_stride
) {
3331 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3332 const_offset
+= info
->component_stride
;
3333 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3335 const_offset
+= val
.bytes();
3336 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3338 bytes_read
+= val
.bytes();
3339 vals
[num_vals
++] = val
;
3342 /* create array of components */
3343 unsigned components_split
= 0;
3344 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3345 bool has_vgprs
= false;
3346 for (unsigned i
= 0; i
< num_vals
;) {
3348 unsigned num_tmps
= 0;
3349 unsigned tmp_size
= 0;
3350 RegType reg_type
= RegType::sgpr
;
3351 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3352 if (vals
[i
].type() == RegType::vgpr
)
3353 reg_type
= RegType::vgpr
;
3354 tmp_size
+= vals
[i
].bytes();
3355 tmp
[num_tmps
++] = vals
[i
++];
3358 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3359 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3360 for (unsigned i
= 0; i
< num_tmps
; i
++)
3361 vec
->operands
[i
] = Operand(tmp
[i
]);
3362 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3363 vec
->definitions
[0] = Definition(tmp
[0]);
3364 bld
.insert(std::move(vec
));
3367 if (tmp
[0].bytes() % component_size
) {
3369 assert(i
== num_vals
);
3370 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3371 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3374 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3376 unsigned start
= components_split
;
3378 if (tmp_size
== elem_rc
.bytes()) {
3379 allocated_vec
[components_split
++] = tmp
[0];
3381 assert(tmp_size
% elem_rc
.bytes() == 0);
3382 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3383 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3384 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3385 Temp component
= bld
.tmp(elem_rc
);
3386 allocated_vec
[components_split
++] = component
;
3387 split
->definitions
[i
] = Definition(component
);
3389 split
->operands
[0] = Operand(tmp
[0]);
3390 bld
.insert(std::move(split
));
3393 /* try to p_as_uniform early so we can create more optimizable code and
3394 * also update allocated_vec */
3395 for (unsigned j
= start
; j
< components_split
; j
++) {
3396 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3397 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3398 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3402 /* concatenate components and p_as_uniform() result if needed */
3403 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3404 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3406 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3408 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3409 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3410 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3411 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3413 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3414 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3415 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3416 vec
->definitions
[0] = Definition(tmp
);
3417 bld
.insert(std::move(vec
));
3418 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3420 vec
->definitions
[0] = Definition(info
->dst
);
3421 bld
.insert(std::move(vec
));
3425 Operand
load_lds_size_m0(Builder
& bld
)
3427 /* TODO: m0 does not need to be initialized on GFX9+ */
3428 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3431 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3432 Temp offset
, unsigned bytes_needed
,
3433 unsigned align
, unsigned const_offset
,
3436 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3438 Operand m
= load_lds_size_m0(bld
);
3440 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3441 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3446 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3447 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3449 op
= aco_opcode::ds_read_b128
;
3450 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3453 op
= aco_opcode::ds_read2_b64
;
3454 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3456 op
= aco_opcode::ds_read_b96
;
3457 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3459 op
= aco_opcode::ds_read_b64
;
3460 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3463 op
= aco_opcode::ds_read2_b32
;
3464 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3466 op
= aco_opcode::ds_read_b32
;
3467 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3469 op
= aco_opcode::ds_read_u16
;
3472 op
= aco_opcode::ds_read_u8
;
3475 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3476 if (const_offset
>= max_offset_plus_one
) {
3477 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3478 const_offset
%= max_offset_plus_one
;
3482 const_offset
/= (size
/ 2u);
3484 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3485 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3488 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3490 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3491 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3494 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3499 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3501 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3502 Temp offset
, unsigned bytes_needed
,
3503 unsigned align
, unsigned const_offset
,
3508 if (bytes_needed
<= 4) {
3510 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3511 } else if (bytes_needed
<= 8) {
3513 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3514 } else if (bytes_needed
<= 16) {
3516 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3517 } else if (bytes_needed
<= 32) {
3519 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3522 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3524 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3525 if (info
->resource
.id()) {
3526 load
->operands
[0] = Operand(info
->resource
);
3527 load
->operands
[1] = Operand(offset
);
3529 load
->operands
[0] = Operand(offset
);
3530 load
->operands
[1] = Operand(0u);
3532 RegClass
rc(RegType::sgpr
, size
);
3533 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3534 load
->definitions
[0] = Definition(val
);
3535 load
->glc
= info
->glc
;
3536 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3537 load
->sync
= info
->sync
;
3538 bld
.insert(std::move(load
));
3542 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3544 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3545 Temp offset
, unsigned bytes_needed
,
3546 unsigned align_
, unsigned const_offset
,
3549 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3550 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3552 if (info
->soffset
.id()) {
3553 if (soffset
.isTemp())
3554 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3555 soffset
= Operand(info
->soffset
);
3558 unsigned bytes_size
= 0;
3560 if (bytes_needed
== 1 || align_
% 2) {
3562 op
= aco_opcode::buffer_load_ubyte
;
3563 } else if (bytes_needed
== 2 || align_
% 4) {
3565 op
= aco_opcode::buffer_load_ushort
;
3566 } else if (bytes_needed
<= 4) {
3568 op
= aco_opcode::buffer_load_dword
;
3569 } else if (bytes_needed
<= 8) {
3571 op
= aco_opcode::buffer_load_dwordx2
;
3572 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3574 op
= aco_opcode::buffer_load_dwordx3
;
3577 op
= aco_opcode::buffer_load_dwordx4
;
3579 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3580 mubuf
->operands
[0] = Operand(info
->resource
);
3581 mubuf
->operands
[1] = vaddr
;
3582 mubuf
->operands
[2] = soffset
;
3583 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3584 mubuf
->glc
= info
->glc
;
3585 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3586 mubuf
->sync
= info
->sync
;
3587 mubuf
->offset
= const_offset
;
3588 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3589 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3590 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3591 mubuf
->definitions
[0] = Definition(val
);
3592 bld
.insert(std::move(mubuf
));
3597 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3598 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3600 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3602 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3603 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3605 if (addr
.type() == RegType::vgpr
)
3606 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3607 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3610 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3611 Temp offset
, unsigned bytes_needed
,
3612 unsigned align_
, unsigned const_offset
,
3615 unsigned bytes_size
= 0;
3616 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3617 bool global
= bld
.program
->chip_class
>= GFX9
;
3619 if (bytes_needed
== 1) {
3621 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3622 } else if (bytes_needed
== 2) {
3624 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3625 } else if (bytes_needed
<= 4) {
3627 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3628 } else if (bytes_needed
<= 8) {
3630 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3631 } else if (bytes_needed
<= 12 && !mubuf
) {
3633 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3636 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3638 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3639 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3641 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3642 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3643 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3644 mubuf
->operands
[2] = Operand(0u);
3645 mubuf
->glc
= info
->glc
;
3648 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3649 mubuf
->disable_wqm
= false;
3650 mubuf
->sync
= info
->sync
;
3651 mubuf
->definitions
[0] = Definition(val
);
3652 bld
.insert(std::move(mubuf
));
3654 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3656 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3657 flat
->operands
[0] = Operand(offset
);
3658 flat
->operands
[1] = Operand(s1
);
3659 flat
->glc
= info
->glc
;
3660 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3661 flat
->sync
= info
->sync
;
3663 flat
->definitions
[0] = Definition(val
);
3664 bld
.insert(std::move(flat
));
3670 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3672 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3673 Temp address
, unsigned base_offset
, unsigned align
)
3675 assert(util_is_power_of_two_nonzero(align
));
3677 Builder
bld(ctx
->program
, ctx
->block
);
3679 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3680 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3681 info
.align_mul
= align
;
3682 info
.align_offset
= 0;
3683 info
.sync
= memory_sync_info(storage_shared
);
3684 info
.const_offset
= base_offset
;
3685 emit_lds_load(ctx
, bld
, &info
);
3690 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3695 Builder
bld(ctx
->program
, ctx
->block
);
3697 ASSERTED
bool is_subdword
= false;
3698 for (unsigned i
= 0; i
< count
; i
++)
3699 is_subdword
|= offsets
[i
] % 4;
3700 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3701 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3703 /* count == 1 fast path */
3705 if (dst_type
== RegType::sgpr
)
3706 dst
[0] = bld
.as_uniform(src
);
3708 dst
[0] = as_vgpr(ctx
, src
);
3712 for (unsigned i
= 0; i
< count
- 1; i
++)
3713 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3714 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3716 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3717 src
= as_vgpr(ctx
, src
);
3719 /* use allocated_vec if possible */
3720 auto it
= ctx
->allocated_vec
.find(src
.id());
3721 if (it
!= ctx
->allocated_vec
.end()) {
3722 if (!it
->second
[0].id())
3724 unsigned elem_size
= it
->second
[0].bytes();
3725 assert(src
.bytes() % elem_size
== 0);
3727 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3728 if (!it
->second
[i
].id())
3732 for (unsigned i
= 0; i
< count
; i
++) {
3733 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3737 for (unsigned i
= 0; i
< count
; i
++) {
3738 unsigned start_idx
= offsets
[i
] / elem_size
;
3739 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3740 if (op_count
== 1) {
3741 if (dst_type
== RegType::sgpr
)
3742 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3744 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3748 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3749 for (unsigned j
= 0; j
< op_count
; j
++) {
3750 Temp tmp
= it
->second
[start_idx
+ j
];
3751 if (dst_type
== RegType::sgpr
)
3752 tmp
= bld
.as_uniform(tmp
);
3753 vec
->operands
[j
] = Operand(tmp
);
3755 vec
->definitions
[0] = Definition(dst
[i
]);
3756 bld
.insert(std::move(vec
));
3764 if (dst_type
== RegType::sgpr
)
3765 src
= bld
.as_uniform(src
);
3768 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3769 split
->operands
[0] = Operand(src
);
3770 for (unsigned i
= 0; i
< count
; i
++)
3771 split
->definitions
[i
] = Definition(dst
[i
]);
3772 bld
.insert(std::move(split
));
3775 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3776 int *start
, int *count
)
3778 unsigned start_elem
= ffs(todo_mask
) - 1;
3779 bool skip
= !(mask
& (1 << start_elem
));
3781 mask
= ~mask
& todo_mask
;
3785 u_bit_scan_consecutive_range(&mask
, start
, count
);
3790 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3792 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3795 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3796 Temp address
, unsigned base_offset
, unsigned align
)
3798 assert(util_is_power_of_two_nonzero(align
));
3799 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3801 Builder
bld(ctx
->program
, ctx
->block
);
3802 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3803 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3805 unsigned write_count
= 0;
3806 Temp write_datas
[32];
3807 unsigned offsets
[32];
3808 aco_opcode opcodes
[32];
3810 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3812 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3815 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3816 offsets
[write_count
] = offset
;
3817 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3819 advance_write_mask(&todo
, offset
, bytes
);
3823 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3824 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3825 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3826 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3828 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3829 aco_opcode op
= aco_opcode::num_opcodes
;
3830 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3831 op
= aco_opcode::ds_write_b128
;
3833 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3834 op
= aco_opcode::ds_write_b96
;
3836 } else if (bytes
>= 8 && aligned8
) {
3837 op
= aco_opcode::ds_write_b64
;
3839 } else if (bytes
>= 4 && aligned4
) {
3840 op
= aco_opcode::ds_write_b32
;
3842 } else if (bytes
>= 2 && aligned2
) {
3843 op
= aco_opcode::ds_write_b16
;
3845 } else if (bytes
>= 1) {
3846 op
= aco_opcode::ds_write_b8
;
3852 offsets
[write_count
] = offset
;
3853 opcodes
[write_count
] = op
;
3855 advance_write_mask(&todo
, offset
, bytes
);
3858 Operand m
= load_lds_size_m0(bld
);
3860 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3862 for (unsigned i
= 0; i
< write_count
; i
++) {
3863 aco_opcode op
= opcodes
[i
];
3864 if (op
== aco_opcode::num_opcodes
)
3867 Temp data
= write_datas
[i
];
3869 unsigned second
= write_count
;
3870 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3871 for (second
= i
+ 1; second
< write_count
; second
++) {
3872 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3873 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3874 opcodes
[second
] = aco_opcode::num_opcodes
;
3880 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3881 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3883 unsigned inline_offset
= base_offset
+ offsets
[i
];
3884 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3885 Temp address_offset
= address
;
3886 if (inline_offset
> max_offset
) {
3887 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3888 inline_offset
= offsets
[i
];
3890 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3894 Temp second_data
= write_datas
[second
];
3895 inline_offset
/= data
.bytes();
3896 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3898 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3900 static_cast<DS_instruction
*>(instr
)->sync
=
3901 memory_sync_info(storage_shared
);
3905 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3907 unsigned align
= 16;
3909 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3915 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3920 return aco_opcode::buffer_store_byte
;
3923 return aco_opcode::buffer_store_short
;
3925 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3927 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3930 return aco_opcode::buffer_store_dwordx3
;
3932 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3934 unreachable("Unexpected store size");
3935 return aco_opcode::num_opcodes
;
3938 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3939 Temp data
, unsigned writemask
, int swizzle_element_size
,
3940 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3942 unsigned write_count_with_skips
= 0;
3945 /* determine how to split the data */
3946 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3949 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3950 offsets
[write_count_with_skips
] = offset
;
3951 if (skips
[write_count_with_skips
]) {
3952 advance_write_mask(&todo
, offset
, bytes
);
3953 write_count_with_skips
++;
3957 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3958 * larger than swizzle_element_size */
3959 bytes
= MIN2(bytes
, swizzle_element_size
);
3961 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3963 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3964 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3967 /* dword or larger stores have to be dword-aligned */
3968 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3969 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3970 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3972 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3974 advance_write_mask(&todo
, offset
, bytes
);
3975 write_count_with_skips
++;
3978 /* actually split data */
3979 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3982 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3985 write_datas
[*write_count
] = write_datas
[i
];
3986 offsets
[*write_count
] = offsets
[i
];
3991 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3992 unsigned split_cnt
= 0u, Temp dst
= Temp())
3994 Builder
bld(ctx
->program
, ctx
->block
);
3995 unsigned dword_size
= elem_size_bytes
/ 4;
3998 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
4000 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
4001 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
4002 instr
->definitions
[0] = Definition(dst
);
4004 for (unsigned i
= 0; i
< cnt
; ++i
) {
4006 assert(arr
[i
].size() == dword_size
);
4007 allocated_vec
[i
] = arr
[i
];
4008 instr
->operands
[i
] = Operand(arr
[i
]);
4010 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
4011 allocated_vec
[i
] = zero
;
4012 instr
->operands
[i
] = Operand(zero
);
4016 bld
.insert(std::move(instr
));
4019 emit_split_vector(ctx
, dst
, split_cnt
);
4021 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
4026 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
4028 if (const_offset
>= 4096) {
4029 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
4030 const_offset
%= 4096u;
4033 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
4034 else if (unlikely(voffset
.regClass() == s1
))
4035 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
4036 else if (likely(voffset
.regClass() == v1
))
4037 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
4039 unreachable("Unsupported register class of voffset");
4042 return const_offset
;
4045 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
4046 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
4047 bool slc
= false, bool swizzled
= false)
4050 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
4051 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
4053 Builder
bld(ctx
->program
, ctx
->block
);
4054 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
4055 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
4057 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
4058 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
4059 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
4060 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
4061 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
4062 /* dlc*/ false, /* slc */ slc
);
4064 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
4067 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
4068 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
4069 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
4071 Builder
bld(ctx
->program
, ctx
->block
);
4072 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4074 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
4076 unsigned write_count
= 0;
4077 Temp write_datas
[32];
4078 unsigned offsets
[32];
4079 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
4080 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4082 for (unsigned i
= 0; i
< write_count
; i
++) {
4083 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4084 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
4088 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4089 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4090 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4092 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4093 assert((num_components
* elem_size_bytes
) == dst
.bytes());
4094 assert(!!stride
!= allow_combining
);
4096 Builder
bld(ctx
->program
, ctx
->block
);
4098 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4099 info
.component_stride
= allow_combining
? 0 : stride
;
4101 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4102 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4103 info
.align_offset
= 0;
4104 info
.soffset
= soffset
;
4105 info
.const_offset
= base_const_offset
;
4106 emit_mubuf_load(ctx
, bld
, &info
);
4109 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4111 Builder
bld(ctx
->program
, ctx
->block
);
4112 Temp offset
= base_offset
.first
;
4113 unsigned const_offset
= base_offset
.second
;
4115 if (!nir_src_is_const(*off_src
)) {
4116 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4119 /* Calculate indirect offset with stride */
4120 if (likely(indirect_offset_arg
.regClass() == v1
))
4121 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4122 else if (indirect_offset_arg
.regClass() == s1
)
4123 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4125 unreachable("Unsupported register class of indirect offset");
4127 /* Add to the supplied base offset */
4128 if (offset
.id() == 0)
4129 offset
= with_stride
;
4130 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4131 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4132 else if (offset
.size() == 1 && with_stride
.size() == 1)
4133 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4135 unreachable("Unsupported register class of indirect offset");
4137 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4138 const_offset
+= const_offset_arg
* stride
;
4141 return std::make_pair(offset
, const_offset
);
4144 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4146 Builder
bld(ctx
->program
, ctx
->block
);
4149 if (off1
.first
.id() && off2
.first
.id()) {
4150 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4151 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4152 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4153 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4155 unreachable("Unsupported register class of indirect offset");
4157 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4160 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4163 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4165 Builder
bld(ctx
->program
, ctx
->block
);
4166 unsigned const_offset
= offs
.second
* multiplier
;
4168 if (!offs
.first
.id())
4169 return std::make_pair(offs
.first
, const_offset
);
4171 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4172 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4173 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4175 return std::make_pair(offset
, const_offset
);
4178 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4180 Builder
bld(ctx
->program
, ctx
->block
);
4182 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4183 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4184 /* component is in bytes */
4185 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4187 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4188 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4189 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4192 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4194 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4197 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4199 Builder
bld(ctx
->program
, ctx
->block
);
4201 switch (ctx
->shader
->info
.stage
) {
4202 case MESA_SHADER_TESS_CTRL
:
4203 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4204 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4205 case MESA_SHADER_TESS_EVAL
:
4206 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4208 unreachable("Unsupported stage in get_tess_rel_patch_id");
4212 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4214 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4215 Builder
bld(ctx
->program
, ctx
->block
);
4217 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4218 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4220 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4222 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4223 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4225 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4226 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4227 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4229 return offset_mul(ctx
, offs
, 4u);
4232 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4234 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4235 Builder
bld(ctx
->program
, ctx
->block
);
4237 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4238 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4239 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4240 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4242 std::pair
<Temp
, unsigned> offs
= instr
4243 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4244 : std::make_pair(Temp(), 0u);
4246 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4247 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4252 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4253 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4255 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4256 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4258 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4259 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4265 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4267 Builder
bld(ctx
->program
, ctx
->block
);
4269 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4270 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4272 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4274 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4275 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4276 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4278 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4279 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4284 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4286 Builder
bld(ctx
->program
, ctx
->block
);
4288 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4289 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4290 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4291 unsigned attr_stride
= ctx
->tcs_num_patches
;
4293 std::pair
<Temp
, unsigned> offs
= instr
4294 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4295 : std::make_pair(Temp(), 0u);
4297 if (const_base_offset
)
4298 offs
.second
+= const_base_offset
* attr_stride
;
4300 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4301 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4302 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4307 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4309 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4314 unsigned drv_loc
= nir_intrinsic_base(instr
);
4315 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4317 if (!nir_src_is_const(*off_src
)) {
4323 uint64_t slot
= per_vertex
4324 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4325 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4326 return (((uint64_t) 1) << slot
) & mask
;
4329 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4331 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4332 unsigned component
= nir_intrinsic_component(instr
);
4333 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4335 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4336 if (off_instr
->type
!= nir_instr_type_load_const
)
4339 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4340 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4342 if (instr
->src
[0].ssa
->bit_size
== 64)
4343 write_mask
= widen_mask(write_mask
, 2);
4345 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4347 for (unsigned i
= 0; i
< 8; ++i
) {
4348 if (write_mask
& (1 << i
)) {
4349 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4350 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4358 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4360 /* Only TCS per-vertex inputs are supported by this function.
4361 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4363 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4366 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4367 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4368 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4369 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4370 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4371 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4376 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4377 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4378 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4383 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4385 Builder
bld(ctx
->program
, ctx
->block
);
4387 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4388 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4389 bool indirect_write
;
4390 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4391 if (temp_only_input
&& !indirect_write
)
4395 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4396 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4397 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4398 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4400 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4401 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4402 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4403 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4404 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4408 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4409 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4410 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4411 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4412 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4413 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4414 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4415 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4416 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4417 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4418 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4419 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4420 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4422 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4423 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4425 unreachable("Invalid LS or ES stage");
4428 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4429 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4430 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4434 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4439 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4440 return off
== ctx
->tcs_tess_lvl_out_loc
||
4441 off
== ctx
->tcs_tess_lvl_in_loc
;
4445 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4447 uint64_t mask
= per_vertex
4448 ? ctx
->program
->info
->tcs
.tes_inputs_read
4449 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4451 bool indirect_write
= false;
4452 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4453 return indirect_write
|| output_read_by_tes
;
4456 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4458 uint64_t mask
= per_vertex
4459 ? ctx
->shader
->info
.outputs_read
4460 : ctx
->shader
->info
.patch_outputs_read
;
4462 bool indirect_write
= false;
4463 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4464 return indirect_write
|| output_read
;
4467 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4469 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4470 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4472 Builder
bld(ctx
->program
, ctx
->block
);
4474 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4475 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4476 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4478 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4479 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4480 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4482 if (write_to_vmem
) {
4483 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4484 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4485 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4487 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4488 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4489 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4493 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4494 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4495 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4499 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4501 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4502 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4504 Builder
bld(ctx
->program
, ctx
->block
);
4506 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4507 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4508 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4509 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4511 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4514 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4516 if (ctx
->stage
== vertex_vs
||
4517 ctx
->stage
== tess_eval_vs
||
4518 ctx
->stage
== fragment_fs
||
4519 ctx
->stage
== ngg_vertex_gs
||
4520 ctx
->stage
== ngg_tess_eval_gs
||
4521 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4522 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4523 if (!stored_to_temps
) {
4524 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4525 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4526 fprintf(stderr
, "\n");
4529 } else if (ctx
->stage
== vertex_es
||
4530 ctx
->stage
== vertex_ls
||
4531 ctx
->stage
== tess_eval_es
||
4532 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4533 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4534 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4535 visit_store_ls_or_es_output(ctx
, instr
);
4536 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4537 visit_store_tcs_output(ctx
, instr
, false);
4539 unreachable("Shader stage not implemented");
4543 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4545 visit_load_tcs_output(ctx
, instr
, false);
4548 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4550 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4551 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4553 Builder
bld(ctx
->program
, ctx
->block
);
4555 if (dst
.regClass() == v2b
) {
4556 if (ctx
->program
->has_16bank_lds
) {
4557 assert(ctx
->options
->chip_class
<= GFX8
);
4558 Builder::Result interp_p1
=
4559 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4560 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4561 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4562 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4563 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4564 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4566 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4568 if (ctx
->options
->chip_class
== GFX8
)
4569 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4571 Builder::Result interp_p1
=
4572 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4573 coord1
, bld
.m0(prim_mask
), idx
, component
);
4574 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4575 interp_p1
, idx
, component
);
4578 Builder::Result interp_p1
=
4579 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4580 bld
.m0(prim_mask
), idx
, component
);
4582 if (ctx
->program
->has_16bank_lds
)
4583 interp_p1
.instr
->operands
[0].setLateKill(true);
4585 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4586 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4590 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4592 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4593 for (unsigned i
= 0; i
< num_components
; i
++)
4594 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4595 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4596 assert(num_components
== 4);
4597 Builder
bld(ctx
->program
, ctx
->block
);
4598 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4601 for (Operand
& op
: vec
->operands
)
4602 op
= op
.isUndefined() ? Operand(0u) : op
;
4604 vec
->definitions
[0] = Definition(dst
);
4605 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4606 emit_split_vector(ctx
, dst
, num_components
);
4610 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4612 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4613 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4614 unsigned idx
= nir_intrinsic_base(instr
);
4615 unsigned component
= nir_intrinsic_component(instr
);
4616 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4618 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4620 assert(offset
->u32
== 0);
4622 /* the lower 15bit of the prim_mask contain the offset into LDS
4623 * while the upper bits contain the number of prims */
4624 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4625 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4626 Builder
bld(ctx
->program
, ctx
->block
);
4627 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4628 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4629 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4630 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4631 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4634 if (instr
->dest
.ssa
.num_components
== 1) {
4635 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4637 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4638 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4640 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4641 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4642 vec
->operands
[i
] = Operand(tmp
);
4644 vec
->definitions
[0] = Definition(dst
);
4645 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4649 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4650 unsigned offset
, unsigned stride
, unsigned channels
)
4652 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4653 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4655 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4656 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4659 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4660 unsigned offset
, unsigned stride
, unsigned *channels
)
4662 if (!vtx_info
->chan_byte_size
) {
4663 *channels
= vtx_info
->num_channels
;
4664 return vtx_info
->chan_format
;
4667 unsigned num_channels
= *channels
;
4668 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4669 unsigned new_channels
= num_channels
+ 1;
4670 /* first, assume more loads is worse and try using a larger data format */
4671 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4673 /* don't make the attribute potentially out-of-bounds */
4674 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4678 if (new_channels
== 5) {
4679 /* then try decreasing load size (at the cost of more loads) */
4680 new_channels
= *channels
;
4681 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4685 if (new_channels
< *channels
)
4686 *channels
= new_channels
;
4687 num_channels
= new_channels
;
4690 switch (vtx_info
->chan_format
) {
4691 case V_008F0C_BUF_DATA_FORMAT_8
:
4692 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4693 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4694 case V_008F0C_BUF_DATA_FORMAT_16
:
4695 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4696 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4697 case V_008F0C_BUF_DATA_FORMAT_32
:
4698 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4699 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4701 unreachable("shouldn't reach here");
4702 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4705 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4706 * so we may need to fix it up. */
4707 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4709 Builder
bld(ctx
->program
, ctx
->block
);
4711 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4712 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4714 /* For the integer-like cases, do a natural sign extension.
4716 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4717 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4720 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4721 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4723 /* Convert back to the right type. */
4724 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4725 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4726 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4727 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4728 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4729 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4735 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4737 Builder
bld(ctx
->program
, ctx
->block
);
4738 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4739 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4741 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4742 if (off_instr
->type
!= nir_instr_type_load_const
) {
4743 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4744 nir_print_instr(off_instr
, stderr
);
4745 fprintf(stderr
, "\n");
4747 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4749 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4751 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4752 unsigned component
= nir_intrinsic_component(instr
);
4753 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4754 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4755 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4756 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4757 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4759 unsigned dfmt
= attrib_format
& 0xf;
4760 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4761 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4763 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4764 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4765 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4766 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4768 num_channels
= MAX2(num_channels
, 3);
4770 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4771 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4774 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4775 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4776 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4778 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4780 Temp divided
= bld
.tmp(v1
);
4781 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4782 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4784 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4787 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4790 index
= bld
.vadd32(bld
.def(v1
),
4791 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4792 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4795 Temp channels
[num_channels
];
4796 unsigned channel_start
= 0;
4797 bool direct_fetch
= false;
4799 /* skip unused channels at the start */
4800 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4801 channel_start
= ffs(mask
) - 1;
4802 for (unsigned i
= 0; i
< channel_start
; i
++)
4803 channels
[i
] = Temp(0, s1
);
4804 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4805 num_channels
= 3 - (ffs(mask
) - 1);
4809 while (channel_start
< num_channels
) {
4810 unsigned fetch_component
= num_channels
- channel_start
;
4811 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4812 bool expanded
= false;
4814 /* use MUBUF when possible to avoid possible alignment issues */
4815 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4816 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4817 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4818 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4819 vtx_info
->chan_byte_size
== 4;
4820 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4822 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4824 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4825 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4826 fetch_component
= 4;
4831 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4833 Temp fetch_index
= index
;
4834 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4835 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4836 fetch_offset
= fetch_offset
% attrib_stride
;
4839 Operand
soffset(0u);
4840 if (fetch_offset
>= 4096) {
4841 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4842 fetch_offset
%= 4096;
4846 switch (fetch_bytes
) {
4848 assert(!use_mubuf
&& bitsize
== 16);
4849 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4852 if (bitsize
== 16) {
4854 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4856 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4860 assert(!use_mubuf
&& bitsize
== 16);
4861 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4864 if (bitsize
== 16) {
4866 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4868 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4872 assert(ctx
->options
->chip_class
>= GFX7
||
4873 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4874 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4877 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4880 unreachable("Unimplemented load_input vector size");
4884 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4885 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4886 num_channels
<= 3)) {
4887 direct_fetch
= true;
4890 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4895 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4896 fetch_offset
, false, false, true).instr
;
4899 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4900 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4903 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4905 if (fetch_component
== 1) {
4906 channels
[channel_start
] = fetch_dst
;
4908 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4909 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4910 bitsize
== 16 ? v2b
: v1
);
4913 channel_start
+= fetch_component
;
4916 if (!direct_fetch
) {
4917 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4918 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4920 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4921 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4922 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4924 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4925 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4926 unsigned num_temp
= 0;
4927 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4928 unsigned idx
= i
+ component
;
4929 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4930 Temp channel
= channels
[swizzle
[idx
]];
4931 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4932 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4933 vec
->operands
[i
] = Operand(channel
);
4937 } else if (is_float
&& idx
== 3) {
4938 vec
->operands
[i
] = Operand(0x3f800000u
);
4939 } else if (!is_float
&& idx
== 3) {
4940 vec
->operands
[i
] = Operand(1u);
4942 vec
->operands
[i
] = Operand(0u);
4945 vec
->definitions
[0] = Definition(dst
);
4946 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4947 emit_split_vector(ctx
, dst
, dst
.size());
4949 if (num_temp
== dst
.size())
4950 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4952 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4953 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4954 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4955 if (off_instr
->type
!= nir_instr_type_load_const
||
4956 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4957 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4958 nir_print_instr(off_instr
, stderr
);
4959 fprintf(stderr
, "\n");
4962 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4963 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4965 assert(offset
->u32
== 0);
4967 /* the lower 15bit of the prim_mask contain the offset into LDS
4968 * while the upper bits contain the number of prims */
4969 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4970 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4971 Builder
bld(ctx
->program
, ctx
->block
);
4972 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4973 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4974 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4975 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4976 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4979 unsigned idx
= nir_intrinsic_base(instr
);
4980 unsigned component
= nir_intrinsic_component(instr
);
4981 unsigned vertex_id
= 2; /* P0 */
4983 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4984 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4985 switch (src0
->u32
) {
4987 vertex_id
= 2; /* P0 */
4990 vertex_id
= 0; /* P10 */
4993 vertex_id
= 1; /* P20 */
4996 unreachable("invalid vertex index");
5000 if (dst
.size() == 1) {
5001 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
5003 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
5004 for (unsigned i
= 0; i
< dst
.size(); i
++)
5005 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
5006 vec
->definitions
[0] = Definition(dst
);
5007 bld
.insert(std::move(vec
));
5010 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
5011 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5012 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
5013 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
5014 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
5016 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
5018 unreachable("Shader stage not implemented");
5022 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
5024 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5026 Builder
bld(ctx
->program
, ctx
->block
);
5027 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
5030 if (!nir_src_is_const(*vertex_src
)) {
5031 /* better code could be created, but this case probably doesn't happen
5032 * much in practice */
5033 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
5034 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
5037 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5038 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
5040 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
5042 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
5045 if (vertex_offset
.id()) {
5046 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
5047 Operand(i
), indirect_vertex
);
5048 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
5050 vertex_offset
= elem
;
5054 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5055 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
5057 unsigned vertex
= nir_src_as_uint(*vertex_src
);
5058 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5059 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5060 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
5061 Operand((vertex
% 2u) * 16u), Operand(16u));
5063 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
5066 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
5067 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
5068 return offset_mul(ctx
, offs
, 4u);
5071 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5073 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5075 Builder
bld(ctx
->program
, ctx
->block
);
5076 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5077 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5079 if (ctx
->stage
== geometry_gs
) {
5080 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
5081 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
5082 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
5083 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5084 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
5085 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5086 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5088 unreachable("Unsupported GS stage.");
5092 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5094 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5096 Builder
bld(ctx
->program
, ctx
->block
);
5097 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5099 if (load_input_from_temps(ctx
, instr
, dst
))
5102 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5103 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5104 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5106 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5109 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5111 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5113 Builder
bld(ctx
->program
, ctx
->block
);
5115 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5116 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5117 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5119 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5120 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5122 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5125 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5127 switch (ctx
->shader
->info
.stage
) {
5128 case MESA_SHADER_GEOMETRY
:
5129 visit_load_gs_per_vertex_input(ctx
, instr
);
5131 case MESA_SHADER_TESS_CTRL
:
5132 visit_load_tcs_per_vertex_input(ctx
, instr
);
5134 case MESA_SHADER_TESS_EVAL
:
5135 visit_load_tes_per_vertex_input(ctx
, instr
);
5138 unreachable("Unimplemented shader stage");
5142 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5144 visit_load_tcs_output(ctx
, instr
, true);
5147 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5149 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5150 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5152 visit_store_tcs_output(ctx
, instr
, true);
5155 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5157 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5159 Builder
bld(ctx
->program
, ctx
->block
);
5160 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5162 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5163 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5166 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5167 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5168 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5169 tes_w
= Operand(tmp
);
5172 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5173 emit_split_vector(ctx
, tess_coord
, 3);
5176 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5178 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5179 Builder
bld(ctx
->program
, ctx
->block
);
5180 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5181 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5182 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5185 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5189 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5191 Builder
bld(ctx
->program
, ctx
->block
);
5192 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5193 if (!nir_dest_is_divergent(instr
->dest
))
5194 index
= bld
.as_uniform(index
);
5195 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5196 unsigned binding
= nir_intrinsic_binding(instr
);
5199 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5200 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5201 unsigned offset
= layout
->binding
[binding
].offset
;
5203 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5204 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5205 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5206 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5207 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5210 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5211 stride
= layout
->binding
[binding
].size
;
5214 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5215 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5217 if (nir_const_index
) {
5218 const_index
= const_index
* stride
;
5219 } else if (index
.type() == RegType::vgpr
) {
5220 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5221 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5223 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5227 if (nir_const_index
) {
5228 const_index
= const_index
+ offset
;
5229 } else if (index
.type() == RegType::vgpr
) {
5230 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5232 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5236 if (nir_const_index
&& const_index
== 0) {
5238 } else if (index
.type() == RegType::vgpr
) {
5239 index
= bld
.vadd32(bld
.def(v1
),
5240 nir_const_index
? Operand(const_index
) : Operand(index
),
5243 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5244 nir_const_index
? Operand(const_index
) : Operand(index
),
5248 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5251 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5252 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5253 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5255 Builder
bld(ctx
->program
, ctx
->block
);
5257 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5259 offset
= bld
.as_uniform(offset
);
5261 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5264 info
.align_mul
= align_mul
;
5265 info
.align_offset
= align_offset
;
5267 emit_smem_load(ctx
, bld
, &info
);
5269 emit_mubuf_load(ctx
, bld
, &info
);
5272 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5274 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5275 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5277 Builder
bld(ctx
->program
, ctx
->block
);
5279 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5280 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5281 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5282 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5284 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5285 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5286 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5287 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5288 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5289 if (ctx
->options
->chip_class
>= GFX10
) {
5290 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5291 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5292 S_008F0C_RESOURCE_LEVEL(1);
5294 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5295 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5297 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5298 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5299 Operand(0xFFFFFFFFu
),
5300 Operand(desc_type
));
5301 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5302 rsrc
, upper_dwords
);
5304 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5305 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5307 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5308 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5309 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5312 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5314 Builder
bld(ctx
->program
, ctx
->block
);
5315 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5316 unsigned offset
= nir_intrinsic_base(instr
);
5317 unsigned count
= instr
->dest
.ssa
.num_components
;
5318 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5320 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5321 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5322 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5323 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5324 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5325 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5326 for (unsigned i
= 0; i
< count
; ++i
) {
5327 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5328 vec
->operands
[i
] = Operand
{elems
[i
]};
5330 vec
->definitions
[0] = Definition(dst
);
5331 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5332 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5337 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5338 if (offset
!= 0) // TODO check if index != 0 as well
5339 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5340 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5343 bool aligned
= true;
5345 if (instr
->dest
.ssa
.bit_size
== 8) {
5346 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5347 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5349 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5350 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5351 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5353 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5358 switch (vec
.size()) {
5360 op
= aco_opcode::s_load_dword
;
5363 op
= aco_opcode::s_load_dwordx2
;
5369 op
= aco_opcode::s_load_dwordx4
;
5375 op
= aco_opcode::s_load_dwordx8
;
5378 unreachable("unimplemented or forbidden load_push_constant.");
5381 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5384 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5385 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5390 emit_split_vector(ctx
, vec
, 4);
5391 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5392 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5393 emit_extract_vector(ctx
, vec
, 0, rc
),
5394 emit_extract_vector(ctx
, vec
, 1, rc
),
5395 emit_extract_vector(ctx
, vec
, 2, rc
));
5398 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5401 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5403 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5405 Builder
bld(ctx
->program
, ctx
->block
);
5407 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5408 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5409 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5410 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5411 if (ctx
->options
->chip_class
>= GFX10
) {
5412 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5413 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5414 S_008F0C_RESOURCE_LEVEL(1);
5416 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5417 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5420 unsigned base
= nir_intrinsic_base(instr
);
5421 unsigned range
= nir_intrinsic_range(instr
);
5423 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5424 if (base
&& offset
.type() == RegType::sgpr
)
5425 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5426 else if (base
&& offset
.type() == RegType::vgpr
)
5427 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5429 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5430 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5431 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5432 Operand(desc_type
));
5433 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5434 // TODO: get alignment information for subdword constants
5435 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5438 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5440 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5441 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5443 ctx
->program
->needs_exact
= true;
5445 // TODO: optimize uniform conditions
5446 Builder
bld(ctx
->program
, ctx
->block
);
5447 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5448 assert(src
.regClass() == bld
.lm
);
5449 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5450 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5451 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5455 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5457 Builder
bld(ctx
->program
, ctx
->block
);
5459 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5460 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5462 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5463 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5465 if (ctx
->block
->loop_nest_depth
&&
5466 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5467 /* we handle discards the same way as jump instructions */
5468 append_logical_end(ctx
->block
);
5470 /* in loops, discard behaves like break */
5471 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5472 ctx
->block
->kind
|= block_kind_discard
;
5475 /* uniform discard - loop ends here */
5476 assert(nir_instr_is_last(&instr
->instr
));
5477 ctx
->block
->kind
|= block_kind_uniform
;
5478 ctx
->cf_info
.has_branch
= true;
5479 bld
.branch(aco_opcode::p_branch
);
5480 add_linear_edge(ctx
->block
->index
, linear_target
);
5484 /* we add a break right behind the discard() instructions */
5485 ctx
->block
->kind
|= block_kind_break
;
5486 unsigned idx
= ctx
->block
->index
;
5488 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5489 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5491 /* remove critical edges from linear CFG */
5492 bld
.branch(aco_opcode::p_branch
);
5493 Block
* break_block
= ctx
->program
->create_and_insert_block();
5494 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5495 break_block
->kind
|= block_kind_uniform
;
5496 add_linear_edge(idx
, break_block
);
5497 add_linear_edge(break_block
->index
, linear_target
);
5498 bld
.reset(break_block
);
5499 bld
.branch(aco_opcode::p_branch
);
5501 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5502 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5503 add_linear_edge(idx
, continue_block
);
5504 append_logical_start(continue_block
);
5505 ctx
->block
= continue_block
;
5510 /* it can currently happen that NIR doesn't remove the unreachable code */
5511 if (!nir_instr_is_last(&instr
->instr
)) {
5512 ctx
->program
->needs_exact
= true;
5513 /* save exec somewhere temporarily so that it doesn't get
5514 * overwritten before the discard from outer exec masks */
5515 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5516 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5517 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5521 /* This condition is incorrect for uniformly branched discards in a loop
5522 * predicated by a divergent condition, but the above code catches that case
5523 * and the discard would end up turning into a discard_if.
5533 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5534 /* program just ends here */
5535 ctx
->block
->kind
|= block_kind_uniform
;
5536 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5537 0 /* enabled mask */, 9 /* dest */,
5538 false /* compressed */, true/* done */, true /* valid mask */);
5539 bld
.sopp(aco_opcode::s_endpgm
);
5540 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5542 ctx
->block
->kind
|= block_kind_discard
;
5543 /* branch and linear edge is added by visit_if() */
5547 enum aco_descriptor_type
{
5558 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5559 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5561 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5562 return dim
== ac_image_cube
||
5563 dim
== ac_image_1darray
||
5564 dim
== ac_image_2darray
||
5565 dim
== ac_image_2darraymsaa
;
5568 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5569 enum aco_descriptor_type desc_type
,
5570 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5572 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5573 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5574 if (it != ctx->tex_desc.end())
5577 Temp index
= Temp();
5578 bool index_set
= false;
5579 unsigned constant_index
= 0;
5580 unsigned descriptor_set
;
5581 unsigned base_index
;
5582 Builder
bld(ctx
->program
, ctx
->block
);
5585 assert(tex_instr
&& !image
);
5587 base_index
= tex_instr
->sampler_index
;
5589 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5590 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5594 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5595 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5597 constant_index
+= array_size
* const_value
->u32
;
5599 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5600 if (indirect
.type() == RegType::vgpr
)
5601 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5603 if (array_size
!= 1)
5604 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5610 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5614 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5616 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5617 base_index
= deref_instr
->var
->data
.binding
;
5620 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5621 list
= convert_pointer_to_64_bit(ctx
, list
);
5623 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5624 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5625 unsigned offset
= binding
->offset
;
5626 unsigned stride
= binding
->size
;
5630 assert(base_index
< layout
->binding_count
);
5632 switch (desc_type
) {
5633 case ACO_DESC_IMAGE
:
5635 opcode
= aco_opcode::s_load_dwordx8
;
5637 case ACO_DESC_FMASK
:
5639 opcode
= aco_opcode::s_load_dwordx8
;
5642 case ACO_DESC_SAMPLER
:
5644 opcode
= aco_opcode::s_load_dwordx4
;
5645 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5646 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5648 case ACO_DESC_BUFFER
:
5650 opcode
= aco_opcode::s_load_dwordx4
;
5652 case ACO_DESC_PLANE_0
:
5653 case ACO_DESC_PLANE_1
:
5655 opcode
= aco_opcode::s_load_dwordx8
;
5656 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5658 case ACO_DESC_PLANE_2
:
5660 opcode
= aco_opcode::s_load_dwordx4
;
5664 unreachable("invalid desc_type\n");
5667 offset
+= constant_index
* stride
;
5669 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5670 (!index_set
|| binding
->immutable_samplers_equal
)) {
5671 if (binding
->immutable_samplers_equal
)
5674 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5675 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5676 Operand(samplers
[constant_index
* 4 + 0]),
5677 Operand(samplers
[constant_index
* 4 + 1]),
5678 Operand(samplers
[constant_index
* 4 + 2]),
5679 Operand(samplers
[constant_index
* 4 + 3]));
5684 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5686 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5687 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5690 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5692 if (desc_type
== ACO_DESC_PLANE_2
) {
5694 for (unsigned i
= 0; i
< 8; i
++)
5695 components
[i
] = bld
.tmp(s1
);
5696 bld
.pseudo(aco_opcode::p_split_vector
,
5697 Definition(components
[0]),
5698 Definition(components
[1]),
5699 Definition(components
[2]),
5700 Definition(components
[3]),
5703 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5704 bld
.pseudo(aco_opcode::p_split_vector
,
5705 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5706 Definition(components
[4]),
5707 Definition(components
[5]),
5708 Definition(components
[6]),
5709 Definition(components
[7]),
5712 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5713 components
[0], components
[1], components
[2], components
[3],
5714 components
[4], components
[5], components
[6], components
[7]);
5720 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5723 case GLSL_SAMPLER_DIM_BUF
:
5725 case GLSL_SAMPLER_DIM_1D
:
5726 return array
? 2 : 1;
5727 case GLSL_SAMPLER_DIM_2D
:
5728 return array
? 3 : 2;
5729 case GLSL_SAMPLER_DIM_MS
:
5730 return array
? 4 : 3;
5731 case GLSL_SAMPLER_DIM_3D
:
5732 case GLSL_SAMPLER_DIM_CUBE
:
5734 case GLSL_SAMPLER_DIM_RECT
:
5735 case GLSL_SAMPLER_DIM_SUBPASS
:
5737 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5746 /* Adjust the sample index according to FMASK.
5748 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5749 * which is the identity mapping. Each nibble says which physical sample
5750 * should be fetched to get that sample.
5752 * For example, 0x11111100 means there are only 2 samples stored and
5753 * the second sample covers 3/4 of the pixel. When reading samples 0
5754 * and 1, return physical sample 0 (determined by the first two 0s
5755 * in FMASK), otherwise return physical sample 1.
5757 * The sample index should be adjusted as follows:
5758 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5760 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5762 Builder
bld(ctx
->program
, ctx
->block
);
5763 Temp fmask
= bld
.tmp(v1
);
5764 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5765 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5768 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5769 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5770 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5771 load
->operands
[0] = Operand(fmask_desc_ptr
);
5772 load
->operands
[1] = Operand(s4
); /* no sampler */
5773 load
->operands
[2] = Operand(coord
);
5774 load
->definitions
[0] = Definition(fmask
);
5781 ctx
->block
->instructions
.emplace_back(std::move(load
));
5783 Operand sample_index4
;
5784 if (sample_index
.isConstant()) {
5785 if (sample_index
.constantValue() < 16) {
5786 sample_index4
= Operand(sample_index
.constantValue() << 2);
5788 sample_index4
= Operand(0u);
5790 } else if (sample_index
.regClass() == s1
) {
5791 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5793 assert(sample_index
.regClass() == v1
);
5794 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5798 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5799 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5800 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5801 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5803 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5805 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5806 * resource descriptor is 0 (invalid),
5808 Temp compare
= bld
.tmp(bld
.lm
);
5809 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5810 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5812 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5814 /* Replace the MSAA sample index. */
5815 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5818 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5821 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5822 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5823 bool is_array
= glsl_sampler_type_is_array(type
);
5824 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5825 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5826 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5827 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5828 int count
= image_type_to_components_count(dim
, is_array
);
5829 std::vector
<Temp
> coords(count
);
5830 Builder
bld(ctx
->program
, ctx
->block
);
5834 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5835 /* get sample index */
5836 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5837 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5838 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5839 std::vector
<Temp
> fmask_load_address
;
5840 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5841 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5843 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5844 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5846 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5851 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5852 coords
.resize(coords
.size() + 1);
5853 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5855 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5857 for (int i
= 0; i
< count
; i
++)
5858 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5861 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5862 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5863 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5864 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5867 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5870 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5871 for (unsigned i
= 0; i
< coords
.size(); i
++)
5872 vec
->operands
[i
] = Operand(coords
[i
]);
5873 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5874 vec
->definitions
[0] = Definition(res
);
5875 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5880 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5882 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5883 if (semantics
& semantic_atomicrmw
)
5884 return memory_sync_info(storage
, semantics
);
5886 unsigned access
= nir_intrinsic_access(instr
);
5888 if (access
& ACCESS_VOLATILE
)
5889 semantics
|= semantic_volatile
;
5890 if (access
& ACCESS_CAN_REORDER
)
5891 semantics
|= semantic_can_reorder
| semantic_private
;
5893 return memory_sync_info(storage
, semantics
);
5896 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5898 Builder
bld(ctx
->program
, ctx
->block
);
5899 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5900 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5901 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5902 bool is_array
= glsl_sampler_type_is_array(type
);
5903 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5905 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5906 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5908 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5909 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5910 unsigned num_channels
= util_last_bit(mask
);
5911 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5912 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5915 switch (num_channels
) {
5917 opcode
= aco_opcode::buffer_load_format_x
;
5920 opcode
= aco_opcode::buffer_load_format_xy
;
5923 opcode
= aco_opcode::buffer_load_format_xyz
;
5926 opcode
= aco_opcode::buffer_load_format_xyzw
;
5929 unreachable(">4 channel buffer image load");
5931 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5932 load
->operands
[0] = Operand(rsrc
);
5933 load
->operands
[1] = Operand(vindex
);
5934 load
->operands
[2] = Operand((uint32_t) 0);
5936 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5939 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5940 load
->definitions
[0] = Definition(tmp
);
5942 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5943 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5945 ctx
->block
->instructions
.emplace_back(std::move(load
));
5947 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5951 Temp coords
= get_image_coords(ctx
, instr
, type
);
5952 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5954 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5955 unsigned num_components
= util_bitcount(dmask
);
5957 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5960 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5962 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5963 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5965 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5966 load
->operands
[0] = Operand(resource
);
5967 load
->operands
[1] = Operand(s4
); /* no sampler */
5968 load
->operands
[2] = Operand(coords
);
5969 load
->definitions
[0] = Definition(tmp
);
5970 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5971 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5972 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5973 load
->dmask
= dmask
;
5975 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5977 ctx
->block
->instructions
.emplace_back(std::move(load
));
5979 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5983 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5985 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5986 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5987 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5988 bool is_array
= glsl_sampler_type_is_array(type
);
5989 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5991 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5992 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5993 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5995 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5996 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5997 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5999 switch (data
.size()) {
6001 opcode
= aco_opcode::buffer_store_format_x
;
6004 opcode
= aco_opcode::buffer_store_format_xy
;
6007 opcode
= aco_opcode::buffer_store_format_xyz
;
6010 opcode
= aco_opcode::buffer_store_format_xyzw
;
6013 unreachable(">4 channel buffer image store");
6015 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
6016 store
->operands
[0] = Operand(rsrc
);
6017 store
->operands
[1] = Operand(vindex
);
6018 store
->operands
[2] = Operand((uint32_t) 0);
6019 store
->operands
[3] = Operand(data
);
6020 store
->idxen
= true;
6023 store
->disable_wqm
= true;
6025 ctx
->program
->needs_exact
= true;
6026 ctx
->block
->instructions
.emplace_back(std::move(store
));
6030 assert(data
.type() == RegType::vgpr
);
6031 Temp coords
= get_image_coords(ctx
, instr
, type
);
6032 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6034 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
6035 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
6037 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
6038 store
->operands
[0] = Operand(resource
);
6039 store
->operands
[1] = Operand(data
);
6040 store
->operands
[2] = Operand(coords
);
6043 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6044 store
->dmask
= (1 << data
.size()) - 1;
6046 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6047 store
->disable_wqm
= true;
6049 ctx
->program
->needs_exact
= true;
6050 ctx
->block
->instructions
.emplace_back(std::move(store
));
6054 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6056 /* return the previous value if dest is ever used */
6057 bool return_previous
= false;
6058 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6059 return_previous
= true;
6062 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6063 return_previous
= true;
6067 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6068 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6069 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6070 bool is_array
= glsl_sampler_type_is_array(type
);
6071 Builder
bld(ctx
->program
, ctx
->block
);
6073 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
6074 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
6076 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
6077 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
6079 aco_opcode buf_op
, image_op
;
6080 switch (instr
->intrinsic
) {
6081 case nir_intrinsic_image_deref_atomic_add
:
6082 buf_op
= aco_opcode::buffer_atomic_add
;
6083 image_op
= aco_opcode::image_atomic_add
;
6085 case nir_intrinsic_image_deref_atomic_umin
:
6086 buf_op
= aco_opcode::buffer_atomic_umin
;
6087 image_op
= aco_opcode::image_atomic_umin
;
6089 case nir_intrinsic_image_deref_atomic_imin
:
6090 buf_op
= aco_opcode::buffer_atomic_smin
;
6091 image_op
= aco_opcode::image_atomic_smin
;
6093 case nir_intrinsic_image_deref_atomic_umax
:
6094 buf_op
= aco_opcode::buffer_atomic_umax
;
6095 image_op
= aco_opcode::image_atomic_umax
;
6097 case nir_intrinsic_image_deref_atomic_imax
:
6098 buf_op
= aco_opcode::buffer_atomic_smax
;
6099 image_op
= aco_opcode::image_atomic_smax
;
6101 case nir_intrinsic_image_deref_atomic_and
:
6102 buf_op
= aco_opcode::buffer_atomic_and
;
6103 image_op
= aco_opcode::image_atomic_and
;
6105 case nir_intrinsic_image_deref_atomic_or
:
6106 buf_op
= aco_opcode::buffer_atomic_or
;
6107 image_op
= aco_opcode::image_atomic_or
;
6109 case nir_intrinsic_image_deref_atomic_xor
:
6110 buf_op
= aco_opcode::buffer_atomic_xor
;
6111 image_op
= aco_opcode::image_atomic_xor
;
6113 case nir_intrinsic_image_deref_atomic_exchange
:
6114 buf_op
= aco_opcode::buffer_atomic_swap
;
6115 image_op
= aco_opcode::image_atomic_swap
;
6117 case nir_intrinsic_image_deref_atomic_comp_swap
:
6118 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
6119 image_op
= aco_opcode::image_atomic_cmpswap
;
6122 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6125 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6126 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
6128 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6129 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6130 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6131 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6132 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6133 mubuf
->operands
[0] = Operand(resource
);
6134 mubuf
->operands
[1] = Operand(vindex
);
6135 mubuf
->operands
[2] = Operand((uint32_t)0);
6136 mubuf
->operands
[3] = Operand(data
);
6137 if (return_previous
)
6138 mubuf
->definitions
[0] = Definition(dst
);
6140 mubuf
->idxen
= true;
6141 mubuf
->glc
= return_previous
;
6142 mubuf
->dlc
= false; /* Not needed for atomics */
6143 mubuf
->disable_wqm
= true;
6145 ctx
->program
->needs_exact
= true;
6146 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6150 Temp coords
= get_image_coords(ctx
, instr
, type
);
6151 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6152 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6153 mimg
->operands
[0] = Operand(resource
);
6154 mimg
->operands
[1] = Operand(data
);
6155 mimg
->operands
[2] = Operand(coords
);
6156 if (return_previous
)
6157 mimg
->definitions
[0] = Definition(dst
);
6158 mimg
->glc
= return_previous
;
6159 mimg
->dlc
= false; /* Not needed for atomics */
6160 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6161 mimg
->dmask
= (1 << data
.size()) - 1;
6163 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6164 mimg
->disable_wqm
= true;
6166 ctx
->program
->needs_exact
= true;
6167 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6171 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6173 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6174 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6175 Builder
bld(ctx
->program
, ctx
->block
);
6177 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6179 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6180 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6182 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6183 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6185 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6186 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6188 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6189 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6190 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6191 if (dst
.type() == RegType::vgpr
)
6192 bld
.copy(Definition(dst
), shr_dst
);
6194 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6196 emit_extract_vector(ctx
, desc
, 2, dst
);
6200 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6202 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6203 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6204 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6205 bool is_array
= glsl_sampler_type_is_array(type
);
6206 Builder
bld(ctx
->program
, ctx
->block
);
6208 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6209 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6210 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6214 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6217 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6219 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6221 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6222 mimg
->operands
[0] = Operand(resource
);
6223 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6224 mimg
->operands
[2] = Operand(lod
);
6225 uint8_t& dmask
= mimg
->dmask
;
6226 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6227 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6228 mimg
->da
= glsl_sampler_type_is_array(type
);
6229 Definition
& def
= mimg
->definitions
[0];
6230 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6232 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6233 glsl_sampler_type_is_array(type
)) {
6235 assert(instr
->dest
.ssa
.num_components
== 3);
6236 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6237 def
= Definition(tmp
);
6238 emit_split_vector(ctx
, tmp
, 3);
6240 /* divide 3rd value by 6 by multiplying with magic number */
6241 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6242 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6244 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6245 emit_extract_vector(ctx
, tmp
, 0, v1
),
6246 emit_extract_vector(ctx
, tmp
, 1, v1
),
6249 } else if (ctx
->options
->chip_class
== GFX9
&&
6250 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6251 glsl_sampler_type_is_array(type
)) {
6252 assert(instr
->dest
.ssa
.num_components
== 2);
6253 def
= Definition(dst
);
6256 def
= Definition(dst
);
6259 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6262 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6264 Builder
bld(ctx
->program
, ctx
->block
);
6265 unsigned num_components
= instr
->num_components
;
6267 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6268 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6269 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6271 unsigned access
= nir_intrinsic_access(instr
);
6272 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6273 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6275 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6276 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6277 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6279 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6280 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6282 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6283 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6284 get_memory_sync_info(instr
, storage_buffer
, 0));
6287 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6289 Builder
bld(ctx
->program
, ctx
->block
);
6290 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6291 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6292 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6293 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6295 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6296 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6298 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6299 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6300 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6301 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6302 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6304 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6306 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6307 ctx
->options
->chip_class
>= GFX8
&&
6308 ctx
->options
->chip_class
< GFX10_3
&&
6309 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6312 offset
= bld
.as_uniform(offset
);
6313 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6315 unsigned write_count
= 0;
6316 Temp write_datas
[32];
6317 unsigned offsets
[32];
6318 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6319 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6321 for (unsigned i
= 0; i
< write_count
; i
++) {
6322 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6323 if (smem
&& ctx
->stage
== fragment_fs
)
6324 op
= aco_opcode::p_fs_buffer_store_smem
;
6327 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6328 store
->operands
[0] = Operand(rsrc
);
6330 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6331 offset
, Operand(offsets
[i
]));
6332 store
->operands
[1] = Operand(off
);
6334 store
->operands
[1] = Operand(offset
);
6336 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6337 store
->operands
[1].setFixed(m0
);
6338 store
->operands
[2] = Operand(write_datas
[i
]);
6341 store
->disable_wqm
= true;
6343 ctx
->block
->instructions
.emplace_back(std::move(store
));
6344 ctx
->program
->wb_smem_l1_on_end
= true;
6345 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6346 ctx
->block
->kind
|= block_kind_needs_lowering
;
6347 ctx
->program
->needs_exact
= true;
6350 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6351 store
->operands
[0] = Operand(rsrc
);
6352 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6353 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6354 store
->operands
[3] = Operand(write_datas
[i
]);
6355 store
->offset
= offsets
[i
];
6356 store
->offen
= (offset
.type() == RegType::vgpr
);
6359 store
->disable_wqm
= true;
6361 ctx
->program
->needs_exact
= true;
6362 ctx
->block
->instructions
.emplace_back(std::move(store
));
6367 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6369 /* return the previous value if dest is ever used */
6370 bool return_previous
= false;
6371 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6372 return_previous
= true;
6375 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6376 return_previous
= true;
6380 Builder
bld(ctx
->program
, ctx
->block
);
6381 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6383 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6384 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6385 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6387 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6388 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6389 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6391 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6393 aco_opcode op32
, op64
;
6394 switch (instr
->intrinsic
) {
6395 case nir_intrinsic_ssbo_atomic_add
:
6396 op32
= aco_opcode::buffer_atomic_add
;
6397 op64
= aco_opcode::buffer_atomic_add_x2
;
6399 case nir_intrinsic_ssbo_atomic_imin
:
6400 op32
= aco_opcode::buffer_atomic_smin
;
6401 op64
= aco_opcode::buffer_atomic_smin_x2
;
6403 case nir_intrinsic_ssbo_atomic_umin
:
6404 op32
= aco_opcode::buffer_atomic_umin
;
6405 op64
= aco_opcode::buffer_atomic_umin_x2
;
6407 case nir_intrinsic_ssbo_atomic_imax
:
6408 op32
= aco_opcode::buffer_atomic_smax
;
6409 op64
= aco_opcode::buffer_atomic_smax_x2
;
6411 case nir_intrinsic_ssbo_atomic_umax
:
6412 op32
= aco_opcode::buffer_atomic_umax
;
6413 op64
= aco_opcode::buffer_atomic_umax_x2
;
6415 case nir_intrinsic_ssbo_atomic_and
:
6416 op32
= aco_opcode::buffer_atomic_and
;
6417 op64
= aco_opcode::buffer_atomic_and_x2
;
6419 case nir_intrinsic_ssbo_atomic_or
:
6420 op32
= aco_opcode::buffer_atomic_or
;
6421 op64
= aco_opcode::buffer_atomic_or_x2
;
6423 case nir_intrinsic_ssbo_atomic_xor
:
6424 op32
= aco_opcode::buffer_atomic_xor
;
6425 op64
= aco_opcode::buffer_atomic_xor_x2
;
6427 case nir_intrinsic_ssbo_atomic_exchange
:
6428 op32
= aco_opcode::buffer_atomic_swap
;
6429 op64
= aco_opcode::buffer_atomic_swap_x2
;
6431 case nir_intrinsic_ssbo_atomic_comp_swap
:
6432 op32
= aco_opcode::buffer_atomic_cmpswap
;
6433 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6436 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6438 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6439 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6440 mubuf
->operands
[0] = Operand(rsrc
);
6441 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6442 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6443 mubuf
->operands
[3] = Operand(data
);
6444 if (return_previous
)
6445 mubuf
->definitions
[0] = Definition(dst
);
6447 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6448 mubuf
->glc
= return_previous
;
6449 mubuf
->dlc
= false; /* Not needed for atomics */
6450 mubuf
->disable_wqm
= true;
6451 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6452 ctx
->program
->needs_exact
= true;
6453 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6456 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6458 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6459 Builder
bld(ctx
->program
, ctx
->block
);
6460 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6461 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6464 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6466 Builder
bld(ctx
->program
, ctx
->block
);
6467 unsigned num_components
= instr
->num_components
;
6468 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6470 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6471 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6472 num_components
, component_size
};
6473 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6474 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6475 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6476 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6477 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6478 * it's safe to use SMEM */
6479 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6480 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6481 emit_global_load(ctx
, bld
, &info
);
6483 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6484 emit_smem_load(ctx
, bld
, &info
);
6488 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6490 Builder
bld(ctx
->program
, ctx
->block
);
6491 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6492 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6494 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6495 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6496 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6497 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6499 if (ctx
->options
->chip_class
>= GFX7
)
6500 addr
= as_vgpr(ctx
, addr
);
6502 unsigned write_count
= 0;
6503 Temp write_datas
[32];
6504 unsigned offsets
[32];
6505 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6506 16, &write_count
, write_datas
, offsets
);
6508 for (unsigned i
= 0; i
< write_count
; i
++) {
6509 if (ctx
->options
->chip_class
>= GFX7
) {
6510 unsigned offset
= offsets
[i
];
6511 Temp store_addr
= addr
;
6512 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6513 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6514 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6515 Temp carry
= bld
.tmp(bld
.lm
);
6516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6518 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6519 Operand(offset
), addr0
);
6520 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6522 carry
).def(1).setHint(vcc
);
6524 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6529 bool global
= ctx
->options
->chip_class
>= GFX9
;
6531 switch (write_datas
[i
].bytes()) {
6533 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6536 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6539 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6542 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6545 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6548 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6551 unreachable("store_global not implemented for this size.");
6554 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6555 flat
->operands
[0] = Operand(store_addr
);
6556 flat
->operands
[1] = Operand(s1
);
6557 flat
->operands
[2] = Operand(write_datas
[i
]);
6560 flat
->offset
= offset
;
6561 flat
->disable_wqm
= true;
6563 ctx
->program
->needs_exact
= true;
6564 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6566 assert(ctx
->options
->chip_class
== GFX6
);
6568 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6570 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6572 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6573 mubuf
->operands
[0] = Operand(rsrc
);
6574 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6575 mubuf
->operands
[2] = Operand(0u);
6576 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6579 mubuf
->offset
= offsets
[i
];
6580 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6581 mubuf
->disable_wqm
= true;
6583 ctx
->program
->needs_exact
= true;
6584 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6589 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6591 /* return the previous value if dest is ever used */
6592 bool return_previous
= false;
6593 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6594 return_previous
= true;
6597 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6598 return_previous
= true;
6602 Builder
bld(ctx
->program
, ctx
->block
);
6603 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6604 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6606 if (ctx
->options
->chip_class
>= GFX7
)
6607 addr
= as_vgpr(ctx
, addr
);
6609 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6610 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6611 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6613 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6615 aco_opcode op32
, op64
;
6617 if (ctx
->options
->chip_class
>= GFX7
) {
6618 bool global
= ctx
->options
->chip_class
>= GFX9
;
6619 switch (instr
->intrinsic
) {
6620 case nir_intrinsic_global_atomic_add
:
6621 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6622 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6624 case nir_intrinsic_global_atomic_imin
:
6625 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6626 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6628 case nir_intrinsic_global_atomic_umin
:
6629 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6630 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6632 case nir_intrinsic_global_atomic_imax
:
6633 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6634 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6636 case nir_intrinsic_global_atomic_umax
:
6637 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6638 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6640 case nir_intrinsic_global_atomic_and
:
6641 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6642 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6644 case nir_intrinsic_global_atomic_or
:
6645 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6646 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6648 case nir_intrinsic_global_atomic_xor
:
6649 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6650 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6652 case nir_intrinsic_global_atomic_exchange
:
6653 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6654 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6656 case nir_intrinsic_global_atomic_comp_swap
:
6657 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6658 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6661 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6664 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6665 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6666 flat
->operands
[0] = Operand(addr
);
6667 flat
->operands
[1] = Operand(s1
);
6668 flat
->operands
[2] = Operand(data
);
6669 if (return_previous
)
6670 flat
->definitions
[0] = Definition(dst
);
6671 flat
->glc
= return_previous
;
6672 flat
->dlc
= false; /* Not needed for atomics */
6674 flat
->disable_wqm
= true;
6675 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6676 ctx
->program
->needs_exact
= true;
6677 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6679 assert(ctx
->options
->chip_class
== GFX6
);
6681 switch (instr
->intrinsic
) {
6682 case nir_intrinsic_global_atomic_add
:
6683 op32
= aco_opcode::buffer_atomic_add
;
6684 op64
= aco_opcode::buffer_atomic_add_x2
;
6686 case nir_intrinsic_global_atomic_imin
:
6687 op32
= aco_opcode::buffer_atomic_smin
;
6688 op64
= aco_opcode::buffer_atomic_smin_x2
;
6690 case nir_intrinsic_global_atomic_umin
:
6691 op32
= aco_opcode::buffer_atomic_umin
;
6692 op64
= aco_opcode::buffer_atomic_umin_x2
;
6694 case nir_intrinsic_global_atomic_imax
:
6695 op32
= aco_opcode::buffer_atomic_smax
;
6696 op64
= aco_opcode::buffer_atomic_smax_x2
;
6698 case nir_intrinsic_global_atomic_umax
:
6699 op32
= aco_opcode::buffer_atomic_umax
;
6700 op64
= aco_opcode::buffer_atomic_umax_x2
;
6702 case nir_intrinsic_global_atomic_and
:
6703 op32
= aco_opcode::buffer_atomic_and
;
6704 op64
= aco_opcode::buffer_atomic_and_x2
;
6706 case nir_intrinsic_global_atomic_or
:
6707 op32
= aco_opcode::buffer_atomic_or
;
6708 op64
= aco_opcode::buffer_atomic_or_x2
;
6710 case nir_intrinsic_global_atomic_xor
:
6711 op32
= aco_opcode::buffer_atomic_xor
;
6712 op64
= aco_opcode::buffer_atomic_xor_x2
;
6714 case nir_intrinsic_global_atomic_exchange
:
6715 op32
= aco_opcode::buffer_atomic_swap
;
6716 op64
= aco_opcode::buffer_atomic_swap_x2
;
6718 case nir_intrinsic_global_atomic_comp_swap
:
6719 op32
= aco_opcode::buffer_atomic_cmpswap
;
6720 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6723 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6726 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6728 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6730 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6731 mubuf
->operands
[0] = Operand(rsrc
);
6732 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6733 mubuf
->operands
[2] = Operand(0u);
6734 mubuf
->operands
[3] = Operand(data
);
6735 if (return_previous
)
6736 mubuf
->definitions
[0] = Definition(dst
);
6737 mubuf
->glc
= return_previous
;
6740 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6741 mubuf
->disable_wqm
= true;
6742 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6743 ctx
->program
->needs_exact
= true;
6744 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6748 sync_scope
translate_nir_scope(nir_scope scope
)
6751 case NIR_SCOPE_NONE
:
6752 case NIR_SCOPE_INVOCATION
:
6753 return scope_invocation
;
6754 case NIR_SCOPE_SUBGROUP
:
6755 return scope_subgroup
;
6756 case NIR_SCOPE_WORKGROUP
:
6757 return scope_workgroup
;
6758 case NIR_SCOPE_QUEUE_FAMILY
:
6759 return scope_queuefamily
;
6760 case NIR_SCOPE_DEVICE
:
6761 return scope_device
;
6763 unreachable("invalid scope");
6766 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6767 Builder
bld(ctx
->program
, ctx
->block
);
6769 unsigned semantics
= 0;
6770 unsigned storage
= 0;
6771 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6772 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6774 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6775 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6776 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6777 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6778 storage
|= storage_shared
;
6779 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6780 storage
|= storage_shared
;
6782 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6783 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6784 semantics
|= semantic_acquire
| semantic_release
;
6785 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6786 semantics
|= semantic_acquire
| semantic_release
;
6788 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6790 bld
.barrier(aco_opcode::p_barrier
,
6791 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6795 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6797 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6798 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6799 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6800 Builder
bld(ctx
->program
, ctx
->block
);
6802 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6803 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6804 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6807 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6809 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6810 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6811 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6812 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6814 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6815 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6818 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6820 unsigned offset
= nir_intrinsic_base(instr
);
6821 Builder
bld(ctx
->program
, ctx
->block
);
6822 Operand m
= load_lds_size_m0(bld
);
6823 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6824 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6826 unsigned num_operands
= 3;
6827 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6828 switch(instr
->intrinsic
) {
6829 case nir_intrinsic_shared_atomic_add
:
6830 op32
= aco_opcode::ds_add_u32
;
6831 op64
= aco_opcode::ds_add_u64
;
6832 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6833 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6835 case nir_intrinsic_shared_atomic_imin
:
6836 op32
= aco_opcode::ds_min_i32
;
6837 op64
= aco_opcode::ds_min_i64
;
6838 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6839 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6841 case nir_intrinsic_shared_atomic_umin
:
6842 op32
= aco_opcode::ds_min_u32
;
6843 op64
= aco_opcode::ds_min_u64
;
6844 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6845 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6847 case nir_intrinsic_shared_atomic_imax
:
6848 op32
= aco_opcode::ds_max_i32
;
6849 op64
= aco_opcode::ds_max_i64
;
6850 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6851 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6853 case nir_intrinsic_shared_atomic_umax
:
6854 op32
= aco_opcode::ds_max_u32
;
6855 op64
= aco_opcode::ds_max_u64
;
6856 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6857 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6859 case nir_intrinsic_shared_atomic_and
:
6860 op32
= aco_opcode::ds_and_b32
;
6861 op64
= aco_opcode::ds_and_b64
;
6862 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6863 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6865 case nir_intrinsic_shared_atomic_or
:
6866 op32
= aco_opcode::ds_or_b32
;
6867 op64
= aco_opcode::ds_or_b64
;
6868 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6869 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6871 case nir_intrinsic_shared_atomic_xor
:
6872 op32
= aco_opcode::ds_xor_b32
;
6873 op64
= aco_opcode::ds_xor_b64
;
6874 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6875 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6877 case nir_intrinsic_shared_atomic_exchange
:
6878 op32
= aco_opcode::ds_write_b32
;
6879 op64
= aco_opcode::ds_write_b64
;
6880 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6881 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6883 case nir_intrinsic_shared_atomic_comp_swap
:
6884 op32
= aco_opcode::ds_cmpst_b32
;
6885 op64
= aco_opcode::ds_cmpst_b64
;
6886 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6887 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6890 case nir_intrinsic_shared_atomic_fadd
:
6891 op32
= aco_opcode::ds_add_f32
;
6892 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6893 op64
= aco_opcode::num_opcodes
;
6894 op64_rtn
= aco_opcode::num_opcodes
;
6897 unreachable("Unhandled shared atomic intrinsic");
6900 /* return the previous value if dest is ever used */
6901 bool return_previous
= false;
6902 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6903 return_previous
= true;
6906 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6907 return_previous
= true;
6912 if (data
.size() == 1) {
6913 assert(instr
->dest
.ssa
.bit_size
== 32);
6914 op
= return_previous
? op32_rtn
: op32
;
6916 assert(instr
->dest
.ssa
.bit_size
== 64);
6917 op
= return_previous
? op64_rtn
: op64
;
6920 if (offset
> 65535) {
6921 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6925 aco_ptr
<DS_instruction
> ds
;
6926 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6927 ds
->operands
[0] = Operand(address
);
6928 ds
->operands
[1] = Operand(data
);
6929 if (num_operands
== 4)
6930 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6931 ds
->operands
[num_operands
- 1] = m
;
6932 ds
->offset0
= offset
;
6933 if (return_previous
)
6934 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6935 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6936 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6939 Temp
get_scratch_resource(isel_context
*ctx
)
6941 Builder
bld(ctx
->program
, ctx
->block
);
6942 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6943 if (ctx
->stage
!= compute_cs
)
6944 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6946 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6947 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6949 if (ctx
->program
->chip_class
>= GFX10
) {
6950 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6951 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6952 S_008F0C_RESOURCE_LEVEL(1);
6953 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6954 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6955 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6958 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6959 if (ctx
->program
->chip_class
<= GFX8
)
6960 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6962 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6965 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6966 Builder
bld(ctx
->program
, ctx
->block
);
6967 Temp rsrc
= get_scratch_resource(ctx
);
6968 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6969 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6971 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6972 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6973 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6974 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6975 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6976 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6977 info
.soffset
= ctx
->program
->scratch_offset
;
6978 emit_scratch_load(ctx
, bld
, &info
);
6981 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6982 Builder
bld(ctx
->program
, ctx
->block
);
6983 Temp rsrc
= get_scratch_resource(ctx
);
6984 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6985 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6987 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6988 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6990 unsigned write_count
= 0;
6991 Temp write_datas
[32];
6992 unsigned offsets
[32];
6993 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6994 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6995 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6997 for (unsigned i
= 0; i
< write_count
; i
++) {
6998 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6999 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
7000 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
7004 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7005 uint8_t log2_ps_iter_samples
;
7006 if (ctx
->program
->info
->ps
.force_persample
) {
7007 log2_ps_iter_samples
=
7008 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
7010 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
7013 /* The bit pattern matches that used by fixed function fragment
7015 static const unsigned ps_iter_masks
[] = {
7016 0xffff, /* not used */
7022 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
7024 Builder
bld(ctx
->program
, ctx
->block
);
7026 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
7027 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7028 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
7029 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
7030 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7031 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
7034 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7035 Builder
bld(ctx
->program
, ctx
->block
);
7037 unsigned stream
= nir_intrinsic_stream_id(instr
);
7038 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7039 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
7040 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
7043 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
7045 unsigned num_components
=
7046 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
7047 assert(num_components
);
7049 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
7050 unsigned stream_offset
= 0;
7051 for (unsigned i
= 0; i
< stream
; i
++) {
7052 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
7053 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
7056 /* Limit on the stride field for <= GFX7. */
7057 assert(stride
< (1 << 14));
7059 Temp gsvs_dwords
[4];
7060 for (unsigned i
= 0; i
< 4; i
++)
7061 gsvs_dwords
[i
] = bld
.tmp(s1
);
7062 bld
.pseudo(aco_opcode::p_split_vector
,
7063 Definition(gsvs_dwords
[0]),
7064 Definition(gsvs_dwords
[1]),
7065 Definition(gsvs_dwords
[2]),
7066 Definition(gsvs_dwords
[3]),
7069 if (stream_offset
) {
7070 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
7072 Temp carry
= bld
.tmp(s1
);
7073 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
7074 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
7077 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
7078 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
7080 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7081 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
7083 unsigned offset
= 0;
7084 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
7085 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
7088 for (unsigned j
= 0; j
< 4; j
++) {
7089 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7092 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7093 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7094 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7095 if (const_offset
>= 4096u) {
7096 if (vaddr_offset
.isUndefined())
7097 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7099 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7100 const_offset
%= 4096u;
7103 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7104 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7105 mtbuf
->operands
[1] = vaddr_offset
;
7106 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7107 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7108 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7109 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7110 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7111 mtbuf
->offset
= const_offset
;
7114 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
7115 bld
.insert(std::move(mtbuf
));
7118 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7121 /* outputs for the next vertex are undefined and keeping them around can
7122 * create invalid IR with control flow */
7123 ctx
->outputs
.mask
[i
] = 0;
7126 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7129 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7131 Builder
bld(ctx
->program
, ctx
->block
);
7133 if (cluster_size
== 1) {
7135 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7136 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7137 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7138 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7139 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7140 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7141 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7142 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7143 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7144 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7145 //subgroupAnd(val) -> (exec & ~val) == 0
7146 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7147 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7148 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7149 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7150 //subgroupOr(val) -> (val & exec) != 0
7151 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7152 return bool_to_vector_condition(ctx
, tmp
);
7153 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7154 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7155 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7156 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7157 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7158 return bool_to_vector_condition(ctx
, tmp
);
7160 //subgroupClustered{And,Or,Xor}(val, n) ->
7161 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7162 //cluster_offset = ~(n - 1) & lane_id
7163 //cluster_mask = ((1 << n) - 1)
7164 //subgroupClusteredAnd():
7165 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7166 //subgroupClusteredOr():
7167 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7168 //subgroupClusteredXor():
7169 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7170 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7171 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7174 if (op
== nir_op_iand
)
7175 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7177 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7179 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7181 if (ctx
->program
->chip_class
<= GFX7
)
7182 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7183 else if (ctx
->program
->wave_size
== 64)
7184 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7186 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7187 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7188 if (cluster_mask
!= 0xffffffff)
7189 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7191 Definition cmp_def
= Definition();
7192 if (op
== nir_op_iand
) {
7193 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7194 } else if (op
== nir_op_ior
) {
7195 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7196 } else if (op
== nir_op_ixor
) {
7197 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7198 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7199 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7201 cmp_def
.setHint(vcc
);
7202 return cmp_def
.getTemp();
7206 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7208 Builder
bld(ctx
->program
, ctx
->block
);
7210 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7211 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7212 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7214 if (op
== nir_op_iand
)
7215 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7217 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7219 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7220 Temp lo
= lohi
.def(0).getTemp();
7221 Temp hi
= lohi
.def(1).getTemp();
7222 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7224 Definition cmp_def
= Definition();
7225 if (op
== nir_op_iand
)
7226 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7227 else if (op
== nir_op_ior
)
7228 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7229 else if (op
== nir_op_ixor
)
7230 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7231 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7232 cmp_def
.setHint(vcc
);
7233 return cmp_def
.getTemp();
7236 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7238 Builder
bld(ctx
->program
, ctx
->block
);
7240 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7241 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7242 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7243 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7244 if (op
== nir_op_iand
)
7245 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7246 else if (op
== nir_op_ior
)
7247 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7248 else if (op
== nir_op_ixor
)
7249 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7255 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7257 Builder
bld(ctx
->program
, ctx
->block
);
7258 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7259 if (src
.regClass().type() == RegType::vgpr
) {
7260 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7261 } else if (src
.regClass() == s1
) {
7262 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7263 } else if (src
.regClass() == s2
) {
7264 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7266 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7267 nir_print_instr(&instr
->instr
, stderr
);
7268 fprintf(stderr
, "\n");
7272 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7274 Builder
bld(ctx
->program
, ctx
->block
);
7275 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7276 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7277 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7279 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7280 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7281 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7282 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7285 if (ctx
->program
->chip_class
>= GFX8
) {
7286 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7287 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7288 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7289 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7290 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7291 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7293 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7294 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7295 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7296 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7297 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7298 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7299 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7300 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7301 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7302 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7305 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7306 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7307 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7308 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7309 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7310 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7311 Temp wqm1
= bld
.tmp(v1
);
7312 emit_wqm(ctx
, tmp1
, wqm1
, true);
7313 Temp wqm2
= bld
.tmp(v1
);
7314 emit_wqm(ctx
, tmp2
, wqm2
, true);
7315 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7319 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7321 Builder
bld(ctx
->program
, ctx
->block
);
7322 switch(instr
->intrinsic
) {
7323 case nir_intrinsic_load_barycentric_sample
:
7324 case nir_intrinsic_load_barycentric_pixel
:
7325 case nir_intrinsic_load_barycentric_centroid
: {
7326 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7327 Temp bary
= Temp(0, s2
);
7329 case INTERP_MODE_SMOOTH
:
7330 case INTERP_MODE_NONE
:
7331 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7332 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7333 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7334 bary
= ctx
->persp_centroid
;
7335 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7336 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7338 case INTERP_MODE_NOPERSPECTIVE
:
7339 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7340 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7341 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7342 bary
= ctx
->linear_centroid
;
7343 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7344 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7349 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7350 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7351 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7352 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7353 Operand(p1
), Operand(p2
));
7354 emit_split_vector(ctx
, dst
, 2);
7357 case nir_intrinsic_load_barycentric_model
: {
7358 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7360 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7361 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7362 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7363 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7364 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7365 Operand(p1
), Operand(p2
), Operand(p3
));
7366 emit_split_vector(ctx
, dst
, 3);
7369 case nir_intrinsic_load_barycentric_at_sample
: {
7370 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7371 switch (ctx
->options
->key
.fs
.num_samples
) {
7372 case 2: sample_pos_offset
+= 1 << 3; break;
7373 case 4: sample_pos_offset
+= 3 << 3; break;
7374 case 8: sample_pos_offset
+= 7 << 3; break;
7378 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7379 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7380 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7381 //TODO: bounds checking?
7382 if (addr
.type() == RegType::sgpr
) {
7385 sample_pos_offset
+= const_addr
->u32
<< 3;
7386 offset
= Operand(sample_pos_offset
);
7387 } else if (ctx
->options
->chip_class
>= GFX9
) {
7388 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7390 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7391 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7394 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7395 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7397 } else if (ctx
->options
->chip_class
>= GFX9
) {
7398 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7399 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7400 } else if (ctx
->options
->chip_class
>= GFX7
) {
7401 /* addr += private_segment_buffer + sample_pos_offset */
7402 Temp tmp0
= bld
.tmp(s1
);
7403 Temp tmp1
= bld
.tmp(s1
);
7404 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7405 Definition scc_tmp
= bld
.def(s1
, scc
);
7406 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7407 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7408 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7409 Temp pck0
= bld
.tmp(v1
);
7410 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7411 tmp1
= as_vgpr(ctx
, tmp1
);
7412 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7413 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7415 /* sample_pos = flat_load_dwordx2 addr */
7416 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7418 assert(ctx
->options
->chip_class
== GFX6
);
7420 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7421 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7422 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7424 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7425 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7427 sample_pos
= bld
.tmp(v2
);
7429 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7430 load
->definitions
[0] = Definition(sample_pos
);
7431 load
->operands
[0] = Operand(rsrc
);
7432 load
->operands
[1] = Operand(addr
);
7433 load
->operands
[2] = Operand(0u);
7434 load
->offset
= sample_pos_offset
;
7436 load
->addr64
= true;
7439 load
->disable_wqm
= false;
7440 ctx
->block
->instructions
.emplace_back(std::move(load
));
7443 /* sample_pos -= 0.5 */
7444 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7445 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7446 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7447 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7448 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7450 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7453 case nir_intrinsic_load_barycentric_at_offset
: {
7454 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7455 RegClass rc
= RegClass(offset
.type(), 1);
7456 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7458 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7461 case nir_intrinsic_load_front_face
: {
7462 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7463 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7466 case nir_intrinsic_load_view_index
: {
7467 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7468 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7469 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7475 case nir_intrinsic_load_layer_id
: {
7476 unsigned idx
= nir_intrinsic_base(instr
);
7477 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7478 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7481 case nir_intrinsic_load_frag_coord
: {
7482 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7485 case nir_intrinsic_load_sample_pos
: {
7486 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7487 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7488 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7489 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7490 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7493 case nir_intrinsic_load_tess_coord
:
7494 visit_load_tess_coord(ctx
, instr
);
7496 case nir_intrinsic_load_interpolated_input
:
7497 visit_load_interpolated_input(ctx
, instr
);
7499 case nir_intrinsic_store_output
:
7500 visit_store_output(ctx
, instr
);
7502 case nir_intrinsic_load_input
:
7503 case nir_intrinsic_load_input_vertex
:
7504 visit_load_input(ctx
, instr
);
7506 case nir_intrinsic_load_output
:
7507 visit_load_output(ctx
, instr
);
7509 case nir_intrinsic_load_per_vertex_input
:
7510 visit_load_per_vertex_input(ctx
, instr
);
7512 case nir_intrinsic_load_per_vertex_output
:
7513 visit_load_per_vertex_output(ctx
, instr
);
7515 case nir_intrinsic_store_per_vertex_output
:
7516 visit_store_per_vertex_output(ctx
, instr
);
7518 case nir_intrinsic_load_ubo
:
7519 visit_load_ubo(ctx
, instr
);
7521 case nir_intrinsic_load_push_constant
:
7522 visit_load_push_constant(ctx
, instr
);
7524 case nir_intrinsic_load_constant
:
7525 visit_load_constant(ctx
, instr
);
7527 case nir_intrinsic_vulkan_resource_index
:
7528 visit_load_resource(ctx
, instr
);
7530 case nir_intrinsic_discard
:
7531 visit_discard(ctx
, instr
);
7533 case nir_intrinsic_discard_if
:
7534 visit_discard_if(ctx
, instr
);
7536 case nir_intrinsic_load_shared
:
7537 visit_load_shared(ctx
, instr
);
7539 case nir_intrinsic_store_shared
:
7540 visit_store_shared(ctx
, instr
);
7542 case nir_intrinsic_shared_atomic_add
:
7543 case nir_intrinsic_shared_atomic_imin
:
7544 case nir_intrinsic_shared_atomic_umin
:
7545 case nir_intrinsic_shared_atomic_imax
:
7546 case nir_intrinsic_shared_atomic_umax
:
7547 case nir_intrinsic_shared_atomic_and
:
7548 case nir_intrinsic_shared_atomic_or
:
7549 case nir_intrinsic_shared_atomic_xor
:
7550 case nir_intrinsic_shared_atomic_exchange
:
7551 case nir_intrinsic_shared_atomic_comp_swap
:
7552 case nir_intrinsic_shared_atomic_fadd
:
7553 visit_shared_atomic(ctx
, instr
);
7555 case nir_intrinsic_image_deref_load
:
7556 visit_image_load(ctx
, instr
);
7558 case nir_intrinsic_image_deref_store
:
7559 visit_image_store(ctx
, instr
);
7561 case nir_intrinsic_image_deref_atomic_add
:
7562 case nir_intrinsic_image_deref_atomic_umin
:
7563 case nir_intrinsic_image_deref_atomic_imin
:
7564 case nir_intrinsic_image_deref_atomic_umax
:
7565 case nir_intrinsic_image_deref_atomic_imax
:
7566 case nir_intrinsic_image_deref_atomic_and
:
7567 case nir_intrinsic_image_deref_atomic_or
:
7568 case nir_intrinsic_image_deref_atomic_xor
:
7569 case nir_intrinsic_image_deref_atomic_exchange
:
7570 case nir_intrinsic_image_deref_atomic_comp_swap
:
7571 visit_image_atomic(ctx
, instr
);
7573 case nir_intrinsic_image_deref_size
:
7574 visit_image_size(ctx
, instr
);
7576 case nir_intrinsic_load_ssbo
:
7577 visit_load_ssbo(ctx
, instr
);
7579 case nir_intrinsic_store_ssbo
:
7580 visit_store_ssbo(ctx
, instr
);
7582 case nir_intrinsic_load_global
:
7583 visit_load_global(ctx
, instr
);
7585 case nir_intrinsic_store_global
:
7586 visit_store_global(ctx
, instr
);
7588 case nir_intrinsic_global_atomic_add
:
7589 case nir_intrinsic_global_atomic_imin
:
7590 case nir_intrinsic_global_atomic_umin
:
7591 case nir_intrinsic_global_atomic_imax
:
7592 case nir_intrinsic_global_atomic_umax
:
7593 case nir_intrinsic_global_atomic_and
:
7594 case nir_intrinsic_global_atomic_or
:
7595 case nir_intrinsic_global_atomic_xor
:
7596 case nir_intrinsic_global_atomic_exchange
:
7597 case nir_intrinsic_global_atomic_comp_swap
:
7598 visit_global_atomic(ctx
, instr
);
7600 case nir_intrinsic_ssbo_atomic_add
:
7601 case nir_intrinsic_ssbo_atomic_imin
:
7602 case nir_intrinsic_ssbo_atomic_umin
:
7603 case nir_intrinsic_ssbo_atomic_imax
:
7604 case nir_intrinsic_ssbo_atomic_umax
:
7605 case nir_intrinsic_ssbo_atomic_and
:
7606 case nir_intrinsic_ssbo_atomic_or
:
7607 case nir_intrinsic_ssbo_atomic_xor
:
7608 case nir_intrinsic_ssbo_atomic_exchange
:
7609 case nir_intrinsic_ssbo_atomic_comp_swap
:
7610 visit_atomic_ssbo(ctx
, instr
);
7612 case nir_intrinsic_load_scratch
:
7613 visit_load_scratch(ctx
, instr
);
7615 case nir_intrinsic_store_scratch
:
7616 visit_store_scratch(ctx
, instr
);
7618 case nir_intrinsic_get_buffer_size
:
7619 visit_get_buffer_size(ctx
, instr
);
7621 case nir_intrinsic_scoped_barrier
:
7622 emit_scoped_barrier(ctx
, instr
);
7624 case nir_intrinsic_load_num_work_groups
: {
7625 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7626 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7627 emit_split_vector(ctx
, dst
, 3);
7630 case nir_intrinsic_load_local_invocation_id
: {
7631 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7632 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7633 emit_split_vector(ctx
, dst
, 3);
7636 case nir_intrinsic_load_work_group_id
: {
7637 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7638 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7639 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7640 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7641 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7642 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7643 emit_split_vector(ctx
, dst
, 3);
7646 case nir_intrinsic_load_local_invocation_index
: {
7647 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7649 /* The tg_size bits [6:11] contain the subgroup id,
7650 * we need this multiplied by the wave size, and then OR the thread id to it.
7652 if (ctx
->program
->wave_size
== 64) {
7653 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7654 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7655 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7656 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7658 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7659 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7660 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7661 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7665 case nir_intrinsic_load_subgroup_id
: {
7666 if (ctx
->stage
== compute_cs
) {
7667 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7668 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7670 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7674 case nir_intrinsic_load_subgroup_invocation
: {
7675 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7678 case nir_intrinsic_load_num_subgroups
: {
7679 if (ctx
->stage
== compute_cs
)
7680 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7681 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7683 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7686 case nir_intrinsic_ballot
: {
7687 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7688 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7689 Definition tmp
= bld
.def(dst
.regClass());
7690 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7691 if (instr
->src
[0].ssa
->bit_size
== 1) {
7692 assert(src
.regClass() == bld
.lm
);
7693 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7694 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7695 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7696 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7697 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7700 nir_print_instr(&instr
->instr
, stderr
);
7701 fprintf(stderr
, "\n");
7703 if (dst
.size() != bld
.lm
.size()) {
7704 /* Wave32 with ballot size set to 64 */
7705 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7707 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7710 case nir_intrinsic_shuffle
:
7711 case nir_intrinsic_read_invocation
: {
7712 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7713 if (!nir_src_is_divergent(instr
->src
[0])) {
7714 emit_uniform_subgroup(ctx
, instr
, src
);
7716 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7717 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7718 tid
= bld
.as_uniform(tid
);
7719 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7720 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7721 Temp tmp
= bld
.tmp(v1
);
7722 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7723 if (dst
.type() == RegType::vgpr
)
7724 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7726 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7727 } else if (src
.regClass() == v1
) {
7728 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7729 } else if (src
.regClass() == v2
) {
7730 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7731 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7732 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7733 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7734 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7735 emit_split_vector(ctx
, dst
, 2);
7736 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7737 assert(src
.regClass() == bld
.lm
);
7738 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7739 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7740 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7741 assert(src
.regClass() == bld
.lm
);
7743 if (ctx
->program
->chip_class
<= GFX7
)
7744 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7745 else if (ctx
->program
->wave_size
== 64)
7746 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7748 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7749 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7750 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7751 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7753 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7754 nir_print_instr(&instr
->instr
, stderr
);
7755 fprintf(stderr
, "\n");
7760 case nir_intrinsic_load_sample_id
: {
7761 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7762 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7765 case nir_intrinsic_load_sample_mask_in
: {
7766 visit_load_sample_mask_in(ctx
, instr
);
7769 case nir_intrinsic_read_first_invocation
: {
7770 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7771 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7772 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7774 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7776 } else if (src
.regClass() == v2
) {
7777 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7778 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7779 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7780 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7781 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7782 emit_split_vector(ctx
, dst
, 2);
7783 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7784 assert(src
.regClass() == bld
.lm
);
7785 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7786 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7787 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7788 } else if (src
.regClass() == s1
) {
7789 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7790 } else if (src
.regClass() == s2
) {
7791 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7793 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7794 nir_print_instr(&instr
->instr
, stderr
);
7795 fprintf(stderr
, "\n");
7799 case nir_intrinsic_vote_all
: {
7800 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7801 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7802 assert(src
.regClass() == bld
.lm
);
7803 assert(dst
.regClass() == bld
.lm
);
7805 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7806 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7807 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7810 case nir_intrinsic_vote_any
: {
7811 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7812 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7813 assert(src
.regClass() == bld
.lm
);
7814 assert(dst
.regClass() == bld
.lm
);
7816 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7817 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7820 case nir_intrinsic_reduce
:
7821 case nir_intrinsic_inclusive_scan
:
7822 case nir_intrinsic_exclusive_scan
: {
7823 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7824 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7825 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7826 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7827 nir_intrinsic_cluster_size(instr
) : 0;
7828 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7830 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7831 emit_uniform_subgroup(ctx
, instr
, src
);
7832 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7833 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7835 else if (op
== nir_op_iadd
)
7837 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7839 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7841 switch (instr
->intrinsic
) {
7842 case nir_intrinsic_reduce
:
7843 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7845 case nir_intrinsic_exclusive_scan
:
7846 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7848 case nir_intrinsic_inclusive_scan
:
7849 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7854 } else if (cluster_size
== 1) {
7855 bld
.copy(Definition(dst
), src
);
7857 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7859 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7863 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7864 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7879 unreachable("unknown reduction op");
7885 switch (instr
->intrinsic
) {
7886 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7887 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7888 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7890 unreachable("unknown reduce intrinsic");
7893 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7894 reduce
->operands
[0] = Operand(src
);
7895 // filled in by aco_reduce_assign.cpp, used internally as part of the
7897 assert(dst
.size() == 1 || dst
.size() == 2);
7898 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7899 reduce
->operands
[2] = Operand(v1
.as_linear());
7901 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7902 reduce
->definitions
[0] = Definition(tmp_dst
);
7903 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7904 reduce
->definitions
[2] = Definition();
7905 reduce
->definitions
[3] = Definition(scc
, s1
);
7906 reduce
->definitions
[4] = Definition();
7907 reduce
->reduce_op
= reduce_op
;
7908 reduce
->cluster_size
= cluster_size
;
7909 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7911 emit_wqm(ctx
, tmp_dst
, dst
);
7915 case nir_intrinsic_quad_broadcast
: {
7916 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7917 if (!nir_dest_is_divergent(instr
->dest
)) {
7918 emit_uniform_subgroup(ctx
, instr
, src
);
7920 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7921 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7922 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7924 if (instr
->dest
.ssa
.bit_size
== 1) {
7925 assert(src
.regClass() == bld
.lm
);
7926 assert(dst
.regClass() == bld
.lm
);
7927 uint32_t half_mask
= 0x11111111u
<< lane
;
7928 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7929 Temp tmp
= bld
.tmp(bld
.lm
);
7930 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7931 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7932 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7933 emit_wqm(ctx
, tmp
, dst
);
7934 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7935 Temp tmp
= bld
.tmp(v1
);
7936 if (ctx
->program
->chip_class
>= GFX8
)
7937 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7939 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7941 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7942 Temp tmp
= bld
.tmp(v1
);
7943 if (ctx
->program
->chip_class
>= GFX8
)
7944 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7946 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7947 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7948 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7949 if (ctx
->program
->chip_class
>= GFX8
)
7950 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7952 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7953 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7954 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7956 if (ctx
->program
->chip_class
>= GFX8
) {
7957 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7958 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7960 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7961 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7963 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7964 emit_split_vector(ctx
, dst
, 2);
7966 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7967 nir_print_instr(&instr
->instr
, stderr
);
7968 fprintf(stderr
, "\n");
7973 case nir_intrinsic_quad_swap_horizontal
:
7974 case nir_intrinsic_quad_swap_vertical
:
7975 case nir_intrinsic_quad_swap_diagonal
:
7976 case nir_intrinsic_quad_swizzle_amd
: {
7977 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7978 if (!nir_dest_is_divergent(instr
->dest
)) {
7979 emit_uniform_subgroup(ctx
, instr
, src
);
7982 uint16_t dpp_ctrl
= 0;
7983 switch (instr
->intrinsic
) {
7984 case nir_intrinsic_quad_swap_horizontal
:
7985 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7987 case nir_intrinsic_quad_swap_vertical
:
7988 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7990 case nir_intrinsic_quad_swap_diagonal
:
7991 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7993 case nir_intrinsic_quad_swizzle_amd
:
7994 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7999 if (ctx
->program
->chip_class
< GFX8
)
8000 dpp_ctrl
|= (1 << 15);
8002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8003 if (instr
->dest
.ssa
.bit_size
== 1) {
8004 assert(src
.regClass() == bld
.lm
);
8005 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
8006 if (ctx
->program
->chip_class
>= GFX8
)
8007 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8009 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8010 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8011 emit_wqm(ctx
, tmp
, dst
);
8012 } else if (instr
->dest
.ssa
.bit_size
== 8) {
8013 Temp tmp
= bld
.tmp(v1
);
8014 if (ctx
->program
->chip_class
>= GFX8
)
8015 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8017 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8018 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
8019 } else if (instr
->dest
.ssa
.bit_size
== 16) {
8020 Temp tmp
= bld
.tmp(v1
);
8021 if (ctx
->program
->chip_class
>= GFX8
)
8022 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8024 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
8026 } else if (instr
->dest
.ssa
.bit_size
== 32) {
8028 if (ctx
->program
->chip_class
>= GFX8
)
8029 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8031 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8032 emit_wqm(ctx
, tmp
, dst
);
8033 } else if (instr
->dest
.ssa
.bit_size
== 64) {
8034 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8035 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8036 if (ctx
->program
->chip_class
>= GFX8
) {
8037 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8038 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8040 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8041 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8043 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8044 emit_split_vector(ctx
, dst
, 2);
8046 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8047 nir_print_instr(&instr
->instr
, stderr
);
8048 fprintf(stderr
, "\n");
8052 case nir_intrinsic_masked_swizzle_amd
: {
8053 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8054 if (!nir_dest_is_divergent(instr
->dest
)) {
8055 emit_uniform_subgroup(ctx
, instr
, src
);
8058 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8059 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
8060 if (instr
->dest
.ssa
.bit_size
== 1) {
8061 assert(src
.regClass() == bld
.lm
);
8062 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
8063 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
8064 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8065 emit_wqm(ctx
, tmp
, dst
);
8066 } else if (dst
.regClass() == v1b
) {
8067 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8068 emit_extract_vector(ctx
, tmp
, 0, dst
);
8069 } else if (dst
.regClass() == v2b
) {
8070 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8071 emit_extract_vector(ctx
, tmp
, 0, dst
);
8072 } else if (dst
.regClass() == v1
) {
8073 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
8074 } else if (dst
.regClass() == v2
) {
8075 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8077 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
8078 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
8079 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8080 emit_split_vector(ctx
, dst
, 2);
8082 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8083 nir_print_instr(&instr
->instr
, stderr
);
8084 fprintf(stderr
, "\n");
8088 case nir_intrinsic_write_invocation_amd
: {
8089 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8090 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8091 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8092 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8093 if (dst
.regClass() == v1
) {
8094 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8095 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8096 } else if (dst
.regClass() == v2
) {
8097 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8098 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8099 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8100 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8101 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8102 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8104 emit_split_vector(ctx
, dst
, 2);
8106 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8107 nir_print_instr(&instr
->instr
, stderr
);
8108 fprintf(stderr
, "\n");
8112 case nir_intrinsic_mbcnt_amd
: {
8113 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8114 RegClass rc
= RegClass(src
.type(), 1);
8115 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8116 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8117 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8118 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8119 emit_wqm(ctx
, wqm_tmp
, dst
);
8122 case nir_intrinsic_load_helper_invocation
: {
8123 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8124 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8125 ctx
->block
->kind
|= block_kind_needs_lowering
;
8126 ctx
->program
->needs_exact
= true;
8129 case nir_intrinsic_is_helper_invocation
: {
8130 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8131 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8132 ctx
->block
->kind
|= block_kind_needs_lowering
;
8133 ctx
->program
->needs_exact
= true;
8136 case nir_intrinsic_demote
:
8137 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8139 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8140 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8141 ctx
->block
->kind
|= block_kind_uses_demote
;
8142 ctx
->program
->needs_exact
= true;
8144 case nir_intrinsic_demote_if
: {
8145 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8146 assert(src
.regClass() == bld
.lm
);
8147 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8148 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8150 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8151 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8152 ctx
->block
->kind
|= block_kind_uses_demote
;
8153 ctx
->program
->needs_exact
= true;
8156 case nir_intrinsic_first_invocation
: {
8157 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8158 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8161 case nir_intrinsic_shader_clock
: {
8162 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8163 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
8164 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
8165 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
8166 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
8169 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8170 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8171 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
8173 emit_split_vector(ctx
, dst
, 2);
8176 case nir_intrinsic_load_vertex_id_zero_base
: {
8177 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8178 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8181 case nir_intrinsic_load_first_vertex
: {
8182 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8183 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8186 case nir_intrinsic_load_base_instance
: {
8187 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8188 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8191 case nir_intrinsic_load_instance_id
: {
8192 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8193 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8196 case nir_intrinsic_load_draw_id
: {
8197 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8198 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8201 case nir_intrinsic_load_invocation_id
: {
8202 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8204 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8205 if (ctx
->options
->chip_class
>= GFX10
)
8206 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8208 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8209 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8210 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8211 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8213 unreachable("Unsupported stage for load_invocation_id");
8218 case nir_intrinsic_load_primitive_id
: {
8219 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8221 switch (ctx
->shader
->info
.stage
) {
8222 case MESA_SHADER_GEOMETRY
:
8223 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8225 case MESA_SHADER_TESS_CTRL
:
8226 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8228 case MESA_SHADER_TESS_EVAL
:
8229 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8232 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8237 case nir_intrinsic_load_patch_vertices_in
: {
8238 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8239 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8241 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8242 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8245 case nir_intrinsic_emit_vertex_with_counter
: {
8246 visit_emit_vertex_with_counter(ctx
, instr
);
8249 case nir_intrinsic_end_primitive_with_counter
: {
8250 unsigned stream
= nir_intrinsic_stream_id(instr
);
8251 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8254 case nir_intrinsic_set_vertex_count
: {
8255 /* unused, the HW keeps track of this for us */
8259 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8260 nir_print_instr(&instr
->instr
, stderr
);
8261 fprintf(stderr
, "\n");
8269 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8270 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8271 enum glsl_base_type
*stype
)
8273 nir_deref_instr
*texture_deref_instr
= NULL
;
8274 nir_deref_instr
*sampler_deref_instr
= NULL
;
8277 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8278 switch (instr
->src
[i
].src_type
) {
8279 case nir_tex_src_texture_deref
:
8280 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8282 case nir_tex_src_sampler_deref
:
8283 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8285 case nir_tex_src_plane
:
8286 plane
= nir_src_as_int(instr
->src
[i
].src
);
8293 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8295 if (!sampler_deref_instr
)
8296 sampler_deref_instr
= texture_deref_instr
;
8299 assert(instr
->op
!= nir_texop_txf_ms
&&
8300 instr
->op
!= nir_texop_samples_identical
);
8301 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8302 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8303 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8304 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8305 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8306 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8308 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8311 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8313 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8314 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8315 Builder
bld(ctx
->program
, ctx
->block
);
8317 /* to avoid unnecessary moves, we split and recombine sampler and image */
8318 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8319 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8320 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8321 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8322 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8323 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8324 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8325 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8327 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8328 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8329 img
[0], img
[1], img
[2], img
[3],
8330 img
[4], img
[5], img
[6], img
[7]);
8331 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8332 samp
[0], samp
[1], samp
[2], samp
[3]);
8335 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8336 instr
->op
== nir_texop_samples_identical
))
8337 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8340 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8341 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8343 Builder
bld(ctx
->program
, ctx
->block
);
8345 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8346 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8347 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8349 Operand
neg_one(0xbf800000u
);
8350 Operand
one(0x3f800000u
);
8351 Operand
two(0x40000000u
);
8352 Operand
four(0x40800000u
);
8354 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8355 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8356 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8358 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8359 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8360 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8361 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8364 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8365 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8366 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8368 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8371 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8372 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8373 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8376 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8377 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8379 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8380 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8383 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8385 Builder
bld(ctx
->program
, ctx
->block
);
8386 Temp ma
, tc
, sc
, id
;
8387 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8388 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8391 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8393 // see comment in ac_prepare_cube_coords()
8394 if (ctx
->options
->chip_class
<= GFX8
)
8395 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8398 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8400 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8401 vop3a
->operands
[0] = Operand(ma
);
8402 vop3a
->abs
[0] = true;
8403 Temp invma
= bld
.tmp(v1
);
8404 vop3a
->definitions
[0] = Definition(invma
);
8405 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8407 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8409 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8411 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8413 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8415 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8418 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8419 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8421 for (unsigned i
= 0; i
< 2; i
++) {
8422 // see comment in ac_prepare_cube_coords()
8424 Temp deriv_sc
, deriv_tc
;
8425 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8426 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8428 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8430 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8431 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8432 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8433 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8434 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8435 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8436 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8439 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8440 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8444 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8451 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8453 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8455 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8456 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8459 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8460 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8461 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8465 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8467 Builder
bld(ctx
->program
, ctx
->block
);
8468 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8469 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8470 has_clamped_lod
= false;
8471 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8472 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8473 clamped_lod
= Temp();
8474 std::vector
<Temp
> coords
;
8475 std::vector
<Temp
> derivs
;
8476 nir_const_value
*sample_index_cv
= NULL
;
8477 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8478 enum glsl_base_type stype
;
8479 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8481 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8482 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8483 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8484 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8486 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8487 switch (instr
->src
[i
].src_type
) {
8488 case nir_tex_src_coord
: {
8489 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8490 for (unsigned i
= 0; i
< coord
.size(); i
++)
8491 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8494 case nir_tex_src_bias
:
8495 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8498 case nir_tex_src_lod
: {
8499 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8501 if (val
&& val
->f32
<= 0.0) {
8504 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8509 case nir_tex_src_min_lod
:
8510 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8511 has_clamped_lod
= true;
8513 case nir_tex_src_comparator
:
8514 if (instr
->is_shadow
) {
8515 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8519 case nir_tex_src_offset
:
8520 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8521 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8524 case nir_tex_src_ddx
:
8525 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8528 case nir_tex_src_ddy
:
8529 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8532 case nir_tex_src_ms_index
:
8533 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8534 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8535 has_sample_index
= true;
8537 case nir_tex_src_texture_offset
:
8538 case nir_tex_src_sampler_offset
:
8544 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8545 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8547 if (instr
->op
== nir_texop_texture_samples
) {
8548 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8550 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8551 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8552 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8554 Operand default_sample
= Operand(1u);
8555 if (ctx
->options
->robust_buffer_access
) {
8556 /* Extract the second dword of the descriptor, if it's
8557 * all zero, then it's a null descriptor.
8559 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8560 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8561 default_sample
= Operand(is_non_null_descriptor
);
8564 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8565 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8566 samples
, default_sample
, bld
.scc(is_msaa
));
8570 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8571 aco_ptr
<Instruction
> tmp_instr
;
8572 Temp acc
, pack
= Temp();
8574 uint32_t pack_const
= 0;
8575 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8576 if (!const_offset
[i
])
8578 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8581 if (offset
.type() == RegType::sgpr
) {
8582 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8583 if (const_offset
[i
])
8586 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8587 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8590 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8593 if (pack
== Temp()) {
8596 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8600 if (pack_const
&& pack
!= Temp())
8601 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8603 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8604 if (const_offset
[i
])
8607 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8608 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8611 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8614 if (pack
== Temp()) {
8617 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8621 if (pack_const
&& pack
!= Temp())
8622 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8624 if (pack_const
&& pack
== Temp())
8625 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8626 else if (pack
== Temp())
8632 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8633 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8635 /* pack derivatives */
8636 if (has_ddx
|| has_ddy
) {
8637 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8638 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8639 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8640 derivs
= {ddx
, zero
, ddy
, zero
};
8642 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8643 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8644 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8645 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8650 if (instr
->coord_components
> 1 &&
8651 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8653 instr
->op
!= nir_texop_txf
)
8654 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8656 if (instr
->coord_components
> 2 &&
8657 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8658 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8659 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8660 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8662 instr
->op
!= nir_texop_txf
&&
8663 instr
->op
!= nir_texop_txf_ms
&&
8664 instr
->op
!= nir_texop_fragment_fetch
&&
8665 instr
->op
!= nir_texop_fragment_mask_fetch
)
8666 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8668 if (ctx
->options
->chip_class
== GFX9
&&
8669 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8670 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8671 assert(coords
.size() > 0 && coords
.size() < 3);
8673 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8674 Operand((uint32_t) 0) :
8675 Operand((uint32_t) 0x3f000000)));
8678 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8680 if (instr
->op
== nir_texop_samples_identical
)
8681 resource
= fmask_ptr
;
8683 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8684 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8685 instr
->op
!= nir_texop_txs
&&
8686 instr
->op
!= nir_texop_fragment_fetch
&&
8687 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8688 assert(has_sample_index
);
8689 Operand
op(sample_index
);
8690 if (sample_index_cv
)
8691 op
= Operand(sample_index_cv
->u32
);
8692 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8695 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8696 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8697 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8698 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8703 /* Build tex instruction */
8704 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8705 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8706 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8708 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8711 /* gather4 selects the component by dmask and always returns vec4 */
8712 if (instr
->op
== nir_texop_tg4
) {
8713 assert(instr
->dest
.ssa
.num_components
== 4);
8714 if (instr
->is_shadow
)
8717 dmask
= 1 << instr
->component
;
8718 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8719 tmp_dst
= bld
.tmp(v4
);
8720 } else if (instr
->op
== nir_texop_samples_identical
) {
8721 tmp_dst
= bld
.tmp(v1
);
8722 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8723 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8726 aco_ptr
<MIMG_instruction
> tex
;
8727 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8729 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8731 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8732 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8735 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8736 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8738 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8739 tex
->operands
[0] = Operand(resource
);
8740 tex
->operands
[1] = Operand(s4
); /* no sampler */
8741 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8742 if (ctx
->options
->chip_class
== GFX9
&&
8743 instr
->op
== nir_texop_txs
&&
8744 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8746 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8747 } else if (instr
->op
== nir_texop_query_levels
) {
8748 tex
->dmask
= 1 << 3;
8753 tex
->definitions
[0] = Definition(tmp_dst
);
8755 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8758 /* divide 3rd value by 6 by multiplying with magic number */
8759 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8760 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8761 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8762 assert(instr
->dest
.ssa
.num_components
== 3);
8763 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8764 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8765 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8766 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8771 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8775 Temp tg4_compare_cube_wa64
= Temp();
8777 if (tg4_integer_workarounds
) {
8778 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8779 tex
->operands
[0] = Operand(resource
);
8780 tex
->operands
[1] = Operand(s4
); /* no sampler */
8781 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8785 Temp size
= bld
.tmp(v2
);
8786 tex
->definitions
[0] = Definition(size
);
8787 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8788 emit_split_vector(ctx
, size
, size
.size());
8791 for (unsigned i
= 0; i
< 2; i
++) {
8792 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8793 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8794 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8795 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8798 Temp new_coords
[2] = {
8799 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8800 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8803 if (tg4_integer_cube_workaround
) {
8804 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8805 Temp desc
[resource
.size()];
8806 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8807 Format::PSEUDO
, 1, resource
.size())};
8808 split
->operands
[0] = Operand(resource
);
8809 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8810 desc
[i
] = bld
.tmp(s1
);
8811 split
->definitions
[i
] = Definition(desc
[i
]);
8813 ctx
->block
->instructions
.emplace_back(std::move(split
));
8815 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8816 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8817 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8820 if (stype
== GLSL_TYPE_UINT
) {
8821 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8822 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8823 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8824 bld
.scc(compare_cube_wa
));
8826 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8827 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8828 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8829 bld
.scc(compare_cube_wa
));
8831 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8832 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8834 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8836 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8837 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8838 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8840 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8841 Format::PSEUDO
, resource
.size(), 1)};
8842 for (unsigned i
= 0; i
< resource
.size(); i
++)
8843 vec
->operands
[i
] = Operand(desc
[i
]);
8844 resource
= bld
.tmp(resource
.regClass());
8845 vec
->definitions
[0] = Definition(resource
);
8846 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8848 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8849 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8850 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8851 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8853 coords
[0] = new_coords
[0];
8854 coords
[1] = new_coords
[1];
8857 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8858 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8860 assert(coords
.size() == 1);
8861 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8865 op
= aco_opcode::buffer_load_format_x
; break;
8867 op
= aco_opcode::buffer_load_format_xy
; break;
8869 op
= aco_opcode::buffer_load_format_xyz
; break;
8871 op
= aco_opcode::buffer_load_format_xyzw
; break;
8873 unreachable("Tex instruction loads more than 4 components.");
8876 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8877 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8880 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8882 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8883 mubuf
->operands
[0] = Operand(resource
);
8884 mubuf
->operands
[1] = Operand(coords
[0]);
8885 mubuf
->operands
[2] = Operand((uint32_t) 0);
8886 mubuf
->definitions
[0] = Definition(tmp_dst
);
8887 mubuf
->idxen
= true;
8888 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8890 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8894 /* gather MIMG address components */
8895 std::vector
<Temp
> args
;
8897 args
.emplace_back(offset
);
8899 args
.emplace_back(bias
);
8901 args
.emplace_back(compare
);
8903 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8905 args
.insert(args
.end(), coords
.begin(), coords
.end());
8906 if (has_sample_index
)
8907 args
.emplace_back(sample_index
);
8909 args
.emplace_back(lod
);
8910 if (has_clamped_lod
)
8911 args
.emplace_back(clamped_lod
);
8913 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8914 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8915 vec
->definitions
[0] = Definition(arg
);
8916 for (unsigned i
= 0; i
< args
.size(); i
++)
8917 vec
->operands
[i
] = Operand(args
[i
]);
8918 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8921 if (instr
->op
== nir_texop_txf
||
8922 instr
->op
== nir_texop_txf_ms
||
8923 instr
->op
== nir_texop_samples_identical
||
8924 instr
->op
== nir_texop_fragment_fetch
||
8925 instr
->op
== nir_texop_fragment_mask_fetch
) {
8926 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8927 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8928 tex
->operands
[0] = Operand(resource
);
8929 tex
->operands
[1] = Operand(s4
); /* no sampler */
8930 tex
->operands
[2] = Operand(arg
);
8935 tex
->definitions
[0] = Definition(tmp_dst
);
8936 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8938 if (instr
->op
== nir_texop_samples_identical
) {
8939 assert(dmask
== 1 && dst
.regClass() == v1
);
8940 assert(dst
.id() != tmp_dst
.id());
8942 Temp tmp
= bld
.tmp(bld
.lm
);
8943 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8944 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8947 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8952 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8953 aco_opcode opcode
= aco_opcode::image_sample
;
8954 if (has_offset
) { /* image_sample_*_o */
8955 if (has_clamped_lod
) {
8957 opcode
= aco_opcode::image_sample_c_cl_o
;
8959 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8961 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8963 opcode
= aco_opcode::image_sample_cl_o
;
8965 opcode
= aco_opcode::image_sample_d_cl_o
;
8967 opcode
= aco_opcode::image_sample_b_cl_o
;
8969 } else if (has_compare
) {
8970 opcode
= aco_opcode::image_sample_c_o
;
8972 opcode
= aco_opcode::image_sample_c_d_o
;
8974 opcode
= aco_opcode::image_sample_c_b_o
;
8976 opcode
= aco_opcode::image_sample_c_lz_o
;
8978 opcode
= aco_opcode::image_sample_c_l_o
;
8980 opcode
= aco_opcode::image_sample_o
;
8982 opcode
= aco_opcode::image_sample_d_o
;
8984 opcode
= aco_opcode::image_sample_b_o
;
8986 opcode
= aco_opcode::image_sample_lz_o
;
8988 opcode
= aco_opcode::image_sample_l_o
;
8990 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8992 opcode
= aco_opcode::image_sample_c_cl
;
8994 opcode
= aco_opcode::image_sample_c_d_cl
;
8996 opcode
= aco_opcode::image_sample_c_b_cl
;
8998 opcode
= aco_opcode::image_sample_cl
;
9000 opcode
= aco_opcode::image_sample_d_cl
;
9002 opcode
= aco_opcode::image_sample_b_cl
;
9004 } else { /* no offset */
9006 opcode
= aco_opcode::image_sample_c
;
9008 opcode
= aco_opcode::image_sample_c_d
;
9010 opcode
= aco_opcode::image_sample_c_b
;
9012 opcode
= aco_opcode::image_sample_c_lz
;
9014 opcode
= aco_opcode::image_sample_c_l
;
9016 opcode
= aco_opcode::image_sample
;
9018 opcode
= aco_opcode::image_sample_d
;
9020 opcode
= aco_opcode::image_sample_b
;
9022 opcode
= aco_opcode::image_sample_lz
;
9024 opcode
= aco_opcode::image_sample_l
;
9028 if (instr
->op
== nir_texop_tg4
) {
9029 if (has_offset
) { /* image_gather4_*_o */
9031 opcode
= aco_opcode::image_gather4_c_lz_o
;
9033 opcode
= aco_opcode::image_gather4_c_l_o
;
9035 opcode
= aco_opcode::image_gather4_c_b_o
;
9037 opcode
= aco_opcode::image_gather4_lz_o
;
9039 opcode
= aco_opcode::image_gather4_l_o
;
9041 opcode
= aco_opcode::image_gather4_b_o
;
9045 opcode
= aco_opcode::image_gather4_c_lz
;
9047 opcode
= aco_opcode::image_gather4_c_l
;
9049 opcode
= aco_opcode::image_gather4_c_b
;
9051 opcode
= aco_opcode::image_gather4_lz
;
9053 opcode
= aco_opcode::image_gather4_l
;
9055 opcode
= aco_opcode::image_gather4_b
;
9058 } else if (instr
->op
== nir_texop_lod
) {
9059 opcode
= aco_opcode::image_get_lod
;
9062 /* we don't need the bias, sample index, compare value or offset to be
9063 * computed in WQM but if the p_create_vector copies the coordinates, then it
9064 * needs to be in WQM */
9065 if (ctx
->stage
== fragment_fs
&&
9066 !has_derivs
&& !has_lod
&& !level_zero
&&
9067 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
9068 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
9069 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
9071 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
9072 tex
->operands
[0] = Operand(resource
);
9073 tex
->operands
[1] = Operand(sampler
);
9074 tex
->operands
[2] = Operand(arg
);
9078 tex
->definitions
[0] = Definition(tmp_dst
);
9079 ctx
->block
->instructions
.emplace_back(std::move(tex
));
9081 if (tg4_integer_cube_workaround
) {
9082 assert(tmp_dst
.id() != dst
.id());
9083 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
9085 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
9087 for (unsigned i
= 0; i
< dst
.size(); i
++) {
9088 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
9090 if (stype
== GLSL_TYPE_UINT
)
9091 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
9093 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
9094 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
9096 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
9097 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
9098 val
[0], val
[1], val
[2], val
[3]);
9100 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
9101 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
9106 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
9108 Temp tmp
= get_ssa_temp(ctx
, ssa
);
9109 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
9111 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
9112 if (ctx
->program
->wave_size
== 64)
9113 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
9115 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
9117 return Operand(tmp
);
9121 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9123 aco_ptr
<Pseudo_instruction
> phi
;
9124 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9125 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9127 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
9128 logical
|= ctx
->block
->kind
& block_kind_merge
;
9129 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9131 /* we want a sorted list of sources, since the predecessor list is also sorted */
9132 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9133 nir_foreach_phi_src(src
, instr
)
9134 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9136 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9137 unsigned num_operands
= 0;
9138 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9139 unsigned num_defined
= 0;
9140 unsigned cur_pred_idx
= 0;
9141 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9142 if (cur_pred_idx
< preds
.size()) {
9143 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9144 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9145 unsigned skipped
= 0;
9146 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9148 if (cur_pred_idx
+ skipped
< preds
.size()) {
9149 for (unsigned i
= 0; i
< skipped
; i
++)
9150 operands
[num_operands
++] = Operand(dst
.regClass());
9151 cur_pred_idx
+= skipped
;
9156 /* Handle missing predecessors at the end. This shouldn't happen with loop
9157 * headers and we can't ignore these sources for loop header phis. */
9158 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9161 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9162 operands
[num_operands
++] = op
;
9163 num_defined
+= !op
.isUndefined();
9165 /* handle block_kind_continue_or_break at loop exit blocks */
9166 while (cur_pred_idx
++ < preds
.size())
9167 operands
[num_operands
++] = Operand(dst
.regClass());
9169 /* If the loop ends with a break, still add a linear continue edge in case
9170 * that break is divergent or continue_or_break is used. We'll either remove
9171 * this operand later in visit_loop() if it's not necessary or replace the
9172 * undef with something correct. */
9173 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9174 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9175 nir_block
*last
= nir_loop_last_block(loop
);
9176 if (last
->successors
[0] != instr
->instr
.block
)
9177 operands
[num_operands
++] = Operand(RegClass());
9180 if (num_defined
== 0) {
9181 Builder
bld(ctx
->program
, ctx
->block
);
9182 if (dst
.regClass() == s1
) {
9183 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9184 } else if (dst
.regClass() == v1
) {
9185 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9187 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9188 for (unsigned i
= 0; i
< dst
.size(); i
++)
9189 vec
->operands
[i
] = Operand(0u);
9190 vec
->definitions
[0] = Definition(dst
);
9191 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9196 /* we can use a linear phi in some cases if one src is undef */
9197 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9198 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9200 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9201 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9202 assert(invert
->kind
& block_kind_invert
);
9204 unsigned then_block
= invert
->linear_preds
[0];
9206 Block
* insert_block
= NULL
;
9207 for (unsigned i
= 0; i
< num_operands
; i
++) {
9208 Operand op
= operands
[i
];
9209 if (op
.isUndefined())
9211 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9212 phi
->operands
[0] = op
;
9215 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9216 phi
->operands
[1] = Operand(dst
.regClass());
9217 phi
->definitions
[0] = Definition(dst
);
9218 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9222 /* try to scalarize vector phis */
9223 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9224 // TODO: scalarize linear phis on divergent ifs
9225 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9226 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9227 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9228 Operand src
= operands
[i
];
9229 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9230 can_scalarize
= false;
9232 if (can_scalarize
) {
9233 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9234 assert(dst
.size() % num_components
== 0);
9235 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9237 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9238 for (unsigned k
= 0; k
< num_components
; k
++) {
9239 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9240 for (unsigned i
= 0; i
< num_operands
; i
++) {
9241 Operand src
= operands
[i
];
9242 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9244 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9245 phi
->definitions
[0] = Definition(phi_dst
);
9246 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9247 new_vec
[k
] = phi_dst
;
9248 vec
->operands
[k
] = Operand(phi_dst
);
9250 vec
->definitions
[0] = Definition(dst
);
9251 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9252 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9257 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9258 for (unsigned i
= 0; i
< num_operands
; i
++)
9259 phi
->operands
[i
] = operands
[i
];
9260 phi
->definitions
[0] = Definition(dst
);
9261 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9265 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9267 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9269 assert(dst
.type() == RegType::sgpr
);
9271 if (dst
.size() == 1) {
9272 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9274 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9275 for (unsigned i
= 0; i
< dst
.size(); i
++)
9276 vec
->operands
[i
] = Operand(0u);
9277 vec
->definitions
[0] = Definition(dst
);
9278 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9282 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9284 Builder
bld(ctx
->program
, ctx
->block
);
9285 Block
*logical_target
;
9286 append_logical_end(ctx
->block
);
9287 unsigned idx
= ctx
->block
->index
;
9289 switch (instr
->type
) {
9290 case nir_jump_break
:
9291 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9292 add_logical_edge(idx
, logical_target
);
9293 ctx
->block
->kind
|= block_kind_break
;
9295 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9296 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9297 /* uniform break - directly jump out of the loop */
9298 ctx
->block
->kind
|= block_kind_uniform
;
9299 ctx
->cf_info
.has_branch
= true;
9300 bld
.branch(aco_opcode::p_branch
);
9301 add_linear_edge(idx
, logical_target
);
9304 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9305 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9307 case nir_jump_continue
:
9308 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9309 add_logical_edge(idx
, logical_target
);
9310 ctx
->block
->kind
|= block_kind_continue
;
9312 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9313 /* for potential uniform breaks after this continue,
9314 we must ensure that they are handled correctly */
9315 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9316 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9317 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9319 /* uniform continue - directly jump to the loop header */
9320 ctx
->block
->kind
|= block_kind_uniform
;
9321 ctx
->cf_info
.has_branch
= true;
9322 bld
.branch(aco_opcode::p_branch
);
9323 add_linear_edge(idx
, logical_target
);
9328 fprintf(stderr
, "Unknown NIR jump instr: ");
9329 nir_print_instr(&instr
->instr
, stderr
);
9330 fprintf(stderr
, "\n");
9334 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9335 ctx
->cf_info
.exec_potentially_empty_break
= true;
9336 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9339 /* remove critical edges from linear CFG */
9340 bld
.branch(aco_opcode::p_branch
);
9341 Block
* break_block
= ctx
->program
->create_and_insert_block();
9342 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9343 break_block
->kind
|= block_kind_uniform
;
9344 add_linear_edge(idx
, break_block
);
9345 /* the loop_header pointer might be invalidated by this point */
9346 if (instr
->type
== nir_jump_continue
)
9347 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9348 add_linear_edge(break_block
->index
, logical_target
);
9349 bld
.reset(break_block
);
9350 bld
.branch(aco_opcode::p_branch
);
9352 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9353 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9354 add_linear_edge(idx
, continue_block
);
9355 append_logical_start(continue_block
);
9356 ctx
->block
= continue_block
;
9360 void visit_block(isel_context
*ctx
, nir_block
*block
)
9362 nir_foreach_instr(instr
, block
) {
9363 switch (instr
->type
) {
9364 case nir_instr_type_alu
:
9365 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9367 case nir_instr_type_load_const
:
9368 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9370 case nir_instr_type_intrinsic
:
9371 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9373 case nir_instr_type_tex
:
9374 visit_tex(ctx
, nir_instr_as_tex(instr
));
9376 case nir_instr_type_phi
:
9377 visit_phi(ctx
, nir_instr_as_phi(instr
));
9379 case nir_instr_type_ssa_undef
:
9380 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9382 case nir_instr_type_deref
:
9384 case nir_instr_type_jump
:
9385 visit_jump(ctx
, nir_instr_as_jump(instr
));
9388 fprintf(stderr
, "Unknown NIR instr type: ");
9389 nir_print_instr(instr
, stderr
);
9390 fprintf(stderr
, "\n");
9395 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9396 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9401 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9402 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9404 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9405 RegClass rc
= vals
[0].regClass();
9407 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9409 unsigned next_pred
= 1;
9411 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9412 Block
& block
= ctx
->program
->blocks
[idx
];
9413 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9414 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9418 if (block
.kind
& block_kind_continue
) {
9419 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9424 bool all_same
= true;
9425 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9426 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9430 val
= vals
[block
.linear_preds
[0] - first
];
9432 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9433 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9434 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9435 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9436 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9437 phi
->definitions
[0] = Definition(val
.getTemp());
9438 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9440 vals
[idx
- first
] = val
;
9443 return vals
[last
- first
];
9446 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9448 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9449 append_logical_end(ctx
->block
);
9450 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9451 Builder
bld(ctx
->program
, ctx
->block
);
9452 bld
.branch(aco_opcode::p_branch
);
9453 unsigned loop_preheader_idx
= ctx
->block
->index
;
9455 Block loop_exit
= Block();
9456 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9457 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9459 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9460 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9461 loop_header
->kind
|= block_kind_loop_header
;
9462 add_edge(loop_preheader_idx
, loop_header
);
9463 ctx
->block
= loop_header
;
9465 /* emit loop body */
9466 unsigned loop_header_idx
= loop_header
->index
;
9467 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9468 append_logical_start(ctx
->block
);
9469 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9471 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9472 if (!ctx
->cf_info
.has_branch
) {
9473 append_logical_end(ctx
->block
);
9474 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9475 /* Discards can result in code running with an empty exec mask.
9476 * This would result in divergent breaks not ever being taken. As a
9477 * workaround, break the loop when the loop mask is empty instead of
9478 * always continuing. */
9479 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9480 unsigned block_idx
= ctx
->block
->index
;
9482 /* create helper blocks to avoid critical edges */
9483 Block
*break_block
= ctx
->program
->create_and_insert_block();
9484 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9485 break_block
->kind
= block_kind_uniform
;
9486 bld
.reset(break_block
);
9487 bld
.branch(aco_opcode::p_branch
);
9488 add_linear_edge(block_idx
, break_block
);
9489 add_linear_edge(break_block
->index
, &loop_exit
);
9491 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9492 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9493 continue_block
->kind
= block_kind_uniform
;
9494 bld
.reset(continue_block
);
9495 bld
.branch(aco_opcode::p_branch
);
9496 add_linear_edge(block_idx
, continue_block
);
9497 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9499 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9500 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9501 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9503 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9504 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9505 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9507 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9510 bld
.reset(ctx
->block
);
9511 bld
.branch(aco_opcode::p_branch
);
9514 /* Fixup phis in loop header from unreachable blocks.
9515 * has_branch/has_divergent_branch also indicates if the loop ends with a
9516 * break/continue instruction, but we don't emit those if unreachable=true */
9518 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9519 bool linear
= ctx
->cf_info
.has_branch
;
9520 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9521 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9522 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9523 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9524 /* the last operand should be the one that needs to be removed */
9525 instr
->operands
.pop_back();
9526 } else if (!is_phi(instr
)) {
9532 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9533 * and the previous one shouldn't both happen at once because a break in the
9534 * merge block would get CSE'd */
9535 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9536 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9537 Operand vals
[num_vals
];
9538 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9539 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9540 if (ctx
->cf_info
.has_branch
)
9541 instr
->operands
.pop_back();
9543 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9544 } else if (!is_phi(instr
)) {
9550 ctx
->cf_info
.has_branch
= false;
9552 // TODO: if the loop has not a single exit, we must add one °°
9553 /* emit loop successor block */
9554 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9555 append_logical_start(ctx
->block
);
9558 // TODO: check if it is beneficial to not branch on continues
9559 /* trim linear phis in loop header */
9560 for (auto&& instr
: loop_entry
->instructions
) {
9561 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9562 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9563 new_phi
->definitions
[0] = instr
->definitions
[0];
9564 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9565 new_phi
->operands
[i
] = instr
->operands
[i
];
9566 /* check that the remaining operands are all the same */
9567 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9568 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9569 instr
.swap(new_phi
);
9570 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9579 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9583 append_logical_end(ctx
->block
);
9584 ctx
->block
->kind
|= block_kind_branch
;
9586 /* branch to linear then block */
9587 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9588 aco_ptr
<Pseudo_branch_instruction
> branch
;
9589 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9590 branch
->operands
[0] = Operand(cond
);
9591 ctx
->block
->instructions
.push_back(std::move(branch
));
9593 ic
->BB_if_idx
= ctx
->block
->index
;
9594 ic
->BB_invert
= Block();
9595 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9596 /* Invert blocks are intentionally not marked as top level because they
9597 * are not part of the logical cfg. */
9598 ic
->BB_invert
.kind
|= block_kind_invert
;
9599 ic
->BB_endif
= Block();
9600 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9601 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9603 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9604 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9605 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9606 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9607 ctx
->cf_info
.parent_if
.is_divergent
= true;
9609 /* divergent branches use cbranch_execz */
9610 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9611 ctx
->cf_info
.exec_potentially_empty_break
= false;
9612 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9614 /** emit logical then block */
9615 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9616 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9617 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9618 ctx
->block
= BB_then_logical
;
9619 append_logical_start(BB_then_logical
);
9622 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9624 Block
*BB_then_logical
= ctx
->block
;
9625 append_logical_end(BB_then_logical
);
9626 /* branch from logical then block to invert block */
9627 aco_ptr
<Pseudo_branch_instruction
> branch
;
9628 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9629 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9630 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9631 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9632 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9633 BB_then_logical
->kind
|= block_kind_uniform
;
9634 assert(!ctx
->cf_info
.has_branch
);
9635 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9636 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9638 /** emit linear then block */
9639 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9640 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9641 BB_then_linear
->kind
|= block_kind_uniform
;
9642 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9643 /* branch from linear then block to invert block */
9644 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9645 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9646 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9648 /** emit invert merge block */
9649 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9650 ic
->invert_idx
= ctx
->block
->index
;
9652 /* branch to linear else block (skip else) */
9653 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9654 branch
->operands
[0] = Operand(ic
->cond
);
9655 ctx
->block
->instructions
.push_back(std::move(branch
));
9657 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9658 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9659 ic
->exec_potentially_empty_break_depth_old
=
9660 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9661 /* divergent branches use cbranch_execz */
9662 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9663 ctx
->cf_info
.exec_potentially_empty_break
= false;
9664 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9666 /** emit logical else block */
9667 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9668 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9669 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9670 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9671 ctx
->block
= BB_else_logical
;
9672 append_logical_start(BB_else_logical
);
9675 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9677 Block
*BB_else_logical
= ctx
->block
;
9678 append_logical_end(BB_else_logical
);
9680 /* branch from logical else block to endif block */
9681 aco_ptr
<Pseudo_branch_instruction
> branch
;
9682 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9683 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9684 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9685 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9686 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9687 BB_else_logical
->kind
|= block_kind_uniform
;
9689 assert(!ctx
->cf_info
.has_branch
);
9690 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9693 /** emit linear else block */
9694 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9695 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9696 BB_else_linear
->kind
|= block_kind_uniform
;
9697 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9699 /* branch from linear else block to endif block */
9700 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9701 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9702 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9705 /** emit endif merge block */
9706 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9707 append_logical_start(ctx
->block
);
9710 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9711 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9712 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9713 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9714 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9715 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9716 !ctx
->cf_info
.parent_if
.is_divergent
) {
9717 ctx
->cf_info
.exec_potentially_empty_break
= false;
9718 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9720 /* uniform control flow never has an empty exec-mask */
9721 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9722 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9723 ctx
->cf_info
.exec_potentially_empty_break
= false;
9724 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9728 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9730 assert(cond
.regClass() == s1
);
9732 append_logical_end(ctx
->block
);
9733 ctx
->block
->kind
|= block_kind_uniform
;
9735 aco_ptr
<Pseudo_branch_instruction
> branch
;
9736 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9737 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9738 branch
->operands
[0] = Operand(cond
);
9739 branch
->operands
[0].setFixed(scc
);
9740 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9742 ic
->BB_if_idx
= ctx
->block
->index
;
9743 ic
->BB_endif
= Block();
9744 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9745 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9747 ctx
->cf_info
.has_branch
= false;
9748 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9750 /** emit then block */
9751 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9752 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9753 add_edge(ic
->BB_if_idx
, BB_then
);
9754 append_logical_start(BB_then
);
9755 ctx
->block
= BB_then
;
9758 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9760 Block
*BB_then
= ctx
->block
;
9762 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9763 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9765 if (!ic
->uniform_has_then_branch
) {
9766 append_logical_end(BB_then
);
9767 /* branch from then block to endif block */
9768 aco_ptr
<Pseudo_branch_instruction
> branch
;
9769 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9770 BB_then
->instructions
.emplace_back(std::move(branch
));
9771 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9772 if (!ic
->then_branch_divergent
)
9773 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9774 BB_then
->kind
|= block_kind_uniform
;
9777 ctx
->cf_info
.has_branch
= false;
9778 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9780 /** emit else block */
9781 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9782 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9783 add_edge(ic
->BB_if_idx
, BB_else
);
9784 append_logical_start(BB_else
);
9785 ctx
->block
= BB_else
;
9788 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9790 Block
*BB_else
= ctx
->block
;
9792 if (!ctx
->cf_info
.has_branch
) {
9793 append_logical_end(BB_else
);
9794 /* branch from then block to endif block */
9795 aco_ptr
<Pseudo_branch_instruction
> branch
;
9796 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9797 BB_else
->instructions
.emplace_back(std::move(branch
));
9798 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9799 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9800 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9801 BB_else
->kind
|= block_kind_uniform
;
9804 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9805 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9807 /** emit endif merge block */
9808 if (!ctx
->cf_info
.has_branch
) {
9809 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9810 append_logical_start(ctx
->block
);
9814 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9816 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9817 Builder
bld(ctx
->program
, ctx
->block
);
9818 aco_ptr
<Pseudo_branch_instruction
> branch
;
9821 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9823 * Uniform conditionals are represented in the following way*) :
9825 * The linear and logical CFG:
9828 * BB_THEN (logical) BB_ELSE (logical)
9832 * *) Exceptions may be due to break and continue statements within loops
9833 * If a break/continue happens within uniform control flow, it branches
9834 * to the loop exit/entry block. Otherwise, it branches to the next
9838 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9839 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9840 cond
= bool_to_scalar_condition(ctx
, cond
);
9842 begin_uniform_if_then(ctx
, &ic
, cond
);
9843 visit_cf_list(ctx
, &if_stmt
->then_list
);
9845 begin_uniform_if_else(ctx
, &ic
);
9846 visit_cf_list(ctx
, &if_stmt
->else_list
);
9848 end_uniform_if(ctx
, &ic
);
9849 } else { /* non-uniform condition */
9851 * To maintain a logical and linear CFG without critical edges,
9852 * non-uniform conditionals are represented in the following way*) :
9857 * BB_THEN (logical) BB_THEN (linear)
9859 * BB_INVERT (linear)
9861 * BB_ELSE (logical) BB_ELSE (linear)
9868 * BB_THEN (logical) BB_ELSE (logical)
9872 * *) Exceptions may be due to break and continue statements within loops
9875 begin_divergent_if_then(ctx
, &ic
, cond
);
9876 visit_cf_list(ctx
, &if_stmt
->then_list
);
9878 begin_divergent_if_else(ctx
, &ic
);
9879 visit_cf_list(ctx
, &if_stmt
->else_list
);
9881 end_divergent_if(ctx
, &ic
);
9884 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9887 static bool visit_cf_list(isel_context
*ctx
,
9888 struct exec_list
*list
)
9890 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9891 switch (node
->type
) {
9892 case nir_cf_node_block
:
9893 visit_block(ctx
, nir_cf_node_as_block(node
));
9895 case nir_cf_node_if
:
9896 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9899 case nir_cf_node_loop
:
9900 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9903 unreachable("unimplemented cf list type");
9909 static void create_null_export(isel_context
*ctx
)
9911 /* Some shader stages always need to have exports.
9912 * So when there is none, we need to add a null export.
9915 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9916 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9917 Builder
bld(ctx
->program
, ctx
->block
);
9918 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9919 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9922 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9924 assert(ctx
->stage
== vertex_vs
||
9925 ctx
->stage
== tess_eval_vs
||
9926 ctx
->stage
== gs_copy_vs
||
9927 ctx
->stage
== ngg_vertex_gs
||
9928 ctx
->stage
== ngg_tess_eval_gs
);
9930 int offset
= (ctx
->stage
& sw_tes
)
9931 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9932 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9933 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9934 if (!is_pos
&& !mask
)
9936 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9938 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9939 exp
->enabled_mask
= mask
;
9940 for (unsigned i
= 0; i
< 4; ++i
) {
9941 if (mask
& (1 << i
))
9942 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9944 exp
->operands
[i
] = Operand(v1
);
9946 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9947 * Setting valid_mask=1 prevents it and has no other effect.
9949 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9951 exp
->compressed
= false;
9953 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9955 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9956 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9961 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9963 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9964 exp
->enabled_mask
= 0;
9965 for (unsigned i
= 0; i
< 4; ++i
)
9966 exp
->operands
[i
] = Operand(v1
);
9967 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9968 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9969 exp
->enabled_mask
|= 0x1;
9971 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9972 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9973 exp
->enabled_mask
|= 0x4;
9975 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9976 if (ctx
->options
->chip_class
< GFX9
) {
9977 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9978 exp
->enabled_mask
|= 0x8;
9980 Builder
bld(ctx
->program
, ctx
->block
);
9982 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9983 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9984 if (exp
->operands
[2].isTemp())
9985 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9987 exp
->operands
[2] = Operand(out
);
9988 exp
->enabled_mask
|= 0x4;
9991 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9993 exp
->compressed
= false;
9994 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9995 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9998 static void create_export_phis(isel_context
*ctx
)
10000 /* Used when exports are needed, but the output temps are defined in a preceding block.
10001 * This function will set up phis in order to access the outputs in the next block.
10004 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
10005 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
10006 ctx
->block
->instructions
.pop_back();
10008 Builder
bld(ctx
->program
, ctx
->block
);
10010 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
10011 uint64_t mask
= ctx
->outputs
.mask
[slot
];
10012 for (unsigned i
= 0; i
< 4; ++i
) {
10013 if (!(mask
& (1 << i
)))
10016 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
10017 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
10018 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
10022 bld
.insert(std::move(logical_start
));
10025 static void create_vs_exports(isel_context
*ctx
)
10027 assert(ctx
->stage
== vertex_vs
||
10028 ctx
->stage
== tess_eval_vs
||
10029 ctx
->stage
== gs_copy_vs
||
10030 ctx
->stage
== ngg_vertex_gs
||
10031 ctx
->stage
== ngg_tess_eval_gs
);
10033 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
10034 ? &ctx
->program
->info
->tes
.outinfo
10035 : &ctx
->program
->info
->vs
.outinfo
;
10037 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
10038 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10039 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
10042 if (ctx
->options
->key
.has_multiview_view_index
) {
10043 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
10044 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
10047 /* the order these position exports are created is important */
10049 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
10050 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
10051 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
10052 exported_pos
= true;
10054 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10055 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
10056 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10057 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
10059 if (ctx
->export_clip_dists
) {
10060 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10061 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
10062 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10063 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
10066 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10067 if (i
< VARYING_SLOT_VAR0
&&
10068 i
!= VARYING_SLOT_LAYER
&&
10069 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
10070 i
!= VARYING_SLOT_VIEWPORT
)
10073 export_vs_varying(ctx
, i
, false, NULL
);
10077 create_null_export(ctx
);
10080 static bool export_fs_mrt_z(isel_context
*ctx
)
10082 Builder
bld(ctx
->program
, ctx
->block
);
10083 unsigned enabled_channels
= 0;
10084 bool compr
= false;
10087 for (unsigned i
= 0; i
< 4; ++i
) {
10088 values
[i
] = Operand(v1
);
10091 /* Both stencil and sample mask only need 16-bits. */
10092 if (!ctx
->program
->info
->ps
.writes_z
&&
10093 (ctx
->program
->info
->ps
.writes_stencil
||
10094 ctx
->program
->info
->ps
.writes_sample_mask
)) {
10095 compr
= true; /* COMPR flag */
10097 if (ctx
->program
->info
->ps
.writes_stencil
) {
10098 /* Stencil should be in X[23:16]. */
10099 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10100 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
10101 enabled_channels
|= 0x3;
10104 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10105 /* SampleMask should be in Y[15:0]. */
10106 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10107 enabled_channels
|= 0xc;
10110 if (ctx
->program
->info
->ps
.writes_z
) {
10111 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
10112 enabled_channels
|= 0x1;
10115 if (ctx
->program
->info
->ps
.writes_stencil
) {
10116 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10117 enabled_channels
|= 0x2;
10120 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10121 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10122 enabled_channels
|= 0x4;
10126 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10127 * writemask component.
10129 if (ctx
->options
->chip_class
== GFX6
&&
10130 ctx
->options
->family
!= CHIP_OLAND
&&
10131 ctx
->options
->family
!= CHIP_HAINAN
) {
10132 enabled_channels
|= 0x1;
10135 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10136 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10141 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10143 Builder
bld(ctx
->program
, ctx
->block
);
10144 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10147 for (unsigned i
= 0; i
< 4; ++i
) {
10148 if (write_mask
& (1 << i
)) {
10149 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10151 values
[i
] = Operand(v1
);
10155 unsigned target
, col_format
;
10156 unsigned enabled_channels
= 0;
10157 aco_opcode compr_op
= (aco_opcode
)0;
10159 slot
-= FRAG_RESULT_DATA0
;
10160 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10161 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10163 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10164 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10165 bool is_16bit
= values
[0].regClass() == v2b
;
10167 switch (col_format
)
10169 case V_028714_SPI_SHADER_ZERO
:
10170 enabled_channels
= 0; /* writemask */
10171 target
= V_008DFC_SQ_EXP_NULL
;
10174 case V_028714_SPI_SHADER_32_R
:
10175 enabled_channels
= 1;
10178 case V_028714_SPI_SHADER_32_GR
:
10179 enabled_channels
= 0x3;
10182 case V_028714_SPI_SHADER_32_AR
:
10183 if (ctx
->options
->chip_class
>= GFX10
) {
10184 /* Special case: on GFX10, the outputs are different for 32_AR */
10185 enabled_channels
= 0x3;
10186 values
[1] = values
[3];
10187 values
[3] = Operand(v1
);
10189 enabled_channels
= 0x9;
10193 case V_028714_SPI_SHADER_FP16_ABGR
:
10194 enabled_channels
= 0x5;
10195 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10197 if (ctx
->options
->chip_class
>= GFX9
) {
10198 /* Pack the FP16 values together instead of converting them to
10199 * FP32 and back to FP16.
10200 * TODO: use p_create_vector and let the compiler optimizes.
10202 compr_op
= aco_opcode::v_pack_b32_f16
;
10204 for (unsigned i
= 0; i
< 4; i
++) {
10205 if ((write_mask
>> i
) & 1)
10206 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10212 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10213 enabled_channels
= 0x5;
10214 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10215 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10217 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10221 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10222 enabled_channels
= 0x5;
10223 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10224 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10226 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10230 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10231 enabled_channels
= 0x5;
10232 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10233 if (is_int8
|| is_int10
) {
10235 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10236 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10238 for (unsigned i
= 0; i
< 4; i
++) {
10239 if ((write_mask
>> i
) & 1) {
10240 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10241 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10245 } else if (is_16bit
) {
10246 for (unsigned i
= 0; i
< 4; i
++) {
10247 if ((write_mask
>> i
) & 1) {
10248 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10249 values
[i
] = Operand(tmp
);
10256 case V_028714_SPI_SHADER_SINT16_ABGR
:
10257 enabled_channels
= 0x5;
10258 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10259 if (is_int8
|| is_int10
) {
10261 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10262 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10263 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10264 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10266 for (unsigned i
= 0; i
< 4; i
++) {
10267 if ((write_mask
>> i
) & 1) {
10268 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10269 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10271 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10272 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10276 } else if (is_16bit
) {
10277 for (unsigned i
= 0; i
< 4; i
++) {
10278 if ((write_mask
>> i
) & 1) {
10279 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10280 values
[i
] = Operand(tmp
);
10286 case V_028714_SPI_SHADER_32_ABGR
:
10287 enabled_channels
= 0xF;
10294 if (target
== V_008DFC_SQ_EXP_NULL
)
10297 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10298 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10300 (col_format
== V_028714_SPI_SHADER_32_R
||
10301 col_format
== V_028714_SPI_SHADER_32_GR
||
10302 col_format
== V_028714_SPI_SHADER_32_AR
||
10303 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10304 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10305 for (int i
= 0; i
< 4; i
++) {
10306 if (!(write_mask
& (1 << i
)))
10309 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10310 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10311 bld
.copy(bld
.def(v1
), Operand(3u)));
10312 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10313 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10317 if ((bool) compr_op
) {
10318 for (int i
= 0; i
< 2; i
++) {
10319 /* check if at least one of the values to be compressed is enabled */
10320 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10322 enabled_channels
|= enabled
<< (i
*2);
10323 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10324 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10325 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10327 values
[i
] = Operand(v1
);
10330 values
[2] = Operand(v1
);
10331 values
[3] = Operand(v1
);
10333 for (int i
= 0; i
< 4; i
++)
10334 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10337 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10338 enabled_channels
, target
, (bool) compr_op
);
10342 static void create_fs_exports(isel_context
*ctx
)
10344 bool exported
= false;
10346 /* Export depth, stencil and sample mask. */
10347 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10348 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10349 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10350 exported
|= export_fs_mrt_z(ctx
);
10352 /* Export all color render targets. */
10353 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10354 if (ctx
->outputs
.mask
[i
])
10355 exported
|= export_fs_mrt_color(ctx
, i
);
10358 create_null_export(ctx
);
10361 static void create_workgroup_barrier(Builder
& bld
)
10363 bld
.barrier(aco_opcode::p_barrier
,
10364 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10368 static void write_tcs_tess_factors(isel_context
*ctx
)
10370 unsigned outer_comps
;
10371 unsigned inner_comps
;
10373 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10390 Builder
bld(ctx
->program
, ctx
->block
);
10392 create_workgroup_barrier(bld
);
10394 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10395 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10397 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10398 if_context ic_invocation_id_is_zero
;
10399 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10400 bld
.reset(ctx
->block
);
10402 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10404 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10405 unsigned stride
= inner_comps
+ outer_comps
;
10406 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10410 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10412 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10414 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10415 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10416 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10418 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10419 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10421 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10422 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10423 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10424 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10427 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10428 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10429 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10430 unsigned tf_const_offset
= 0;
10432 if (ctx
->program
->chip_class
<= GFX8
) {
10433 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10434 if_context ic_rel_patch_id_is_zero
;
10435 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10436 bld
.reset(ctx
->block
);
10438 /* Store the dynamic HS control word. */
10439 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10440 bld
.mubuf(aco_opcode::buffer_store_dword
,
10441 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10442 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10443 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10444 tf_const_offset
+= 4;
10446 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10447 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10448 bld
.reset(ctx
->block
);
10451 assert(stride
== 2 || stride
== 4 || stride
== 6);
10452 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10453 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10455 /* Store to offchip for TES to read - only if TES reads them */
10456 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10457 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10458 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10460 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10461 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10463 if (likely(inner_comps
)) {
10464 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10465 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10469 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10470 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10473 static void emit_stream_output(isel_context
*ctx
,
10474 Temp
const *so_buffers
,
10475 Temp
const *so_write_offset
,
10476 const struct radv_stream_output
*output
)
10478 unsigned num_comps
= util_bitcount(output
->component_mask
);
10479 unsigned writemask
= (1 << num_comps
) - 1;
10480 unsigned loc
= output
->location
;
10481 unsigned buf
= output
->buffer
;
10483 assert(num_comps
&& num_comps
<= 4);
10484 if (!num_comps
|| num_comps
> 4)
10487 unsigned start
= ffs(output
->component_mask
) - 1;
10490 bool all_undef
= true;
10491 assert(ctx
->stage
& hw_vs
);
10492 for (unsigned i
= 0; i
< num_comps
; i
++) {
10493 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10494 all_undef
= all_undef
&& !out
[i
].id();
10499 while (writemask
) {
10501 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10502 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10503 /* GFX6 doesn't support storing vec3, split it. */
10504 writemask
|= 1u << (start
+ 2);
10508 unsigned offset
= output
->offset
+ start
* 4;
10510 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10511 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10512 for (int i
= 0; i
< count
; ++i
)
10513 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10514 vec
->definitions
[0] = Definition(write_data
);
10515 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10520 opcode
= aco_opcode::buffer_store_dword
;
10523 opcode
= aco_opcode::buffer_store_dwordx2
;
10526 opcode
= aco_opcode::buffer_store_dwordx3
;
10529 opcode
= aco_opcode::buffer_store_dwordx4
;
10532 unreachable("Unsupported dword count.");
10535 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10536 store
->operands
[0] = Operand(so_buffers
[buf
]);
10537 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10538 store
->operands
[2] = Operand((uint32_t) 0);
10539 store
->operands
[3] = Operand(write_data
);
10540 if (offset
> 4095) {
10541 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10542 Builder
bld(ctx
->program
, ctx
->block
);
10543 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10545 store
->offset
= offset
;
10547 store
->offen
= true;
10549 store
->dlc
= false;
10551 ctx
->block
->instructions
.emplace_back(std::move(store
));
10555 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10557 Builder
bld(ctx
->program
, ctx
->block
);
10559 Temp so_buffers
[4];
10560 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10561 for (unsigned i
= 0; i
< 4; i
++) {
10562 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10566 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10567 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10570 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10571 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10573 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10575 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10578 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10580 bld
.reset(ctx
->block
);
10582 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10584 Temp so_write_offset
[4];
10586 for (unsigned i
= 0; i
< 4; i
++) {
10587 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10592 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10593 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10594 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10595 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10597 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10599 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10600 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10601 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10602 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10606 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10607 struct radv_stream_output
*output
=
10608 &ctx
->program
->info
->so
.outputs
[i
];
10609 if (stream
!= output
->stream
)
10612 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10615 begin_divergent_if_else(ctx
, &ic
);
10616 end_divergent_if(ctx
, &ic
);
10619 } /* end namespace */
10621 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10623 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10624 Builder
bld(ctx
->program
, ctx
->block
);
10625 constexpr unsigned hs_idx
= 1u;
10626 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10627 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10628 Operand((8u << 16) | (hs_idx
* 8u)));
10629 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10631 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10633 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10634 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10635 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10636 ls_has_nonzero_hs_threads
);
10637 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10638 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10639 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10640 ls_has_nonzero_hs_threads
);
10641 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10642 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10643 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10644 ls_has_nonzero_hs_threads
);
10646 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10647 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10648 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10651 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10653 /* Split all arguments except for the first (ring_offsets) and the last
10654 * (exec) so that the dead channels don't stay live throughout the program.
10656 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10657 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10658 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10659 startpgm
->definitions
[i
].regClass().size());
10664 void handle_bc_optimize(isel_context
*ctx
)
10666 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10667 Builder
bld(ctx
->program
, ctx
->block
);
10668 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10669 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10670 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10671 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10672 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10673 if (uses_center
&& uses_centroid
) {
10674 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10675 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10677 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10679 for (unsigned i
= 0; i
< 2; i
++) {
10680 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10681 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10682 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10683 persp_centroid
, persp_center
, sel
);
10685 ctx
->persp_centroid
= bld
.tmp(v2
);
10686 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10687 Operand(new_coord
[0]), Operand(new_coord
[1]));
10688 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10691 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10693 for (unsigned i
= 0; i
< 2; i
++) {
10694 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10695 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10696 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10697 linear_centroid
, linear_center
, sel
);
10699 ctx
->linear_centroid
= bld
.tmp(v2
);
10700 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10701 Operand(new_coord
[0]), Operand(new_coord
[1]));
10702 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10707 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10709 Program
*program
= ctx
->program
;
10711 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10713 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10714 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10715 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10716 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10717 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10719 program
->next_fp_mode
.must_flush_denorms32
=
10720 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10721 program
->next_fp_mode
.must_flush_denorms16_64
=
10722 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10723 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10725 program
->next_fp_mode
.care_about_round32
=
10726 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10728 program
->next_fp_mode
.care_about_round16_64
=
10729 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10730 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10732 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10733 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10734 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10735 program
->next_fp_mode
.denorm16_64
= 0;
10737 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10739 /* preserving fp32 denorms is expensive, so only do it if asked */
10740 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10741 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10743 program
->next_fp_mode
.denorm32
= 0;
10745 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10746 program
->next_fp_mode
.round32
= fp_round_tz
;
10748 program
->next_fp_mode
.round32
= fp_round_ne
;
10750 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10751 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10753 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10755 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10758 void cleanup_cfg(Program
*program
)
10760 /* create linear_succs/logical_succs */
10761 for (Block
& BB
: program
->blocks
) {
10762 for (unsigned idx
: BB
.linear_preds
)
10763 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10764 for (unsigned idx
: BB
.logical_preds
)
10765 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10769 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10771 Builder
bld(ctx
->program
, ctx
->block
);
10773 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10774 Temp count
= i
== 0
10775 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10776 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10777 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10779 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10782 if (ctx
->program
->wave_size
== 64) {
10783 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10784 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10785 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10787 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10788 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10794 bool ngg_early_prim_export(isel_context
*ctx
)
10796 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10800 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10802 Builder
bld(ctx
->program
, ctx
->block
);
10804 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10805 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10807 /* Get the id of the current wave within the threadgroup (workgroup) */
10808 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10809 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10811 /* Execute the following code only on the first wave (wave id 0),
10812 * use the SCC def to tell if the wave id is zero or not.
10814 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10816 begin_uniform_if_then(ctx
, &ic
, cond
);
10817 begin_uniform_if_else(ctx
, &ic
);
10818 bld
.reset(ctx
->block
);
10820 /* Number of vertices output by VS/TES */
10821 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10822 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10823 /* Number of primitives output by VS/TES */
10824 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10825 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10827 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10828 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10829 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10831 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10832 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10834 end_uniform_if(ctx
, &ic
);
10836 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10837 bld
.reset(ctx
->block
);
10838 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10841 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10843 Builder
bld(ctx
->program
, ctx
->block
);
10845 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10846 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10849 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10852 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10853 assert(vtxindex
[i
].id());
10856 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10860 /* The initial edge flag is always false in tess eval shaders. */
10861 if (ctx
->stage
== ngg_vertex_gs
) {
10862 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10863 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10867 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10872 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10874 Builder
bld(ctx
->program
, ctx
->block
);
10875 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10877 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10878 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10879 false /* compressed */, true/* done */, false /* valid mask */);
10882 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10884 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10885 * These must always come before VS exports.
10887 * It is recommended to do these as early as possible. They can be at the beginning when
10888 * there is no SW GS and the shader doesn't write edge flags.
10892 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10893 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10895 Builder
bld(ctx
->program
, ctx
->block
);
10896 constexpr unsigned max_vertices_per_primitive
= 3;
10897 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10899 if (ctx
->stage
== ngg_vertex_gs
) {
10900 /* TODO: optimize for points & lines */
10901 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10902 if (ctx
->shader
->info
.tess
.point_mode
)
10903 num_vertices_per_primitive
= 1;
10904 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10905 num_vertices_per_primitive
= 2;
10907 unreachable("Unsupported NGG shader stage");
10910 Temp vtxindex
[max_vertices_per_primitive
];
10911 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10912 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10913 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10914 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10915 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10916 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10917 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10918 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10920 /* Export primitive data to the index buffer. */
10921 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10923 /* Export primitive ID. */
10924 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10925 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10926 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10927 Temp provoking_vtx_index
= vtxindex
[0];
10928 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10930 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10933 begin_divergent_if_else(ctx
, &ic
);
10934 end_divergent_if(ctx
, &ic
);
10937 void ngg_emit_nogs_output(isel_context
*ctx
)
10939 /* Emits NGG GS output, for stages that don't have SW GS. */
10942 Builder
bld(ctx
->program
, ctx
->block
);
10943 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10945 /* NGG streamout is currently disabled by default. */
10946 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10948 if (late_prim_export
) {
10949 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10950 create_export_phis(ctx
);
10951 /* Do what we need to do in the GS threads. */
10952 ngg_emit_nogs_gsthreads(ctx
);
10954 /* What comes next should be executed on ES threads. */
10955 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10956 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10957 bld
.reset(ctx
->block
);
10960 /* Export VS outputs */
10961 ctx
->block
->kind
|= block_kind_export_end
;
10962 create_vs_exports(ctx
);
10964 /* Export primitive ID */
10965 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10968 if (ctx
->stage
== ngg_vertex_gs
) {
10969 /* Wait for GS threads to store primitive ID in LDS. */
10970 create_workgroup_barrier(bld
);
10972 /* Calculate LDS address where the GS threads stored the primitive ID. */
10973 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10974 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10975 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10976 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10977 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10978 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10980 /* Load primitive ID from LDS. */
10981 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10982 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10983 /* TES: Just use the patch ID as the primitive ID. */
10984 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10986 unreachable("unsupported NGG shader stage.");
10989 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10990 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10992 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10995 if (late_prim_export
) {
10996 begin_divergent_if_else(ctx
, &ic
);
10997 end_divergent_if(ctx
, &ic
);
10998 bld
.reset(ctx
->block
);
11002 void select_program(Program
*program
,
11003 unsigned shader_count
,
11004 struct nir_shader
*const *shaders
,
11005 ac_shader_config
* config
,
11006 struct radv_shader_args
*args
)
11008 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
11009 if_context ic_merged_wave_info
;
11010 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
11012 for (unsigned i
= 0; i
< shader_count
; i
++) {
11013 nir_shader
*nir
= shaders
[i
];
11014 init_context(&ctx
, nir
);
11016 setup_fp_mode(&ctx
, nir
);
11019 /* needs to be after init_context() for FS */
11020 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
11021 append_logical_start(ctx
.block
);
11023 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
11024 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
11026 split_arguments(&ctx
, startpgm
);
11030 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
11032 if (ngg_early_prim_export(&ctx
))
11033 ngg_emit_nogs_gsthreads(&ctx
);
11036 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
11037 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
11038 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
11039 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
11040 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
11041 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
11042 ctx
.stage
== tess_eval_geometry_gs
));
11044 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
11045 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
11046 if (check_merged_wave_info
) {
11047 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
11048 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
11052 Builder
bld(ctx
.program
, ctx
.block
);
11054 create_workgroup_barrier(bld
);
11056 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
11057 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
11059 } else if (ctx
.stage
== geometry_gs
)
11060 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
11062 if (ctx
.stage
== fragment_fs
)
11063 handle_bc_optimize(&ctx
);
11065 visit_cf_list(&ctx
, &func
->body
);
11067 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
11068 emit_streamout(&ctx
, 0);
11070 if (ctx
.stage
& hw_vs
) {
11071 create_vs_exports(&ctx
);
11072 ctx
.block
->kind
|= block_kind_export_end
;
11073 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
11074 ngg_emit_nogs_output(&ctx
);
11075 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
11076 Builder
bld(ctx
.program
, ctx
.block
);
11077 bld
.barrier(aco_opcode::p_barrier
,
11078 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
11079 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
11080 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
11081 write_tcs_tess_factors(&ctx
);
11084 if (ctx
.stage
== fragment_fs
) {
11085 create_fs_exports(&ctx
);
11086 ctx
.block
->kind
|= block_kind_export_end
;
11089 if (endif_merged_wave_info
) {
11090 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
11091 end_divergent_if(&ctx
, &ic_merged_wave_info
);
11094 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
11095 ngg_emit_nogs_output(&ctx
);
11097 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
11098 /* Outputs of the previous stage are inputs to the next stage */
11099 ctx
.inputs
= ctx
.outputs
;
11100 ctx
.outputs
= shader_io_state();
11104 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11106 append_logical_end(ctx
.block
);
11107 ctx
.block
->kind
|= block_kind_uniform
;
11108 Builder
bld(ctx
.program
, ctx
.block
);
11109 if (ctx
.program
->wb_smem_l1_on_end
)
11110 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
11111 bld
.sopp(aco_opcode::s_endpgm
);
11113 cleanup_cfg(program
);
11116 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
11117 ac_shader_config
* config
,
11118 struct radv_shader_args
*args
)
11120 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
11122 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11124 add_startpgm(&ctx
);
11125 append_logical_start(ctx
.block
);
11127 Builder
bld(ctx
.program
, ctx
.block
);
11129 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11131 Operand
stream_id(0u);
11132 if (args
->shader_info
->so
.num_outputs
)
11133 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11134 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11136 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11138 std::stack
<Block
> endif_blocks
;
11140 for (unsigned stream
= 0; stream
< 4; stream
++) {
11141 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11144 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11145 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11148 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11150 unsigned BB_if_idx
= ctx
.block
->index
;
11151 Block BB_endif
= Block();
11152 if (!stream_id
.isConstant()) {
11154 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11155 append_logical_end(ctx
.block
);
11156 ctx
.block
->kind
|= block_kind_uniform
;
11157 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11159 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11161 ctx
.block
= ctx
.program
->create_and_insert_block();
11162 add_edge(BB_if_idx
, ctx
.block
);
11163 bld
.reset(ctx
.block
);
11164 append_logical_start(ctx
.block
);
11167 unsigned offset
= 0;
11168 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11169 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11172 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11173 unsigned length
= util_last_bit(output_usage_mask
);
11174 for (unsigned j
= 0; j
< length
; ++j
) {
11175 if (!(output_usage_mask
& (1 << j
)))
11178 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11179 Temp voffset
= vtx_offset
;
11180 if (const_offset
>= 4096u) {
11181 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11182 const_offset
%= 4096u;
11185 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11186 mubuf
->definitions
[0] = bld
.def(v1
);
11187 mubuf
->operands
[0] = Operand(gsvs_ring
);
11188 mubuf
->operands
[1] = Operand(voffset
);
11189 mubuf
->operands
[2] = Operand(0u);
11190 mubuf
->offen
= true;
11191 mubuf
->offset
= const_offset
;
11194 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11196 ctx
.outputs
.mask
[i
] |= 1 << j
;
11197 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11199 bld
.insert(std::move(mubuf
));
11205 if (args
->shader_info
->so
.num_outputs
) {
11206 emit_streamout(&ctx
, stream
);
11207 bld
.reset(ctx
.block
);
11211 create_vs_exports(&ctx
);
11212 ctx
.block
->kind
|= block_kind_export_end
;
11215 if (!stream_id
.isConstant()) {
11216 append_logical_end(ctx
.block
);
11218 /* branch from then block to endif block */
11219 bld
.branch(aco_opcode::p_branch
);
11220 add_edge(ctx
.block
->index
, &BB_endif
);
11221 ctx
.block
->kind
|= block_kind_uniform
;
11223 /* emit else block */
11224 ctx
.block
= ctx
.program
->create_and_insert_block();
11225 add_edge(BB_if_idx
, ctx
.block
);
11226 bld
.reset(ctx
.block
);
11227 append_logical_start(ctx
.block
);
11229 endif_blocks
.push(std::move(BB_endif
));
11233 while (!endif_blocks
.empty()) {
11234 Block BB_endif
= std::move(endif_blocks
.top());
11235 endif_blocks
.pop();
11237 Block
*BB_else
= ctx
.block
;
11239 append_logical_end(BB_else
);
11240 /* branch from else block to endif block */
11241 bld
.branch(aco_opcode::p_branch
);
11242 add_edge(BB_else
->index
, &BB_endif
);
11243 BB_else
->kind
|= block_kind_uniform
;
11245 /** emit endif merge block */
11246 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11247 bld
.reset(ctx
.block
);
11248 append_logical_start(ctx
.block
);
11251 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11253 append_logical_end(ctx
.block
);
11254 ctx
.block
->kind
|= block_kind_uniform
;
11255 bld
.sopp(aco_opcode::s_endpgm
);
11257 cleanup_cfg(program
);