2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 #define isel_err(...) _isel_err(ctx, __FILE__, __LINE__, __VA_ARGS__)
43 static void _isel_err(isel_context
*ctx
, const char *file
, unsigned line
,
44 const nir_instr
*instr
, const char *msg
)
48 FILE *memf
= open_memstream(&out
, &outsize
);
50 fprintf(memf
, "%s: ", msg
);
51 nir_print_instr(instr
, memf
);
54 _aco_err(ctx
->program
, file
, line
, out
);
58 class loop_info_RAII
{
60 unsigned header_idx_old
;
62 bool divergent_cont_old
;
63 bool divergent_branch_old
;
64 bool divergent_if_old
;
67 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
69 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
70 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
71 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
72 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
75 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
76 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
77 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
78 ctx
->cf_info
.parent_if
.is_divergent
= false;
79 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
84 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
85 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
86 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
87 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
88 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
89 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
90 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
91 ctx
->cf_info
.exec_potentially_empty_discard
= false;
99 bool exec_potentially_empty_discard_old
;
100 bool exec_potentially_empty_break_old
;
101 uint16_t exec_potentially_empty_break_depth_old
;
105 bool uniform_has_then_branch
;
106 bool then_branch_divergent
;
111 static bool visit_cf_list(struct isel_context
*ctx
,
112 struct exec_list
*list
);
114 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
116 succ
->logical_preds
.emplace_back(pred_idx
);
120 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
122 succ
->linear_preds
.emplace_back(pred_idx
);
125 static void add_edge(unsigned pred_idx
, Block
*succ
)
127 add_logical_edge(pred_idx
, succ
);
128 add_linear_edge(pred_idx
, succ
);
131 static void append_logical_start(Block
*b
)
133 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
136 static void append_logical_end(Block
*b
)
138 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
141 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
143 assert(ctx
->allocated
[def
->index
].id());
144 return ctx
->allocated
[def
->index
];
147 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
148 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
150 Builder
bld(ctx
->program
, ctx
->block
);
151 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
152 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
154 if (ctx
->program
->wave_size
== 32) {
156 } else if (ctx
->program
->chip_class
<= GFX7
) {
157 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
160 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
165 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
167 Builder
bld(ctx
->program
, ctx
->block
);
170 dst
= bld
.tmp(src
.regClass());
172 assert(src
.size() == dst
.size());
174 if (ctx
->stage
!= fragment_fs
) {
178 bld
.copy(Definition(dst
), src
);
182 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
183 ctx
->program
->needs_wqm
|= program_needs_wqm
;
187 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
189 if (index
.regClass() == s1
)
190 return bld
.readlane(bld
.def(s1
), data
, index
);
192 if (ctx
->options
->chip_class
<= GFX7
) {
193 /* GFX6-7: there is no bpermute instruction */
194 Operand
index_op(index
);
195 Operand
input_data(data
);
196 index_op
.setLateKill(true);
197 input_data
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
200 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
201 /* GFX10 wave64 mode: emulate full-wave bpermute */
202 if (!ctx
->has_gfx10_wave64_bpermute
) {
203 ctx
->has_gfx10_wave64_bpermute
= true;
204 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
205 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
208 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
209 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
210 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
211 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
212 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
213 Operand
input_data(data
);
215 index_x4
.setLateKill(true);
216 input_data
.setLateKill(true);
217 same_half
.setLateKill(true);
219 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
221 /* GFX8-9 or GFX10 wave32: bpermute works normally */
222 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
223 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
227 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
229 if (ctx
->options
->chip_class
>= GFX8
) {
230 unsigned and_mask
= mask
& 0x1f;
231 unsigned or_mask
= (mask
>> 5) & 0x1f;
232 unsigned xor_mask
= (mask
>> 10) & 0x1f;
234 uint16_t dpp_ctrl
= 0xffff;
236 // TODO: we could use DPP8 for some swizzles
237 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
238 unsigned res
[4] = {0, 1, 2, 3};
239 for (unsigned i
= 0; i
< 4; i
++)
240 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
241 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
242 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
243 dpp_ctrl
= dpp_row_rr(8);
244 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
245 dpp_ctrl
= dpp_row_mirror
;
246 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
247 dpp_ctrl
= dpp_row_half_mirror
;
250 if (dpp_ctrl
!= 0xffff)
251 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
254 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
257 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
259 if (val
.type() == RegType::sgpr
) {
260 Builder
bld(ctx
->program
, ctx
->block
);
261 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
263 assert(val
.type() == RegType::vgpr
);
267 //assumes a != 0xffffffff
268 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
271 Builder
bld(ctx
->program
, ctx
->block
);
273 if (util_is_power_of_two_or_zero(b
)) {
274 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
278 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
280 assert(info
.multiplier
<= 0xffffffff);
282 bool pre_shift
= info
.pre_shift
!= 0;
283 bool increment
= info
.increment
!= 0;
284 bool multiply
= true;
285 bool post_shift
= info
.post_shift
!= 0;
287 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
288 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
292 Temp pre_shift_dst
= a
;
294 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
298 Temp increment_dst
= pre_shift_dst
;
300 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
301 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
304 Temp multiply_dst
= increment_dst
;
306 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
307 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
308 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
312 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
316 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
318 Builder
bld(ctx
->program
, ctx
->block
);
319 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
323 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
325 /* no need to extract the whole vector */
326 if (src
.regClass() == dst_rc
) {
331 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
332 Builder
bld(ctx
->program
, ctx
->block
);
333 auto it
= ctx
->allocated_vec
.find(src
.id());
334 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
335 if (it
->second
[idx
].regClass() == dst_rc
) {
336 return it
->second
[idx
];
338 assert(!dst_rc
.is_subdword());
339 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
340 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
344 if (dst_rc
.is_subdword())
345 src
= as_vgpr(ctx
, src
);
347 if (src
.bytes() == dst_rc
.bytes()) {
349 return bld
.copy(bld
.def(dst_rc
), src
);
351 Temp dst
= bld
.tmp(dst_rc
);
352 emit_extract_vector(ctx
, src
, idx
, dst
);
357 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
359 if (num_components
== 1)
361 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
364 if (num_components
> vec_src
.size()) {
365 if (vec_src
.type() == RegType::sgpr
) {
366 /* should still help get_alu_src() */
367 emit_split_vector(ctx
, vec_src
, vec_src
.size());
370 /* sub-dword split */
371 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
373 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
375 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
376 split
->operands
[0] = Operand(vec_src
);
377 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
378 for (unsigned i
= 0; i
< num_components
; i
++) {
379 elems
[i
] = {ctx
->program
->allocateId(), rc
};
380 split
->definitions
[i
] = Definition(elems
[i
]);
382 ctx
->block
->instructions
.emplace_back(std::move(split
));
383 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
386 /* This vector expansion uses a mask to determine which elements in the new vector
387 * come from the original vector. The other elements are undefined. */
388 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
390 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
395 Builder
bld(ctx
->program
, ctx
->block
);
396 if (num_components
== 1) {
397 if (dst
.type() == RegType::sgpr
)
398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
400 bld
.copy(Definition(dst
), vec_src
);
404 unsigned component_size
= dst
.size() / num_components
;
405 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
407 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
408 vec
->definitions
[0] = Definition(dst
);
410 for (unsigned i
= 0; i
< num_components
; i
++) {
411 if (mask
& (1 << i
)) {
412 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
413 if (dst
.type() == RegType::sgpr
)
414 src
= bld
.as_uniform(src
);
415 vec
->operands
[i
] = Operand(src
);
417 vec
->operands
[i
] = Operand(0u);
419 elems
[i
] = vec
->operands
[i
].getTemp();
421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
422 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
425 /* adjust misaligned small bit size loads */
426 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
428 Builder
bld(ctx
->program
, ctx
->block
);
430 Temp select
= Temp();
431 if (offset
.isConstant()) {
432 assert(offset
.constantValue() && offset
.constantValue() < 4);
433 shift
= Operand(offset
.constantValue() * 8);
435 /* bit_offset = 8 * (offset & 0x3) */
436 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
437 select
= bld
.tmp(s1
);
438 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
441 if (vec
.size() == 1) {
442 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
443 } else if (vec
.size() == 2) {
444 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
445 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
447 emit_split_vector(ctx
, dst
, 2);
449 emit_extract_vector(ctx
, tmp
, 0, dst
);
450 } else if (vec
.size() == 4) {
451 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
453 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
454 if (select
!= Temp())
455 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
456 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
457 Temp mid
= bld
.tmp(s1
);
458 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
459 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
460 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
461 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
462 emit_split_vector(ctx
, dst
, 2);
466 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
468 Builder
bld(ctx
->program
, ctx
->block
);
469 if (offset
.isTemp()) {
470 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
472 if (vec
.size() == 4) {
473 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
474 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
475 } else if (vec
.size() == 3) {
476 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
477 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
478 } else if (vec
.size() == 2) {
479 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
480 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
482 for (unsigned i
= 0; i
< dst
.size(); i
++)
483 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
487 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
489 offset
= Operand(0u);
492 unsigned num_components
= vec
.bytes() / component_size
;
493 if (vec
.regClass() == dst
.regClass()) {
494 assert(offset
.constantValue() == 0);
495 bld
.copy(Definition(dst
), vec
);
496 emit_split_vector(ctx
, dst
, num_components
);
500 emit_split_vector(ctx
, vec
, num_components
);
501 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
502 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
504 assert(offset
.constantValue() % component_size
== 0);
505 unsigned skip
= offset
.constantValue() / component_size
;
506 for (unsigned i
= skip
; i
< num_components
; i
++)
507 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
509 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
510 if (dst
.type() == RegType::vgpr
) {
511 num_components
= dst
.bytes() / component_size
;
512 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
513 for (unsigned i
= 0; i
< num_components
; i
++)
514 create_vec
->operands
[i
] = Operand(elems
[i
]);
515 create_vec
->definitions
[0] = Definition(dst
);
516 bld
.insert(std::move(create_vec
));
518 /* if dst is sgpr - split the src, but move the original to sgpr. */
520 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
521 byte_align_scalar(ctx
, vec
, offset
, dst
);
523 assert(dst
.size() == vec
.size());
524 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
527 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
530 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
532 Builder
bld(ctx
->program
, ctx
->block
);
534 dst
= bld
.tmp(bld
.lm
);
536 assert(val
.regClass() == s1
);
537 assert(dst
.regClass() == bld
.lm
);
539 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
542 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
544 Builder
bld(ctx
->program
, ctx
->block
);
548 assert(val
.regClass() == bld
.lm
);
549 assert(dst
.regClass() == s1
);
551 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
552 Temp tmp
= bld
.tmp(s1
);
553 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
554 return emit_wqm(ctx
, tmp
, dst
);
557 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
560 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
561 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
563 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
566 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
567 return bld
.copy(Definition(dst
), src
);
568 else if (dst
.bytes() < src
.bytes())
569 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
573 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
576 } else if (src
.regClass() == s1
) {
578 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
580 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
581 } else if (ctx
->options
->chip_class
>= GFX8
) {
582 assert(src_bits
!= 8 || src
.regClass() == v1b
);
583 assert(src_bits
!= 16 || src
.regClass() == v2b
);
584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
585 sdwa
->operands
[0] = Operand(src
);
586 sdwa
->definitions
[0] = Definition(tmp
);
588 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
590 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
591 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
592 bld
.insert(std::move(sdwa
));
594 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
595 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
596 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
599 if (dst_bits
== 64) {
600 if (is_signed
&& dst
.regClass() == s2
) {
601 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
602 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
603 } else if (is_signed
&& dst
.regClass() == v2
) {
604 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
607 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
614 enum sgpr_extract_mode
{
620 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
622 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
623 unsigned src_size
= src
->src
.ssa
->bit_size
;
624 unsigned swizzle
= src
->swizzle
[0];
626 if (vec
.size() > 1) {
627 assert(src_size
== 16);
628 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
629 swizzle
= swizzle
& 1;
632 Builder
bld(ctx
->program
, ctx
->block
);
633 unsigned offset
= src_size
* swizzle
;
634 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
636 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
637 bld
.copy(Definition(tmp
), vec
);
638 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
639 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
640 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
641 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
642 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
643 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
645 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
646 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
649 if (dst
.regClass() == s2
)
650 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
655 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
657 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
658 return get_ssa_temp(ctx
, src
.src
.ssa
);
660 if (src
.src
.ssa
->num_components
== size
) {
661 bool identity_swizzle
= true;
662 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
663 if (src
.swizzle
[i
] != i
)
664 identity_swizzle
= false;
666 if (identity_swizzle
)
667 return get_ssa_temp(ctx
, src
.src
.ssa
);
670 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
671 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
672 assert(elem_size
> 0);
673 assert(vec
.bytes() % elem_size
== 0);
675 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
676 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
678 return extract_8_16_bit_sgpr_element(
679 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
682 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
684 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
687 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
688 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
689 for (unsigned i
= 0; i
< size
; ++i
) {
690 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
691 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
693 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
694 vec_instr
->definitions
[0] = Definition(dst
);
695 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
696 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
701 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
705 Builder
bld(ctx
->program
, ctx
->block
);
706 if (ptr
.type() == RegType::vgpr
)
707 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
708 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
709 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
712 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
714 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
715 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
716 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
717 sop2
->definitions
[0] = Definition(dst
);
718 if (instr
->no_unsigned_wrap
)
719 sop2
->definitions
[0].setNUW(true);
721 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
722 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
725 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
726 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
728 Builder
bld(ctx
->program
, ctx
->block
);
729 bld
.is_precise
= instr
->exact
;
731 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
733 if (src1
.type() == RegType::sgpr
) {
734 if (commutative
&& src0
.type() == RegType::vgpr
) {
739 src1
= as_vgpr(ctx
, src1
);
743 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
744 assert(dst
.size() == 1);
745 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
746 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
748 bld
.vop2(op
, Definition(dst
), src0
, src1
);
752 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
753 aco_opcode op
, Temp dst
)
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.is_precise
= instr
->exact
;
758 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
759 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
761 if (src1
.type() == RegType::sgpr
) {
762 assert(src0
.type() == RegType::vgpr
);
763 std::swap(src0
, src1
);
766 Temp src00
= bld
.tmp(src0
.type(), 1);
767 Temp src01
= bld
.tmp(src0
.type(), 1);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
769 Temp src10
= bld
.tmp(v1
);
770 Temp src11
= bld
.tmp(v1
);
771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
772 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
773 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
777 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
778 bool flush_denorms
= false)
780 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
781 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
782 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
784 /* ensure that the instruction has at most 1 sgpr operand
785 * The optimizer will inline constants for us */
786 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
787 src0
= as_vgpr(ctx
, src0
);
788 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
789 src1
= as_vgpr(ctx
, src1
);
790 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
791 src2
= as_vgpr(ctx
, src2
);
793 Builder
bld(ctx
->program
, ctx
->block
);
794 bld
.is_precise
= instr
->exact
;
795 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
796 assert(dst
.size() == 1);
797 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
798 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
800 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
804 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
806 Builder
bld(ctx
->program
, ctx
->block
);
807 bld
.is_precise
= instr
->exact
;
808 if (dst
.type() == RegType::sgpr
)
809 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
810 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
812 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
815 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
817 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
818 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
819 assert(src0
.size() == src1
.size());
821 aco_ptr
<Instruction
> vopc
;
822 if (src1
.type() == RegType::sgpr
) {
823 if (src0
.type() == RegType::vgpr
) {
824 /* to swap the operands, we might also have to change the opcode */
826 case aco_opcode::v_cmp_lt_f16
:
827 op
= aco_opcode::v_cmp_gt_f16
;
829 case aco_opcode::v_cmp_ge_f16
:
830 op
= aco_opcode::v_cmp_le_f16
;
832 case aco_opcode::v_cmp_lt_i16
:
833 op
= aco_opcode::v_cmp_gt_i16
;
835 case aco_opcode::v_cmp_ge_i16
:
836 op
= aco_opcode::v_cmp_le_i16
;
838 case aco_opcode::v_cmp_lt_u16
:
839 op
= aco_opcode::v_cmp_gt_u16
;
841 case aco_opcode::v_cmp_ge_u16
:
842 op
= aco_opcode::v_cmp_le_u16
;
844 case aco_opcode::v_cmp_lt_f32
:
845 op
= aco_opcode::v_cmp_gt_f32
;
847 case aco_opcode::v_cmp_ge_f32
:
848 op
= aco_opcode::v_cmp_le_f32
;
850 case aco_opcode::v_cmp_lt_i32
:
851 op
= aco_opcode::v_cmp_gt_i32
;
853 case aco_opcode::v_cmp_ge_i32
:
854 op
= aco_opcode::v_cmp_le_i32
;
856 case aco_opcode::v_cmp_lt_u32
:
857 op
= aco_opcode::v_cmp_gt_u32
;
859 case aco_opcode::v_cmp_ge_u32
:
860 op
= aco_opcode::v_cmp_le_u32
;
862 case aco_opcode::v_cmp_lt_f64
:
863 op
= aco_opcode::v_cmp_gt_f64
;
865 case aco_opcode::v_cmp_ge_f64
:
866 op
= aco_opcode::v_cmp_le_f64
;
868 case aco_opcode::v_cmp_lt_i64
:
869 op
= aco_opcode::v_cmp_gt_i64
;
871 case aco_opcode::v_cmp_ge_i64
:
872 op
= aco_opcode::v_cmp_le_i64
;
874 case aco_opcode::v_cmp_lt_u64
:
875 op
= aco_opcode::v_cmp_gt_u64
;
877 case aco_opcode::v_cmp_ge_u64
:
878 op
= aco_opcode::v_cmp_le_u64
;
880 default: /* eq and ne are commutative */
887 src1
= as_vgpr(ctx
, src1
);
891 Builder
bld(ctx
->program
, ctx
->block
);
892 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
895 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
897 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
898 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
899 Builder
bld(ctx
->program
, ctx
->block
);
901 assert(dst
.regClass() == bld
.lm
);
902 assert(src0
.type() == RegType::sgpr
);
903 assert(src1
.type() == RegType::sgpr
);
904 assert(src0
.regClass() == src1
.regClass());
906 /* Emit the SALU comparison instruction */
907 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
908 /* Turn the result into a per-lane bool */
909 bool_to_vector_condition(ctx
, cmp
, dst
);
912 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
913 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
915 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
916 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
917 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
918 nir_dest_is_divergent(instr
->dest
.dest
) ||
919 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
920 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
921 aco_opcode op
= use_valu
? v_op
: s_op
;
922 assert(op
!= aco_opcode::num_opcodes
);
923 assert(dst
.regClass() == ctx
->program
->lane_mask
);
926 emit_vopc_instruction(ctx
, instr
, op
, dst
);
928 emit_sopc_instruction(ctx
, instr
, op
, dst
);
931 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
933 Builder
bld(ctx
->program
, ctx
->block
);
934 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
935 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
937 assert(dst
.regClass() == bld
.lm
);
938 assert(src0
.regClass() == bld
.lm
);
939 assert(src1
.regClass() == bld
.lm
);
941 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
944 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
946 Builder
bld(ctx
->program
, ctx
->block
);
947 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
948 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
949 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
951 assert(cond
.regClass() == bld
.lm
);
953 if (dst
.type() == RegType::vgpr
) {
954 aco_ptr
<Instruction
> bcsel
;
955 if (dst
.size() == 1) {
956 then
= as_vgpr(ctx
, then
);
957 els
= as_vgpr(ctx
, els
);
959 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
960 } else if (dst
.size() == 2) {
961 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
963 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
966 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
967 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
971 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
976 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
977 assert(dst
.regClass() == bld
.lm
);
978 assert(then
.regClass() == bld
.lm
);
979 assert(els
.regClass() == bld
.lm
);
982 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
983 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
984 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
985 assert(dst
.size() == then
.size());
986 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
987 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
989 isel_err(&instr
->instr
, "Unimplemented uniform bcsel bit size");
994 /* divergent boolean bcsel
995 * this implements bcsel on bools: dst = s0 ? s1 : s2
996 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
997 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
999 if (cond
.id() != then
.id())
1000 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
1002 if (cond
.id() == els
.id())
1003 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
1005 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
1006 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
1009 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
1010 aco_opcode op
, uint32_t undo
)
1012 /* multiply by 16777216 to handle denormals */
1013 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1014 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1015 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1016 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1017 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1019 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1021 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1024 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1026 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1027 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1031 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1034 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1036 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1037 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1041 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1044 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1046 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1047 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1051 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1054 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1056 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1057 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1061 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1064 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1066 if (ctx
->options
->chip_class
>= GFX7
)
1067 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1069 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1070 /* TODO: create more efficient code! */
1071 if (val
.type() == RegType::sgpr
)
1072 val
= as_vgpr(ctx
, val
);
1074 /* Split the input value. */
1075 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1078 /* Extract the exponent and compute the unbiased value. */
1079 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1080 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1082 /* Extract the fractional part. */
1083 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1084 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1086 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1089 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1090 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1091 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1092 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1093 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1095 /* Get the sign bit. */
1096 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1098 /* Decide the operation to apply depending on the unbiased exponent. */
1099 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1100 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1101 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1102 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1103 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1104 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1106 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1109 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1111 if (ctx
->options
->chip_class
>= GFX7
)
1112 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1114 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1115 * lowered at NIR level for precision reasons). */
1116 Temp src0
= as_vgpr(ctx
, val
);
1118 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1119 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1121 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1122 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1123 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1125 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1127 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1128 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1130 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1131 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1133 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1135 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1136 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1138 return add
->definitions
[0].getTemp();
1141 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1143 if (!instr
->dest
.dest
.is_ssa
) {
1144 isel_err(&instr
->instr
, "nir alu dst not in ssa");
1147 Builder
bld(ctx
->program
, ctx
->block
);
1148 bld
.is_precise
= instr
->exact
;
1149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1154 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1155 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1156 for (unsigned i
= 0; i
< num
; ++i
)
1157 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1159 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1160 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1161 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1162 for (unsigned i
= 0; i
< num
; ++i
) {
1163 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1164 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1166 vec
->operands
[i
] = Operand
{elems
[i
]};
1168 vec
->definitions
[0] = Definition(dst
);
1169 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1170 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1172 // TODO: that is a bit suboptimal..
1173 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1174 for (unsigned i
= 0; i
< num
- 1; ++i
)
1175 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1176 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1177 for (unsigned i
= 0; i
< num
; ++i
) {
1178 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1179 if (bit
% 32 == 0) {
1180 elems
[bit
/ 32] = elems
[i
];
1182 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1183 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1184 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1187 if (dst
.size() == 1)
1188 bld
.copy(Definition(dst
), elems
[0]);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1195 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1196 aco_ptr
<Instruction
> mov
;
1197 if (dst
.type() == RegType::sgpr
) {
1198 if (src
.type() == RegType::vgpr
)
1199 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1200 else if (src
.regClass() == s1
)
1201 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1202 else if (src
.regClass() == s2
)
1203 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1205 unreachable("wrong src register class for nir_op_imov");
1207 if (dst
.regClass() == v1
)
1208 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1209 else if (dst
.regClass() == v1b
||
1210 dst
.regClass() == v2b
||
1211 dst
.regClass() == v2
)
1212 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1214 unreachable("wrong src register class for nir_op_imov");
1219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1220 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1221 assert(src
.regClass() == bld
.lm
);
1222 assert(dst
.regClass() == bld
.lm
);
1223 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1224 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1225 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1226 } else if (dst
.regClass() == v1
) {
1227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1228 } else if (dst
.regClass() == v2
) {
1229 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1230 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1231 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1232 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1234 } else if (dst
.type() == RegType::sgpr
) {
1235 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1236 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1238 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1243 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1244 if (dst
.regClass() == v1
) {
1245 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1246 } else if (dst
.regClass() == s1
) {
1247 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1248 } else if (dst
.size() == 2) {
1249 Temp src0
= bld
.tmp(dst
.type(), 1);
1250 Temp src1
= bld
.tmp(dst
.type(), 1);
1251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1253 if (dst
.regClass() == s2
) {
1254 Temp carry
= bld
.tmp(s1
);
1255 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1256 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1257 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1259 Temp lower
= bld
.tmp(v1
);
1260 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1261 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1265 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1270 if (dst
.regClass() == s1
) {
1271 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1272 } else if (dst
.regClass() == v1
) {
1273 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1274 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1276 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1280 case nir_op_isign
: {
1281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1282 if (dst
.regClass() == s1
) {
1283 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1284 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1285 } else if (dst
.regClass() == s2
) {
1286 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1288 if (ctx
->program
->chip_class
>= GFX8
)
1289 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1291 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1292 /* SCC gets zero-extended to 64 bit */
1293 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1294 } else if (dst
.regClass() == v1
) {
1295 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1296 } else if (dst
.regClass() == v2
) {
1297 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1298 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1299 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1300 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1301 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1304 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1309 if (dst
.regClass() == v1
) {
1310 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1311 } else if (dst
.regClass() == s1
) {
1312 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1314 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1319 if (dst
.regClass() == v1
) {
1320 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1321 } else if (dst
.regClass() == s1
) {
1322 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1324 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1329 if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1331 } else if (dst
.regClass() == s1
) {
1332 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1334 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1339 if (dst
.regClass() == v1
) {
1340 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1341 } else if (dst
.regClass() == s1
) {
1342 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1344 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1349 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1350 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1351 } else if (dst
.regClass() == v1
) {
1352 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1353 } else if (dst
.regClass() == v2
) {
1354 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1360 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1365 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1366 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1367 } else if (dst
.regClass() == v1
) {
1368 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1369 } else if (dst
.regClass() == v2
) {
1370 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1371 } else if (dst
.regClass() == s1
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1373 } else if (dst
.regClass() == s2
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1376 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1381 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1382 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1383 } else if (dst
.regClass() == v1
) {
1384 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1385 } else if (dst
.regClass() == v2
) {
1386 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1387 } else if (dst
.regClass() == s1
) {
1388 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1392 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1397 if (dst
.regClass() == v1
) {
1398 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1399 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1400 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1401 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1402 } else if (dst
.regClass() == v2
) {
1403 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1404 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1405 } else if (dst
.regClass() == s2
) {
1406 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1407 } else if (dst
.regClass() == s1
) {
1408 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1410 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1415 if (dst
.regClass() == v1
) {
1416 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1417 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1418 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1419 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1420 } else if (dst
.regClass() == v2
) {
1421 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1423 } else if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1425 } else if (dst
.regClass() == s2
) {
1426 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1428 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1433 if (dst
.regClass() == v1
) {
1434 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1435 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1436 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1437 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1438 } else if (dst
.regClass() == v2
) {
1439 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1440 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1441 } else if (dst
.regClass() == s1
) {
1442 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1443 } else if (dst
.regClass() == s2
) {
1444 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1446 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1450 case nir_op_find_lsb
: {
1451 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1452 if (src
.regClass() == s1
) {
1453 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1454 } else if (src
.regClass() == v1
) {
1455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1456 } else if (src
.regClass() == s2
) {
1457 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1459 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1463 case nir_op_ufind_msb
:
1464 case nir_op_ifind_msb
: {
1465 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1466 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1467 aco_opcode op
= src
.regClass() == s2
?
1468 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1469 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1470 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1472 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1473 Operand(src
.size() * 32u - 1u), msb_rev
);
1474 Temp msb
= sub
.def(0).getTemp();
1475 Temp carry
= sub
.def(1).getTemp();
1477 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1478 } else if (src
.regClass() == v1
) {
1479 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1480 Temp msb_rev
= bld
.tmp(v1
);
1481 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1482 Temp msb
= bld
.tmp(v1
);
1483 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1484 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1486 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1490 case nir_op_bitfield_reverse
: {
1491 if (dst
.regClass() == s1
) {
1492 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1493 } else if (dst
.regClass() == v1
) {
1494 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1496 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1501 if (dst
.regClass() == s1
) {
1502 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1506 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1507 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1508 if (dst
.regClass() == v1
) {
1509 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1513 assert(src0
.size() == 2 && src1
.size() == 2);
1514 Temp src00
= bld
.tmp(src0
.type(), 1);
1515 Temp src01
= bld
.tmp(dst
.type(), 1);
1516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1517 Temp src10
= bld
.tmp(src1
.type(), 1);
1518 Temp src11
= bld
.tmp(dst
.type(), 1);
1519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1521 if (dst
.regClass() == s2
) {
1522 Temp carry
= bld
.tmp(s1
);
1523 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1524 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1525 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1526 } else if (dst
.regClass() == v2
) {
1527 Temp dst0
= bld
.tmp(v1
);
1528 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1529 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1530 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1532 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1536 case nir_op_uadd_sat
: {
1537 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1538 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1539 if (dst
.regClass() == s1
) {
1540 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1541 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1543 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1544 } else if (dst
.regClass() == v1
) {
1545 if (ctx
->options
->chip_class
>= GFX9
) {
1546 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1547 add
->operands
[0] = Operand(src0
);
1548 add
->operands
[1] = Operand(src1
);
1549 add
->definitions
[0] = Definition(dst
);
1551 ctx
->block
->instructions
.emplace_back(std::move(add
));
1553 if (src1
.regClass() != v1
)
1554 std::swap(src0
, src1
);
1555 assert(src1
.regClass() == v1
);
1556 Temp tmp
= bld
.tmp(v1
);
1557 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1558 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1561 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1600 if (dst
.regClass() == s1
) {
1601 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1605 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1606 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1607 if (dst
.regClass() == v1
) {
1608 bld
.vsub32(Definition(dst
), src0
, src1
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp carry
= bld
.tmp(s1
);
1620 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1621 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1623 } else if (dst
.regClass() == v2
) {
1624 Temp lower
= bld
.tmp(v1
);
1625 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1626 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1629 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1633 case nir_op_usub_borrow
: {
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == s1
) {
1637 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1639 } else if (dst
.regClass() == v1
) {
1640 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1641 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1645 Temp src00
= bld
.tmp(src0
.type(), 1);
1646 Temp src01
= bld
.tmp(dst
.type(), 1);
1647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1648 Temp src10
= bld
.tmp(src1
.type(), 1);
1649 Temp src11
= bld
.tmp(dst
.type(), 1);
1650 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1651 if (dst
.regClass() == s2
) {
1652 Temp borrow
= bld
.tmp(s1
);
1653 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1654 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1656 } else if (dst
.regClass() == v2
) {
1657 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1658 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1659 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1660 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1662 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1667 if (dst
.regClass() == v1
) {
1668 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1669 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1670 } else if (dst
.regClass() == s1
) {
1671 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1673 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1677 case nir_op_umul_high
: {
1678 if (dst
.regClass() == v1
) {
1679 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1680 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1681 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1682 } else if (dst
.regClass() == s1
) {
1683 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1684 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1685 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1687 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1691 case nir_op_imul_high
: {
1692 if (dst
.regClass() == v1
) {
1693 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1694 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1695 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1696 } else if (dst
.regClass() == s1
) {
1697 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1698 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1699 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1701 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1706 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1707 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1712 } else if (dst
.regClass() == v2
) {
1713 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1715 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1721 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1722 if (dst
.regClass() == v2b
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1726 } else if (dst
.regClass() == v2
) {
1727 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1729 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1736 if (dst
.regClass() == v2b
) {
1737 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1738 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1740 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1741 } else if (dst
.regClass() == v1
) {
1742 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1743 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1746 } else if (dst
.regClass() == v2
) {
1747 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1748 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1749 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1752 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1757 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1758 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1759 if (dst
.regClass() == v2b
) {
1760 // TODO: check fp_mode.must_flush_denorms16_64
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1764 } else if (dst
.regClass() == v2
) {
1765 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1766 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1767 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1769 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1772 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1779 if (dst
.regClass() == v2b
) {
1780 // TODO: check fp_mode.must_flush_denorms16_64
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1782 } else if (dst
.regClass() == v1
) {
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1784 } else if (dst
.regClass() == v2
) {
1785 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1786 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1787 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1789 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1792 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1796 case nir_op_fmax3
: {
1797 if (dst
.regClass() == v2b
) {
1798 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1799 } else if (dst
.regClass() == v1
) {
1800 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1802 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1806 case nir_op_fmin3
: {
1807 if (dst
.regClass() == v2b
) {
1808 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1809 } else if (dst
.regClass() == v1
) {
1810 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1812 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1816 case nir_op_fmed3
: {
1817 if (dst
.regClass() == v2b
) {
1818 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1819 } else if (dst
.regClass() == v1
) {
1820 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1822 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1826 case nir_op_umax3
: {
1827 if (dst
.size() == 1) {
1828 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1830 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1834 case nir_op_umin3
: {
1835 if (dst
.size() == 1) {
1836 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1838 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1842 case nir_op_umed3
: {
1843 if (dst
.size() == 1) {
1844 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1846 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1850 case nir_op_imax3
: {
1851 if (dst
.size() == 1) {
1852 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1854 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1858 case nir_op_imin3
: {
1859 if (dst
.size() == 1) {
1860 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1862 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1866 case nir_op_imed3
: {
1867 if (dst
.size() == 1) {
1868 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1870 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1874 case nir_op_cube_face_coord
: {
1875 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1876 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1877 emit_extract_vector(ctx
, in
, 1, v1
),
1878 emit_extract_vector(ctx
, in
, 2, v1
) };
1879 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1880 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1881 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1882 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1883 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1884 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
), Operand(0x3f000000u
/*0.5*/));
1885 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1886 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
), Operand(0x3f000000u
/*0.5*/));
1887 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1890 case nir_op_cube_face_index
: {
1891 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1892 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1893 emit_extract_vector(ctx
, in
, 1, v1
),
1894 emit_extract_vector(ctx
, in
, 2, v1
) };
1895 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1898 case nir_op_bcsel
: {
1899 emit_bcsel(ctx
, instr
, dst
);
1903 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1904 if (dst
.regClass() == v2b
) {
1905 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1906 } else if (dst
.regClass() == v1
) {
1907 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1908 } else if (dst
.regClass() == v2
) {
1909 /* Lowered at NIR level for precision reasons. */
1910 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1912 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1917 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1918 if (dst
.regClass() == v2b
) {
1919 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1920 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1921 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1922 } else if (dst
.regClass() == v1
) {
1923 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1924 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1925 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1926 } else if (dst
.regClass() == v2
) {
1927 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1928 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1929 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1931 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1932 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1934 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1939 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1940 if (dst
.regClass() == v2b
) {
1941 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1942 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1943 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1944 } else if (dst
.regClass() == v1
) {
1945 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1946 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1947 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1948 } else if (dst
.regClass() == v2
) {
1949 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1950 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1951 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1952 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1953 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1954 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1956 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1961 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1962 if (dst
.regClass() == v2b
) {
1963 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1964 } else if (dst
.regClass() == v1
) {
1965 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1966 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1967 // TODO: confirm that this holds under any circumstances
1968 } else if (dst
.regClass() == v2
) {
1969 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1970 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1973 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1977 case nir_op_flog2
: {
1978 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1979 if (dst
.regClass() == v2b
) {
1980 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1981 } else if (dst
.regClass() == v1
) {
1982 emit_log2(ctx
, bld
, Definition(dst
), src
);
1984 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1989 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1990 if (dst
.regClass() == v2b
) {
1991 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1992 } else if (dst
.regClass() == v1
) {
1993 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1994 } else if (dst
.regClass() == v2
) {
1995 /* Lowered at NIR level for precision reasons. */
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1998 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2002 case nir_op_fexp2
: {
2003 if (dst
.regClass() == v2b
) {
2004 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2005 } else if (dst
.regClass() == v1
) {
2006 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2008 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2012 case nir_op_fsqrt
: {
2013 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2016 } else if (dst
.regClass() == v1
) {
2017 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2018 } else if (dst
.regClass() == v2
) {
2019 /* Lowered at NIR level for precision reasons. */
2020 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2022 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2026 case nir_op_ffract
: {
2027 if (dst
.regClass() == v2b
) {
2028 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2029 } else if (dst
.regClass() == v1
) {
2030 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2031 } else if (dst
.regClass() == v2
) {
2032 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2034 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2038 case nir_op_ffloor
: {
2039 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2040 if (dst
.regClass() == v2b
) {
2041 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2042 } else if (dst
.regClass() == v1
) {
2043 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2044 } else if (dst
.regClass() == v2
) {
2045 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2047 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2051 case nir_op_fceil
: {
2052 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2053 if (dst
.regClass() == v2b
) {
2054 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2055 } else if (dst
.regClass() == v1
) {
2056 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2057 } else if (dst
.regClass() == v2
) {
2058 if (ctx
->options
->chip_class
>= GFX7
) {
2059 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2061 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2062 /* trunc = trunc(src0)
2063 * if (src0 > 0.0 && src0 != trunc)
2066 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2067 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2068 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2069 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2070 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2071 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2072 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2075 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2079 case nir_op_ftrunc
: {
2080 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2081 if (dst
.regClass() == v2b
) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2083 } else if (dst
.regClass() == v1
) {
2084 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2085 } else if (dst
.regClass() == v2
) {
2086 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2088 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2092 case nir_op_fround_even
: {
2093 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2094 if (dst
.regClass() == v2b
) {
2095 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2096 } else if (dst
.regClass() == v1
) {
2097 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2098 } else if (dst
.regClass() == v2
) {
2099 if (ctx
->options
->chip_class
>= GFX7
) {
2100 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2102 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2103 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2104 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2106 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2107 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2108 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2109 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2110 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2111 tmp
= sub
->definitions
[0].getTemp();
2113 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2114 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2115 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2116 Temp cond
= vop3
->definitions
[0].getTemp();
2118 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2119 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2120 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2121 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2123 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2126 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2132 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2133 aco_ptr
<Instruction
> norm
;
2134 if (dst
.regClass() == v2b
) {
2135 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2136 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2137 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2138 bld
.vop1(opcode
, Definition(dst
), tmp
);
2139 } else if (dst
.regClass() == v1
) {
2140 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2141 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2143 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2144 if (ctx
->options
->chip_class
< GFX9
)
2145 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2147 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2148 bld
.vop1(opcode
, Definition(dst
), tmp
);
2150 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2154 case nir_op_ldexp
: {
2155 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2156 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2157 if (dst
.regClass() == v2b
) {
2158 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2159 } else if (dst
.regClass() == v1
) {
2160 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2161 } else if (dst
.regClass() == v2
) {
2162 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2164 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2168 case nir_op_frexp_sig
: {
2169 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2170 if (dst
.regClass() == v2b
) {
2171 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2172 } else if (dst
.regClass() == v1
) {
2173 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2174 } else if (dst
.regClass() == v2
) {
2175 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2177 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2181 case nir_op_frexp_exp
: {
2182 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2183 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2184 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2185 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2186 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2187 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2188 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2189 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2190 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2192 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2196 case nir_op_fsign
: {
2197 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2198 if (dst
.regClass() == v2b
) {
2199 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2200 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2201 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2202 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2203 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2204 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2205 } else if (dst
.regClass() == v1
) {
2206 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2207 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2208 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2209 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2210 } else if (dst
.regClass() == v2
) {
2211 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2212 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2213 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2215 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2216 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2217 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2219 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2221 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2226 case nir_op_f2f16_rtne
: {
2227 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2228 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2229 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2230 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2231 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2232 * keep value numbering and the scheduler simpler.
2234 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2236 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2239 case nir_op_f2f16_rtz
: {
2240 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2241 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2242 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2243 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2246 case nir_op_f2f32
: {
2247 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2248 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2249 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2250 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2252 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2256 case nir_op_f2f64
: {
2257 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2258 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2259 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2260 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2263 case nir_op_i2f16
: {
2264 assert(dst
.regClass() == v2b
);
2265 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2266 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2267 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2268 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2269 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2270 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2273 case nir_op_i2f32
: {
2274 assert(dst
.size() == 1);
2275 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2276 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2277 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2278 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2281 case nir_op_i2f64
: {
2282 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2283 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2284 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2285 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2286 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2287 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2288 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2289 RegClass rc
= RegClass(src
.type(), 1);
2290 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2291 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2292 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2293 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2294 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2295 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2298 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2302 case nir_op_u2f16
: {
2303 assert(dst
.regClass() == v2b
);
2304 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2305 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2306 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2307 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2308 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2309 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2312 case nir_op_u2f32
: {
2313 assert(dst
.size() == 1);
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2316 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2318 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2319 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2320 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2324 case nir_op_u2f64
: {
2325 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2326 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2327 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2328 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2329 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2330 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2331 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2332 RegClass rc
= RegClass(src
.type(), 1);
2333 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2334 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2335 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2336 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2337 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2338 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2340 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2345 case nir_op_f2i16
: {
2346 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2347 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2348 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2349 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2351 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2355 case nir_op_f2u16
: {
2356 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2357 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2358 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2359 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2361 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2364 case nir_op_f2i32
: {
2365 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2366 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2367 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2368 if (dst
.type() == RegType::vgpr
) {
2369 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2371 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2372 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2374 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2375 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2376 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2377 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2379 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2383 case nir_op_f2u32
: {
2384 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2385 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2386 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2387 if (dst
.type() == RegType::vgpr
) {
2388 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2390 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2391 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2393 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2394 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2395 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2396 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2398 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2402 case nir_op_f2i64
: {
2403 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2404 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2405 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2407 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2408 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2409 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2410 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2411 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2412 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2413 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2414 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2415 Temp new_exponent
= bld
.tmp(v1
);
2416 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2417 if (ctx
->program
->chip_class
>= GFX8
)
2418 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2420 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2421 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2422 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2423 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2424 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2425 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2426 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2427 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2428 Temp new_lower
= bld
.tmp(v1
);
2429 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2430 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2431 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2433 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2434 if (src
.type() == RegType::vgpr
)
2435 src
= bld
.as_uniform(src
);
2436 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2437 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2438 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2439 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2440 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2441 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2442 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2443 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2444 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2445 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2446 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2447 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2448 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2449 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2450 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2451 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2452 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2453 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2454 Temp borrow
= bld
.tmp(s1
);
2455 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2456 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2457 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2459 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2460 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2461 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2462 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2463 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2464 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2465 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2466 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2467 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2468 if (dst
.type() == RegType::sgpr
) {
2469 lower
= bld
.as_uniform(lower
);
2470 upper
= bld
.as_uniform(upper
);
2472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2475 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2479 case nir_op_f2u64
: {
2480 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2481 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2482 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2484 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2485 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2486 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2487 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2488 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2489 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2490 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2491 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2492 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2493 Temp new_exponent
= bld
.tmp(v1
);
2494 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2495 if (ctx
->program
->chip_class
>= GFX8
)
2496 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2498 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2499 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2500 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2501 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2502 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2503 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2504 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2507 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2508 if (src
.type() == RegType::vgpr
)
2509 src
= bld
.as_uniform(src
);
2510 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2511 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2512 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2513 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2514 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2515 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2516 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2517 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2518 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2519 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2520 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2521 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2522 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2523 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2524 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2525 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2526 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2527 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2529 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2530 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2531 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2532 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2533 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2534 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2535 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2536 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2537 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2538 if (dst
.type() == RegType::sgpr
) {
2539 lower
= bld
.as_uniform(lower
);
2540 upper
= bld
.as_uniform(upper
);
2542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2545 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2549 case nir_op_b2f16
: {
2550 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2551 assert(src
.regClass() == bld
.lm
);
2553 if (dst
.regClass() == s1
) {
2554 src
= bool_to_scalar_condition(ctx
, src
);
2555 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2556 } else if (dst
.regClass() == v2b
) {
2557 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2558 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2560 unreachable("Wrong destination register class for nir_op_b2f16.");
2564 case nir_op_b2f32
: {
2565 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2566 assert(src
.regClass() == bld
.lm
);
2568 if (dst
.regClass() == s1
) {
2569 src
= bool_to_scalar_condition(ctx
, src
);
2570 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2571 } else if (dst
.regClass() == v1
) {
2572 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2574 unreachable("Wrong destination register class for nir_op_b2f32.");
2578 case nir_op_b2f64
: {
2579 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2580 assert(src
.regClass() == bld
.lm
);
2582 if (dst
.regClass() == s2
) {
2583 src
= bool_to_scalar_condition(ctx
, src
);
2584 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2585 } else if (dst
.regClass() == v2
) {
2586 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2587 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2590 unreachable("Wrong destination register class for nir_op_b2f64.");
2597 case nir_op_i2i64
: {
2598 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2599 /* no need to do the extract in get_alu_src() */
2600 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2601 sgpr_extract_sext
: sgpr_extract_undef
;
2602 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2604 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2605 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2612 case nir_op_u2u64
: {
2613 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2614 /* no need to do the extract in get_alu_src() */
2615 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2616 sgpr_extract_zext
: sgpr_extract_undef
;
2617 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2619 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2620 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2628 case nir_op_b2i64
: {
2629 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2630 assert(src
.regClass() == bld
.lm
);
2632 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2633 if (tmp
.regClass() == s1
) {
2634 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2635 bool_to_scalar_condition(ctx
, src
, tmp
);
2636 } else if (tmp
.type() == RegType::vgpr
) {
2637 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2639 unreachable("Invalid register class for b2i32");
2643 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2648 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2649 assert(dst
.regClass() == bld
.lm
);
2651 if (src
.type() == RegType::vgpr
) {
2652 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2653 assert(dst
.regClass() == bld
.lm
);
2654 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2655 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2657 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2659 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2660 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2662 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2663 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2665 bool_to_vector_condition(ctx
, tmp
, dst
);
2669 case nir_op_pack_64_2x32_split
: {
2670 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2671 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2673 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2676 case nir_op_unpack_64_2x32_split_x
:
2677 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2679 case nir_op_unpack_64_2x32_split_y
:
2680 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2682 case nir_op_unpack_32_2x16_split_x
:
2683 if (dst
.type() == RegType::vgpr
) {
2684 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2686 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2689 case nir_op_unpack_32_2x16_split_y
:
2690 if (dst
.type() == RegType::vgpr
) {
2691 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2693 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2696 case nir_op_pack_32_2x16_split
: {
2697 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2698 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2699 if (dst
.regClass() == v1
) {
2700 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2701 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2702 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2704 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2705 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2706 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2710 case nir_op_pack_half_2x16
: {
2711 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2713 if (dst
.regClass() == v1
) {
2714 Temp src0
= bld
.tmp(v1
);
2715 Temp src1
= bld
.tmp(v1
);
2716 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2717 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2718 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2720 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2721 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2722 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2724 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2728 case nir_op_unpack_half_2x16_split_x
: {
2729 if (dst
.regClass() == v1
) {
2730 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2732 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2736 case nir_op_unpack_half_2x16_split_y
: {
2737 if (dst
.regClass() == v1
) {
2738 /* TODO: use SDWA here */
2739 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2740 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2742 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2746 case nir_op_fquantize2f16
: {
2747 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2748 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2751 if (ctx
->program
->chip_class
>= GFX8
) {
2752 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2753 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2754 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2756 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2757 * so compare the result and flush to 0 if it's smaller.
2759 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2760 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2761 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2762 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2763 cmp_res
= vop3
->definitions
[0].getTemp();
2766 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2767 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2768 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2770 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2775 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2776 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2778 if (dst
.regClass() == s1
) {
2779 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2780 } else if (dst
.regClass() == v1
) {
2781 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2783 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2787 case nir_op_bitfield_select
: {
2788 /* (mask & insert) | (~mask & base) */
2789 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2790 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2791 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2793 /* dst = (insert & bitmask) | (base & ~bitmask) */
2794 if (dst
.regClass() == s1
) {
2795 aco_ptr
<Instruction
> sop2
;
2796 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2797 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2799 if (const_insert
&& const_bitmask
) {
2800 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2802 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2803 lhs
= Operand(insert
);
2807 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2808 if (const_base
&& const_bitmask
) {
2809 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2811 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2812 rhs
= Operand(base
);
2815 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2817 } else if (dst
.regClass() == v1
) {
2818 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2819 base
= as_vgpr(ctx
, base
);
2820 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2821 insert
= as_vgpr(ctx
, insert
);
2823 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2826 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2832 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2833 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2834 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2836 if (dst
.type() == RegType::sgpr
) {
2838 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2839 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2840 if (const_offset
&& const_bits
) {
2841 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2842 extract
= Operand(const_extract
);
2846 width
= Operand(const_bits
->u32
<< 16);
2848 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2850 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2854 if (dst
.regClass() == s1
) {
2855 if (instr
->op
== nir_op_ubfe
)
2856 opcode
= aco_opcode::s_bfe_u32
;
2858 opcode
= aco_opcode::s_bfe_i32
;
2859 } else if (dst
.regClass() == s2
) {
2860 if (instr
->op
== nir_op_ubfe
)
2861 opcode
= aco_opcode::s_bfe_u64
;
2863 opcode
= aco_opcode::s_bfe_i64
;
2865 unreachable("Unsupported BFE bit size");
2868 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2872 if (dst
.regClass() == v1
) {
2873 if (instr
->op
== nir_op_ubfe
)
2874 opcode
= aco_opcode::v_bfe_u32
;
2876 opcode
= aco_opcode::v_bfe_i32
;
2878 unreachable("Unsupported BFE bit size");
2881 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2885 case nir_op_bit_count
: {
2886 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2887 if (src
.regClass() == s1
) {
2888 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2889 } else if (src
.regClass() == v1
) {
2890 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2891 } else if (src
.regClass() == v2
) {
2892 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2893 emit_extract_vector(ctx
, src
, 1, v1
),
2894 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2895 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2896 } else if (src
.regClass() == s2
) {
2897 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2899 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2904 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2908 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2912 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2916 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2920 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2924 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2928 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2929 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2931 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2932 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2936 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2937 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2939 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2940 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2948 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2953 case nir_op_fddx_fine
:
2954 case nir_op_fddy_fine
:
2955 case nir_op_fddx_coarse
:
2956 case nir_op_fddy_coarse
: {
2957 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2958 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2959 if (instr
->op
== nir_op_fddx_fine
) {
2960 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2961 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2962 } else if (instr
->op
== nir_op_fddy_fine
) {
2963 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2964 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2966 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2967 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2968 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2970 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2974 if (ctx
->program
->chip_class
>= GFX8
) {
2975 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2976 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2978 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2979 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2980 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2982 emit_wqm(ctx
, tmp
, dst
, true);
2986 isel_err(&instr
->instr
, "Unknown NIR ALU instr");
2990 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2992 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2994 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2995 // which get truncated the lsb if double and msb if int
2996 // for now, we only use s_mov_b64 with 64bit inline constants
2997 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2998 assert(dst
.type() == RegType::sgpr
);
3000 Builder
bld(ctx
->program
, ctx
->block
);
3002 if (instr
->def
.bit_size
== 1) {
3003 assert(dst
.regClass() == bld
.lm
);
3004 int val
= instr
->value
[0].b
? -1 : 0;
3005 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3006 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3007 } else if (instr
->def
.bit_size
== 8) {
3008 /* ensure that the value is correctly represented in the low byte of the register */
3009 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3010 } else if (instr
->def
.bit_size
== 16) {
3011 /* ensure that the value is correctly represented in the low half of the register */
3012 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3013 } else if (dst
.size() == 1) {
3014 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3016 assert(dst
.size() != 1);
3017 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3018 if (instr
->def
.bit_size
== 64)
3019 for (unsigned i
= 0; i
< dst
.size(); i
++)
3020 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3022 for (unsigned i
= 0; i
< dst
.size(); i
++)
3023 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3025 vec
->definitions
[0] = Definition(dst
);
3026 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3030 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3032 uint32_t new_mask
= 0;
3033 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3034 if (mask
& (1u << i
))
3035 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3039 struct LoadEmitInfo
{
3042 unsigned num_components
;
3043 unsigned component_size
;
3044 Temp resource
= Temp(0, s1
);
3045 unsigned component_stride
= 0;
3046 unsigned const_offset
= 0;
3047 unsigned align_mul
= 0;
3048 unsigned align_offset
= 0;
3051 unsigned swizzle_component_size
= 0;
3052 memory_sync_info sync
;
3053 Temp soffset
= Temp(0, s1
);
3056 using LoadCallback
= Temp(*)(
3057 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3058 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3060 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3061 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3063 unsigned load_size
= info
->num_components
* info
->component_size
;
3064 unsigned component_size
= info
->component_size
;
3066 unsigned num_vals
= 0;
3067 Temp vals
[info
->dst
.bytes()];
3069 unsigned const_offset
= info
->const_offset
;
3071 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3072 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3074 unsigned bytes_read
= 0;
3075 while (bytes_read
< load_size
) {
3076 unsigned bytes_needed
= load_size
- bytes_read
;
3078 /* add buffer for unaligned loads */
3079 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3082 if ((bytes_needed
> 2 ||
3083 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3084 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3085 if (info
->component_stride
) {
3086 assert(supports_8bit_16bit_loads
&& "unimplemented");
3090 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3091 bytes_needed
= align(bytes_needed
, 4);
3098 if (info
->swizzle_component_size
)
3099 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3100 if (info
->component_stride
)
3101 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3103 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3105 /* reduce constant offset */
3106 Operand offset
= info
->offset
;
3107 unsigned reduced_const_offset
= const_offset
;
3108 bool remove_const_offset_completely
= need_to_align_offset
;
3109 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3110 unsigned to_add
= const_offset
;
3111 if (remove_const_offset_completely
) {
3112 reduced_const_offset
= 0;
3114 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3115 reduced_const_offset
%= max_const_offset_plus_one
;
3117 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3118 if (offset
.isConstant()) {
3119 offset
= Operand(offset
.constantValue() + to_add
);
3120 } else if (offset_tmp
.regClass() == s1
) {
3121 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3122 offset_tmp
, Operand(to_add
));
3123 } else if (offset_tmp
.regClass() == v1
) {
3124 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3126 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3127 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3128 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3130 if (offset_tmp
.regClass() == s2
) {
3131 Temp carry
= bld
.tmp(s1
);
3132 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3133 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3134 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3136 Temp new_lo
= bld
.tmp(v1
);
3137 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3138 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3139 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3144 /* align offset down if needed */
3145 Operand aligned_offset
= offset
;
3146 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3147 if (need_to_align_offset
) {
3149 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3150 if (offset
.isConstant()) {
3151 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3152 } else if (offset_tmp
.regClass() == s1
) {
3153 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3154 } else if (offset_tmp
.regClass() == s2
) {
3155 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3156 } else if (offset_tmp
.regClass() == v1
) {
3157 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3158 } else if (offset_tmp
.regClass() == v2
) {
3159 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3160 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3161 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3162 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3165 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3166 bld
.copy(bld
.def(s1
), aligned_offset
);
3168 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3169 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3171 /* the callback wrote directly to dst */
3172 if (val
== info
->dst
) {
3173 assert(num_vals
== 0);
3174 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3178 /* shift result right if needed */
3179 if (info
->component_size
< 4 && byte_align_loads
) {
3180 Operand
align((uint32_t)byte_align
);
3181 if (byte_align
== -1) {
3182 if (offset
.isConstant())
3183 align
= Operand(offset
.constantValue() % 4u);
3184 else if (offset
.size() == 2)
3185 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3190 assert(val
.bytes() >= load_size
&& "unimplemented");
3191 if (val
.type() == RegType::sgpr
)
3192 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3194 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3198 /* add result to list and advance */
3199 if (info
->component_stride
) {
3200 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3201 const_offset
+= info
->component_stride
;
3202 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3204 const_offset
+= val
.bytes();
3205 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3207 bytes_read
+= val
.bytes();
3208 vals
[num_vals
++] = val
;
3211 /* create array of components */
3212 unsigned components_split
= 0;
3213 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3214 bool has_vgprs
= false;
3215 for (unsigned i
= 0; i
< num_vals
;) {
3217 unsigned num_tmps
= 0;
3218 unsigned tmp_size
= 0;
3219 RegType reg_type
= RegType::sgpr
;
3220 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3221 if (vals
[i
].type() == RegType::vgpr
)
3222 reg_type
= RegType::vgpr
;
3223 tmp_size
+= vals
[i
].bytes();
3224 tmp
[num_tmps
++] = vals
[i
++];
3227 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3228 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3229 for (unsigned i
= 0; i
< num_tmps
; i
++)
3230 vec
->operands
[i
] = Operand(tmp
[i
]);
3231 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3232 vec
->definitions
[0] = Definition(tmp
[0]);
3233 bld
.insert(std::move(vec
));
3236 if (tmp
[0].bytes() % component_size
) {
3238 assert(i
== num_vals
);
3239 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3240 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3243 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3245 unsigned start
= components_split
;
3247 if (tmp_size
== elem_rc
.bytes()) {
3248 allocated_vec
[components_split
++] = tmp
[0];
3250 assert(tmp_size
% elem_rc
.bytes() == 0);
3251 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3252 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3253 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3254 Temp component
= bld
.tmp(elem_rc
);
3255 allocated_vec
[components_split
++] = component
;
3256 split
->definitions
[i
] = Definition(component
);
3258 split
->operands
[0] = Operand(tmp
[0]);
3259 bld
.insert(std::move(split
));
3262 /* try to p_as_uniform early so we can create more optimizable code and
3263 * also update allocated_vec */
3264 for (unsigned j
= start
; j
< components_split
; j
++) {
3265 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3266 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3267 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3271 /* concatenate components and p_as_uniform() result if needed */
3272 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3273 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3275 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3277 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3278 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3279 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3280 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3282 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3283 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3284 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3285 vec
->definitions
[0] = Definition(tmp
);
3286 bld
.insert(std::move(vec
));
3287 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3289 vec
->definitions
[0] = Definition(info
->dst
);
3290 bld
.insert(std::move(vec
));
3294 Operand
load_lds_size_m0(Builder
& bld
)
3296 /* TODO: m0 does not need to be initialized on GFX9+ */
3297 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3300 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3301 Temp offset
, unsigned bytes_needed
,
3302 unsigned align
, unsigned const_offset
,
3305 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3307 Operand m
= load_lds_size_m0(bld
);
3309 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3310 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3315 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3316 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3318 op
= aco_opcode::ds_read_b128
;
3319 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3322 op
= aco_opcode::ds_read2_b64
;
3323 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3325 op
= aco_opcode::ds_read_b96
;
3326 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3328 op
= aco_opcode::ds_read_b64
;
3329 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3332 op
= aco_opcode::ds_read2_b32
;
3333 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3335 op
= aco_opcode::ds_read_b32
;
3336 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3338 op
= aco_opcode::ds_read_u16
;
3341 op
= aco_opcode::ds_read_u8
;
3344 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3345 if (const_offset
>= max_offset_plus_one
) {
3346 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3347 const_offset
%= max_offset_plus_one
;
3351 const_offset
/= (size
/ 2u);
3353 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3354 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3357 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3359 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3360 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3363 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3368 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3370 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3371 Temp offset
, unsigned bytes_needed
,
3372 unsigned align
, unsigned const_offset
,
3377 if (bytes_needed
<= 4) {
3379 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3380 } else if (bytes_needed
<= 8) {
3382 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3383 } else if (bytes_needed
<= 16) {
3385 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3386 } else if (bytes_needed
<= 32) {
3388 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3391 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3393 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3394 if (info
->resource
.id()) {
3395 load
->operands
[0] = Operand(info
->resource
);
3396 load
->operands
[1] = Operand(offset
);
3398 load
->operands
[0] = Operand(offset
);
3399 load
->operands
[1] = Operand(0u);
3401 RegClass
rc(RegType::sgpr
, size
);
3402 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3403 load
->definitions
[0] = Definition(val
);
3404 load
->glc
= info
->glc
;
3405 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3406 load
->sync
= info
->sync
;
3407 bld
.insert(std::move(load
));
3411 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3413 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3414 Temp offset
, unsigned bytes_needed
,
3415 unsigned align_
, unsigned const_offset
,
3418 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3419 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3421 if (info
->soffset
.id()) {
3422 if (soffset
.isTemp())
3423 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3424 soffset
= Operand(info
->soffset
);
3427 unsigned bytes_size
= 0;
3429 if (bytes_needed
== 1 || align_
% 2) {
3431 op
= aco_opcode::buffer_load_ubyte
;
3432 } else if (bytes_needed
== 2 || align_
% 4) {
3434 op
= aco_opcode::buffer_load_ushort
;
3435 } else if (bytes_needed
<= 4) {
3437 op
= aco_opcode::buffer_load_dword
;
3438 } else if (bytes_needed
<= 8) {
3440 op
= aco_opcode::buffer_load_dwordx2
;
3441 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3443 op
= aco_opcode::buffer_load_dwordx3
;
3446 op
= aco_opcode::buffer_load_dwordx4
;
3448 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3449 mubuf
->operands
[0] = Operand(info
->resource
);
3450 mubuf
->operands
[1] = vaddr
;
3451 mubuf
->operands
[2] = soffset
;
3452 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3453 mubuf
->glc
= info
->glc
;
3454 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3455 mubuf
->sync
= info
->sync
;
3456 mubuf
->offset
= const_offset
;
3457 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3458 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3459 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3460 mubuf
->definitions
[0] = Definition(val
);
3461 bld
.insert(std::move(mubuf
));
3466 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3467 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3469 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3471 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3472 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3474 if (addr
.type() == RegType::vgpr
)
3475 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3476 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3479 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3480 Temp offset
, unsigned bytes_needed
,
3481 unsigned align_
, unsigned const_offset
,
3484 unsigned bytes_size
= 0;
3485 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3486 bool global
= bld
.program
->chip_class
>= GFX9
;
3488 if (bytes_needed
== 1) {
3490 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3491 } else if (bytes_needed
== 2) {
3493 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3494 } else if (bytes_needed
<= 4) {
3496 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3497 } else if (bytes_needed
<= 8) {
3499 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3500 } else if (bytes_needed
<= 12 && !mubuf
) {
3502 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3505 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3507 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3508 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3510 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3511 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3512 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3513 mubuf
->operands
[2] = Operand(0u);
3514 mubuf
->glc
= info
->glc
;
3517 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3518 mubuf
->disable_wqm
= false;
3519 mubuf
->sync
= info
->sync
;
3520 mubuf
->definitions
[0] = Definition(val
);
3521 bld
.insert(std::move(mubuf
));
3523 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3525 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3526 flat
->operands
[0] = Operand(offset
);
3527 flat
->operands
[1] = Operand(s1
);
3528 flat
->glc
= info
->glc
;
3529 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3530 flat
->sync
= info
->sync
;
3532 flat
->definitions
[0] = Definition(val
);
3533 bld
.insert(std::move(flat
));
3539 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3541 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3542 Temp address
, unsigned base_offset
, unsigned align
)
3544 assert(util_is_power_of_two_nonzero(align
));
3546 Builder
bld(ctx
->program
, ctx
->block
);
3548 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3549 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3550 info
.align_mul
= align
;
3551 info
.align_offset
= 0;
3552 info
.sync
= memory_sync_info(storage_shared
);
3553 info
.const_offset
= base_offset
;
3554 emit_lds_load(ctx
, bld
, &info
);
3559 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3564 Builder
bld(ctx
->program
, ctx
->block
);
3566 ASSERTED
bool is_subdword
= false;
3567 for (unsigned i
= 0; i
< count
; i
++)
3568 is_subdword
|= offsets
[i
] % 4;
3569 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3570 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3572 /* count == 1 fast path */
3574 if (dst_type
== RegType::sgpr
)
3575 dst
[0] = bld
.as_uniform(src
);
3577 dst
[0] = as_vgpr(ctx
, src
);
3581 for (unsigned i
= 0; i
< count
- 1; i
++)
3582 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3583 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3585 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3586 src
= as_vgpr(ctx
, src
);
3588 /* use allocated_vec if possible */
3589 auto it
= ctx
->allocated_vec
.find(src
.id());
3590 if (it
!= ctx
->allocated_vec
.end()) {
3591 if (!it
->second
[0].id())
3593 unsigned elem_size
= it
->second
[0].bytes();
3594 assert(src
.bytes() % elem_size
== 0);
3596 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3597 if (!it
->second
[i
].id())
3601 for (unsigned i
= 0; i
< count
; i
++) {
3602 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3606 for (unsigned i
= 0; i
< count
; i
++) {
3607 unsigned start_idx
= offsets
[i
] / elem_size
;
3608 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3609 if (op_count
== 1) {
3610 if (dst_type
== RegType::sgpr
)
3611 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3613 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3617 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3618 for (unsigned j
= 0; j
< op_count
; j
++) {
3619 Temp tmp
= it
->second
[start_idx
+ j
];
3620 if (dst_type
== RegType::sgpr
)
3621 tmp
= bld
.as_uniform(tmp
);
3622 vec
->operands
[j
] = Operand(tmp
);
3624 vec
->definitions
[0] = Definition(dst
[i
]);
3625 bld
.insert(std::move(vec
));
3633 if (dst_type
== RegType::sgpr
)
3634 src
= bld
.as_uniform(src
);
3637 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3638 split
->operands
[0] = Operand(src
);
3639 for (unsigned i
= 0; i
< count
; i
++)
3640 split
->definitions
[i
] = Definition(dst
[i
]);
3641 bld
.insert(std::move(split
));
3644 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3645 int *start
, int *count
)
3647 unsigned start_elem
= ffs(todo_mask
) - 1;
3648 bool skip
= !(mask
& (1 << start_elem
));
3650 mask
= ~mask
& todo_mask
;
3654 u_bit_scan_consecutive_range(&mask
, start
, count
);
3659 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3661 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3664 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3665 Temp address
, unsigned base_offset
, unsigned align
)
3667 assert(util_is_power_of_two_nonzero(align
));
3668 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3670 Builder
bld(ctx
->program
, ctx
->block
);
3671 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3672 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3674 unsigned write_count
= 0;
3675 Temp write_datas
[32];
3676 unsigned offsets
[32];
3677 aco_opcode opcodes
[32];
3679 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3681 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3684 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3685 offsets
[write_count
] = offset
;
3686 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3688 advance_write_mask(&todo
, offset
, bytes
);
3692 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3693 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3694 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3695 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3697 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3698 aco_opcode op
= aco_opcode::num_opcodes
;
3699 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3700 op
= aco_opcode::ds_write_b128
;
3702 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3703 op
= aco_opcode::ds_write_b96
;
3705 } else if (bytes
>= 8 && aligned8
) {
3706 op
= aco_opcode::ds_write_b64
;
3708 } else if (bytes
>= 4 && aligned4
) {
3709 op
= aco_opcode::ds_write_b32
;
3711 } else if (bytes
>= 2 && aligned2
) {
3712 op
= aco_opcode::ds_write_b16
;
3714 } else if (bytes
>= 1) {
3715 op
= aco_opcode::ds_write_b8
;
3721 offsets
[write_count
] = offset
;
3722 opcodes
[write_count
] = op
;
3724 advance_write_mask(&todo
, offset
, bytes
);
3727 Operand m
= load_lds_size_m0(bld
);
3729 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3731 for (unsigned i
= 0; i
< write_count
; i
++) {
3732 aco_opcode op
= opcodes
[i
];
3733 if (op
== aco_opcode::num_opcodes
)
3736 Temp data
= write_datas
[i
];
3738 unsigned second
= write_count
;
3739 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3740 for (second
= i
+ 1; second
< write_count
; second
++) {
3741 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3742 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3743 opcodes
[second
] = aco_opcode::num_opcodes
;
3749 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3750 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3752 unsigned inline_offset
= base_offset
+ offsets
[i
];
3753 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3754 Temp address_offset
= address
;
3755 if (inline_offset
> max_offset
) {
3756 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3757 inline_offset
= offsets
[i
];
3759 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3763 Temp second_data
= write_datas
[second
];
3764 inline_offset
/= data
.bytes();
3765 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3767 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3769 static_cast<DS_instruction
*>(instr
)->sync
=
3770 memory_sync_info(storage_shared
);
3774 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3776 unsigned align
= 16;
3778 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3784 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3789 return aco_opcode::buffer_store_byte
;
3792 return aco_opcode::buffer_store_short
;
3794 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3796 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3799 return aco_opcode::buffer_store_dwordx3
;
3801 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3803 unreachable("Unexpected store size");
3804 return aco_opcode::num_opcodes
;
3807 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3808 Temp data
, unsigned writemask
, int swizzle_element_size
,
3809 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3811 unsigned write_count_with_skips
= 0;
3814 /* determine how to split the data */
3815 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3818 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3819 offsets
[write_count_with_skips
] = offset
;
3820 if (skips
[write_count_with_skips
]) {
3821 advance_write_mask(&todo
, offset
, bytes
);
3822 write_count_with_skips
++;
3826 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3827 * larger than swizzle_element_size */
3828 bytes
= MIN2(bytes
, swizzle_element_size
);
3830 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3832 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3833 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3836 /* dword or larger stores have to be dword-aligned */
3837 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3838 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3839 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3841 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3843 advance_write_mask(&todo
, offset
, bytes
);
3844 write_count_with_skips
++;
3847 /* actually split data */
3848 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3851 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3854 write_datas
[*write_count
] = write_datas
[i
];
3855 offsets
[*write_count
] = offsets
[i
];
3860 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3861 unsigned split_cnt
= 0u, Temp dst
= Temp())
3863 Builder
bld(ctx
->program
, ctx
->block
);
3864 unsigned dword_size
= elem_size_bytes
/ 4;
3867 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3869 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3870 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3871 instr
->definitions
[0] = Definition(dst
);
3873 for (unsigned i
= 0; i
< cnt
; ++i
) {
3875 assert(arr
[i
].size() == dword_size
);
3876 allocated_vec
[i
] = arr
[i
];
3877 instr
->operands
[i
] = Operand(arr
[i
]);
3879 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3880 allocated_vec
[i
] = zero
;
3881 instr
->operands
[i
] = Operand(zero
);
3885 bld
.insert(std::move(instr
));
3888 emit_split_vector(ctx
, dst
, split_cnt
);
3890 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3895 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3897 if (const_offset
>= 4096) {
3898 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3899 const_offset
%= 4096u;
3902 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3903 else if (unlikely(voffset
.regClass() == s1
))
3904 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3905 else if (likely(voffset
.regClass() == v1
))
3906 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3908 unreachable("Unsupported register class of voffset");
3911 return const_offset
;
3914 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3915 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
3916 bool slc
= false, bool swizzled
= false)
3919 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3920 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3922 Builder
bld(ctx
->program
, ctx
->block
);
3923 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3924 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3926 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3927 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3928 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3929 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
3930 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
3931 /* dlc*/ false, /* slc */ slc
);
3933 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
3936 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3937 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3938 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
3940 Builder
bld(ctx
->program
, ctx
->block
);
3941 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3943 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3945 unsigned write_count
= 0;
3946 Temp write_datas
[32];
3947 unsigned offsets
[32];
3948 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3949 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3951 for (unsigned i
= 0; i
< write_count
; i
++) {
3952 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3953 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
3957 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3958 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3959 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3961 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3962 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3963 assert(!!stride
!= allow_combining
);
3965 Builder
bld(ctx
->program
, ctx
->block
);
3967 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3968 info
.component_stride
= allow_combining
? 0 : stride
;
3970 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3971 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3972 info
.align_offset
= 0;
3973 info
.soffset
= soffset
;
3974 info
.const_offset
= base_const_offset
;
3975 emit_mubuf_load(ctx
, bld
, &info
);
3978 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3980 Builder
bld(ctx
->program
, ctx
->block
);
3981 Temp offset
= base_offset
.first
;
3982 unsigned const_offset
= base_offset
.second
;
3984 if (!nir_src_is_const(*off_src
)) {
3985 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3988 /* Calculate indirect offset with stride */
3989 if (likely(indirect_offset_arg
.regClass() == v1
))
3990 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3991 else if (indirect_offset_arg
.regClass() == s1
)
3992 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3994 unreachable("Unsupported register class of indirect offset");
3996 /* Add to the supplied base offset */
3997 if (offset
.id() == 0)
3998 offset
= with_stride
;
3999 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4000 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4001 else if (offset
.size() == 1 && with_stride
.size() == 1)
4002 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4004 unreachable("Unsupported register class of indirect offset");
4006 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4007 const_offset
+= const_offset_arg
* stride
;
4010 return std::make_pair(offset
, const_offset
);
4013 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4015 Builder
bld(ctx
->program
, ctx
->block
);
4018 if (off1
.first
.id() && off2
.first
.id()) {
4019 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4020 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4021 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4022 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4024 unreachable("Unsupported register class of indirect offset");
4026 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4029 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4032 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4034 Builder
bld(ctx
->program
, ctx
->block
);
4035 unsigned const_offset
= offs
.second
* multiplier
;
4037 if (!offs
.first
.id())
4038 return std::make_pair(offs
.first
, const_offset
);
4040 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4041 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4042 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4044 return std::make_pair(offset
, const_offset
);
4047 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4049 Builder
bld(ctx
->program
, ctx
->block
);
4051 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4052 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4053 /* component is in bytes */
4054 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4056 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4057 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4058 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4061 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4063 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4066 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4068 Builder
bld(ctx
->program
, ctx
->block
);
4070 switch (ctx
->shader
->info
.stage
) {
4071 case MESA_SHADER_TESS_CTRL
:
4072 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4073 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4074 case MESA_SHADER_TESS_EVAL
:
4075 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4077 unreachable("Unsupported stage in get_tess_rel_patch_id");
4081 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4083 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4084 Builder
bld(ctx
->program
, ctx
->block
);
4086 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4087 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4089 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4091 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4092 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4094 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4095 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4096 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4098 return offset_mul(ctx
, offs
, 4u);
4101 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4103 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4104 Builder
bld(ctx
->program
, ctx
->block
);
4106 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4107 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4108 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4109 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4111 std::pair
<Temp
, unsigned> offs
= instr
4112 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4113 : std::make_pair(Temp(), 0u);
4115 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4116 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4121 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4122 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4124 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4125 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4127 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4128 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4134 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4136 Builder
bld(ctx
->program
, ctx
->block
);
4138 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4139 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4141 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4143 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4144 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4145 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4147 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4148 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4153 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4155 Builder
bld(ctx
->program
, ctx
->block
);
4157 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4158 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4159 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4160 unsigned attr_stride
= ctx
->tcs_num_patches
;
4162 std::pair
<Temp
, unsigned> offs
= instr
4163 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4164 : std::make_pair(Temp(), 0u);
4166 if (const_base_offset
)
4167 offs
.second
+= const_base_offset
* attr_stride
;
4169 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4170 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4171 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4176 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4178 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4183 unsigned drv_loc
= nir_intrinsic_base(instr
);
4184 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4186 if (!nir_src_is_const(*off_src
)) {
4192 uint64_t slot
= per_vertex
4193 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4194 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4195 return (((uint64_t) 1) << slot
) & mask
;
4198 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4200 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4201 unsigned component
= nir_intrinsic_component(instr
);
4202 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4204 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4205 if (off_instr
->type
!= nir_instr_type_load_const
)
4208 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4209 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4211 if (instr
->src
[0].ssa
->bit_size
== 64)
4212 write_mask
= widen_mask(write_mask
, 2);
4214 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4216 for (unsigned i
= 0; i
< 8; ++i
) {
4217 if (write_mask
& (1 << i
)) {
4218 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4219 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4227 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4229 /* Only TCS per-vertex inputs are supported by this function.
4230 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4232 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4235 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4236 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4237 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4238 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4239 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4240 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4245 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4246 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4247 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4252 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4254 Builder
bld(ctx
->program
, ctx
->block
);
4256 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4257 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4258 bool indirect_write
;
4259 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4260 if (temp_only_input
&& !indirect_write
)
4264 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4265 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4266 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4267 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4269 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4270 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4271 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4272 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4273 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4277 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4278 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4279 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4280 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4281 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4282 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4283 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4284 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4285 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4286 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4287 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4288 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4289 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4291 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4292 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4294 unreachable("Invalid LS or ES stage");
4297 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4298 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4299 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4303 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4308 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4309 return off
== ctx
->tcs_tess_lvl_out_loc
||
4310 off
== ctx
->tcs_tess_lvl_in_loc
;
4314 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4316 uint64_t mask
= per_vertex
4317 ? ctx
->program
->info
->tcs
.tes_inputs_read
4318 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4320 bool indirect_write
= false;
4321 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4322 return indirect_write
|| output_read_by_tes
;
4325 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4327 uint64_t mask
= per_vertex
4328 ? ctx
->shader
->info
.outputs_read
4329 : ctx
->shader
->info
.patch_outputs_read
;
4331 bool indirect_write
= false;
4332 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4333 return indirect_write
|| output_read
;
4336 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4338 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4339 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4341 Builder
bld(ctx
->program
, ctx
->block
);
4343 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4344 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4345 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4347 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4348 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4349 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4351 if (write_to_vmem
) {
4352 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4353 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4354 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4356 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4357 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4358 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4362 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4363 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4364 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4368 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4370 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4371 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4373 Builder
bld(ctx
->program
, ctx
->block
);
4375 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4376 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4377 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4378 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4380 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4383 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4385 if (ctx
->stage
== vertex_vs
||
4386 ctx
->stage
== tess_eval_vs
||
4387 ctx
->stage
== fragment_fs
||
4388 ctx
->stage
== ngg_vertex_gs
||
4389 ctx
->stage
== ngg_tess_eval_gs
||
4390 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4391 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4392 if (!stored_to_temps
) {
4393 isel_err(instr
->src
[1].ssa
->parent_instr
, "Unimplemented output offset instruction");
4396 } else if (ctx
->stage
== vertex_es
||
4397 ctx
->stage
== vertex_ls
||
4398 ctx
->stage
== tess_eval_es
||
4399 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4400 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4401 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4402 visit_store_ls_or_es_output(ctx
, instr
);
4403 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4404 visit_store_tcs_output(ctx
, instr
, false);
4406 unreachable("Shader stage not implemented");
4410 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4412 visit_load_tcs_output(ctx
, instr
, false);
4415 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4417 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4418 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4420 Builder
bld(ctx
->program
, ctx
->block
);
4422 if (dst
.regClass() == v2b
) {
4423 if (ctx
->program
->has_16bank_lds
) {
4424 assert(ctx
->options
->chip_class
<= GFX8
);
4425 Builder::Result interp_p1
=
4426 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4427 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4428 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4429 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4430 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4431 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4433 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4435 if (ctx
->options
->chip_class
== GFX8
)
4436 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4438 Builder::Result interp_p1
=
4439 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4440 coord1
, bld
.m0(prim_mask
), idx
, component
);
4441 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4442 interp_p1
, idx
, component
);
4445 Builder::Result interp_p1
=
4446 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4447 bld
.m0(prim_mask
), idx
, component
);
4449 if (ctx
->program
->has_16bank_lds
)
4450 interp_p1
.instr
->operands
[0].setLateKill(true);
4452 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4453 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4457 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4459 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4460 for (unsigned i
= 0; i
< num_components
; i
++)
4461 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4462 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4463 assert(num_components
== 4);
4464 Builder
bld(ctx
->program
, ctx
->block
);
4465 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4468 for (Operand
& op
: vec
->operands
)
4469 op
= op
.isUndefined() ? Operand(0u) : op
;
4471 vec
->definitions
[0] = Definition(dst
);
4472 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4473 emit_split_vector(ctx
, dst
, num_components
);
4477 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4479 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4480 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4481 unsigned idx
= nir_intrinsic_base(instr
);
4482 unsigned component
= nir_intrinsic_component(instr
);
4483 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4485 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4487 assert(offset
->u32
== 0);
4489 /* the lower 15bit of the prim_mask contain the offset into LDS
4490 * while the upper bits contain the number of prims */
4491 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4492 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4493 Builder
bld(ctx
->program
, ctx
->block
);
4494 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4495 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4496 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4497 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4498 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4501 if (instr
->dest
.ssa
.num_components
== 1) {
4502 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4504 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4505 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4507 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4508 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4509 vec
->operands
[i
] = Operand(tmp
);
4511 vec
->definitions
[0] = Definition(dst
);
4512 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4516 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4517 unsigned offset
, unsigned stride
, unsigned channels
)
4519 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4520 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4522 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4523 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4526 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4527 unsigned offset
, unsigned stride
, unsigned *channels
)
4529 if (!vtx_info
->chan_byte_size
) {
4530 *channels
= vtx_info
->num_channels
;
4531 return vtx_info
->chan_format
;
4534 unsigned num_channels
= *channels
;
4535 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4536 unsigned new_channels
= num_channels
+ 1;
4537 /* first, assume more loads is worse and try using a larger data format */
4538 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4540 /* don't make the attribute potentially out-of-bounds */
4541 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4545 if (new_channels
== 5) {
4546 /* then try decreasing load size (at the cost of more loads) */
4547 new_channels
= *channels
;
4548 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4552 if (new_channels
< *channels
)
4553 *channels
= new_channels
;
4554 num_channels
= new_channels
;
4557 switch (vtx_info
->chan_format
) {
4558 case V_008F0C_BUF_DATA_FORMAT_8
:
4559 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4560 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4561 case V_008F0C_BUF_DATA_FORMAT_16
:
4562 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4563 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4564 case V_008F0C_BUF_DATA_FORMAT_32
:
4565 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4566 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4568 unreachable("shouldn't reach here");
4569 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4572 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4573 * so we may need to fix it up. */
4574 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4576 Builder
bld(ctx
->program
, ctx
->block
);
4578 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4579 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4581 /* For the integer-like cases, do a natural sign extension.
4583 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4584 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4587 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4588 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4590 /* Convert back to the right type. */
4591 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4592 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4593 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4594 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4595 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4596 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4602 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4604 Builder
bld(ctx
->program
, ctx
->block
);
4605 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4606 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4608 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4609 if (off_instr
->type
!= nir_instr_type_load_const
) {
4610 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4612 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4614 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4616 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4617 unsigned component
= nir_intrinsic_component(instr
);
4618 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4619 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4620 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4621 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4622 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4624 unsigned dfmt
= attrib_format
& 0xf;
4625 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4626 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4628 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4629 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4630 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4631 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4633 num_channels
= MAX2(num_channels
, 3);
4635 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4636 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4639 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4640 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4641 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4643 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4645 Temp divided
= bld
.tmp(v1
);
4646 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4647 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4649 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4652 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4655 index
= bld
.vadd32(bld
.def(v1
),
4656 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4657 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4660 Temp channels
[num_channels
];
4661 unsigned channel_start
= 0;
4662 bool direct_fetch
= false;
4664 /* skip unused channels at the start */
4665 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4666 channel_start
= ffs(mask
) - 1;
4667 for (unsigned i
= 0; i
< channel_start
; i
++)
4668 channels
[i
] = Temp(0, s1
);
4669 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4670 num_channels
= 3 - (ffs(mask
) - 1);
4674 while (channel_start
< num_channels
) {
4675 unsigned fetch_component
= num_channels
- channel_start
;
4676 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4677 bool expanded
= false;
4679 /* use MUBUF when possible to avoid possible alignment issues */
4680 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4681 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4682 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4683 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4684 vtx_info
->chan_byte_size
== 4;
4685 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4687 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4689 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4690 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4691 fetch_component
= 4;
4696 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4698 Temp fetch_index
= index
;
4699 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4700 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4701 fetch_offset
= fetch_offset
% attrib_stride
;
4704 Operand
soffset(0u);
4705 if (fetch_offset
>= 4096) {
4706 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4707 fetch_offset
%= 4096;
4711 switch (fetch_bytes
) {
4713 assert(!use_mubuf
&& bitsize
== 16);
4714 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4717 if (bitsize
== 16) {
4719 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4721 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4725 assert(!use_mubuf
&& bitsize
== 16);
4726 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4729 if (bitsize
== 16) {
4731 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4733 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4737 assert(ctx
->options
->chip_class
>= GFX7
||
4738 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4739 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4742 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4745 unreachable("Unimplemented load_input vector size");
4749 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4750 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4751 num_channels
<= 3)) {
4752 direct_fetch
= true;
4755 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4760 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4761 fetch_offset
, false, false, true).instr
;
4764 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4765 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4768 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4770 if (fetch_component
== 1) {
4771 channels
[channel_start
] = fetch_dst
;
4773 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4774 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4775 bitsize
== 16 ? v2b
: v1
);
4778 channel_start
+= fetch_component
;
4781 if (!direct_fetch
) {
4782 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4783 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4785 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4786 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4787 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4789 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4790 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4791 unsigned num_temp
= 0;
4792 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4793 unsigned idx
= i
+ component
;
4794 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4795 Temp channel
= channels
[swizzle
[idx
]];
4796 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4797 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4798 vec
->operands
[i
] = Operand(channel
);
4802 } else if (is_float
&& idx
== 3) {
4803 vec
->operands
[i
] = Operand(0x3f800000u
);
4804 } else if (!is_float
&& idx
== 3) {
4805 vec
->operands
[i
] = Operand(1u);
4807 vec
->operands
[i
] = Operand(0u);
4810 vec
->definitions
[0] = Definition(dst
);
4811 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4812 emit_split_vector(ctx
, dst
, dst
.size());
4814 if (num_temp
== dst
.size())
4815 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4817 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4818 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4819 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4820 if (off_instr
->type
!= nir_instr_type_load_const
||
4821 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4822 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4825 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4826 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4828 assert(offset
->u32
== 0);
4830 /* the lower 15bit of the prim_mask contain the offset into LDS
4831 * while the upper bits contain the number of prims */
4832 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4833 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4834 Builder
bld(ctx
->program
, ctx
->block
);
4835 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4836 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4837 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4838 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4839 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4842 unsigned idx
= nir_intrinsic_base(instr
);
4843 unsigned component
= nir_intrinsic_component(instr
);
4844 unsigned vertex_id
= 2; /* P0 */
4846 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4847 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4848 switch (src0
->u32
) {
4850 vertex_id
= 2; /* P0 */
4853 vertex_id
= 0; /* P10 */
4856 vertex_id
= 1; /* P20 */
4859 unreachable("invalid vertex index");
4863 if (dst
.size() == 1) {
4864 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4866 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4867 for (unsigned i
= 0; i
< dst
.size(); i
++)
4868 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4869 vec
->definitions
[0] = Definition(dst
);
4870 bld
.insert(std::move(vec
));
4873 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4874 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4875 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4876 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4877 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4879 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4881 unreachable("Shader stage not implemented");
4885 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4887 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4889 Builder
bld(ctx
->program
, ctx
->block
);
4890 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4893 if (!nir_src_is_const(*vertex_src
)) {
4894 /* better code could be created, but this case probably doesn't happen
4895 * much in practice */
4896 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4897 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4900 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4901 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4903 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4905 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4908 if (vertex_offset
.id()) {
4909 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4910 Operand(i
), indirect_vertex
);
4911 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4913 vertex_offset
= elem
;
4917 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4918 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4920 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4921 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4922 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4923 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4924 Operand((vertex
% 2u) * 16u), Operand(16u));
4926 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4929 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4930 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4931 return offset_mul(ctx
, offs
, 4u);
4934 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4936 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4938 Builder
bld(ctx
->program
, ctx
->block
);
4939 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4940 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4942 if (ctx
->stage
== geometry_gs
) {
4943 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4944 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4945 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4946 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4947 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4948 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4949 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4951 unreachable("Unsupported GS stage.");
4955 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4957 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4959 Builder
bld(ctx
->program
, ctx
->block
);
4960 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4962 if (load_input_from_temps(ctx
, instr
, dst
))
4965 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4966 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4967 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4969 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4972 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4974 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4976 Builder
bld(ctx
->program
, ctx
->block
);
4978 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4979 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4980 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4982 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4983 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4985 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4988 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4990 switch (ctx
->shader
->info
.stage
) {
4991 case MESA_SHADER_GEOMETRY
:
4992 visit_load_gs_per_vertex_input(ctx
, instr
);
4994 case MESA_SHADER_TESS_CTRL
:
4995 visit_load_tcs_per_vertex_input(ctx
, instr
);
4997 case MESA_SHADER_TESS_EVAL
:
4998 visit_load_tes_per_vertex_input(ctx
, instr
);
5001 unreachable("Unimplemented shader stage");
5005 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5007 visit_load_tcs_output(ctx
, instr
, true);
5010 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5012 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5013 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5015 visit_store_tcs_output(ctx
, instr
, true);
5018 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5020 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5022 Builder
bld(ctx
->program
, ctx
->block
);
5023 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5025 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5026 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5029 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5030 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5031 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5032 tes_w
= Operand(tmp
);
5035 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5036 emit_split_vector(ctx
, tess_coord
, 3);
5039 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5041 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5042 Builder
bld(ctx
->program
, ctx
->block
);
5043 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5044 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5045 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5048 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5052 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5054 Builder
bld(ctx
->program
, ctx
->block
);
5055 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5056 if (!nir_dest_is_divergent(instr
->dest
))
5057 index
= bld
.as_uniform(index
);
5058 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5059 unsigned binding
= nir_intrinsic_binding(instr
);
5062 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5063 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5064 unsigned offset
= layout
->binding
[binding
].offset
;
5066 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5067 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5068 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5069 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5070 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5073 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5074 stride
= layout
->binding
[binding
].size
;
5077 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5078 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5080 if (nir_const_index
) {
5081 const_index
= const_index
* stride
;
5082 } else if (index
.type() == RegType::vgpr
) {
5083 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5084 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5086 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5090 if (nir_const_index
) {
5091 const_index
= const_index
+ offset
;
5092 } else if (index
.type() == RegType::vgpr
) {
5093 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5095 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5099 if (nir_const_index
&& const_index
== 0) {
5101 } else if (index
.type() == RegType::vgpr
) {
5102 index
= bld
.vadd32(bld
.def(v1
),
5103 nir_const_index
? Operand(const_index
) : Operand(index
),
5106 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5107 nir_const_index
? Operand(const_index
) : Operand(index
),
5111 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5114 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5115 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5116 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5118 Builder
bld(ctx
->program
, ctx
->block
);
5120 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5122 offset
= bld
.as_uniform(offset
);
5124 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5127 info
.align_mul
= align_mul
;
5128 info
.align_offset
= align_offset
;
5130 emit_smem_load(ctx
, bld
, &info
);
5132 emit_mubuf_load(ctx
, bld
, &info
);
5135 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5137 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5138 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5140 Builder
bld(ctx
->program
, ctx
->block
);
5142 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5143 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5144 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5145 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5147 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5148 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5149 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5150 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5151 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5152 if (ctx
->options
->chip_class
>= GFX10
) {
5153 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5154 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5155 S_008F0C_RESOURCE_LEVEL(1);
5157 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5158 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5160 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5161 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5162 Operand(0xFFFFFFFFu
),
5163 Operand(desc_type
));
5164 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5165 rsrc
, upper_dwords
);
5167 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5168 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5170 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5171 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5172 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5175 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5177 Builder
bld(ctx
->program
, ctx
->block
);
5178 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5179 unsigned offset
= nir_intrinsic_base(instr
);
5180 unsigned count
= instr
->dest
.ssa
.num_components
;
5181 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5183 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5184 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5185 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5186 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5187 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5188 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5189 for (unsigned i
= 0; i
< count
; ++i
) {
5190 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5191 vec
->operands
[i
] = Operand
{elems
[i
]};
5193 vec
->definitions
[0] = Definition(dst
);
5194 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5195 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5200 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5201 if (offset
!= 0) // TODO check if index != 0 as well
5202 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5203 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5206 bool aligned
= true;
5208 if (instr
->dest
.ssa
.bit_size
== 8) {
5209 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5210 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5212 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5213 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5214 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5216 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5221 switch (vec
.size()) {
5223 op
= aco_opcode::s_load_dword
;
5226 op
= aco_opcode::s_load_dwordx2
;
5232 op
= aco_opcode::s_load_dwordx4
;
5238 op
= aco_opcode::s_load_dwordx8
;
5241 unreachable("unimplemented or forbidden load_push_constant.");
5244 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5247 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5248 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5253 emit_split_vector(ctx
, vec
, 4);
5254 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5255 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5256 emit_extract_vector(ctx
, vec
, 0, rc
),
5257 emit_extract_vector(ctx
, vec
, 1, rc
),
5258 emit_extract_vector(ctx
, vec
, 2, rc
));
5261 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5264 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5266 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5268 Builder
bld(ctx
->program
, ctx
->block
);
5270 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5271 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5272 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5273 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5274 if (ctx
->options
->chip_class
>= GFX10
) {
5275 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5276 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5277 S_008F0C_RESOURCE_LEVEL(1);
5279 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5283 unsigned base
= nir_intrinsic_base(instr
);
5284 unsigned range
= nir_intrinsic_range(instr
);
5286 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5287 if (base
&& offset
.type() == RegType::sgpr
)
5288 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5289 else if (base
&& offset
.type() == RegType::vgpr
)
5290 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5292 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5293 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5294 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5295 Operand(desc_type
));
5296 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5297 // TODO: get alignment information for subdword constants
5298 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5301 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5303 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5304 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5306 ctx
->program
->needs_exact
= true;
5308 // TODO: optimize uniform conditions
5309 Builder
bld(ctx
->program
, ctx
->block
);
5310 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5311 assert(src
.regClass() == bld
.lm
);
5312 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5313 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5314 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5318 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5320 Builder
bld(ctx
->program
, ctx
->block
);
5322 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5323 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5325 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5326 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5328 if (ctx
->block
->loop_nest_depth
&&
5329 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5330 /* we handle discards the same way as jump instructions */
5331 append_logical_end(ctx
->block
);
5333 /* in loops, discard behaves like break */
5334 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5335 ctx
->block
->kind
|= block_kind_discard
;
5338 /* uniform discard - loop ends here */
5339 assert(nir_instr_is_last(&instr
->instr
));
5340 ctx
->block
->kind
|= block_kind_uniform
;
5341 ctx
->cf_info
.has_branch
= true;
5342 bld
.branch(aco_opcode::p_branch
);
5343 add_linear_edge(ctx
->block
->index
, linear_target
);
5347 /* we add a break right behind the discard() instructions */
5348 ctx
->block
->kind
|= block_kind_break
;
5349 unsigned idx
= ctx
->block
->index
;
5351 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5352 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5354 /* remove critical edges from linear CFG */
5355 bld
.branch(aco_opcode::p_branch
);
5356 Block
* break_block
= ctx
->program
->create_and_insert_block();
5357 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5358 break_block
->kind
|= block_kind_uniform
;
5359 add_linear_edge(idx
, break_block
);
5360 add_linear_edge(break_block
->index
, linear_target
);
5361 bld
.reset(break_block
);
5362 bld
.branch(aco_opcode::p_branch
);
5364 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5365 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5366 add_linear_edge(idx
, continue_block
);
5367 append_logical_start(continue_block
);
5368 ctx
->block
= continue_block
;
5373 /* it can currently happen that NIR doesn't remove the unreachable code */
5374 if (!nir_instr_is_last(&instr
->instr
)) {
5375 ctx
->program
->needs_exact
= true;
5376 /* save exec somewhere temporarily so that it doesn't get
5377 * overwritten before the discard from outer exec masks */
5378 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5379 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5380 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5384 /* This condition is incorrect for uniformly branched discards in a loop
5385 * predicated by a divergent condition, but the above code catches that case
5386 * and the discard would end up turning into a discard_if.
5396 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5397 /* program just ends here */
5398 ctx
->block
->kind
|= block_kind_uniform
;
5399 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5400 0 /* enabled mask */, 9 /* dest */,
5401 false /* compressed */, true/* done */, true /* valid mask */);
5402 bld
.sopp(aco_opcode::s_endpgm
);
5403 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5405 ctx
->block
->kind
|= block_kind_discard
;
5406 /* branch and linear edge is added by visit_if() */
5410 enum aco_descriptor_type
{
5421 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5422 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5424 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5425 return dim
== ac_image_cube
||
5426 dim
== ac_image_1darray
||
5427 dim
== ac_image_2darray
||
5428 dim
== ac_image_2darraymsaa
;
5431 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5432 enum aco_descriptor_type desc_type
,
5433 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5435 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5436 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5437 if (it != ctx->tex_desc.end())
5440 Temp index
= Temp();
5441 bool index_set
= false;
5442 unsigned constant_index
= 0;
5443 unsigned descriptor_set
;
5444 unsigned base_index
;
5445 Builder
bld(ctx
->program
, ctx
->block
);
5448 assert(tex_instr
&& !image
);
5450 base_index
= tex_instr
->sampler_index
;
5452 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5453 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5457 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5458 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5460 constant_index
+= array_size
* const_value
->u32
;
5462 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5463 if (indirect
.type() == RegType::vgpr
)
5464 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5466 if (array_size
!= 1)
5467 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5473 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5477 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5479 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5480 base_index
= deref_instr
->var
->data
.binding
;
5483 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5484 list
= convert_pointer_to_64_bit(ctx
, list
);
5486 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5487 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5488 unsigned offset
= binding
->offset
;
5489 unsigned stride
= binding
->size
;
5493 assert(base_index
< layout
->binding_count
);
5495 switch (desc_type
) {
5496 case ACO_DESC_IMAGE
:
5498 opcode
= aco_opcode::s_load_dwordx8
;
5500 case ACO_DESC_FMASK
:
5502 opcode
= aco_opcode::s_load_dwordx8
;
5505 case ACO_DESC_SAMPLER
:
5507 opcode
= aco_opcode::s_load_dwordx4
;
5508 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5509 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5511 case ACO_DESC_BUFFER
:
5513 opcode
= aco_opcode::s_load_dwordx4
;
5515 case ACO_DESC_PLANE_0
:
5516 case ACO_DESC_PLANE_1
:
5518 opcode
= aco_opcode::s_load_dwordx8
;
5519 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5521 case ACO_DESC_PLANE_2
:
5523 opcode
= aco_opcode::s_load_dwordx4
;
5527 unreachable("invalid desc_type\n");
5530 offset
+= constant_index
* stride
;
5532 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5533 (!index_set
|| binding
->immutable_samplers_equal
)) {
5534 if (binding
->immutable_samplers_equal
)
5537 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5539 Operand(samplers
[constant_index
* 4 + 0]),
5540 Operand(samplers
[constant_index
* 4 + 1]),
5541 Operand(samplers
[constant_index
* 4 + 2]),
5542 Operand(samplers
[constant_index
* 4 + 3]));
5547 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5549 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5550 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5553 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5555 if (desc_type
== ACO_DESC_PLANE_2
) {
5557 for (unsigned i
= 0; i
< 8; i
++)
5558 components
[i
] = bld
.tmp(s1
);
5559 bld
.pseudo(aco_opcode::p_split_vector
,
5560 Definition(components
[0]),
5561 Definition(components
[1]),
5562 Definition(components
[2]),
5563 Definition(components
[3]),
5566 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5567 bld
.pseudo(aco_opcode::p_split_vector
,
5568 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5569 Definition(components
[4]),
5570 Definition(components
[5]),
5571 Definition(components
[6]),
5572 Definition(components
[7]),
5575 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5576 components
[0], components
[1], components
[2], components
[3],
5577 components
[4], components
[5], components
[6], components
[7]);
5583 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5586 case GLSL_SAMPLER_DIM_BUF
:
5588 case GLSL_SAMPLER_DIM_1D
:
5589 return array
? 2 : 1;
5590 case GLSL_SAMPLER_DIM_2D
:
5591 return array
? 3 : 2;
5592 case GLSL_SAMPLER_DIM_MS
:
5593 return array
? 4 : 3;
5594 case GLSL_SAMPLER_DIM_3D
:
5595 case GLSL_SAMPLER_DIM_CUBE
:
5597 case GLSL_SAMPLER_DIM_RECT
:
5598 case GLSL_SAMPLER_DIM_SUBPASS
:
5600 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5609 /* Adjust the sample index according to FMASK.
5611 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5612 * which is the identity mapping. Each nibble says which physical sample
5613 * should be fetched to get that sample.
5615 * For example, 0x11111100 means there are only 2 samples stored and
5616 * the second sample covers 3/4 of the pixel. When reading samples 0
5617 * and 1, return physical sample 0 (determined by the first two 0s
5618 * in FMASK), otherwise return physical sample 1.
5620 * The sample index should be adjusted as follows:
5621 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5623 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5625 Builder
bld(ctx
->program
, ctx
->block
);
5626 Temp fmask
= bld
.tmp(v1
);
5627 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5628 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5631 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5632 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5633 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5634 load
->operands
[0] = Operand(fmask_desc_ptr
);
5635 load
->operands
[1] = Operand(s4
); /* no sampler */
5636 load
->operands
[2] = Operand(coord
);
5637 load
->definitions
[0] = Definition(fmask
);
5644 ctx
->block
->instructions
.emplace_back(std::move(load
));
5646 Operand sample_index4
;
5647 if (sample_index
.isConstant()) {
5648 if (sample_index
.constantValue() < 16) {
5649 sample_index4
= Operand(sample_index
.constantValue() << 2);
5651 sample_index4
= Operand(0u);
5653 } else if (sample_index
.regClass() == s1
) {
5654 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5656 assert(sample_index
.regClass() == v1
);
5657 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5661 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5662 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5663 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5664 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5666 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5668 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5669 * resource descriptor is 0 (invalid),
5671 Temp compare
= bld
.tmp(bld
.lm
);
5672 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5673 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5675 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5677 /* Replace the MSAA sample index. */
5678 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5681 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5684 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5685 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5686 bool is_array
= glsl_sampler_type_is_array(type
);
5687 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5688 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5689 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5690 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5691 int count
= image_type_to_components_count(dim
, is_array
);
5692 std::vector
<Temp
> coords(count
);
5693 Builder
bld(ctx
->program
, ctx
->block
);
5697 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5698 /* get sample index */
5699 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5700 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5701 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5702 std::vector
<Temp
> fmask_load_address
;
5703 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5704 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5706 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5707 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5709 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5714 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5715 coords
.resize(coords
.size() + 1);
5716 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5718 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5720 for (int i
= 0; i
< count
; i
++)
5721 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5724 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5725 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5726 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5727 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5730 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5733 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5734 for (unsigned i
= 0; i
< coords
.size(); i
++)
5735 vec
->operands
[i
] = Operand(coords
[i
]);
5736 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5737 vec
->definitions
[0] = Definition(res
);
5738 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5743 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5745 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5746 if (semantics
& semantic_atomicrmw
)
5747 return memory_sync_info(storage
, semantics
);
5749 unsigned access
= nir_intrinsic_access(instr
);
5751 if (access
& ACCESS_VOLATILE
)
5752 semantics
|= semantic_volatile
;
5753 if (access
& ACCESS_CAN_REORDER
)
5754 semantics
|= semantic_can_reorder
| semantic_private
;
5756 return memory_sync_info(storage
, semantics
);
5759 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5761 Builder
bld(ctx
->program
, ctx
->block
);
5762 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5763 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5764 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5765 bool is_array
= glsl_sampler_type_is_array(type
);
5766 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5768 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5769 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5771 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5772 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5773 unsigned num_channels
= util_last_bit(mask
);
5774 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5775 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5778 switch (num_channels
) {
5780 opcode
= aco_opcode::buffer_load_format_x
;
5783 opcode
= aco_opcode::buffer_load_format_xy
;
5786 opcode
= aco_opcode::buffer_load_format_xyz
;
5789 opcode
= aco_opcode::buffer_load_format_xyzw
;
5792 unreachable(">4 channel buffer image load");
5794 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5795 load
->operands
[0] = Operand(rsrc
);
5796 load
->operands
[1] = Operand(vindex
);
5797 load
->operands
[2] = Operand((uint32_t) 0);
5799 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5802 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5803 load
->definitions
[0] = Definition(tmp
);
5805 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5806 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5808 ctx
->block
->instructions
.emplace_back(std::move(load
));
5810 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5814 Temp coords
= get_image_coords(ctx
, instr
, type
);
5815 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5817 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5818 unsigned num_components
= util_bitcount(dmask
);
5820 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5823 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5825 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5826 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5828 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5829 load
->operands
[0] = Operand(resource
);
5830 load
->operands
[1] = Operand(s4
); /* no sampler */
5831 load
->operands
[2] = Operand(coords
);
5832 load
->definitions
[0] = Definition(tmp
);
5833 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5834 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5835 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5836 load
->dmask
= dmask
;
5838 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5840 ctx
->block
->instructions
.emplace_back(std::move(load
));
5842 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5846 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5848 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5849 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5850 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5851 bool is_array
= glsl_sampler_type_is_array(type
);
5852 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5854 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5855 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5856 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5858 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5859 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5860 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5862 switch (data
.size()) {
5864 opcode
= aco_opcode::buffer_store_format_x
;
5867 opcode
= aco_opcode::buffer_store_format_xy
;
5870 opcode
= aco_opcode::buffer_store_format_xyz
;
5873 opcode
= aco_opcode::buffer_store_format_xyzw
;
5876 unreachable(">4 channel buffer image store");
5878 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5879 store
->operands
[0] = Operand(rsrc
);
5880 store
->operands
[1] = Operand(vindex
);
5881 store
->operands
[2] = Operand((uint32_t) 0);
5882 store
->operands
[3] = Operand(data
);
5883 store
->idxen
= true;
5886 store
->disable_wqm
= true;
5888 ctx
->program
->needs_exact
= true;
5889 ctx
->block
->instructions
.emplace_back(std::move(store
));
5893 assert(data
.type() == RegType::vgpr
);
5894 Temp coords
= get_image_coords(ctx
, instr
, type
);
5895 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5897 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5898 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5900 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5901 store
->operands
[0] = Operand(resource
);
5902 store
->operands
[1] = Operand(data
);
5903 store
->operands
[2] = Operand(coords
);
5906 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5907 store
->dmask
= (1 << data
.size()) - 1;
5909 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5910 store
->disable_wqm
= true;
5912 ctx
->program
->needs_exact
= true;
5913 ctx
->block
->instructions
.emplace_back(std::move(store
));
5917 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5919 /* return the previous value if dest is ever used */
5920 bool return_previous
= false;
5921 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5922 return_previous
= true;
5925 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5926 return_previous
= true;
5930 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5931 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5932 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5933 bool is_array
= glsl_sampler_type_is_array(type
);
5934 Builder
bld(ctx
->program
, ctx
->block
);
5936 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5937 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5939 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5940 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5942 aco_opcode buf_op
, image_op
;
5943 switch (instr
->intrinsic
) {
5944 case nir_intrinsic_image_deref_atomic_add
:
5945 buf_op
= aco_opcode::buffer_atomic_add
;
5946 image_op
= aco_opcode::image_atomic_add
;
5948 case nir_intrinsic_image_deref_atomic_umin
:
5949 buf_op
= aco_opcode::buffer_atomic_umin
;
5950 image_op
= aco_opcode::image_atomic_umin
;
5952 case nir_intrinsic_image_deref_atomic_imin
:
5953 buf_op
= aco_opcode::buffer_atomic_smin
;
5954 image_op
= aco_opcode::image_atomic_smin
;
5956 case nir_intrinsic_image_deref_atomic_umax
:
5957 buf_op
= aco_opcode::buffer_atomic_umax
;
5958 image_op
= aco_opcode::image_atomic_umax
;
5960 case nir_intrinsic_image_deref_atomic_imax
:
5961 buf_op
= aco_opcode::buffer_atomic_smax
;
5962 image_op
= aco_opcode::image_atomic_smax
;
5964 case nir_intrinsic_image_deref_atomic_and
:
5965 buf_op
= aco_opcode::buffer_atomic_and
;
5966 image_op
= aco_opcode::image_atomic_and
;
5968 case nir_intrinsic_image_deref_atomic_or
:
5969 buf_op
= aco_opcode::buffer_atomic_or
;
5970 image_op
= aco_opcode::image_atomic_or
;
5972 case nir_intrinsic_image_deref_atomic_xor
:
5973 buf_op
= aco_opcode::buffer_atomic_xor
;
5974 image_op
= aco_opcode::image_atomic_xor
;
5976 case nir_intrinsic_image_deref_atomic_exchange
:
5977 buf_op
= aco_opcode::buffer_atomic_swap
;
5978 image_op
= aco_opcode::image_atomic_swap
;
5980 case nir_intrinsic_image_deref_atomic_comp_swap
:
5981 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5982 image_op
= aco_opcode::image_atomic_cmpswap
;
5985 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5988 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5989 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
5991 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5992 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5993 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5994 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5995 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5996 mubuf
->operands
[0] = Operand(resource
);
5997 mubuf
->operands
[1] = Operand(vindex
);
5998 mubuf
->operands
[2] = Operand((uint32_t)0);
5999 mubuf
->operands
[3] = Operand(data
);
6000 if (return_previous
)
6001 mubuf
->definitions
[0] = Definition(dst
);
6003 mubuf
->idxen
= true;
6004 mubuf
->glc
= return_previous
;
6005 mubuf
->dlc
= false; /* Not needed for atomics */
6006 mubuf
->disable_wqm
= true;
6008 ctx
->program
->needs_exact
= true;
6009 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6013 Temp coords
= get_image_coords(ctx
, instr
, type
);
6014 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6015 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6016 mimg
->operands
[0] = Operand(resource
);
6017 mimg
->operands
[1] = Operand(data
);
6018 mimg
->operands
[2] = Operand(coords
);
6019 if (return_previous
)
6020 mimg
->definitions
[0] = Definition(dst
);
6021 mimg
->glc
= return_previous
;
6022 mimg
->dlc
= false; /* Not needed for atomics */
6023 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6024 mimg
->dmask
= (1 << data
.size()) - 1;
6026 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6027 mimg
->disable_wqm
= true;
6029 ctx
->program
->needs_exact
= true;
6030 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6034 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6036 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6037 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6038 Builder
bld(ctx
->program
, ctx
->block
);
6040 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6042 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6043 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6045 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6046 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6048 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6049 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6051 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6052 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6053 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6054 if (dst
.type() == RegType::vgpr
)
6055 bld
.copy(Definition(dst
), shr_dst
);
6057 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6059 emit_extract_vector(ctx
, desc
, 2, dst
);
6063 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6065 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6066 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6067 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6068 bool is_array
= glsl_sampler_type_is_array(type
);
6069 Builder
bld(ctx
->program
, ctx
->block
);
6071 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6072 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6073 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6077 assert(nir_src_as_uint(instr
->src
[1]) == 0);
6078 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6081 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6083 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6085 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6086 mimg
->operands
[0] = Operand(resource
);
6087 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6088 mimg
->operands
[2] = Operand(lod
);
6089 uint8_t& dmask
= mimg
->dmask
;
6090 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6091 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6092 mimg
->da
= glsl_sampler_type_is_array(type
);
6093 Definition
& def
= mimg
->definitions
[0];
6094 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6096 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6097 glsl_sampler_type_is_array(type
)) {
6099 assert(instr
->dest
.ssa
.num_components
== 3);
6100 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6101 def
= Definition(tmp
);
6102 emit_split_vector(ctx
, tmp
, 3);
6104 /* divide 3rd value by 6 by multiplying with magic number */
6105 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6106 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6108 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6109 emit_extract_vector(ctx
, tmp
, 0, v1
),
6110 emit_extract_vector(ctx
, tmp
, 1, v1
),
6113 } else if (ctx
->options
->chip_class
== GFX9
&&
6114 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6115 glsl_sampler_type_is_array(type
)) {
6116 assert(instr
->dest
.ssa
.num_components
== 2);
6117 def
= Definition(dst
);
6120 def
= Definition(dst
);
6123 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6126 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6128 Builder
bld(ctx
->program
, ctx
->block
);
6129 unsigned num_components
= instr
->num_components
;
6131 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6132 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6133 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6135 unsigned access
= nir_intrinsic_access(instr
);
6136 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6137 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6139 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6140 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6141 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6143 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6144 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6146 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6147 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6148 get_memory_sync_info(instr
, storage_buffer
, 0));
6151 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6153 Builder
bld(ctx
->program
, ctx
->block
);
6154 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6155 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6156 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6157 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6159 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6160 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6162 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6163 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6164 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6165 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6166 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6168 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6170 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6171 ctx
->options
->chip_class
>= GFX8
&&
6172 ctx
->options
->chip_class
< GFX10_3
&&
6173 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6176 offset
= bld
.as_uniform(offset
);
6177 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6179 unsigned write_count
= 0;
6180 Temp write_datas
[32];
6181 unsigned offsets
[32];
6182 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6183 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6185 for (unsigned i
= 0; i
< write_count
; i
++) {
6186 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6187 if (smem
&& ctx
->stage
== fragment_fs
)
6188 op
= aco_opcode::p_fs_buffer_store_smem
;
6191 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6192 store
->operands
[0] = Operand(rsrc
);
6194 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6195 offset
, Operand(offsets
[i
]));
6196 store
->operands
[1] = Operand(off
);
6198 store
->operands
[1] = Operand(offset
);
6200 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6201 store
->operands
[1].setFixed(m0
);
6202 store
->operands
[2] = Operand(write_datas
[i
]);
6205 store
->disable_wqm
= true;
6207 ctx
->block
->instructions
.emplace_back(std::move(store
));
6208 ctx
->program
->wb_smem_l1_on_end
= true;
6209 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6210 ctx
->block
->kind
|= block_kind_needs_lowering
;
6211 ctx
->program
->needs_exact
= true;
6214 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6215 store
->operands
[0] = Operand(rsrc
);
6216 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6217 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6218 store
->operands
[3] = Operand(write_datas
[i
]);
6219 store
->offset
= offsets
[i
];
6220 store
->offen
= (offset
.type() == RegType::vgpr
);
6223 store
->disable_wqm
= true;
6225 ctx
->program
->needs_exact
= true;
6226 ctx
->block
->instructions
.emplace_back(std::move(store
));
6231 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6233 /* return the previous value if dest is ever used */
6234 bool return_previous
= false;
6235 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6236 return_previous
= true;
6239 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6240 return_previous
= true;
6244 Builder
bld(ctx
->program
, ctx
->block
);
6245 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6247 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6248 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6249 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6251 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6252 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6253 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6255 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6257 aco_opcode op32
, op64
;
6258 switch (instr
->intrinsic
) {
6259 case nir_intrinsic_ssbo_atomic_add
:
6260 op32
= aco_opcode::buffer_atomic_add
;
6261 op64
= aco_opcode::buffer_atomic_add_x2
;
6263 case nir_intrinsic_ssbo_atomic_imin
:
6264 op32
= aco_opcode::buffer_atomic_smin
;
6265 op64
= aco_opcode::buffer_atomic_smin_x2
;
6267 case nir_intrinsic_ssbo_atomic_umin
:
6268 op32
= aco_opcode::buffer_atomic_umin
;
6269 op64
= aco_opcode::buffer_atomic_umin_x2
;
6271 case nir_intrinsic_ssbo_atomic_imax
:
6272 op32
= aco_opcode::buffer_atomic_smax
;
6273 op64
= aco_opcode::buffer_atomic_smax_x2
;
6275 case nir_intrinsic_ssbo_atomic_umax
:
6276 op32
= aco_opcode::buffer_atomic_umax
;
6277 op64
= aco_opcode::buffer_atomic_umax_x2
;
6279 case nir_intrinsic_ssbo_atomic_and
:
6280 op32
= aco_opcode::buffer_atomic_and
;
6281 op64
= aco_opcode::buffer_atomic_and_x2
;
6283 case nir_intrinsic_ssbo_atomic_or
:
6284 op32
= aco_opcode::buffer_atomic_or
;
6285 op64
= aco_opcode::buffer_atomic_or_x2
;
6287 case nir_intrinsic_ssbo_atomic_xor
:
6288 op32
= aco_opcode::buffer_atomic_xor
;
6289 op64
= aco_opcode::buffer_atomic_xor_x2
;
6291 case nir_intrinsic_ssbo_atomic_exchange
:
6292 op32
= aco_opcode::buffer_atomic_swap
;
6293 op64
= aco_opcode::buffer_atomic_swap_x2
;
6295 case nir_intrinsic_ssbo_atomic_comp_swap
:
6296 op32
= aco_opcode::buffer_atomic_cmpswap
;
6297 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6300 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6302 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6303 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6304 mubuf
->operands
[0] = Operand(rsrc
);
6305 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6306 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6307 mubuf
->operands
[3] = Operand(data
);
6308 if (return_previous
)
6309 mubuf
->definitions
[0] = Definition(dst
);
6311 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6312 mubuf
->glc
= return_previous
;
6313 mubuf
->dlc
= false; /* Not needed for atomics */
6314 mubuf
->disable_wqm
= true;
6315 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6316 ctx
->program
->needs_exact
= true;
6317 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6320 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6322 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6323 Builder
bld(ctx
->program
, ctx
->block
);
6324 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6325 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6328 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6330 Builder
bld(ctx
->program
, ctx
->block
);
6331 unsigned num_components
= instr
->num_components
;
6332 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6334 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6335 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6336 num_components
, component_size
};
6337 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6338 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6339 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6340 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6341 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6342 * it's safe to use SMEM */
6343 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6344 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6345 emit_global_load(ctx
, bld
, &info
);
6347 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6348 emit_smem_load(ctx
, bld
, &info
);
6352 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6354 Builder
bld(ctx
->program
, ctx
->block
);
6355 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6356 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6358 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6359 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6360 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6361 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6363 if (ctx
->options
->chip_class
>= GFX7
)
6364 addr
= as_vgpr(ctx
, addr
);
6366 unsigned write_count
= 0;
6367 Temp write_datas
[32];
6368 unsigned offsets
[32];
6369 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6370 16, &write_count
, write_datas
, offsets
);
6372 for (unsigned i
= 0; i
< write_count
; i
++) {
6373 if (ctx
->options
->chip_class
>= GFX7
) {
6374 unsigned offset
= offsets
[i
];
6375 Temp store_addr
= addr
;
6376 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6377 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6378 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6379 Temp carry
= bld
.tmp(bld
.lm
);
6380 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6382 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6383 Operand(offset
), addr0
);
6384 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6386 carry
).def(1).setHint(vcc
);
6388 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6393 bool global
= ctx
->options
->chip_class
>= GFX9
;
6395 switch (write_datas
[i
].bytes()) {
6397 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6400 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6403 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6406 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6409 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6412 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6415 unreachable("store_global not implemented for this size.");
6418 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6419 flat
->operands
[0] = Operand(store_addr
);
6420 flat
->operands
[1] = Operand(s1
);
6421 flat
->operands
[2] = Operand(write_datas
[i
]);
6424 flat
->offset
= offset
;
6425 flat
->disable_wqm
= true;
6427 ctx
->program
->needs_exact
= true;
6428 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6430 assert(ctx
->options
->chip_class
== GFX6
);
6432 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6434 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6436 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6437 mubuf
->operands
[0] = Operand(rsrc
);
6438 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6439 mubuf
->operands
[2] = Operand(0u);
6440 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6443 mubuf
->offset
= offsets
[i
];
6444 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6445 mubuf
->disable_wqm
= true;
6447 ctx
->program
->needs_exact
= true;
6448 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6453 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6455 /* return the previous value if dest is ever used */
6456 bool return_previous
= false;
6457 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6458 return_previous
= true;
6461 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6462 return_previous
= true;
6466 Builder
bld(ctx
->program
, ctx
->block
);
6467 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6468 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6470 if (ctx
->options
->chip_class
>= GFX7
)
6471 addr
= as_vgpr(ctx
, addr
);
6473 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6474 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6475 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6477 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6479 aco_opcode op32
, op64
;
6481 if (ctx
->options
->chip_class
>= GFX7
) {
6482 bool global
= ctx
->options
->chip_class
>= GFX9
;
6483 switch (instr
->intrinsic
) {
6484 case nir_intrinsic_global_atomic_add
:
6485 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6486 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6488 case nir_intrinsic_global_atomic_imin
:
6489 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6490 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6492 case nir_intrinsic_global_atomic_umin
:
6493 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6494 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6496 case nir_intrinsic_global_atomic_imax
:
6497 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6498 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6500 case nir_intrinsic_global_atomic_umax
:
6501 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6502 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6504 case nir_intrinsic_global_atomic_and
:
6505 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6506 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6508 case nir_intrinsic_global_atomic_or
:
6509 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6510 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6512 case nir_intrinsic_global_atomic_xor
:
6513 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6514 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6516 case nir_intrinsic_global_atomic_exchange
:
6517 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6518 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6520 case nir_intrinsic_global_atomic_comp_swap
:
6521 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6522 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6525 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6528 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6529 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6530 flat
->operands
[0] = Operand(addr
);
6531 flat
->operands
[1] = Operand(s1
);
6532 flat
->operands
[2] = Operand(data
);
6533 if (return_previous
)
6534 flat
->definitions
[0] = Definition(dst
);
6535 flat
->glc
= return_previous
;
6536 flat
->dlc
= false; /* Not needed for atomics */
6538 flat
->disable_wqm
= true;
6539 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6540 ctx
->program
->needs_exact
= true;
6541 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6543 assert(ctx
->options
->chip_class
== GFX6
);
6545 switch (instr
->intrinsic
) {
6546 case nir_intrinsic_global_atomic_add
:
6547 op32
= aco_opcode::buffer_atomic_add
;
6548 op64
= aco_opcode::buffer_atomic_add_x2
;
6550 case nir_intrinsic_global_atomic_imin
:
6551 op32
= aco_opcode::buffer_atomic_smin
;
6552 op64
= aco_opcode::buffer_atomic_smin_x2
;
6554 case nir_intrinsic_global_atomic_umin
:
6555 op32
= aco_opcode::buffer_atomic_umin
;
6556 op64
= aco_opcode::buffer_atomic_umin_x2
;
6558 case nir_intrinsic_global_atomic_imax
:
6559 op32
= aco_opcode::buffer_atomic_smax
;
6560 op64
= aco_opcode::buffer_atomic_smax_x2
;
6562 case nir_intrinsic_global_atomic_umax
:
6563 op32
= aco_opcode::buffer_atomic_umax
;
6564 op64
= aco_opcode::buffer_atomic_umax_x2
;
6566 case nir_intrinsic_global_atomic_and
:
6567 op32
= aco_opcode::buffer_atomic_and
;
6568 op64
= aco_opcode::buffer_atomic_and_x2
;
6570 case nir_intrinsic_global_atomic_or
:
6571 op32
= aco_opcode::buffer_atomic_or
;
6572 op64
= aco_opcode::buffer_atomic_or_x2
;
6574 case nir_intrinsic_global_atomic_xor
:
6575 op32
= aco_opcode::buffer_atomic_xor
;
6576 op64
= aco_opcode::buffer_atomic_xor_x2
;
6578 case nir_intrinsic_global_atomic_exchange
:
6579 op32
= aco_opcode::buffer_atomic_swap
;
6580 op64
= aco_opcode::buffer_atomic_swap_x2
;
6582 case nir_intrinsic_global_atomic_comp_swap
:
6583 op32
= aco_opcode::buffer_atomic_cmpswap
;
6584 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6587 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6590 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6592 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6594 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6595 mubuf
->operands
[0] = Operand(rsrc
);
6596 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6597 mubuf
->operands
[2] = Operand(0u);
6598 mubuf
->operands
[3] = Operand(data
);
6599 if (return_previous
)
6600 mubuf
->definitions
[0] = Definition(dst
);
6601 mubuf
->glc
= return_previous
;
6604 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6605 mubuf
->disable_wqm
= true;
6606 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6607 ctx
->program
->needs_exact
= true;
6608 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6612 sync_scope
translate_nir_scope(nir_scope scope
)
6615 case NIR_SCOPE_NONE
:
6616 case NIR_SCOPE_INVOCATION
:
6617 return scope_invocation
;
6618 case NIR_SCOPE_SUBGROUP
:
6619 return scope_subgroup
;
6620 case NIR_SCOPE_WORKGROUP
:
6621 return scope_workgroup
;
6622 case NIR_SCOPE_QUEUE_FAMILY
:
6623 return scope_queuefamily
;
6624 case NIR_SCOPE_DEVICE
:
6625 return scope_device
;
6627 unreachable("invalid scope");
6630 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6631 Builder
bld(ctx
->program
, ctx
->block
);
6633 unsigned semantics
= 0;
6634 unsigned storage
= 0;
6635 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6636 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6638 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6639 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6640 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6641 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6642 storage
|= storage_shared
;
6643 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6644 storage
|= storage_shared
;
6646 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6647 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6648 semantics
|= semantic_acquire
| semantic_release
;
6649 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6650 semantics
|= semantic_acquire
| semantic_release
;
6652 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6654 bld
.barrier(aco_opcode::p_barrier
,
6655 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6659 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6661 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6662 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6663 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6664 Builder
bld(ctx
->program
, ctx
->block
);
6666 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6667 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6668 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6671 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6673 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6674 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6675 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6676 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6678 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6679 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6682 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6684 unsigned offset
= nir_intrinsic_base(instr
);
6685 Builder
bld(ctx
->program
, ctx
->block
);
6686 Operand m
= load_lds_size_m0(bld
);
6687 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6688 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6690 unsigned num_operands
= 3;
6691 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6692 switch(instr
->intrinsic
) {
6693 case nir_intrinsic_shared_atomic_add
:
6694 op32
= aco_opcode::ds_add_u32
;
6695 op64
= aco_opcode::ds_add_u64
;
6696 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6697 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6699 case nir_intrinsic_shared_atomic_imin
:
6700 op32
= aco_opcode::ds_min_i32
;
6701 op64
= aco_opcode::ds_min_i64
;
6702 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6703 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6705 case nir_intrinsic_shared_atomic_umin
:
6706 op32
= aco_opcode::ds_min_u32
;
6707 op64
= aco_opcode::ds_min_u64
;
6708 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6709 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6711 case nir_intrinsic_shared_atomic_imax
:
6712 op32
= aco_opcode::ds_max_i32
;
6713 op64
= aco_opcode::ds_max_i64
;
6714 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6715 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6717 case nir_intrinsic_shared_atomic_umax
:
6718 op32
= aco_opcode::ds_max_u32
;
6719 op64
= aco_opcode::ds_max_u64
;
6720 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6721 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6723 case nir_intrinsic_shared_atomic_and
:
6724 op32
= aco_opcode::ds_and_b32
;
6725 op64
= aco_opcode::ds_and_b64
;
6726 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6727 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6729 case nir_intrinsic_shared_atomic_or
:
6730 op32
= aco_opcode::ds_or_b32
;
6731 op64
= aco_opcode::ds_or_b64
;
6732 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6733 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6735 case nir_intrinsic_shared_atomic_xor
:
6736 op32
= aco_opcode::ds_xor_b32
;
6737 op64
= aco_opcode::ds_xor_b64
;
6738 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6739 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6741 case nir_intrinsic_shared_atomic_exchange
:
6742 op32
= aco_opcode::ds_write_b32
;
6743 op64
= aco_opcode::ds_write_b64
;
6744 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6745 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6747 case nir_intrinsic_shared_atomic_comp_swap
:
6748 op32
= aco_opcode::ds_cmpst_b32
;
6749 op64
= aco_opcode::ds_cmpst_b64
;
6750 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6751 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6754 case nir_intrinsic_shared_atomic_fadd
:
6755 op32
= aco_opcode::ds_add_f32
;
6756 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6757 op64
= aco_opcode::num_opcodes
;
6758 op64_rtn
= aco_opcode::num_opcodes
;
6761 unreachable("Unhandled shared atomic intrinsic");
6764 /* return the previous value if dest is ever used */
6765 bool return_previous
= false;
6766 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6767 return_previous
= true;
6770 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6771 return_previous
= true;
6776 if (data
.size() == 1) {
6777 assert(instr
->dest
.ssa
.bit_size
== 32);
6778 op
= return_previous
? op32_rtn
: op32
;
6780 assert(instr
->dest
.ssa
.bit_size
== 64);
6781 op
= return_previous
? op64_rtn
: op64
;
6784 if (offset
> 65535) {
6785 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6789 aco_ptr
<DS_instruction
> ds
;
6790 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6791 ds
->operands
[0] = Operand(address
);
6792 ds
->operands
[1] = Operand(data
);
6793 if (num_operands
== 4)
6794 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6795 ds
->operands
[num_operands
- 1] = m
;
6796 ds
->offset0
= offset
;
6797 if (return_previous
)
6798 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6799 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6800 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6803 Temp
get_scratch_resource(isel_context
*ctx
)
6805 Builder
bld(ctx
->program
, ctx
->block
);
6806 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6807 if (ctx
->stage
!= compute_cs
)
6808 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6810 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6811 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6813 if (ctx
->program
->chip_class
>= GFX10
) {
6814 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6815 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6816 S_008F0C_RESOURCE_LEVEL(1);
6817 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6818 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6819 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6822 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6823 if (ctx
->program
->chip_class
<= GFX8
)
6824 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6826 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6829 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6830 Builder
bld(ctx
->program
, ctx
->block
);
6831 Temp rsrc
= get_scratch_resource(ctx
);
6832 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6833 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6835 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6836 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6837 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6838 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6839 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6840 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6841 info
.soffset
= ctx
->program
->scratch_offset
;
6842 emit_scratch_load(ctx
, bld
, &info
);
6845 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6846 Builder
bld(ctx
->program
, ctx
->block
);
6847 Temp rsrc
= get_scratch_resource(ctx
);
6848 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6849 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6851 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6852 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6854 unsigned write_count
= 0;
6855 Temp write_datas
[32];
6856 unsigned offsets
[32];
6857 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6858 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6859 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6861 for (unsigned i
= 0; i
< write_count
; i
++) {
6862 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6863 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6864 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6868 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6869 uint8_t log2_ps_iter_samples
;
6870 if (ctx
->program
->info
->ps
.force_persample
) {
6871 log2_ps_iter_samples
=
6872 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6874 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6877 /* The bit pattern matches that used by fixed function fragment
6879 static const unsigned ps_iter_masks
[] = {
6880 0xffff, /* not used */
6886 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6888 Builder
bld(ctx
->program
, ctx
->block
);
6890 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6891 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6892 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6893 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6894 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6895 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6898 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6899 Builder
bld(ctx
->program
, ctx
->block
);
6901 unsigned stream
= nir_intrinsic_stream_id(instr
);
6902 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6903 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6904 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6907 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6909 unsigned num_components
=
6910 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6911 assert(num_components
);
6913 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6914 unsigned stream_offset
= 0;
6915 for (unsigned i
= 0; i
< stream
; i
++) {
6916 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6917 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6920 /* Limit on the stride field for <= GFX7. */
6921 assert(stride
< (1 << 14));
6923 Temp gsvs_dwords
[4];
6924 for (unsigned i
= 0; i
< 4; i
++)
6925 gsvs_dwords
[i
] = bld
.tmp(s1
);
6926 bld
.pseudo(aco_opcode::p_split_vector
,
6927 Definition(gsvs_dwords
[0]),
6928 Definition(gsvs_dwords
[1]),
6929 Definition(gsvs_dwords
[2]),
6930 Definition(gsvs_dwords
[3]),
6933 if (stream_offset
) {
6934 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6936 Temp carry
= bld
.tmp(s1
);
6937 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6938 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6941 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6942 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6944 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6945 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6947 unsigned offset
= 0;
6948 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6949 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6952 for (unsigned j
= 0; j
< 4; j
++) {
6953 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6956 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6957 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6958 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6959 if (const_offset
>= 4096u) {
6960 if (vaddr_offset
.isUndefined())
6961 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6963 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6964 const_offset
%= 4096u;
6967 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6968 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6969 mtbuf
->operands
[1] = vaddr_offset
;
6970 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6971 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6972 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6973 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6974 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6975 mtbuf
->offset
= const_offset
;
6978 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
6979 bld
.insert(std::move(mtbuf
));
6982 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6985 /* outputs for the next vertex are undefined and keeping them around can
6986 * create invalid IR with control flow */
6987 ctx
->outputs
.mask
[i
] = 0;
6990 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6993 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6995 Builder
bld(ctx
->program
, ctx
->block
);
6997 if (cluster_size
== 1) {
6999 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7000 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7001 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7002 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7003 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7004 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7005 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7006 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7007 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7008 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7009 //subgroupAnd(val) -> (exec & ~val) == 0
7010 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7011 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7012 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7013 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7014 //subgroupOr(val) -> (val & exec) != 0
7015 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7016 return bool_to_vector_condition(ctx
, tmp
);
7017 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7018 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7019 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7020 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7021 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7022 return bool_to_vector_condition(ctx
, tmp
);
7024 //subgroupClustered{And,Or,Xor}(val, n) ->
7025 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7026 //cluster_offset = ~(n - 1) & lane_id
7027 //cluster_mask = ((1 << n) - 1)
7028 //subgroupClusteredAnd():
7029 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7030 //subgroupClusteredOr():
7031 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7032 //subgroupClusteredXor():
7033 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7034 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7035 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7038 if (op
== nir_op_iand
)
7039 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7041 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7043 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7045 if (ctx
->program
->chip_class
<= GFX7
)
7046 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7047 else if (ctx
->program
->wave_size
== 64)
7048 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7050 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7051 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7052 if (cluster_mask
!= 0xffffffff)
7053 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7055 Definition cmp_def
= Definition();
7056 if (op
== nir_op_iand
) {
7057 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7058 } else if (op
== nir_op_ior
) {
7059 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7060 } else if (op
== nir_op_ixor
) {
7061 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7062 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7063 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7065 cmp_def
.setHint(vcc
);
7066 return cmp_def
.getTemp();
7070 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7072 Builder
bld(ctx
->program
, ctx
->block
);
7074 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7075 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7076 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7078 if (op
== nir_op_iand
)
7079 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7081 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7083 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7084 Temp lo
= lohi
.def(0).getTemp();
7085 Temp hi
= lohi
.def(1).getTemp();
7086 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7088 Definition cmp_def
= Definition();
7089 if (op
== nir_op_iand
)
7090 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7091 else if (op
== nir_op_ior
)
7092 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7093 else if (op
== nir_op_ixor
)
7094 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7095 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7096 cmp_def
.setHint(vcc
);
7097 return cmp_def
.getTemp();
7100 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7102 Builder
bld(ctx
->program
, ctx
->block
);
7104 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7105 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7106 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7107 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7108 if (op
== nir_op_iand
)
7109 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7110 else if (op
== nir_op_ior
)
7111 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7112 else if (op
== nir_op_ixor
)
7113 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7119 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7121 Builder
bld(ctx
->program
, ctx
->block
);
7122 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7123 if (src
.regClass().type() == RegType::vgpr
) {
7124 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7125 } else if (src
.regClass() == s1
) {
7126 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7127 } else if (src
.regClass() == s2
) {
7128 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7130 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7134 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7136 Builder
bld(ctx
->program
, ctx
->block
);
7137 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7138 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7139 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7141 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7142 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7143 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7144 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7147 if (ctx
->program
->chip_class
>= GFX8
) {
7148 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7149 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7150 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7151 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7152 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7153 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7155 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7156 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7157 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7158 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7159 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7160 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7161 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7162 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7163 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7164 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7167 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7168 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7169 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7170 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7171 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7172 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7173 Temp wqm1
= bld
.tmp(v1
);
7174 emit_wqm(ctx
, tmp1
, wqm1
, true);
7175 Temp wqm2
= bld
.tmp(v1
);
7176 emit_wqm(ctx
, tmp2
, wqm2
, true);
7177 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7181 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7183 Builder
bld(ctx
->program
, ctx
->block
);
7184 switch(instr
->intrinsic
) {
7185 case nir_intrinsic_load_barycentric_sample
:
7186 case nir_intrinsic_load_barycentric_pixel
:
7187 case nir_intrinsic_load_barycentric_centroid
: {
7188 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7189 Temp bary
= Temp(0, s2
);
7191 case INTERP_MODE_SMOOTH
:
7192 case INTERP_MODE_NONE
:
7193 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7194 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7195 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7196 bary
= ctx
->persp_centroid
;
7197 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7198 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7200 case INTERP_MODE_NOPERSPECTIVE
:
7201 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7202 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7203 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7204 bary
= ctx
->linear_centroid
;
7205 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7206 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7211 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7212 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7213 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7214 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7215 Operand(p1
), Operand(p2
));
7216 emit_split_vector(ctx
, dst
, 2);
7219 case nir_intrinsic_load_barycentric_model
: {
7220 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7222 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7223 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7224 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7225 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7227 Operand(p1
), Operand(p2
), Operand(p3
));
7228 emit_split_vector(ctx
, dst
, 3);
7231 case nir_intrinsic_load_barycentric_at_sample
: {
7232 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7233 switch (ctx
->options
->key
.fs
.num_samples
) {
7234 case 2: sample_pos_offset
+= 1 << 3; break;
7235 case 4: sample_pos_offset
+= 3 << 3; break;
7236 case 8: sample_pos_offset
+= 7 << 3; break;
7240 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7241 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7242 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7243 //TODO: bounds checking?
7244 if (addr
.type() == RegType::sgpr
) {
7247 sample_pos_offset
+= const_addr
->u32
<< 3;
7248 offset
= Operand(sample_pos_offset
);
7249 } else if (ctx
->options
->chip_class
>= GFX9
) {
7250 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7252 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7253 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7256 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7257 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7259 } else if (ctx
->options
->chip_class
>= GFX9
) {
7260 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7261 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7262 } else if (ctx
->options
->chip_class
>= GFX7
) {
7263 /* addr += private_segment_buffer + sample_pos_offset */
7264 Temp tmp0
= bld
.tmp(s1
);
7265 Temp tmp1
= bld
.tmp(s1
);
7266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7267 Definition scc_tmp
= bld
.def(s1
, scc
);
7268 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7269 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7270 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7271 Temp pck0
= bld
.tmp(v1
);
7272 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7273 tmp1
= as_vgpr(ctx
, tmp1
);
7274 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7275 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7277 /* sample_pos = flat_load_dwordx2 addr */
7278 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7280 assert(ctx
->options
->chip_class
== GFX6
);
7282 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7284 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7286 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7287 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7289 sample_pos
= bld
.tmp(v2
);
7291 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7292 load
->definitions
[0] = Definition(sample_pos
);
7293 load
->operands
[0] = Operand(rsrc
);
7294 load
->operands
[1] = Operand(addr
);
7295 load
->operands
[2] = Operand(0u);
7296 load
->offset
= sample_pos_offset
;
7298 load
->addr64
= true;
7301 load
->disable_wqm
= false;
7302 ctx
->block
->instructions
.emplace_back(std::move(load
));
7305 /* sample_pos -= 0.5 */
7306 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7307 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7308 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7309 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7310 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7312 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7315 case nir_intrinsic_load_barycentric_at_offset
: {
7316 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7317 RegClass rc
= RegClass(offset
.type(), 1);
7318 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7319 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7320 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7323 case nir_intrinsic_load_front_face
: {
7324 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7325 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7328 case nir_intrinsic_load_view_index
: {
7329 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7330 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7331 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7337 case nir_intrinsic_load_layer_id
: {
7338 unsigned idx
= nir_intrinsic_base(instr
);
7339 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7340 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7343 case nir_intrinsic_load_frag_coord
: {
7344 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7347 case nir_intrinsic_load_sample_pos
: {
7348 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7349 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7350 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7351 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7352 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7355 case nir_intrinsic_load_tess_coord
:
7356 visit_load_tess_coord(ctx
, instr
);
7358 case nir_intrinsic_load_interpolated_input
:
7359 visit_load_interpolated_input(ctx
, instr
);
7361 case nir_intrinsic_store_output
:
7362 visit_store_output(ctx
, instr
);
7364 case nir_intrinsic_load_input
:
7365 case nir_intrinsic_load_input_vertex
:
7366 visit_load_input(ctx
, instr
);
7368 case nir_intrinsic_load_output
:
7369 visit_load_output(ctx
, instr
);
7371 case nir_intrinsic_load_per_vertex_input
:
7372 visit_load_per_vertex_input(ctx
, instr
);
7374 case nir_intrinsic_load_per_vertex_output
:
7375 visit_load_per_vertex_output(ctx
, instr
);
7377 case nir_intrinsic_store_per_vertex_output
:
7378 visit_store_per_vertex_output(ctx
, instr
);
7380 case nir_intrinsic_load_ubo
:
7381 visit_load_ubo(ctx
, instr
);
7383 case nir_intrinsic_load_push_constant
:
7384 visit_load_push_constant(ctx
, instr
);
7386 case nir_intrinsic_load_constant
:
7387 visit_load_constant(ctx
, instr
);
7389 case nir_intrinsic_vulkan_resource_index
:
7390 visit_load_resource(ctx
, instr
);
7392 case nir_intrinsic_discard
:
7393 visit_discard(ctx
, instr
);
7395 case nir_intrinsic_discard_if
:
7396 visit_discard_if(ctx
, instr
);
7398 case nir_intrinsic_load_shared
:
7399 visit_load_shared(ctx
, instr
);
7401 case nir_intrinsic_store_shared
:
7402 visit_store_shared(ctx
, instr
);
7404 case nir_intrinsic_shared_atomic_add
:
7405 case nir_intrinsic_shared_atomic_imin
:
7406 case nir_intrinsic_shared_atomic_umin
:
7407 case nir_intrinsic_shared_atomic_imax
:
7408 case nir_intrinsic_shared_atomic_umax
:
7409 case nir_intrinsic_shared_atomic_and
:
7410 case nir_intrinsic_shared_atomic_or
:
7411 case nir_intrinsic_shared_atomic_xor
:
7412 case nir_intrinsic_shared_atomic_exchange
:
7413 case nir_intrinsic_shared_atomic_comp_swap
:
7414 case nir_intrinsic_shared_atomic_fadd
:
7415 visit_shared_atomic(ctx
, instr
);
7417 case nir_intrinsic_image_deref_load
:
7418 visit_image_load(ctx
, instr
);
7420 case nir_intrinsic_image_deref_store
:
7421 visit_image_store(ctx
, instr
);
7423 case nir_intrinsic_image_deref_atomic_add
:
7424 case nir_intrinsic_image_deref_atomic_umin
:
7425 case nir_intrinsic_image_deref_atomic_imin
:
7426 case nir_intrinsic_image_deref_atomic_umax
:
7427 case nir_intrinsic_image_deref_atomic_imax
:
7428 case nir_intrinsic_image_deref_atomic_and
:
7429 case nir_intrinsic_image_deref_atomic_or
:
7430 case nir_intrinsic_image_deref_atomic_xor
:
7431 case nir_intrinsic_image_deref_atomic_exchange
:
7432 case nir_intrinsic_image_deref_atomic_comp_swap
:
7433 visit_image_atomic(ctx
, instr
);
7435 case nir_intrinsic_image_deref_size
:
7436 visit_image_size(ctx
, instr
);
7438 case nir_intrinsic_load_ssbo
:
7439 visit_load_ssbo(ctx
, instr
);
7441 case nir_intrinsic_store_ssbo
:
7442 visit_store_ssbo(ctx
, instr
);
7444 case nir_intrinsic_load_global
:
7445 visit_load_global(ctx
, instr
);
7447 case nir_intrinsic_store_global
:
7448 visit_store_global(ctx
, instr
);
7450 case nir_intrinsic_global_atomic_add
:
7451 case nir_intrinsic_global_atomic_imin
:
7452 case nir_intrinsic_global_atomic_umin
:
7453 case nir_intrinsic_global_atomic_imax
:
7454 case nir_intrinsic_global_atomic_umax
:
7455 case nir_intrinsic_global_atomic_and
:
7456 case nir_intrinsic_global_atomic_or
:
7457 case nir_intrinsic_global_atomic_xor
:
7458 case nir_intrinsic_global_atomic_exchange
:
7459 case nir_intrinsic_global_atomic_comp_swap
:
7460 visit_global_atomic(ctx
, instr
);
7462 case nir_intrinsic_ssbo_atomic_add
:
7463 case nir_intrinsic_ssbo_atomic_imin
:
7464 case nir_intrinsic_ssbo_atomic_umin
:
7465 case nir_intrinsic_ssbo_atomic_imax
:
7466 case nir_intrinsic_ssbo_atomic_umax
:
7467 case nir_intrinsic_ssbo_atomic_and
:
7468 case nir_intrinsic_ssbo_atomic_or
:
7469 case nir_intrinsic_ssbo_atomic_xor
:
7470 case nir_intrinsic_ssbo_atomic_exchange
:
7471 case nir_intrinsic_ssbo_atomic_comp_swap
:
7472 visit_atomic_ssbo(ctx
, instr
);
7474 case nir_intrinsic_load_scratch
:
7475 visit_load_scratch(ctx
, instr
);
7477 case nir_intrinsic_store_scratch
:
7478 visit_store_scratch(ctx
, instr
);
7480 case nir_intrinsic_get_buffer_size
:
7481 visit_get_buffer_size(ctx
, instr
);
7483 case nir_intrinsic_scoped_barrier
:
7484 emit_scoped_barrier(ctx
, instr
);
7486 case nir_intrinsic_load_num_work_groups
: {
7487 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7488 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7489 emit_split_vector(ctx
, dst
, 3);
7492 case nir_intrinsic_load_local_invocation_id
: {
7493 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7494 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7495 emit_split_vector(ctx
, dst
, 3);
7498 case nir_intrinsic_load_work_group_id
: {
7499 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7500 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7501 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7502 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7503 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7504 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7505 emit_split_vector(ctx
, dst
, 3);
7508 case nir_intrinsic_load_local_invocation_index
: {
7509 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7511 /* The tg_size bits [6:11] contain the subgroup id,
7512 * we need this multiplied by the wave size, and then OR the thread id to it.
7514 if (ctx
->program
->wave_size
== 64) {
7515 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7516 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7517 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7518 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7520 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7521 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7522 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7523 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7527 case nir_intrinsic_load_subgroup_id
: {
7528 if (ctx
->stage
== compute_cs
) {
7529 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7530 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7532 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7536 case nir_intrinsic_load_subgroup_invocation
: {
7537 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7540 case nir_intrinsic_load_num_subgroups
: {
7541 if (ctx
->stage
== compute_cs
)
7542 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7543 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7545 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7548 case nir_intrinsic_ballot
: {
7549 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7550 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7551 Definition tmp
= bld
.def(dst
.regClass());
7552 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7553 if (instr
->src
[0].ssa
->bit_size
== 1) {
7554 assert(src
.regClass() == bld
.lm
);
7555 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7556 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7557 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7558 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7559 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7561 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7563 if (dst
.size() != bld
.lm
.size()) {
7564 /* Wave32 with ballot size set to 64 */
7565 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7567 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7570 case nir_intrinsic_shuffle
:
7571 case nir_intrinsic_read_invocation
: {
7572 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7573 if (!nir_src_is_divergent(instr
->src
[0])) {
7574 emit_uniform_subgroup(ctx
, instr
, src
);
7576 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7577 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7578 tid
= bld
.as_uniform(tid
);
7579 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7580 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7581 Temp tmp
= bld
.tmp(v1
);
7582 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7583 if (dst
.type() == RegType::vgpr
)
7584 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7586 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7587 } else if (src
.regClass() == v1
) {
7588 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7589 } else if (src
.regClass() == v2
) {
7590 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7591 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7592 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7593 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7594 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7595 emit_split_vector(ctx
, dst
, 2);
7596 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7597 assert(src
.regClass() == bld
.lm
);
7598 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7599 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7600 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7601 assert(src
.regClass() == bld
.lm
);
7603 if (ctx
->program
->chip_class
<= GFX7
)
7604 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7605 else if (ctx
->program
->wave_size
== 64)
7606 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7608 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7609 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7610 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7611 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7613 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7618 case nir_intrinsic_load_sample_id
: {
7619 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7620 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7623 case nir_intrinsic_load_sample_mask_in
: {
7624 visit_load_sample_mask_in(ctx
, instr
);
7627 case nir_intrinsic_read_first_invocation
: {
7628 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7629 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7630 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7632 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7634 } else if (src
.regClass() == v2
) {
7635 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7636 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7637 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7638 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7639 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7640 emit_split_vector(ctx
, dst
, 2);
7641 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7642 assert(src
.regClass() == bld
.lm
);
7643 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7644 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7645 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7646 } else if (src
.regClass() == s1
) {
7647 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7648 } else if (src
.regClass() == s2
) {
7649 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7651 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7655 case nir_intrinsic_vote_all
: {
7656 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7657 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7658 assert(src
.regClass() == bld
.lm
);
7659 assert(dst
.regClass() == bld
.lm
);
7661 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7662 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7663 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7666 case nir_intrinsic_vote_any
: {
7667 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7668 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7669 assert(src
.regClass() == bld
.lm
);
7670 assert(dst
.regClass() == bld
.lm
);
7672 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7673 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7676 case nir_intrinsic_reduce
:
7677 case nir_intrinsic_inclusive_scan
:
7678 case nir_intrinsic_exclusive_scan
: {
7679 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7680 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7681 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7682 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7683 nir_intrinsic_cluster_size(instr
) : 0;
7684 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7686 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7687 emit_uniform_subgroup(ctx
, instr
, src
);
7688 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7689 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7691 else if (op
== nir_op_iadd
)
7693 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7695 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7697 switch (instr
->intrinsic
) {
7698 case nir_intrinsic_reduce
:
7699 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7701 case nir_intrinsic_exclusive_scan
:
7702 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7704 case nir_intrinsic_inclusive_scan
:
7705 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7710 } else if (cluster_size
== 1) {
7711 bld
.copy(Definition(dst
), src
);
7713 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7715 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7719 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7720 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7735 unreachable("unknown reduction op");
7741 switch (instr
->intrinsic
) {
7742 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7743 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7744 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7746 unreachable("unknown reduce intrinsic");
7749 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7750 reduce
->operands
[0] = Operand(src
);
7751 // filled in by aco_reduce_assign.cpp, used internally as part of the
7753 assert(dst
.size() == 1 || dst
.size() == 2);
7754 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7755 reduce
->operands
[2] = Operand(v1
.as_linear());
7757 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7758 reduce
->definitions
[0] = Definition(tmp_dst
);
7759 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7760 reduce
->definitions
[2] = Definition();
7761 reduce
->definitions
[3] = Definition(scc
, s1
);
7762 reduce
->definitions
[4] = Definition();
7763 reduce
->reduce_op
= reduce_op
;
7764 reduce
->cluster_size
= cluster_size
;
7765 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7767 emit_wqm(ctx
, tmp_dst
, dst
);
7771 case nir_intrinsic_quad_broadcast
: {
7772 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7773 if (!nir_dest_is_divergent(instr
->dest
)) {
7774 emit_uniform_subgroup(ctx
, instr
, src
);
7776 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7777 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7778 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7780 if (instr
->dest
.ssa
.bit_size
== 1) {
7781 assert(src
.regClass() == bld
.lm
);
7782 assert(dst
.regClass() == bld
.lm
);
7783 uint32_t half_mask
= 0x11111111u
<< lane
;
7784 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7785 Temp tmp
= bld
.tmp(bld
.lm
);
7786 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7787 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7788 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7789 emit_wqm(ctx
, tmp
, dst
);
7790 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7791 Temp tmp
= bld
.tmp(v1
);
7792 if (ctx
->program
->chip_class
>= GFX8
)
7793 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7795 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7796 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7797 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7798 Temp tmp
= bld
.tmp(v1
);
7799 if (ctx
->program
->chip_class
>= GFX8
)
7800 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7802 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7803 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7804 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7805 if (ctx
->program
->chip_class
>= GFX8
)
7806 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7808 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7809 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7810 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7811 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7812 if (ctx
->program
->chip_class
>= GFX8
) {
7813 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7814 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7816 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7817 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7819 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7820 emit_split_vector(ctx
, dst
, 2);
7822 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7827 case nir_intrinsic_quad_swap_horizontal
:
7828 case nir_intrinsic_quad_swap_vertical
:
7829 case nir_intrinsic_quad_swap_diagonal
:
7830 case nir_intrinsic_quad_swizzle_amd
: {
7831 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7832 if (!nir_dest_is_divergent(instr
->dest
)) {
7833 emit_uniform_subgroup(ctx
, instr
, src
);
7836 uint16_t dpp_ctrl
= 0;
7837 switch (instr
->intrinsic
) {
7838 case nir_intrinsic_quad_swap_horizontal
:
7839 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7841 case nir_intrinsic_quad_swap_vertical
:
7842 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7844 case nir_intrinsic_quad_swap_diagonal
:
7845 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7847 case nir_intrinsic_quad_swizzle_amd
:
7848 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7853 if (ctx
->program
->chip_class
< GFX8
)
7854 dpp_ctrl
|= (1 << 15);
7856 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7857 if (instr
->dest
.ssa
.bit_size
== 1) {
7858 assert(src
.regClass() == bld
.lm
);
7859 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7860 if (ctx
->program
->chip_class
>= GFX8
)
7861 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7863 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7864 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7865 emit_wqm(ctx
, tmp
, dst
);
7866 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7867 Temp tmp
= bld
.tmp(v1
);
7868 if (ctx
->program
->chip_class
>= GFX8
)
7869 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7871 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7872 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7873 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7874 Temp tmp
= bld
.tmp(v1
);
7875 if (ctx
->program
->chip_class
>= GFX8
)
7876 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7878 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7879 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7880 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7882 if (ctx
->program
->chip_class
>= GFX8
)
7883 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7885 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7886 emit_wqm(ctx
, tmp
, dst
);
7887 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7888 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7889 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7890 if (ctx
->program
->chip_class
>= GFX8
) {
7891 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7892 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7894 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7895 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7897 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7898 emit_split_vector(ctx
, dst
, 2);
7900 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7904 case nir_intrinsic_masked_swizzle_amd
: {
7905 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7906 if (!nir_dest_is_divergent(instr
->dest
)) {
7907 emit_uniform_subgroup(ctx
, instr
, src
);
7910 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7911 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7912 if (instr
->dest
.ssa
.bit_size
== 1) {
7913 assert(src
.regClass() == bld
.lm
);
7914 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7915 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7916 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7917 emit_wqm(ctx
, tmp
, dst
);
7918 } else if (dst
.regClass() == v1b
) {
7919 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7920 emit_extract_vector(ctx
, tmp
, 0, dst
);
7921 } else if (dst
.regClass() == v2b
) {
7922 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7923 emit_extract_vector(ctx
, tmp
, 0, dst
);
7924 } else if (dst
.regClass() == v1
) {
7925 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7926 } else if (dst
.regClass() == v2
) {
7927 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7928 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7929 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7930 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7931 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7932 emit_split_vector(ctx
, dst
, 2);
7934 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7938 case nir_intrinsic_write_invocation_amd
: {
7939 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7940 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7941 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7942 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7943 if (dst
.regClass() == v1
) {
7944 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7945 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7946 } else if (dst
.regClass() == v2
) {
7947 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7948 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7949 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7950 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7951 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7952 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7953 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7954 emit_split_vector(ctx
, dst
, 2);
7956 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7960 case nir_intrinsic_mbcnt_amd
: {
7961 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7962 RegClass rc
= RegClass(src
.type(), 1);
7963 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7965 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7966 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7967 emit_wqm(ctx
, wqm_tmp
, dst
);
7970 case nir_intrinsic_load_helper_invocation
: {
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7973 ctx
->block
->kind
|= block_kind_needs_lowering
;
7974 ctx
->program
->needs_exact
= true;
7977 case nir_intrinsic_is_helper_invocation
: {
7978 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7979 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7980 ctx
->block
->kind
|= block_kind_needs_lowering
;
7981 ctx
->program
->needs_exact
= true;
7984 case nir_intrinsic_demote
:
7985 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7987 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7988 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7989 ctx
->block
->kind
|= block_kind_uses_demote
;
7990 ctx
->program
->needs_exact
= true;
7992 case nir_intrinsic_demote_if
: {
7993 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7994 assert(src
.regClass() == bld
.lm
);
7995 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7996 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7998 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7999 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8000 ctx
->block
->kind
|= block_kind_uses_demote
;
8001 ctx
->program
->needs_exact
= true;
8004 case nir_intrinsic_first_invocation
: {
8005 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8006 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8009 case nir_intrinsic_shader_clock
: {
8010 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8011 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
8012 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
8013 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
8014 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
8017 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8018 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8019 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
8021 emit_split_vector(ctx
, dst
, 2);
8024 case nir_intrinsic_load_vertex_id_zero_base
: {
8025 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8026 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8029 case nir_intrinsic_load_first_vertex
: {
8030 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8031 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8034 case nir_intrinsic_load_base_instance
: {
8035 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8036 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8039 case nir_intrinsic_load_instance_id
: {
8040 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8041 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8044 case nir_intrinsic_load_draw_id
: {
8045 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8046 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8049 case nir_intrinsic_load_invocation_id
: {
8050 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8052 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8053 if (ctx
->options
->chip_class
>= GFX10
)
8054 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8056 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8057 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8058 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8059 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8061 unreachable("Unsupported stage for load_invocation_id");
8066 case nir_intrinsic_load_primitive_id
: {
8067 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8069 switch (ctx
->shader
->info
.stage
) {
8070 case MESA_SHADER_GEOMETRY
:
8071 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8073 case MESA_SHADER_TESS_CTRL
:
8074 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8076 case MESA_SHADER_TESS_EVAL
:
8077 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8080 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8085 case nir_intrinsic_load_patch_vertices_in
: {
8086 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8087 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8089 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8090 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8093 case nir_intrinsic_emit_vertex_with_counter
: {
8094 visit_emit_vertex_with_counter(ctx
, instr
);
8097 case nir_intrinsic_end_primitive_with_counter
: {
8098 unsigned stream
= nir_intrinsic_stream_id(instr
);
8099 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8102 case nir_intrinsic_set_vertex_count
: {
8103 /* unused, the HW keeps track of this for us */
8107 isel_err(&instr
->instr
, "Unimplemented intrinsic instr");
8115 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8116 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8117 enum glsl_base_type
*stype
)
8119 nir_deref_instr
*texture_deref_instr
= NULL
;
8120 nir_deref_instr
*sampler_deref_instr
= NULL
;
8123 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8124 switch (instr
->src
[i
].src_type
) {
8125 case nir_tex_src_texture_deref
:
8126 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8128 case nir_tex_src_sampler_deref
:
8129 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8131 case nir_tex_src_plane
:
8132 plane
= nir_src_as_int(instr
->src
[i
].src
);
8139 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8141 if (!sampler_deref_instr
)
8142 sampler_deref_instr
= texture_deref_instr
;
8145 assert(instr
->op
!= nir_texop_txf_ms
&&
8146 instr
->op
!= nir_texop_samples_identical
);
8147 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8148 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8149 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8150 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8151 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8152 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8154 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8157 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8159 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8160 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8161 Builder
bld(ctx
->program
, ctx
->block
);
8163 /* to avoid unnecessary moves, we split and recombine sampler and image */
8164 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8165 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8166 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8167 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8168 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8169 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8170 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8171 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8173 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8174 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8175 img
[0], img
[1], img
[2], img
[3],
8176 img
[4], img
[5], img
[6], img
[7]);
8177 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8178 samp
[0], samp
[1], samp
[2], samp
[3]);
8181 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8182 instr
->op
== nir_texop_samples_identical
))
8183 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8186 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8187 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8189 Builder
bld(ctx
->program
, ctx
->block
);
8191 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8192 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8193 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8195 Operand
neg_one(0xbf800000u
);
8196 Operand
one(0x3f800000u
);
8197 Operand
two(0x40000000u
);
8198 Operand
four(0x40800000u
);
8200 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8201 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8202 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8204 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8205 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8206 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8207 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8210 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8211 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8212 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8214 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8217 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8218 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8219 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8222 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8223 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8225 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8226 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8229 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8231 Builder
bld(ctx
->program
, ctx
->block
);
8232 Temp ma
, tc
, sc
, id
;
8233 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8234 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8237 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8239 // see comment in ac_prepare_cube_coords()
8240 if (ctx
->options
->chip_class
<= GFX8
)
8241 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8244 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8246 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8247 vop3a
->operands
[0] = Operand(ma
);
8248 vop3a
->abs
[0] = true;
8249 Temp invma
= bld
.tmp(v1
);
8250 vop3a
->definitions
[0] = Definition(invma
);
8251 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8253 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8255 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8257 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8259 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8261 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8264 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8265 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8267 for (unsigned i
= 0; i
< 2; i
++) {
8268 // see comment in ac_prepare_cube_coords()
8270 Temp deriv_sc
, deriv_tc
;
8271 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8272 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8274 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8276 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8277 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8278 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8279 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8280 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8281 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8282 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8285 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8286 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8290 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8297 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8299 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8301 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8302 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8305 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8306 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8307 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8311 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8313 Builder
bld(ctx
->program
, ctx
->block
);
8314 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8315 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8316 has_clamped_lod
= false;
8317 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8318 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8319 clamped_lod
= Temp();
8320 std::vector
<Temp
> coords
;
8321 std::vector
<Temp
> derivs
;
8322 nir_const_value
*sample_index_cv
= NULL
;
8323 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8324 enum glsl_base_type stype
;
8325 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8327 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8328 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8329 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8330 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8332 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8333 switch (instr
->src
[i
].src_type
) {
8334 case nir_tex_src_coord
: {
8335 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8336 for (unsigned i
= 0; i
< coord
.size(); i
++)
8337 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8340 case nir_tex_src_bias
:
8341 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8344 case nir_tex_src_lod
: {
8345 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8347 if (val
&& val
->f32
<= 0.0) {
8350 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8355 case nir_tex_src_min_lod
:
8356 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8357 has_clamped_lod
= true;
8359 case nir_tex_src_comparator
:
8360 if (instr
->is_shadow
) {
8361 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8365 case nir_tex_src_offset
:
8366 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8367 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8370 case nir_tex_src_ddx
:
8371 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8374 case nir_tex_src_ddy
:
8375 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8378 case nir_tex_src_ms_index
:
8379 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8380 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8381 has_sample_index
= true;
8383 case nir_tex_src_texture_offset
:
8384 case nir_tex_src_sampler_offset
:
8390 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8391 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8393 if (instr
->op
== nir_texop_texture_samples
) {
8394 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8396 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8397 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8398 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8400 Operand default_sample
= Operand(1u);
8401 if (ctx
->options
->robust_buffer_access
) {
8402 /* Extract the second dword of the descriptor, if it's
8403 * all zero, then it's a null descriptor.
8405 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8406 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8407 default_sample
= Operand(is_non_null_descriptor
);
8410 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8411 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8412 samples
, default_sample
, bld
.scc(is_msaa
));
8416 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8417 aco_ptr
<Instruction
> tmp_instr
;
8418 Temp acc
, pack
= Temp();
8420 uint32_t pack_const
= 0;
8421 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8422 if (!const_offset
[i
])
8424 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8427 if (offset
.type() == RegType::sgpr
) {
8428 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8429 if (const_offset
[i
])
8432 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8433 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8436 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8439 if (pack
== Temp()) {
8442 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8446 if (pack_const
&& pack
!= Temp())
8447 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8449 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8450 if (const_offset
[i
])
8453 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8454 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8457 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8460 if (pack
== Temp()) {
8463 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8467 if (pack_const
&& pack
!= Temp())
8468 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8470 if (pack_const
&& pack
== Temp())
8471 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8472 else if (pack
== Temp())
8478 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8479 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8481 /* pack derivatives */
8482 if (has_ddx
|| has_ddy
) {
8483 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8484 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8485 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8486 derivs
= {ddx
, zero
, ddy
, zero
};
8488 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8489 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8490 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8491 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8496 if (instr
->coord_components
> 1 &&
8497 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8499 instr
->op
!= nir_texop_txf
)
8500 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8502 if (instr
->coord_components
> 2 &&
8503 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8504 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8505 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8506 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8508 instr
->op
!= nir_texop_txf
&&
8509 instr
->op
!= nir_texop_txf_ms
&&
8510 instr
->op
!= nir_texop_fragment_fetch
&&
8511 instr
->op
!= nir_texop_fragment_mask_fetch
)
8512 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8514 if (ctx
->options
->chip_class
== GFX9
&&
8515 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8516 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8517 assert(coords
.size() > 0 && coords
.size() < 3);
8519 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8520 Operand((uint32_t) 0) :
8521 Operand((uint32_t) 0x3f000000)));
8524 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8526 if (instr
->op
== nir_texop_samples_identical
)
8527 resource
= fmask_ptr
;
8529 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8530 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8531 instr
->op
!= nir_texop_txs
&&
8532 instr
->op
!= nir_texop_fragment_fetch
&&
8533 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8534 assert(has_sample_index
);
8535 Operand
op(sample_index
);
8536 if (sample_index_cv
)
8537 op
= Operand(sample_index_cv
->u32
);
8538 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8541 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8542 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8543 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8544 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8549 /* Build tex instruction */
8550 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8551 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8552 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8554 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8557 /* gather4 selects the component by dmask and always returns vec4 */
8558 if (instr
->op
== nir_texop_tg4
) {
8559 assert(instr
->dest
.ssa
.num_components
== 4);
8560 if (instr
->is_shadow
)
8563 dmask
= 1 << instr
->component
;
8564 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8565 tmp_dst
= bld
.tmp(v4
);
8566 } else if (instr
->op
== nir_texop_samples_identical
) {
8567 tmp_dst
= bld
.tmp(v1
);
8568 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8569 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8572 aco_ptr
<MIMG_instruction
> tex
;
8573 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8575 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8577 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8578 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8581 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8582 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8584 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8585 tex
->operands
[0] = Operand(resource
);
8586 tex
->operands
[1] = Operand(s4
); /* no sampler */
8587 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8588 if (ctx
->options
->chip_class
== GFX9
&&
8589 instr
->op
== nir_texop_txs
&&
8590 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8592 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8593 } else if (instr
->op
== nir_texop_query_levels
) {
8594 tex
->dmask
= 1 << 3;
8599 tex
->definitions
[0] = Definition(tmp_dst
);
8601 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8604 /* divide 3rd value by 6 by multiplying with magic number */
8605 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8606 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8607 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8608 assert(instr
->dest
.ssa
.num_components
== 3);
8609 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8610 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8611 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8612 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8617 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8621 Temp tg4_compare_cube_wa64
= Temp();
8623 if (tg4_integer_workarounds
) {
8624 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8625 tex
->operands
[0] = Operand(resource
);
8626 tex
->operands
[1] = Operand(s4
); /* no sampler */
8627 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8631 Temp size
= bld
.tmp(v2
);
8632 tex
->definitions
[0] = Definition(size
);
8633 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8634 emit_split_vector(ctx
, size
, size
.size());
8637 for (unsigned i
= 0; i
< 2; i
++) {
8638 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8639 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8640 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8641 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8644 Temp new_coords
[2] = {
8645 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8646 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8649 if (tg4_integer_cube_workaround
) {
8650 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8651 Temp desc
[resource
.size()];
8652 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8653 Format::PSEUDO
, 1, resource
.size())};
8654 split
->operands
[0] = Operand(resource
);
8655 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8656 desc
[i
] = bld
.tmp(s1
);
8657 split
->definitions
[i
] = Definition(desc
[i
]);
8659 ctx
->block
->instructions
.emplace_back(std::move(split
));
8661 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8662 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8663 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8666 if (stype
== GLSL_TYPE_UINT
) {
8667 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8668 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8669 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8670 bld
.scc(compare_cube_wa
));
8672 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8673 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8674 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8675 bld
.scc(compare_cube_wa
));
8677 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8678 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8680 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8682 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8683 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8684 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8686 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8687 Format::PSEUDO
, resource
.size(), 1)};
8688 for (unsigned i
= 0; i
< resource
.size(); i
++)
8689 vec
->operands
[i
] = Operand(desc
[i
]);
8690 resource
= bld
.tmp(resource
.regClass());
8691 vec
->definitions
[0] = Definition(resource
);
8692 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8694 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8695 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8696 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8697 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8699 coords
[0] = new_coords
[0];
8700 coords
[1] = new_coords
[1];
8703 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8704 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8706 assert(coords
.size() == 1);
8707 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8711 op
= aco_opcode::buffer_load_format_x
; break;
8713 op
= aco_opcode::buffer_load_format_xy
; break;
8715 op
= aco_opcode::buffer_load_format_xyz
; break;
8717 op
= aco_opcode::buffer_load_format_xyzw
; break;
8719 unreachable("Tex instruction loads more than 4 components.");
8722 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8723 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8726 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8728 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8729 mubuf
->operands
[0] = Operand(resource
);
8730 mubuf
->operands
[1] = Operand(coords
[0]);
8731 mubuf
->operands
[2] = Operand((uint32_t) 0);
8732 mubuf
->definitions
[0] = Definition(tmp_dst
);
8733 mubuf
->idxen
= true;
8734 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8736 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8740 /* gather MIMG address components */
8741 std::vector
<Temp
> args
;
8743 args
.emplace_back(offset
);
8745 args
.emplace_back(bias
);
8747 args
.emplace_back(compare
);
8749 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8751 args
.insert(args
.end(), coords
.begin(), coords
.end());
8752 if (has_sample_index
)
8753 args
.emplace_back(sample_index
);
8755 args
.emplace_back(lod
);
8756 if (has_clamped_lod
)
8757 args
.emplace_back(clamped_lod
);
8759 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8760 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8761 vec
->definitions
[0] = Definition(arg
);
8762 for (unsigned i
= 0; i
< args
.size(); i
++)
8763 vec
->operands
[i
] = Operand(args
[i
]);
8764 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8767 if (instr
->op
== nir_texop_txf
||
8768 instr
->op
== nir_texop_txf_ms
||
8769 instr
->op
== nir_texop_samples_identical
||
8770 instr
->op
== nir_texop_fragment_fetch
||
8771 instr
->op
== nir_texop_fragment_mask_fetch
) {
8772 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8773 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8774 tex
->operands
[0] = Operand(resource
);
8775 tex
->operands
[1] = Operand(s4
); /* no sampler */
8776 tex
->operands
[2] = Operand(arg
);
8781 tex
->definitions
[0] = Definition(tmp_dst
);
8782 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8784 if (instr
->op
== nir_texop_samples_identical
) {
8785 assert(dmask
== 1 && dst
.regClass() == v1
);
8786 assert(dst
.id() != tmp_dst
.id());
8788 Temp tmp
= bld
.tmp(bld
.lm
);
8789 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8790 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8793 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8798 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8799 aco_opcode opcode
= aco_opcode::image_sample
;
8800 if (has_offset
) { /* image_sample_*_o */
8801 if (has_clamped_lod
) {
8803 opcode
= aco_opcode::image_sample_c_cl_o
;
8805 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8807 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8809 opcode
= aco_opcode::image_sample_cl_o
;
8811 opcode
= aco_opcode::image_sample_d_cl_o
;
8813 opcode
= aco_opcode::image_sample_b_cl_o
;
8815 } else if (has_compare
) {
8816 opcode
= aco_opcode::image_sample_c_o
;
8818 opcode
= aco_opcode::image_sample_c_d_o
;
8820 opcode
= aco_opcode::image_sample_c_b_o
;
8822 opcode
= aco_opcode::image_sample_c_lz_o
;
8824 opcode
= aco_opcode::image_sample_c_l_o
;
8826 opcode
= aco_opcode::image_sample_o
;
8828 opcode
= aco_opcode::image_sample_d_o
;
8830 opcode
= aco_opcode::image_sample_b_o
;
8832 opcode
= aco_opcode::image_sample_lz_o
;
8834 opcode
= aco_opcode::image_sample_l_o
;
8836 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8838 opcode
= aco_opcode::image_sample_c_cl
;
8840 opcode
= aco_opcode::image_sample_c_d_cl
;
8842 opcode
= aco_opcode::image_sample_c_b_cl
;
8844 opcode
= aco_opcode::image_sample_cl
;
8846 opcode
= aco_opcode::image_sample_d_cl
;
8848 opcode
= aco_opcode::image_sample_b_cl
;
8850 } else { /* no offset */
8852 opcode
= aco_opcode::image_sample_c
;
8854 opcode
= aco_opcode::image_sample_c_d
;
8856 opcode
= aco_opcode::image_sample_c_b
;
8858 opcode
= aco_opcode::image_sample_c_lz
;
8860 opcode
= aco_opcode::image_sample_c_l
;
8862 opcode
= aco_opcode::image_sample
;
8864 opcode
= aco_opcode::image_sample_d
;
8866 opcode
= aco_opcode::image_sample_b
;
8868 opcode
= aco_opcode::image_sample_lz
;
8870 opcode
= aco_opcode::image_sample_l
;
8874 if (instr
->op
== nir_texop_tg4
) {
8875 if (has_offset
) { /* image_gather4_*_o */
8877 opcode
= aco_opcode::image_gather4_c_lz_o
;
8879 opcode
= aco_opcode::image_gather4_c_l_o
;
8881 opcode
= aco_opcode::image_gather4_c_b_o
;
8883 opcode
= aco_opcode::image_gather4_lz_o
;
8885 opcode
= aco_opcode::image_gather4_l_o
;
8887 opcode
= aco_opcode::image_gather4_b_o
;
8891 opcode
= aco_opcode::image_gather4_c_lz
;
8893 opcode
= aco_opcode::image_gather4_c_l
;
8895 opcode
= aco_opcode::image_gather4_c_b
;
8897 opcode
= aco_opcode::image_gather4_lz
;
8899 opcode
= aco_opcode::image_gather4_l
;
8901 opcode
= aco_opcode::image_gather4_b
;
8904 } else if (instr
->op
== nir_texop_lod
) {
8905 opcode
= aco_opcode::image_get_lod
;
8908 /* we don't need the bias, sample index, compare value or offset to be
8909 * computed in WQM but if the p_create_vector copies the coordinates, then it
8910 * needs to be in WQM */
8911 if (ctx
->stage
== fragment_fs
&&
8912 !has_derivs
&& !has_lod
&& !level_zero
&&
8913 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8914 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8915 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8917 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8918 tex
->operands
[0] = Operand(resource
);
8919 tex
->operands
[1] = Operand(sampler
);
8920 tex
->operands
[2] = Operand(arg
);
8924 tex
->definitions
[0] = Definition(tmp_dst
);
8925 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8927 if (tg4_integer_cube_workaround
) {
8928 assert(tmp_dst
.id() != dst
.id());
8929 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8931 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8933 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8934 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8936 if (stype
== GLSL_TYPE_UINT
)
8937 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8939 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8940 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8942 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8943 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8944 val
[0], val
[1], val
[2], val
[3]);
8946 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8947 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8952 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8954 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8955 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8957 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8958 if (ctx
->program
->wave_size
== 64)
8959 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8961 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8963 return Operand(tmp
);
8967 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8969 aco_ptr
<Pseudo_instruction
> phi
;
8970 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8971 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8973 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8974 logical
|= ctx
->block
->kind
& block_kind_merge
;
8975 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8977 /* we want a sorted list of sources, since the predecessor list is also sorted */
8978 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8979 nir_foreach_phi_src(src
, instr
)
8980 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8982 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8983 unsigned num_operands
= 0;
8984 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8985 unsigned num_defined
= 0;
8986 unsigned cur_pred_idx
= 0;
8987 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8988 if (cur_pred_idx
< preds
.size()) {
8989 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8990 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8991 unsigned skipped
= 0;
8992 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8994 if (cur_pred_idx
+ skipped
< preds
.size()) {
8995 for (unsigned i
= 0; i
< skipped
; i
++)
8996 operands
[num_operands
++] = Operand(dst
.regClass());
8997 cur_pred_idx
+= skipped
;
9002 /* Handle missing predecessors at the end. This shouldn't happen with loop
9003 * headers and we can't ignore these sources for loop header phis. */
9004 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9007 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9008 operands
[num_operands
++] = op
;
9009 num_defined
+= !op
.isUndefined();
9011 /* handle block_kind_continue_or_break at loop exit blocks */
9012 while (cur_pred_idx
++ < preds
.size())
9013 operands
[num_operands
++] = Operand(dst
.regClass());
9015 /* If the loop ends with a break, still add a linear continue edge in case
9016 * that break is divergent or continue_or_break is used. We'll either remove
9017 * this operand later in visit_loop() if it's not necessary or replace the
9018 * undef with something correct. */
9019 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9020 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9021 nir_block
*last
= nir_loop_last_block(loop
);
9022 if (last
->successors
[0] != instr
->instr
.block
)
9023 operands
[num_operands
++] = Operand(RegClass());
9026 if (num_defined
== 0) {
9027 Builder
bld(ctx
->program
, ctx
->block
);
9028 if (dst
.regClass() == s1
) {
9029 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9030 } else if (dst
.regClass() == v1
) {
9031 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9033 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9034 for (unsigned i
= 0; i
< dst
.size(); i
++)
9035 vec
->operands
[i
] = Operand(0u);
9036 vec
->definitions
[0] = Definition(dst
);
9037 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9042 /* we can use a linear phi in some cases if one src is undef */
9043 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9044 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9046 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9047 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9048 assert(invert
->kind
& block_kind_invert
);
9050 unsigned then_block
= invert
->linear_preds
[0];
9052 Block
* insert_block
= NULL
;
9053 for (unsigned i
= 0; i
< num_operands
; i
++) {
9054 Operand op
= operands
[i
];
9055 if (op
.isUndefined())
9057 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9058 phi
->operands
[0] = op
;
9061 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9062 phi
->operands
[1] = Operand(dst
.regClass());
9063 phi
->definitions
[0] = Definition(dst
);
9064 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9068 /* try to scalarize vector phis */
9069 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9070 // TODO: scalarize linear phis on divergent ifs
9071 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9072 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9073 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9074 Operand src
= operands
[i
];
9075 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9076 can_scalarize
= false;
9078 if (can_scalarize
) {
9079 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9080 assert(dst
.size() % num_components
== 0);
9081 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9083 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9084 for (unsigned k
= 0; k
< num_components
; k
++) {
9085 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9086 for (unsigned i
= 0; i
< num_operands
; i
++) {
9087 Operand src
= operands
[i
];
9088 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9090 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9091 phi
->definitions
[0] = Definition(phi_dst
);
9092 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9093 new_vec
[k
] = phi_dst
;
9094 vec
->operands
[k
] = Operand(phi_dst
);
9096 vec
->definitions
[0] = Definition(dst
);
9097 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9098 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9103 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9104 for (unsigned i
= 0; i
< num_operands
; i
++)
9105 phi
->operands
[i
] = operands
[i
];
9106 phi
->definitions
[0] = Definition(dst
);
9107 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9111 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9113 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9115 assert(dst
.type() == RegType::sgpr
);
9117 if (dst
.size() == 1) {
9118 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9120 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9121 for (unsigned i
= 0; i
< dst
.size(); i
++)
9122 vec
->operands
[i
] = Operand(0u);
9123 vec
->definitions
[0] = Definition(dst
);
9124 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9128 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9130 Builder
bld(ctx
->program
, ctx
->block
);
9131 Block
*logical_target
;
9132 append_logical_end(ctx
->block
);
9133 unsigned idx
= ctx
->block
->index
;
9135 switch (instr
->type
) {
9136 case nir_jump_break
:
9137 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9138 add_logical_edge(idx
, logical_target
);
9139 ctx
->block
->kind
|= block_kind_break
;
9141 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9142 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9143 /* uniform break - directly jump out of the loop */
9144 ctx
->block
->kind
|= block_kind_uniform
;
9145 ctx
->cf_info
.has_branch
= true;
9146 bld
.branch(aco_opcode::p_branch
);
9147 add_linear_edge(idx
, logical_target
);
9150 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9151 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9153 case nir_jump_continue
:
9154 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9155 add_logical_edge(idx
, logical_target
);
9156 ctx
->block
->kind
|= block_kind_continue
;
9158 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9159 /* for potential uniform breaks after this continue,
9160 we must ensure that they are handled correctly */
9161 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9162 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9163 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9165 /* uniform continue - directly jump to the loop header */
9166 ctx
->block
->kind
|= block_kind_uniform
;
9167 ctx
->cf_info
.has_branch
= true;
9168 bld
.branch(aco_opcode::p_branch
);
9169 add_linear_edge(idx
, logical_target
);
9174 isel_err(&instr
->instr
, "Unknown NIR jump instr");
9178 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9179 ctx
->cf_info
.exec_potentially_empty_break
= true;
9180 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9183 /* remove critical edges from linear CFG */
9184 bld
.branch(aco_opcode::p_branch
);
9185 Block
* break_block
= ctx
->program
->create_and_insert_block();
9186 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9187 break_block
->kind
|= block_kind_uniform
;
9188 add_linear_edge(idx
, break_block
);
9189 /* the loop_header pointer might be invalidated by this point */
9190 if (instr
->type
== nir_jump_continue
)
9191 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9192 add_linear_edge(break_block
->index
, logical_target
);
9193 bld
.reset(break_block
);
9194 bld
.branch(aco_opcode::p_branch
);
9196 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9197 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9198 add_linear_edge(idx
, continue_block
);
9199 append_logical_start(continue_block
);
9200 ctx
->block
= continue_block
;
9204 void visit_block(isel_context
*ctx
, nir_block
*block
)
9206 nir_foreach_instr(instr
, block
) {
9207 switch (instr
->type
) {
9208 case nir_instr_type_alu
:
9209 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9211 case nir_instr_type_load_const
:
9212 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9214 case nir_instr_type_intrinsic
:
9215 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9217 case nir_instr_type_tex
:
9218 visit_tex(ctx
, nir_instr_as_tex(instr
));
9220 case nir_instr_type_phi
:
9221 visit_phi(ctx
, nir_instr_as_phi(instr
));
9223 case nir_instr_type_ssa_undef
:
9224 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9226 case nir_instr_type_deref
:
9228 case nir_instr_type_jump
:
9229 visit_jump(ctx
, nir_instr_as_jump(instr
));
9232 isel_err(instr
, "Unknown NIR instr type");
9237 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9238 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9243 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9244 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9246 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9247 RegClass rc
= vals
[0].regClass();
9249 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9251 unsigned next_pred
= 1;
9253 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9254 Block
& block
= ctx
->program
->blocks
[idx
];
9255 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9256 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9260 if (block
.kind
& block_kind_continue
) {
9261 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9266 bool all_same
= true;
9267 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9268 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9272 val
= vals
[block
.linear_preds
[0] - first
];
9274 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9275 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9276 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9277 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9278 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9279 phi
->definitions
[0] = Definition(val
.getTemp());
9280 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9282 vals
[idx
- first
] = val
;
9285 return vals
[last
- first
];
9288 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9290 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9291 append_logical_end(ctx
->block
);
9292 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9293 Builder
bld(ctx
->program
, ctx
->block
);
9294 bld
.branch(aco_opcode::p_branch
);
9295 unsigned loop_preheader_idx
= ctx
->block
->index
;
9297 Block loop_exit
= Block();
9298 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9299 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9301 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9302 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9303 loop_header
->kind
|= block_kind_loop_header
;
9304 add_edge(loop_preheader_idx
, loop_header
);
9305 ctx
->block
= loop_header
;
9307 /* emit loop body */
9308 unsigned loop_header_idx
= loop_header
->index
;
9309 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9310 append_logical_start(ctx
->block
);
9311 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9313 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9314 if (!ctx
->cf_info
.has_branch
) {
9315 append_logical_end(ctx
->block
);
9316 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9317 /* Discards can result in code running with an empty exec mask.
9318 * This would result in divergent breaks not ever being taken. As a
9319 * workaround, break the loop when the loop mask is empty instead of
9320 * always continuing. */
9321 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9322 unsigned block_idx
= ctx
->block
->index
;
9324 /* create helper blocks to avoid critical edges */
9325 Block
*break_block
= ctx
->program
->create_and_insert_block();
9326 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9327 break_block
->kind
= block_kind_uniform
;
9328 bld
.reset(break_block
);
9329 bld
.branch(aco_opcode::p_branch
);
9330 add_linear_edge(block_idx
, break_block
);
9331 add_linear_edge(break_block
->index
, &loop_exit
);
9333 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9334 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9335 continue_block
->kind
= block_kind_uniform
;
9336 bld
.reset(continue_block
);
9337 bld
.branch(aco_opcode::p_branch
);
9338 add_linear_edge(block_idx
, continue_block
);
9339 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9341 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9342 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9343 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9345 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9346 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9347 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9349 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9352 bld
.reset(ctx
->block
);
9353 bld
.branch(aco_opcode::p_branch
);
9356 /* Fixup phis in loop header from unreachable blocks.
9357 * has_branch/has_divergent_branch also indicates if the loop ends with a
9358 * break/continue instruction, but we don't emit those if unreachable=true */
9360 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9361 bool linear
= ctx
->cf_info
.has_branch
;
9362 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9363 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9364 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9365 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9366 /* the last operand should be the one that needs to be removed */
9367 instr
->operands
.pop_back();
9368 } else if (!is_phi(instr
)) {
9374 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9375 * and the previous one shouldn't both happen at once because a break in the
9376 * merge block would get CSE'd */
9377 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9378 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9379 Operand vals
[num_vals
];
9380 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9381 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9382 if (ctx
->cf_info
.has_branch
)
9383 instr
->operands
.pop_back();
9385 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9386 } else if (!is_phi(instr
)) {
9392 ctx
->cf_info
.has_branch
= false;
9394 // TODO: if the loop has not a single exit, we must add one °°
9395 /* emit loop successor block */
9396 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9397 append_logical_start(ctx
->block
);
9400 // TODO: check if it is beneficial to not branch on continues
9401 /* trim linear phis in loop header */
9402 for (auto&& instr
: loop_entry
->instructions
) {
9403 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9404 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9405 new_phi
->definitions
[0] = instr
->definitions
[0];
9406 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9407 new_phi
->operands
[i
] = instr
->operands
[i
];
9408 /* check that the remaining operands are all the same */
9409 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9410 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9411 instr
.swap(new_phi
);
9412 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9421 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9425 append_logical_end(ctx
->block
);
9426 ctx
->block
->kind
|= block_kind_branch
;
9428 /* branch to linear then block */
9429 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9430 aco_ptr
<Pseudo_branch_instruction
> branch
;
9431 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9432 branch
->operands
[0] = Operand(cond
);
9433 ctx
->block
->instructions
.push_back(std::move(branch
));
9435 ic
->BB_if_idx
= ctx
->block
->index
;
9436 ic
->BB_invert
= Block();
9437 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9438 /* Invert blocks are intentionally not marked as top level because they
9439 * are not part of the logical cfg. */
9440 ic
->BB_invert
.kind
|= block_kind_invert
;
9441 ic
->BB_endif
= Block();
9442 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9443 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9445 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9446 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9447 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9448 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9449 ctx
->cf_info
.parent_if
.is_divergent
= true;
9451 /* divergent branches use cbranch_execz */
9452 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9453 ctx
->cf_info
.exec_potentially_empty_break
= false;
9454 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9456 /** emit logical then block */
9457 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9458 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9459 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9460 ctx
->block
= BB_then_logical
;
9461 append_logical_start(BB_then_logical
);
9464 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9466 Block
*BB_then_logical
= ctx
->block
;
9467 append_logical_end(BB_then_logical
);
9468 /* branch from logical then block to invert block */
9469 aco_ptr
<Pseudo_branch_instruction
> branch
;
9470 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9471 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9472 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9473 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9474 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9475 BB_then_logical
->kind
|= block_kind_uniform
;
9476 assert(!ctx
->cf_info
.has_branch
);
9477 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9478 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9480 /** emit linear then block */
9481 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9482 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9483 BB_then_linear
->kind
|= block_kind_uniform
;
9484 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9485 /* branch from linear then block to invert block */
9486 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9487 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9488 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9490 /** emit invert merge block */
9491 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9492 ic
->invert_idx
= ctx
->block
->index
;
9494 /* branch to linear else block (skip else) */
9495 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9496 branch
->operands
[0] = Operand(ic
->cond
);
9497 ctx
->block
->instructions
.push_back(std::move(branch
));
9499 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9500 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9501 ic
->exec_potentially_empty_break_depth_old
=
9502 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9503 /* divergent branches use cbranch_execz */
9504 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9505 ctx
->cf_info
.exec_potentially_empty_break
= false;
9506 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9508 /** emit logical else block */
9509 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9510 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9511 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9512 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9513 ctx
->block
= BB_else_logical
;
9514 append_logical_start(BB_else_logical
);
9517 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9519 Block
*BB_else_logical
= ctx
->block
;
9520 append_logical_end(BB_else_logical
);
9522 /* branch from logical else block to endif block */
9523 aco_ptr
<Pseudo_branch_instruction
> branch
;
9524 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9525 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9526 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9527 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9528 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9529 BB_else_logical
->kind
|= block_kind_uniform
;
9531 assert(!ctx
->cf_info
.has_branch
);
9532 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9535 /** emit linear else block */
9536 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9537 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9538 BB_else_linear
->kind
|= block_kind_uniform
;
9539 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9541 /* branch from linear else block to endif block */
9542 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9543 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9544 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9547 /** emit endif merge block */
9548 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9549 append_logical_start(ctx
->block
);
9552 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9553 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9554 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9555 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9556 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9557 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9558 !ctx
->cf_info
.parent_if
.is_divergent
) {
9559 ctx
->cf_info
.exec_potentially_empty_break
= false;
9560 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9562 /* uniform control flow never has an empty exec-mask */
9563 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9564 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9565 ctx
->cf_info
.exec_potentially_empty_break
= false;
9566 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9570 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9572 assert(cond
.regClass() == s1
);
9574 append_logical_end(ctx
->block
);
9575 ctx
->block
->kind
|= block_kind_uniform
;
9577 aco_ptr
<Pseudo_branch_instruction
> branch
;
9578 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9579 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9580 branch
->operands
[0] = Operand(cond
);
9581 branch
->operands
[0].setFixed(scc
);
9582 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9584 ic
->BB_if_idx
= ctx
->block
->index
;
9585 ic
->BB_endif
= Block();
9586 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9587 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9589 ctx
->cf_info
.has_branch
= false;
9590 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9592 /** emit then block */
9593 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9594 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9595 add_edge(ic
->BB_if_idx
, BB_then
);
9596 append_logical_start(BB_then
);
9597 ctx
->block
= BB_then
;
9600 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9602 Block
*BB_then
= ctx
->block
;
9604 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9605 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9607 if (!ic
->uniform_has_then_branch
) {
9608 append_logical_end(BB_then
);
9609 /* branch from then block to endif block */
9610 aco_ptr
<Pseudo_branch_instruction
> branch
;
9611 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9612 BB_then
->instructions
.emplace_back(std::move(branch
));
9613 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9614 if (!ic
->then_branch_divergent
)
9615 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9616 BB_then
->kind
|= block_kind_uniform
;
9619 ctx
->cf_info
.has_branch
= false;
9620 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9622 /** emit else block */
9623 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9624 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9625 add_edge(ic
->BB_if_idx
, BB_else
);
9626 append_logical_start(BB_else
);
9627 ctx
->block
= BB_else
;
9630 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9632 Block
*BB_else
= ctx
->block
;
9634 if (!ctx
->cf_info
.has_branch
) {
9635 append_logical_end(BB_else
);
9636 /* branch from then block to endif block */
9637 aco_ptr
<Pseudo_branch_instruction
> branch
;
9638 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9639 BB_else
->instructions
.emplace_back(std::move(branch
));
9640 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9641 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9642 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9643 BB_else
->kind
|= block_kind_uniform
;
9646 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9647 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9649 /** emit endif merge block */
9650 if (!ctx
->cf_info
.has_branch
) {
9651 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9652 append_logical_start(ctx
->block
);
9656 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9658 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9659 Builder
bld(ctx
->program
, ctx
->block
);
9660 aco_ptr
<Pseudo_branch_instruction
> branch
;
9663 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9665 * Uniform conditionals are represented in the following way*) :
9667 * The linear and logical CFG:
9670 * BB_THEN (logical) BB_ELSE (logical)
9674 * *) Exceptions may be due to break and continue statements within loops
9675 * If a break/continue happens within uniform control flow, it branches
9676 * to the loop exit/entry block. Otherwise, it branches to the next
9680 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9681 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9682 cond
= bool_to_scalar_condition(ctx
, cond
);
9684 begin_uniform_if_then(ctx
, &ic
, cond
);
9685 visit_cf_list(ctx
, &if_stmt
->then_list
);
9687 begin_uniform_if_else(ctx
, &ic
);
9688 visit_cf_list(ctx
, &if_stmt
->else_list
);
9690 end_uniform_if(ctx
, &ic
);
9691 } else { /* non-uniform condition */
9693 * To maintain a logical and linear CFG without critical edges,
9694 * non-uniform conditionals are represented in the following way*) :
9699 * BB_THEN (logical) BB_THEN (linear)
9701 * BB_INVERT (linear)
9703 * BB_ELSE (logical) BB_ELSE (linear)
9710 * BB_THEN (logical) BB_ELSE (logical)
9714 * *) Exceptions may be due to break and continue statements within loops
9717 begin_divergent_if_then(ctx
, &ic
, cond
);
9718 visit_cf_list(ctx
, &if_stmt
->then_list
);
9720 begin_divergent_if_else(ctx
, &ic
);
9721 visit_cf_list(ctx
, &if_stmt
->else_list
);
9723 end_divergent_if(ctx
, &ic
);
9726 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9729 static bool visit_cf_list(isel_context
*ctx
,
9730 struct exec_list
*list
)
9732 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9733 switch (node
->type
) {
9734 case nir_cf_node_block
:
9735 visit_block(ctx
, nir_cf_node_as_block(node
));
9737 case nir_cf_node_if
:
9738 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9741 case nir_cf_node_loop
:
9742 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9745 unreachable("unimplemented cf list type");
9751 static void create_null_export(isel_context
*ctx
)
9753 /* Some shader stages always need to have exports.
9754 * So when there is none, we need to add a null export.
9757 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9758 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9759 Builder
bld(ctx
->program
, ctx
->block
);
9760 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9761 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9764 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9766 assert(ctx
->stage
== vertex_vs
||
9767 ctx
->stage
== tess_eval_vs
||
9768 ctx
->stage
== gs_copy_vs
||
9769 ctx
->stage
== ngg_vertex_gs
||
9770 ctx
->stage
== ngg_tess_eval_gs
);
9772 int offset
= (ctx
->stage
& sw_tes
)
9773 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9774 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9775 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9776 if (!is_pos
&& !mask
)
9778 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9780 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9781 exp
->enabled_mask
= mask
;
9782 for (unsigned i
= 0; i
< 4; ++i
) {
9783 if (mask
& (1 << i
))
9784 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9786 exp
->operands
[i
] = Operand(v1
);
9788 /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9789 * Setting valid_mask=1 prevents it and has no other effect.
9791 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& is_pos
&& *next_pos
== 0;
9793 exp
->compressed
= false;
9795 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9797 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9798 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9803 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9805 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9806 exp
->enabled_mask
= 0;
9807 for (unsigned i
= 0; i
< 4; ++i
)
9808 exp
->operands
[i
] = Operand(v1
);
9809 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9810 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9811 exp
->enabled_mask
|= 0x1;
9813 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9814 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9815 exp
->enabled_mask
|= 0x4;
9817 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9818 if (ctx
->options
->chip_class
< GFX9
) {
9819 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9820 exp
->enabled_mask
|= 0x8;
9822 Builder
bld(ctx
->program
, ctx
->block
);
9824 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9825 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9826 if (exp
->operands
[2].isTemp())
9827 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9829 exp
->operands
[2] = Operand(out
);
9830 exp
->enabled_mask
|= 0x4;
9833 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& *next_pos
== 0;
9835 exp
->compressed
= false;
9836 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9837 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9840 static void create_export_phis(isel_context
*ctx
)
9842 /* Used when exports are needed, but the output temps are defined in a preceding block.
9843 * This function will set up phis in order to access the outputs in the next block.
9846 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9847 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9848 ctx
->block
->instructions
.pop_back();
9850 Builder
bld(ctx
->program
, ctx
->block
);
9852 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9853 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9854 for (unsigned i
= 0; i
< 4; ++i
) {
9855 if (!(mask
& (1 << i
)))
9858 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9859 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9860 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9864 bld
.insert(std::move(logical_start
));
9867 static void create_vs_exports(isel_context
*ctx
)
9869 assert(ctx
->stage
== vertex_vs
||
9870 ctx
->stage
== tess_eval_vs
||
9871 ctx
->stage
== gs_copy_vs
||
9872 ctx
->stage
== ngg_vertex_gs
||
9873 ctx
->stage
== ngg_tess_eval_gs
);
9875 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9876 ? &ctx
->program
->info
->tes
.outinfo
9877 : &ctx
->program
->info
->vs
.outinfo
;
9879 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9880 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9881 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9884 if (ctx
->options
->key
.has_multiview_view_index
) {
9885 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9886 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9889 /* the order these position exports are created is important */
9891 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9892 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9893 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9894 exported_pos
= true;
9896 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9897 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9898 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9899 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9901 if (ctx
->export_clip_dists
) {
9902 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9903 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9904 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9905 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9908 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9909 if (i
< VARYING_SLOT_VAR0
&&
9910 i
!= VARYING_SLOT_LAYER
&&
9911 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9912 i
!= VARYING_SLOT_VIEWPORT
)
9915 export_vs_varying(ctx
, i
, false, NULL
);
9919 create_null_export(ctx
);
9922 static bool export_fs_mrt_z(isel_context
*ctx
)
9924 Builder
bld(ctx
->program
, ctx
->block
);
9925 unsigned enabled_channels
= 0;
9929 for (unsigned i
= 0; i
< 4; ++i
) {
9930 values
[i
] = Operand(v1
);
9933 /* Both stencil and sample mask only need 16-bits. */
9934 if (!ctx
->program
->info
->ps
.writes_z
&&
9935 (ctx
->program
->info
->ps
.writes_stencil
||
9936 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9937 compr
= true; /* COMPR flag */
9939 if (ctx
->program
->info
->ps
.writes_stencil
) {
9940 /* Stencil should be in X[23:16]. */
9941 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9942 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9943 enabled_channels
|= 0x3;
9946 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9947 /* SampleMask should be in Y[15:0]. */
9948 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9949 enabled_channels
|= 0xc;
9952 if (ctx
->program
->info
->ps
.writes_z
) {
9953 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9954 enabled_channels
|= 0x1;
9957 if (ctx
->program
->info
->ps
.writes_stencil
) {
9958 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9959 enabled_channels
|= 0x2;
9962 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9963 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9964 enabled_channels
|= 0x4;
9968 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9969 * writemask component.
9971 if (ctx
->options
->chip_class
== GFX6
&&
9972 ctx
->options
->family
!= CHIP_OLAND
&&
9973 ctx
->options
->family
!= CHIP_HAINAN
) {
9974 enabled_channels
|= 0x1;
9977 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9978 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9983 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9985 Builder
bld(ctx
->program
, ctx
->block
);
9986 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9989 for (unsigned i
= 0; i
< 4; ++i
) {
9990 if (write_mask
& (1 << i
)) {
9991 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9993 values
[i
] = Operand(v1
);
9997 unsigned target
, col_format
;
9998 unsigned enabled_channels
= 0;
9999 aco_opcode compr_op
= (aco_opcode
)0;
10001 slot
-= FRAG_RESULT_DATA0
;
10002 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10003 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10005 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10006 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10007 bool is_16bit
= values
[0].regClass() == v2b
;
10009 switch (col_format
)
10011 case V_028714_SPI_SHADER_ZERO
:
10012 enabled_channels
= 0; /* writemask */
10013 target
= V_008DFC_SQ_EXP_NULL
;
10016 case V_028714_SPI_SHADER_32_R
:
10017 enabled_channels
= 1;
10020 case V_028714_SPI_SHADER_32_GR
:
10021 enabled_channels
= 0x3;
10024 case V_028714_SPI_SHADER_32_AR
:
10025 if (ctx
->options
->chip_class
>= GFX10
) {
10026 /* Special case: on GFX10, the outputs are different for 32_AR */
10027 enabled_channels
= 0x3;
10028 values
[1] = values
[3];
10029 values
[3] = Operand(v1
);
10031 enabled_channels
= 0x9;
10035 case V_028714_SPI_SHADER_FP16_ABGR
:
10036 enabled_channels
= 0x5;
10037 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10039 if (ctx
->options
->chip_class
>= GFX9
) {
10040 /* Pack the FP16 values together instead of converting them to
10041 * FP32 and back to FP16.
10042 * TODO: use p_create_vector and let the compiler optimizes.
10044 compr_op
= aco_opcode::v_pack_b32_f16
;
10046 for (unsigned i
= 0; i
< 4; i
++) {
10047 if ((write_mask
>> i
) & 1)
10048 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10054 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10055 enabled_channels
= 0x5;
10056 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10057 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10059 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10063 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10064 enabled_channels
= 0x5;
10065 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10066 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10068 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10072 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10073 enabled_channels
= 0x5;
10074 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10075 if (is_int8
|| is_int10
) {
10077 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10078 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10080 for (unsigned i
= 0; i
< 4; i
++) {
10081 if ((write_mask
>> i
) & 1) {
10082 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10083 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10087 } else if (is_16bit
) {
10088 for (unsigned i
= 0; i
< 4; i
++) {
10089 if ((write_mask
>> i
) & 1) {
10090 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10091 values
[i
] = Operand(tmp
);
10098 case V_028714_SPI_SHADER_SINT16_ABGR
:
10099 enabled_channels
= 0x5;
10100 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10101 if (is_int8
|| is_int10
) {
10103 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10104 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10105 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10106 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10108 for (unsigned i
= 0; i
< 4; i
++) {
10109 if ((write_mask
>> i
) & 1) {
10110 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10111 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10113 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10114 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10118 } else if (is_16bit
) {
10119 for (unsigned i
= 0; i
< 4; i
++) {
10120 if ((write_mask
>> i
) & 1) {
10121 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10122 values
[i
] = Operand(tmp
);
10128 case V_028714_SPI_SHADER_32_ABGR
:
10129 enabled_channels
= 0xF;
10136 if (target
== V_008DFC_SQ_EXP_NULL
)
10139 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10140 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10142 (col_format
== V_028714_SPI_SHADER_32_R
||
10143 col_format
== V_028714_SPI_SHADER_32_GR
||
10144 col_format
== V_028714_SPI_SHADER_32_AR
||
10145 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10146 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10147 for (int i
= 0; i
< 4; i
++) {
10148 if (!(write_mask
& (1 << i
)))
10151 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10152 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10153 bld
.copy(bld
.def(v1
), Operand(3u)));
10154 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10155 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10159 if ((bool) compr_op
) {
10160 for (int i
= 0; i
< 2; i
++) {
10161 /* check if at least one of the values to be compressed is enabled */
10162 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10164 enabled_channels
|= enabled
<< (i
*2);
10165 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10166 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10167 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10169 values
[i
] = Operand(v1
);
10172 values
[2] = Operand(v1
);
10173 values
[3] = Operand(v1
);
10175 for (int i
= 0; i
< 4; i
++)
10176 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10179 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10180 enabled_channels
, target
, (bool) compr_op
);
10184 static void create_fs_exports(isel_context
*ctx
)
10186 bool exported
= false;
10188 /* Export depth, stencil and sample mask. */
10189 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10190 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10191 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10192 exported
|= export_fs_mrt_z(ctx
);
10194 /* Export all color render targets. */
10195 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10196 if (ctx
->outputs
.mask
[i
])
10197 exported
|= export_fs_mrt_color(ctx
, i
);
10200 create_null_export(ctx
);
10203 static void create_workgroup_barrier(Builder
& bld
)
10205 bld
.barrier(aco_opcode::p_barrier
,
10206 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10210 static void write_tcs_tess_factors(isel_context
*ctx
)
10212 unsigned outer_comps
;
10213 unsigned inner_comps
;
10215 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10232 Builder
bld(ctx
->program
, ctx
->block
);
10234 create_workgroup_barrier(bld
);
10236 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10237 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10239 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10240 if_context ic_invocation_id_is_zero
;
10241 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10242 bld
.reset(ctx
->block
);
10244 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10246 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10247 unsigned stride
= inner_comps
+ outer_comps
;
10248 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10252 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10254 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10256 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10257 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10258 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10260 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10261 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10263 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10264 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10265 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10266 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10269 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10270 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10271 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10272 unsigned tf_const_offset
= 0;
10274 if (ctx
->program
->chip_class
<= GFX8
) {
10275 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10276 if_context ic_rel_patch_id_is_zero
;
10277 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10278 bld
.reset(ctx
->block
);
10280 /* Store the dynamic HS control word. */
10281 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10282 bld
.mubuf(aco_opcode::buffer_store_dword
,
10283 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10284 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10285 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10286 tf_const_offset
+= 4;
10288 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10289 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10290 bld
.reset(ctx
->block
);
10293 assert(stride
== 2 || stride
== 4 || stride
== 6);
10294 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10295 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10297 /* Store to offchip for TES to read - only if TES reads them */
10298 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10299 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10300 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10302 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10303 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10305 if (likely(inner_comps
)) {
10306 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10307 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10311 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10312 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10315 static void emit_stream_output(isel_context
*ctx
,
10316 Temp
const *so_buffers
,
10317 Temp
const *so_write_offset
,
10318 const struct radv_stream_output
*output
)
10320 unsigned num_comps
= util_bitcount(output
->component_mask
);
10321 unsigned writemask
= (1 << num_comps
) - 1;
10322 unsigned loc
= output
->location
;
10323 unsigned buf
= output
->buffer
;
10325 assert(num_comps
&& num_comps
<= 4);
10326 if (!num_comps
|| num_comps
> 4)
10329 unsigned start
= ffs(output
->component_mask
) - 1;
10332 bool all_undef
= true;
10333 assert(ctx
->stage
& hw_vs
);
10334 for (unsigned i
= 0; i
< num_comps
; i
++) {
10335 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10336 all_undef
= all_undef
&& !out
[i
].id();
10341 while (writemask
) {
10343 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10344 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10345 /* GFX6 doesn't support storing vec3, split it. */
10346 writemask
|= 1u << (start
+ 2);
10350 unsigned offset
= output
->offset
+ start
* 4;
10352 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10353 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10354 for (int i
= 0; i
< count
; ++i
)
10355 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10356 vec
->definitions
[0] = Definition(write_data
);
10357 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10362 opcode
= aco_opcode::buffer_store_dword
;
10365 opcode
= aco_opcode::buffer_store_dwordx2
;
10368 opcode
= aco_opcode::buffer_store_dwordx3
;
10371 opcode
= aco_opcode::buffer_store_dwordx4
;
10374 unreachable("Unsupported dword count.");
10377 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10378 store
->operands
[0] = Operand(so_buffers
[buf
]);
10379 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10380 store
->operands
[2] = Operand((uint32_t) 0);
10381 store
->operands
[3] = Operand(write_data
);
10382 if (offset
> 4095) {
10383 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10384 Builder
bld(ctx
->program
, ctx
->block
);
10385 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10387 store
->offset
= offset
;
10389 store
->offen
= true;
10391 store
->dlc
= false;
10393 ctx
->block
->instructions
.emplace_back(std::move(store
));
10397 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10399 Builder
bld(ctx
->program
, ctx
->block
);
10401 Temp so_buffers
[4];
10402 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10403 for (unsigned i
= 0; i
< 4; i
++) {
10404 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10408 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10409 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10412 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10413 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10415 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10417 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10420 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10422 bld
.reset(ctx
->block
);
10424 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10426 Temp so_write_offset
[4];
10428 for (unsigned i
= 0; i
< 4; i
++) {
10429 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10434 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10435 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10436 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10437 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10439 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10441 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10442 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10443 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10444 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10448 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10449 struct radv_stream_output
*output
=
10450 &ctx
->program
->info
->so
.outputs
[i
];
10451 if (stream
!= output
->stream
)
10454 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10457 begin_divergent_if_else(ctx
, &ic
);
10458 end_divergent_if(ctx
, &ic
);
10461 } /* end namespace */
10463 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10465 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10466 Builder
bld(ctx
->program
, ctx
->block
);
10467 constexpr unsigned hs_idx
= 1u;
10468 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10469 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10470 Operand((8u << 16) | (hs_idx
* 8u)));
10471 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10473 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10475 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10476 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10477 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10478 ls_has_nonzero_hs_threads
);
10479 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10480 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10481 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10482 ls_has_nonzero_hs_threads
);
10483 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10484 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10485 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10486 ls_has_nonzero_hs_threads
);
10488 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10489 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10490 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10493 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10495 /* Split all arguments except for the first (ring_offsets) and the last
10496 * (exec) so that the dead channels don't stay live throughout the program.
10498 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10499 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10500 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10501 startpgm
->definitions
[i
].regClass().size());
10506 void handle_bc_optimize(isel_context
*ctx
)
10508 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10509 Builder
bld(ctx
->program
, ctx
->block
);
10510 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10511 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10512 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10513 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10514 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10515 if (uses_center
&& uses_centroid
) {
10516 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10517 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10519 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10521 for (unsigned i
= 0; i
< 2; i
++) {
10522 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10523 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10524 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10525 persp_centroid
, persp_center
, sel
);
10527 ctx
->persp_centroid
= bld
.tmp(v2
);
10528 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10529 Operand(new_coord
[0]), Operand(new_coord
[1]));
10530 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10533 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10535 for (unsigned i
= 0; i
< 2; i
++) {
10536 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10537 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10538 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10539 linear_centroid
, linear_center
, sel
);
10541 ctx
->linear_centroid
= bld
.tmp(v2
);
10542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10543 Operand(new_coord
[0]), Operand(new_coord
[1]));
10544 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10549 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10551 Program
*program
= ctx
->program
;
10553 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10555 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10556 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10557 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10558 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10559 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10561 program
->next_fp_mode
.must_flush_denorms32
=
10562 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10563 program
->next_fp_mode
.must_flush_denorms16_64
=
10564 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10565 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10567 program
->next_fp_mode
.care_about_round32
=
10568 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10570 program
->next_fp_mode
.care_about_round16_64
=
10571 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10572 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10574 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10575 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10576 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10577 program
->next_fp_mode
.denorm16_64
= 0;
10579 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10581 /* preserving fp32 denorms is expensive, so only do it if asked */
10582 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10583 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10585 program
->next_fp_mode
.denorm32
= 0;
10587 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10588 program
->next_fp_mode
.round32
= fp_round_tz
;
10590 program
->next_fp_mode
.round32
= fp_round_ne
;
10592 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10593 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10595 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10597 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10600 void cleanup_cfg(Program
*program
)
10602 /* create linear_succs/logical_succs */
10603 for (Block
& BB
: program
->blocks
) {
10604 for (unsigned idx
: BB
.linear_preds
)
10605 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10606 for (unsigned idx
: BB
.logical_preds
)
10607 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10611 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10613 Builder
bld(ctx
->program
, ctx
->block
);
10615 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10616 Temp count
= i
== 0
10617 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10618 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10619 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10621 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10624 if (ctx
->program
->wave_size
== 64) {
10625 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10626 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10627 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10629 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10630 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10636 bool ngg_early_prim_export(isel_context
*ctx
)
10638 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10642 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10644 Builder
bld(ctx
->program
, ctx
->block
);
10646 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10647 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10649 /* Get the id of the current wave within the threadgroup (workgroup) */
10650 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10651 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10653 /* Execute the following code only on the first wave (wave id 0),
10654 * use the SCC def to tell if the wave id is zero or not.
10656 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10658 begin_uniform_if_then(ctx
, &ic
, cond
);
10659 begin_uniform_if_else(ctx
, &ic
);
10660 bld
.reset(ctx
->block
);
10662 /* Number of vertices output by VS/TES */
10663 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10664 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10665 /* Number of primitives output by VS/TES */
10666 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10667 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10669 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10670 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10671 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10673 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10674 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10676 end_uniform_if(ctx
, &ic
);
10678 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10679 bld
.reset(ctx
->block
);
10680 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10683 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10685 Builder
bld(ctx
->program
, ctx
->block
);
10687 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10688 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10691 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10694 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10695 assert(vtxindex
[i
].id());
10698 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10702 /* The initial edge flag is always false in tess eval shaders. */
10703 if (ctx
->stage
== ngg_vertex_gs
) {
10704 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10705 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10709 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10714 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10716 Builder
bld(ctx
->program
, ctx
->block
);
10717 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10719 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10720 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10721 false /* compressed */, true/* done */, false /* valid mask */);
10724 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10726 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10727 * These must always come before VS exports.
10729 * It is recommended to do these as early as possible. They can be at the beginning when
10730 * there is no SW GS and the shader doesn't write edge flags.
10734 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10735 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10737 Builder
bld(ctx
->program
, ctx
->block
);
10738 constexpr unsigned max_vertices_per_primitive
= 3;
10739 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10741 if (ctx
->stage
== ngg_vertex_gs
) {
10742 /* TODO: optimize for points & lines */
10743 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10744 if (ctx
->shader
->info
.tess
.point_mode
)
10745 num_vertices_per_primitive
= 1;
10746 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10747 num_vertices_per_primitive
= 2;
10749 unreachable("Unsupported NGG shader stage");
10752 Temp vtxindex
[max_vertices_per_primitive
];
10753 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10754 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10755 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10756 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10757 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10758 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10759 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10760 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10762 /* Export primitive data to the index buffer. */
10763 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10765 /* Export primitive ID. */
10766 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10767 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10768 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10769 Temp provoking_vtx_index
= vtxindex
[0];
10770 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10772 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10775 begin_divergent_if_else(ctx
, &ic
);
10776 end_divergent_if(ctx
, &ic
);
10779 void ngg_emit_nogs_output(isel_context
*ctx
)
10781 /* Emits NGG GS output, for stages that don't have SW GS. */
10784 Builder
bld(ctx
->program
, ctx
->block
);
10785 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10787 /* NGG streamout is currently disabled by default. */
10788 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10790 if (late_prim_export
) {
10791 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10792 create_export_phis(ctx
);
10793 /* Do what we need to do in the GS threads. */
10794 ngg_emit_nogs_gsthreads(ctx
);
10796 /* What comes next should be executed on ES threads. */
10797 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10798 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10799 bld
.reset(ctx
->block
);
10802 /* Export VS outputs */
10803 ctx
->block
->kind
|= block_kind_export_end
;
10804 create_vs_exports(ctx
);
10806 /* Export primitive ID */
10807 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10810 if (ctx
->stage
== ngg_vertex_gs
) {
10811 /* Wait for GS threads to store primitive ID in LDS. */
10812 create_workgroup_barrier(bld
);
10814 /* Calculate LDS address where the GS threads stored the primitive ID. */
10815 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10816 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10817 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10818 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10819 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10820 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10822 /* Load primitive ID from LDS. */
10823 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10824 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10825 /* TES: Just use the patch ID as the primitive ID. */
10826 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10828 unreachable("unsupported NGG shader stage.");
10831 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10832 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10834 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10837 if (late_prim_export
) {
10838 begin_divergent_if_else(ctx
, &ic
);
10839 end_divergent_if(ctx
, &ic
);
10840 bld
.reset(ctx
->block
);
10844 void select_program(Program
*program
,
10845 unsigned shader_count
,
10846 struct nir_shader
*const *shaders
,
10847 ac_shader_config
* config
,
10848 struct radv_shader_args
*args
)
10850 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10851 if_context ic_merged_wave_info
;
10852 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10854 for (unsigned i
= 0; i
< shader_count
; i
++) {
10855 nir_shader
*nir
= shaders
[i
];
10856 init_context(&ctx
, nir
);
10858 setup_fp_mode(&ctx
, nir
);
10861 /* needs to be after init_context() for FS */
10862 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10863 append_logical_start(ctx
.block
);
10865 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10866 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10868 split_arguments(&ctx
, startpgm
);
10872 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10874 if (ngg_early_prim_export(&ctx
))
10875 ngg_emit_nogs_gsthreads(&ctx
);
10878 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10879 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10880 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10881 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10882 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10883 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10884 ctx
.stage
== tess_eval_geometry_gs
));
10886 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10887 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10888 if (check_merged_wave_info
) {
10889 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10890 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10894 Builder
bld(ctx
.program
, ctx
.block
);
10896 create_workgroup_barrier(bld
);
10898 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10899 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10901 } else if (ctx
.stage
== geometry_gs
)
10902 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10904 if (ctx
.stage
== fragment_fs
)
10905 handle_bc_optimize(&ctx
);
10907 visit_cf_list(&ctx
, &func
->body
);
10909 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10910 emit_streamout(&ctx
, 0);
10912 if (ctx
.stage
& hw_vs
) {
10913 create_vs_exports(&ctx
);
10914 ctx
.block
->kind
|= block_kind_export_end
;
10915 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10916 ngg_emit_nogs_output(&ctx
);
10917 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10918 Builder
bld(ctx
.program
, ctx
.block
);
10919 bld
.barrier(aco_opcode::p_barrier
,
10920 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
10921 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10922 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10923 write_tcs_tess_factors(&ctx
);
10926 if (ctx
.stage
== fragment_fs
) {
10927 create_fs_exports(&ctx
);
10928 ctx
.block
->kind
|= block_kind_export_end
;
10931 if (endif_merged_wave_info
) {
10932 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10933 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10936 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10937 ngg_emit_nogs_output(&ctx
);
10939 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10940 /* Outputs of the previous stage are inputs to the next stage */
10941 ctx
.inputs
= ctx
.outputs
;
10942 ctx
.outputs
= shader_io_state();
10946 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10948 append_logical_end(ctx
.block
);
10949 ctx
.block
->kind
|= block_kind_uniform
;
10950 Builder
bld(ctx
.program
, ctx
.block
);
10951 if (ctx
.program
->wb_smem_l1_on_end
)
10952 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
10953 bld
.sopp(aco_opcode::s_endpgm
);
10955 cleanup_cfg(program
);
10958 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10959 ac_shader_config
* config
,
10960 struct radv_shader_args
*args
)
10962 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10964 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10966 add_startpgm(&ctx
);
10967 append_logical_start(ctx
.block
);
10969 Builder
bld(ctx
.program
, ctx
.block
);
10971 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10973 Operand
stream_id(0u);
10974 if (args
->shader_info
->so
.num_outputs
)
10975 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10976 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10978 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10980 std::stack
<Block
> endif_blocks
;
10982 for (unsigned stream
= 0; stream
< 4; stream
++) {
10983 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10986 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10987 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10990 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10992 unsigned BB_if_idx
= ctx
.block
->index
;
10993 Block BB_endif
= Block();
10994 if (!stream_id
.isConstant()) {
10996 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10997 append_logical_end(ctx
.block
);
10998 ctx
.block
->kind
|= block_kind_uniform
;
10999 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11001 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11003 ctx
.block
= ctx
.program
->create_and_insert_block();
11004 add_edge(BB_if_idx
, ctx
.block
);
11005 bld
.reset(ctx
.block
);
11006 append_logical_start(ctx
.block
);
11009 unsigned offset
= 0;
11010 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11011 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11014 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11015 unsigned length
= util_last_bit(output_usage_mask
);
11016 for (unsigned j
= 0; j
< length
; ++j
) {
11017 if (!(output_usage_mask
& (1 << j
)))
11020 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11021 Temp voffset
= vtx_offset
;
11022 if (const_offset
>= 4096u) {
11023 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11024 const_offset
%= 4096u;
11027 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11028 mubuf
->definitions
[0] = bld
.def(v1
);
11029 mubuf
->operands
[0] = Operand(gsvs_ring
);
11030 mubuf
->operands
[1] = Operand(voffset
);
11031 mubuf
->operands
[2] = Operand(0u);
11032 mubuf
->offen
= true;
11033 mubuf
->offset
= const_offset
;
11036 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11038 ctx
.outputs
.mask
[i
] |= 1 << j
;
11039 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11041 bld
.insert(std::move(mubuf
));
11047 if (args
->shader_info
->so
.num_outputs
) {
11048 emit_streamout(&ctx
, stream
);
11049 bld
.reset(ctx
.block
);
11053 create_vs_exports(&ctx
);
11054 ctx
.block
->kind
|= block_kind_export_end
;
11057 if (!stream_id
.isConstant()) {
11058 append_logical_end(ctx
.block
);
11060 /* branch from then block to endif block */
11061 bld
.branch(aco_opcode::p_branch
);
11062 add_edge(ctx
.block
->index
, &BB_endif
);
11063 ctx
.block
->kind
|= block_kind_uniform
;
11065 /* emit else block */
11066 ctx
.block
= ctx
.program
->create_and_insert_block();
11067 add_edge(BB_if_idx
, ctx
.block
);
11068 bld
.reset(ctx
.block
);
11069 append_logical_start(ctx
.block
);
11071 endif_blocks
.push(std::move(BB_endif
));
11075 while (!endif_blocks
.empty()) {
11076 Block BB_endif
= std::move(endif_blocks
.top());
11077 endif_blocks
.pop();
11079 Block
*BB_else
= ctx
.block
;
11081 append_logical_end(BB_else
);
11082 /* branch from else block to endif block */
11083 bld
.branch(aco_opcode::p_branch
);
11084 add_edge(BB_else
->index
, &BB_endif
);
11085 BB_else
->kind
|= block_kind_uniform
;
11087 /** emit endif merge block */
11088 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11089 bld
.reset(ctx
.block
);
11090 append_logical_start(ctx
.block
);
11093 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11095 append_logical_end(ctx
.block
);
11096 ctx
.block
->kind
|= block_kind_uniform
;
11097 bld
.sopp(aco_opcode::s_endpgm
);
11099 cleanup_cfg(program
);