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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
139 } else if (ctx
->program
->chip_class
<= GFX7
) {
140 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
143 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
148 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
150 Builder
bld(ctx
->program
, ctx
->block
);
153 dst
= bld
.tmp(src
.regClass());
155 assert(src
.size() == dst
.size());
157 if (ctx
->stage
!= fragment_fs
) {
161 bld
.copy(Definition(dst
), src
);
165 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
166 ctx
->program
->needs_wqm
|= program_needs_wqm
;
170 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
172 if (index
.regClass() == s1
)
173 return bld
.readlane(bld
.def(s1
), data
, index
);
175 if (ctx
->options
->chip_class
<= GFX7
) {
176 /* GFX6-7: there is no bpermute instruction */
177 Operand
index_op(index
);
178 Operand
input_data(data
);
179 index_op
.setLateKill(true);
180 input_data
.setLateKill(true);
182 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
183 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
184 /* GFX10 wave64 mode: emulate full-wave bpermute */
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
192 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
193 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
194 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
195 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
196 Operand
input_data(data
);
198 index_x4
.setLateKill(true);
199 input_data
.setLateKill(true);
200 same_half
.setLateKill(true);
202 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
204 /* GFX8-9 or GFX10 wave32: bpermute works normally */
205 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
206 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
210 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
212 if (ctx
->options
->chip_class
>= GFX8
) {
213 unsigned and_mask
= mask
& 0x1f;
214 unsigned or_mask
= (mask
>> 5) & 0x1f;
215 unsigned xor_mask
= (mask
>> 10) & 0x1f;
217 uint16_t dpp_ctrl
= 0xffff;
219 // TODO: we could use DPP8 for some swizzles
220 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
221 unsigned res
[4] = {0, 1, 2, 3};
222 for (unsigned i
= 0; i
< 4; i
++)
223 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
224 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
225 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
226 dpp_ctrl
= dpp_row_rr(8);
227 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
228 dpp_ctrl
= dpp_row_mirror
;
229 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
230 dpp_ctrl
= dpp_row_half_mirror
;
233 if (dpp_ctrl
!= 0xffff)
234 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
237 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
240 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
242 if (val
.type() == RegType::sgpr
) {
243 Builder
bld(ctx
->program
, ctx
->block
);
244 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
246 assert(val
.type() == RegType::vgpr
);
250 //assumes a != 0xffffffff
251 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
254 Builder
bld(ctx
->program
, ctx
->block
);
256 if (util_is_power_of_two_or_zero(b
)) {
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
261 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
263 assert(info
.multiplier
<= 0xffffffff);
265 bool pre_shift
= info
.pre_shift
!= 0;
266 bool increment
= info
.increment
!= 0;
267 bool multiply
= true;
268 bool post_shift
= info
.post_shift
!= 0;
270 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
271 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
275 Temp pre_shift_dst
= a
;
277 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
278 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
281 Temp increment_dst
= pre_shift_dst
;
283 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
284 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
287 Temp multiply_dst
= increment_dst
;
289 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
290 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
291 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
299 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
301 Builder
bld(ctx
->program
, ctx
->block
);
302 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
306 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
308 /* no need to extract the whole vector */
309 if (src
.regClass() == dst_rc
) {
314 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
315 Builder
bld(ctx
->program
, ctx
->block
);
316 auto it
= ctx
->allocated_vec
.find(src
.id());
317 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
318 if (it
->second
[idx
].regClass() == dst_rc
) {
319 return it
->second
[idx
];
321 assert(!dst_rc
.is_subdword());
322 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
323 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
327 if (dst_rc
.is_subdword())
328 src
= as_vgpr(ctx
, src
);
330 if (src
.bytes() == dst_rc
.bytes()) {
332 return bld
.copy(bld
.def(dst_rc
), src
);
334 Temp dst
= bld
.tmp(dst_rc
);
335 emit_extract_vector(ctx
, src
, idx
, dst
);
340 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
342 if (num_components
== 1)
344 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
347 if (num_components
> vec_src
.size()) {
348 if (vec_src
.type() == RegType::sgpr
) {
349 /* should still help get_alu_src() */
350 emit_split_vector(ctx
, vec_src
, vec_src
.size());
353 /* sub-dword split */
354 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
356 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
358 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
359 split
->operands
[0] = Operand(vec_src
);
360 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
361 for (unsigned i
= 0; i
< num_components
; i
++) {
362 elems
[i
] = {ctx
->program
->allocateId(), rc
};
363 split
->definitions
[i
] = Definition(elems
[i
]);
365 ctx
->block
->instructions
.emplace_back(std::move(split
));
366 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
369 /* This vector expansion uses a mask to determine which elements in the new vector
370 * come from the original vector. The other elements are undefined. */
371 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
373 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
378 Builder
bld(ctx
->program
, ctx
->block
);
379 if (num_components
== 1) {
380 if (dst
.type() == RegType::sgpr
)
381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
383 bld
.copy(Definition(dst
), vec_src
);
387 unsigned component_size
= dst
.size() / num_components
;
388 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
390 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
391 vec
->definitions
[0] = Definition(dst
);
393 for (unsigned i
= 0; i
< num_components
; i
++) {
394 if (mask
& (1 << i
)) {
395 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
396 if (dst
.type() == RegType::sgpr
)
397 src
= bld
.as_uniform(src
);
398 vec
->operands
[i
] = Operand(src
);
400 vec
->operands
[i
] = Operand(0u);
402 elems
[i
] = vec
->operands
[i
].getTemp();
404 ctx
->block
->instructions
.emplace_back(std::move(vec
));
405 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
408 /* adjust misaligned small bit size loads */
409 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
411 Builder
bld(ctx
->program
, ctx
->block
);
413 Temp select
= Temp();
414 if (offset
.isConstant()) {
415 assert(offset
.constantValue() && offset
.constantValue() < 4);
416 shift
= Operand(offset
.constantValue() * 8);
418 /* bit_offset = 8 * (offset & 0x3) */
419 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
420 select
= bld
.tmp(s1
);
421 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
424 if (vec
.size() == 1) {
425 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
426 } else if (vec
.size() == 2) {
427 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
428 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
430 emit_split_vector(ctx
, dst
, 2);
432 emit_extract_vector(ctx
, tmp
, 0, dst
);
433 } else if (vec
.size() == 4) {
434 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
435 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
436 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
437 if (select
!= Temp())
438 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
439 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
440 Temp mid
= bld
.tmp(s1
);
441 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
442 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
443 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
444 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
445 emit_split_vector(ctx
, dst
, 2);
449 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
451 Builder
bld(ctx
->program
, ctx
->block
);
452 if (offset
.isTemp()) {
453 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
455 if (vec
.size() == 4) {
456 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
458 } else if (vec
.size() == 3) {
459 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
461 } else if (vec
.size() == 2) {
462 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
465 for (unsigned i
= 0; i
< dst
.size(); i
++)
466 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
470 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
472 offset
= Operand(0u);
475 unsigned num_components
= vec
.bytes() / component_size
;
476 if (vec
.regClass() == dst
.regClass()) {
477 assert(offset
.constantValue() == 0);
478 bld
.copy(Definition(dst
), vec
);
479 emit_split_vector(ctx
, dst
, num_components
);
483 emit_split_vector(ctx
, vec
, num_components
);
484 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
485 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
487 assert(offset
.constantValue() % component_size
== 0);
488 unsigned skip
= offset
.constantValue() / component_size
;
489 for (unsigned i
= skip
; i
< num_components
; i
++)
490 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
492 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
493 if (dst
.type() == RegType::vgpr
) {
494 num_components
= dst
.bytes() / component_size
;
495 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
496 for (unsigned i
= 0; i
< num_components
; i
++)
497 create_vec
->operands
[i
] = Operand(elems
[i
]);
498 create_vec
->definitions
[0] = Definition(dst
);
499 bld
.insert(std::move(create_vec
));
501 /* if dst is sgpr - split the src, but move the original to sgpr. */
503 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
504 byte_align_scalar(ctx
, vec
, offset
, dst
);
506 assert(dst
.size() == vec
.size());
507 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
510 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
513 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
515 Builder
bld(ctx
->program
, ctx
->block
);
517 dst
= bld
.tmp(bld
.lm
);
519 assert(val
.regClass() == s1
);
520 assert(dst
.regClass() == bld
.lm
);
522 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
525 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
527 Builder
bld(ctx
->program
, ctx
->block
);
531 assert(val
.regClass() == bld
.lm
);
532 assert(dst
.regClass() == s1
);
534 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
535 Temp tmp
= bld
.tmp(s1
);
536 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
537 return emit_wqm(ctx
, tmp
, dst
);
540 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
542 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
543 return get_ssa_temp(ctx
, src
.src
.ssa
);
545 if (src
.src
.ssa
->num_components
== size
) {
546 bool identity_swizzle
= true;
547 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
548 if (src
.swizzle
[i
] != i
)
549 identity_swizzle
= false;
551 if (identity_swizzle
)
552 return get_ssa_temp(ctx
, src
.src
.ssa
);
555 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
556 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
557 assert(elem_size
> 0);
558 assert(vec
.bytes() % elem_size
== 0);
560 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
561 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
563 unsigned swizzle
= src
.swizzle
[0];
564 if (vec
.size() > 1) {
565 assert(src
.src
.ssa
->bit_size
== 16);
566 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
567 swizzle
= swizzle
& 1;
572 Temp dst
{ctx
->program
->allocateId(), s1
};
573 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
574 bfe
->operands
[0] = Operand(vec
);
575 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
576 bfe
->definitions
[0] = Definition(dst
);
577 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
578 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
582 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
584 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
587 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
588 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
589 for (unsigned i
= 0; i
< size
; ++i
) {
590 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
591 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
593 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
594 vec_instr
->definitions
[0] = Definition(dst
);
595 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
596 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
601 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
605 Builder
bld(ctx
->program
, ctx
->block
);
606 if (ptr
.type() == RegType::vgpr
)
607 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
608 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
609 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
612 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
614 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
615 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
616 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
617 sop2
->definitions
[0] = Definition(dst
);
618 if (instr
->no_unsigned_wrap
)
619 sop2
->definitions
[0].setNUW(true);
621 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
622 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
625 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
626 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
628 Builder
bld(ctx
->program
, ctx
->block
);
629 bld
.is_precise
= instr
->exact
;
631 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
632 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
633 if (src1
.type() == RegType::sgpr
) {
634 if (commutative
&& src0
.type() == RegType::vgpr
) {
639 src1
= as_vgpr(ctx
, src1
);
643 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
644 assert(dst
.size() == 1);
645 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
646 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
648 bld
.vop2(op
, Definition(dst
), src0
, src1
);
652 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
653 aco_opcode op
, Temp dst
)
655 Builder
bld(ctx
->program
, ctx
->block
);
656 bld
.is_precise
= instr
->exact
;
658 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
659 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
661 if (src1
.type() == RegType::sgpr
) {
662 assert(src0
.type() == RegType::vgpr
);
663 std::swap(src0
, src1
);
666 Temp src00
= bld
.tmp(src0
.type(), 1);
667 Temp src01
= bld
.tmp(src0
.type(), 1);
668 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
669 Temp src10
= bld
.tmp(v1
);
670 Temp src11
= bld
.tmp(v1
);
671 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
672 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
673 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
674 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
677 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
678 bool flush_denorms
= false)
680 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
681 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
682 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
684 /* ensure that the instruction has at most 1 sgpr operand
685 * The optimizer will inline constants for us */
686 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
687 src0
= as_vgpr(ctx
, src0
);
688 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
689 src1
= as_vgpr(ctx
, src1
);
690 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
691 src2
= as_vgpr(ctx
, src2
);
693 Builder
bld(ctx
->program
, ctx
->block
);
694 bld
.is_precise
= instr
->exact
;
695 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
696 assert(dst
.size() == 1);
697 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
698 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
700 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
704 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
706 Builder
bld(ctx
->program
, ctx
->block
);
707 bld
.is_precise
= instr
->exact
;
708 if (dst
.type() == RegType::sgpr
)
709 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
710 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
712 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
715 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
717 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
718 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
719 assert(src0
.size() == src1
.size());
721 aco_ptr
<Instruction
> vopc
;
722 if (src1
.type() == RegType::sgpr
) {
723 if (src0
.type() == RegType::vgpr
) {
724 /* to swap the operands, we might also have to change the opcode */
726 case aco_opcode::v_cmp_lt_f16
:
727 op
= aco_opcode::v_cmp_gt_f16
;
729 case aco_opcode::v_cmp_ge_f16
:
730 op
= aco_opcode::v_cmp_le_f16
;
732 case aco_opcode::v_cmp_lt_i16
:
733 op
= aco_opcode::v_cmp_gt_i16
;
735 case aco_opcode::v_cmp_ge_i16
:
736 op
= aco_opcode::v_cmp_le_i16
;
738 case aco_opcode::v_cmp_lt_u16
:
739 op
= aco_opcode::v_cmp_gt_u16
;
741 case aco_opcode::v_cmp_ge_u16
:
742 op
= aco_opcode::v_cmp_le_u16
;
744 case aco_opcode::v_cmp_lt_f32
:
745 op
= aco_opcode::v_cmp_gt_f32
;
747 case aco_opcode::v_cmp_ge_f32
:
748 op
= aco_opcode::v_cmp_le_f32
;
750 case aco_opcode::v_cmp_lt_i32
:
751 op
= aco_opcode::v_cmp_gt_i32
;
753 case aco_opcode::v_cmp_ge_i32
:
754 op
= aco_opcode::v_cmp_le_i32
;
756 case aco_opcode::v_cmp_lt_u32
:
757 op
= aco_opcode::v_cmp_gt_u32
;
759 case aco_opcode::v_cmp_ge_u32
:
760 op
= aco_opcode::v_cmp_le_u32
;
762 case aco_opcode::v_cmp_lt_f64
:
763 op
= aco_opcode::v_cmp_gt_f64
;
765 case aco_opcode::v_cmp_ge_f64
:
766 op
= aco_opcode::v_cmp_le_f64
;
768 case aco_opcode::v_cmp_lt_i64
:
769 op
= aco_opcode::v_cmp_gt_i64
;
771 case aco_opcode::v_cmp_ge_i64
:
772 op
= aco_opcode::v_cmp_le_i64
;
774 case aco_opcode::v_cmp_lt_u64
:
775 op
= aco_opcode::v_cmp_gt_u64
;
777 case aco_opcode::v_cmp_ge_u64
:
778 op
= aco_opcode::v_cmp_le_u64
;
780 default: /* eq and ne are commutative */
787 src1
= as_vgpr(ctx
, src1
);
791 Builder
bld(ctx
->program
, ctx
->block
);
792 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
795 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
797 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
798 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
799 Builder
bld(ctx
->program
, ctx
->block
);
801 assert(dst
.regClass() == bld
.lm
);
802 assert(src0
.type() == RegType::sgpr
);
803 assert(src1
.type() == RegType::sgpr
);
804 assert(src0
.regClass() == src1
.regClass());
806 /* Emit the SALU comparison instruction */
807 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
808 /* Turn the result into a per-lane bool */
809 bool_to_vector_condition(ctx
, cmp
, dst
);
812 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
813 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
815 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
816 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
817 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
818 nir_dest_is_divergent(instr
->dest
.dest
) ||
819 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
820 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
821 aco_opcode op
= use_valu
? v_op
: s_op
;
822 assert(op
!= aco_opcode::num_opcodes
);
823 assert(dst
.regClass() == ctx
->program
->lane_mask
);
826 emit_vopc_instruction(ctx
, instr
, op
, dst
);
828 emit_sopc_instruction(ctx
, instr
, op
, dst
);
831 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
833 Builder
bld(ctx
->program
, ctx
->block
);
834 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
835 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
837 assert(dst
.regClass() == bld
.lm
);
838 assert(src0
.regClass() == bld
.lm
);
839 assert(src1
.regClass() == bld
.lm
);
841 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
844 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
846 Builder
bld(ctx
->program
, ctx
->block
);
847 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
848 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
849 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
851 assert(cond
.regClass() == bld
.lm
);
853 if (dst
.type() == RegType::vgpr
) {
854 aco_ptr
<Instruction
> bcsel
;
855 if (dst
.size() == 1) {
856 then
= as_vgpr(ctx
, then
);
857 els
= as_vgpr(ctx
, els
);
859 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
860 } else if (dst
.size() == 2) {
861 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
863 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
864 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
866 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
867 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
872 nir_print_instr(&instr
->instr
, stderr
);
873 fprintf(stderr
, "\n");
878 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
879 assert(dst
.regClass() == bld
.lm
);
880 assert(then
.regClass() == bld
.lm
);
881 assert(els
.regClass() == bld
.lm
);
884 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
885 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
886 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
887 assert(dst
.size() == then
.size());
888 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
889 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
891 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
892 nir_print_instr(&instr
->instr
, stderr
);
893 fprintf(stderr
, "\n");
898 /* divergent boolean bcsel
899 * this implements bcsel on bools: dst = s0 ? s1 : s2
900 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
901 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
903 if (cond
.id() != then
.id())
904 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
906 if (cond
.id() == els
.id())
907 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
909 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
910 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
913 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
914 aco_opcode op
, uint32_t undo
)
916 /* multiply by 16777216 to handle denormals */
917 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
918 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
919 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
920 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
921 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
923 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
925 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
928 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
930 if (ctx
->block
->fp_mode
.denorm32
== 0) {
931 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
935 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
938 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
940 if (ctx
->block
->fp_mode
.denorm32
== 0) {
941 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
945 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
948 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
950 if (ctx
->block
->fp_mode
.denorm32
== 0) {
951 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
955 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
958 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
960 if (ctx
->block
->fp_mode
.denorm32
== 0) {
961 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
965 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
968 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
970 if (ctx
->options
->chip_class
>= GFX7
)
971 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
973 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
974 /* TODO: create more efficient code! */
975 if (val
.type() == RegType::sgpr
)
976 val
= as_vgpr(ctx
, val
);
978 /* Split the input value. */
979 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
980 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
982 /* Extract the exponent and compute the unbiased value. */
983 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
984 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
986 /* Extract the fractional part. */
987 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
988 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
990 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
991 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
993 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
994 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
995 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
996 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
997 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
999 /* Get the sign bit. */
1000 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1002 /* Decide the operation to apply depending on the unbiased exponent. */
1003 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1004 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1005 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1006 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1007 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1008 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1010 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1013 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1015 if (ctx
->options
->chip_class
>= GFX7
)
1016 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1018 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1019 * lowered at NIR level for precision reasons). */
1020 Temp src0
= as_vgpr(ctx
, val
);
1022 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1023 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1025 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1026 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1027 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1029 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1030 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1031 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1032 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1034 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1035 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1037 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1039 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1040 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1042 return add
->definitions
[0].getTemp();
1045 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1047 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1048 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1050 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1053 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1054 return bld
.copy(Definition(dst
), src
);
1055 else if (dst
.bytes() < src
.bytes())
1056 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1060 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1063 } else if (src
.regClass() == s1
) {
1065 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1067 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1068 } else if (ctx
->options
->chip_class
>= GFX8
) {
1069 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1070 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1071 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1072 sdwa
->operands
[0] = Operand(src
);
1073 sdwa
->definitions
[0] = Definition(tmp
);
1075 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1077 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1078 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1079 bld
.insert(std::move(sdwa
));
1081 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1082 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1083 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1086 if (dst_bits
== 64) {
1087 if (is_signed
&& dst
.regClass() == s2
) {
1088 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1089 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1090 } else if (is_signed
&& dst
.regClass() == v2
) {
1091 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1092 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1094 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1101 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1103 if (!instr
->dest
.dest
.is_ssa
) {
1104 fprintf(stderr
, "nir alu dst not in ssa: ");
1105 nir_print_instr(&instr
->instr
, stderr
);
1106 fprintf(stderr
, "\n");
1109 Builder
bld(ctx
->program
, ctx
->block
);
1110 bld
.is_precise
= instr
->exact
;
1111 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1116 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1117 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1118 for (unsigned i
= 0; i
< num
; ++i
)
1119 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1121 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1122 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1123 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1124 for (unsigned i
= 0; i
< num
; ++i
) {
1125 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1126 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1128 vec
->operands
[i
] = Operand
{elems
[i
]};
1130 vec
->definitions
[0] = Definition(dst
);
1131 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1132 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1134 // TODO: that is a bit suboptimal..
1135 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1136 for (unsigned i
= 0; i
< num
- 1; ++i
)
1137 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1138 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1139 for (unsigned i
= 0; i
< num
; ++i
) {
1140 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1141 if (bit
% 32 == 0) {
1142 elems
[bit
/ 32] = elems
[i
];
1144 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1145 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1146 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1149 if (dst
.size() == 1)
1150 bld
.copy(Definition(dst
), elems
[0]);
1152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1157 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1158 aco_ptr
<Instruction
> mov
;
1159 if (dst
.type() == RegType::sgpr
) {
1160 if (src
.type() == RegType::vgpr
)
1161 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1162 else if (src
.regClass() == s1
)
1163 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1164 else if (src
.regClass() == s2
)
1165 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1167 unreachable("wrong src register class for nir_op_imov");
1169 if (dst
.regClass() == v1
)
1170 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1171 else if (dst
.regClass() == v1b
||
1172 dst
.regClass() == v2b
||
1173 dst
.regClass() == v2
)
1174 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1176 unreachable("wrong src register class for nir_op_imov");
1181 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1182 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1183 assert(src
.regClass() == bld
.lm
);
1184 assert(dst
.regClass() == bld
.lm
);
1185 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1186 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1187 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1188 } else if (dst
.regClass() == v1
) {
1189 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1190 } else if (dst
.regClass() == v2
) {
1191 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1192 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1193 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1194 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1196 } else if (dst
.type() == RegType::sgpr
) {
1197 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1198 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1200 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1201 nir_print_instr(&instr
->instr
, stderr
);
1202 fprintf(stderr
, "\n");
1207 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1208 if (dst
.regClass() == v1
) {
1209 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1210 } else if (dst
.regClass() == s1
) {
1211 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1212 } else if (dst
.size() == 2) {
1213 Temp src0
= bld
.tmp(dst
.type(), 1);
1214 Temp src1
= bld
.tmp(dst
.type(), 1);
1215 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1217 if (dst
.regClass() == s2
) {
1218 Temp carry
= bld
.tmp(s1
);
1219 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1220 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1221 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1223 Temp lower
= bld
.tmp(v1
);
1224 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1225 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == s1
) {
1237 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1238 } else if (dst
.regClass() == v1
) {
1239 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1240 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1242 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1243 nir_print_instr(&instr
->instr
, stderr
);
1244 fprintf(stderr
, "\n");
1248 case nir_op_isign
: {
1249 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1250 if (dst
.regClass() == s1
) {
1251 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1252 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1253 } else if (dst
.regClass() == s2
) {
1254 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1256 if (ctx
->program
->chip_class
>= GFX8
)
1257 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1259 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1260 /* SCC gets zero-extended to 64 bit */
1261 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1262 } else if (dst
.regClass() == v1
) {
1263 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1264 } else if (dst
.regClass() == v2
) {
1265 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1266 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1267 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1268 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1269 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1270 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1272 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1273 nir_print_instr(&instr
->instr
, stderr
);
1274 fprintf(stderr
, "\n");
1279 if (dst
.regClass() == v1
) {
1280 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1281 } else if (dst
.regClass() == s1
) {
1282 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1291 if (dst
.regClass() == v1
) {
1292 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1293 } else if (dst
.regClass() == s1
) {
1294 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1296 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1297 nir_print_instr(&instr
->instr
, stderr
);
1298 fprintf(stderr
, "\n");
1303 if (dst
.regClass() == v1
) {
1304 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1305 } else if (dst
.regClass() == s1
) {
1306 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1308 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1309 nir_print_instr(&instr
->instr
, stderr
);
1310 fprintf(stderr
, "\n");
1315 if (dst
.regClass() == v1
) {
1316 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1317 } else if (dst
.regClass() == s1
) {
1318 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1320 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1321 nir_print_instr(&instr
->instr
, stderr
);
1322 fprintf(stderr
, "\n");
1327 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1328 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1329 } else if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1331 } else if (dst
.regClass() == v2
) {
1332 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1333 } else if (dst
.regClass() == s1
) {
1334 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1335 } else if (dst
.regClass() == s2
) {
1336 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1338 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1339 nir_print_instr(&instr
->instr
, stderr
);
1340 fprintf(stderr
, "\n");
1345 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1346 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1347 } else if (dst
.regClass() == v1
) {
1348 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1349 } else if (dst
.regClass() == v2
) {
1350 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1351 } else if (dst
.regClass() == s1
) {
1352 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1353 } else if (dst
.regClass() == s2
) {
1354 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1356 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1357 nir_print_instr(&instr
->instr
, stderr
);
1358 fprintf(stderr
, "\n");
1363 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1364 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1365 } else if (dst
.regClass() == v1
) {
1366 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1367 } else if (dst
.regClass() == v2
) {
1368 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1369 } else if (dst
.regClass() == s1
) {
1370 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1371 } else if (dst
.regClass() == s2
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1374 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1375 nir_print_instr(&instr
->instr
, stderr
);
1376 fprintf(stderr
, "\n");
1381 if (dst
.regClass() == v1
) {
1382 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1383 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1384 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1385 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1386 } else if (dst
.regClass() == v2
) {
1387 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1388 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1391 } else if (dst
.regClass() == s1
) {
1392 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1401 if (dst
.regClass() == v1
) {
1402 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1403 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1404 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1405 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1406 } else if (dst
.regClass() == v2
) {
1407 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1408 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1409 } else if (dst
.regClass() == s1
) {
1410 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1411 } else if (dst
.regClass() == s2
) {
1412 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1414 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1415 nir_print_instr(&instr
->instr
, stderr
);
1416 fprintf(stderr
, "\n");
1421 if (dst
.regClass() == v1
) {
1422 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1423 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1424 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1425 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1426 } else if (dst
.regClass() == v2
) {
1427 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1428 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1429 } else if (dst
.regClass() == s1
) {
1430 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1431 } else if (dst
.regClass() == s2
) {
1432 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1434 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1435 nir_print_instr(&instr
->instr
, stderr
);
1436 fprintf(stderr
, "\n");
1440 case nir_op_find_lsb
: {
1441 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1442 if (src
.regClass() == s1
) {
1443 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1444 } else if (src
.regClass() == v1
) {
1445 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1446 } else if (src
.regClass() == s2
) {
1447 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1449 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1450 nir_print_instr(&instr
->instr
, stderr
);
1451 fprintf(stderr
, "\n");
1455 case nir_op_ufind_msb
:
1456 case nir_op_ifind_msb
: {
1457 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1458 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1459 aco_opcode op
= src
.regClass() == s2
?
1460 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1461 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1462 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1464 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1465 Operand(src
.size() * 32u - 1u), msb_rev
);
1466 Temp msb
= sub
.def(0).getTemp();
1467 Temp carry
= sub
.def(1).getTemp();
1469 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1470 } else if (src
.regClass() == v1
) {
1471 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1472 Temp msb_rev
= bld
.tmp(v1
);
1473 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1474 Temp msb
= bld
.tmp(v1
);
1475 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1476 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1478 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1479 nir_print_instr(&instr
->instr
, stderr
);
1480 fprintf(stderr
, "\n");
1484 case nir_op_bitfield_reverse
: {
1485 if (dst
.regClass() == s1
) {
1486 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1487 } else if (dst
.regClass() == v1
) {
1488 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1497 if (dst
.regClass() == s1
) {
1498 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1502 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1503 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1504 if (dst
.regClass() == v1
) {
1505 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1509 assert(src0
.size() == 2 && src1
.size() == 2);
1510 Temp src00
= bld
.tmp(src0
.type(), 1);
1511 Temp src01
= bld
.tmp(dst
.type(), 1);
1512 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1513 Temp src10
= bld
.tmp(src1
.type(), 1);
1514 Temp src11
= bld
.tmp(dst
.type(), 1);
1515 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1517 if (dst
.regClass() == s2
) {
1518 Temp carry
= bld
.tmp(s1
);
1519 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1520 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1521 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1522 } else if (dst
.regClass() == v2
) {
1523 Temp dst0
= bld
.tmp(v1
);
1524 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1525 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1526 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1528 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1529 nir_print_instr(&instr
->instr
, stderr
);
1530 fprintf(stderr
, "\n");
1534 case nir_op_uadd_sat
: {
1535 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1536 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1537 if (dst
.regClass() == s1
) {
1538 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1539 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1541 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1542 } else if (dst
.regClass() == v1
) {
1543 if (ctx
->options
->chip_class
>= GFX9
) {
1544 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1545 add
->operands
[0] = Operand(src0
);
1546 add
->operands
[1] = Operand(src1
);
1547 add
->definitions
[0] = Definition(dst
);
1549 ctx
->block
->instructions
.emplace_back(std::move(add
));
1551 if (src1
.regClass() != v1
)
1552 std::swap(src0
, src1
);
1553 assert(src1
.regClass() == v1
);
1554 Temp tmp
= bld
.tmp(v1
);
1555 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1556 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1560 nir_print_instr(&instr
->instr
, stderr
);
1561 fprintf(stderr
, "\n");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1596 nir_print_instr(&instr
->instr
, stderr
);
1597 fprintf(stderr
, "\n");
1602 if (dst
.regClass() == s1
) {
1603 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1607 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1608 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1609 if (dst
.regClass() == v1
) {
1610 bld
.vsub32(Definition(dst
), src0
, src1
);
1614 Temp src00
= bld
.tmp(src0
.type(), 1);
1615 Temp src01
= bld
.tmp(dst
.type(), 1);
1616 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1617 Temp src10
= bld
.tmp(src1
.type(), 1);
1618 Temp src11
= bld
.tmp(dst
.type(), 1);
1619 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1620 if (dst
.regClass() == s2
) {
1621 Temp carry
= bld
.tmp(s1
);
1622 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1623 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1625 } else if (dst
.regClass() == v2
) {
1626 Temp lower
= bld
.tmp(v1
);
1627 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1628 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1629 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_usub_borrow
: {
1638 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1639 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1640 if (dst
.regClass() == s1
) {
1641 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1643 } else if (dst
.regClass() == v1
) {
1644 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1645 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1649 Temp src00
= bld
.tmp(src0
.type(), 1);
1650 Temp src01
= bld
.tmp(dst
.type(), 1);
1651 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1652 Temp src10
= bld
.tmp(src1
.type(), 1);
1653 Temp src11
= bld
.tmp(dst
.type(), 1);
1654 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1655 if (dst
.regClass() == s2
) {
1656 Temp borrow
= bld
.tmp(s1
);
1657 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1658 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1659 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1660 } else if (dst
.regClass() == v2
) {
1661 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1662 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1663 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1664 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1666 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1667 nir_print_instr(&instr
->instr
, stderr
);
1668 fprintf(stderr
, "\n");
1673 if (dst
.regClass() == v1
) {
1674 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1675 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1676 } else if (dst
.regClass() == s1
) {
1677 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1685 case nir_op_umul_high
: {
1686 if (dst
.regClass() == v1
) {
1687 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1688 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1689 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1690 } else if (dst
.regClass() == s1
) {
1691 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1692 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1693 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1695 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1696 nir_print_instr(&instr
->instr
, stderr
);
1697 fprintf(stderr
, "\n");
1701 case nir_op_imul_high
: {
1702 if (dst
.regClass() == v1
) {
1703 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1704 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1705 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1706 } else if (dst
.regClass() == s1
) {
1707 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1708 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1709 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1711 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1712 nir_print_instr(&instr
->instr
, stderr
);
1713 fprintf(stderr
, "\n");
1718 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1719 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1720 if (dst
.regClass() == v2b
) {
1721 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1722 } else if (dst
.regClass() == v1
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1724 } else if (dst
.regClass() == v2
) {
1725 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1727 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1728 nir_print_instr(&instr
->instr
, stderr
);
1729 fprintf(stderr
, "\n");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1736 if (dst
.regClass() == v2b
) {
1737 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1738 } else if (dst
.regClass() == v1
) {
1739 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1740 } else if (dst
.regClass() == v2
) {
1741 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1743 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1744 nir_print_instr(&instr
->instr
, stderr
);
1745 fprintf(stderr
, "\n");
1750 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1751 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1752 if (dst
.regClass() == v2b
) {
1753 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1754 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1756 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1757 } else if (dst
.regClass() == v1
) {
1758 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1759 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1762 } else if (dst
.regClass() == v2
) {
1763 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1764 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1765 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1769 nir_print_instr(&instr
->instr
, stderr
);
1770 fprintf(stderr
, "\n");
1775 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1776 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1777 if (dst
.regClass() == v2b
) {
1778 // TODO: check fp_mode.must_flush_denorms16_64
1779 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1780 } else if (dst
.regClass() == v1
) {
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1782 } else if (dst
.regClass() == v2
) {
1783 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1784 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1785 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1787 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1791 nir_print_instr(&instr
->instr
, stderr
);
1792 fprintf(stderr
, "\n");
1797 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1798 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1799 if (dst
.regClass() == v2b
) {
1800 // TODO: check fp_mode.must_flush_denorms16_64
1801 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1802 } else if (dst
.regClass() == v1
) {
1803 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1804 } else if (dst
.regClass() == v2
) {
1805 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1806 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1807 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1809 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1812 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1813 nir_print_instr(&instr
->instr
, stderr
);
1814 fprintf(stderr
, "\n");
1818 case nir_op_fmax3
: {
1819 if (dst
.regClass() == v2b
) {
1820 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1821 } else if (dst
.regClass() == v1
) {
1822 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1830 case nir_op_fmin3
: {
1831 if (dst
.regClass() == v2b
) {
1832 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1833 } else if (dst
.regClass() == v1
) {
1834 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1836 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1837 nir_print_instr(&instr
->instr
, stderr
);
1838 fprintf(stderr
, "\n");
1842 case nir_op_fmed3
: {
1843 if (dst
.regClass() == v2b
) {
1844 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1845 } else if (dst
.regClass() == v1
) {
1846 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1848 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1849 nir_print_instr(&instr
->instr
, stderr
);
1850 fprintf(stderr
, "\n");
1854 case nir_op_umax3
: {
1855 if (dst
.size() == 1) {
1856 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1858 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1859 nir_print_instr(&instr
->instr
, stderr
);
1860 fprintf(stderr
, "\n");
1864 case nir_op_umin3
: {
1865 if (dst
.size() == 1) {
1866 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1868 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1869 nir_print_instr(&instr
->instr
, stderr
);
1870 fprintf(stderr
, "\n");
1874 case nir_op_umed3
: {
1875 if (dst
.size() == 1) {
1876 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1878 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1879 nir_print_instr(&instr
->instr
, stderr
);
1880 fprintf(stderr
, "\n");
1884 case nir_op_imax3
: {
1885 if (dst
.size() == 1) {
1886 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1894 case nir_op_imin3
: {
1895 if (dst
.size() == 1) {
1896 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1898 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1899 nir_print_instr(&instr
->instr
, stderr
);
1900 fprintf(stderr
, "\n");
1904 case nir_op_imed3
: {
1905 if (dst
.size() == 1) {
1906 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_cube_face_coord
: {
1915 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1916 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1917 emit_extract_vector(ctx
, in
, 1, v1
),
1918 emit_extract_vector(ctx
, in
, 2, v1
) };
1919 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1920 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1921 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1922 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1923 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1924 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1925 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1928 case nir_op_cube_face_index
: {
1929 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1930 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1931 emit_extract_vector(ctx
, in
, 1, v1
),
1932 emit_extract_vector(ctx
, in
, 2, v1
) };
1933 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1936 case nir_op_bcsel
: {
1937 emit_bcsel(ctx
, instr
, dst
);
1941 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1942 if (dst
.regClass() == v2b
) {
1943 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1944 } else if (dst
.regClass() == v1
) {
1945 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1946 } else if (dst
.regClass() == v2
) {
1947 /* Lowered at NIR level for precision reasons. */
1948 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1950 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1951 nir_print_instr(&instr
->instr
, stderr
);
1952 fprintf(stderr
, "\n");
1957 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1958 if (dst
.regClass() == v2b
) {
1959 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1960 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1961 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1962 } else if (dst
.regClass() == v1
) {
1963 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1964 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1965 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1966 } else if (dst
.regClass() == v2
) {
1967 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1968 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1969 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1970 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1971 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1972 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1974 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1975 nir_print_instr(&instr
->instr
, stderr
);
1976 fprintf(stderr
, "\n");
1981 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1982 if (dst
.regClass() == v2b
) {
1983 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1984 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1985 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1986 } else if (dst
.regClass() == v1
) {
1987 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1988 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1989 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1990 } else if (dst
.regClass() == v2
) {
1991 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1992 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1993 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1995 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1996 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1998 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1999 nir_print_instr(&instr
->instr
, stderr
);
2000 fprintf(stderr
, "\n");
2005 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2006 if (dst
.regClass() == v2b
) {
2007 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
2008 } else if (dst
.regClass() == v1
) {
2009 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2010 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
2011 // TODO: confirm that this holds under any circumstances
2012 } else if (dst
.regClass() == v2
) {
2013 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
2014 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
2017 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2018 nir_print_instr(&instr
->instr
, stderr
);
2019 fprintf(stderr
, "\n");
2023 case nir_op_flog2
: {
2024 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2025 if (dst
.regClass() == v2b
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
2027 } else if (dst
.regClass() == v1
) {
2028 emit_log2(ctx
, bld
, Definition(dst
), src
);
2030 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2031 nir_print_instr(&instr
->instr
, stderr
);
2032 fprintf(stderr
, "\n");
2037 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2038 if (dst
.regClass() == v2b
) {
2039 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2040 } else if (dst
.regClass() == v1
) {
2041 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2042 } else if (dst
.regClass() == v2
) {
2043 /* Lowered at NIR level for precision reasons. */
2044 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2046 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2047 nir_print_instr(&instr
->instr
, stderr
);
2048 fprintf(stderr
, "\n");
2052 case nir_op_fexp2
: {
2053 if (dst
.regClass() == v2b
) {
2054 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2055 } else if (dst
.regClass() == v1
) {
2056 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2058 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2059 nir_print_instr(&instr
->instr
, stderr
);
2060 fprintf(stderr
, "\n");
2064 case nir_op_fsqrt
: {
2065 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2066 if (dst
.regClass() == v2b
) {
2067 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2068 } else if (dst
.regClass() == v1
) {
2069 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2070 } else if (dst
.regClass() == v2
) {
2071 /* Lowered at NIR level for precision reasons. */
2072 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2074 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2075 nir_print_instr(&instr
->instr
, stderr
);
2076 fprintf(stderr
, "\n");
2080 case nir_op_ffract
: {
2081 if (dst
.regClass() == v2b
) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2083 } else if (dst
.regClass() == v1
) {
2084 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2085 } else if (dst
.regClass() == v2
) {
2086 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2088 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2089 nir_print_instr(&instr
->instr
, stderr
);
2090 fprintf(stderr
, "\n");
2094 case nir_op_ffloor
: {
2095 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2096 if (dst
.regClass() == v2b
) {
2097 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2098 } else if (dst
.regClass() == v1
) {
2099 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2100 } else if (dst
.regClass() == v2
) {
2101 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2103 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2104 nir_print_instr(&instr
->instr
, stderr
);
2105 fprintf(stderr
, "\n");
2109 case nir_op_fceil
: {
2110 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2111 if (dst
.regClass() == v2b
) {
2112 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2113 } else if (dst
.regClass() == v1
) {
2114 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2115 } else if (dst
.regClass() == v2
) {
2116 if (ctx
->options
->chip_class
>= GFX7
) {
2117 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2119 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2120 /* trunc = trunc(src0)
2121 * if (src0 > 0.0 && src0 != trunc)
2124 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2125 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2126 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2127 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2128 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2129 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2130 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2133 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2134 nir_print_instr(&instr
->instr
, stderr
);
2135 fprintf(stderr
, "\n");
2139 case nir_op_ftrunc
: {
2140 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2141 if (dst
.regClass() == v2b
) {
2142 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2143 } else if (dst
.regClass() == v1
) {
2144 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2145 } else if (dst
.regClass() == v2
) {
2146 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_fround_even
: {
2155 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (dst
.regClass() == v2b
) {
2157 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2158 } else if (dst
.regClass() == v1
) {
2159 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2160 } else if (dst
.regClass() == v2
) {
2161 if (ctx
->options
->chip_class
>= GFX7
) {
2162 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2164 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2165 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2166 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2168 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2169 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2170 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2171 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2172 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2173 tmp
= sub
->definitions
[0].getTemp();
2175 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2176 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2177 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2178 Temp cond
= vop3
->definitions
[0].getTemp();
2180 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2181 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2182 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2183 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2185 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2188 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2189 nir_print_instr(&instr
->instr
, stderr
);
2190 fprintf(stderr
, "\n");
2196 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2197 aco_ptr
<Instruction
> norm
;
2198 if (dst
.regClass() == v2b
) {
2199 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2200 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2201 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2202 bld
.vop1(opcode
, Definition(dst
), tmp
);
2203 } else if (dst
.regClass() == v1
) {
2204 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2205 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2207 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2208 if (ctx
->options
->chip_class
< GFX9
)
2209 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2211 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2212 bld
.vop1(opcode
, Definition(dst
), tmp
);
2214 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2215 nir_print_instr(&instr
->instr
, stderr
);
2216 fprintf(stderr
, "\n");
2220 case nir_op_ldexp
: {
2221 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2222 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2223 if (dst
.regClass() == v2b
) {
2224 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2225 } else if (dst
.regClass() == v1
) {
2226 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2227 } else if (dst
.regClass() == v2
) {
2228 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2230 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2231 nir_print_instr(&instr
->instr
, stderr
);
2232 fprintf(stderr
, "\n");
2236 case nir_op_frexp_sig
: {
2237 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2238 if (dst
.regClass() == v2b
) {
2239 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2240 } else if (dst
.regClass() == v1
) {
2241 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2242 } else if (dst
.regClass() == v2
) {
2243 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2246 nir_print_instr(&instr
->instr
, stderr
);
2247 fprintf(stderr
, "\n");
2251 case nir_op_frexp_exp
: {
2252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2253 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2254 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2255 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2256 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2257 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2258 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2259 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2260 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2262 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2263 nir_print_instr(&instr
->instr
, stderr
);
2264 fprintf(stderr
, "\n");
2268 case nir_op_fsign
: {
2269 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2270 if (dst
.regClass() == v2b
) {
2271 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2272 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2273 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2274 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2275 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2276 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2277 } else if (dst
.regClass() == v1
) {
2278 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2279 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2280 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2281 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2282 } else if (dst
.regClass() == v2
) {
2283 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2284 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2285 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2287 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2288 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2289 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2291 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2293 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2294 nir_print_instr(&instr
->instr
, stderr
);
2295 fprintf(stderr
, "\n");
2300 case nir_op_f2f16_rtne
: {
2301 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2302 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2303 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2304 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2305 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2306 * keep value numbering and the scheduler simpler.
2308 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2310 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2313 case nir_op_f2f16_rtz
: {
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2316 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2317 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2320 case nir_op_f2f32
: {
2321 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2322 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2323 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2324 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2326 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2327 nir_print_instr(&instr
->instr
, stderr
);
2328 fprintf(stderr
, "\n");
2332 case nir_op_f2f64
: {
2333 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2334 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2335 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2336 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2339 case nir_op_i2f16
: {
2340 assert(dst
.regClass() == v2b
);
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2343 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2344 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2345 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2346 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2349 case nir_op_i2f32
: {
2350 assert(dst
.size() == 1);
2351 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2352 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2353 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2354 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2357 case nir_op_i2f64
: {
2358 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2359 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2360 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2361 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2362 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2363 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2364 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2365 RegClass rc
= RegClass(src
.type(), 1);
2366 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2367 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2368 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2369 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2370 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2371 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2374 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2375 nir_print_instr(&instr
->instr
, stderr
);
2376 fprintf(stderr
, "\n");
2380 case nir_op_u2f16
: {
2381 assert(dst
.regClass() == v2b
);
2382 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2383 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2384 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2385 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2386 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2387 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2390 case nir_op_u2f32
: {
2391 assert(dst
.size() == 1);
2392 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2393 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2394 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2396 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2397 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2398 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2402 case nir_op_u2f64
: {
2403 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2404 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2405 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2406 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2407 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2408 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2409 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2410 RegClass rc
= RegClass(src
.type(), 1);
2411 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2412 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2413 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2414 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2415 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2416 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2418 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2419 nir_print_instr(&instr
->instr
, stderr
);
2420 fprintf(stderr
, "\n");
2425 case nir_op_f2i16
: {
2426 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2427 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2428 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2429 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2431 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2435 case nir_op_f2u16
: {
2436 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2437 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2438 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2439 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2441 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2444 case nir_op_f2i32
: {
2445 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2446 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2447 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2448 if (dst
.type() == RegType::vgpr
) {
2449 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2451 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2452 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2454 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2456 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2457 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2459 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2460 nir_print_instr(&instr
->instr
, stderr
);
2461 fprintf(stderr
, "\n");
2465 case nir_op_f2u32
: {
2466 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2467 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2468 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2469 if (dst
.type() == RegType::vgpr
) {
2470 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2472 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2473 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2475 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2476 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2477 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2478 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2480 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2481 nir_print_instr(&instr
->instr
, stderr
);
2482 fprintf(stderr
, "\n");
2486 case nir_op_f2i64
: {
2487 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2488 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2489 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2491 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2492 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2493 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2494 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2495 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2496 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2497 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2498 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2499 Temp new_exponent
= bld
.tmp(v1
);
2500 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2501 if (ctx
->program
->chip_class
>= GFX8
)
2502 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2504 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2505 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2506 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2507 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2508 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2509 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2510 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2511 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2512 Temp new_lower
= bld
.tmp(v1
);
2513 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2514 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2515 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2517 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2518 if (src
.type() == RegType::vgpr
)
2519 src
= bld
.as_uniform(src
);
2520 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2521 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2522 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2523 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2524 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2525 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2526 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2527 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2528 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2529 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2530 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2531 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2532 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2533 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2534 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2535 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2536 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2537 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2538 Temp borrow
= bld
.tmp(s1
);
2539 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2540 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2543 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2544 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2545 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2546 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2547 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2548 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2549 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2550 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2551 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2552 if (dst
.type() == RegType::sgpr
) {
2553 lower
= bld
.as_uniform(lower
);
2554 upper
= bld
.as_uniform(upper
);
2556 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2560 nir_print_instr(&instr
->instr
, stderr
);
2561 fprintf(stderr
, "\n");
2565 case nir_op_f2u64
: {
2566 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2567 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2568 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2570 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2571 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2572 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2573 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2574 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2575 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2576 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2577 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2578 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2579 Temp new_exponent
= bld
.tmp(v1
);
2580 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2581 if (ctx
->program
->chip_class
>= GFX8
)
2582 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2584 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2585 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2586 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2587 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2588 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2589 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2590 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2591 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2593 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2594 if (src
.type() == RegType::vgpr
)
2595 src
= bld
.as_uniform(src
);
2596 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2597 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2598 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2599 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2600 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2601 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2602 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2603 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2604 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2605 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2606 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2607 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2608 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2609 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2610 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2611 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2612 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2613 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2615 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2616 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2617 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2618 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2619 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2620 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2621 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2622 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2623 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2624 if (dst
.type() == RegType::sgpr
) {
2625 lower
= bld
.as_uniform(lower
);
2626 upper
= bld
.as_uniform(upper
);
2628 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2632 nir_print_instr(&instr
->instr
, stderr
);
2633 fprintf(stderr
, "\n");
2637 case nir_op_b2f16
: {
2638 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2639 assert(src
.regClass() == bld
.lm
);
2641 if (dst
.regClass() == s1
) {
2642 src
= bool_to_scalar_condition(ctx
, src
);
2643 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2644 } else if (dst
.regClass() == v2b
) {
2645 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2646 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2648 unreachable("Wrong destination register class for nir_op_b2f16.");
2652 case nir_op_b2f32
: {
2653 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2654 assert(src
.regClass() == bld
.lm
);
2656 if (dst
.regClass() == s1
) {
2657 src
= bool_to_scalar_condition(ctx
, src
);
2658 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2659 } else if (dst
.regClass() == v1
) {
2660 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2662 unreachable("Wrong destination register class for nir_op_b2f32.");
2666 case nir_op_b2f64
: {
2667 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2668 assert(src
.regClass() == bld
.lm
);
2670 if (dst
.regClass() == s2
) {
2671 src
= bool_to_scalar_condition(ctx
, src
);
2672 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2673 } else if (dst
.regClass() == v2
) {
2674 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2675 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2676 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2678 unreachable("Wrong destination register class for nir_op_b2f64.");
2685 case nir_op_i2i64
: {
2686 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2687 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2693 case nir_op_u2u64
: {
2694 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2695 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2702 case nir_op_b2i64
: {
2703 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2704 assert(src
.regClass() == bld
.lm
);
2706 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2707 if (tmp
.regClass() == s1
) {
2708 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2709 bool_to_scalar_condition(ctx
, src
, tmp
);
2710 } else if (tmp
.type() == RegType::vgpr
) {
2711 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2713 unreachable("Invalid register class for b2i32");
2717 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2722 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2723 assert(dst
.regClass() == bld
.lm
);
2725 if (src
.type() == RegType::vgpr
) {
2726 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2727 assert(dst
.regClass() == bld
.lm
);
2728 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2729 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2731 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2733 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2734 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2736 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2737 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2739 bool_to_vector_condition(ctx
, tmp
, dst
);
2743 case nir_op_pack_64_2x32_split
: {
2744 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2745 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2747 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2750 case nir_op_unpack_64_2x32_split_x
:
2751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2753 case nir_op_unpack_64_2x32_split_y
:
2754 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2756 case nir_op_unpack_32_2x16_split_x
:
2757 if (dst
.type() == RegType::vgpr
) {
2758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2760 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2763 case nir_op_unpack_32_2x16_split_y
:
2764 if (dst
.type() == RegType::vgpr
) {
2765 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2767 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2770 case nir_op_pack_32_2x16_split
: {
2771 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2772 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2773 if (dst
.regClass() == v1
) {
2774 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2775 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2778 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2779 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2780 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2784 case nir_op_pack_half_2x16
: {
2785 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2787 if (dst
.regClass() == v1
) {
2788 Temp src0
= bld
.tmp(v1
);
2789 Temp src1
= bld
.tmp(v1
);
2790 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2791 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2792 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2794 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2795 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2796 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2798 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2799 nir_print_instr(&instr
->instr
, stderr
);
2800 fprintf(stderr
, "\n");
2804 case nir_op_unpack_half_2x16_split_x
: {
2805 if (dst
.regClass() == v1
) {
2806 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2808 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2809 nir_print_instr(&instr
->instr
, stderr
);
2810 fprintf(stderr
, "\n");
2814 case nir_op_unpack_half_2x16_split_y
: {
2815 if (dst
.regClass() == v1
) {
2816 /* TODO: use SDWA here */
2817 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2818 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2820 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2821 nir_print_instr(&instr
->instr
, stderr
);
2822 fprintf(stderr
, "\n");
2826 case nir_op_fquantize2f16
: {
2827 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2828 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2831 if (ctx
->program
->chip_class
>= GFX8
) {
2832 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2833 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2834 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2836 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2837 * so compare the result and flush to 0 if it's smaller.
2839 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2840 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2841 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2842 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2843 cmp_res
= vop3
->definitions
[0].getTemp();
2846 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2847 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2848 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2850 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2855 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2856 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2858 if (dst
.regClass() == s1
) {
2859 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2860 } else if (dst
.regClass() == v1
) {
2861 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2863 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2864 nir_print_instr(&instr
->instr
, stderr
);
2865 fprintf(stderr
, "\n");
2869 case nir_op_bitfield_select
: {
2870 /* (mask & insert) | (~mask & base) */
2871 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2872 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2873 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2875 /* dst = (insert & bitmask) | (base & ~bitmask) */
2876 if (dst
.regClass() == s1
) {
2877 aco_ptr
<Instruction
> sop2
;
2878 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2879 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2881 if (const_insert
&& const_bitmask
) {
2882 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2884 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2885 lhs
= Operand(insert
);
2889 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2890 if (const_base
&& const_bitmask
) {
2891 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2893 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2894 rhs
= Operand(base
);
2897 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2899 } else if (dst
.regClass() == v1
) {
2900 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2901 base
= as_vgpr(ctx
, base
);
2902 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2903 insert
= as_vgpr(ctx
, insert
);
2905 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2909 nir_print_instr(&instr
->instr
, stderr
);
2910 fprintf(stderr
, "\n");
2916 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2917 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2918 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2920 if (dst
.type() == RegType::sgpr
) {
2922 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2923 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2924 if (const_offset
&& const_bits
) {
2925 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2926 extract
= Operand(const_extract
);
2930 width
= Operand(const_bits
->u32
<< 16);
2932 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2934 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2938 if (dst
.regClass() == s1
) {
2939 if (instr
->op
== nir_op_ubfe
)
2940 opcode
= aco_opcode::s_bfe_u32
;
2942 opcode
= aco_opcode::s_bfe_i32
;
2943 } else if (dst
.regClass() == s2
) {
2944 if (instr
->op
== nir_op_ubfe
)
2945 opcode
= aco_opcode::s_bfe_u64
;
2947 opcode
= aco_opcode::s_bfe_i64
;
2949 unreachable("Unsupported BFE bit size");
2952 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2956 if (dst
.regClass() == v1
) {
2957 if (instr
->op
== nir_op_ubfe
)
2958 opcode
= aco_opcode::v_bfe_u32
;
2960 opcode
= aco_opcode::v_bfe_i32
;
2962 unreachable("Unsupported BFE bit size");
2965 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2969 case nir_op_bit_count
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 if (src
.regClass() == s1
) {
2972 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2973 } else if (src
.regClass() == v1
) {
2974 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2975 } else if (src
.regClass() == v2
) {
2976 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2977 emit_extract_vector(ctx
, src
, 1, v1
),
2978 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2979 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2980 } else if (src
.regClass() == s2
) {
2981 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2983 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2984 nir_print_instr(&instr
->instr
, stderr
);
2985 fprintf(stderr
, "\n");
2990 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2994 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2998 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
3002 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3006 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3010 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3014 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3015 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3017 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3018 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3022 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3023 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3025 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3026 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3030 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3034 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3039 case nir_op_fddx_fine
:
3040 case nir_op_fddy_fine
:
3041 case nir_op_fddx_coarse
:
3042 case nir_op_fddy_coarse
: {
3043 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3044 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3045 if (instr
->op
== nir_op_fddx_fine
) {
3046 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3047 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3048 } else if (instr
->op
== nir_op_fddy_fine
) {
3049 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3050 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3052 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3053 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3054 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3056 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3060 if (ctx
->program
->chip_class
>= GFX8
) {
3061 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3062 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3064 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3065 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3066 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3068 emit_wqm(ctx
, tmp
, dst
, true);
3072 fprintf(stderr
, "Unknown NIR ALU instr: ");
3073 nir_print_instr(&instr
->instr
, stderr
);
3074 fprintf(stderr
, "\n");
3078 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3080 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3082 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3083 // which get truncated the lsb if double and msb if int
3084 // for now, we only use s_mov_b64 with 64bit inline constants
3085 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3086 assert(dst
.type() == RegType::sgpr
);
3088 Builder
bld(ctx
->program
, ctx
->block
);
3090 if (instr
->def
.bit_size
== 1) {
3091 assert(dst
.regClass() == bld
.lm
);
3092 int val
= instr
->value
[0].b
? -1 : 0;
3093 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3094 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3095 } else if (instr
->def
.bit_size
== 8) {
3096 /* ensure that the value is correctly represented in the low byte of the register */
3097 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3098 } else if (instr
->def
.bit_size
== 16) {
3099 /* ensure that the value is correctly represented in the low half of the register */
3100 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3101 } else if (dst
.size() == 1) {
3102 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3104 assert(dst
.size() != 1);
3105 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3106 if (instr
->def
.bit_size
== 64)
3107 for (unsigned i
= 0; i
< dst
.size(); i
++)
3108 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3110 for (unsigned i
= 0; i
< dst
.size(); i
++)
3111 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3113 vec
->definitions
[0] = Definition(dst
);
3114 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3118 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3120 uint32_t new_mask
= 0;
3121 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3122 if (mask
& (1u << i
))
3123 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3127 struct LoadEmitInfo
{
3130 unsigned num_components
;
3131 unsigned component_size
;
3132 Temp resource
= Temp(0, s1
);
3133 unsigned component_stride
= 0;
3134 unsigned const_offset
= 0;
3135 unsigned align_mul
= 0;
3136 unsigned align_offset
= 0;
3139 unsigned swizzle_component_size
= 0;
3140 memory_sync_info sync
;
3141 Temp soffset
= Temp(0, s1
);
3144 using LoadCallback
= Temp(*)(
3145 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3146 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3148 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3149 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3151 unsigned load_size
= info
->num_components
* info
->component_size
;
3152 unsigned component_size
= info
->component_size
;
3154 unsigned num_vals
= 0;
3155 Temp vals
[info
->dst
.bytes()];
3157 unsigned const_offset
= info
->const_offset
;
3159 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3160 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3162 unsigned bytes_read
= 0;
3163 while (bytes_read
< load_size
) {
3164 unsigned bytes_needed
= load_size
- bytes_read
;
3166 /* add buffer for unaligned loads */
3167 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3170 if ((bytes_needed
> 2 ||
3171 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3172 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3173 if (info
->component_stride
) {
3174 assert(supports_8bit_16bit_loads
&& "unimplemented");
3178 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3179 bytes_needed
= align(bytes_needed
, 4);
3186 if (info
->swizzle_component_size
)
3187 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3188 if (info
->component_stride
)
3189 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3191 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3193 /* reduce constant offset */
3194 Operand offset
= info
->offset
;
3195 unsigned reduced_const_offset
= const_offset
;
3196 bool remove_const_offset_completely
= need_to_align_offset
;
3197 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3198 unsigned to_add
= const_offset
;
3199 if (remove_const_offset_completely
) {
3200 reduced_const_offset
= 0;
3202 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3203 reduced_const_offset
%= max_const_offset_plus_one
;
3205 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3206 if (offset
.isConstant()) {
3207 offset
= Operand(offset
.constantValue() + to_add
);
3208 } else if (offset_tmp
.regClass() == s1
) {
3209 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3210 offset_tmp
, Operand(to_add
));
3211 } else if (offset_tmp
.regClass() == v1
) {
3212 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3214 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3215 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3218 if (offset_tmp
.regClass() == s2
) {
3219 Temp carry
= bld
.tmp(s1
);
3220 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3221 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3222 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3224 Temp new_lo
= bld
.tmp(v1
);
3225 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3226 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3227 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3232 /* align offset down if needed */
3233 Operand aligned_offset
= offset
;
3234 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3235 if (need_to_align_offset
) {
3237 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3238 if (offset
.isConstant()) {
3239 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3240 } else if (offset_tmp
.regClass() == s1
) {
3241 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3242 } else if (offset_tmp
.regClass() == s2
) {
3243 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3244 } else if (offset_tmp
.regClass() == v1
) {
3245 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3246 } else if (offset_tmp
.regClass() == v2
) {
3247 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3248 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3249 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3250 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3253 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3254 bld
.copy(bld
.def(s1
), aligned_offset
);
3256 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3257 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3259 /* the callback wrote directly to dst */
3260 if (val
== info
->dst
) {
3261 assert(num_vals
== 0);
3262 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3266 /* shift result right if needed */
3267 if (info
->component_size
< 4 && byte_align_loads
) {
3268 Operand
align((uint32_t)byte_align
);
3269 if (byte_align
== -1) {
3270 if (offset
.isConstant())
3271 align
= Operand(offset
.constantValue() % 4u);
3272 else if (offset
.size() == 2)
3273 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3278 assert(val
.bytes() >= load_size
&& "unimplemented");
3279 if (val
.type() == RegType::sgpr
)
3280 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3282 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3286 /* add result to list and advance */
3287 if (info
->component_stride
) {
3288 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3289 const_offset
+= info
->component_stride
;
3290 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3292 const_offset
+= val
.bytes();
3293 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3295 bytes_read
+= val
.bytes();
3296 vals
[num_vals
++] = val
;
3299 /* create array of components */
3300 unsigned components_split
= 0;
3301 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3302 bool has_vgprs
= false;
3303 for (unsigned i
= 0; i
< num_vals
;) {
3305 unsigned num_tmps
= 0;
3306 unsigned tmp_size
= 0;
3307 RegType reg_type
= RegType::sgpr
;
3308 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3309 if (vals
[i
].type() == RegType::vgpr
)
3310 reg_type
= RegType::vgpr
;
3311 tmp_size
+= vals
[i
].bytes();
3312 tmp
[num_tmps
++] = vals
[i
++];
3315 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3316 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3317 for (unsigned i
= 0; i
< num_tmps
; i
++)
3318 vec
->operands
[i
] = Operand(tmp
[i
]);
3319 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3320 vec
->definitions
[0] = Definition(tmp
[0]);
3321 bld
.insert(std::move(vec
));
3324 if (tmp
[0].bytes() % component_size
) {
3326 assert(i
== num_vals
);
3327 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3328 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3331 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3333 unsigned start
= components_split
;
3335 if (tmp_size
== elem_rc
.bytes()) {
3336 allocated_vec
[components_split
++] = tmp
[0];
3338 assert(tmp_size
% elem_rc
.bytes() == 0);
3339 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3340 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3341 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3342 Temp component
= bld
.tmp(elem_rc
);
3343 allocated_vec
[components_split
++] = component
;
3344 split
->definitions
[i
] = Definition(component
);
3346 split
->operands
[0] = Operand(tmp
[0]);
3347 bld
.insert(std::move(split
));
3350 /* try to p_as_uniform early so we can create more optimizable code and
3351 * also update allocated_vec */
3352 for (unsigned j
= start
; j
< components_split
; j
++) {
3353 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3354 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3355 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3359 /* concatenate components and p_as_uniform() result if needed */
3360 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3361 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3363 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3365 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3366 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3367 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3368 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3370 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3371 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3372 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3373 vec
->definitions
[0] = Definition(tmp
);
3374 bld
.insert(std::move(vec
));
3375 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3377 vec
->definitions
[0] = Definition(info
->dst
);
3378 bld
.insert(std::move(vec
));
3382 Operand
load_lds_size_m0(Builder
& bld
)
3384 /* TODO: m0 does not need to be initialized on GFX9+ */
3385 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3388 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3389 Temp offset
, unsigned bytes_needed
,
3390 unsigned align
, unsigned const_offset
,
3393 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3395 Operand m
= load_lds_size_m0(bld
);
3397 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3398 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3403 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3404 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3406 op
= aco_opcode::ds_read_b128
;
3407 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3410 op
= aco_opcode::ds_read2_b64
;
3411 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3413 op
= aco_opcode::ds_read_b96
;
3414 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3416 op
= aco_opcode::ds_read_b64
;
3417 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3420 op
= aco_opcode::ds_read2_b32
;
3421 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3423 op
= aco_opcode::ds_read_b32
;
3424 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3426 op
= aco_opcode::ds_read_u16
;
3429 op
= aco_opcode::ds_read_u8
;
3432 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3433 if (const_offset
>= max_offset_plus_one
) {
3434 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3435 const_offset
%= max_offset_plus_one
;
3439 const_offset
/= (size
/ 2u);
3441 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3442 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3445 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3447 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3448 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3451 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3456 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3458 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3459 Temp offset
, unsigned bytes_needed
,
3460 unsigned align
, unsigned const_offset
,
3465 if (bytes_needed
<= 4) {
3467 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3468 } else if (bytes_needed
<= 8) {
3470 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3471 } else if (bytes_needed
<= 16) {
3473 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3474 } else if (bytes_needed
<= 32) {
3476 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3479 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3481 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3482 if (info
->resource
.id()) {
3483 load
->operands
[0] = Operand(info
->resource
);
3484 load
->operands
[1] = Operand(offset
);
3486 load
->operands
[0] = Operand(offset
);
3487 load
->operands
[1] = Operand(0u);
3489 RegClass
rc(RegType::sgpr
, size
);
3490 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3491 load
->definitions
[0] = Definition(val
);
3492 load
->glc
= info
->glc
;
3493 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3494 load
->sync
= info
->sync
;
3495 bld
.insert(std::move(load
));
3499 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3501 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3502 Temp offset
, unsigned bytes_needed
,
3503 unsigned align_
, unsigned const_offset
,
3506 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3507 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3509 if (info
->soffset
.id()) {
3510 if (soffset
.isTemp())
3511 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3512 soffset
= Operand(info
->soffset
);
3515 unsigned bytes_size
= 0;
3517 if (bytes_needed
== 1 || align_
% 2) {
3519 op
= aco_opcode::buffer_load_ubyte
;
3520 } else if (bytes_needed
== 2 || align_
% 4) {
3522 op
= aco_opcode::buffer_load_ushort
;
3523 } else if (bytes_needed
<= 4) {
3525 op
= aco_opcode::buffer_load_dword
;
3526 } else if (bytes_needed
<= 8) {
3528 op
= aco_opcode::buffer_load_dwordx2
;
3529 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3531 op
= aco_opcode::buffer_load_dwordx3
;
3534 op
= aco_opcode::buffer_load_dwordx4
;
3536 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3537 mubuf
->operands
[0] = Operand(info
->resource
);
3538 mubuf
->operands
[1] = vaddr
;
3539 mubuf
->operands
[2] = soffset
;
3540 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3541 mubuf
->glc
= info
->glc
;
3542 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3543 mubuf
->sync
= info
->sync
;
3544 mubuf
->offset
= const_offset
;
3545 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3546 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3547 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3548 mubuf
->definitions
[0] = Definition(val
);
3549 bld
.insert(std::move(mubuf
));
3554 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3555 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3557 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3559 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3560 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3562 if (addr
.type() == RegType::vgpr
)
3563 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3564 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3567 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3568 Temp offset
, unsigned bytes_needed
,
3569 unsigned align_
, unsigned const_offset
,
3572 unsigned bytes_size
= 0;
3573 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3574 bool global
= bld
.program
->chip_class
>= GFX9
;
3576 if (bytes_needed
== 1) {
3578 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3579 } else if (bytes_needed
== 2) {
3581 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3582 } else if (bytes_needed
<= 4) {
3584 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3585 } else if (bytes_needed
<= 8) {
3587 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3588 } else if (bytes_needed
<= 12 && !mubuf
) {
3590 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3593 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3595 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3596 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3598 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3599 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3600 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3601 mubuf
->operands
[2] = Operand(0u);
3602 mubuf
->glc
= info
->glc
;
3605 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3606 mubuf
->disable_wqm
= false;
3607 mubuf
->sync
= info
->sync
;
3608 mubuf
->definitions
[0] = Definition(val
);
3609 bld
.insert(std::move(mubuf
));
3611 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3613 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3614 flat
->operands
[0] = Operand(offset
);
3615 flat
->operands
[1] = Operand(s1
);
3616 flat
->glc
= info
->glc
;
3617 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3618 flat
->sync
= info
->sync
;
3620 flat
->definitions
[0] = Definition(val
);
3621 bld
.insert(std::move(flat
));
3627 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3629 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3630 Temp address
, unsigned base_offset
, unsigned align
)
3632 assert(util_is_power_of_two_nonzero(align
));
3634 Builder
bld(ctx
->program
, ctx
->block
);
3636 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3637 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3638 info
.align_mul
= align
;
3639 info
.align_offset
= 0;
3640 info
.sync
= memory_sync_info(storage_shared
);
3641 info
.const_offset
= base_offset
;
3642 emit_lds_load(ctx
, bld
, &info
);
3647 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3652 Builder
bld(ctx
->program
, ctx
->block
);
3654 ASSERTED
bool is_subdword
= false;
3655 for (unsigned i
= 0; i
< count
; i
++)
3656 is_subdword
|= offsets
[i
] % 4;
3657 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3658 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3660 /* count == 1 fast path */
3662 if (dst_type
== RegType::sgpr
)
3663 dst
[0] = bld
.as_uniform(src
);
3665 dst
[0] = as_vgpr(ctx
, src
);
3669 for (unsigned i
= 0; i
< count
- 1; i
++)
3670 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3671 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3673 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3674 src
= as_vgpr(ctx
, src
);
3676 /* use allocated_vec if possible */
3677 auto it
= ctx
->allocated_vec
.find(src
.id());
3678 if (it
!= ctx
->allocated_vec
.end()) {
3679 if (!it
->second
[0].id())
3681 unsigned elem_size
= it
->second
[0].bytes();
3682 assert(src
.bytes() % elem_size
== 0);
3684 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3685 if (!it
->second
[i
].id())
3689 for (unsigned i
= 0; i
< count
; i
++) {
3690 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3694 for (unsigned i
= 0; i
< count
; i
++) {
3695 unsigned start_idx
= offsets
[i
] / elem_size
;
3696 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3697 if (op_count
== 1) {
3698 if (dst_type
== RegType::sgpr
)
3699 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3701 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3705 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3706 for (unsigned j
= 0; j
< op_count
; j
++) {
3707 Temp tmp
= it
->second
[start_idx
+ j
];
3708 if (dst_type
== RegType::sgpr
)
3709 tmp
= bld
.as_uniform(tmp
);
3710 vec
->operands
[j
] = Operand(tmp
);
3712 vec
->definitions
[0] = Definition(dst
[i
]);
3713 bld
.insert(std::move(vec
));
3721 if (dst_type
== RegType::sgpr
)
3722 src
= bld
.as_uniform(src
);
3725 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3726 split
->operands
[0] = Operand(src
);
3727 for (unsigned i
= 0; i
< count
; i
++)
3728 split
->definitions
[i
] = Definition(dst
[i
]);
3729 bld
.insert(std::move(split
));
3732 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3733 int *start
, int *count
)
3735 unsigned start_elem
= ffs(todo_mask
) - 1;
3736 bool skip
= !(mask
& (1 << start_elem
));
3738 mask
= ~mask
& todo_mask
;
3742 u_bit_scan_consecutive_range(&mask
, start
, count
);
3747 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3749 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3752 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3753 Temp address
, unsigned base_offset
, unsigned align
)
3755 assert(util_is_power_of_two_nonzero(align
));
3756 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3758 Builder
bld(ctx
->program
, ctx
->block
);
3759 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3760 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3762 unsigned write_count
= 0;
3763 Temp write_datas
[32];
3764 unsigned offsets
[32];
3765 aco_opcode opcodes
[32];
3767 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3769 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3772 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3773 offsets
[write_count
] = offset
;
3774 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3776 advance_write_mask(&todo
, offset
, bytes
);
3780 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3781 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3782 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3783 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3785 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3786 aco_opcode op
= aco_opcode::num_opcodes
;
3787 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3788 op
= aco_opcode::ds_write_b128
;
3790 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3791 op
= aco_opcode::ds_write_b96
;
3793 } else if (bytes
>= 8 && aligned8
) {
3794 op
= aco_opcode::ds_write_b64
;
3796 } else if (bytes
>= 4 && aligned4
) {
3797 op
= aco_opcode::ds_write_b32
;
3799 } else if (bytes
>= 2 && aligned2
) {
3800 op
= aco_opcode::ds_write_b16
;
3802 } else if (bytes
>= 1) {
3803 op
= aco_opcode::ds_write_b8
;
3809 offsets
[write_count
] = offset
;
3810 opcodes
[write_count
] = op
;
3812 advance_write_mask(&todo
, offset
, bytes
);
3815 Operand m
= load_lds_size_m0(bld
);
3817 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3819 for (unsigned i
= 0; i
< write_count
; i
++) {
3820 aco_opcode op
= opcodes
[i
];
3821 if (op
== aco_opcode::num_opcodes
)
3824 Temp data
= write_datas
[i
];
3826 unsigned second
= write_count
;
3827 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3828 for (second
= i
+ 1; second
< write_count
; second
++) {
3829 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3830 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3831 opcodes
[second
] = aco_opcode::num_opcodes
;
3837 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3838 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3840 unsigned inline_offset
= base_offset
+ offsets
[i
];
3841 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3842 Temp address_offset
= address
;
3843 if (inline_offset
> max_offset
) {
3844 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3845 inline_offset
= offsets
[i
];
3847 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3851 Temp second_data
= write_datas
[second
];
3852 inline_offset
/= data
.bytes();
3853 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3855 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3857 static_cast<DS_instruction
*>(instr
)->sync
=
3858 memory_sync_info(storage_shared
);
3862 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3864 unsigned align
= 16;
3866 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3872 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3877 return aco_opcode::buffer_store_byte
;
3880 return aco_opcode::buffer_store_short
;
3882 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3884 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3887 return aco_opcode::buffer_store_dwordx3
;
3889 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3891 unreachable("Unexpected store size");
3892 return aco_opcode::num_opcodes
;
3895 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3896 Temp data
, unsigned writemask
, int swizzle_element_size
,
3897 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3899 unsigned write_count_with_skips
= 0;
3902 /* determine how to split the data */
3903 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3906 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3907 offsets
[write_count_with_skips
] = offset
;
3908 if (skips
[write_count_with_skips
]) {
3909 advance_write_mask(&todo
, offset
, bytes
);
3910 write_count_with_skips
++;
3914 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3915 * larger than swizzle_element_size */
3916 bytes
= MIN2(bytes
, swizzle_element_size
);
3918 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3920 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3921 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3924 /* dword or larger stores have to be dword-aligned */
3925 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3926 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3927 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3929 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3931 advance_write_mask(&todo
, offset
, bytes
);
3932 write_count_with_skips
++;
3935 /* actually split data */
3936 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3939 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3942 write_datas
[*write_count
] = write_datas
[i
];
3943 offsets
[*write_count
] = offsets
[i
];
3948 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3949 unsigned split_cnt
= 0u, Temp dst
= Temp())
3951 Builder
bld(ctx
->program
, ctx
->block
);
3952 unsigned dword_size
= elem_size_bytes
/ 4;
3955 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3957 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3958 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3959 instr
->definitions
[0] = Definition(dst
);
3961 for (unsigned i
= 0; i
< cnt
; ++i
) {
3963 assert(arr
[i
].size() == dword_size
);
3964 allocated_vec
[i
] = arr
[i
];
3965 instr
->operands
[i
] = Operand(arr
[i
]);
3967 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3968 allocated_vec
[i
] = zero
;
3969 instr
->operands
[i
] = Operand(zero
);
3973 bld
.insert(std::move(instr
));
3976 emit_split_vector(ctx
, dst
, split_cnt
);
3978 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3983 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3985 if (const_offset
>= 4096) {
3986 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3987 const_offset
%= 4096u;
3990 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3991 else if (unlikely(voffset
.regClass() == s1
))
3992 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3993 else if (likely(voffset
.regClass() == v1
))
3994 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3996 unreachable("Unsupported register class of voffset");
3999 return const_offset
;
4002 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
4003 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false,
4004 bool swizzled
= false)
4007 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
4008 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
4010 Builder
bld(ctx
->program
, ctx
->block
);
4011 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
4012 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
4014 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
4015 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
4016 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
4017 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
4018 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
4019 /* dlc*/ false, /* slc */ slc
);
4022 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= memory_sync_info(storage_buffer
, semantic_private
);
4025 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
4026 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
4027 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
4029 Builder
bld(ctx
->program
, ctx
->block
);
4030 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4032 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
4034 unsigned write_count
= 0;
4035 Temp write_datas
[32];
4036 unsigned offsets
[32];
4037 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
4038 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4040 for (unsigned i
= 0; i
< write_count
; i
++) {
4041 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4042 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
, !allow_combining
);
4046 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4047 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4048 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4050 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4051 assert((num_components
* elem_size_bytes
) == dst
.bytes());
4052 assert(!!stride
!= allow_combining
);
4054 Builder
bld(ctx
->program
, ctx
->block
);
4056 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4057 info
.component_stride
= allow_combining
? 0 : stride
;
4059 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4060 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4061 info
.align_offset
= 0;
4062 info
.soffset
= soffset
;
4063 info
.const_offset
= base_const_offset
;
4064 emit_mubuf_load(ctx
, bld
, &info
);
4067 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4069 Builder
bld(ctx
->program
, ctx
->block
);
4070 Temp offset
= base_offset
.first
;
4071 unsigned const_offset
= base_offset
.second
;
4073 if (!nir_src_is_const(*off_src
)) {
4074 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4077 /* Calculate indirect offset with stride */
4078 if (likely(indirect_offset_arg
.regClass() == v1
))
4079 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4080 else if (indirect_offset_arg
.regClass() == s1
)
4081 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4083 unreachable("Unsupported register class of indirect offset");
4085 /* Add to the supplied base offset */
4086 if (offset
.id() == 0)
4087 offset
= with_stride
;
4088 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4089 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4090 else if (offset
.size() == 1 && with_stride
.size() == 1)
4091 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4093 unreachable("Unsupported register class of indirect offset");
4095 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4096 const_offset
+= const_offset_arg
* stride
;
4099 return std::make_pair(offset
, const_offset
);
4102 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4104 Builder
bld(ctx
->program
, ctx
->block
);
4107 if (off1
.first
.id() && off2
.first
.id()) {
4108 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4109 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4110 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4111 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4113 unreachable("Unsupported register class of indirect offset");
4115 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4118 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4121 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4123 Builder
bld(ctx
->program
, ctx
->block
);
4124 unsigned const_offset
= offs
.second
* multiplier
;
4126 if (!offs
.first
.id())
4127 return std::make_pair(offs
.first
, const_offset
);
4129 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4130 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4131 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4133 return std::make_pair(offset
, const_offset
);
4136 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4138 Builder
bld(ctx
->program
, ctx
->block
);
4140 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4141 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4142 /* component is in bytes */
4143 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4145 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4146 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4147 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4150 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4152 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4155 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4157 Builder
bld(ctx
->program
, ctx
->block
);
4159 switch (ctx
->shader
->info
.stage
) {
4160 case MESA_SHADER_TESS_CTRL
:
4161 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4162 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4163 case MESA_SHADER_TESS_EVAL
:
4164 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4166 unreachable("Unsupported stage in get_tess_rel_patch_id");
4170 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4172 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4173 Builder
bld(ctx
->program
, ctx
->block
);
4175 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4176 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4178 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4180 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4181 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4183 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4184 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4185 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4187 return offset_mul(ctx
, offs
, 4u);
4190 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4192 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4193 Builder
bld(ctx
->program
, ctx
->block
);
4195 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4196 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4197 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4198 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4200 std::pair
<Temp
, unsigned> offs
= instr
4201 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4202 : std::make_pair(Temp(), 0u);
4204 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4205 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4210 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4211 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4213 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4214 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4216 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4217 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4223 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4225 Builder
bld(ctx
->program
, ctx
->block
);
4227 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4228 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4230 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4232 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4233 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4234 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4236 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4237 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4242 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4244 Builder
bld(ctx
->program
, ctx
->block
);
4246 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4247 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4248 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4249 unsigned attr_stride
= ctx
->tcs_num_patches
;
4251 std::pair
<Temp
, unsigned> offs
= instr
4252 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4253 : std::make_pair(Temp(), 0u);
4255 if (const_base_offset
)
4256 offs
.second
+= const_base_offset
* attr_stride
;
4258 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4259 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4260 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4265 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4267 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4272 unsigned drv_loc
= nir_intrinsic_base(instr
);
4273 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4275 if (!nir_src_is_const(*off_src
)) {
4281 uint64_t slot
= per_vertex
4282 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4283 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4284 return (((uint64_t) 1) << slot
) & mask
;
4287 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4289 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4290 unsigned component
= nir_intrinsic_component(instr
);
4291 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4293 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4294 if (off_instr
->type
!= nir_instr_type_load_const
)
4297 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4298 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4300 if (instr
->src
[0].ssa
->bit_size
== 64)
4301 write_mask
= widen_mask(write_mask
, 2);
4303 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4305 for (unsigned i
= 0; i
< 8; ++i
) {
4306 if (write_mask
& (1 << i
)) {
4307 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4308 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4316 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4318 /* Only TCS per-vertex inputs are supported by this function.
4319 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4321 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4324 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4325 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4326 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4327 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4328 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4329 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4334 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4335 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4336 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4341 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4343 Builder
bld(ctx
->program
, ctx
->block
);
4345 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4346 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4347 bool indirect_write
;
4348 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4349 if (temp_only_input
&& !indirect_write
)
4353 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4354 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4355 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4356 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4358 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4359 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4360 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4361 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4362 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4366 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4367 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4368 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4369 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4370 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4371 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4372 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4373 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4374 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4375 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4376 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4377 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4378 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4380 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4381 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4383 unreachable("Invalid LS or ES stage");
4386 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4387 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4388 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4392 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4397 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4398 return off
== ctx
->tcs_tess_lvl_out_loc
||
4399 off
== ctx
->tcs_tess_lvl_in_loc
;
4403 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4405 uint64_t mask
= per_vertex
4406 ? ctx
->program
->info
->tcs
.tes_inputs_read
4407 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4409 bool indirect_write
= false;
4410 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4411 return indirect_write
|| output_read_by_tes
;
4414 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4416 uint64_t mask
= per_vertex
4417 ? ctx
->shader
->info
.outputs_read
4418 : ctx
->shader
->info
.patch_outputs_read
;
4420 bool indirect_write
= false;
4421 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4422 return indirect_write
|| output_read
;
4425 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4427 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4428 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4430 Builder
bld(ctx
->program
, ctx
->block
);
4432 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4433 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4434 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4436 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4437 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4438 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4440 if (write_to_vmem
) {
4441 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4442 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4443 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4445 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4446 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4447 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4451 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4452 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4453 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4457 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4459 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4460 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4462 Builder
bld(ctx
->program
, ctx
->block
);
4464 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4465 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4466 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4467 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4469 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4472 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4474 if (ctx
->stage
== vertex_vs
||
4475 ctx
->stage
== tess_eval_vs
||
4476 ctx
->stage
== fragment_fs
||
4477 ctx
->stage
== ngg_vertex_gs
||
4478 ctx
->stage
== ngg_tess_eval_gs
||
4479 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4480 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4481 if (!stored_to_temps
) {
4482 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4483 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4484 fprintf(stderr
, "\n");
4487 } else if (ctx
->stage
== vertex_es
||
4488 ctx
->stage
== vertex_ls
||
4489 ctx
->stage
== tess_eval_es
||
4490 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4491 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4492 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4493 visit_store_ls_or_es_output(ctx
, instr
);
4494 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4495 visit_store_tcs_output(ctx
, instr
, false);
4497 unreachable("Shader stage not implemented");
4501 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4503 visit_load_tcs_output(ctx
, instr
, false);
4506 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4508 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4509 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4511 Builder
bld(ctx
->program
, ctx
->block
);
4513 if (dst
.regClass() == v2b
) {
4514 if (ctx
->program
->has_16bank_lds
) {
4515 assert(ctx
->options
->chip_class
<= GFX8
);
4516 Builder::Result interp_p1
=
4517 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4518 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4519 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4520 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4521 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4522 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4524 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4526 if (ctx
->options
->chip_class
== GFX8
)
4527 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4529 Builder::Result interp_p1
=
4530 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4531 coord1
, bld
.m0(prim_mask
), idx
, component
);
4532 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4533 interp_p1
, idx
, component
);
4536 Builder::Result interp_p1
=
4537 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4538 bld
.m0(prim_mask
), idx
, component
);
4540 if (ctx
->program
->has_16bank_lds
)
4541 interp_p1
.instr
->operands
[0].setLateKill(true);
4543 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4544 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4548 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4550 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4551 for (unsigned i
= 0; i
< num_components
; i
++)
4552 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4553 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4554 assert(num_components
== 4);
4555 Builder
bld(ctx
->program
, ctx
->block
);
4556 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4559 for (Operand
& op
: vec
->operands
)
4560 op
= op
.isUndefined() ? Operand(0u) : op
;
4562 vec
->definitions
[0] = Definition(dst
);
4563 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4564 emit_split_vector(ctx
, dst
, num_components
);
4568 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4570 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4571 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4572 unsigned idx
= nir_intrinsic_base(instr
);
4573 unsigned component
= nir_intrinsic_component(instr
);
4574 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4576 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4578 assert(offset
->u32
== 0);
4580 /* the lower 15bit of the prim_mask contain the offset into LDS
4581 * while the upper bits contain the number of prims */
4582 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4583 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4584 Builder
bld(ctx
->program
, ctx
->block
);
4585 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4586 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4587 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4588 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4589 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4592 if (instr
->dest
.ssa
.num_components
== 1) {
4593 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4595 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4596 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4598 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4599 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4600 vec
->operands
[i
] = Operand(tmp
);
4602 vec
->definitions
[0] = Definition(dst
);
4603 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4607 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4608 unsigned offset
, unsigned stride
, unsigned channels
)
4610 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4611 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4613 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4614 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4617 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4618 unsigned offset
, unsigned stride
, unsigned *channels
)
4620 if (!vtx_info
->chan_byte_size
) {
4621 *channels
= vtx_info
->num_channels
;
4622 return vtx_info
->chan_format
;
4625 unsigned num_channels
= *channels
;
4626 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4627 unsigned new_channels
= num_channels
+ 1;
4628 /* first, assume more loads is worse and try using a larger data format */
4629 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4631 /* don't make the attribute potentially out-of-bounds */
4632 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4636 if (new_channels
== 5) {
4637 /* then try decreasing load size (at the cost of more loads) */
4638 new_channels
= *channels
;
4639 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4643 if (new_channels
< *channels
)
4644 *channels
= new_channels
;
4645 num_channels
= new_channels
;
4648 switch (vtx_info
->chan_format
) {
4649 case V_008F0C_BUF_DATA_FORMAT_8
:
4650 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4651 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4652 case V_008F0C_BUF_DATA_FORMAT_16
:
4653 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4654 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4655 case V_008F0C_BUF_DATA_FORMAT_32
:
4656 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4657 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4659 unreachable("shouldn't reach here");
4660 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4663 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4664 * so we may need to fix it up. */
4665 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4667 Builder
bld(ctx
->program
, ctx
->block
);
4669 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4670 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4672 /* For the integer-like cases, do a natural sign extension.
4674 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4675 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4678 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4679 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4681 /* Convert back to the right type. */
4682 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4683 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4684 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4685 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4686 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4687 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4693 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4695 Builder
bld(ctx
->program
, ctx
->block
);
4696 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4697 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4699 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4700 if (off_instr
->type
!= nir_instr_type_load_const
) {
4701 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4702 nir_print_instr(off_instr
, stderr
);
4703 fprintf(stderr
, "\n");
4705 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4707 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4709 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4710 unsigned component
= nir_intrinsic_component(instr
);
4711 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4712 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4713 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4714 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4715 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4717 unsigned dfmt
= attrib_format
& 0xf;
4718 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4719 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4721 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4722 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4723 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4724 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4726 num_channels
= MAX2(num_channels
, 3);
4728 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4729 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4732 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4733 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4734 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4736 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4738 Temp divided
= bld
.tmp(v1
);
4739 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4740 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4742 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4745 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4748 index
= bld
.vadd32(bld
.def(v1
),
4749 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4750 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4753 Temp channels
[num_channels
];
4754 unsigned channel_start
= 0;
4755 bool direct_fetch
= false;
4757 /* skip unused channels at the start */
4758 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4759 channel_start
= ffs(mask
) - 1;
4760 for (unsigned i
= 0; i
< channel_start
; i
++)
4761 channels
[i
] = Temp(0, s1
);
4762 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4763 num_channels
= 3 - (ffs(mask
) - 1);
4767 while (channel_start
< num_channels
) {
4768 unsigned fetch_component
= num_channels
- channel_start
;
4769 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4770 bool expanded
= false;
4772 /* use MUBUF when possible to avoid possible alignment issues */
4773 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4774 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4775 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4776 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4777 vtx_info
->chan_byte_size
== 4;
4778 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4780 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4782 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4783 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4784 fetch_component
= 4;
4789 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4791 Temp fetch_index
= index
;
4792 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4793 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4794 fetch_offset
= fetch_offset
% attrib_stride
;
4797 Operand
soffset(0u);
4798 if (fetch_offset
>= 4096) {
4799 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4800 fetch_offset
%= 4096;
4804 switch (fetch_bytes
) {
4806 assert(!use_mubuf
&& bitsize
== 16);
4807 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4810 if (bitsize
== 16) {
4812 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4814 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4818 assert(!use_mubuf
&& bitsize
== 16);
4819 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4822 if (bitsize
== 16) {
4824 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4826 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4830 assert(ctx
->options
->chip_class
>= GFX7
||
4831 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4832 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4835 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4838 unreachable("Unimplemented load_input vector size");
4842 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4843 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4844 num_channels
<= 3)) {
4845 direct_fetch
= true;
4848 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4853 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4854 fetch_offset
, false, false, true).instr
;
4857 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4858 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4861 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4863 if (fetch_component
== 1) {
4864 channels
[channel_start
] = fetch_dst
;
4866 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4867 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4868 bitsize
== 16 ? v2b
: v1
);
4871 channel_start
+= fetch_component
;
4874 if (!direct_fetch
) {
4875 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4876 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4878 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4879 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4880 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4882 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4883 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4884 unsigned num_temp
= 0;
4885 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4886 unsigned idx
= i
+ component
;
4887 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4888 Temp channel
= channels
[swizzle
[idx
]];
4889 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4890 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4891 vec
->operands
[i
] = Operand(channel
);
4895 } else if (is_float
&& idx
== 3) {
4896 vec
->operands
[i
] = Operand(0x3f800000u
);
4897 } else if (!is_float
&& idx
== 3) {
4898 vec
->operands
[i
] = Operand(1u);
4900 vec
->operands
[i
] = Operand(0u);
4903 vec
->definitions
[0] = Definition(dst
);
4904 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4905 emit_split_vector(ctx
, dst
, dst
.size());
4907 if (num_temp
== dst
.size())
4908 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4910 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4911 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4912 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4913 if (off_instr
->type
!= nir_instr_type_load_const
||
4914 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4915 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4916 nir_print_instr(off_instr
, stderr
);
4917 fprintf(stderr
, "\n");
4920 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4921 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4923 assert(offset
->u32
== 0);
4925 /* the lower 15bit of the prim_mask contain the offset into LDS
4926 * while the upper bits contain the number of prims */
4927 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4928 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4929 Builder
bld(ctx
->program
, ctx
->block
);
4930 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4931 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4932 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4933 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4934 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4937 unsigned idx
= nir_intrinsic_base(instr
);
4938 unsigned component
= nir_intrinsic_component(instr
);
4939 unsigned vertex_id
= 2; /* P0 */
4941 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4942 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4943 switch (src0
->u32
) {
4945 vertex_id
= 2; /* P0 */
4948 vertex_id
= 0; /* P10 */
4951 vertex_id
= 1; /* P20 */
4954 unreachable("invalid vertex index");
4958 if (dst
.size() == 1) {
4959 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4961 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4962 for (unsigned i
= 0; i
< dst
.size(); i
++)
4963 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4964 vec
->definitions
[0] = Definition(dst
);
4965 bld
.insert(std::move(vec
));
4968 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4969 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4970 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4971 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4972 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4974 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4976 unreachable("Shader stage not implemented");
4980 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4982 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4984 Builder
bld(ctx
->program
, ctx
->block
);
4985 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4988 if (!nir_src_is_const(*vertex_src
)) {
4989 /* better code could be created, but this case probably doesn't happen
4990 * much in practice */
4991 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4992 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4995 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4996 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4998 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
5000 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
5003 if (vertex_offset
.id()) {
5004 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
5005 Operand(i
), indirect_vertex
);
5006 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
5008 vertex_offset
= elem
;
5012 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5013 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
5015 unsigned vertex
= nir_src_as_uint(*vertex_src
);
5016 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5017 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5018 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
5019 Operand((vertex
% 2u) * 16u), Operand(16u));
5021 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
5024 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
5025 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
5026 return offset_mul(ctx
, offs
, 4u);
5029 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5031 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5033 Builder
bld(ctx
->program
, ctx
->block
);
5034 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5035 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5037 if (ctx
->stage
== geometry_gs
) {
5038 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
5039 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
5040 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
5041 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5042 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
5043 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5044 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5046 unreachable("Unsupported GS stage.");
5050 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5052 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5054 Builder
bld(ctx
->program
, ctx
->block
);
5055 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5057 if (load_input_from_temps(ctx
, instr
, dst
))
5060 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5061 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5062 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5064 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5067 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5069 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5071 Builder
bld(ctx
->program
, ctx
->block
);
5073 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5074 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5075 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5077 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5078 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5080 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5083 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5085 switch (ctx
->shader
->info
.stage
) {
5086 case MESA_SHADER_GEOMETRY
:
5087 visit_load_gs_per_vertex_input(ctx
, instr
);
5089 case MESA_SHADER_TESS_CTRL
:
5090 visit_load_tcs_per_vertex_input(ctx
, instr
);
5092 case MESA_SHADER_TESS_EVAL
:
5093 visit_load_tes_per_vertex_input(ctx
, instr
);
5096 unreachable("Unimplemented shader stage");
5100 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5102 visit_load_tcs_output(ctx
, instr
, true);
5105 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5107 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5108 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5110 visit_store_tcs_output(ctx
, instr
, true);
5113 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5115 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5117 Builder
bld(ctx
->program
, ctx
->block
);
5118 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5120 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5121 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5124 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5125 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5126 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5127 tes_w
= Operand(tmp
);
5130 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5131 emit_split_vector(ctx
, tess_coord
, 3);
5134 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5136 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5137 Builder
bld(ctx
->program
, ctx
->block
);
5138 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5139 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5140 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5143 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5147 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5149 Builder
bld(ctx
->program
, ctx
->block
);
5150 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5151 if (!nir_dest_is_divergent(instr
->dest
))
5152 index
= bld
.as_uniform(index
);
5153 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5154 unsigned binding
= nir_intrinsic_binding(instr
);
5157 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5158 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5159 unsigned offset
= layout
->binding
[binding
].offset
;
5161 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5162 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5163 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5164 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5165 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5168 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5169 stride
= layout
->binding
[binding
].size
;
5172 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5173 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5175 if (nir_const_index
) {
5176 const_index
= const_index
* stride
;
5177 } else if (index
.type() == RegType::vgpr
) {
5178 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5179 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5181 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5185 if (nir_const_index
) {
5186 const_index
= const_index
+ offset
;
5187 } else if (index
.type() == RegType::vgpr
) {
5188 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5190 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5194 if (nir_const_index
&& const_index
== 0) {
5196 } else if (index
.type() == RegType::vgpr
) {
5197 index
= bld
.vadd32(bld
.def(v1
),
5198 nir_const_index
? Operand(const_index
) : Operand(index
),
5201 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5202 nir_const_index
? Operand(const_index
) : Operand(index
),
5206 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5209 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5210 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5211 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5213 Builder
bld(ctx
->program
, ctx
->block
);
5215 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5217 offset
= bld
.as_uniform(offset
);
5219 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5222 info
.align_mul
= align_mul
;
5223 info
.align_offset
= align_offset
;
5225 emit_smem_load(ctx
, bld
, &info
);
5227 emit_mubuf_load(ctx
, bld
, &info
);
5230 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5232 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5233 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5235 Builder
bld(ctx
->program
, ctx
->block
);
5237 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5238 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5239 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5240 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5242 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5243 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5244 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5245 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5246 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5247 if (ctx
->options
->chip_class
>= GFX10
) {
5248 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5249 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5250 S_008F0C_RESOURCE_LEVEL(1);
5252 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5253 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5255 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5256 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5257 Operand(0xFFFFFFFFu
),
5258 Operand(desc_type
));
5259 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5260 rsrc
, upper_dwords
);
5262 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5263 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5265 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5266 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5267 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5270 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5272 Builder
bld(ctx
->program
, ctx
->block
);
5273 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5274 unsigned offset
= nir_intrinsic_base(instr
);
5275 unsigned count
= instr
->dest
.ssa
.num_components
;
5276 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5278 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5279 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5280 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5281 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5282 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5283 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5284 for (unsigned i
= 0; i
< count
; ++i
) {
5285 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5286 vec
->operands
[i
] = Operand
{elems
[i
]};
5288 vec
->definitions
[0] = Definition(dst
);
5289 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5290 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5295 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5296 if (offset
!= 0) // TODO check if index != 0 as well
5297 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5298 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5301 bool aligned
= true;
5303 if (instr
->dest
.ssa
.bit_size
== 8) {
5304 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5305 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5307 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5308 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5309 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5311 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5316 switch (vec
.size()) {
5318 op
= aco_opcode::s_load_dword
;
5321 op
= aco_opcode::s_load_dwordx2
;
5327 op
= aco_opcode::s_load_dwordx4
;
5333 op
= aco_opcode::s_load_dwordx8
;
5336 unreachable("unimplemented or forbidden load_push_constant.");
5339 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5342 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5343 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5348 emit_split_vector(ctx
, vec
, 4);
5349 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5350 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5351 emit_extract_vector(ctx
, vec
, 0, rc
),
5352 emit_extract_vector(ctx
, vec
, 1, rc
),
5353 emit_extract_vector(ctx
, vec
, 2, rc
));
5356 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5359 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5361 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5363 Builder
bld(ctx
->program
, ctx
->block
);
5365 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5366 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5367 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5368 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5369 if (ctx
->options
->chip_class
>= GFX10
) {
5370 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5371 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5372 S_008F0C_RESOURCE_LEVEL(1);
5374 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5375 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5378 unsigned base
= nir_intrinsic_base(instr
);
5379 unsigned range
= nir_intrinsic_range(instr
);
5381 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5382 if (base
&& offset
.type() == RegType::sgpr
)
5383 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5384 else if (base
&& offset
.type() == RegType::vgpr
)
5385 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5387 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5388 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5389 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5390 Operand(desc_type
));
5391 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5392 // TODO: get alignment information for subdword constants
5393 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5396 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5398 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5399 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5401 ctx
->program
->needs_exact
= true;
5403 // TODO: optimize uniform conditions
5404 Builder
bld(ctx
->program
, ctx
->block
);
5405 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5406 assert(src
.regClass() == bld
.lm
);
5407 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5408 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5409 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5413 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5415 Builder
bld(ctx
->program
, ctx
->block
);
5417 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5418 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5420 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5421 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5423 if (ctx
->block
->loop_nest_depth
&&
5424 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5425 /* we handle discards the same way as jump instructions */
5426 append_logical_end(ctx
->block
);
5428 /* in loops, discard behaves like break */
5429 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5430 ctx
->block
->kind
|= block_kind_discard
;
5433 /* uniform discard - loop ends here */
5434 assert(nir_instr_is_last(&instr
->instr
));
5435 ctx
->block
->kind
|= block_kind_uniform
;
5436 ctx
->cf_info
.has_branch
= true;
5437 bld
.branch(aco_opcode::p_branch
);
5438 add_linear_edge(ctx
->block
->index
, linear_target
);
5442 /* we add a break right behind the discard() instructions */
5443 ctx
->block
->kind
|= block_kind_break
;
5444 unsigned idx
= ctx
->block
->index
;
5446 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5447 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5449 /* remove critical edges from linear CFG */
5450 bld
.branch(aco_opcode::p_branch
);
5451 Block
* break_block
= ctx
->program
->create_and_insert_block();
5452 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5453 break_block
->kind
|= block_kind_uniform
;
5454 add_linear_edge(idx
, break_block
);
5455 add_linear_edge(break_block
->index
, linear_target
);
5456 bld
.reset(break_block
);
5457 bld
.branch(aco_opcode::p_branch
);
5459 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5460 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5461 add_linear_edge(idx
, continue_block
);
5462 append_logical_start(continue_block
);
5463 ctx
->block
= continue_block
;
5468 /* it can currently happen that NIR doesn't remove the unreachable code */
5469 if (!nir_instr_is_last(&instr
->instr
)) {
5470 ctx
->program
->needs_exact
= true;
5471 /* save exec somewhere temporarily so that it doesn't get
5472 * overwritten before the discard from outer exec masks */
5473 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5474 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5475 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5479 /* This condition is incorrect for uniformly branched discards in a loop
5480 * predicated by a divergent condition, but the above code catches that case
5481 * and the discard would end up turning into a discard_if.
5491 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5492 /* program just ends here */
5493 ctx
->block
->kind
|= block_kind_uniform
;
5494 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5495 0 /* enabled mask */, 9 /* dest */,
5496 false /* compressed */, true/* done */, true /* valid mask */);
5497 bld
.sopp(aco_opcode::s_endpgm
);
5498 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5500 ctx
->block
->kind
|= block_kind_discard
;
5501 /* branch and linear edge is added by visit_if() */
5505 enum aco_descriptor_type
{
5516 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5517 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5519 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5520 return dim
== ac_image_cube
||
5521 dim
== ac_image_1darray
||
5522 dim
== ac_image_2darray
||
5523 dim
== ac_image_2darraymsaa
;
5526 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5527 enum aco_descriptor_type desc_type
,
5528 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5530 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5531 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5532 if (it != ctx->tex_desc.end())
5535 Temp index
= Temp();
5536 bool index_set
= false;
5537 unsigned constant_index
= 0;
5538 unsigned descriptor_set
;
5539 unsigned base_index
;
5540 Builder
bld(ctx
->program
, ctx
->block
);
5543 assert(tex_instr
&& !image
);
5545 base_index
= tex_instr
->sampler_index
;
5547 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5548 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5552 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5553 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5555 constant_index
+= array_size
* const_value
->u32
;
5557 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5558 if (indirect
.type() == RegType::vgpr
)
5559 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5561 if (array_size
!= 1)
5562 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5568 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5572 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5574 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5575 base_index
= deref_instr
->var
->data
.binding
;
5578 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5579 list
= convert_pointer_to_64_bit(ctx
, list
);
5581 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5582 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5583 unsigned offset
= binding
->offset
;
5584 unsigned stride
= binding
->size
;
5588 assert(base_index
< layout
->binding_count
);
5590 switch (desc_type
) {
5591 case ACO_DESC_IMAGE
:
5593 opcode
= aco_opcode::s_load_dwordx8
;
5595 case ACO_DESC_FMASK
:
5597 opcode
= aco_opcode::s_load_dwordx8
;
5600 case ACO_DESC_SAMPLER
:
5602 opcode
= aco_opcode::s_load_dwordx4
;
5603 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5604 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5606 case ACO_DESC_BUFFER
:
5608 opcode
= aco_opcode::s_load_dwordx4
;
5610 case ACO_DESC_PLANE_0
:
5611 case ACO_DESC_PLANE_1
:
5613 opcode
= aco_opcode::s_load_dwordx8
;
5614 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5616 case ACO_DESC_PLANE_2
:
5618 opcode
= aco_opcode::s_load_dwordx4
;
5622 unreachable("invalid desc_type\n");
5625 offset
+= constant_index
* stride
;
5627 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5628 (!index_set
|| binding
->immutable_samplers_equal
)) {
5629 if (binding
->immutable_samplers_equal
)
5632 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5633 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5634 Operand(samplers
[constant_index
* 4 + 0]),
5635 Operand(samplers
[constant_index
* 4 + 1]),
5636 Operand(samplers
[constant_index
* 4 + 2]),
5637 Operand(samplers
[constant_index
* 4 + 3]));
5642 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5644 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5645 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5648 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5650 if (desc_type
== ACO_DESC_PLANE_2
) {
5652 for (unsigned i
= 0; i
< 8; i
++)
5653 components
[i
] = bld
.tmp(s1
);
5654 bld
.pseudo(aco_opcode::p_split_vector
,
5655 Definition(components
[0]),
5656 Definition(components
[1]),
5657 Definition(components
[2]),
5658 Definition(components
[3]),
5661 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5662 bld
.pseudo(aco_opcode::p_split_vector
,
5663 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5664 Definition(components
[4]),
5665 Definition(components
[5]),
5666 Definition(components
[6]),
5667 Definition(components
[7]),
5670 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5671 components
[0], components
[1], components
[2], components
[3],
5672 components
[4], components
[5], components
[6], components
[7]);
5678 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5681 case GLSL_SAMPLER_DIM_BUF
:
5683 case GLSL_SAMPLER_DIM_1D
:
5684 return array
? 2 : 1;
5685 case GLSL_SAMPLER_DIM_2D
:
5686 return array
? 3 : 2;
5687 case GLSL_SAMPLER_DIM_MS
:
5688 return array
? 4 : 3;
5689 case GLSL_SAMPLER_DIM_3D
:
5690 case GLSL_SAMPLER_DIM_CUBE
:
5692 case GLSL_SAMPLER_DIM_RECT
:
5693 case GLSL_SAMPLER_DIM_SUBPASS
:
5695 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5704 /* Adjust the sample index according to FMASK.
5706 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5707 * which is the identity mapping. Each nibble says which physical sample
5708 * should be fetched to get that sample.
5710 * For example, 0x11111100 means there are only 2 samples stored and
5711 * the second sample covers 3/4 of the pixel. When reading samples 0
5712 * and 1, return physical sample 0 (determined by the first two 0s
5713 * in FMASK), otherwise return physical sample 1.
5715 * The sample index should be adjusted as follows:
5716 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5718 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5720 Builder
bld(ctx
->program
, ctx
->block
);
5721 Temp fmask
= bld
.tmp(v1
);
5722 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5723 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5726 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5727 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5728 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5729 load
->operands
[0] = Operand(fmask_desc_ptr
);
5730 load
->operands
[1] = Operand(s4
); /* no sampler */
5731 load
->operands
[2] = Operand(coord
);
5732 load
->definitions
[0] = Definition(fmask
);
5739 ctx
->block
->instructions
.emplace_back(std::move(load
));
5741 Operand sample_index4
;
5742 if (sample_index
.isConstant()) {
5743 if (sample_index
.constantValue() < 16) {
5744 sample_index4
= Operand(sample_index
.constantValue() << 2);
5746 sample_index4
= Operand(0u);
5748 } else if (sample_index
.regClass() == s1
) {
5749 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5751 assert(sample_index
.regClass() == v1
);
5752 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5756 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5757 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5758 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5759 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5761 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5763 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5764 * resource descriptor is 0 (invalid),
5766 Temp compare
= bld
.tmp(bld
.lm
);
5767 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5768 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5770 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5772 /* Replace the MSAA sample index. */
5773 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5776 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5779 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5780 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5781 bool is_array
= glsl_sampler_type_is_array(type
);
5782 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5783 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5784 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5785 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5786 int count
= image_type_to_components_count(dim
, is_array
);
5787 std::vector
<Temp
> coords(count
);
5788 Builder
bld(ctx
->program
, ctx
->block
);
5792 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5793 /* get sample index */
5794 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5795 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5796 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5797 std::vector
<Temp
> fmask_load_address
;
5798 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5799 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5801 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5802 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5804 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5809 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5810 coords
.resize(coords
.size() + 1);
5811 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5813 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5815 for (int i
= 0; i
< count
; i
++)
5816 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5819 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5820 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5821 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5822 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5825 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5828 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5829 for (unsigned i
= 0; i
< coords
.size(); i
++)
5830 vec
->operands
[i
] = Operand(coords
[i
]);
5831 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5832 vec
->definitions
[0] = Definition(res
);
5833 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5838 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5840 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5841 if (semantics
& semantic_atomicrmw
)
5842 return memory_sync_info(storage
, semantics
);
5844 unsigned access
= nir_intrinsic_access(instr
);
5846 if (access
& ACCESS_VOLATILE
)
5847 semantics
|= semantic_volatile
;
5848 if (access
& ACCESS_CAN_REORDER
)
5849 semantics
|= semantic_can_reorder
| semantic_private
;
5851 return memory_sync_info(storage
, semantics
);
5854 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5856 Builder
bld(ctx
->program
, ctx
->block
);
5857 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5858 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5859 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5860 bool is_array
= glsl_sampler_type_is_array(type
);
5861 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5863 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5865 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5866 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5867 unsigned num_channels
= util_last_bit(mask
);
5868 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5869 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5872 switch (num_channels
) {
5874 opcode
= aco_opcode::buffer_load_format_x
;
5877 opcode
= aco_opcode::buffer_load_format_xy
;
5880 opcode
= aco_opcode::buffer_load_format_xyz
;
5883 opcode
= aco_opcode::buffer_load_format_xyzw
;
5886 unreachable(">4 channel buffer image load");
5888 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5889 load
->operands
[0] = Operand(rsrc
);
5890 load
->operands
[1] = Operand(vindex
);
5891 load
->operands
[2] = Operand((uint32_t) 0);
5893 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5896 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5897 load
->definitions
[0] = Definition(tmp
);
5899 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5900 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5902 ctx
->block
->instructions
.emplace_back(std::move(load
));
5904 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5908 Temp coords
= get_image_coords(ctx
, instr
, type
);
5909 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5911 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5912 unsigned num_components
= util_bitcount(dmask
);
5914 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5917 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5919 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5920 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5922 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5923 load
->operands
[0] = Operand(resource
);
5924 load
->operands
[1] = Operand(s4
); /* no sampler */
5925 load
->operands
[2] = Operand(coords
);
5926 load
->definitions
[0] = Definition(tmp
);
5927 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5928 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5929 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5930 load
->dmask
= dmask
;
5932 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5934 ctx
->block
->instructions
.emplace_back(std::move(load
));
5936 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5940 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5942 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5943 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5944 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5945 bool is_array
= glsl_sampler_type_is_array(type
);
5946 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5948 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5949 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5951 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5952 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5953 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5955 switch (data
.size()) {
5957 opcode
= aco_opcode::buffer_store_format_x
;
5960 opcode
= aco_opcode::buffer_store_format_xy
;
5963 opcode
= aco_opcode::buffer_store_format_xyz
;
5966 opcode
= aco_opcode::buffer_store_format_xyzw
;
5969 unreachable(">4 channel buffer image store");
5971 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5972 store
->operands
[0] = Operand(rsrc
);
5973 store
->operands
[1] = Operand(vindex
);
5974 store
->operands
[2] = Operand((uint32_t) 0);
5975 store
->operands
[3] = Operand(data
);
5976 store
->idxen
= true;
5979 store
->disable_wqm
= true;
5981 ctx
->program
->needs_exact
= true;
5982 ctx
->block
->instructions
.emplace_back(std::move(store
));
5986 assert(data
.type() == RegType::vgpr
);
5987 Temp coords
= get_image_coords(ctx
, instr
, type
);
5988 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5990 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5991 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5993 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5994 store
->operands
[0] = Operand(resource
);
5995 store
->operands
[1] = Operand(data
);
5996 store
->operands
[2] = Operand(coords
);
5999 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6000 store
->dmask
= (1 << data
.size()) - 1;
6002 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6003 store
->disable_wqm
= true;
6005 ctx
->program
->needs_exact
= true;
6006 ctx
->block
->instructions
.emplace_back(std::move(store
));
6010 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6012 /* return the previous value if dest is ever used */
6013 bool return_previous
= false;
6014 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6015 return_previous
= true;
6018 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6019 return_previous
= true;
6023 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6024 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6025 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6026 bool is_array
= glsl_sampler_type_is_array(type
);
6027 Builder
bld(ctx
->program
, ctx
->block
);
6029 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
6030 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
6032 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
6033 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
6035 aco_opcode buf_op
, image_op
;
6036 switch (instr
->intrinsic
) {
6037 case nir_intrinsic_image_deref_atomic_add
:
6038 buf_op
= aco_opcode::buffer_atomic_add
;
6039 image_op
= aco_opcode::image_atomic_add
;
6041 case nir_intrinsic_image_deref_atomic_umin
:
6042 buf_op
= aco_opcode::buffer_atomic_umin
;
6043 image_op
= aco_opcode::image_atomic_umin
;
6045 case nir_intrinsic_image_deref_atomic_imin
:
6046 buf_op
= aco_opcode::buffer_atomic_smin
;
6047 image_op
= aco_opcode::image_atomic_smin
;
6049 case nir_intrinsic_image_deref_atomic_umax
:
6050 buf_op
= aco_opcode::buffer_atomic_umax
;
6051 image_op
= aco_opcode::image_atomic_umax
;
6053 case nir_intrinsic_image_deref_atomic_imax
:
6054 buf_op
= aco_opcode::buffer_atomic_smax
;
6055 image_op
= aco_opcode::image_atomic_smax
;
6057 case nir_intrinsic_image_deref_atomic_and
:
6058 buf_op
= aco_opcode::buffer_atomic_and
;
6059 image_op
= aco_opcode::image_atomic_and
;
6061 case nir_intrinsic_image_deref_atomic_or
:
6062 buf_op
= aco_opcode::buffer_atomic_or
;
6063 image_op
= aco_opcode::image_atomic_or
;
6065 case nir_intrinsic_image_deref_atomic_xor
:
6066 buf_op
= aco_opcode::buffer_atomic_xor
;
6067 image_op
= aco_opcode::image_atomic_xor
;
6069 case nir_intrinsic_image_deref_atomic_exchange
:
6070 buf_op
= aco_opcode::buffer_atomic_swap
;
6071 image_op
= aco_opcode::image_atomic_swap
;
6073 case nir_intrinsic_image_deref_atomic_comp_swap
:
6074 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
6075 image_op
= aco_opcode::image_atomic_cmpswap
;
6078 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6081 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6082 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
6084 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6085 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6086 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6087 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6088 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6089 mubuf
->operands
[0] = Operand(resource
);
6090 mubuf
->operands
[1] = Operand(vindex
);
6091 mubuf
->operands
[2] = Operand((uint32_t)0);
6092 mubuf
->operands
[3] = Operand(data
);
6093 if (return_previous
)
6094 mubuf
->definitions
[0] = Definition(dst
);
6096 mubuf
->idxen
= true;
6097 mubuf
->glc
= return_previous
;
6098 mubuf
->dlc
= false; /* Not needed for atomics */
6099 mubuf
->disable_wqm
= true;
6101 ctx
->program
->needs_exact
= true;
6102 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6106 Temp coords
= get_image_coords(ctx
, instr
, type
);
6107 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6108 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6109 mimg
->operands
[0] = Operand(resource
);
6110 mimg
->operands
[1] = Operand(data
);
6111 mimg
->operands
[2] = Operand(coords
);
6112 if (return_previous
)
6113 mimg
->definitions
[0] = Definition(dst
);
6114 mimg
->glc
= return_previous
;
6115 mimg
->dlc
= false; /* Not needed for atomics */
6116 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6117 mimg
->dmask
= (1 << data
.size()) - 1;
6119 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6120 mimg
->disable_wqm
= true;
6122 ctx
->program
->needs_exact
= true;
6123 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6127 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6129 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6130 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6131 Builder
bld(ctx
->program
, ctx
->block
);
6133 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6135 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6136 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6138 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6139 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6141 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6142 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6144 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6145 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6146 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6147 if (dst
.type() == RegType::vgpr
)
6148 bld
.copy(Definition(dst
), shr_dst
);
6150 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6152 emit_extract_vector(ctx
, desc
, 2, dst
);
6156 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6158 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6159 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6160 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6161 bool is_array
= glsl_sampler_type_is_array(type
);
6162 Builder
bld(ctx
->program
, ctx
->block
);
6164 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6165 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6166 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6170 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6173 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6175 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6177 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6178 mimg
->operands
[0] = Operand(resource
);
6179 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6180 mimg
->operands
[2] = Operand(lod
);
6181 uint8_t& dmask
= mimg
->dmask
;
6182 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6183 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6184 mimg
->da
= glsl_sampler_type_is_array(type
);
6185 Definition
& def
= mimg
->definitions
[0];
6186 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6188 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6189 glsl_sampler_type_is_array(type
)) {
6191 assert(instr
->dest
.ssa
.num_components
== 3);
6192 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6193 def
= Definition(tmp
);
6194 emit_split_vector(ctx
, tmp
, 3);
6196 /* divide 3rd value by 6 by multiplying with magic number */
6197 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6198 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6200 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6201 emit_extract_vector(ctx
, tmp
, 0, v1
),
6202 emit_extract_vector(ctx
, tmp
, 1, v1
),
6205 } else if (ctx
->options
->chip_class
== GFX9
&&
6206 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6207 glsl_sampler_type_is_array(type
)) {
6208 assert(instr
->dest
.ssa
.num_components
== 2);
6209 def
= Definition(dst
);
6212 def
= Definition(dst
);
6215 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6218 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6220 Builder
bld(ctx
->program
, ctx
->block
);
6221 unsigned num_components
= instr
->num_components
;
6223 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6224 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6225 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6227 unsigned access
= nir_intrinsic_access(instr
);
6228 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6229 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6231 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6232 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6233 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6235 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6236 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6238 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6239 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6240 get_memory_sync_info(instr
, storage_buffer
, 0));
6243 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6245 Builder
bld(ctx
->program
, ctx
->block
);
6246 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6247 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6248 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6249 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6251 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6252 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6254 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6255 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6256 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6257 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6258 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6260 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6262 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6263 ctx
->options
->chip_class
>= GFX8
&&
6264 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6267 offset
= bld
.as_uniform(offset
);
6268 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6270 unsigned write_count
= 0;
6271 Temp write_datas
[32];
6272 unsigned offsets
[32];
6273 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6274 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6276 for (unsigned i
= 0; i
< write_count
; i
++) {
6277 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6278 if (smem
&& ctx
->stage
== fragment_fs
)
6279 op
= aco_opcode::p_fs_buffer_store_smem
;
6282 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6283 store
->operands
[0] = Operand(rsrc
);
6285 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6286 offset
, Operand(offsets
[i
]));
6287 store
->operands
[1] = Operand(off
);
6289 store
->operands
[1] = Operand(offset
);
6291 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6292 store
->operands
[1].setFixed(m0
);
6293 store
->operands
[2] = Operand(write_datas
[i
]);
6296 store
->disable_wqm
= true;
6298 ctx
->block
->instructions
.emplace_back(std::move(store
));
6299 ctx
->program
->wb_smem_l1_on_end
= true;
6300 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6301 ctx
->block
->kind
|= block_kind_needs_lowering
;
6302 ctx
->program
->needs_exact
= true;
6305 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6306 store
->operands
[0] = Operand(rsrc
);
6307 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6308 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6309 store
->operands
[3] = Operand(write_datas
[i
]);
6310 store
->offset
= offsets
[i
];
6311 store
->offen
= (offset
.type() == RegType::vgpr
);
6314 store
->disable_wqm
= true;
6316 ctx
->program
->needs_exact
= true;
6317 ctx
->block
->instructions
.emplace_back(std::move(store
));
6322 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6324 /* return the previous value if dest is ever used */
6325 bool return_previous
= false;
6326 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6327 return_previous
= true;
6330 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6331 return_previous
= true;
6335 Builder
bld(ctx
->program
, ctx
->block
);
6336 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6338 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6339 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6340 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6342 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6343 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6344 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6346 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6348 aco_opcode op32
, op64
;
6349 switch (instr
->intrinsic
) {
6350 case nir_intrinsic_ssbo_atomic_add
:
6351 op32
= aco_opcode::buffer_atomic_add
;
6352 op64
= aco_opcode::buffer_atomic_add_x2
;
6354 case nir_intrinsic_ssbo_atomic_imin
:
6355 op32
= aco_opcode::buffer_atomic_smin
;
6356 op64
= aco_opcode::buffer_atomic_smin_x2
;
6358 case nir_intrinsic_ssbo_atomic_umin
:
6359 op32
= aco_opcode::buffer_atomic_umin
;
6360 op64
= aco_opcode::buffer_atomic_umin_x2
;
6362 case nir_intrinsic_ssbo_atomic_imax
:
6363 op32
= aco_opcode::buffer_atomic_smax
;
6364 op64
= aco_opcode::buffer_atomic_smax_x2
;
6366 case nir_intrinsic_ssbo_atomic_umax
:
6367 op32
= aco_opcode::buffer_atomic_umax
;
6368 op64
= aco_opcode::buffer_atomic_umax_x2
;
6370 case nir_intrinsic_ssbo_atomic_and
:
6371 op32
= aco_opcode::buffer_atomic_and
;
6372 op64
= aco_opcode::buffer_atomic_and_x2
;
6374 case nir_intrinsic_ssbo_atomic_or
:
6375 op32
= aco_opcode::buffer_atomic_or
;
6376 op64
= aco_opcode::buffer_atomic_or_x2
;
6378 case nir_intrinsic_ssbo_atomic_xor
:
6379 op32
= aco_opcode::buffer_atomic_xor
;
6380 op64
= aco_opcode::buffer_atomic_xor_x2
;
6382 case nir_intrinsic_ssbo_atomic_exchange
:
6383 op32
= aco_opcode::buffer_atomic_swap
;
6384 op64
= aco_opcode::buffer_atomic_swap_x2
;
6386 case nir_intrinsic_ssbo_atomic_comp_swap
:
6387 op32
= aco_opcode::buffer_atomic_cmpswap
;
6388 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6391 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6393 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6394 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6395 mubuf
->operands
[0] = Operand(rsrc
);
6396 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6397 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6398 mubuf
->operands
[3] = Operand(data
);
6399 if (return_previous
)
6400 mubuf
->definitions
[0] = Definition(dst
);
6402 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6403 mubuf
->glc
= return_previous
;
6404 mubuf
->dlc
= false; /* Not needed for atomics */
6405 mubuf
->disable_wqm
= true;
6406 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6407 ctx
->program
->needs_exact
= true;
6408 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6411 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6413 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6414 Builder
bld(ctx
->program
, ctx
->block
);
6415 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6416 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6419 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6421 Builder
bld(ctx
->program
, ctx
->block
);
6422 unsigned num_components
= instr
->num_components
;
6423 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6425 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6426 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6427 num_components
, component_size
};
6428 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6429 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6430 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6431 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6432 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6433 * it's safe to use SMEM */
6434 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6435 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6436 emit_global_load(ctx
, bld
, &info
);
6438 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6439 emit_smem_load(ctx
, bld
, &info
);
6443 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6445 Builder
bld(ctx
->program
, ctx
->block
);
6446 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6447 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6449 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6450 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6451 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6452 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6454 if (ctx
->options
->chip_class
>= GFX7
)
6455 addr
= as_vgpr(ctx
, addr
);
6457 unsigned write_count
= 0;
6458 Temp write_datas
[32];
6459 unsigned offsets
[32];
6460 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6461 16, &write_count
, write_datas
, offsets
);
6463 for (unsigned i
= 0; i
< write_count
; i
++) {
6464 if (ctx
->options
->chip_class
>= GFX7
) {
6465 unsigned offset
= offsets
[i
];
6466 Temp store_addr
= addr
;
6467 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6468 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6469 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6470 Temp carry
= bld
.tmp(bld
.lm
);
6471 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6473 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6474 Operand(offset
), addr0
);
6475 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6477 carry
).def(1).setHint(vcc
);
6479 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6484 bool global
= ctx
->options
->chip_class
>= GFX9
;
6486 switch (write_datas
[i
].bytes()) {
6488 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6491 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6494 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6497 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6500 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6503 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6506 unreachable("store_global not implemented for this size.");
6509 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6510 flat
->operands
[0] = Operand(store_addr
);
6511 flat
->operands
[1] = Operand(s1
);
6512 flat
->operands
[2] = Operand(write_datas
[i
]);
6515 flat
->offset
= offset
;
6516 flat
->disable_wqm
= true;
6518 ctx
->program
->needs_exact
= true;
6519 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6521 assert(ctx
->options
->chip_class
== GFX6
);
6523 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6525 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6527 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6528 mubuf
->operands
[0] = Operand(rsrc
);
6529 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6530 mubuf
->operands
[2] = Operand(0u);
6531 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6534 mubuf
->offset
= offsets
[i
];
6535 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6536 mubuf
->disable_wqm
= true;
6538 ctx
->program
->needs_exact
= true;
6539 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6544 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6546 /* return the previous value if dest is ever used */
6547 bool return_previous
= false;
6548 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6549 return_previous
= true;
6552 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6553 return_previous
= true;
6557 Builder
bld(ctx
->program
, ctx
->block
);
6558 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6559 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6561 if (ctx
->options
->chip_class
>= GFX7
)
6562 addr
= as_vgpr(ctx
, addr
);
6564 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6565 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6566 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6568 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6570 aco_opcode op32
, op64
;
6572 if (ctx
->options
->chip_class
>= GFX7
) {
6573 bool global
= ctx
->options
->chip_class
>= GFX9
;
6574 switch (instr
->intrinsic
) {
6575 case nir_intrinsic_global_atomic_add
:
6576 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6577 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6579 case nir_intrinsic_global_atomic_imin
:
6580 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6581 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6583 case nir_intrinsic_global_atomic_umin
:
6584 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6585 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6587 case nir_intrinsic_global_atomic_imax
:
6588 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6589 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6591 case nir_intrinsic_global_atomic_umax
:
6592 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6593 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6595 case nir_intrinsic_global_atomic_and
:
6596 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6597 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6599 case nir_intrinsic_global_atomic_or
:
6600 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6601 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6603 case nir_intrinsic_global_atomic_xor
:
6604 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6605 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6607 case nir_intrinsic_global_atomic_exchange
:
6608 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6609 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6611 case nir_intrinsic_global_atomic_comp_swap
:
6612 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6613 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6616 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6619 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6620 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6621 flat
->operands
[0] = Operand(addr
);
6622 flat
->operands
[1] = Operand(s1
);
6623 flat
->operands
[2] = Operand(data
);
6624 if (return_previous
)
6625 flat
->definitions
[0] = Definition(dst
);
6626 flat
->glc
= return_previous
;
6627 flat
->dlc
= false; /* Not needed for atomics */
6629 flat
->disable_wqm
= true;
6630 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6631 ctx
->program
->needs_exact
= true;
6632 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6634 assert(ctx
->options
->chip_class
== GFX6
);
6636 switch (instr
->intrinsic
) {
6637 case nir_intrinsic_global_atomic_add
:
6638 op32
= aco_opcode::buffer_atomic_add
;
6639 op64
= aco_opcode::buffer_atomic_add_x2
;
6641 case nir_intrinsic_global_atomic_imin
:
6642 op32
= aco_opcode::buffer_atomic_smin
;
6643 op64
= aco_opcode::buffer_atomic_smin_x2
;
6645 case nir_intrinsic_global_atomic_umin
:
6646 op32
= aco_opcode::buffer_atomic_umin
;
6647 op64
= aco_opcode::buffer_atomic_umin_x2
;
6649 case nir_intrinsic_global_atomic_imax
:
6650 op32
= aco_opcode::buffer_atomic_smax
;
6651 op64
= aco_opcode::buffer_atomic_smax_x2
;
6653 case nir_intrinsic_global_atomic_umax
:
6654 op32
= aco_opcode::buffer_atomic_umax
;
6655 op64
= aco_opcode::buffer_atomic_umax_x2
;
6657 case nir_intrinsic_global_atomic_and
:
6658 op32
= aco_opcode::buffer_atomic_and
;
6659 op64
= aco_opcode::buffer_atomic_and_x2
;
6661 case nir_intrinsic_global_atomic_or
:
6662 op32
= aco_opcode::buffer_atomic_or
;
6663 op64
= aco_opcode::buffer_atomic_or_x2
;
6665 case nir_intrinsic_global_atomic_xor
:
6666 op32
= aco_opcode::buffer_atomic_xor
;
6667 op64
= aco_opcode::buffer_atomic_xor_x2
;
6669 case nir_intrinsic_global_atomic_exchange
:
6670 op32
= aco_opcode::buffer_atomic_swap
;
6671 op64
= aco_opcode::buffer_atomic_swap_x2
;
6673 case nir_intrinsic_global_atomic_comp_swap
:
6674 op32
= aco_opcode::buffer_atomic_cmpswap
;
6675 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6678 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6681 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6683 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6685 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6686 mubuf
->operands
[0] = Operand(rsrc
);
6687 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6688 mubuf
->operands
[2] = Operand(0u);
6689 mubuf
->operands
[3] = Operand(data
);
6690 if (return_previous
)
6691 mubuf
->definitions
[0] = Definition(dst
);
6692 mubuf
->glc
= return_previous
;
6695 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6696 mubuf
->disable_wqm
= true;
6697 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6698 ctx
->program
->needs_exact
= true;
6699 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6703 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6704 Builder
bld(ctx
->program
, ctx
->block
);
6705 storage_class all_mem
= (storage_class
)(storage_buffer
| storage_image
| storage_atomic_counter
| storage_shared
);
6706 switch(instr
->intrinsic
) {
6707 case nir_intrinsic_group_memory_barrier
:
6708 bld
.barrier(aco_opcode::p_barrier
,
6709 memory_sync_info(all_mem
, semantic_acqrel
, scope_workgroup
));
6711 case nir_intrinsic_memory_barrier
:
6712 bld
.barrier(aco_opcode::p_barrier
,
6713 memory_sync_info(all_mem
, semantic_acqrel
, scope_device
));
6715 case nir_intrinsic_memory_barrier_buffer
:
6716 case nir_intrinsic_memory_barrier_image
:
6717 /* since NIR splits barriers, we have to unify buffer and image barriers
6718 * for now so dEQP-VK.memory_model.message_passing.core11.u32.coherent.
6719 * fence_fence.atomicwrite.device.payload_nonlocal.buffer.guard_nonlocal.image.comp
6722 bld
.barrier(aco_opcode::p_barrier
,
6723 memory_sync_info((storage_class
)(storage_buffer
| storage_image
), semantic_acqrel
, scope_device
));
6725 case nir_intrinsic_memory_barrier_tcs_patch
:
6726 case nir_intrinsic_memory_barrier_shared
:
6727 bld
.barrier(aco_opcode::p_barrier
,
6728 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
));
6731 unreachable("Unimplemented memory barrier intrinsic");
6736 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6738 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6739 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6740 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6741 Builder
bld(ctx
->program
, ctx
->block
);
6743 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6744 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6745 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6748 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6750 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6751 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6752 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6753 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6755 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6756 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6759 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6761 unsigned offset
= nir_intrinsic_base(instr
);
6762 Builder
bld(ctx
->program
, ctx
->block
);
6763 Operand m
= load_lds_size_m0(bld
);
6764 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6765 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6767 unsigned num_operands
= 3;
6768 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6769 switch(instr
->intrinsic
) {
6770 case nir_intrinsic_shared_atomic_add
:
6771 op32
= aco_opcode::ds_add_u32
;
6772 op64
= aco_opcode::ds_add_u64
;
6773 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6774 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6776 case nir_intrinsic_shared_atomic_imin
:
6777 op32
= aco_opcode::ds_min_i32
;
6778 op64
= aco_opcode::ds_min_i64
;
6779 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6780 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6782 case nir_intrinsic_shared_atomic_umin
:
6783 op32
= aco_opcode::ds_min_u32
;
6784 op64
= aco_opcode::ds_min_u64
;
6785 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6786 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6788 case nir_intrinsic_shared_atomic_imax
:
6789 op32
= aco_opcode::ds_max_i32
;
6790 op64
= aco_opcode::ds_max_i64
;
6791 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6792 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6794 case nir_intrinsic_shared_atomic_umax
:
6795 op32
= aco_opcode::ds_max_u32
;
6796 op64
= aco_opcode::ds_max_u64
;
6797 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6798 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6800 case nir_intrinsic_shared_atomic_and
:
6801 op32
= aco_opcode::ds_and_b32
;
6802 op64
= aco_opcode::ds_and_b64
;
6803 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6804 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6806 case nir_intrinsic_shared_atomic_or
:
6807 op32
= aco_opcode::ds_or_b32
;
6808 op64
= aco_opcode::ds_or_b64
;
6809 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6810 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6812 case nir_intrinsic_shared_atomic_xor
:
6813 op32
= aco_opcode::ds_xor_b32
;
6814 op64
= aco_opcode::ds_xor_b64
;
6815 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6816 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6818 case nir_intrinsic_shared_atomic_exchange
:
6819 op32
= aco_opcode::ds_write_b32
;
6820 op64
= aco_opcode::ds_write_b64
;
6821 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6822 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6824 case nir_intrinsic_shared_atomic_comp_swap
:
6825 op32
= aco_opcode::ds_cmpst_b32
;
6826 op64
= aco_opcode::ds_cmpst_b64
;
6827 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6828 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6831 case nir_intrinsic_shared_atomic_fadd
:
6832 op32
= aco_opcode::ds_add_f32
;
6833 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6834 op64
= aco_opcode::num_opcodes
;
6835 op64_rtn
= aco_opcode::num_opcodes
;
6838 unreachable("Unhandled shared atomic intrinsic");
6841 /* return the previous value if dest is ever used */
6842 bool return_previous
= false;
6843 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6844 return_previous
= true;
6847 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6848 return_previous
= true;
6853 if (data
.size() == 1) {
6854 assert(instr
->dest
.ssa
.bit_size
== 32);
6855 op
= return_previous
? op32_rtn
: op32
;
6857 assert(instr
->dest
.ssa
.bit_size
== 64);
6858 op
= return_previous
? op64_rtn
: op64
;
6861 if (offset
> 65535) {
6862 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6866 aco_ptr
<DS_instruction
> ds
;
6867 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6868 ds
->operands
[0] = Operand(address
);
6869 ds
->operands
[1] = Operand(data
);
6870 if (num_operands
== 4)
6871 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6872 ds
->operands
[num_operands
- 1] = m
;
6873 ds
->offset0
= offset
;
6874 if (return_previous
)
6875 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6876 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6877 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6880 Temp
get_scratch_resource(isel_context
*ctx
)
6882 Builder
bld(ctx
->program
, ctx
->block
);
6883 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6884 if (ctx
->stage
!= compute_cs
)
6885 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6887 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6888 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6890 if (ctx
->program
->chip_class
>= GFX10
) {
6891 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6892 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6893 S_008F0C_RESOURCE_LEVEL(1);
6894 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6895 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6896 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6899 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6900 if (ctx
->program
->chip_class
<= GFX8
)
6901 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6903 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6906 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6907 Builder
bld(ctx
->program
, ctx
->block
);
6908 Temp rsrc
= get_scratch_resource(ctx
);
6909 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6910 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6912 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6913 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6914 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6915 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6916 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6917 info
.sync
= memory_sync_info(storage_buffer
, semantic_private
);
6918 info
.soffset
= ctx
->program
->scratch_offset
;
6919 emit_scratch_load(ctx
, bld
, &info
);
6922 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6923 Builder
bld(ctx
->program
, ctx
->block
);
6924 Temp rsrc
= get_scratch_resource(ctx
);
6925 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6926 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6928 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6929 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6931 unsigned write_count
= 0;
6932 Temp write_datas
[32];
6933 unsigned offsets
[32];
6934 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6935 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6936 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6938 for (unsigned i
= 0; i
< write_count
; i
++) {
6939 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6940 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6941 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_buffer
, semantic_private
);
6945 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6946 uint8_t log2_ps_iter_samples
;
6947 if (ctx
->program
->info
->ps
.force_persample
) {
6948 log2_ps_iter_samples
=
6949 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6951 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6954 /* The bit pattern matches that used by fixed function fragment
6956 static const unsigned ps_iter_masks
[] = {
6957 0xffff, /* not used */
6963 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6965 Builder
bld(ctx
->program
, ctx
->block
);
6967 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6968 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6969 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6970 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6972 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6975 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6976 Builder
bld(ctx
->program
, ctx
->block
);
6978 unsigned stream
= nir_intrinsic_stream_id(instr
);
6979 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6980 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6981 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6984 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6986 unsigned num_components
=
6987 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6988 assert(num_components
);
6990 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6991 unsigned stream_offset
= 0;
6992 for (unsigned i
= 0; i
< stream
; i
++) {
6993 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6994 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6997 /* Limit on the stride field for <= GFX7. */
6998 assert(stride
< (1 << 14));
7000 Temp gsvs_dwords
[4];
7001 for (unsigned i
= 0; i
< 4; i
++)
7002 gsvs_dwords
[i
] = bld
.tmp(s1
);
7003 bld
.pseudo(aco_opcode::p_split_vector
,
7004 Definition(gsvs_dwords
[0]),
7005 Definition(gsvs_dwords
[1]),
7006 Definition(gsvs_dwords
[2]),
7007 Definition(gsvs_dwords
[3]),
7010 if (stream_offset
) {
7011 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
7013 Temp carry
= bld
.tmp(s1
);
7014 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
7015 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
7018 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
7019 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
7021 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7022 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
7024 unsigned offset
= 0;
7025 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
7026 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
7029 for (unsigned j
= 0; j
< 4; j
++) {
7030 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7033 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7034 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7035 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7036 if (const_offset
>= 4096u) {
7037 if (vaddr_offset
.isUndefined())
7038 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7040 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7041 const_offset
%= 4096u;
7044 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7045 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7046 mtbuf
->operands
[1] = vaddr_offset
;
7047 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7048 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7049 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7050 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7051 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7052 mtbuf
->offset
= const_offset
;
7055 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
7056 bld
.insert(std::move(mtbuf
));
7059 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7062 /* outputs for the next vertex are undefined and keeping them around can
7063 * create invalid IR with control flow */
7064 ctx
->outputs
.mask
[i
] = 0;
7067 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7070 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7072 Builder
bld(ctx
->program
, ctx
->block
);
7074 if (cluster_size
== 1) {
7076 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7077 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7078 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7079 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7080 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7081 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7082 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7083 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7084 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7085 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7086 //subgroupAnd(val) -> (exec & ~val) == 0
7087 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7088 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7089 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7090 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7091 //subgroupOr(val) -> (val & exec) != 0
7092 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7093 return bool_to_vector_condition(ctx
, tmp
);
7094 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7095 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7096 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7097 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7098 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7099 return bool_to_vector_condition(ctx
, tmp
);
7101 //subgroupClustered{And,Or,Xor}(val, n) ->
7102 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7103 //cluster_offset = ~(n - 1) & lane_id
7104 //cluster_mask = ((1 << n) - 1)
7105 //subgroupClusteredAnd():
7106 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7107 //subgroupClusteredOr():
7108 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7109 //subgroupClusteredXor():
7110 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7111 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7112 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7115 if (op
== nir_op_iand
)
7116 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7118 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7120 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7122 if (ctx
->program
->chip_class
<= GFX7
)
7123 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7124 else if (ctx
->program
->wave_size
== 64)
7125 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7127 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7128 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7129 if (cluster_mask
!= 0xffffffff)
7130 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7132 Definition cmp_def
= Definition();
7133 if (op
== nir_op_iand
) {
7134 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7135 } else if (op
== nir_op_ior
) {
7136 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7137 } else if (op
== nir_op_ixor
) {
7138 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7139 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7140 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7142 cmp_def
.setHint(vcc
);
7143 return cmp_def
.getTemp();
7147 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7149 Builder
bld(ctx
->program
, ctx
->block
);
7151 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7152 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7153 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7155 if (op
== nir_op_iand
)
7156 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7158 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7160 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7161 Temp lo
= lohi
.def(0).getTemp();
7162 Temp hi
= lohi
.def(1).getTemp();
7163 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7165 Definition cmp_def
= Definition();
7166 if (op
== nir_op_iand
)
7167 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7168 else if (op
== nir_op_ior
)
7169 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7170 else if (op
== nir_op_ixor
)
7171 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7172 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7173 cmp_def
.setHint(vcc
);
7174 return cmp_def
.getTemp();
7177 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7179 Builder
bld(ctx
->program
, ctx
->block
);
7181 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7182 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7183 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7184 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7185 if (op
== nir_op_iand
)
7186 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7187 else if (op
== nir_op_ior
)
7188 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7189 else if (op
== nir_op_ixor
)
7190 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7196 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7198 Builder
bld(ctx
->program
, ctx
->block
);
7199 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7200 if (src
.regClass().type() == RegType::vgpr
) {
7201 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7202 } else if (src
.regClass() == s1
) {
7203 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7204 } else if (src
.regClass() == s2
) {
7205 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7207 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7208 nir_print_instr(&instr
->instr
, stderr
);
7209 fprintf(stderr
, "\n");
7213 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7215 Builder
bld(ctx
->program
, ctx
->block
);
7216 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7217 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7218 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7220 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7221 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7222 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7223 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7226 if (ctx
->program
->chip_class
>= GFX8
) {
7227 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7228 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7229 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7230 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7231 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7232 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7234 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7235 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7236 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7237 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7238 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7239 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7240 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7241 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7242 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7243 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7246 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7247 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7248 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7249 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7250 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7251 Temp wqm1
= bld
.tmp(v1
);
7252 emit_wqm(ctx
, tmp1
, wqm1
, true);
7253 Temp wqm2
= bld
.tmp(v1
);
7254 emit_wqm(ctx
, tmp2
, wqm2
, true);
7255 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7259 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7261 Builder
bld(ctx
->program
, ctx
->block
);
7262 switch(instr
->intrinsic
) {
7263 case nir_intrinsic_load_barycentric_sample
:
7264 case nir_intrinsic_load_barycentric_pixel
:
7265 case nir_intrinsic_load_barycentric_centroid
: {
7266 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7267 Temp bary
= Temp(0, s2
);
7269 case INTERP_MODE_SMOOTH
:
7270 case INTERP_MODE_NONE
:
7271 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7272 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7273 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7274 bary
= ctx
->persp_centroid
;
7275 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7276 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7278 case INTERP_MODE_NOPERSPECTIVE
:
7279 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7280 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7281 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7282 bary
= ctx
->linear_centroid
;
7283 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7284 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7289 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7290 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7291 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7292 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7293 Operand(p1
), Operand(p2
));
7294 emit_split_vector(ctx
, dst
, 2);
7297 case nir_intrinsic_load_barycentric_model
: {
7298 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7300 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7301 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7302 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7303 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7304 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7305 Operand(p1
), Operand(p2
), Operand(p3
));
7306 emit_split_vector(ctx
, dst
, 3);
7309 case nir_intrinsic_load_barycentric_at_sample
: {
7310 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7311 switch (ctx
->options
->key
.fs
.num_samples
) {
7312 case 2: sample_pos_offset
+= 1 << 3; break;
7313 case 4: sample_pos_offset
+= 3 << 3; break;
7314 case 8: sample_pos_offset
+= 7 << 3; break;
7318 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7319 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7320 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7321 //TODO: bounds checking?
7322 if (addr
.type() == RegType::sgpr
) {
7325 sample_pos_offset
+= const_addr
->u32
<< 3;
7326 offset
= Operand(sample_pos_offset
);
7327 } else if (ctx
->options
->chip_class
>= GFX9
) {
7328 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7330 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7331 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7334 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7335 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7337 } else if (ctx
->options
->chip_class
>= GFX9
) {
7338 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7339 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7340 } else if (ctx
->options
->chip_class
>= GFX7
) {
7341 /* addr += private_segment_buffer + sample_pos_offset */
7342 Temp tmp0
= bld
.tmp(s1
);
7343 Temp tmp1
= bld
.tmp(s1
);
7344 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7345 Definition scc_tmp
= bld
.def(s1
, scc
);
7346 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7347 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7348 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7349 Temp pck0
= bld
.tmp(v1
);
7350 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7351 tmp1
= as_vgpr(ctx
, tmp1
);
7352 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7353 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7355 /* sample_pos = flat_load_dwordx2 addr */
7356 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7358 assert(ctx
->options
->chip_class
== GFX6
);
7360 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7361 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7362 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7364 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7365 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7367 sample_pos
= bld
.tmp(v2
);
7369 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7370 load
->definitions
[0] = Definition(sample_pos
);
7371 load
->operands
[0] = Operand(rsrc
);
7372 load
->operands
[1] = Operand(addr
);
7373 load
->operands
[2] = Operand(0u);
7374 load
->offset
= sample_pos_offset
;
7376 load
->addr64
= true;
7379 load
->disable_wqm
= false;
7380 ctx
->block
->instructions
.emplace_back(std::move(load
));
7383 /* sample_pos -= 0.5 */
7384 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7385 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7386 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7387 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7388 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7390 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7393 case nir_intrinsic_load_barycentric_at_offset
: {
7394 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7395 RegClass rc
= RegClass(offset
.type(), 1);
7396 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7397 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7398 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7401 case nir_intrinsic_load_front_face
: {
7402 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7403 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7406 case nir_intrinsic_load_view_index
: {
7407 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7408 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7409 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7415 case nir_intrinsic_load_layer_id
: {
7416 unsigned idx
= nir_intrinsic_base(instr
);
7417 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7418 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7421 case nir_intrinsic_load_frag_coord
: {
7422 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7425 case nir_intrinsic_load_sample_pos
: {
7426 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7427 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7429 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7430 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7433 case nir_intrinsic_load_tess_coord
:
7434 visit_load_tess_coord(ctx
, instr
);
7436 case nir_intrinsic_load_interpolated_input
:
7437 visit_load_interpolated_input(ctx
, instr
);
7439 case nir_intrinsic_store_output
:
7440 visit_store_output(ctx
, instr
);
7442 case nir_intrinsic_load_input
:
7443 case nir_intrinsic_load_input_vertex
:
7444 visit_load_input(ctx
, instr
);
7446 case nir_intrinsic_load_output
:
7447 visit_load_output(ctx
, instr
);
7449 case nir_intrinsic_load_per_vertex_input
:
7450 visit_load_per_vertex_input(ctx
, instr
);
7452 case nir_intrinsic_load_per_vertex_output
:
7453 visit_load_per_vertex_output(ctx
, instr
);
7455 case nir_intrinsic_store_per_vertex_output
:
7456 visit_store_per_vertex_output(ctx
, instr
);
7458 case nir_intrinsic_load_ubo
:
7459 visit_load_ubo(ctx
, instr
);
7461 case nir_intrinsic_load_push_constant
:
7462 visit_load_push_constant(ctx
, instr
);
7464 case nir_intrinsic_load_constant
:
7465 visit_load_constant(ctx
, instr
);
7467 case nir_intrinsic_vulkan_resource_index
:
7468 visit_load_resource(ctx
, instr
);
7470 case nir_intrinsic_discard
:
7471 visit_discard(ctx
, instr
);
7473 case nir_intrinsic_discard_if
:
7474 visit_discard_if(ctx
, instr
);
7476 case nir_intrinsic_load_shared
:
7477 visit_load_shared(ctx
, instr
);
7479 case nir_intrinsic_store_shared
:
7480 visit_store_shared(ctx
, instr
);
7482 case nir_intrinsic_shared_atomic_add
:
7483 case nir_intrinsic_shared_atomic_imin
:
7484 case nir_intrinsic_shared_atomic_umin
:
7485 case nir_intrinsic_shared_atomic_imax
:
7486 case nir_intrinsic_shared_atomic_umax
:
7487 case nir_intrinsic_shared_atomic_and
:
7488 case nir_intrinsic_shared_atomic_or
:
7489 case nir_intrinsic_shared_atomic_xor
:
7490 case nir_intrinsic_shared_atomic_exchange
:
7491 case nir_intrinsic_shared_atomic_comp_swap
:
7492 case nir_intrinsic_shared_atomic_fadd
:
7493 visit_shared_atomic(ctx
, instr
);
7495 case nir_intrinsic_image_deref_load
:
7496 visit_image_load(ctx
, instr
);
7498 case nir_intrinsic_image_deref_store
:
7499 visit_image_store(ctx
, instr
);
7501 case nir_intrinsic_image_deref_atomic_add
:
7502 case nir_intrinsic_image_deref_atomic_umin
:
7503 case nir_intrinsic_image_deref_atomic_imin
:
7504 case nir_intrinsic_image_deref_atomic_umax
:
7505 case nir_intrinsic_image_deref_atomic_imax
:
7506 case nir_intrinsic_image_deref_atomic_and
:
7507 case nir_intrinsic_image_deref_atomic_or
:
7508 case nir_intrinsic_image_deref_atomic_xor
:
7509 case nir_intrinsic_image_deref_atomic_exchange
:
7510 case nir_intrinsic_image_deref_atomic_comp_swap
:
7511 visit_image_atomic(ctx
, instr
);
7513 case nir_intrinsic_image_deref_size
:
7514 visit_image_size(ctx
, instr
);
7516 case nir_intrinsic_load_ssbo
:
7517 visit_load_ssbo(ctx
, instr
);
7519 case nir_intrinsic_store_ssbo
:
7520 visit_store_ssbo(ctx
, instr
);
7522 case nir_intrinsic_load_global
:
7523 visit_load_global(ctx
, instr
);
7525 case nir_intrinsic_store_global
:
7526 visit_store_global(ctx
, instr
);
7528 case nir_intrinsic_global_atomic_add
:
7529 case nir_intrinsic_global_atomic_imin
:
7530 case nir_intrinsic_global_atomic_umin
:
7531 case nir_intrinsic_global_atomic_imax
:
7532 case nir_intrinsic_global_atomic_umax
:
7533 case nir_intrinsic_global_atomic_and
:
7534 case nir_intrinsic_global_atomic_or
:
7535 case nir_intrinsic_global_atomic_xor
:
7536 case nir_intrinsic_global_atomic_exchange
:
7537 case nir_intrinsic_global_atomic_comp_swap
:
7538 visit_global_atomic(ctx
, instr
);
7540 case nir_intrinsic_ssbo_atomic_add
:
7541 case nir_intrinsic_ssbo_atomic_imin
:
7542 case nir_intrinsic_ssbo_atomic_umin
:
7543 case nir_intrinsic_ssbo_atomic_imax
:
7544 case nir_intrinsic_ssbo_atomic_umax
:
7545 case nir_intrinsic_ssbo_atomic_and
:
7546 case nir_intrinsic_ssbo_atomic_or
:
7547 case nir_intrinsic_ssbo_atomic_xor
:
7548 case nir_intrinsic_ssbo_atomic_exchange
:
7549 case nir_intrinsic_ssbo_atomic_comp_swap
:
7550 visit_atomic_ssbo(ctx
, instr
);
7552 case nir_intrinsic_load_scratch
:
7553 visit_load_scratch(ctx
, instr
);
7555 case nir_intrinsic_store_scratch
:
7556 visit_store_scratch(ctx
, instr
);
7558 case nir_intrinsic_get_buffer_size
:
7559 visit_get_buffer_size(ctx
, instr
);
7561 case nir_intrinsic_control_barrier
: {
7562 bld
.barrier(aco_opcode::p_barrier
, memory_sync_info(0, 0, scope_invocation
), scope_workgroup
);
7565 case nir_intrinsic_memory_barrier_tcs_patch
:
7566 case nir_intrinsic_group_memory_barrier
:
7567 case nir_intrinsic_memory_barrier
:
7568 case nir_intrinsic_memory_barrier_buffer
:
7569 case nir_intrinsic_memory_barrier_image
:
7570 case nir_intrinsic_memory_barrier_shared
:
7571 emit_memory_barrier(ctx
, instr
);
7573 case nir_intrinsic_load_num_work_groups
: {
7574 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7575 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7576 emit_split_vector(ctx
, dst
, 3);
7579 case nir_intrinsic_load_local_invocation_id
: {
7580 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7581 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7582 emit_split_vector(ctx
, dst
, 3);
7585 case nir_intrinsic_load_work_group_id
: {
7586 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7587 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7589 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7590 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7591 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7592 emit_split_vector(ctx
, dst
, 3);
7595 case nir_intrinsic_load_local_invocation_index
: {
7596 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7598 /* The tg_size bits [6:11] contain the subgroup id,
7599 * we need this multiplied by the wave size, and then OR the thread id to it.
7601 if (ctx
->program
->wave_size
== 64) {
7602 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7603 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7604 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7605 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7607 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7608 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7609 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7610 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7614 case nir_intrinsic_load_subgroup_id
: {
7615 if (ctx
->stage
== compute_cs
) {
7616 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7617 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7619 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7623 case nir_intrinsic_load_subgroup_invocation
: {
7624 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7627 case nir_intrinsic_load_num_subgroups
: {
7628 if (ctx
->stage
== compute_cs
)
7629 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7630 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7632 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7635 case nir_intrinsic_ballot
: {
7636 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7637 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7638 Definition tmp
= bld
.def(dst
.regClass());
7639 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7640 if (instr
->src
[0].ssa
->bit_size
== 1) {
7641 assert(src
.regClass() == bld
.lm
);
7642 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7643 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7644 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7645 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7646 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7648 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7649 nir_print_instr(&instr
->instr
, stderr
);
7650 fprintf(stderr
, "\n");
7652 if (dst
.size() != bld
.lm
.size()) {
7653 /* Wave32 with ballot size set to 64 */
7654 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7656 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7659 case nir_intrinsic_shuffle
:
7660 case nir_intrinsic_read_invocation
: {
7661 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7662 if (!nir_src_is_divergent(instr
->src
[0])) {
7663 emit_uniform_subgroup(ctx
, instr
, src
);
7665 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7666 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7667 tid
= bld
.as_uniform(tid
);
7668 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7669 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7670 Temp tmp
= bld
.tmp(v1
);
7671 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7672 if (dst
.type() == RegType::vgpr
)
7673 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7675 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7676 } else if (src
.regClass() == v1
) {
7677 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7678 } else if (src
.regClass() == v2
) {
7679 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7680 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7681 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7682 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7683 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7684 emit_split_vector(ctx
, dst
, 2);
7685 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7686 assert(src
.regClass() == bld
.lm
);
7687 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7688 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7689 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7690 assert(src
.regClass() == bld
.lm
);
7692 if (ctx
->program
->chip_class
<= GFX7
)
7693 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7694 else if (ctx
->program
->wave_size
== 64)
7695 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7697 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7698 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7699 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7700 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7702 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7703 nir_print_instr(&instr
->instr
, stderr
);
7704 fprintf(stderr
, "\n");
7709 case nir_intrinsic_load_sample_id
: {
7710 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7711 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7714 case nir_intrinsic_load_sample_mask_in
: {
7715 visit_load_sample_mask_in(ctx
, instr
);
7718 case nir_intrinsic_read_first_invocation
: {
7719 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7720 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7721 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7723 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7725 } else if (src
.regClass() == v2
) {
7726 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7727 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7728 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7729 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7730 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7731 emit_split_vector(ctx
, dst
, 2);
7732 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7733 assert(src
.regClass() == bld
.lm
);
7734 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7735 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7736 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7737 } else if (src
.regClass() == s1
) {
7738 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7739 } else if (src
.regClass() == s2
) {
7740 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7742 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7743 nir_print_instr(&instr
->instr
, stderr
);
7744 fprintf(stderr
, "\n");
7748 case nir_intrinsic_vote_all
: {
7749 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7750 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7751 assert(src
.regClass() == bld
.lm
);
7752 assert(dst
.regClass() == bld
.lm
);
7754 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7755 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7756 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7759 case nir_intrinsic_vote_any
: {
7760 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7761 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7762 assert(src
.regClass() == bld
.lm
);
7763 assert(dst
.regClass() == bld
.lm
);
7765 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7766 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7769 case nir_intrinsic_reduce
:
7770 case nir_intrinsic_inclusive_scan
:
7771 case nir_intrinsic_exclusive_scan
: {
7772 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7773 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7774 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7775 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7776 nir_intrinsic_cluster_size(instr
) : 0;
7777 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7779 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7780 emit_uniform_subgroup(ctx
, instr
, src
);
7781 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7782 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7784 else if (op
== nir_op_iadd
)
7786 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7788 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7790 switch (instr
->intrinsic
) {
7791 case nir_intrinsic_reduce
:
7792 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7794 case nir_intrinsic_exclusive_scan
:
7795 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7797 case nir_intrinsic_inclusive_scan
:
7798 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7803 } else if (cluster_size
== 1) {
7804 bld
.copy(Definition(dst
), src
);
7806 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7808 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7812 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7813 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7828 unreachable("unknown reduction op");
7834 switch (instr
->intrinsic
) {
7835 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7836 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7837 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7839 unreachable("unknown reduce intrinsic");
7842 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7843 reduce
->operands
[0] = Operand(src
);
7844 // filled in by aco_reduce_assign.cpp, used internally as part of the
7846 assert(dst
.size() == 1 || dst
.size() == 2);
7847 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7848 reduce
->operands
[2] = Operand(v1
.as_linear());
7850 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7851 reduce
->definitions
[0] = Definition(tmp_dst
);
7852 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7853 reduce
->definitions
[2] = Definition();
7854 reduce
->definitions
[3] = Definition(scc
, s1
);
7855 reduce
->definitions
[4] = Definition();
7856 reduce
->reduce_op
= reduce_op
;
7857 reduce
->cluster_size
= cluster_size
;
7858 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7860 emit_wqm(ctx
, tmp_dst
, dst
);
7864 case nir_intrinsic_quad_broadcast
: {
7865 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7866 if (!nir_dest_is_divergent(instr
->dest
)) {
7867 emit_uniform_subgroup(ctx
, instr
, src
);
7869 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7870 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7871 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7873 if (instr
->dest
.ssa
.bit_size
== 1) {
7874 assert(src
.regClass() == bld
.lm
);
7875 assert(dst
.regClass() == bld
.lm
);
7876 uint32_t half_mask
= 0x11111111u
<< lane
;
7877 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7878 Temp tmp
= bld
.tmp(bld
.lm
);
7879 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7880 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7881 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7882 emit_wqm(ctx
, tmp
, dst
);
7883 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7884 Temp tmp
= bld
.tmp(v1
);
7885 if (ctx
->program
->chip_class
>= GFX8
)
7886 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7888 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7889 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7890 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7891 Temp tmp
= bld
.tmp(v1
);
7892 if (ctx
->program
->chip_class
>= GFX8
)
7893 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7895 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7896 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7897 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7898 if (ctx
->program
->chip_class
>= GFX8
)
7899 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7901 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7902 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7903 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7904 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7905 if (ctx
->program
->chip_class
>= GFX8
) {
7906 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7907 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7909 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7910 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7912 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7913 emit_split_vector(ctx
, dst
, 2);
7915 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7916 nir_print_instr(&instr
->instr
, stderr
);
7917 fprintf(stderr
, "\n");
7922 case nir_intrinsic_quad_swap_horizontal
:
7923 case nir_intrinsic_quad_swap_vertical
:
7924 case nir_intrinsic_quad_swap_diagonal
:
7925 case nir_intrinsic_quad_swizzle_amd
: {
7926 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7927 if (!nir_dest_is_divergent(instr
->dest
)) {
7928 emit_uniform_subgroup(ctx
, instr
, src
);
7931 uint16_t dpp_ctrl
= 0;
7932 switch (instr
->intrinsic
) {
7933 case nir_intrinsic_quad_swap_horizontal
:
7934 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7936 case nir_intrinsic_quad_swap_vertical
:
7937 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7939 case nir_intrinsic_quad_swap_diagonal
:
7940 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7942 case nir_intrinsic_quad_swizzle_amd
:
7943 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7948 if (ctx
->program
->chip_class
< GFX8
)
7949 dpp_ctrl
|= (1 << 15);
7951 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7952 if (instr
->dest
.ssa
.bit_size
== 1) {
7953 assert(src
.regClass() == bld
.lm
);
7954 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7955 if (ctx
->program
->chip_class
>= GFX8
)
7956 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7958 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7959 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7960 emit_wqm(ctx
, tmp
, dst
);
7961 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7962 Temp tmp
= bld
.tmp(v1
);
7963 if (ctx
->program
->chip_class
>= GFX8
)
7964 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7966 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7967 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7968 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7969 Temp tmp
= bld
.tmp(v1
);
7970 if (ctx
->program
->chip_class
>= GFX8
)
7971 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7973 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7974 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7975 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7977 if (ctx
->program
->chip_class
>= GFX8
)
7978 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7980 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7981 emit_wqm(ctx
, tmp
, dst
);
7982 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7983 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7984 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7985 if (ctx
->program
->chip_class
>= GFX8
) {
7986 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7987 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7989 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7990 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7992 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7993 emit_split_vector(ctx
, dst
, 2);
7995 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7996 nir_print_instr(&instr
->instr
, stderr
);
7997 fprintf(stderr
, "\n");
8001 case nir_intrinsic_masked_swizzle_amd
: {
8002 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8003 if (!nir_dest_is_divergent(instr
->dest
)) {
8004 emit_uniform_subgroup(ctx
, instr
, src
);
8007 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8008 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
8009 if (instr
->dest
.ssa
.bit_size
== 1) {
8010 assert(src
.regClass() == bld
.lm
);
8011 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
8012 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
8013 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8014 emit_wqm(ctx
, tmp
, dst
);
8015 } else if (dst
.regClass() == v1b
) {
8016 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8017 emit_extract_vector(ctx
, tmp
, 0, dst
);
8018 } else if (dst
.regClass() == v2b
) {
8019 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8020 emit_extract_vector(ctx
, tmp
, 0, dst
);
8021 } else if (dst
.regClass() == v1
) {
8022 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
8023 } else if (dst
.regClass() == v2
) {
8024 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8026 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
8027 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
8028 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8029 emit_split_vector(ctx
, dst
, 2);
8031 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8032 nir_print_instr(&instr
->instr
, stderr
);
8033 fprintf(stderr
, "\n");
8037 case nir_intrinsic_write_invocation_amd
: {
8038 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8039 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8040 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8041 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8042 if (dst
.regClass() == v1
) {
8043 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8044 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8045 } else if (dst
.regClass() == v2
) {
8046 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8047 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8048 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8049 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8050 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8051 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8052 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8053 emit_split_vector(ctx
, dst
, 2);
8055 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8056 nir_print_instr(&instr
->instr
, stderr
);
8057 fprintf(stderr
, "\n");
8061 case nir_intrinsic_mbcnt_amd
: {
8062 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8063 RegClass rc
= RegClass(src
.type(), 1);
8064 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8065 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8066 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8067 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8068 emit_wqm(ctx
, wqm_tmp
, dst
);
8071 case nir_intrinsic_load_helper_invocation
: {
8072 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8073 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8074 ctx
->block
->kind
|= block_kind_needs_lowering
;
8075 ctx
->program
->needs_exact
= true;
8078 case nir_intrinsic_is_helper_invocation
: {
8079 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8080 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8081 ctx
->block
->kind
|= block_kind_needs_lowering
;
8082 ctx
->program
->needs_exact
= true;
8085 case nir_intrinsic_demote
:
8086 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8088 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8089 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8090 ctx
->block
->kind
|= block_kind_uses_demote
;
8091 ctx
->program
->needs_exact
= true;
8093 case nir_intrinsic_demote_if
: {
8094 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8095 assert(src
.regClass() == bld
.lm
);
8096 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8097 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8099 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8100 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8101 ctx
->block
->kind
|= block_kind_uses_demote
;
8102 ctx
->program
->needs_exact
= true;
8105 case nir_intrinsic_first_invocation
: {
8106 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8107 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8110 case nir_intrinsic_shader_clock
: {
8112 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8113 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8114 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), memory_sync_info(0, semantic_volatile
));
8115 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8118 case nir_intrinsic_load_vertex_id_zero_base
: {
8119 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8120 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8123 case nir_intrinsic_load_first_vertex
: {
8124 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8125 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8128 case nir_intrinsic_load_base_instance
: {
8129 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8130 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8133 case nir_intrinsic_load_instance_id
: {
8134 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8135 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8138 case nir_intrinsic_load_draw_id
: {
8139 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8140 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8143 case nir_intrinsic_load_invocation_id
: {
8144 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8146 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8147 if (ctx
->options
->chip_class
>= GFX10
)
8148 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8150 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8151 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8152 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8153 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8155 unreachable("Unsupported stage for load_invocation_id");
8160 case nir_intrinsic_load_primitive_id
: {
8161 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8163 switch (ctx
->shader
->info
.stage
) {
8164 case MESA_SHADER_GEOMETRY
:
8165 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8167 case MESA_SHADER_TESS_CTRL
:
8168 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8170 case MESA_SHADER_TESS_EVAL
:
8171 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8174 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8179 case nir_intrinsic_load_patch_vertices_in
: {
8180 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8181 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8183 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8184 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8187 case nir_intrinsic_emit_vertex_with_counter
: {
8188 visit_emit_vertex_with_counter(ctx
, instr
);
8191 case nir_intrinsic_end_primitive_with_counter
: {
8192 unsigned stream
= nir_intrinsic_stream_id(instr
);
8193 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8196 case nir_intrinsic_set_vertex_count
: {
8197 /* unused, the HW keeps track of this for us */
8201 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8202 nir_print_instr(&instr
->instr
, stderr
);
8203 fprintf(stderr
, "\n");
8211 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8212 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8213 enum glsl_base_type
*stype
)
8215 nir_deref_instr
*texture_deref_instr
= NULL
;
8216 nir_deref_instr
*sampler_deref_instr
= NULL
;
8219 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8220 switch (instr
->src
[i
].src_type
) {
8221 case nir_tex_src_texture_deref
:
8222 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8224 case nir_tex_src_sampler_deref
:
8225 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8227 case nir_tex_src_plane
:
8228 plane
= nir_src_as_int(instr
->src
[i
].src
);
8235 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8237 if (!sampler_deref_instr
)
8238 sampler_deref_instr
= texture_deref_instr
;
8241 assert(instr
->op
!= nir_texop_txf_ms
&&
8242 instr
->op
!= nir_texop_samples_identical
);
8243 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8244 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8245 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8246 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8247 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8248 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8250 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8253 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8255 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8256 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8257 Builder
bld(ctx
->program
, ctx
->block
);
8259 /* to avoid unnecessary moves, we split and recombine sampler and image */
8260 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8261 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8262 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8263 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8264 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8265 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8267 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8269 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8270 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8271 img
[0], img
[1], img
[2], img
[3],
8272 img
[4], img
[5], img
[6], img
[7]);
8273 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8274 samp
[0], samp
[1], samp
[2], samp
[3]);
8277 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8278 instr
->op
== nir_texop_samples_identical
))
8279 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8282 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8283 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8285 Builder
bld(ctx
->program
, ctx
->block
);
8287 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8288 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8289 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8291 Operand
neg_one(0xbf800000u
);
8292 Operand
one(0x3f800000u
);
8293 Operand
two(0x40000000u
);
8294 Operand
four(0x40800000u
);
8296 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8297 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8298 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8300 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8301 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8302 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8303 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8306 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8307 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8308 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8310 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8313 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8314 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8315 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8318 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8319 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8321 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8322 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8325 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8327 Builder
bld(ctx
->program
, ctx
->block
);
8328 Temp ma
, tc
, sc
, id
;
8331 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8333 // see comment in ac_prepare_cube_coords()
8334 if (ctx
->options
->chip_class
<= GFX8
)
8335 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8338 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8340 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8341 vop3a
->operands
[0] = Operand(ma
);
8342 vop3a
->abs
[0] = true;
8343 Temp invma
= bld
.tmp(v1
);
8344 vop3a
->definitions
[0] = Definition(invma
);
8345 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8347 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8349 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8351 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8353 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8355 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8358 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8359 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8361 for (unsigned i
= 0; i
< 2; i
++) {
8362 // see comment in ac_prepare_cube_coords()
8364 Temp deriv_sc
, deriv_tc
;
8365 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8366 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8368 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8370 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8371 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8372 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8373 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8374 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8375 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8376 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8379 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8380 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8384 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8391 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8393 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8395 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8396 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8399 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8400 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8401 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8405 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8407 Builder
bld(ctx
->program
, ctx
->block
);
8408 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8409 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8410 has_clamped_lod
= false;
8411 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8412 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8413 clamped_lod
= Temp();
8414 std::vector
<Temp
> coords
;
8415 std::vector
<Temp
> derivs
;
8416 nir_const_value
*sample_index_cv
= NULL
;
8417 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8418 enum glsl_base_type stype
;
8419 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8421 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8422 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8423 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8424 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8426 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8427 switch (instr
->src
[i
].src_type
) {
8428 case nir_tex_src_coord
: {
8429 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8430 for (unsigned i
= 0; i
< coord
.size(); i
++)
8431 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8434 case nir_tex_src_bias
:
8435 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8438 case nir_tex_src_lod
: {
8439 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8441 if (val
&& val
->f32
<= 0.0) {
8444 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8449 case nir_tex_src_min_lod
:
8450 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8451 has_clamped_lod
= true;
8453 case nir_tex_src_comparator
:
8454 if (instr
->is_shadow
) {
8455 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8459 case nir_tex_src_offset
:
8460 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8461 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8464 case nir_tex_src_ddx
:
8465 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8468 case nir_tex_src_ddy
:
8469 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8472 case nir_tex_src_ms_index
:
8473 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8474 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8475 has_sample_index
= true;
8477 case nir_tex_src_texture_offset
:
8478 case nir_tex_src_sampler_offset
:
8484 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8485 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8487 if (instr
->op
== nir_texop_texture_samples
) {
8488 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8490 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8491 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8492 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8494 Operand default_sample
= Operand(1u);
8495 if (ctx
->options
->robust_buffer_access
) {
8496 /* Extract the second dword of the descriptor, if it's
8497 * all zero, then it's a null descriptor.
8499 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8500 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8501 default_sample
= Operand(is_non_null_descriptor
);
8504 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8505 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8506 samples
, default_sample
, bld
.scc(is_msaa
));
8510 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8511 aco_ptr
<Instruction
> tmp_instr
;
8512 Temp acc
, pack
= Temp();
8514 uint32_t pack_const
= 0;
8515 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8516 if (!const_offset
[i
])
8518 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8521 if (offset
.type() == RegType::sgpr
) {
8522 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8523 if (const_offset
[i
])
8526 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8527 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8530 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8533 if (pack
== Temp()) {
8536 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8540 if (pack_const
&& pack
!= Temp())
8541 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8543 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8544 if (const_offset
[i
])
8547 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8548 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8551 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8554 if (pack
== Temp()) {
8557 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8561 if (pack_const
&& pack
!= Temp())
8562 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8564 if (pack_const
&& pack
== Temp())
8565 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8566 else if (pack
== Temp())
8572 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8573 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8575 /* pack derivatives */
8576 if (has_ddx
|| has_ddy
) {
8577 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8578 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8579 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8580 derivs
= {ddx
, zero
, ddy
, zero
};
8582 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8583 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8584 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8585 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8590 if (instr
->coord_components
> 1 &&
8591 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8593 instr
->op
!= nir_texop_txf
)
8594 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8596 if (instr
->coord_components
> 2 &&
8597 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8598 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8599 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8600 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8602 instr
->op
!= nir_texop_txf
&&
8603 instr
->op
!= nir_texop_txf_ms
&&
8604 instr
->op
!= nir_texop_fragment_fetch
&&
8605 instr
->op
!= nir_texop_fragment_mask_fetch
)
8606 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8608 if (ctx
->options
->chip_class
== GFX9
&&
8609 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8610 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8611 assert(coords
.size() > 0 && coords
.size() < 3);
8613 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8614 Operand((uint32_t) 0) :
8615 Operand((uint32_t) 0x3f000000)));
8618 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8620 if (instr
->op
== nir_texop_samples_identical
)
8621 resource
= fmask_ptr
;
8623 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8624 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8625 instr
->op
!= nir_texop_txs
&&
8626 instr
->op
!= nir_texop_fragment_fetch
&&
8627 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8628 assert(has_sample_index
);
8629 Operand
op(sample_index
);
8630 if (sample_index_cv
)
8631 op
= Operand(sample_index_cv
->u32
);
8632 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8635 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8636 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8637 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8638 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8643 /* Build tex instruction */
8644 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8645 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8646 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8648 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8651 /* gather4 selects the component by dmask and always returns vec4 */
8652 if (instr
->op
== nir_texop_tg4
) {
8653 assert(instr
->dest
.ssa
.num_components
== 4);
8654 if (instr
->is_shadow
)
8657 dmask
= 1 << instr
->component
;
8658 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8659 tmp_dst
= bld
.tmp(v4
);
8660 } else if (instr
->op
== nir_texop_samples_identical
) {
8661 tmp_dst
= bld
.tmp(v1
);
8662 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8663 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8666 aco_ptr
<MIMG_instruction
> tex
;
8667 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8669 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8671 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8672 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8675 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8676 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8678 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8679 tex
->operands
[0] = Operand(resource
);
8680 tex
->operands
[1] = Operand(s4
); /* no sampler */
8681 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8682 if (ctx
->options
->chip_class
== GFX9
&&
8683 instr
->op
== nir_texop_txs
&&
8684 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8686 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8687 } else if (instr
->op
== nir_texop_query_levels
) {
8688 tex
->dmask
= 1 << 3;
8693 tex
->definitions
[0] = Definition(tmp_dst
);
8695 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8698 /* divide 3rd value by 6 by multiplying with magic number */
8699 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8700 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8701 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8702 assert(instr
->dest
.ssa
.num_components
== 3);
8703 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8704 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8705 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8706 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8711 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8715 Temp tg4_compare_cube_wa64
= Temp();
8717 if (tg4_integer_workarounds
) {
8718 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8719 tex
->operands
[0] = Operand(resource
);
8720 tex
->operands
[1] = Operand(s4
); /* no sampler */
8721 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8725 Temp size
= bld
.tmp(v2
);
8726 tex
->definitions
[0] = Definition(size
);
8727 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8728 emit_split_vector(ctx
, size
, size
.size());
8731 for (unsigned i
= 0; i
< 2; i
++) {
8732 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8733 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8734 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8735 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8738 Temp new_coords
[2] = {
8739 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8740 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8743 if (tg4_integer_cube_workaround
) {
8744 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8745 Temp desc
[resource
.size()];
8746 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8747 Format::PSEUDO
, 1, resource
.size())};
8748 split
->operands
[0] = Operand(resource
);
8749 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8750 desc
[i
] = bld
.tmp(s1
);
8751 split
->definitions
[i
] = Definition(desc
[i
]);
8753 ctx
->block
->instructions
.emplace_back(std::move(split
));
8755 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8756 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8757 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8760 if (stype
== GLSL_TYPE_UINT
) {
8761 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8762 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8763 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8764 bld
.scc(compare_cube_wa
));
8766 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8767 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8768 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8769 bld
.scc(compare_cube_wa
));
8771 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8772 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8774 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8776 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8777 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8778 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8780 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8781 Format::PSEUDO
, resource
.size(), 1)};
8782 for (unsigned i
= 0; i
< resource
.size(); i
++)
8783 vec
->operands
[i
] = Operand(desc
[i
]);
8784 resource
= bld
.tmp(resource
.regClass());
8785 vec
->definitions
[0] = Definition(resource
);
8786 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8788 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8789 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8790 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8791 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8793 coords
[0] = new_coords
[0];
8794 coords
[1] = new_coords
[1];
8797 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8798 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8800 assert(coords
.size() == 1);
8801 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8805 op
= aco_opcode::buffer_load_format_x
; break;
8807 op
= aco_opcode::buffer_load_format_xy
; break;
8809 op
= aco_opcode::buffer_load_format_xyz
; break;
8811 op
= aco_opcode::buffer_load_format_xyzw
; break;
8813 unreachable("Tex instruction loads more than 4 components.");
8816 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8817 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8820 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8822 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8823 mubuf
->operands
[0] = Operand(resource
);
8824 mubuf
->operands
[1] = Operand(coords
[0]);
8825 mubuf
->operands
[2] = Operand((uint32_t) 0);
8826 mubuf
->definitions
[0] = Definition(tmp_dst
);
8827 mubuf
->idxen
= true;
8828 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8830 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8834 /* gather MIMG address components */
8835 std::vector
<Temp
> args
;
8837 args
.emplace_back(offset
);
8839 args
.emplace_back(bias
);
8841 args
.emplace_back(compare
);
8843 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8845 args
.insert(args
.end(), coords
.begin(), coords
.end());
8846 if (has_sample_index
)
8847 args
.emplace_back(sample_index
);
8849 args
.emplace_back(lod
);
8850 if (has_clamped_lod
)
8851 args
.emplace_back(clamped_lod
);
8853 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8854 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8855 vec
->definitions
[0] = Definition(arg
);
8856 for (unsigned i
= 0; i
< args
.size(); i
++)
8857 vec
->operands
[i
] = Operand(args
[i
]);
8858 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8861 if (instr
->op
== nir_texop_txf
||
8862 instr
->op
== nir_texop_txf_ms
||
8863 instr
->op
== nir_texop_samples_identical
||
8864 instr
->op
== nir_texop_fragment_fetch
||
8865 instr
->op
== nir_texop_fragment_mask_fetch
) {
8866 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8867 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8868 tex
->operands
[0] = Operand(resource
);
8869 tex
->operands
[1] = Operand(s4
); /* no sampler */
8870 tex
->operands
[2] = Operand(arg
);
8875 tex
->definitions
[0] = Definition(tmp_dst
);
8876 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8878 if (instr
->op
== nir_texop_samples_identical
) {
8879 assert(dmask
== 1 && dst
.regClass() == v1
);
8880 assert(dst
.id() != tmp_dst
.id());
8882 Temp tmp
= bld
.tmp(bld
.lm
);
8883 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8884 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8887 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8892 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8893 aco_opcode opcode
= aco_opcode::image_sample
;
8894 if (has_offset
) { /* image_sample_*_o */
8895 if (has_clamped_lod
) {
8897 opcode
= aco_opcode::image_sample_c_cl_o
;
8899 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8901 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8903 opcode
= aco_opcode::image_sample_cl_o
;
8905 opcode
= aco_opcode::image_sample_d_cl_o
;
8907 opcode
= aco_opcode::image_sample_b_cl_o
;
8909 } else if (has_compare
) {
8910 opcode
= aco_opcode::image_sample_c_o
;
8912 opcode
= aco_opcode::image_sample_c_d_o
;
8914 opcode
= aco_opcode::image_sample_c_b_o
;
8916 opcode
= aco_opcode::image_sample_c_lz_o
;
8918 opcode
= aco_opcode::image_sample_c_l_o
;
8920 opcode
= aco_opcode::image_sample_o
;
8922 opcode
= aco_opcode::image_sample_d_o
;
8924 opcode
= aco_opcode::image_sample_b_o
;
8926 opcode
= aco_opcode::image_sample_lz_o
;
8928 opcode
= aco_opcode::image_sample_l_o
;
8930 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8932 opcode
= aco_opcode::image_sample_c_cl
;
8934 opcode
= aco_opcode::image_sample_c_d_cl
;
8936 opcode
= aco_opcode::image_sample_c_b_cl
;
8938 opcode
= aco_opcode::image_sample_cl
;
8940 opcode
= aco_opcode::image_sample_d_cl
;
8942 opcode
= aco_opcode::image_sample_b_cl
;
8944 } else { /* no offset */
8946 opcode
= aco_opcode::image_sample_c
;
8948 opcode
= aco_opcode::image_sample_c_d
;
8950 opcode
= aco_opcode::image_sample_c_b
;
8952 opcode
= aco_opcode::image_sample_c_lz
;
8954 opcode
= aco_opcode::image_sample_c_l
;
8956 opcode
= aco_opcode::image_sample
;
8958 opcode
= aco_opcode::image_sample_d
;
8960 opcode
= aco_opcode::image_sample_b
;
8962 opcode
= aco_opcode::image_sample_lz
;
8964 opcode
= aco_opcode::image_sample_l
;
8968 if (instr
->op
== nir_texop_tg4
) {
8969 if (has_offset
) { /* image_gather4_*_o */
8971 opcode
= aco_opcode::image_gather4_c_lz_o
;
8973 opcode
= aco_opcode::image_gather4_c_l_o
;
8975 opcode
= aco_opcode::image_gather4_c_b_o
;
8977 opcode
= aco_opcode::image_gather4_lz_o
;
8979 opcode
= aco_opcode::image_gather4_l_o
;
8981 opcode
= aco_opcode::image_gather4_b_o
;
8985 opcode
= aco_opcode::image_gather4_c_lz
;
8987 opcode
= aco_opcode::image_gather4_c_l
;
8989 opcode
= aco_opcode::image_gather4_c_b
;
8991 opcode
= aco_opcode::image_gather4_lz
;
8993 opcode
= aco_opcode::image_gather4_l
;
8995 opcode
= aco_opcode::image_gather4_b
;
8998 } else if (instr
->op
== nir_texop_lod
) {
8999 opcode
= aco_opcode::image_get_lod
;
9002 /* we don't need the bias, sample index, compare value or offset to be
9003 * computed in WQM but if the p_create_vector copies the coordinates, then it
9004 * needs to be in WQM */
9005 if (ctx
->stage
== fragment_fs
&&
9006 !has_derivs
&& !has_lod
&& !level_zero
&&
9007 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
9008 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
9009 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
9011 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
9012 tex
->operands
[0] = Operand(resource
);
9013 tex
->operands
[1] = Operand(sampler
);
9014 tex
->operands
[2] = Operand(arg
);
9018 tex
->definitions
[0] = Definition(tmp_dst
);
9019 ctx
->block
->instructions
.emplace_back(std::move(tex
));
9021 if (tg4_integer_cube_workaround
) {
9022 assert(tmp_dst
.id() != dst
.id());
9023 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
9025 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
9027 for (unsigned i
= 0; i
< dst
.size(); i
++) {
9028 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
9030 if (stype
== GLSL_TYPE_UINT
)
9031 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
9033 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
9034 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
9036 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
9037 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
9038 val
[0], val
[1], val
[2], val
[3]);
9040 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
9041 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
9046 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
9048 Temp tmp
= get_ssa_temp(ctx
, ssa
);
9049 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
9051 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
9052 if (ctx
->program
->wave_size
== 64)
9053 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
9055 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
9057 return Operand(tmp
);
9061 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9063 aco_ptr
<Pseudo_instruction
> phi
;
9064 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9065 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9067 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
9068 logical
|= ctx
->block
->kind
& block_kind_merge
;
9069 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9071 /* we want a sorted list of sources, since the predecessor list is also sorted */
9072 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9073 nir_foreach_phi_src(src
, instr
)
9074 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9076 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9077 unsigned num_operands
= 0;
9078 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9079 unsigned num_defined
= 0;
9080 unsigned cur_pred_idx
= 0;
9081 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9082 if (cur_pred_idx
< preds
.size()) {
9083 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9084 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9085 unsigned skipped
= 0;
9086 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9088 if (cur_pred_idx
+ skipped
< preds
.size()) {
9089 for (unsigned i
= 0; i
< skipped
; i
++)
9090 operands
[num_operands
++] = Operand(dst
.regClass());
9091 cur_pred_idx
+= skipped
;
9096 /* Handle missing predecessors at the end. This shouldn't happen with loop
9097 * headers and we can't ignore these sources for loop header phis. */
9098 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9101 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9102 operands
[num_operands
++] = op
;
9103 num_defined
+= !op
.isUndefined();
9105 /* handle block_kind_continue_or_break at loop exit blocks */
9106 while (cur_pred_idx
++ < preds
.size())
9107 operands
[num_operands
++] = Operand(dst
.regClass());
9109 /* If the loop ends with a break, still add a linear continue edge in case
9110 * that break is divergent or continue_or_break is used. We'll either remove
9111 * this operand later in visit_loop() if it's not necessary or replace the
9112 * undef with something correct. */
9113 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9114 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9115 nir_block
*last
= nir_loop_last_block(loop
);
9116 if (last
->successors
[0] != instr
->instr
.block
)
9117 operands
[num_operands
++] = Operand(RegClass());
9120 if (num_defined
== 0) {
9121 Builder
bld(ctx
->program
, ctx
->block
);
9122 if (dst
.regClass() == s1
) {
9123 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9124 } else if (dst
.regClass() == v1
) {
9125 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9127 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9128 for (unsigned i
= 0; i
< dst
.size(); i
++)
9129 vec
->operands
[i
] = Operand(0u);
9130 vec
->definitions
[0] = Definition(dst
);
9131 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9136 /* we can use a linear phi in some cases if one src is undef */
9137 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9138 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9140 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9141 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9142 assert(invert
->kind
& block_kind_invert
);
9144 unsigned then_block
= invert
->linear_preds
[0];
9146 Block
* insert_block
= NULL
;
9147 for (unsigned i
= 0; i
< num_operands
; i
++) {
9148 Operand op
= operands
[i
];
9149 if (op
.isUndefined())
9151 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9152 phi
->operands
[0] = op
;
9155 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9156 phi
->operands
[1] = Operand(dst
.regClass());
9157 phi
->definitions
[0] = Definition(dst
);
9158 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9162 /* try to scalarize vector phis */
9163 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9164 // TODO: scalarize linear phis on divergent ifs
9165 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9166 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9167 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9168 Operand src
= operands
[i
];
9169 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9170 can_scalarize
= false;
9172 if (can_scalarize
) {
9173 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9174 assert(dst
.size() % num_components
== 0);
9175 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9177 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9178 for (unsigned k
= 0; k
< num_components
; k
++) {
9179 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9180 for (unsigned i
= 0; i
< num_operands
; i
++) {
9181 Operand src
= operands
[i
];
9182 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9184 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9185 phi
->definitions
[0] = Definition(phi_dst
);
9186 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9187 new_vec
[k
] = phi_dst
;
9188 vec
->operands
[k
] = Operand(phi_dst
);
9190 vec
->definitions
[0] = Definition(dst
);
9191 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9192 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9197 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9198 for (unsigned i
= 0; i
< num_operands
; i
++)
9199 phi
->operands
[i
] = operands
[i
];
9200 phi
->definitions
[0] = Definition(dst
);
9201 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9205 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9207 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9209 assert(dst
.type() == RegType::sgpr
);
9211 if (dst
.size() == 1) {
9212 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9214 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9215 for (unsigned i
= 0; i
< dst
.size(); i
++)
9216 vec
->operands
[i
] = Operand(0u);
9217 vec
->definitions
[0] = Definition(dst
);
9218 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9222 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9224 Builder
bld(ctx
->program
, ctx
->block
);
9225 Block
*logical_target
;
9226 append_logical_end(ctx
->block
);
9227 unsigned idx
= ctx
->block
->index
;
9229 switch (instr
->type
) {
9230 case nir_jump_break
:
9231 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9232 add_logical_edge(idx
, logical_target
);
9233 ctx
->block
->kind
|= block_kind_break
;
9235 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9236 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9237 /* uniform break - directly jump out of the loop */
9238 ctx
->block
->kind
|= block_kind_uniform
;
9239 ctx
->cf_info
.has_branch
= true;
9240 bld
.branch(aco_opcode::p_branch
);
9241 add_linear_edge(idx
, logical_target
);
9244 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9245 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9247 case nir_jump_continue
:
9248 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9249 add_logical_edge(idx
, logical_target
);
9250 ctx
->block
->kind
|= block_kind_continue
;
9252 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9253 /* for potential uniform breaks after this continue,
9254 we must ensure that they are handled correctly */
9255 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9256 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9257 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9259 /* uniform continue - directly jump to the loop header */
9260 ctx
->block
->kind
|= block_kind_uniform
;
9261 ctx
->cf_info
.has_branch
= true;
9262 bld
.branch(aco_opcode::p_branch
);
9263 add_linear_edge(idx
, logical_target
);
9268 fprintf(stderr
, "Unknown NIR jump instr: ");
9269 nir_print_instr(&instr
->instr
, stderr
);
9270 fprintf(stderr
, "\n");
9274 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9275 ctx
->cf_info
.exec_potentially_empty_break
= true;
9276 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9279 /* remove critical edges from linear CFG */
9280 bld
.branch(aco_opcode::p_branch
);
9281 Block
* break_block
= ctx
->program
->create_and_insert_block();
9282 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9283 break_block
->kind
|= block_kind_uniform
;
9284 add_linear_edge(idx
, break_block
);
9285 /* the loop_header pointer might be invalidated by this point */
9286 if (instr
->type
== nir_jump_continue
)
9287 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9288 add_linear_edge(break_block
->index
, logical_target
);
9289 bld
.reset(break_block
);
9290 bld
.branch(aco_opcode::p_branch
);
9292 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9293 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9294 add_linear_edge(idx
, continue_block
);
9295 append_logical_start(continue_block
);
9296 ctx
->block
= continue_block
;
9300 void visit_block(isel_context
*ctx
, nir_block
*block
)
9302 nir_foreach_instr(instr
, block
) {
9303 switch (instr
->type
) {
9304 case nir_instr_type_alu
:
9305 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9307 case nir_instr_type_load_const
:
9308 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9310 case nir_instr_type_intrinsic
:
9311 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9313 case nir_instr_type_tex
:
9314 visit_tex(ctx
, nir_instr_as_tex(instr
));
9316 case nir_instr_type_phi
:
9317 visit_phi(ctx
, nir_instr_as_phi(instr
));
9319 case nir_instr_type_ssa_undef
:
9320 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9322 case nir_instr_type_deref
:
9324 case nir_instr_type_jump
:
9325 visit_jump(ctx
, nir_instr_as_jump(instr
));
9328 fprintf(stderr
, "Unknown NIR instr type: ");
9329 nir_print_instr(instr
, stderr
);
9330 fprintf(stderr
, "\n");
9335 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9336 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9341 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9342 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9344 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9345 RegClass rc
= vals
[0].regClass();
9347 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9349 unsigned next_pred
= 1;
9351 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9352 Block
& block
= ctx
->program
->blocks
[idx
];
9353 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9354 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9358 if (block
.kind
& block_kind_continue
) {
9359 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9364 bool all_same
= true;
9365 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9366 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9370 val
= vals
[block
.linear_preds
[0] - first
];
9372 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9373 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9374 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9375 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9376 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9377 phi
->definitions
[0] = Definition(val
.getTemp());
9378 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9380 vals
[idx
- first
] = val
;
9383 return vals
[last
- first
];
9386 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9388 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9389 append_logical_end(ctx
->block
);
9390 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9391 Builder
bld(ctx
->program
, ctx
->block
);
9392 bld
.branch(aco_opcode::p_branch
);
9393 unsigned loop_preheader_idx
= ctx
->block
->index
;
9395 Block loop_exit
= Block();
9396 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9397 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9399 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9400 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9401 loop_header
->kind
|= block_kind_loop_header
;
9402 add_edge(loop_preheader_idx
, loop_header
);
9403 ctx
->block
= loop_header
;
9405 /* emit loop body */
9406 unsigned loop_header_idx
= loop_header
->index
;
9407 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9408 append_logical_start(ctx
->block
);
9409 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9411 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9412 if (!ctx
->cf_info
.has_branch
) {
9413 append_logical_end(ctx
->block
);
9414 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9415 /* Discards can result in code running with an empty exec mask.
9416 * This would result in divergent breaks not ever being taken. As a
9417 * workaround, break the loop when the loop mask is empty instead of
9418 * always continuing. */
9419 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9420 unsigned block_idx
= ctx
->block
->index
;
9422 /* create helper blocks to avoid critical edges */
9423 Block
*break_block
= ctx
->program
->create_and_insert_block();
9424 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9425 break_block
->kind
= block_kind_uniform
;
9426 bld
.reset(break_block
);
9427 bld
.branch(aco_opcode::p_branch
);
9428 add_linear_edge(block_idx
, break_block
);
9429 add_linear_edge(break_block
->index
, &loop_exit
);
9431 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9432 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9433 continue_block
->kind
= block_kind_uniform
;
9434 bld
.reset(continue_block
);
9435 bld
.branch(aco_opcode::p_branch
);
9436 add_linear_edge(block_idx
, continue_block
);
9437 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9439 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9440 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9441 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9443 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9444 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9445 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9447 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9450 bld
.reset(ctx
->block
);
9451 bld
.branch(aco_opcode::p_branch
);
9454 /* Fixup phis in loop header from unreachable blocks.
9455 * has_branch/has_divergent_branch also indicates if the loop ends with a
9456 * break/continue instruction, but we don't emit those if unreachable=true */
9458 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9459 bool linear
= ctx
->cf_info
.has_branch
;
9460 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9461 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9462 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9463 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9464 /* the last operand should be the one that needs to be removed */
9465 instr
->operands
.pop_back();
9466 } else if (!is_phi(instr
)) {
9472 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9473 * and the previous one shouldn't both happen at once because a break in the
9474 * merge block would get CSE'd */
9475 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9476 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9477 Operand vals
[num_vals
];
9478 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9479 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9480 if (ctx
->cf_info
.has_branch
)
9481 instr
->operands
.pop_back();
9483 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9484 } else if (!is_phi(instr
)) {
9490 ctx
->cf_info
.has_branch
= false;
9492 // TODO: if the loop has not a single exit, we must add one °°
9493 /* emit loop successor block */
9494 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9495 append_logical_start(ctx
->block
);
9498 // TODO: check if it is beneficial to not branch on continues
9499 /* trim linear phis in loop header */
9500 for (auto&& instr
: loop_entry
->instructions
) {
9501 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9502 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9503 new_phi
->definitions
[0] = instr
->definitions
[0];
9504 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9505 new_phi
->operands
[i
] = instr
->operands
[i
];
9506 /* check that the remaining operands are all the same */
9507 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9508 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9509 instr
.swap(new_phi
);
9510 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9519 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9523 append_logical_end(ctx
->block
);
9524 ctx
->block
->kind
|= block_kind_branch
;
9526 /* branch to linear then block */
9527 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9528 aco_ptr
<Pseudo_branch_instruction
> branch
;
9529 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9530 branch
->operands
[0] = Operand(cond
);
9531 ctx
->block
->instructions
.push_back(std::move(branch
));
9533 ic
->BB_if_idx
= ctx
->block
->index
;
9534 ic
->BB_invert
= Block();
9535 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9536 /* Invert blocks are intentionally not marked as top level because they
9537 * are not part of the logical cfg. */
9538 ic
->BB_invert
.kind
|= block_kind_invert
;
9539 ic
->BB_endif
= Block();
9540 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9541 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9543 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9544 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9545 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9546 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9547 ctx
->cf_info
.parent_if
.is_divergent
= true;
9549 /* divergent branches use cbranch_execz */
9550 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9551 ctx
->cf_info
.exec_potentially_empty_break
= false;
9552 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9554 /** emit logical then block */
9555 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9556 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9557 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9558 ctx
->block
= BB_then_logical
;
9559 append_logical_start(BB_then_logical
);
9562 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9564 Block
*BB_then_logical
= ctx
->block
;
9565 append_logical_end(BB_then_logical
);
9566 /* branch from logical then block to invert block */
9567 aco_ptr
<Pseudo_branch_instruction
> branch
;
9568 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9569 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9570 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9571 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9572 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9573 BB_then_logical
->kind
|= block_kind_uniform
;
9574 assert(!ctx
->cf_info
.has_branch
);
9575 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9576 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9578 /** emit linear then block */
9579 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9580 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9581 BB_then_linear
->kind
|= block_kind_uniform
;
9582 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9583 /* branch from linear then block to invert block */
9584 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9585 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9586 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9588 /** emit invert merge block */
9589 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9590 ic
->invert_idx
= ctx
->block
->index
;
9592 /* branch to linear else block (skip else) */
9593 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9594 branch
->operands
[0] = Operand(ic
->cond
);
9595 ctx
->block
->instructions
.push_back(std::move(branch
));
9597 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9598 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9599 ic
->exec_potentially_empty_break_depth_old
=
9600 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9601 /* divergent branches use cbranch_execz */
9602 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9603 ctx
->cf_info
.exec_potentially_empty_break
= false;
9604 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9606 /** emit logical else block */
9607 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9608 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9609 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9610 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9611 ctx
->block
= BB_else_logical
;
9612 append_logical_start(BB_else_logical
);
9615 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9617 Block
*BB_else_logical
= ctx
->block
;
9618 append_logical_end(BB_else_logical
);
9620 /* branch from logical else block to endif block */
9621 aco_ptr
<Pseudo_branch_instruction
> branch
;
9622 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9623 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9624 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9625 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9626 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9627 BB_else_logical
->kind
|= block_kind_uniform
;
9629 assert(!ctx
->cf_info
.has_branch
);
9630 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9633 /** emit linear else block */
9634 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9635 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9636 BB_else_linear
->kind
|= block_kind_uniform
;
9637 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9639 /* branch from linear else block to endif block */
9640 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9641 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9642 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9645 /** emit endif merge block */
9646 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9647 append_logical_start(ctx
->block
);
9650 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9651 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9652 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9653 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9654 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9655 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9656 !ctx
->cf_info
.parent_if
.is_divergent
) {
9657 ctx
->cf_info
.exec_potentially_empty_break
= false;
9658 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9660 /* uniform control flow never has an empty exec-mask */
9661 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9662 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9663 ctx
->cf_info
.exec_potentially_empty_break
= false;
9664 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9668 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9670 assert(cond
.regClass() == s1
);
9672 append_logical_end(ctx
->block
);
9673 ctx
->block
->kind
|= block_kind_uniform
;
9675 aco_ptr
<Pseudo_branch_instruction
> branch
;
9676 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9677 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9678 branch
->operands
[0] = Operand(cond
);
9679 branch
->operands
[0].setFixed(scc
);
9680 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9682 ic
->BB_if_idx
= ctx
->block
->index
;
9683 ic
->BB_endif
= Block();
9684 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9685 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9687 ctx
->cf_info
.has_branch
= false;
9688 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9690 /** emit then block */
9691 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9692 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9693 add_edge(ic
->BB_if_idx
, BB_then
);
9694 append_logical_start(BB_then
);
9695 ctx
->block
= BB_then
;
9698 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9700 Block
*BB_then
= ctx
->block
;
9702 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9703 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9705 if (!ic
->uniform_has_then_branch
) {
9706 append_logical_end(BB_then
);
9707 /* branch from then block to endif block */
9708 aco_ptr
<Pseudo_branch_instruction
> branch
;
9709 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9710 BB_then
->instructions
.emplace_back(std::move(branch
));
9711 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9712 if (!ic
->then_branch_divergent
)
9713 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9714 BB_then
->kind
|= block_kind_uniform
;
9717 ctx
->cf_info
.has_branch
= false;
9718 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9720 /** emit else block */
9721 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9722 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9723 add_edge(ic
->BB_if_idx
, BB_else
);
9724 append_logical_start(BB_else
);
9725 ctx
->block
= BB_else
;
9728 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9730 Block
*BB_else
= ctx
->block
;
9732 if (!ctx
->cf_info
.has_branch
) {
9733 append_logical_end(BB_else
);
9734 /* branch from then block to endif block */
9735 aco_ptr
<Pseudo_branch_instruction
> branch
;
9736 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9737 BB_else
->instructions
.emplace_back(std::move(branch
));
9738 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9739 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9740 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9741 BB_else
->kind
|= block_kind_uniform
;
9744 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9745 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9747 /** emit endif merge block */
9748 if (!ctx
->cf_info
.has_branch
) {
9749 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9750 append_logical_start(ctx
->block
);
9754 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9756 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9757 Builder
bld(ctx
->program
, ctx
->block
);
9758 aco_ptr
<Pseudo_branch_instruction
> branch
;
9761 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9763 * Uniform conditionals are represented in the following way*) :
9765 * The linear and logical CFG:
9768 * BB_THEN (logical) BB_ELSE (logical)
9772 * *) Exceptions may be due to break and continue statements within loops
9773 * If a break/continue happens within uniform control flow, it branches
9774 * to the loop exit/entry block. Otherwise, it branches to the next
9778 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9779 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9780 cond
= bool_to_scalar_condition(ctx
, cond
);
9782 begin_uniform_if_then(ctx
, &ic
, cond
);
9783 visit_cf_list(ctx
, &if_stmt
->then_list
);
9785 begin_uniform_if_else(ctx
, &ic
);
9786 visit_cf_list(ctx
, &if_stmt
->else_list
);
9788 end_uniform_if(ctx
, &ic
);
9789 } else { /* non-uniform condition */
9791 * To maintain a logical and linear CFG without critical edges,
9792 * non-uniform conditionals are represented in the following way*) :
9797 * BB_THEN (logical) BB_THEN (linear)
9799 * BB_INVERT (linear)
9801 * BB_ELSE (logical) BB_ELSE (linear)
9808 * BB_THEN (logical) BB_ELSE (logical)
9812 * *) Exceptions may be due to break and continue statements within loops
9815 begin_divergent_if_then(ctx
, &ic
, cond
);
9816 visit_cf_list(ctx
, &if_stmt
->then_list
);
9818 begin_divergent_if_else(ctx
, &ic
);
9819 visit_cf_list(ctx
, &if_stmt
->else_list
);
9821 end_divergent_if(ctx
, &ic
);
9824 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9827 static bool visit_cf_list(isel_context
*ctx
,
9828 struct exec_list
*list
)
9830 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9831 switch (node
->type
) {
9832 case nir_cf_node_block
:
9833 visit_block(ctx
, nir_cf_node_as_block(node
));
9835 case nir_cf_node_if
:
9836 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9839 case nir_cf_node_loop
:
9840 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9843 unreachable("unimplemented cf list type");
9849 static void create_null_export(isel_context
*ctx
)
9851 /* Some shader stages always need to have exports.
9852 * So when there is none, we need to add a null export.
9855 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9856 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9857 Builder
bld(ctx
->program
, ctx
->block
);
9858 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9859 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9862 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9864 assert(ctx
->stage
== vertex_vs
||
9865 ctx
->stage
== tess_eval_vs
||
9866 ctx
->stage
== gs_copy_vs
||
9867 ctx
->stage
== ngg_vertex_gs
||
9868 ctx
->stage
== ngg_tess_eval_gs
);
9870 int offset
= (ctx
->stage
& sw_tes
)
9871 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9872 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9873 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9874 if (!is_pos
&& !mask
)
9876 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9878 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9879 exp
->enabled_mask
= mask
;
9880 for (unsigned i
= 0; i
< 4; ++i
) {
9881 if (mask
& (1 << i
))
9882 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9884 exp
->operands
[i
] = Operand(v1
);
9886 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9887 * Setting valid_mask=1 prevents it and has no other effect.
9889 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9891 exp
->compressed
= false;
9893 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9895 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9896 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9901 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9903 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9904 exp
->enabled_mask
= 0;
9905 for (unsigned i
= 0; i
< 4; ++i
)
9906 exp
->operands
[i
] = Operand(v1
);
9907 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9908 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9909 exp
->enabled_mask
|= 0x1;
9911 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9912 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9913 exp
->enabled_mask
|= 0x4;
9915 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9916 if (ctx
->options
->chip_class
< GFX9
) {
9917 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9918 exp
->enabled_mask
|= 0x8;
9920 Builder
bld(ctx
->program
, ctx
->block
);
9922 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9923 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9924 if (exp
->operands
[2].isTemp())
9925 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9927 exp
->operands
[2] = Operand(out
);
9928 exp
->enabled_mask
|= 0x4;
9931 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9933 exp
->compressed
= false;
9934 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9935 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9938 static void create_export_phis(isel_context
*ctx
)
9940 /* Used when exports are needed, but the output temps are defined in a preceding block.
9941 * This function will set up phis in order to access the outputs in the next block.
9944 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9945 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9946 ctx
->block
->instructions
.pop_back();
9948 Builder
bld(ctx
->program
, ctx
->block
);
9950 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9951 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9952 for (unsigned i
= 0; i
< 4; ++i
) {
9953 if (!(mask
& (1 << i
)))
9956 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9957 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9958 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9962 bld
.insert(std::move(logical_start
));
9965 static void create_vs_exports(isel_context
*ctx
)
9967 assert(ctx
->stage
== vertex_vs
||
9968 ctx
->stage
== tess_eval_vs
||
9969 ctx
->stage
== gs_copy_vs
||
9970 ctx
->stage
== ngg_vertex_gs
||
9971 ctx
->stage
== ngg_tess_eval_gs
);
9973 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9974 ? &ctx
->program
->info
->tes
.outinfo
9975 : &ctx
->program
->info
->vs
.outinfo
;
9977 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9978 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9979 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9982 if (ctx
->options
->key
.has_multiview_view_index
) {
9983 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9984 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9987 /* the order these position exports are created is important */
9989 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9990 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9991 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9992 exported_pos
= true;
9994 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9995 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9996 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9997 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9999 if (ctx
->export_clip_dists
) {
10000 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10001 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
10002 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10003 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
10006 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10007 if (i
< VARYING_SLOT_VAR0
&&
10008 i
!= VARYING_SLOT_LAYER
&&
10009 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
10010 i
!= VARYING_SLOT_VIEWPORT
)
10013 export_vs_varying(ctx
, i
, false, NULL
);
10017 create_null_export(ctx
);
10020 static bool export_fs_mrt_z(isel_context
*ctx
)
10022 Builder
bld(ctx
->program
, ctx
->block
);
10023 unsigned enabled_channels
= 0;
10024 bool compr
= false;
10027 for (unsigned i
= 0; i
< 4; ++i
) {
10028 values
[i
] = Operand(v1
);
10031 /* Both stencil and sample mask only need 16-bits. */
10032 if (!ctx
->program
->info
->ps
.writes_z
&&
10033 (ctx
->program
->info
->ps
.writes_stencil
||
10034 ctx
->program
->info
->ps
.writes_sample_mask
)) {
10035 compr
= true; /* COMPR flag */
10037 if (ctx
->program
->info
->ps
.writes_stencil
) {
10038 /* Stencil should be in X[23:16]. */
10039 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10040 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
10041 enabled_channels
|= 0x3;
10044 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10045 /* SampleMask should be in Y[15:0]. */
10046 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10047 enabled_channels
|= 0xc;
10050 if (ctx
->program
->info
->ps
.writes_z
) {
10051 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
10052 enabled_channels
|= 0x1;
10055 if (ctx
->program
->info
->ps
.writes_stencil
) {
10056 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10057 enabled_channels
|= 0x2;
10060 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10061 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10062 enabled_channels
|= 0x4;
10066 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10067 * writemask component.
10069 if (ctx
->options
->chip_class
== GFX6
&&
10070 ctx
->options
->family
!= CHIP_OLAND
&&
10071 ctx
->options
->family
!= CHIP_HAINAN
) {
10072 enabled_channels
|= 0x1;
10075 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10076 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10081 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10083 Builder
bld(ctx
->program
, ctx
->block
);
10084 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10087 for (unsigned i
= 0; i
< 4; ++i
) {
10088 if (write_mask
& (1 << i
)) {
10089 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10091 values
[i
] = Operand(v1
);
10095 unsigned target
, col_format
;
10096 unsigned enabled_channels
= 0;
10097 aco_opcode compr_op
= (aco_opcode
)0;
10099 slot
-= FRAG_RESULT_DATA0
;
10100 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10101 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10103 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10104 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10105 bool is_16bit
= values
[0].regClass() == v2b
;
10107 switch (col_format
)
10109 case V_028714_SPI_SHADER_ZERO
:
10110 enabled_channels
= 0; /* writemask */
10111 target
= V_008DFC_SQ_EXP_NULL
;
10114 case V_028714_SPI_SHADER_32_R
:
10115 enabled_channels
= 1;
10118 case V_028714_SPI_SHADER_32_GR
:
10119 enabled_channels
= 0x3;
10122 case V_028714_SPI_SHADER_32_AR
:
10123 if (ctx
->options
->chip_class
>= GFX10
) {
10124 /* Special case: on GFX10, the outputs are different for 32_AR */
10125 enabled_channels
= 0x3;
10126 values
[1] = values
[3];
10127 values
[3] = Operand(v1
);
10129 enabled_channels
= 0x9;
10133 case V_028714_SPI_SHADER_FP16_ABGR
:
10134 enabled_channels
= 0x5;
10135 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10137 if (ctx
->options
->chip_class
>= GFX9
) {
10138 /* Pack the FP16 values together instead of converting them to
10139 * FP32 and back to FP16.
10140 * TODO: use p_create_vector and let the compiler optimizes.
10142 compr_op
= aco_opcode::v_pack_b32_f16
;
10144 for (unsigned i
= 0; i
< 4; i
++) {
10145 if ((write_mask
>> i
) & 1)
10146 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10152 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10153 enabled_channels
= 0x5;
10154 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10155 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10157 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10161 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10162 enabled_channels
= 0x5;
10163 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10164 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10166 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10170 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10171 enabled_channels
= 0x5;
10172 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10173 if (is_int8
|| is_int10
) {
10175 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10176 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10178 for (unsigned i
= 0; i
< 4; i
++) {
10179 if ((write_mask
>> i
) & 1) {
10180 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10181 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10185 } else if (is_16bit
) {
10186 for (unsigned i
= 0; i
< 4; i
++) {
10187 if ((write_mask
>> i
) & 1) {
10188 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10189 values
[i
] = Operand(tmp
);
10196 case V_028714_SPI_SHADER_SINT16_ABGR
:
10197 enabled_channels
= 0x5;
10198 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10199 if (is_int8
|| is_int10
) {
10201 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10202 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10203 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10204 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10206 for (unsigned i
= 0; i
< 4; i
++) {
10207 if ((write_mask
>> i
) & 1) {
10208 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10209 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10211 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10212 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10216 } else if (is_16bit
) {
10217 for (unsigned i
= 0; i
< 4; i
++) {
10218 if ((write_mask
>> i
) & 1) {
10219 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10220 values
[i
] = Operand(tmp
);
10226 case V_028714_SPI_SHADER_32_ABGR
:
10227 enabled_channels
= 0xF;
10234 if (target
== V_008DFC_SQ_EXP_NULL
)
10237 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10238 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10240 (col_format
== V_028714_SPI_SHADER_32_R
||
10241 col_format
== V_028714_SPI_SHADER_32_GR
||
10242 col_format
== V_028714_SPI_SHADER_32_AR
||
10243 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10244 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10245 for (int i
= 0; i
< 4; i
++) {
10246 if (!(write_mask
& (1 << i
)))
10249 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10250 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10251 bld
.copy(bld
.def(v1
), Operand(3u)));
10252 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10253 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10257 if ((bool) compr_op
) {
10258 for (int i
= 0; i
< 2; i
++) {
10259 /* check if at least one of the values to be compressed is enabled */
10260 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10262 enabled_channels
|= enabled
<< (i
*2);
10263 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10264 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10265 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10267 values
[i
] = Operand(v1
);
10270 values
[2] = Operand(v1
);
10271 values
[3] = Operand(v1
);
10273 for (int i
= 0; i
< 4; i
++)
10274 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10277 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10278 enabled_channels
, target
, (bool) compr_op
);
10282 static void create_fs_exports(isel_context
*ctx
)
10284 bool exported
= false;
10286 /* Export depth, stencil and sample mask. */
10287 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10288 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10289 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10290 exported
|= export_fs_mrt_z(ctx
);
10292 /* Export all color render targets. */
10293 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10294 if (ctx
->outputs
.mask
[i
])
10295 exported
|= export_fs_mrt_color(ctx
, i
);
10298 create_null_export(ctx
);
10301 static void create_workgroup_barrier(Builder
& bld
)
10303 bld
.barrier(aco_opcode::p_barrier
,
10304 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10308 static void write_tcs_tess_factors(isel_context
*ctx
)
10310 unsigned outer_comps
;
10311 unsigned inner_comps
;
10313 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10330 Builder
bld(ctx
->program
, ctx
->block
);
10332 create_workgroup_barrier(bld
);
10334 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10335 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10337 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10338 if_context ic_invocation_id_is_zero
;
10339 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10340 bld
.reset(ctx
->block
);
10342 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10344 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10345 unsigned stride
= inner_comps
+ outer_comps
;
10346 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10350 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10352 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10354 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10355 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10356 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10358 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10359 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10361 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10362 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10363 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10364 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10367 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10368 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10369 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10370 unsigned tf_const_offset
= 0;
10372 if (ctx
->program
->chip_class
<= GFX8
) {
10373 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10374 if_context ic_rel_patch_id_is_zero
;
10375 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10376 bld
.reset(ctx
->block
);
10378 /* Store the dynamic HS control word. */
10379 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10380 bld
.mubuf(aco_opcode::buffer_store_dword
,
10381 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10382 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10383 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10384 tf_const_offset
+= 4;
10386 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10387 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10388 bld
.reset(ctx
->block
);
10391 assert(stride
== 2 || stride
== 4 || stride
== 6);
10392 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10393 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10395 /* Store to offchip for TES to read - only if TES reads them */
10396 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10397 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10398 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10400 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10401 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10403 if (likely(inner_comps
)) {
10404 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10405 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10409 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10410 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10413 static void emit_stream_output(isel_context
*ctx
,
10414 Temp
const *so_buffers
,
10415 Temp
const *so_write_offset
,
10416 const struct radv_stream_output
*output
)
10418 unsigned num_comps
= util_bitcount(output
->component_mask
);
10419 unsigned writemask
= (1 << num_comps
) - 1;
10420 unsigned loc
= output
->location
;
10421 unsigned buf
= output
->buffer
;
10423 assert(num_comps
&& num_comps
<= 4);
10424 if (!num_comps
|| num_comps
> 4)
10427 unsigned start
= ffs(output
->component_mask
) - 1;
10430 bool all_undef
= true;
10431 assert(ctx
->stage
& hw_vs
);
10432 for (unsigned i
= 0; i
< num_comps
; i
++) {
10433 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10434 all_undef
= all_undef
&& !out
[i
].id();
10439 while (writemask
) {
10441 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10442 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10443 /* GFX6 doesn't support storing vec3, split it. */
10444 writemask
|= 1u << (start
+ 2);
10448 unsigned offset
= output
->offset
+ start
* 4;
10450 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10451 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10452 for (int i
= 0; i
< count
; ++i
)
10453 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10454 vec
->definitions
[0] = Definition(write_data
);
10455 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10460 opcode
= aco_opcode::buffer_store_dword
;
10463 opcode
= aco_opcode::buffer_store_dwordx2
;
10466 opcode
= aco_opcode::buffer_store_dwordx3
;
10469 opcode
= aco_opcode::buffer_store_dwordx4
;
10472 unreachable("Unsupported dword count.");
10475 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10476 store
->operands
[0] = Operand(so_buffers
[buf
]);
10477 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10478 store
->operands
[2] = Operand((uint32_t) 0);
10479 store
->operands
[3] = Operand(write_data
);
10480 if (offset
> 4095) {
10481 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10482 Builder
bld(ctx
->program
, ctx
->block
);
10483 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10485 store
->offset
= offset
;
10487 store
->offen
= true;
10489 store
->dlc
= false;
10491 ctx
->block
->instructions
.emplace_back(std::move(store
));
10495 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10497 Builder
bld(ctx
->program
, ctx
->block
);
10499 Temp so_buffers
[4];
10500 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10501 for (unsigned i
= 0; i
< 4; i
++) {
10502 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10506 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10507 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10510 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10511 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10513 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10515 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10518 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10520 bld
.reset(ctx
->block
);
10522 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10524 Temp so_write_offset
[4];
10526 for (unsigned i
= 0; i
< 4; i
++) {
10527 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10532 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10533 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10534 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10535 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10537 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10539 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10540 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10541 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10542 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10546 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10547 struct radv_stream_output
*output
=
10548 &ctx
->program
->info
->so
.outputs
[i
];
10549 if (stream
!= output
->stream
)
10552 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10555 begin_divergent_if_else(ctx
, &ic
);
10556 end_divergent_if(ctx
, &ic
);
10559 } /* end namespace */
10561 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10563 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10564 Builder
bld(ctx
->program
, ctx
->block
);
10565 constexpr unsigned hs_idx
= 1u;
10566 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10567 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10568 Operand((8u << 16) | (hs_idx
* 8u)));
10569 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10571 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10573 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10574 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10575 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10576 ls_has_nonzero_hs_threads
);
10577 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10578 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10579 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10580 ls_has_nonzero_hs_threads
);
10581 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10582 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10583 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10584 ls_has_nonzero_hs_threads
);
10586 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10587 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10588 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10591 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10593 /* Split all arguments except for the first (ring_offsets) and the last
10594 * (exec) so that the dead channels don't stay live throughout the program.
10596 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10597 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10598 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10599 startpgm
->definitions
[i
].regClass().size());
10604 void handle_bc_optimize(isel_context
*ctx
)
10606 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10607 Builder
bld(ctx
->program
, ctx
->block
);
10608 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10609 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10610 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10611 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10612 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10613 if (uses_center
&& uses_centroid
) {
10614 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10615 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10617 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10619 for (unsigned i
= 0; i
< 2; i
++) {
10620 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10621 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10622 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10623 persp_centroid
, persp_center
, sel
);
10625 ctx
->persp_centroid
= bld
.tmp(v2
);
10626 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10627 Operand(new_coord
[0]), Operand(new_coord
[1]));
10628 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10631 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10633 for (unsigned i
= 0; i
< 2; i
++) {
10634 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10635 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10636 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10637 linear_centroid
, linear_center
, sel
);
10639 ctx
->linear_centroid
= bld
.tmp(v2
);
10640 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10641 Operand(new_coord
[0]), Operand(new_coord
[1]));
10642 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10647 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10649 Program
*program
= ctx
->program
;
10651 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10653 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10654 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10655 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10656 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10657 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10659 program
->next_fp_mode
.must_flush_denorms32
=
10660 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10661 program
->next_fp_mode
.must_flush_denorms16_64
=
10662 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10663 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10665 program
->next_fp_mode
.care_about_round32
=
10666 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10668 program
->next_fp_mode
.care_about_round16_64
=
10669 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10670 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10672 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10673 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10674 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10675 program
->next_fp_mode
.denorm16_64
= 0;
10677 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10679 /* preserving fp32 denorms is expensive, so only do it if asked */
10680 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10681 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10683 program
->next_fp_mode
.denorm32
= 0;
10685 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10686 program
->next_fp_mode
.round32
= fp_round_tz
;
10688 program
->next_fp_mode
.round32
= fp_round_ne
;
10690 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10691 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10693 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10695 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10698 void cleanup_cfg(Program
*program
)
10700 /* create linear_succs/logical_succs */
10701 for (Block
& BB
: program
->blocks
) {
10702 for (unsigned idx
: BB
.linear_preds
)
10703 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10704 for (unsigned idx
: BB
.logical_preds
)
10705 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10709 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10711 Builder
bld(ctx
->program
, ctx
->block
);
10713 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10714 Temp count
= i
== 0
10715 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10716 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10717 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10719 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10722 if (ctx
->program
->wave_size
== 64) {
10723 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10724 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10725 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10727 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10728 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10734 bool ngg_early_prim_export(isel_context
*ctx
)
10736 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10740 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10742 Builder
bld(ctx
->program
, ctx
->block
);
10744 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10745 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10747 /* Get the id of the current wave within the threadgroup (workgroup) */
10748 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10749 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10751 /* Execute the following code only on the first wave (wave id 0),
10752 * use the SCC def to tell if the wave id is zero or not.
10754 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10756 begin_uniform_if_then(ctx
, &ic
, cond
);
10757 begin_uniform_if_else(ctx
, &ic
);
10758 bld
.reset(ctx
->block
);
10760 /* Number of vertices output by VS/TES */
10761 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10762 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10763 /* Number of primitives output by VS/TES */
10764 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10765 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10767 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10768 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10769 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10771 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10772 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10774 end_uniform_if(ctx
, &ic
);
10776 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10777 bld
.reset(ctx
->block
);
10778 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10781 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10783 Builder
bld(ctx
->program
, ctx
->block
);
10785 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10786 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10789 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10792 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10793 assert(vtxindex
[i
].id());
10796 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10800 /* The initial edge flag is always false in tess eval shaders. */
10801 if (ctx
->stage
== ngg_vertex_gs
) {
10802 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10803 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10807 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10812 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10814 Builder
bld(ctx
->program
, ctx
->block
);
10815 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10817 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10818 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10819 false /* compressed */, true/* done */, false /* valid mask */);
10822 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10824 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10825 * These must always come before VS exports.
10827 * It is recommended to do these as early as possible. They can be at the beginning when
10828 * there is no SW GS and the shader doesn't write edge flags.
10832 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10833 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10835 Builder
bld(ctx
->program
, ctx
->block
);
10836 constexpr unsigned max_vertices_per_primitive
= 3;
10837 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10839 if (ctx
->stage
== ngg_vertex_gs
) {
10840 /* TODO: optimize for points & lines */
10841 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10842 if (ctx
->shader
->info
.tess
.point_mode
)
10843 num_vertices_per_primitive
= 1;
10844 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10845 num_vertices_per_primitive
= 2;
10847 unreachable("Unsupported NGG shader stage");
10850 Temp vtxindex
[max_vertices_per_primitive
];
10851 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10852 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10853 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10854 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10855 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10856 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10857 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10858 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10860 /* Export primitive data to the index buffer. */
10861 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10863 /* Export primitive ID. */
10864 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10865 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10866 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10867 Temp provoking_vtx_index
= vtxindex
[0];
10868 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10870 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10873 begin_divergent_if_else(ctx
, &ic
);
10874 end_divergent_if(ctx
, &ic
);
10877 void ngg_emit_nogs_output(isel_context
*ctx
)
10879 /* Emits NGG GS output, for stages that don't have SW GS. */
10882 Builder
bld(ctx
->program
, ctx
->block
);
10883 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10885 /* NGG streamout is currently disabled by default. */
10886 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10888 if (late_prim_export
) {
10889 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10890 create_export_phis(ctx
);
10891 /* Do what we need to do in the GS threads. */
10892 ngg_emit_nogs_gsthreads(ctx
);
10894 /* What comes next should be executed on ES threads. */
10895 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10896 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10897 bld
.reset(ctx
->block
);
10900 /* Export VS outputs */
10901 ctx
->block
->kind
|= block_kind_export_end
;
10902 create_vs_exports(ctx
);
10904 /* Export primitive ID */
10905 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10908 if (ctx
->stage
== ngg_vertex_gs
) {
10909 /* Wait for GS threads to store primitive ID in LDS. */
10910 create_workgroup_barrier(bld
);
10912 /* Calculate LDS address where the GS threads stored the primitive ID. */
10913 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10914 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10915 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10916 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10917 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10918 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10920 /* Load primitive ID from LDS. */
10921 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10922 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10923 /* TES: Just use the patch ID as the primitive ID. */
10924 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10926 unreachable("unsupported NGG shader stage.");
10929 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10930 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10932 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10935 if (late_prim_export
) {
10936 begin_divergent_if_else(ctx
, &ic
);
10937 end_divergent_if(ctx
, &ic
);
10938 bld
.reset(ctx
->block
);
10942 void select_program(Program
*program
,
10943 unsigned shader_count
,
10944 struct nir_shader
*const *shaders
,
10945 ac_shader_config
* config
,
10946 struct radv_shader_args
*args
)
10948 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10949 if_context ic_merged_wave_info
;
10950 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10952 for (unsigned i
= 0; i
< shader_count
; i
++) {
10953 nir_shader
*nir
= shaders
[i
];
10954 init_context(&ctx
, nir
);
10956 setup_fp_mode(&ctx
, nir
);
10959 /* needs to be after init_context() for FS */
10960 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10961 append_logical_start(ctx
.block
);
10963 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10964 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10966 split_arguments(&ctx
, startpgm
);
10970 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10972 if (ngg_early_prim_export(&ctx
))
10973 ngg_emit_nogs_gsthreads(&ctx
);
10976 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10977 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10978 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10979 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10980 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10981 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10982 ctx
.stage
== tess_eval_geometry_gs
));
10984 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10985 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10986 if (check_merged_wave_info
) {
10987 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10988 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10992 Builder
bld(ctx
.program
, ctx
.block
);
10994 create_workgroup_barrier(bld
);
10996 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10997 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10999 } else if (ctx
.stage
== geometry_gs
)
11000 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
11002 if (ctx
.stage
== fragment_fs
)
11003 handle_bc_optimize(&ctx
);
11005 visit_cf_list(&ctx
, &func
->body
);
11007 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
11008 emit_streamout(&ctx
, 0);
11010 if (ctx
.stage
& hw_vs
) {
11011 create_vs_exports(&ctx
);
11012 ctx
.block
->kind
|= block_kind_export_end
;
11013 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
11014 ngg_emit_nogs_output(&ctx
);
11015 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
11016 Builder
bld(ctx
.program
, ctx
.block
);
11017 bld
.barrier(aco_opcode::p_barrier
,
11018 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
11019 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
11020 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
11021 write_tcs_tess_factors(&ctx
);
11024 if (ctx
.stage
== fragment_fs
) {
11025 create_fs_exports(&ctx
);
11026 ctx
.block
->kind
|= block_kind_export_end
;
11029 if (endif_merged_wave_info
) {
11030 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
11031 end_divergent_if(&ctx
, &ic_merged_wave_info
);
11034 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
11035 ngg_emit_nogs_output(&ctx
);
11037 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
11038 /* Outputs of the previous stage are inputs to the next stage */
11039 ctx
.inputs
= ctx
.outputs
;
11040 ctx
.outputs
= shader_io_state();
11044 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11046 append_logical_end(ctx
.block
);
11047 ctx
.block
->kind
|= block_kind_uniform
;
11048 Builder
bld(ctx
.program
, ctx
.block
);
11049 if (ctx
.program
->wb_smem_l1_on_end
)
11050 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
11051 bld
.sopp(aco_opcode::s_endpgm
);
11053 cleanup_cfg(program
);
11056 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
11057 ac_shader_config
* config
,
11058 struct radv_shader_args
*args
)
11060 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
11062 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11064 add_startpgm(&ctx
);
11065 append_logical_start(ctx
.block
);
11067 Builder
bld(ctx
.program
, ctx
.block
);
11069 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11071 Operand
stream_id(0u);
11072 if (args
->shader_info
->so
.num_outputs
)
11073 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11074 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11076 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11078 std::stack
<Block
> endif_blocks
;
11080 for (unsigned stream
= 0; stream
< 4; stream
++) {
11081 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11084 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11085 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11088 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11090 unsigned BB_if_idx
= ctx
.block
->index
;
11091 Block BB_endif
= Block();
11092 if (!stream_id
.isConstant()) {
11094 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11095 append_logical_end(ctx
.block
);
11096 ctx
.block
->kind
|= block_kind_uniform
;
11097 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11099 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11101 ctx
.block
= ctx
.program
->create_and_insert_block();
11102 add_edge(BB_if_idx
, ctx
.block
);
11103 bld
.reset(ctx
.block
);
11104 append_logical_start(ctx
.block
);
11107 unsigned offset
= 0;
11108 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11109 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11112 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11113 unsigned length
= util_last_bit(output_usage_mask
);
11114 for (unsigned j
= 0; j
< length
; ++j
) {
11115 if (!(output_usage_mask
& (1 << j
)))
11118 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11119 Temp voffset
= vtx_offset
;
11120 if (const_offset
>= 4096u) {
11121 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11122 const_offset
%= 4096u;
11125 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11126 mubuf
->definitions
[0] = bld
.def(v1
);
11127 mubuf
->operands
[0] = Operand(gsvs_ring
);
11128 mubuf
->operands
[1] = Operand(voffset
);
11129 mubuf
->operands
[2] = Operand(0u);
11130 mubuf
->offen
= true;
11131 mubuf
->offset
= const_offset
;
11134 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11136 ctx
.outputs
.mask
[i
] |= 1 << j
;
11137 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11139 bld
.insert(std::move(mubuf
));
11145 if (args
->shader_info
->so
.num_outputs
) {
11146 emit_streamout(&ctx
, stream
);
11147 bld
.reset(ctx
.block
);
11151 create_vs_exports(&ctx
);
11152 ctx
.block
->kind
|= block_kind_export_end
;
11155 if (!stream_id
.isConstant()) {
11156 append_logical_end(ctx
.block
);
11158 /* branch from then block to endif block */
11159 bld
.branch(aco_opcode::p_branch
);
11160 add_edge(ctx
.block
->index
, &BB_endif
);
11161 ctx
.block
->kind
|= block_kind_uniform
;
11163 /* emit else block */
11164 ctx
.block
= ctx
.program
->create_and_insert_block();
11165 add_edge(BB_if_idx
, ctx
.block
);
11166 bld
.reset(ctx
.block
);
11167 append_logical_start(ctx
.block
);
11169 endif_blocks
.push(std::move(BB_endif
));
11173 while (!endif_blocks
.empty()) {
11174 Block BB_endif
= std::move(endif_blocks
.top());
11175 endif_blocks
.pop();
11177 Block
*BB_else
= ctx
.block
;
11179 append_logical_end(BB_else
);
11180 /* branch from else block to endif block */
11181 bld
.branch(aco_opcode::p_branch
);
11182 add_edge(BB_else
->index
, &BB_endif
);
11183 BB_else
->kind
|= block_kind_uniform
;
11185 /** emit endif merge block */
11186 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11187 bld
.reset(ctx
.block
);
11188 append_logical_start(ctx
.block
);
11191 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11193 append_logical_end(ctx
.block
);
11194 ctx
.block
->kind
|= block_kind_uniform
;
11195 bld
.sopp(aco_opcode::s_endpgm
);
11197 cleanup_cfg(program
);