src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <map>
  29
  30 #include "ac_shader_util.h"
  31 #include "aco_ir.h"
  32 #include "aco_builder.h"
  33 #include "aco_interface.h"
  34 #include "aco_instruction_selection_setup.cpp"
  35 #include "util/fast_idiv_by_const.h"
  36
  37 namespace aco {
  38 namespace {
  39
  40 class loop_info_RAII {
  41    isel_context* ctx;
  42    unsigned header_idx_old;
  43    Block* exit_old;
  44    bool divergent_cont_old;
  45    bool divergent_branch_old;
  46    bool divergent_if_old;
  47
  48 public:
  49    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  50       : ctx(ctx),
  51         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  52         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  53         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  54         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  55    {
  56       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  57       ctx->cf_info.parent_loop.exit = loop_exit;
  58       ctx->cf_info.parent_loop.has_divergent_continue = false;
  59       ctx->cf_info.parent_loop.has_divergent_branch = false;
  60       ctx->cf_info.parent_if.is_divergent = false;
  61       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  62    }
  63
  64    ~loop_info_RAII()
  65    {
  66       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  67       ctx->cf_info.parent_loop.exit = exit_old;
  68       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  69       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  70       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  71       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  72       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  73          ctx->cf_info.exec_potentially_empty = false;
  74    }
  75 };
  76
  77 struct if_context {
  78    Temp cond;
  79
  80    bool divergent_old;
  81    bool exec_potentially_empty_old;
  82
  83    unsigned BB_if_idx;
  84    unsigned invert_idx;
  85    bool then_branch_divergent;
  86    Block BB_invert;
  87    Block BB_endif;
  88 };
  89
  90 static void visit_cf_list(struct isel_context *ctx,
  91                           struct exec_list *list);
  92
  93 static void add_logical_edge(unsigned pred_idx, Block *succ)
  94 {
  95    succ->logical_preds.emplace_back(pred_idx);
  96 }
  97
  98
  99 static void add_linear_edge(unsigned pred_idx, Block *succ)
 100 {
 101    succ->linear_preds.emplace_back(pred_idx);
 102 }
 103
 104 static void add_edge(unsigned pred_idx, Block *succ)
 105 {
 106    add_logical_edge(pred_idx, succ);
 107    add_linear_edge(pred_idx, succ);
 108 }
 109
 110 static void append_logical_start(Block *b)
 111 {
 112    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 113 }
 114
 115 static void append_logical_end(Block *b)
 116 {
 117    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 118 }
 119
 120 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 121 {
 122    assert(ctx->allocated[def->index].id());
 123    return ctx->allocated[def->index];
 124 }
 125
 126 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 127                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 128 {
 129    Builder bld(ctx->program, ctx->block);
 130    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 131    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 132
 133    if (ctx->program->wave_size == 32) {
 134       return thread_id_lo;
 135    } else {
 136       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 137       return thread_id_hi;
 138    }
 139 }
 140
 141 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 142 {
 143    Builder bld(ctx->program, ctx->block);
 144
 145    if (!dst.id())
 146       dst = bld.tmp(src.regClass());
 147
 148    assert(src.size() == dst.size());
 149
 150    if (ctx->stage != fragment_fs) {
 151       if (!dst.id())
 152          return src;
 153
 154       bld.copy(Definition(dst), src);
 155       return dst;
 156    }
 157
 158    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 159    ctx->program->needs_wqm |= program_needs_wqm;
 160    return dst;
 161 }
 162
 163 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 164 {
 165    if (index.regClass() == s1)
 166       return bld.readlane(bld.def(s1), data, index);
 167
 168    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 169
 170    /* Currently not implemented on GFX6-7 */
 171    assert(ctx->options->chip_class >= GFX8);
 172
 173    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 174       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 175    }
 176
 177    /* GFX10, wave64 mode:
 178     * The bpermute instruction is limited to half-wave operation, which means that it can't
 179     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 180     * emulate it here.
 181     */
 182    if (!ctx->has_gfx10_wave64_bpermute) {
 183       ctx->has_gfx10_wave64_bpermute = true;
 184       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 185       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 186    }
 187
 188    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 189    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 190    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 191    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 192
 193    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 194                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 195 }
 196
 197 Temp as_vgpr(isel_context *ctx, Temp val)
 198 {
 199    if (val.type() == RegType::sgpr) {
 200       Builder bld(ctx->program, ctx->block);
 201       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 202    }
 203    assert(val.type() == RegType::vgpr);
 204    return val;
 205 }
 206
 207 //assumes a != 0xffffffff
 208 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 209 {
 210    assert(b != 0);
 211    Builder bld(ctx->program, ctx->block);
 212
 213    if (util_is_power_of_two_or_zero(b)) {
 214       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 215       return;
 216    }
 217
 218    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 219
 220    assert(info.multiplier <= 0xffffffff);
 221
 222    bool pre_shift = info.pre_shift != 0;
 223    bool increment = info.increment != 0;
 224    bool multiply = true;
 225    bool post_shift = info.post_shift != 0;
 226
 227    if (!pre_shift && !increment && !multiply && !post_shift) {
 228       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 229       return;
 230    }
 231
 232    Temp pre_shift_dst = a;
 233    if (pre_shift) {
 234       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 235       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 236    }
 237
 238    Temp increment_dst = pre_shift_dst;
 239    if (increment) {
 240       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 241       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 242    }
 243
 244    Temp multiply_dst = increment_dst;
 245    if (multiply) {
 246       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 247       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 248                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 249    }
 250
 251    if (post_shift) {
 252       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 253    }
 254 }
 255
 256 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 257 {
 258    Builder bld(ctx->program, ctx->block);
 259    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 260 }
 261
 262
 263 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 264 {
 265    /* no need to extract the whole vector */
 266    if (src.regClass() == dst_rc) {
 267       assert(idx == 0);
 268       return src;
 269    }
 270    assert(src.size() > idx);
 271    Builder bld(ctx->program, ctx->block);
 272    auto it = ctx->allocated_vec.find(src.id());
 273    /* the size check needs to be early because elements other than 0 may be garbage */
 274    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 275       if (it->second[idx].regClass() == dst_rc) {
 276          return it->second[idx];
 277       } else {
 278          assert(dst_rc.size() == it->second[idx].regClass().size());
 279          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 280          return bld.copy(bld.def(dst_rc), it->second[idx]);
 281       }
 282    }
 283
 284    if (src.size() == dst_rc.size()) {
 285       assert(idx == 0);
 286       return bld.copy(bld.def(dst_rc), src);
 287    } else {
 288       Temp dst = bld.tmp(dst_rc);
 289       emit_extract_vector(ctx, src, idx, dst);
 290       return dst;
 291    }
 292 }
 293
 294 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 295 {
 296    if (num_components == 1)
 297       return;
 298    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 299       return;
 300    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 301    split->operands[0] = Operand(vec_src);
 302    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 303    for (unsigned i = 0; i < num_components; i++) {
 304       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 305       split->definitions[i] = Definition(elems[i]);
 306    }
 307    ctx->block->instructions.emplace_back(std::move(split));
 308    ctx->allocated_vec.emplace(vec_src.id(), elems);
 309 }
 310
 311 /* This vector expansion uses a mask to determine which elements in the new vector
 312  * come from the original vector. The other elements are undefined. */
 313 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 314 {
 315    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 316
 317    if (vec_src == dst)
 318       return;
 319
 320    Builder bld(ctx->program, ctx->block);
 321    if (num_components == 1) {
 322       if (dst.type() == RegType::sgpr)
 323          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 324       else
 325          bld.copy(Definition(dst), vec_src);
 326       return;
 327    }
 328
 329    unsigned component_size = dst.size() / num_components;
 330    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 331
 332    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 333    vec->definitions[0] = Definition(dst);
 334    unsigned k = 0;
 335    for (unsigned i = 0; i < num_components; i++) {
 336       if (mask & (1 << i)) {
 337          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 338          if (dst.type() == RegType::sgpr)
 339             src = bld.as_uniform(src);
 340          vec->operands[i] = Operand(src);
 341       } else {
 342          vec->operands[i] = Operand(0u);
 343       }
 344       elems[i] = vec->operands[i].getTemp();
 345    }
 346    ctx->block->instructions.emplace_back(std::move(vec));
 347    ctx->allocated_vec.emplace(dst.id(), elems);
 348 }
 349
 350 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 351 {
 352    Builder bld(ctx->program, ctx->block);
 353    if (!dst.id())
 354       dst = bld.tmp(bld.lm);
 355
 356    assert(val.regClass() == s1);
 357    assert(dst.regClass() == bld.lm);
 358
 359    return bld.sop2(Builder::s_cselect, bld.hint_vcc(Definition(dst)), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 360 }
 361
 362 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 363 {
 364    Builder bld(ctx->program, ctx->block);
 365    if (!dst.id())
 366       dst = bld.tmp(s1);
 367
 368    assert(val.regClass() == bld.lm);
 369    assert(dst.regClass() == s1);
 370
 371    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 372    Temp tmp = bld.tmp(s1);
 373    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 374    return emit_wqm(ctx, tmp, dst);
 375 }
 376
 377 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 378 {
 379    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 380       return get_ssa_temp(ctx, src.src.ssa);
 381
 382    if (src.src.ssa->num_components == size) {
 383       bool identity_swizzle = true;
 384       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 385          if (src.swizzle[i] != i)
 386             identity_swizzle = false;
 387       }
 388       if (identity_swizzle)
 389          return get_ssa_temp(ctx, src.src.ssa);
 390    }
 391
 392    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 393    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 394    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 395    assert(vec.size() % elem_size == 0);
 396
 397    RegClass elem_rc = RegClass(vec.type(), elem_size);
 398    if (size == 1) {
 399       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 400    } else {
 401       assert(size <= 4);
 402       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 403       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 404       for (unsigned i = 0; i < size; ++i) {
 405          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 406          vec_instr->operands[i] = Operand{elems[i]};
 407       }
 408       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 409       vec_instr->definitions[0] = Definition(dst);
 410       ctx->block->instructions.emplace_back(std::move(vec_instr));
 411       ctx->allocated_vec.emplace(dst.id(), elems);
 412       return dst;
 413    }
 414 }
 415
 416 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 417 {
 418    if (ptr.size() == 2)
 419       return ptr;
 420    Builder bld(ctx->program, ctx->block);
 421    if (ptr.type() == RegType::vgpr)
 422       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 423    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 424                      ptr, Operand((unsigned)ctx->options->address32_hi));
 425 }
 426
 427 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 428 {
 429    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 430    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 431    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 432    sop2->definitions[0] = Definition(dst);
 433    if (writes_scc)
 434       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 435    ctx->block->instructions.emplace_back(std::move(sop2));
 436 }
 437
 438 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 439                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 440 {
 441    Builder bld(ctx->program, ctx->block);
 442    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 443    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 444    if (src1.type() == RegType::sgpr) {
 445       if (commutative && src0.type() == RegType::vgpr) {
 446          Temp t = src0;
 447          src0 = src1;
 448          src1 = t;
 449       } else if (src0.type() == RegType::vgpr &&
 450                  op != aco_opcode::v_madmk_f32 &&
 451                  op != aco_opcode::v_madak_f32 &&
 452                  op != aco_opcode::v_madmk_f16 &&
 453                  op != aco_opcode::v_madak_f16) {
 454          /* If the instruction is not commutative, we emit a VOP3A instruction */
 455          bld.vop2_e64(op, Definition(dst), src0, src1);
 456          return;
 457       } else {
 458          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 459       }
 460    }
 461
 462    if (flush_denorms && ctx->program->chip_class < GFX9) {
 463       assert(dst.size() == 1);
 464       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 465       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 466    } else {
 467       bld.vop2(op, Definition(dst), src0, src1);
 468    }
 469 }
 470
 471 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 472                             bool flush_denorms = false)
 473 {
 474    Temp src0 = get_alu_src(ctx, instr->src[0]);
 475    Temp src1 = get_alu_src(ctx, instr->src[1]);
 476    Temp src2 = get_alu_src(ctx, instr->src[2]);
 477
 478    /* ensure that the instruction has at most 1 sgpr operand
 479     * The optimizer will inline constants for us */
 480    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 481       src0 = as_vgpr(ctx, src0);
 482    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 483       src1 = as_vgpr(ctx, src1);
 484    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 485       src2 = as_vgpr(ctx, src2);
 486
 487    Builder bld(ctx->program, ctx->block);
 488    if (flush_denorms && ctx->program->chip_class < GFX9) {
 489       assert(dst.size() == 1);
 490       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 491       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 492    } else {
 493       bld.vop3(op, Definition(dst), src0, src1, src2);
 494    }
 495 }
 496
 497 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 498 {
 499    Builder bld(ctx->program, ctx->block);
 500    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 501 }
 502
 503 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 504 {
 505    Temp src0 = get_alu_src(ctx, instr->src[0]);
 506    Temp src1 = get_alu_src(ctx, instr->src[1]);
 507    assert(src0.size() == src1.size());
 508
 509    aco_ptr<Instruction> vopc;
 510    if (src1.type() == RegType::sgpr) {
 511       if (src0.type() == RegType::vgpr) {
 512          /* to swap the operands, we might also have to change the opcode */
 513          switch (op) {
 514             case aco_opcode::v_cmp_lt_f32:
 515                op = aco_opcode::v_cmp_gt_f32;
 516                break;
 517             case aco_opcode::v_cmp_ge_f32:
 518                op = aco_opcode::v_cmp_le_f32;
 519                break;
 520             case aco_opcode::v_cmp_lt_i32:
 521                op = aco_opcode::v_cmp_gt_i32;
 522                break;
 523             case aco_opcode::v_cmp_ge_i32:
 524                op = aco_opcode::v_cmp_le_i32;
 525                break;
 526             case aco_opcode::v_cmp_lt_u32:
 527                op = aco_opcode::v_cmp_gt_u32;
 528                break;
 529             case aco_opcode::v_cmp_ge_u32:
 530                op = aco_opcode::v_cmp_le_u32;
 531                break;
 532             case aco_opcode::v_cmp_lt_f64:
 533                op = aco_opcode::v_cmp_gt_f64;
 534                break;
 535             case aco_opcode::v_cmp_ge_f64:
 536                op = aco_opcode::v_cmp_le_f64;
 537                break;
 538             case aco_opcode::v_cmp_lt_i64:
 539                op = aco_opcode::v_cmp_gt_i64;
 540                break;
 541             case aco_opcode::v_cmp_ge_i64:
 542                op = aco_opcode::v_cmp_le_i64;
 543                break;
 544             case aco_opcode::v_cmp_lt_u64:
 545                op = aco_opcode::v_cmp_gt_u64;
 546                break;
 547             case aco_opcode::v_cmp_ge_u64:
 548                op = aco_opcode::v_cmp_le_u64;
 549                break;
 550             default: /* eq and ne are commutative */
 551                break;
 552          }
 553          Temp t = src0;
 554          src0 = src1;
 555          src1 = t;
 556       } else {
 557          src1 = as_vgpr(ctx, src1);
 558       }
 559    }
 560
 561    Builder bld(ctx->program, ctx->block);
 562    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 563 }
 564
 565 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 566 {
 567    Temp src0 = get_alu_src(ctx, instr->src[0]);
 568    Temp src1 = get_alu_src(ctx, instr->src[1]);
 569    Builder bld(ctx->program, ctx->block);
 570
 571    assert(dst.regClass() == bld.lm);
 572    assert(src0.type() == RegType::sgpr);
 573    assert(src1.type() == RegType::sgpr);
 574    assert(src0.regClass() == src1.regClass());
 575
 576    /* Emit the SALU comparison instruction */
 577    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 578    /* Turn the result into a per-lane bool */
 579    bool_to_vector_condition(ctx, cmp, dst);
 580 }
 581
 582 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 583                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 584 {
 585    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 586    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 587    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 588    bool use_valu = s_op == aco_opcode::num_opcodes ||
 589                    divergent_vals ||
 590                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 591                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 592    aco_opcode op = use_valu ? v_op : s_op;
 593    assert(op != aco_opcode::num_opcodes);
 594    assert(dst.regClass() == ctx->program->lane_mask);
 595
 596    if (use_valu)
 597       emit_vopc_instruction(ctx, instr, op, dst);
 598    else
 599       emit_sopc_instruction(ctx, instr, op, dst);
 600 }
 601
 602 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 603 {
 604    Builder bld(ctx->program, ctx->block);
 605    Temp src0 = get_alu_src(ctx, instr->src[0]);
 606    Temp src1 = get_alu_src(ctx, instr->src[1]);
 607
 608    assert(dst.regClass() == bld.lm);
 609    assert(src0.regClass() == bld.lm);
 610    assert(src1.regClass() == bld.lm);
 611
 612    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 613 }
 614
 615 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 616 {
 617    Builder bld(ctx->program, ctx->block);
 618    Temp cond = get_alu_src(ctx, instr->src[0]);
 619    Temp then = get_alu_src(ctx, instr->src[1]);
 620    Temp els = get_alu_src(ctx, instr->src[2]);
 621
 622    assert(cond.regClass() == bld.lm);
 623
 624    if (dst.type() == RegType::vgpr) {
 625       aco_ptr<Instruction> bcsel;
 626       if (dst.size() == 1) {
 627          then = as_vgpr(ctx, then);
 628          els = as_vgpr(ctx, els);
 629
 630          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 631       } else if (dst.size() == 2) {
 632          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 633          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 634          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 635          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 636
 637          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 638          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 639
 640          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 641       } else {
 642          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 643          nir_print_instr(&instr->instr, stderr);
 644          fprintf(stderr, "\n");
 645       }
 646       return;
 647    }
 648
 649    if (instr->dest.dest.ssa.bit_size == 1) {
 650       assert(dst.regClass() == bld.lm);
 651       assert(then.regClass() == bld.lm);
 652       assert(els.regClass() == bld.lm);
 653    }
 654
 655    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 656       if (dst.regClass() == s1 || dst.regClass() == s2) {
 657          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 658          assert(dst.size() == then.size());
 659          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 660          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 661       } else {
 662          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 663          nir_print_instr(&instr->instr, stderr);
 664          fprintf(stderr, "\n");
 665       }
 666       return;
 667    }
 668
 669    /* divergent boolean bcsel
 670     * this implements bcsel on bools: dst = s0 ? s1 : s2
 671     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 672    assert(instr->dest.dest.ssa.bit_size == 1);
 673
 674    if (cond.id() != then.id())
 675       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 676
 677    if (cond.id() == els.id())
 678       bld.sop1(Builder::s_mov, Definition(dst), then);
 679    else
 680       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 681                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 682 }
 683
 684 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 685                     aco_opcode op, uint32_t undo)
 686 {
 687    /* multiply by 16777216 to handle denormals */
 688    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 689                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 690    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 691    scaled = bld.vop1(op, bld.def(v1), scaled);
 692    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 693
 694    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 695
 696    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 697 }
 698
 699 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 700 {
 701    if (ctx->block->fp_mode.denorm32 == 0) {
 702       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 703       return;
 704    }
 705
 706    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 707 }
 708
 709 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 710 {
 711    if (ctx->block->fp_mode.denorm32 == 0) {
 712       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 713       return;
 714    }
 715
 716    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 717 }
 718
 719 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 720 {
 721    if (ctx->block->fp_mode.denorm32 == 0) {
 722       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 723       return;
 724    }
 725
 726    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 727 }
 728
 729 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 730 {
 731    if (ctx->block->fp_mode.denorm32 == 0) {
 732       bld.vop1(aco_opcode::v_log_f32, dst, val);
 733       return;
 734    }
 735
 736    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 737 }
 738
 739 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 740 {
 741    if (!instr->dest.dest.is_ssa) {
 742       fprintf(stderr, "nir alu dst not in ssa: ");
 743       nir_print_instr(&instr->instr, stderr);
 744       fprintf(stderr, "\n");
 745       abort();
 746    }
 747    Builder bld(ctx->program, ctx->block);
 748    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 749    switch(instr->op) {
 750    case nir_op_vec2:
 751    case nir_op_vec3:
 752    case nir_op_vec4: {
 753       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 754       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 755       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 756          elems[i] = get_alu_src(ctx, instr->src[i]);
 757          vec->operands[i] = Operand{elems[i]};
 758       }
 759       vec->definitions[0] = Definition(dst);
 760       ctx->block->instructions.emplace_back(std::move(vec));
 761       ctx->allocated_vec.emplace(dst.id(), elems);
 762       break;
 763    }
 764    case nir_op_mov: {
 765       Temp src = get_alu_src(ctx, instr->src[0]);
 766       aco_ptr<Instruction> mov;
 767       if (dst.type() == RegType::sgpr) {
 768          if (src.type() == RegType::vgpr)
 769             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 770          else if (src.regClass() == s1)
 771             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 772          else if (src.regClass() == s2)
 773             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 774          else
 775             unreachable("wrong src register class for nir_op_imov");
 776       } else if (dst.regClass() == v1) {
 777          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 778       } else if (dst.regClass() == v2) {
 779          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 780       } else {
 781          nir_print_instr(&instr->instr, stderr);
 782          unreachable("Should have been lowered to scalar.");
 783       }
 784       break;
 785    }
 786    case nir_op_inot: {
 787       Temp src = get_alu_src(ctx, instr->src[0]);
 788       if (instr->dest.dest.ssa.bit_size == 1) {
 789          assert(src.regClass() == bld.lm);
 790          assert(dst.regClass() == bld.lm);
 791          bld.sop2(Builder::s_andn2, Definition(dst), bld.def(s1, scc), Operand(exec, bld.lm), src);
 792       } else if (dst.regClass() == v1) {
 793          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 794       } else if (dst.type() == RegType::sgpr) {
 795          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 796          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 797       } else {
 798          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 799          nir_print_instr(&instr->instr, stderr);
 800          fprintf(stderr, "\n");
 801       }
 802       break;
 803    }
 804    case nir_op_ineg: {
 805       Temp src = get_alu_src(ctx, instr->src[0]);
 806       if (dst.regClass() == v1) {
 807          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 808       } else if (dst.regClass() == s1) {
 809          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 810       } else if (dst.size() == 2) {
 811          Temp src0 = bld.tmp(dst.type(), 1);
 812          Temp src1 = bld.tmp(dst.type(), 1);
 813          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 814
 815          if (dst.regClass() == s2) {
 816             Temp carry = bld.tmp(s1);
 817             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 818             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 819             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 820          } else {
 821             Temp lower = bld.tmp(v1);
 822             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 823             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 824             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 825          }
 826       } else {
 827          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 828          nir_print_instr(&instr->instr, stderr);
 829          fprintf(stderr, "\n");
 830       }
 831       break;
 832    }
 833    case nir_op_iabs: {
 834       if (dst.regClass() == s1) {
 835          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 836       } else if (dst.regClass() == v1) {
 837          Temp src = get_alu_src(ctx, instr->src[0]);
 838          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 839       } else {
 840          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 841          nir_print_instr(&instr->instr, stderr);
 842          fprintf(stderr, "\n");
 843       }
 844       break;
 845    }
 846    case nir_op_isign: {
 847       Temp src = get_alu_src(ctx, instr->src[0]);
 848       if (dst.regClass() == s1) {
 849          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 850          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 851          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 852       } else if (dst.regClass() == s2) {
 853          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 854          Temp neqz;
 855          if (ctx->program->chip_class >= GFX8)
 856             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 857          else
 858             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 859          /* SCC gets zero-extended to 64 bit */
 860          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 861       } else if (dst.regClass() == v1) {
 862          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 863          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 864          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 865       } else if (dst.regClass() == v2) {
 866          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 867          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 868          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 869          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 870          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 871          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 872       } else {
 873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 874          nir_print_instr(&instr->instr, stderr);
 875          fprintf(stderr, "\n");
 876       }
 877       break;
 878    }
 879    case nir_op_imax: {
 880       if (dst.regClass() == v1) {
 881          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 882       } else if (dst.regClass() == s1) {
 883          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 884       } else {
 885          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 886          nir_print_instr(&instr->instr, stderr);
 887          fprintf(stderr, "\n");
 888       }
 889       break;
 890    }
 891    case nir_op_umax: {
 892       if (dst.regClass() == v1) {
 893          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 894       } else if (dst.regClass() == s1) {
 895          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 896       } else {
 897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 898          nir_print_instr(&instr->instr, stderr);
 899          fprintf(stderr, "\n");
 900       }
 901       break;
 902    }
 903    case nir_op_imin: {
 904       if (dst.regClass() == v1) {
 905          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 906       } else if (dst.regClass() == s1) {
 907          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 908       } else {
 909          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 910          nir_print_instr(&instr->instr, stderr);
 911          fprintf(stderr, "\n");
 912       }
 913       break;
 914    }
 915    case nir_op_umin: {
 916       if (dst.regClass() == v1) {
 917          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 918       } else if (dst.regClass() == s1) {
 919          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
 920       } else {
 921          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 922          nir_print_instr(&instr->instr, stderr);
 923          fprintf(stderr, "\n");
 924       }
 925       break;
 926    }
 927    case nir_op_ior: {
 928       if (instr->dest.dest.ssa.bit_size == 1) {
 929          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
 930       } else if (dst.regClass() == v1) {
 931          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
 932       } else if (dst.regClass() == s1) {
 933          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
 934       } else if (dst.regClass() == s2) {
 935          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
 936       } else {
 937          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 938          nir_print_instr(&instr->instr, stderr);
 939          fprintf(stderr, "\n");
 940       }
 941       break;
 942    }
 943    case nir_op_iand: {
 944       if (instr->dest.dest.ssa.bit_size == 1) {
 945          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
 946       } else if (dst.regClass() == v1) {
 947          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
 948       } else if (dst.regClass() == s1) {
 949          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
 950       } else if (dst.regClass() == s2) {
 951          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_ixor: {
 960       if (instr->dest.dest.ssa.bit_size == 1) {
 961          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
 962       } else if (dst.regClass() == v1) {
 963          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
 964       } else if (dst.regClass() == s1) {
 965          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
 966       } else if (dst.regClass() == s2) {
 967          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
 968       } else {
 969          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 970          nir_print_instr(&instr->instr, stderr);
 971          fprintf(stderr, "\n");
 972       }
 973       break;
 974    }
 975    case nir_op_ushr: {
 976       if (dst.regClass() == v1) {
 977          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
 978       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
 979          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
 980                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 981       } else if (dst.regClass() == v2) {
 982          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
 983                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
 984       } else if (dst.regClass() == s2) {
 985          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_ishl: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
 998       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
 999          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1000                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1001       } else if (dst.regClass() == v2) {
1002          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1003                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1004       } else if (dst.regClass() == s1) {
1005          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1006       } else if (dst.regClass() == s2) {
1007          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1008       } else {
1009          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1010          nir_print_instr(&instr->instr, stderr);
1011          fprintf(stderr, "\n");
1012       }
1013       break;
1014    }
1015    case nir_op_ishr: {
1016       if (dst.regClass() == v1) {
1017          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1018       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1019          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1020                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1021       } else if (dst.regClass() == v2) {
1022          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1023                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1024       } else if (dst.regClass() == s1) {
1025          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1026       } else if (dst.regClass() == s2) {
1027          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1028       } else {
1029          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1030          nir_print_instr(&instr->instr, stderr);
1031          fprintf(stderr, "\n");
1032       }
1033       break;
1034    }
1035    case nir_op_find_lsb: {
1036       Temp src = get_alu_src(ctx, instr->src[0]);
1037       if (src.regClass() == s1) {
1038          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1039       } else if (src.regClass() == v1) {
1040          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1041       } else if (src.regClass() == s2) {
1042          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1043       } else {
1044          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1045          nir_print_instr(&instr->instr, stderr);
1046          fprintf(stderr, "\n");
1047       }
1048       break;
1049    }
1050    case nir_op_ufind_msb:
1051    case nir_op_ifind_msb: {
1052       Temp src = get_alu_src(ctx, instr->src[0]);
1053       if (src.regClass() == s1 || src.regClass() == s2) {
1054          aco_opcode op = src.regClass() == s2 ?
1055                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1056                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1057          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1058
1059          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1060                                         Operand(src.size() * 32u - 1u), msb_rev);
1061          Temp msb = sub.def(0).getTemp();
1062          Temp carry = sub.def(1).getTemp();
1063
1064          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, carry);
1065       } else if (src.regClass() == v1) {
1066          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1067          Temp msb_rev = bld.tmp(v1);
1068          emit_vop1_instruction(ctx, instr, op, msb_rev);
1069          Temp msb = bld.tmp(v1);
1070          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1071          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1072       } else {
1073          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1074          nir_print_instr(&instr->instr, stderr);
1075          fprintf(stderr, "\n");
1076       }
1077       break;
1078    }
1079    case nir_op_bitfield_reverse: {
1080       if (dst.regClass() == s1) {
1081          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1082       } else if (dst.regClass() == v1) {
1083          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1084       } else {
1085          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1086          nir_print_instr(&instr->instr, stderr);
1087          fprintf(stderr, "\n");
1088       }
1089       break;
1090    }
1091    case nir_op_iadd: {
1092       if (dst.regClass() == s1) {
1093          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1094          break;
1095       }
1096
1097       Temp src0 = get_alu_src(ctx, instr->src[0]);
1098       Temp src1 = get_alu_src(ctx, instr->src[1]);
1099       if (dst.regClass() == v1) {
1100          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1101          break;
1102       }
1103
1104       assert(src0.size() == 2 && src1.size() == 2);
1105       Temp src00 = bld.tmp(src0.type(), 1);
1106       Temp src01 = bld.tmp(dst.type(), 1);
1107       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1108       Temp src10 = bld.tmp(src1.type(), 1);
1109       Temp src11 = bld.tmp(dst.type(), 1);
1110       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1111
1112       if (dst.regClass() == s2) {
1113          Temp carry = bld.tmp(s1);
1114          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1115          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1116          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1117       } else if (dst.regClass() == v2) {
1118          Temp dst0 = bld.tmp(v1);
1119          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1120          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1121          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1122       } else {
1123          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1124          nir_print_instr(&instr->instr, stderr);
1125          fprintf(stderr, "\n");
1126       }
1127       break;
1128    }
1129    case nir_op_uadd_sat: {
1130       Temp src0 = get_alu_src(ctx, instr->src[0]);
1131       Temp src1 = get_alu_src(ctx, instr->src[1]);
1132       if (dst.regClass() == s1) {
1133          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1134          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1135                   src0, src1);
1136          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1137       } else if (dst.regClass() == v1) {
1138          if (ctx->options->chip_class >= GFX9) {
1139             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1140             add->operands[0] = Operand(src0);
1141             add->operands[1] = Operand(src1);
1142             add->definitions[0] = Definition(dst);
1143             add->clamp = 1;
1144             ctx->block->instructions.emplace_back(std::move(add));
1145          } else {
1146             if (src1.regClass() != v1)
1147                std::swap(src0, src1);
1148             assert(src1.regClass() == v1);
1149             Temp tmp = bld.tmp(v1);
1150             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1151             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1152          }
1153       } else {
1154          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1155          nir_print_instr(&instr->instr, stderr);
1156          fprintf(stderr, "\n");
1157       }
1158       break;
1159    }
1160    case nir_op_uadd_carry: {
1161       Temp src0 = get_alu_src(ctx, instr->src[0]);
1162       Temp src1 = get_alu_src(ctx, instr->src[1]);
1163       if (dst.regClass() == s1) {
1164          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1165          break;
1166       }
1167       if (dst.regClass() == v1) {
1168          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1169          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1170          break;
1171       }
1172
1173       Temp src00 = bld.tmp(src0.type(), 1);
1174       Temp src01 = bld.tmp(dst.type(), 1);
1175       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1176       Temp src10 = bld.tmp(src1.type(), 1);
1177       Temp src11 = bld.tmp(dst.type(), 1);
1178       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1179       if (dst.regClass() == s2) {
1180          Temp carry = bld.tmp(s1);
1181          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1182          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1183          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1184       } else if (dst.regClass() == v2) {
1185          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1186          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1187          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1188          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1189       } else {
1190          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1191          nir_print_instr(&instr->instr, stderr);
1192          fprintf(stderr, "\n");
1193       }
1194       break;
1195    }
1196    case nir_op_isub: {
1197       if (dst.regClass() == s1) {
1198          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1199          break;
1200       }
1201
1202       Temp src0 = get_alu_src(ctx, instr->src[0]);
1203       Temp src1 = get_alu_src(ctx, instr->src[1]);
1204       if (dst.regClass() == v1) {
1205          bld.vsub32(Definition(dst), src0, src1);
1206          break;
1207       }
1208
1209       Temp src00 = bld.tmp(src0.type(), 1);
1210       Temp src01 = bld.tmp(dst.type(), 1);
1211       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1212       Temp src10 = bld.tmp(src1.type(), 1);
1213       Temp src11 = bld.tmp(dst.type(), 1);
1214       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1215       if (dst.regClass() == s2) {
1216          Temp carry = bld.tmp(s1);
1217          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1218          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1219          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1220       } else if (dst.regClass() == v2) {
1221          Temp lower = bld.tmp(v1);
1222          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1223          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1224          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1225       } else {
1226          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1227          nir_print_instr(&instr->instr, stderr);
1228          fprintf(stderr, "\n");
1229       }
1230       break;
1231    }
1232    case nir_op_usub_borrow: {
1233       Temp src0 = get_alu_src(ctx, instr->src[0]);
1234       Temp src1 = get_alu_src(ctx, instr->src[1]);
1235       if (dst.regClass() == s1) {
1236          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1237          break;
1238       } else if (dst.regClass() == v1) {
1239          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1240          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1241          break;
1242       }
1243
1244       Temp src00 = bld.tmp(src0.type(), 1);
1245       Temp src01 = bld.tmp(dst.type(), 1);
1246       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1247       Temp src10 = bld.tmp(src1.type(), 1);
1248       Temp src11 = bld.tmp(dst.type(), 1);
1249       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1250       if (dst.regClass() == s2) {
1251          Temp borrow = bld.tmp(s1);
1252          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1253          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1254          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1255       } else if (dst.regClass() == v2) {
1256          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1257          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1258          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1259          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1260       } else {
1261          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1262          nir_print_instr(&instr->instr, stderr);
1263          fprintf(stderr, "\n");
1264       }
1265       break;
1266    }
1267    case nir_op_imul: {
1268       if (dst.regClass() == v1) {
1269          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1270                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1271       } else if (dst.regClass() == s1) {
1272          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1273       } else {
1274          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1275          nir_print_instr(&instr->instr, stderr);
1276          fprintf(stderr, "\n");
1277       }
1278       break;
1279    }
1280    case nir_op_umul_high: {
1281       if (dst.regClass() == v1) {
1282          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1283       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1284          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1285       } else if (dst.regClass() == s1) {
1286          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1287                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1288          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1289       } else {
1290          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1291          nir_print_instr(&instr->instr, stderr);
1292          fprintf(stderr, "\n");
1293       }
1294       break;
1295    }
1296    case nir_op_imul_high: {
1297       if (dst.regClass() == v1) {
1298          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1299       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1300          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1301       } else if (dst.regClass() == s1) {
1302          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1303                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1304          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_fmul: {
1313       if (dst.size() == 1) {
1314          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1315       } else if (dst.size() == 2) {
1316          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1317                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1318       } else {
1319          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1320          nir_print_instr(&instr->instr, stderr);
1321          fprintf(stderr, "\n");
1322       }
1323       break;
1324    }
1325    case nir_op_fadd: {
1326       if (dst.size() == 1) {
1327          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1328       } else if (dst.size() == 2) {
1329          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1330                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1331       } else {
1332          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1333          nir_print_instr(&instr->instr, stderr);
1334          fprintf(stderr, "\n");
1335       }
1336       break;
1337    }
1338    case nir_op_fsub: {
1339       Temp src0 = get_alu_src(ctx, instr->src[0]);
1340       Temp src1 = get_alu_src(ctx, instr->src[1]);
1341       if (dst.size() == 1) {
1342          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1343             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1344          else
1345             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1346       } else if (dst.size() == 2) {
1347          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1348                                      get_alu_src(ctx, instr->src[0]),
1349                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1350          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1351          sub->neg[1] = true;
1352       } else {
1353          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1354          nir_print_instr(&instr->instr, stderr);
1355          fprintf(stderr, "\n");
1356       }
1357       break;
1358    }
1359    case nir_op_fmax: {
1360       if (dst.size() == 1) {
1361          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1362       } else if (dst.size() == 2) {
1363          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1364             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1365                                 get_alu_src(ctx, instr->src[0]),
1366                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1367             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1368          } else {
1369             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1370                      get_alu_src(ctx, instr->src[0]),
1371                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1372          }
1373       } else {
1374          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1375          nir_print_instr(&instr->instr, stderr);
1376          fprintf(stderr, "\n");
1377       }
1378       break;
1379    }
1380    case nir_op_fmin: {
1381       if (dst.size() == 1) {
1382          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1383       } else if (dst.size() == 2) {
1384          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1385             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1386                                 get_alu_src(ctx, instr->src[0]),
1387                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1388             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1389          } else {
1390             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1391                      get_alu_src(ctx, instr->src[0]),
1392                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1393          }
1394       } else {
1395          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1396          nir_print_instr(&instr->instr, stderr);
1397          fprintf(stderr, "\n");
1398       }
1399       break;
1400    }
1401    case nir_op_fmax3: {
1402       if (dst.size() == 1) {
1403          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1404       } else {
1405          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1406          nir_print_instr(&instr->instr, stderr);
1407          fprintf(stderr, "\n");
1408       }
1409       break;
1410    }
1411    case nir_op_fmin3: {
1412       if (dst.size() == 1) {
1413          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1414       } else {
1415          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1416          nir_print_instr(&instr->instr, stderr);
1417          fprintf(stderr, "\n");
1418       }
1419       break;
1420    }
1421    case nir_op_fmed3: {
1422       if (dst.size() == 1) {
1423          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1424       } else {
1425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1426          nir_print_instr(&instr->instr, stderr);
1427          fprintf(stderr, "\n");
1428       }
1429       break;
1430    }
1431    case nir_op_umax3: {
1432       if (dst.size() == 1) {
1433          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1434       } else {
1435          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1436          nir_print_instr(&instr->instr, stderr);
1437          fprintf(stderr, "\n");
1438       }
1439       break;
1440    }
1441    case nir_op_umin3: {
1442       if (dst.size() == 1) {
1443          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1444       } else {
1445          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1446          nir_print_instr(&instr->instr, stderr);
1447          fprintf(stderr, "\n");
1448       }
1449       break;
1450    }
1451    case nir_op_umed3: {
1452       if (dst.size() == 1) {
1453          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1454       } else {
1455          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1456          nir_print_instr(&instr->instr, stderr);
1457          fprintf(stderr, "\n");
1458       }
1459       break;
1460    }
1461    case nir_op_imax3: {
1462       if (dst.size() == 1) {
1463          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1464       } else {
1465          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1466          nir_print_instr(&instr->instr, stderr);
1467          fprintf(stderr, "\n");
1468       }
1469       break;
1470    }
1471    case nir_op_imin3: {
1472       if (dst.size() == 1) {
1473          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_imed3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_cube_face_coord: {
1492       Temp in = get_alu_src(ctx, instr->src[0], 3);
1493       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1494                       emit_extract_vector(ctx, in, 1, v1),
1495                       emit_extract_vector(ctx, in, 2, v1) };
1496       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1497       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1498       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1499       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1500       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1501       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1502       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1503       break;
1504    }
1505    case nir_op_cube_face_index: {
1506       Temp in = get_alu_src(ctx, instr->src[0], 3);
1507       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1508                       emit_extract_vector(ctx, in, 1, v1),
1509                       emit_extract_vector(ctx, in, 2, v1) };
1510       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1511       break;
1512    }
1513    case nir_op_bcsel: {
1514       emit_bcsel(ctx, instr, dst);
1515       break;
1516    }
1517    case nir_op_frsq: {
1518       if (dst.size() == 1) {
1519          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1520       } else if (dst.size() == 2) {
1521          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1522       } else {
1523          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1524          nir_print_instr(&instr->instr, stderr);
1525          fprintf(stderr, "\n");
1526       }
1527       break;
1528    }
1529    case nir_op_fneg: {
1530       Temp src = get_alu_src(ctx, instr->src[0]);
1531       if (dst.size() == 1) {
1532          if (ctx->block->fp_mode.must_flush_denorms32)
1533             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1534          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1535       } else if (dst.size() == 2) {
1536          if (ctx->block->fp_mode.must_flush_denorms16_64)
1537             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1538          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1539          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1540          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1541          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1542       } else {
1543          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1544          nir_print_instr(&instr->instr, stderr);
1545          fprintf(stderr, "\n");
1546       }
1547       break;
1548    }
1549    case nir_op_fabs: {
1550       Temp src = get_alu_src(ctx, instr->src[0]);
1551       if (dst.size() == 1) {
1552          if (ctx->block->fp_mode.must_flush_denorms32)
1553             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1554          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1555       } else if (dst.size() == 2) {
1556          if (ctx->block->fp_mode.must_flush_denorms16_64)
1557             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1558          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1559          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1560          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1561          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1562       } else {
1563          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1564          nir_print_instr(&instr->instr, stderr);
1565          fprintf(stderr, "\n");
1566       }
1567       break;
1568    }
1569    case nir_op_fsat: {
1570       Temp src = get_alu_src(ctx, instr->src[0]);
1571       if (dst.size() == 1) {
1572          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1573          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1574          // TODO: confirm that this holds under any circumstances
1575       } else if (dst.size() == 2) {
1576          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1577          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1578          vop3->clamp = true;
1579       } else {
1580          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1581          nir_print_instr(&instr->instr, stderr);
1582          fprintf(stderr, "\n");
1583       }
1584       break;
1585    }
1586    case nir_op_flog2: {
1587       if (dst.size() == 1) {
1588          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1589       } else {
1590          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1591          nir_print_instr(&instr->instr, stderr);
1592          fprintf(stderr, "\n");
1593       }
1594       break;
1595    }
1596    case nir_op_frcp: {
1597       if (dst.size() == 1) {
1598          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1599       } else if (dst.size() == 2) {
1600          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1601       } else {
1602          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1603          nir_print_instr(&instr->instr, stderr);
1604          fprintf(stderr, "\n");
1605       }
1606       break;
1607    }
1608    case nir_op_fexp2: {
1609       if (dst.size() == 1) {
1610          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1611       } else {
1612          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1613          nir_print_instr(&instr->instr, stderr);
1614          fprintf(stderr, "\n");
1615       }
1616       break;
1617    }
1618    case nir_op_fsqrt: {
1619       if (dst.size() == 1) {
1620          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1621       } else if (dst.size() == 2) {
1622          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1623       } else {
1624          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1625          nir_print_instr(&instr->instr, stderr);
1626          fprintf(stderr, "\n");
1627       }
1628       break;
1629    }
1630    case nir_op_ffract: {
1631       if (dst.size() == 1) {
1632          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1633       } else if (dst.size() == 2) {
1634          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1635       } else {
1636          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1637          nir_print_instr(&instr->instr, stderr);
1638          fprintf(stderr, "\n");
1639       }
1640       break;
1641    }
1642    case nir_op_ffloor: {
1643       if (dst.size() == 1) {
1644          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1645       } else if (dst.size() == 2) {
1646          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f64, dst);
1647       } else {
1648          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1649          nir_print_instr(&instr->instr, stderr);
1650          fprintf(stderr, "\n");
1651       }
1652       break;
1653    }
1654    case nir_op_fceil: {
1655       if (dst.size() == 1) {
1656          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1657       } else if (dst.size() == 2) {
1658          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_ftrunc: {
1667       if (dst.size() == 1) {
1668          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1669       } else if (dst.size() == 2) {
1670          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f64, dst);
1671       } else {
1672          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1673          nir_print_instr(&instr->instr, stderr);
1674          fprintf(stderr, "\n");
1675       }
1676       break;
1677    }
1678    case nir_op_fround_even: {
1679       if (dst.size() == 1) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1681       } else if (dst.size() == 2) {
1682          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1683       } else {
1684          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1685          nir_print_instr(&instr->instr, stderr);
1686          fprintf(stderr, "\n");
1687       }
1688       break;
1689    }
1690    case nir_op_fsin:
1691    case nir_op_fcos: {
1692       Temp src = get_alu_src(ctx, instr->src[0]);
1693       aco_ptr<Instruction> norm;
1694       if (dst.size() == 1) {
1695          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1696          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1697
1698          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1699          if (ctx->options->chip_class < GFX9)
1700             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1701
1702          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1703          bld.vop1(opcode, Definition(dst), tmp);
1704       } else {
1705          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1706          nir_print_instr(&instr->instr, stderr);
1707          fprintf(stderr, "\n");
1708       }
1709       break;
1710    }
1711    case nir_op_ldexp: {
1712       if (dst.size() == 1) {
1713          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1714                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1715                   get_alu_src(ctx, instr->src[1]));
1716       } else if (dst.size() == 2) {
1717          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1718                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1719                   get_alu_src(ctx, instr->src[1]));
1720       } else {
1721          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1722          nir_print_instr(&instr->instr, stderr);
1723          fprintf(stderr, "\n");
1724       }
1725       break;
1726    }
1727    case nir_op_frexp_sig: {
1728       if (dst.size() == 1) {
1729          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1730                   get_alu_src(ctx, instr->src[0]));
1731       } else if (dst.size() == 2) {
1732          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1733                   get_alu_src(ctx, instr->src[0]));
1734       } else {
1735          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1736          nir_print_instr(&instr->instr, stderr);
1737          fprintf(stderr, "\n");
1738       }
1739       break;
1740    }
1741    case nir_op_frexp_exp: {
1742       if (instr->src[0].src.ssa->bit_size == 32) {
1743          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1744                   get_alu_src(ctx, instr->src[0]));
1745       } else if (instr->src[0].src.ssa->bit_size == 64) {
1746          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1747                   get_alu_src(ctx, instr->src[0]));
1748       } else {
1749          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1750          nir_print_instr(&instr->instr, stderr);
1751          fprintf(stderr, "\n");
1752       }
1753       break;
1754    }
1755    case nir_op_fsign: {
1756       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1757       if (dst.size() == 1) {
1758          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1759          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1760          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1761          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1762       } else if (dst.size() == 2) {
1763          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1764          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1765          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1766
1767          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1768          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1769          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1770
1771          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1772       } else {
1773          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1774          nir_print_instr(&instr->instr, stderr);
1775          fprintf(stderr, "\n");
1776       }
1777       break;
1778    }
1779    case nir_op_f2f32: {
1780       if (instr->src[0].src.ssa->bit_size == 64) {
1781          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1782       } else {
1783          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1784          nir_print_instr(&instr->instr, stderr);
1785          fprintf(stderr, "\n");
1786       }
1787       break;
1788    }
1789    case nir_op_f2f64: {
1790       if (instr->src[0].src.ssa->bit_size == 32) {
1791          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1792       } else {
1793          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1794          nir_print_instr(&instr->instr, stderr);
1795          fprintf(stderr, "\n");
1796       }
1797       break;
1798    }
1799    case nir_op_i2f32: {
1800       assert(dst.size() == 1);
1801       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1802       break;
1803    }
1804    case nir_op_i2f64: {
1805       if (instr->src[0].src.ssa->bit_size == 32) {
1806          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1807       } else if (instr->src[0].src.ssa->bit_size == 64) {
1808          Temp src = get_alu_src(ctx, instr->src[0]);
1809          RegClass rc = RegClass(src.type(), 1);
1810          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1811          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1812          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1813          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1814          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1815          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1816
1817       } else {
1818          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1819          nir_print_instr(&instr->instr, stderr);
1820          fprintf(stderr, "\n");
1821       }
1822       break;
1823    }
1824    case nir_op_u2f32: {
1825       assert(dst.size() == 1);
1826       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1827       break;
1828    }
1829    case nir_op_u2f64: {
1830       if (instr->src[0].src.ssa->bit_size == 32) {
1831          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1832       } else if (instr->src[0].src.ssa->bit_size == 64) {
1833          Temp src = get_alu_src(ctx, instr->src[0]);
1834          RegClass rc = RegClass(src.type(), 1);
1835          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1836          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1837          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1838          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1839          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1840          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1841       } else {
1842          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1843          nir_print_instr(&instr->instr, stderr);
1844          fprintf(stderr, "\n");
1845       }
1846       break;
1847    }
1848    case nir_op_f2i32: {
1849       Temp src = get_alu_src(ctx, instr->src[0]);
1850       if (instr->src[0].src.ssa->bit_size == 32) {
1851          if (dst.type() == RegType::vgpr)
1852             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1853          else
1854             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1855                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1856
1857       } else if (instr->src[0].src.ssa->bit_size == 64) {
1858          if (dst.type() == RegType::vgpr)
1859             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1860          else
1861             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1862                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1863
1864       } else {
1865          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1866          nir_print_instr(&instr->instr, stderr);
1867          fprintf(stderr, "\n");
1868       }
1869       break;
1870    }
1871    case nir_op_f2u32: {
1872       Temp src = get_alu_src(ctx, instr->src[0]);
1873       if (instr->src[0].src.ssa->bit_size == 32) {
1874          if (dst.type() == RegType::vgpr)
1875             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
1876          else
1877             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1878                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
1879
1880       } else if (instr->src[0].src.ssa->bit_size == 64) {
1881          if (dst.type() == RegType::vgpr)
1882             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
1883          else
1884             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1885                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
1886
1887       } else {
1888          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1889          nir_print_instr(&instr->instr, stderr);
1890          fprintf(stderr, "\n");
1891       }
1892       break;
1893    }
1894    case nir_op_f2i64: {
1895       Temp src = get_alu_src(ctx, instr->src[0]);
1896       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1897          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1898          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
1899          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1900          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
1901          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1902          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
1903          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1904          Temp new_exponent = bld.tmp(v1);
1905          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
1906          if (ctx->program->chip_class >= GFX8)
1907             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
1908          else
1909             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
1910          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
1911          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1912          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1913          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
1914          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
1915          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
1916          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
1917          Temp new_lower = bld.tmp(v1);
1918          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
1919          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
1920          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
1921
1922       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1923          if (src.type() == RegType::vgpr)
1924             src = bld.as_uniform(src);
1925          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1926          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1927          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1928          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
1929          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1930          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
1931          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1932          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
1933          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1934          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
1935          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
1936          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
1937          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
1938          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
1939          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1940          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1941          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
1942          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
1943          Temp borrow = bld.tmp(s1);
1944          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
1945          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
1946          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1947
1948       } else if (instr->src[0].src.ssa->bit_size == 64) {
1949          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1950          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1951          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1952          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1953          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1954          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1955          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1956          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
1957          if (dst.type() == RegType::sgpr) {
1958             lower = bld.as_uniform(lower);
1959             upper = bld.as_uniform(upper);
1960          }
1961          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1962
1963       } else {
1964          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1965          nir_print_instr(&instr->instr, stderr);
1966          fprintf(stderr, "\n");
1967       }
1968       break;
1969    }
1970    case nir_op_f2u64: {
1971       Temp src = get_alu_src(ctx, instr->src[0]);
1972       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1973          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1974          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
1975          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
1976          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1977          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1978          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
1979          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
1980          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1981          Temp new_exponent = bld.tmp(v1);
1982          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
1983          if (ctx->program->chip_class >= GFX8)
1984             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
1985          else
1986             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
1987          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1988          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1989          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
1990          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
1991          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
1992          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
1993          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1994
1995       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1996          if (src.type() == RegType::vgpr)
1997             src = bld.as_uniform(src);
1998          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1999          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2000          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2001          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2002          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2003          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2004          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2005          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2006          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2007          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2008          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2009          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2010          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2011          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2012          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2013          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2014          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2015          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2016
2017       } else if (instr->src[0].src.ssa->bit_size == 64) {
2018          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2019          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
2020          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2021          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2022          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
2023          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2024          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2025          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2026          if (dst.type() == RegType::sgpr) {
2027             lower = bld.as_uniform(lower);
2028             upper = bld.as_uniform(upper);
2029          }
2030          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2031
2032       } else {
2033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2034          nir_print_instr(&instr->instr, stderr);
2035          fprintf(stderr, "\n");
2036       }
2037       break;
2038    }
2039    case nir_op_b2f32: {
2040       Temp src = get_alu_src(ctx, instr->src[0]);
2041       assert(src.regClass() == bld.lm);
2042
2043       if (dst.regClass() == s1) {
2044          src = bool_to_scalar_condition(ctx, src);
2045          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2046       } else if (dst.regClass() == v1) {
2047          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2048       } else {
2049          unreachable("Wrong destination register class for nir_op_b2f32.");
2050       }
2051       break;
2052    }
2053    case nir_op_b2f64: {
2054       Temp src = get_alu_src(ctx, instr->src[0]);
2055       assert(src.regClass() == bld.lm);
2056
2057       if (dst.regClass() == s2) {
2058          src = bool_to_scalar_condition(ctx, src);
2059          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2060       } else if (dst.regClass() == v2) {
2061          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2062          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2063          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2064       } else {
2065          unreachable("Wrong destination register class for nir_op_b2f64.");
2066       }
2067       break;
2068    }
2069    case nir_op_i2i32: {
2070       Temp src = get_alu_src(ctx, instr->src[0]);
2071       if (instr->src[0].src.ssa->bit_size == 64) {
2072          /* we can actually just say dst = src, as it would map the lower register */
2073          emit_extract_vector(ctx, src, 0, dst);
2074       } else {
2075          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2076          nir_print_instr(&instr->instr, stderr);
2077          fprintf(stderr, "\n");
2078       }
2079       break;
2080    }
2081    case nir_op_u2u32: {
2082       Temp src = get_alu_src(ctx, instr->src[0]);
2083       if (instr->src[0].src.ssa->bit_size == 16) {
2084          if (dst.regClass() == s1) {
2085             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2086          } else {
2087             // TODO: do better with SDWA
2088             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2089          }
2090       } else if (instr->src[0].src.ssa->bit_size == 64) {
2091          /* we can actually just say dst = src, as it would map the lower register */
2092          emit_extract_vector(ctx, src, 0, dst);
2093       } else {
2094          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2095          nir_print_instr(&instr->instr, stderr);
2096          fprintf(stderr, "\n");
2097       }
2098       break;
2099    }
2100    case nir_op_i2i64: {
2101       Temp src = get_alu_src(ctx, instr->src[0]);
2102       if (src.regClass() == s1) {
2103          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2104          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2105       } else if (src.regClass() == v1) {
2106          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2107          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2108       } else {
2109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2110          nir_print_instr(&instr->instr, stderr);
2111          fprintf(stderr, "\n");
2112       }
2113       break;
2114    }
2115    case nir_op_u2u64: {
2116       Temp src = get_alu_src(ctx, instr->src[0]);
2117       if (instr->src[0].src.ssa->bit_size == 32) {
2118          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2119       } else {
2120          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2121          nir_print_instr(&instr->instr, stderr);
2122          fprintf(stderr, "\n");
2123       }
2124       break;
2125    }
2126    case nir_op_b2i32: {
2127       Temp src = get_alu_src(ctx, instr->src[0]);
2128       assert(src.regClass() == bld.lm);
2129
2130       if (dst.regClass() == s1) {
2131          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2132          bool_to_scalar_condition(ctx, src, dst);
2133       } else if (dst.regClass() == v1) {
2134          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2135       } else {
2136          unreachable("Invalid register class for b2i32");
2137       }
2138       break;
2139    }
2140    case nir_op_i2b1: {
2141       Temp src = get_alu_src(ctx, instr->src[0]);
2142       assert(dst.regClass() == bld.lm);
2143
2144       if (src.type() == RegType::vgpr) {
2145          assert(src.regClass() == v1 || src.regClass() == v2);
2146          assert(dst.regClass() == bld.lm);
2147          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2148                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2149       } else {
2150          assert(src.regClass() == s1 || src.regClass() == s2);
2151          Temp tmp;
2152          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2153             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2154          } else {
2155             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2156                            bld.scc(bld.def(s1)), Operand(0u), src);
2157          }
2158          bool_to_vector_condition(ctx, tmp, dst);
2159       }
2160       break;
2161    }
2162    case nir_op_pack_64_2x32_split: {
2163       Temp src0 = get_alu_src(ctx, instr->src[0]);
2164       Temp src1 = get_alu_src(ctx, instr->src[1]);
2165
2166       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2167       break;
2168    }
2169    case nir_op_unpack_64_2x32_split_x:
2170       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2171       break;
2172    case nir_op_unpack_64_2x32_split_y:
2173       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2174       break;
2175    case nir_op_pack_half_2x16: {
2176       Temp src = get_alu_src(ctx, instr->src[0], 2);
2177
2178       if (dst.regClass() == v1) {
2179          Temp src0 = bld.tmp(v1);
2180          Temp src1 = bld.tmp(v1);
2181          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2182          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2183             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2184          else
2185             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2186                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2187                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2188       } else {
2189          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2190          nir_print_instr(&instr->instr, stderr);
2191          fprintf(stderr, "\n");
2192       }
2193       break;
2194    }
2195    case nir_op_unpack_half_2x16_split_x: {
2196       if (dst.regClass() == v1) {
2197          Builder bld(ctx->program, ctx->block);
2198          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2199       } else {
2200          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2201          nir_print_instr(&instr->instr, stderr);
2202          fprintf(stderr, "\n");
2203       }
2204       break;
2205    }
2206    case nir_op_unpack_half_2x16_split_y: {
2207       if (dst.regClass() == v1) {
2208          Builder bld(ctx->program, ctx->block);
2209          /* TODO: use SDWA here */
2210          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2211                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2212       } else {
2213          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2214          nir_print_instr(&instr->instr, stderr);
2215          fprintf(stderr, "\n");
2216       }
2217       break;
2218    }
2219    case nir_op_fquantize2f16: {
2220       Temp src = get_alu_src(ctx, instr->src[0]);
2221       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2222       Temp f32, cmp_res;
2223
2224       if (ctx->program->chip_class >= GFX8) {
2225          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2226          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2227          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2228       } else {
2229          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2230           * so compare the result and flush to 0 if it's smaller.
2231           */
2232          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2233          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2234          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2235          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2236          cmp_res = vop3->definitions[0].getTemp();
2237       }
2238
2239       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2240          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2241          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2242       } else {
2243          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2244       }
2245       break;
2246    }
2247    case nir_op_bfm: {
2248       Temp bits = get_alu_src(ctx, instr->src[0]);
2249       Temp offset = get_alu_src(ctx, instr->src[1]);
2250
2251       if (dst.regClass() == s1) {
2252          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2253       } else if (dst.regClass() == v1) {
2254          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2255       } else {
2256          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2257          nir_print_instr(&instr->instr, stderr);
2258          fprintf(stderr, "\n");
2259       }
2260       break;
2261    }
2262    case nir_op_bitfield_select: {
2263       /* (mask & insert) | (~mask & base) */
2264       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2265       Temp insert = get_alu_src(ctx, instr->src[1]);
2266       Temp base = get_alu_src(ctx, instr->src[2]);
2267
2268       /* dst = (insert & bitmask) | (base & ~bitmask) */
2269       if (dst.regClass() == s1) {
2270          aco_ptr<Instruction> sop2;
2271          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2272          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2273          Operand lhs;
2274          if (const_insert && const_bitmask) {
2275             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2276          } else {
2277             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2278             lhs = Operand(insert);
2279          }
2280
2281          Operand rhs;
2282          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2283          if (const_base && const_bitmask) {
2284             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2285          } else {
2286             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2287             rhs = Operand(base);
2288          }
2289
2290          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2291
2292       } else if (dst.regClass() == v1) {
2293          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2294             base = as_vgpr(ctx, base);
2295          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2296             insert = as_vgpr(ctx, insert);
2297
2298          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2299
2300       } else {
2301          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2302          nir_print_instr(&instr->instr, stderr);
2303          fprintf(stderr, "\n");
2304       }
2305       break;
2306    }
2307    case nir_op_ubfe:
2308    case nir_op_ibfe: {
2309       Temp base = get_alu_src(ctx, instr->src[0]);
2310       Temp offset = get_alu_src(ctx, instr->src[1]);
2311       Temp bits = get_alu_src(ctx, instr->src[2]);
2312
2313       if (dst.type() == RegType::sgpr) {
2314          Operand extract;
2315          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2316          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2317          if (const_offset && const_bits) {
2318             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2319             extract = Operand(const_extract);
2320          } else {
2321             Operand width;
2322             if (const_bits) {
2323                width = Operand(const_bits->u32 << 16);
2324             } else {
2325                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2326             }
2327             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2328          }
2329
2330          aco_opcode opcode;
2331          if (dst.regClass() == s1) {
2332             if (instr->op == nir_op_ubfe)
2333                opcode = aco_opcode::s_bfe_u32;
2334             else
2335                opcode = aco_opcode::s_bfe_i32;
2336          } else if (dst.regClass() == s2) {
2337             if (instr->op == nir_op_ubfe)
2338                opcode = aco_opcode::s_bfe_u64;
2339             else
2340                opcode = aco_opcode::s_bfe_i64;
2341          } else {
2342             unreachable("Unsupported BFE bit size");
2343          }
2344
2345          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2346
2347       } else {
2348          aco_opcode opcode;
2349          if (dst.regClass() == v1) {
2350             if (instr->op == nir_op_ubfe)
2351                opcode = aco_opcode::v_bfe_u32;
2352             else
2353                opcode = aco_opcode::v_bfe_i32;
2354          } else {
2355             unreachable("Unsupported BFE bit size");
2356          }
2357
2358          emit_vop3a_instruction(ctx, instr, opcode, dst);
2359       }
2360       break;
2361    }
2362    case nir_op_bit_count: {
2363       Temp src = get_alu_src(ctx, instr->src[0]);
2364       if (src.regClass() == s1) {
2365          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2366       } else if (src.regClass() == v1) {
2367          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2368       } else if (src.regClass() == v2) {
2369          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2370                   emit_extract_vector(ctx, src, 1, v1),
2371                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2372                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2373       } else if (src.regClass() == s2) {
2374          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2375       } else {
2376          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2377          nir_print_instr(&instr->instr, stderr);
2378          fprintf(stderr, "\n");
2379       }
2380       break;
2381    }
2382    case nir_op_flt: {
2383       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2384       break;
2385    }
2386    case nir_op_fge: {
2387       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2388       break;
2389    }
2390    case nir_op_feq: {
2391       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2392       break;
2393    }
2394    case nir_op_fne: {
2395       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2396       break;
2397    }
2398    case nir_op_ilt: {
2399       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2400       break;
2401    }
2402    case nir_op_ige: {
2403       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2404       break;
2405    }
2406    case nir_op_ieq: {
2407       if (instr->src[0].src.ssa->bit_size == 1)
2408          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2409       else
2410          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2411                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2412       break;
2413    }
2414    case nir_op_ine: {
2415       if (instr->src[0].src.ssa->bit_size == 1)
2416          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2417       else
2418          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2419                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2420       break;
2421    }
2422    case nir_op_ult: {
2423       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2424       break;
2425    }
2426    case nir_op_uge: {
2427       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2428       break;
2429    }
2430    case nir_op_fddx:
2431    case nir_op_fddy:
2432    case nir_op_fddx_fine:
2433    case nir_op_fddy_fine:
2434    case nir_op_fddx_coarse:
2435    case nir_op_fddy_coarse: {
2436       Temp src = get_alu_src(ctx, instr->src[0]);
2437       uint16_t dpp_ctrl1, dpp_ctrl2;
2438       if (instr->op == nir_op_fddx_fine) {
2439          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2440          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2441       } else if (instr->op == nir_op_fddy_fine) {
2442          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2443          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2444       } else {
2445          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2446          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2447             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2448          else
2449             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2450       }
2451
2452       Temp tmp;
2453       if (ctx->program->chip_class >= GFX8) {
2454          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2455          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2456       } else {
2457          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2458          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2459          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2460       }
2461       emit_wqm(ctx, tmp, dst, true);
2462       break;
2463    }
2464    default:
2465       fprintf(stderr, "Unknown NIR ALU instr: ");
2466       nir_print_instr(&instr->instr, stderr);
2467       fprintf(stderr, "\n");
2468    }
2469 }
2470
2471 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2472 {
2473    Temp dst = get_ssa_temp(ctx, &instr->def);
2474
2475    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2476    // which get truncated the lsb if double and msb if int
2477    // for now, we only use s_mov_b64 with 64bit inline constants
2478    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2479    assert(dst.type() == RegType::sgpr);
2480
2481    Builder bld(ctx->program, ctx->block);
2482
2483    if (instr->def.bit_size == 1) {
2484       assert(dst.regClass() == bld.lm);
2485       int val = instr->value[0].b ? -1 : 0;
2486       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2487       bld.sop1(Builder::s_mov, Definition(dst), op);
2488    } else if (dst.size() == 1) {
2489       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2490    } else {
2491       assert(dst.size() != 1);
2492       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2493       if (instr->def.bit_size == 64)
2494          for (unsigned i = 0; i < dst.size(); i++)
2495             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2496       else {
2497          for (unsigned i = 0; i < dst.size(); i++)
2498             vec->operands[i] = Operand{instr->value[i].u32};
2499       }
2500       vec->definitions[0] = Definition(dst);
2501       ctx->block->instructions.emplace_back(std::move(vec));
2502    }
2503 }
2504
2505 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2506 {
2507    uint32_t new_mask = 0;
2508    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2509       if (mask & (1u << i))
2510          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2511    return new_mask;
2512 }
2513
2514 void visit_store_vs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2515 {
2516    /* This wouldn't work inside control flow or with indirect offsets but
2517     * that doesn't happen because of nir_lower_io_to_temporaries(). */
2518
2519    unsigned write_mask = nir_intrinsic_write_mask(instr);
2520    unsigned component = nir_intrinsic_component(instr);
2521    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2522    unsigned idx = nir_intrinsic_base(instr) + component;
2523
2524    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2525    if (off_instr->type != nir_instr_type_load_const) {
2526       fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2527       nir_print_instr(off_instr, stderr);
2528       fprintf(stderr, "\n");
2529    }
2530    idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
2531
2532    if (instr->src[0].ssa->bit_size == 64)
2533       write_mask = widen_mask(write_mask, 2);
2534
2535    for (unsigned i = 0; i < 8; ++i) {
2536       if (write_mask & (1 << i)) {
2537          ctx->vs_output.mask[idx / 4u] |= 1 << (idx % 4u);
2538          ctx->vs_output.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
2539       }
2540       idx++;
2541    }
2542 }
2543
2544 void visit_store_fs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2545 {
2546    Builder bld(ctx->program, ctx->block);
2547    unsigned write_mask = nir_intrinsic_write_mask(instr);
2548    Operand values[4];
2549    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2550    for (unsigned i = 0; i < 4; ++i) {
2551       if (write_mask & (1 << i)) {
2552          Temp tmp = emit_extract_vector(ctx, src, i, v1);
2553          values[i] = Operand(tmp);
2554       } else {
2555          values[i] = Operand(v1);
2556       }
2557    }
2558
2559    unsigned index = nir_intrinsic_base(instr) / 4;
2560    unsigned target, col_format;
2561    unsigned enabled_channels = 0xF;
2562    aco_opcode compr_op = (aco_opcode)0;
2563
2564    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2565    assert(offset && "Non-const offsets on exports not yet supported");
2566    index += offset->u32;
2567
2568    assert(index != FRAG_RESULT_COLOR);
2569
2570    /* Unlike vertex shader exports, it's fine to use multiple exports to
2571     * export separate channels of one target. So shaders which export both
2572     * FRAG_RESULT_SAMPLE_MASK and FRAG_RESULT_DEPTH should work fine.
2573     * TODO: combine the exports in those cases and create better code
2574     */
2575
2576    if (index == FRAG_RESULT_SAMPLE_MASK) {
2577
2578       if (ctx->program->info->ps.writes_z) {
2579          target = V_008DFC_SQ_EXP_MRTZ;
2580          enabled_channels = 0x4;
2581          col_format = (unsigned) -1;
2582
2583          values[2] = values[0];
2584          values[0] = Operand(v1);
2585       } else {
2586          bld.exp(aco_opcode::exp, Operand(v1), Operand(values[0]), Operand(v1), Operand(v1),
2587                  0xc, V_008DFC_SQ_EXP_MRTZ, true);
2588          return;
2589       }
2590
2591    } else if (index == FRAG_RESULT_DEPTH) {
2592
2593       target = V_008DFC_SQ_EXP_MRTZ;
2594       enabled_channels = 0x1;
2595       col_format = (unsigned) -1;
2596
2597    } else if (index == FRAG_RESULT_STENCIL) {
2598
2599       if (ctx->program->info->ps.writes_z) {
2600          target = V_008DFC_SQ_EXP_MRTZ;
2601          enabled_channels = 0x2;
2602          col_format = (unsigned) -1;
2603
2604          values[1] = values[0];
2605          values[0] = Operand(v1);
2606       } else {
2607          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
2608          bld.exp(aco_opcode::exp, values[0], Operand(v1), Operand(v1), Operand(v1),
2609                  0x3, V_008DFC_SQ_EXP_MRTZ, true);
2610          return;
2611       }
2612
2613    } else {
2614       index -= FRAG_RESULT_DATA0;
2615       target = V_008DFC_SQ_EXP_MRT + index;
2616       col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2617    }
2618    bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2619    bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2620
2621    switch (col_format)
2622    {
2623    case V_028714_SPI_SHADER_ZERO:
2624       enabled_channels = 0; /* writemask */
2625       target = V_008DFC_SQ_EXP_NULL;
2626       break;
2627
2628    case V_028714_SPI_SHADER_32_R:
2629       enabled_channels = 1;
2630       break;
2631
2632    case V_028714_SPI_SHADER_32_GR:
2633       enabled_channels = 0x3;
2634       break;
2635
2636    case V_028714_SPI_SHADER_32_AR:
2637       if (ctx->options->chip_class >= GFX10) {
2638          /* Special case: on GFX10, the outputs are different for 32_AR */
2639          enabled_channels = 0x3;
2640          values[1] = values[3];
2641          values[3] = Operand(v1);
2642       } else {
2643          enabled_channels = 0x9;
2644       }
2645       break;
2646
2647    case V_028714_SPI_SHADER_FP16_ABGR:
2648       enabled_channels = 0x5;
2649       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
2650       break;
2651
2652    case V_028714_SPI_SHADER_UNORM16_ABGR:
2653       enabled_channels = 0x5;
2654       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
2655       break;
2656
2657    case V_028714_SPI_SHADER_SNORM16_ABGR:
2658       enabled_channels = 0x5;
2659       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
2660       break;
2661
2662    case V_028714_SPI_SHADER_UINT16_ABGR: {
2663       enabled_channels = 0x5;
2664       compr_op = aco_opcode::v_cvt_pk_u16_u32;
2665       if (is_int8 || is_int10) {
2666          /* clamp */
2667          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
2668          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
2669
2670          for (unsigned i = 0; i < 4; i++) {
2671             if ((write_mask >> i) & 1) {
2672                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
2673                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
2674                                     values[i]);
2675             }
2676          }
2677       }
2678       break;
2679    }
2680
2681    case V_028714_SPI_SHADER_SINT16_ABGR:
2682       enabled_channels = 0x5;
2683       compr_op = aco_opcode::v_cvt_pk_i16_i32;
2684       if (is_int8 || is_int10) {
2685          /* clamp */
2686          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
2687          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
2688          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
2689          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
2690
2691          for (unsigned i = 0; i < 4; i++) {
2692             if ((write_mask >> i) & 1) {
2693                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
2694                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
2695                                     values[i]);
2696                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
2697                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
2698                                     values[i]);
2699             }
2700          }
2701       }
2702       break;
2703
2704    case V_028714_SPI_SHADER_32_ABGR:
2705       enabled_channels = 0xF;
2706       break;
2707
2708    default:
2709       break;
2710    }
2711
2712    if (target == V_008DFC_SQ_EXP_NULL)
2713       return;
2714
2715    if ((bool) compr_op) {
2716       for (int i = 0; i < 2; i++) {
2717          /* check if at least one of the values to be compressed is enabled */
2718          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
2719          if (enabled) {
2720             enabled_channels |= enabled << (i*2);
2721             values[i] = bld.vop3(compr_op, bld.def(v1),
2722                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
2723                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
2724          } else {
2725             values[i] = Operand(v1);
2726          }
2727       }
2728       values[2] = Operand(v1);
2729       values[3] = Operand(v1);
2730    } else {
2731       for (int i = 0; i < 4; i++)
2732          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
2733    }
2734
2735    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
2736            enabled_channels, target, (bool) compr_op);
2737 }
2738
2739 Operand load_lds_size_m0(isel_context *ctx)
2740 {
2741    /* TODO: m0 does not need to be initialized on GFX9+ */
2742    Builder bld(ctx->program, ctx->block);
2743    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2744 }
2745
2746 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2747               Temp address, unsigned base_offset, unsigned align)
2748 {
2749    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2750
2751    Builder bld(ctx->program, ctx->block);
2752
2753    Operand m = load_lds_size_m0(ctx);
2754
2755    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2756    unsigned bytes_read = 0;
2757    unsigned result_size = 0;
2758    unsigned total_bytes = num_components * elem_size_bytes;
2759    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2760
2761    while (bytes_read < total_bytes) {
2762       unsigned todo = total_bytes - bytes_read;
2763       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2764       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2765
2766       aco_opcode op = aco_opcode::last_opcode;
2767       bool read2 = false;
2768       if (todo >= 16 && aligned16) {
2769          op = aco_opcode::ds_read_b128;
2770          todo = 16;
2771       } else if (todo >= 16 && aligned8) {
2772          op = aco_opcode::ds_read2_b64;
2773          read2 = true;
2774          todo = 16;
2775       } else if (todo >= 12 && aligned16) {
2776          op = aco_opcode::ds_read_b96;
2777          todo = 12;
2778       } else if (todo >= 8 && aligned8) {
2779          op = aco_opcode::ds_read_b64;
2780          todo = 8;
2781       } else if (todo >= 8) {
2782          op = aco_opcode::ds_read2_b32;
2783          read2 = true;
2784          todo = 8;
2785       } else if (todo >= 4) {
2786          op = aco_opcode::ds_read_b32;
2787          todo = 4;
2788       } else {
2789          assert(false);
2790       }
2791       assert(todo % elem_size_bytes == 0);
2792       unsigned num_elements = todo / elem_size_bytes;
2793       unsigned offset = base_offset + bytes_read;
2794       unsigned max_offset = read2 ? 1019 : 65535;
2795
2796       Temp address_offset = address;
2797       if (offset > max_offset) {
2798          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2799          offset = bytes_read;
2800       }
2801       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2802
2803       Temp res;
2804       if (num_components == 1 && dst.type() == RegType::vgpr)
2805          res = dst;
2806       else
2807          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2808
2809       if (read2)
2810          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2811       else
2812          res = bld.ds(op, Definition(res), address_offset, m, offset);
2813
2814       if (num_components == 1) {
2815          assert(todo == total_bytes);
2816          if (dst.type() == RegType::sgpr)
2817             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2818          return;
2819       }
2820
2821       if (dst.type() == RegType::sgpr)
2822          res = bld.as_uniform(res);
2823
2824       if (num_elements == 1) {
2825          result[result_size++] = res;
2826       } else {
2827          assert(res != dst && res.size() % num_elements == 0);
2828          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2829          split->operands[0] = Operand(res);
2830          for (unsigned i = 0; i < num_elements; i++)
2831             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2832          ctx->block->instructions.emplace_back(std::move(split));
2833       }
2834
2835       bytes_read += todo;
2836    }
2837
2838    assert(result_size == num_components && result_size > 1);
2839    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2840    for (unsigned i = 0; i < result_size; i++)
2841       vec->operands[i] = Operand(result[i]);
2842    vec->definitions[0] = Definition(dst);
2843    ctx->block->instructions.emplace_back(std::move(vec));
2844    ctx->allocated_vec.emplace(dst.id(), result);
2845 }
2846
2847 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2848 {
2849    if (start == 0 && size == data.size())
2850       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2851
2852    unsigned size_hint = 1;
2853    auto it = ctx->allocated_vec.find(data.id());
2854    if (it != ctx->allocated_vec.end())
2855       size_hint = it->second[0].size();
2856    if (size % size_hint || start % size_hint)
2857       size_hint = 1;
2858
2859    start /= size_hint;
2860    size /= size_hint;
2861
2862    Temp elems[size];
2863    for (unsigned i = 0; i < size; i++)
2864       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2865
2866    if (size == 1)
2867       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2868
2869    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2870    for (unsigned i = 0; i < size; i++)
2871       vec->operands[i] = Operand(elems[i]);
2872    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2873    vec->definitions[0] = Definition(res);
2874    ctx->block->instructions.emplace_back(std::move(vec));
2875    return res;
2876 }
2877
2878 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2879 {
2880    Builder bld(ctx->program, ctx->block);
2881    unsigned bytes_written = 0;
2882    while (bytes_written < total_size * 4) {
2883       unsigned todo = total_size * 4 - bytes_written;
2884       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2885       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2886
2887       aco_opcode op = aco_opcode::last_opcode;
2888       bool write2 = false;
2889       unsigned size = 0;
2890       if (todo >= 16 && aligned16) {
2891          op = aco_opcode::ds_write_b128;
2892          size = 4;
2893       } else if (todo >= 16 && aligned8) {
2894          op = aco_opcode::ds_write2_b64;
2895          write2 = true;
2896          size = 4;
2897       } else if (todo >= 12 && aligned16) {
2898          op = aco_opcode::ds_write_b96;
2899          size = 3;
2900       } else if (todo >= 8 && aligned8) {
2901          op = aco_opcode::ds_write_b64;
2902          size = 2;
2903       } else if (todo >= 8) {
2904          op = aco_opcode::ds_write2_b32;
2905          write2 = true;
2906          size = 2;
2907       } else if (todo >= 4) {
2908          op = aco_opcode::ds_write_b32;
2909          size = 1;
2910       } else {
2911          assert(false);
2912       }
2913
2914       unsigned offset = offset0 + offset1 + bytes_written;
2915       unsigned max_offset = write2 ? 1020 : 65535;
2916       Temp address_offset = address;
2917       if (offset > max_offset) {
2918          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2919          offset = offset1 + bytes_written;
2920       }
2921       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2922
2923       if (write2) {
2924          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2925          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2926          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2927       } else {
2928          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2929          bld.ds(op, address_offset, val, m, offset);
2930       }
2931
2932       bytes_written += size * 4;
2933    }
2934 }
2935
2936 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2937                Temp address, unsigned base_offset, unsigned align)
2938 {
2939    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2940
2941    Operand m = load_lds_size_m0(ctx);
2942
2943    /* we need at most two stores for 32bit variables */
2944    int start[2], count[2];
2945    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2946    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2947    assert(wrmask == 0);
2948
2949    /* one combined store is sufficient */
2950    if (count[0] == count[1]) {
2951       Builder bld(ctx->program, ctx->block);
2952
2953       Temp address_offset = address;
2954       if ((base_offset >> 2) + start[1] > 255) {
2955          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2956          base_offset = 0;
2957       }
2958
2959       assert(count[0] == 1);
2960       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2961       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2962       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2963       base_offset = base_offset / elem_size_bytes;
2964       bld.ds(op, address_offset, val0, val1, m,
2965              base_offset + start[0], base_offset + start[1]);
2966       return;
2967    }
2968
2969    for (unsigned i = 0; i < 2; i++) {
2970       if (count[i] == 0)
2971          continue;
2972
2973       unsigned elem_size_words = elem_size_bytes / 4;
2974       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2975                       base_offset, start[i] * elem_size_bytes, align);
2976    }
2977    return;
2978 }
2979
2980 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
2981 {
2982    if (ctx->stage == vertex_vs) {
2983       visit_store_vs_output(ctx, instr);
2984    } else if (ctx->stage == fragment_fs) {
2985       visit_store_fs_output(ctx, instr);
2986    } else {
2987       unreachable("Shader stage not implemented");
2988    }
2989 }
2990
2991 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
2992 {
2993    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
2994    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
2995
2996    Builder bld(ctx->program, ctx->block);
2997    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
2998    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
2999 }
3000
3001 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3002 {
3003    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3004    for (unsigned i = 0; i < num_components; i++)
3005       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3006    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3007       assert(num_components == 4);
3008       Builder bld(ctx->program, ctx->block);
3009       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3010    }
3011
3012    for (Operand& op : vec->operands)
3013       op = op.isUndefined() ? Operand(0u) : op;
3014
3015    vec->definitions[0] = Definition(dst);
3016    ctx->block->instructions.emplace_back(std::move(vec));
3017    emit_split_vector(ctx, dst, num_components);
3018    return;
3019 }
3020
3021 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3022 {
3023    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3024    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3025    unsigned idx = nir_intrinsic_base(instr);
3026    unsigned component = nir_intrinsic_component(instr);
3027    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3028
3029    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3030    if (offset) {
3031       assert(offset->u32 == 0);
3032    } else {
3033       /* the lower 15bit of the prim_mask contain the offset into LDS
3034        * while the upper bits contain the number of prims */
3035       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3036       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3037       Builder bld(ctx->program, ctx->block);
3038       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3039       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3040       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3041       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3042       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3043    }
3044
3045    if (instr->dest.ssa.num_components == 1) {
3046       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3047    } else {
3048       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3049       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3050       {
3051          Temp tmp = {ctx->program->allocateId(), v1};
3052          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3053          vec->operands[i] = Operand(tmp);
3054       }
3055       vec->definitions[0] = Definition(dst);
3056       ctx->block->instructions.emplace_back(std::move(vec));
3057    }
3058 }
3059
3060 unsigned get_num_channels_from_data_format(unsigned data_format)
3061 {
3062    switch (data_format) {
3063    case V_008F0C_BUF_DATA_FORMAT_8:
3064    case V_008F0C_BUF_DATA_FORMAT_16:
3065    case V_008F0C_BUF_DATA_FORMAT_32:
3066       return 1;
3067    case V_008F0C_BUF_DATA_FORMAT_8_8:
3068    case V_008F0C_BUF_DATA_FORMAT_16_16:
3069    case V_008F0C_BUF_DATA_FORMAT_32_32:
3070       return 2;
3071    case V_008F0C_BUF_DATA_FORMAT_10_11_11:
3072    case V_008F0C_BUF_DATA_FORMAT_11_11_10:
3073    case V_008F0C_BUF_DATA_FORMAT_32_32_32:
3074       return 3;
3075    case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
3076    case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
3077    case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
3078    case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
3079    case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
3080       return 4;
3081    default:
3082       break;
3083    }
3084
3085    return 4;
3086 }
3087
3088 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3089  * so we may need to fix it up. */
3090 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3091 {
3092    Builder bld(ctx->program, ctx->block);
3093
3094    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3095       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3096
3097    /* For the integer-like cases, do a natural sign extension.
3098     *
3099     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3100     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3101     * exponent.
3102     */
3103    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3104    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3105
3106    /* Convert back to the right type. */
3107    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3108       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3109       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3110       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3111    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3112       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3113    }
3114
3115    return alpha;
3116 }
3117
3118 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3119 {
3120    Builder bld(ctx->program, ctx->block);
3121    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3122    if (ctx->stage & sw_vs) {
3123
3124       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3125       if (off_instr->type != nir_instr_type_load_const) {
3126          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3127          nir_print_instr(off_instr, stderr);
3128          fprintf(stderr, "\n");
3129       }
3130       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3131
3132       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3133
3134       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3135       unsigned component = nir_intrinsic_component(instr);
3136       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3137       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3138       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3139       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3140
3141       unsigned dfmt = attrib_format & 0xf;
3142
3143       unsigned nfmt = (attrib_format >> 4) & 0x7;
3144       unsigned num_dfmt_channels = get_num_channels_from_data_format(dfmt);
3145       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3146       unsigned num_channels = MIN2(util_last_bit(mask), num_dfmt_channels);
3147       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3148       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3149       if (post_shuffle)
3150          num_channels = MAX2(num_channels, 3);
3151
3152       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, Operand(attrib_binding * 16u));
3153
3154       Temp index;
3155       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3156          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3157          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3158          if (divisor) {
3159             ctx->needs_instance_id = true;
3160             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3161             if (divisor != 1) {
3162                Temp divided = bld.tmp(v1);
3163                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3164                index = bld.vadd32(bld.def(v1), start_instance, divided);
3165             } else {
3166                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3167             }
3168          } else {
3169             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3170          }
3171       } else {
3172          index = bld.vadd32(bld.def(v1),
3173                             get_arg(ctx, ctx->args->ac.base_vertex),
3174                             get_arg(ctx, ctx->args->ac.vertex_id));
3175       }
3176
3177       if (attrib_stride != 0 && attrib_offset > attrib_stride) {
3178          index = bld.vadd32(bld.def(v1), Operand(attrib_offset / attrib_stride), index);
3179          attrib_offset = attrib_offset % attrib_stride;
3180       }
3181
3182       Operand soffset(0u);
3183       if (attrib_offset >= 4096) {
3184          soffset = bld.copy(bld.def(s1), Operand(attrib_offset));
3185          attrib_offset = 0;
3186       }
3187
3188       aco_opcode opcode;
3189       switch (num_channels) {
3190       case 1:
3191          opcode = aco_opcode::tbuffer_load_format_x;
3192          break;
3193       case 2:
3194          opcode = aco_opcode::tbuffer_load_format_xy;
3195          break;
3196       case 3:
3197          opcode = aco_opcode::tbuffer_load_format_xyz;
3198          break;
3199       case 4:
3200          opcode = aco_opcode::tbuffer_load_format_xyzw;
3201          break;
3202       default:
3203          unreachable("Unimplemented load_input vector size");
3204       }
3205
3206       Temp tmp = post_shuffle || num_channels != dst.size() || alpha_adjust != RADV_ALPHA_ADJUST_NONE || component ? bld.tmp(RegType::vgpr, num_channels) : dst;
3207
3208       aco_ptr<MTBUF_instruction> mubuf{create_instruction<MTBUF_instruction>(opcode, Format::MTBUF, 3, 1)};
3209       mubuf->operands[0] = Operand(index);
3210       mubuf->operands[1] = Operand(list);
3211       mubuf->operands[2] = soffset;
3212       mubuf->definitions[0] = Definition(tmp);
3213       mubuf->idxen = true;
3214       mubuf->can_reorder = true;
3215       mubuf->dfmt = dfmt;
3216       mubuf->nfmt = nfmt;
3217       assert(attrib_offset < 4096);
3218       mubuf->offset = attrib_offset;
3219       ctx->block->instructions.emplace_back(std::move(mubuf));
3220
3221       emit_split_vector(ctx, tmp, tmp.size());
3222
3223       if (tmp.id() != dst.id()) {
3224          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3225                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3226
3227          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3228          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3229          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3230
3231          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3232          for (unsigned i = 0; i < dst.size(); i++) {
3233             unsigned idx = i + component;
3234             if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE && num_channels >= 4) {
3235                Temp alpha = emit_extract_vector(ctx, tmp, swizzle[3], v1);
3236                vec->operands[3] = Operand(adjust_vertex_fetch_alpha(ctx, alpha_adjust, alpha));
3237             } else if (idx < num_channels) {
3238                vec->operands[i] = Operand(emit_extract_vector(ctx, tmp, swizzle[idx], v1));
3239             } else if (is_float && idx == 3) {
3240                vec->operands[i] = Operand(0x3f800000u);
3241             } else if (!is_float && idx == 3) {
3242                vec->operands[i] = Operand(1u);
3243             } else {
3244                vec->operands[i] = Operand(0u);
3245             }
3246          }
3247          vec->definitions[0] = Definition(dst);
3248          ctx->block->instructions.emplace_back(std::move(vec));
3249          emit_split_vector(ctx, dst, dst.size());
3250       }
3251
3252    } else if (ctx->stage == fragment_fs) {
3253       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3254       if (off_instr->type != nir_instr_type_load_const ||
3255           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3256          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3257          nir_print_instr(off_instr, stderr);
3258          fprintf(stderr, "\n");
3259       }
3260
3261       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3262       nir_const_value* offset = nir_src_as_const_value(instr->src[0]);
3263       if (offset) {
3264          assert(offset->u32 == 0);
3265       } else {
3266          /* the lower 15bit of the prim_mask contain the offset into LDS
3267           * while the upper bits contain the number of prims */
3268          Temp offset_src = get_ssa_temp(ctx, instr->src[0].ssa);
3269          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3270          Builder bld(ctx->program, ctx->block);
3271          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3272          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3273          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3274          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3275          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3276       }
3277
3278       unsigned idx = nir_intrinsic_base(instr);
3279       unsigned component = nir_intrinsic_component(instr);
3280
3281       if (dst.size() == 1) {
3282          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(2u), bld.m0(prim_mask), idx, component);
3283       } else {
3284          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3285          for (unsigned i = 0; i < dst.size(); i++)
3286             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(2u), bld.m0(prim_mask), idx, component + i);
3287          vec->definitions[0] = Definition(dst);
3288          bld.insert(std::move(vec));
3289       }
3290
3291    } else {
3292       unreachable("Shader stage not implemented");
3293    }
3294 }
3295
3296 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3297 {
3298    if (ctx->program->info->need_indirect_descriptor_sets) {
3299       Builder bld(ctx->program, ctx->block);
3300       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3301       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, Operand(desc_set << 2));//, false, false, false);
3302    }
3303
3304    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3305 }
3306
3307
3308 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3309 {
3310    Builder bld(ctx->program, ctx->block);
3311    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3312    if (!ctx->divergent_vals[instr->dest.ssa.index])
3313       index = bld.as_uniform(index);
3314    unsigned desc_set = nir_intrinsic_desc_set(instr);
3315    unsigned binding = nir_intrinsic_binding(instr);
3316
3317    Temp desc_ptr;
3318    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3319    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3320    unsigned offset = layout->binding[binding].offset;
3321    unsigned stride;
3322    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3323        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3324       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3325       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
3326       offset = pipeline_layout->push_constant_size + 16 * idx;
3327       stride = 16;
3328    } else {
3329       desc_ptr = load_desc_ptr(ctx, desc_set);
3330       stride = layout->binding[binding].size;
3331    }
3332
3333    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3334    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3335    if (stride != 1) {
3336       if (nir_const_index) {
3337          const_index = const_index * stride;
3338       } else if (index.type() == RegType::vgpr) {
3339          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3340          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3341       } else {
3342          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3343       }
3344    }
3345    if (offset) {
3346       if (nir_const_index) {
3347          const_index = const_index + offset;
3348       } else if (index.type() == RegType::vgpr) {
3349          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3350       } else {
3351          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3352       }
3353    }
3354
3355    if (nir_const_index && const_index == 0) {
3356       index = desc_ptr;
3357    } else if (index.type() == RegType::vgpr) {
3358       index = bld.vadd32(bld.def(v1),
3359                          nir_const_index ? Operand(const_index) : Operand(index),
3360                          Operand(desc_ptr));
3361    } else {
3362       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3363                        nir_const_index ? Operand(const_index) : Operand(index),
3364                        Operand(desc_ptr));
3365    }
3366
3367    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3368 }
3369
3370 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3371                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3372 {
3373    Builder bld(ctx->program, ctx->block);
3374
3375    unsigned num_bytes = dst.size() * 4;
3376    bool dlc = glc && ctx->options->chip_class >= GFX10;
3377
3378    aco_opcode op;
3379    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
3380       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3381       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3382       unsigned const_offset = 0;
3383
3384       Temp lower = Temp();
3385       if (num_bytes > 16) {
3386          assert(num_components == 3 || num_components == 4);
3387          op = aco_opcode::buffer_load_dwordx4;
3388          lower = bld.tmp(v4);
3389          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3390          mubuf->definitions[0] = Definition(lower);
3391          mubuf->operands[0] = vaddr;
3392          mubuf->operands[1] = Operand(rsrc);
3393          mubuf->operands[2] = soffset;
3394          mubuf->offen = (offset.type() == RegType::vgpr);
3395          mubuf->glc = glc;
3396          mubuf->dlc = dlc;
3397          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3398          mubuf->can_reorder = readonly;
3399          bld.insert(std::move(mubuf));
3400          emit_split_vector(ctx, lower, 2);
3401          num_bytes -= 16;
3402          const_offset = 16;
3403       }
3404
3405       switch (num_bytes) {
3406          case 4:
3407             op = aco_opcode::buffer_load_dword;
3408             break;
3409          case 8:
3410             op = aco_opcode::buffer_load_dwordx2;
3411             break;
3412          case 12:
3413             op = aco_opcode::buffer_load_dwordx3;
3414             break;
3415          case 16:
3416             op = aco_opcode::buffer_load_dwordx4;
3417             break;
3418          default:
3419             unreachable("Load SSBO not implemented for this size.");
3420       }
3421       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3422       mubuf->operands[0] = vaddr;
3423       mubuf->operands[1] = Operand(rsrc);
3424       mubuf->operands[2] = soffset;
3425       mubuf->offen = (offset.type() == RegType::vgpr);
3426       mubuf->glc = glc;
3427       mubuf->dlc = dlc;
3428       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3429       mubuf->can_reorder = readonly;
3430       mubuf->offset = const_offset;
3431       aco_ptr<Instruction> instr = std::move(mubuf);
3432
3433       if (dst.size() > 4) {
3434          assert(lower != Temp());
3435          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3436          instr->definitions[0] = Definition(upper);
3437          bld.insert(std::move(instr));
3438          if (dst.size() == 8)
3439             emit_split_vector(ctx, upper, 2);
3440          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3441          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3442          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3443          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3444          if (dst.size() == 8)
3445             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3446       }
3447
3448       if (dst.type() == RegType::sgpr) {
3449          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3450          instr->definitions[0] = Definition(vec);
3451          bld.insert(std::move(instr));
3452          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
3453       } else {
3454          instr->definitions[0] = Definition(dst);
3455          bld.insert(std::move(instr));
3456          emit_split_vector(ctx, dst, num_components);
3457       }
3458    } else {
3459       switch (num_bytes) {
3460          case 4:
3461             op = aco_opcode::s_buffer_load_dword;
3462             break;
3463          case 8:
3464             op = aco_opcode::s_buffer_load_dwordx2;
3465             break;
3466          case 12:
3467          case 16:
3468             op = aco_opcode::s_buffer_load_dwordx4;
3469             break;
3470          case 24:
3471          case 32:
3472             op = aco_opcode::s_buffer_load_dwordx8;
3473             break;
3474          default:
3475             unreachable("Load SSBO not implemented for this size.");
3476       }
3477       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3478       load->operands[0] = Operand(rsrc);
3479       load->operands[1] = Operand(bld.as_uniform(offset));
3480       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3481       load->definitions[0] = Definition(dst);
3482       load->glc = glc;
3483       load->dlc = dlc;
3484       load->barrier = readonly ? barrier_none : barrier_buffer;
3485       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3486       assert(ctx->options->chip_class >= GFX8 || !glc);
3487
3488       /* trim vector */
3489       if (dst.size() == 3) {
3490          Temp vec = bld.tmp(s4);
3491          load->definitions[0] = Definition(vec);
3492          bld.insert(std::move(load));
3493          emit_split_vector(ctx, vec, 4);
3494
3495          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3496                     emit_extract_vector(ctx, vec, 0, s1),
3497                     emit_extract_vector(ctx, vec, 1, s1),
3498                     emit_extract_vector(ctx, vec, 2, s1));
3499       } else if (dst.size() == 6) {
3500          Temp vec = bld.tmp(s8);
3501          load->definitions[0] = Definition(vec);
3502          bld.insert(std::move(load));
3503          emit_split_vector(ctx, vec, 4);
3504
3505          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3506                     emit_extract_vector(ctx, vec, 0, s2),
3507                     emit_extract_vector(ctx, vec, 1, s2),
3508                     emit_extract_vector(ctx, vec, 2, s2));
3509       } else {
3510          bld.insert(std::move(load));
3511       }
3512       emit_split_vector(ctx, dst, num_components);
3513    }
3514 }
3515
3516 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
3517 {
3518    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3519    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
3520
3521    Builder bld(ctx->program, ctx->block);
3522
3523    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3524    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
3525    unsigned binding = nir_intrinsic_binding(idx_instr);
3526    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3527
3528    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
3529       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3530                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3531                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3532                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3533       if (ctx->options->chip_class >= GFX10) {
3534          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3535                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3536                       S_008F0C_RESOURCE_LEVEL(1);
3537       } else {
3538          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3539                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3540       }
3541       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
3542                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
3543                                      Operand(0xFFFFFFFFu),
3544                                      Operand(desc_type));
3545       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3546                         rsrc, upper_dwords);
3547    } else {
3548       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
3549       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
3550    }
3551
3552    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
3553 }
3554
3555 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3556 {
3557    Builder bld(ctx->program, ctx->block);
3558    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3559
3560    unsigned offset = nir_intrinsic_base(instr);
3561    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
3562    if (index_cv && instr->dest.ssa.bit_size == 32) {
3563
3564       unsigned count = instr->dest.ssa.num_components;
3565       unsigned start = (offset + index_cv->u32) / 4u;
3566       start -= ctx->args->ac.base_inline_push_consts;
3567       if (start + count <= ctx->args->ac.num_inline_push_consts) {
3568          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3569          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
3570          for (unsigned i = 0; i < count; ++i) {
3571             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
3572             vec->operands[i] = Operand{elems[i]};
3573          }
3574          vec->definitions[0] = Definition(dst);
3575          ctx->block->instructions.emplace_back(std::move(vec));
3576          ctx->allocated_vec.emplace(dst.id(), elems);
3577          return;
3578       }
3579    }
3580
3581    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
3582    if (offset != 0) // TODO check if index != 0 as well
3583       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
3584    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
3585    Temp vec = dst;
3586    bool trim = false;
3587    aco_opcode op;
3588
3589    switch (dst.size()) {
3590    case 1:
3591       op = aco_opcode::s_load_dword;
3592       break;
3593    case 2:
3594       op = aco_opcode::s_load_dwordx2;
3595       break;
3596    case 3:
3597       vec = bld.tmp(s4);
3598       trim = true;
3599    case 4:
3600       op = aco_opcode::s_load_dwordx4;
3601       break;
3602    case 6:
3603       vec = bld.tmp(s8);
3604       trim = true;
3605    case 8:
3606       op = aco_opcode::s_load_dwordx8;
3607       break;
3608    default:
3609       unreachable("unimplemented or forbidden load_push_constant.");
3610    }
3611
3612    bld.smem(op, Definition(vec), ptr, index);
3613
3614    if (trim) {
3615       emit_split_vector(ctx, vec, 4);
3616       RegClass rc = dst.size() == 3 ? s1 : s2;
3617       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3618                  emit_extract_vector(ctx, vec, 0, rc),
3619                  emit_extract_vector(ctx, vec, 1, rc),
3620                  emit_extract_vector(ctx, vec, 2, rc));
3621
3622    }
3623    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
3624 }
3625
3626 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3627 {
3628    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3629
3630    Builder bld(ctx->program, ctx->block);
3631
3632    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3633                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3634                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3635                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3636    if (ctx->options->chip_class >= GFX10) {
3637       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3638                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3639                    S_008F0C_RESOURCE_LEVEL(1);
3640    } else {
3641       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3642                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3643    }
3644
3645    unsigned base = nir_intrinsic_base(instr);
3646    unsigned range = nir_intrinsic_range(instr);
3647
3648    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
3649    if (base && offset.type() == RegType::sgpr)
3650       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
3651    else if (base && offset.type() == RegType::vgpr)
3652       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
3653
3654    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3655                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
3656                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
3657                           Operand(desc_type));
3658
3659    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
3660 }
3661
3662 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
3663 {
3664    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3665       ctx->cf_info.exec_potentially_empty = true;
3666
3667    ctx->program->needs_exact = true;
3668
3669    // TODO: optimize uniform conditions
3670    Builder bld(ctx->program, ctx->block);
3671    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3672    assert(src.regClass() == bld.lm);
3673    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
3674    bld.pseudo(aco_opcode::p_discard_if, src);
3675    ctx->block->kind |= block_kind_uses_discard_if;
3676    return;
3677 }
3678
3679 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
3680 {
3681    Builder bld(ctx->program, ctx->block);
3682
3683    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3684       ctx->cf_info.exec_potentially_empty = true;
3685
3686    bool divergent = ctx->cf_info.parent_if.is_divergent ||
3687                     ctx->cf_info.parent_loop.has_divergent_continue;
3688
3689    if (ctx->block->loop_nest_depth &&
3690        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
3691       /* we handle discards the same way as jump instructions */
3692       append_logical_end(ctx->block);
3693
3694       /* in loops, discard behaves like break */
3695       Block *linear_target = ctx->cf_info.parent_loop.exit;
3696       ctx->block->kind |= block_kind_discard;
3697
3698       if (!divergent) {
3699          /* uniform discard - loop ends here */
3700          assert(nir_instr_is_last(&instr->instr));
3701          ctx->block->kind |= block_kind_uniform;
3702          ctx->cf_info.has_branch = true;
3703          bld.branch(aco_opcode::p_branch);
3704          add_linear_edge(ctx->block->index, linear_target);
3705          return;
3706       }
3707
3708       /* we add a break right behind the discard() instructions */
3709       ctx->block->kind |= block_kind_break;
3710       unsigned idx = ctx->block->index;
3711
3712       /* remove critical edges from linear CFG */
3713       bld.branch(aco_opcode::p_branch);
3714       Block* break_block = ctx->program->create_and_insert_block();
3715       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3716       break_block->kind |= block_kind_uniform;
3717       add_linear_edge(idx, break_block);
3718       add_linear_edge(break_block->index, linear_target);
3719       bld.reset(break_block);
3720       bld.branch(aco_opcode::p_branch);
3721
3722       Block* continue_block = ctx->program->create_and_insert_block();
3723       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3724       add_linear_edge(idx, continue_block);
3725       append_logical_start(continue_block);
3726       ctx->block = continue_block;
3727
3728       return;
3729    }
3730
3731    /* it can currently happen that NIR doesn't remove the unreachable code */
3732    if (!nir_instr_is_last(&instr->instr)) {
3733       ctx->program->needs_exact = true;
3734       /* save exec somewhere temporarily so that it doesn't get
3735        * overwritten before the discard from outer exec masks */
3736       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
3737       bld.pseudo(aco_opcode::p_discard_if, cond);
3738       ctx->block->kind |= block_kind_uses_discard_if;
3739       return;
3740    }
3741
3742    /* This condition is incorrect for uniformly branched discards in a loop
3743     * predicated by a divergent condition, but the above code catches that case
3744     * and the discard would end up turning into a discard_if.
3745     * For example:
3746     * if (divergent) {
3747     *    while (...) {
3748     *       if (uniform) {
3749     *          discard;
3750     *       }
3751     *    }
3752     * }
3753     */
3754    if (!ctx->cf_info.parent_if.is_divergent) {
3755       /* program just ends here */
3756       ctx->block->kind |= block_kind_uniform;
3757       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
3758               0 /* enabled mask */, 9 /* dest */,
3759               false /* compressed */, true/* done */, true /* valid mask */);
3760       bld.sopp(aco_opcode::s_endpgm);
3761       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3762    } else {
3763       ctx->block->kind |= block_kind_discard;
3764       /* branch and linear edge is added by visit_if() */
3765    }
3766 }
3767
3768 enum aco_descriptor_type {
3769    ACO_DESC_IMAGE,
3770    ACO_DESC_FMASK,
3771    ACO_DESC_SAMPLER,
3772    ACO_DESC_BUFFER,
3773    ACO_DESC_PLANE_0,
3774    ACO_DESC_PLANE_1,
3775    ACO_DESC_PLANE_2,
3776 };
3777
3778 static bool
3779 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
3780    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
3781       return false;
3782    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
3783    return dim == ac_image_cube ||
3784           dim == ac_image_1darray ||
3785           dim == ac_image_2darray ||
3786           dim == ac_image_2darraymsaa;
3787 }
3788
3789 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
3790                       enum aco_descriptor_type desc_type,
3791                       const nir_tex_instr *tex_instr, bool image, bool write)
3792 {
3793 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3794    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3795    if (it != ctx->tex_desc.end())
3796       return it->second;
3797 */
3798    Temp index = Temp();
3799    bool index_set = false;
3800    unsigned constant_index = 0;
3801    unsigned descriptor_set;
3802    unsigned base_index;
3803    Builder bld(ctx->program, ctx->block);
3804
3805    if (!deref_instr) {
3806       assert(tex_instr && !image);
3807       descriptor_set = 0;
3808       base_index = tex_instr->sampler_index;
3809    } else {
3810       while(deref_instr->deref_type != nir_deref_type_var) {
3811          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
3812          if (!array_size)
3813             array_size = 1;
3814
3815          assert(deref_instr->deref_type == nir_deref_type_array);
3816          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
3817          if (const_value) {
3818             constant_index += array_size * const_value->u32;
3819          } else {
3820             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
3821             if (indirect.type() == RegType::vgpr)
3822                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
3823
3824             if (array_size != 1)
3825                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
3826
3827             if (!index_set) {
3828                index = indirect;
3829                index_set = true;
3830             } else {
3831                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
3832             }
3833          }
3834
3835          deref_instr = nir_src_as_deref(deref_instr->parent);
3836       }
3837       descriptor_set = deref_instr->var->data.descriptor_set;
3838       base_index = deref_instr->var->data.binding;
3839    }
3840
3841    Temp list = load_desc_ptr(ctx, descriptor_set);
3842    list = convert_pointer_to_64_bit(ctx, list);
3843
3844    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
3845    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
3846    unsigned offset = binding->offset;
3847    unsigned stride = binding->size;
3848    aco_opcode opcode;
3849    RegClass type;
3850
3851    assert(base_index < layout->binding_count);
3852
3853    switch (desc_type) {
3854    case ACO_DESC_IMAGE:
3855       type = s8;
3856       opcode = aco_opcode::s_load_dwordx8;
3857       break;
3858    case ACO_DESC_FMASK:
3859       type = s8;
3860       opcode = aco_opcode::s_load_dwordx8;
3861       offset += 32;
3862       break;
3863    case ACO_DESC_SAMPLER:
3864       type = s4;
3865       opcode = aco_opcode::s_load_dwordx4;
3866       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3867          offset += radv_combined_image_descriptor_sampler_offset(binding);
3868       break;
3869    case ACO_DESC_BUFFER:
3870       type = s4;
3871       opcode = aco_opcode::s_load_dwordx4;
3872       break;
3873    case ACO_DESC_PLANE_0:
3874    case ACO_DESC_PLANE_1:
3875       type = s8;
3876       opcode = aco_opcode::s_load_dwordx8;
3877       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
3878       break;
3879    case ACO_DESC_PLANE_2:
3880       type = s4;
3881       opcode = aco_opcode::s_load_dwordx4;
3882       offset += 64;
3883       break;
3884    default:
3885       unreachable("invalid desc_type\n");
3886    }
3887
3888    offset += constant_index * stride;
3889
3890    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
3891       (!index_set || binding->immutable_samplers_equal)) {
3892       if (binding->immutable_samplers_equal)
3893          constant_index = 0;
3894
3895       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3896       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3897                         Operand(samplers[constant_index * 4 + 0]),
3898                         Operand(samplers[constant_index * 4 + 1]),
3899                         Operand(samplers[constant_index * 4 + 2]),
3900                         Operand(samplers[constant_index * 4 + 3]));
3901    }
3902
3903    Operand off;
3904    if (!index_set) {
3905       off = Operand(offset);
3906    } else {
3907       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
3908                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
3909    }
3910
3911    Temp res = bld.smem(opcode, bld.def(type), list, off);
3912
3913    if (desc_type == ACO_DESC_PLANE_2) {
3914       Temp components[8];
3915       for (unsigned i = 0; i < 8; i++)
3916          components[i] = bld.tmp(s1);
3917       bld.pseudo(aco_opcode::p_split_vector,
3918                  Definition(components[0]),
3919                  Definition(components[1]),
3920                  Definition(components[2]),
3921                  Definition(components[3]),
3922                  res);
3923
3924       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
3925       bld.pseudo(aco_opcode::p_split_vector,
3926                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
3927                  Definition(components[4]),
3928                  Definition(components[5]),
3929                  Definition(components[6]),
3930                  Definition(components[7]),
3931                  desc2);
3932
3933       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
3934                        components[0], components[1], components[2], components[3],
3935                        components[4], components[5], components[6], components[7]);
3936    }
3937
3938    return res;
3939 }
3940
3941 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3942 {
3943    switch (dim) {
3944    case GLSL_SAMPLER_DIM_BUF:
3945       return 1;
3946    case GLSL_SAMPLER_DIM_1D:
3947       return array ? 2 : 1;
3948    case GLSL_SAMPLER_DIM_2D:
3949       return array ? 3 : 2;
3950    case GLSL_SAMPLER_DIM_MS:
3951       return array ? 4 : 3;
3952    case GLSL_SAMPLER_DIM_3D:
3953    case GLSL_SAMPLER_DIM_CUBE:
3954       return 3;
3955    case GLSL_SAMPLER_DIM_RECT:
3956    case GLSL_SAMPLER_DIM_SUBPASS:
3957       return 2;
3958    case GLSL_SAMPLER_DIM_SUBPASS_MS:
3959       return 3;
3960    default:
3961       break;
3962    }
3963    return 0;
3964 }
3965
3966
3967 /* Adjust the sample index according to FMASK.
3968  *
3969  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3970  * which is the identity mapping. Each nibble says which physical sample
3971  * should be fetched to get that sample.
3972  *
3973  * For example, 0x11111100 means there are only 2 samples stored and
3974  * the second sample covers 3/4 of the pixel. When reading samples 0
3975  * and 1, return physical sample 0 (determined by the first two 0s
3976  * in FMASK), otherwise return physical sample 1.
3977  *
3978  * The sample index should be adjusted as follows:
3979  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
3980  */
3981 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, Temp coords, Operand sample_index, Temp fmask_desc_ptr)
3982 {
3983    Builder bld(ctx->program, ctx->block);
3984    Temp fmask = bld.tmp(v1);
3985    unsigned dim = ctx->options->chip_class >= GFX10
3986                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
3987                   : 0;
3988
3989    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
3990    load->operands[0] = Operand(coords);
3991    load->operands[1] = Operand(fmask_desc_ptr);
3992    load->definitions[0] = Definition(fmask);
3993    load->glc = false;
3994    load->dlc = false;
3995    load->dmask = 0x1;
3996    load->unrm = true;
3997    load->da = da;
3998    load->dim = dim;
3999    load->can_reorder = true; /* fmask images shouldn't be modified */
4000    ctx->block->instructions.emplace_back(std::move(load));
4001
4002    Operand sample_index4;
4003    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4004       sample_index4 = Operand(sample_index.constantValue() << 2);
4005    } else if (sample_index.regClass() == s1) {
4006       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4007    } else {
4008       assert(sample_index.regClass() == v1);
4009       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4010    }
4011
4012    Temp final_sample;
4013    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4014       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4015    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4016       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4017    else
4018       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4019
4020    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4021     * resource descriptor is 0 (invalid),
4022     */
4023    Temp compare = bld.tmp(bld.lm);
4024    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4025                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4026
4027    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4028
4029    /* Replace the MSAA sample index. */
4030    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4031 }
4032
4033 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4034 {
4035
4036    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4037    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4038    bool is_array = glsl_sampler_type_is_array(type);
4039    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4040    assert(!add_frag_pos && "Input attachments should be lowered.");
4041    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4042    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4043    int count = image_type_to_components_count(dim, is_array);
4044    std::vector<Operand> coords(count);
4045
4046    if (is_ms) {
4047       Operand sample_index;
4048       nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4049       if (sample_cv)
4050          sample_index = Operand(sample_cv->u32);
4051       else
4052          sample_index = Operand(emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[2].ssa), 0, v1));
4053
4054       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4055          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, is_array ? 3 : 2, 1)};
4056          for (unsigned i = 0; i < vec->operands.size(); i++)
4057             vec->operands[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
4058          Temp fmask_load_address = {ctx->program->allocateId(), is_array ? v3 : v2};
4059          vec->definitions[0] = Definition(fmask_load_address);
4060          ctx->block->instructions.emplace_back(std::move(vec));
4061
4062          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4063          sample_index = Operand(adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr));
4064       }
4065       count--;
4066       coords[count] = sample_index;
4067    }
4068
4069    if (count == 1 && !gfx9_1d)
4070       return emit_extract_vector(ctx, src0, 0, v1);
4071
4072    if (gfx9_1d) {
4073       coords[0] = Operand(emit_extract_vector(ctx, src0, 0, v1));
4074       coords.resize(coords.size() + 1);
4075       coords[1] = Operand((uint32_t) 0);
4076       if (is_array)
4077          coords[2] = Operand(emit_extract_vector(ctx, src0, 1, v1));
4078    } else {
4079       for (int i = 0; i < count; i++)
4080          coords[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
4081    }
4082
4083    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4084        instr->intrinsic == nir_intrinsic_image_deref_store) {
4085       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4086       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4087
4088       if (!level_zero)
4089          coords.emplace_back(Operand(get_ssa_temp(ctx, instr->src[lod_index].ssa)));
4090    }
4091
4092    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4093    for (unsigned i = 0; i < coords.size(); i++)
4094       vec->operands[i] = coords[i];
4095    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4096    vec->definitions[0] = Definition(res);
4097    ctx->block->instructions.emplace_back(std::move(vec));
4098    return res;
4099 }
4100
4101
4102 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4103 {
4104    Builder bld(ctx->program, ctx->block);
4105    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4106    const struct glsl_type *type = glsl_without_array(var->type);
4107    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4108    bool is_array = glsl_sampler_type_is_array(type);
4109    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4110
4111    if (dim == GLSL_SAMPLER_DIM_BUF) {
4112       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4113       unsigned num_channels = util_last_bit(mask);
4114       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4115       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4116
4117       aco_opcode opcode;
4118       switch (num_channels) {
4119       case 1:
4120          opcode = aco_opcode::buffer_load_format_x;
4121          break;
4122       case 2:
4123          opcode = aco_opcode::buffer_load_format_xy;
4124          break;
4125       case 3:
4126          opcode = aco_opcode::buffer_load_format_xyz;
4127          break;
4128       case 4:
4129          opcode = aco_opcode::buffer_load_format_xyzw;
4130          break;
4131       default:
4132          unreachable(">4 channel buffer image load");
4133       }
4134       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4135       load->operands[0] = Operand(vindex);
4136       load->operands[1] = Operand(rsrc);
4137       load->operands[2] = Operand((uint32_t) 0);
4138       Temp tmp;
4139       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4140          tmp = dst;
4141       else
4142          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4143       load->definitions[0] = Definition(tmp);
4144       load->idxen = true;
4145       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4146       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4147       load->barrier = barrier_image;
4148       ctx->block->instructions.emplace_back(std::move(load));
4149
4150       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4151       return;
4152    }
4153
4154    Temp coords = get_image_coords(ctx, instr, type);
4155    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4156
4157    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4158    unsigned num_components = util_bitcount(dmask);
4159    Temp tmp;
4160    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4161       tmp = dst;
4162    else
4163       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4164
4165    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4166    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4167
4168    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 2, 1)};
4169    load->operands[0] = Operand(coords);
4170    load->operands[1] = Operand(resource);
4171    load->definitions[0] = Definition(tmp);
4172    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4173    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4174    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4175    load->dmask = dmask;
4176    load->unrm = true;
4177    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4178    load->barrier = barrier_image;
4179    ctx->block->instructions.emplace_back(std::move(load));
4180
4181    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4182    return;
4183 }
4184
4185 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4186 {
4187    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4188    const struct glsl_type *type = glsl_without_array(var->type);
4189    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4190    bool is_array = glsl_sampler_type_is_array(type);
4191    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4192
4193    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4194
4195    if (dim == GLSL_SAMPLER_DIM_BUF) {
4196       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4197       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4198       aco_opcode opcode;
4199       switch (data.size()) {
4200       case 1:
4201          opcode = aco_opcode::buffer_store_format_x;
4202          break;
4203       case 2:
4204          opcode = aco_opcode::buffer_store_format_xy;
4205          break;
4206       case 3:
4207          opcode = aco_opcode::buffer_store_format_xyz;
4208          break;
4209       case 4:
4210          opcode = aco_opcode::buffer_store_format_xyzw;
4211          break;
4212       default:
4213          unreachable(">4 channel buffer image store");
4214       }
4215       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4216       store->operands[0] = Operand(vindex);
4217       store->operands[1] = Operand(rsrc);
4218       store->operands[2] = Operand((uint32_t) 0);
4219       store->operands[3] = Operand(data);
4220       store->idxen = true;
4221       store->glc = glc;
4222       store->dlc = false;
4223       store->disable_wqm = true;
4224       store->barrier = barrier_image;
4225       ctx->program->needs_exact = true;
4226       ctx->block->instructions.emplace_back(std::move(store));
4227       return;
4228    }
4229
4230    assert(data.type() == RegType::vgpr);
4231    Temp coords = get_image_coords(ctx, instr, type);
4232    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4233
4234    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4235    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4236
4237    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 4, 0)};
4238    store->operands[0] = Operand(coords);
4239    store->operands[1] = Operand(resource);
4240    store->operands[2] = Operand(s4);
4241    store->operands[3] = Operand(data);
4242    store->glc = glc;
4243    store->dlc = false;
4244    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4245    store->dmask = (1 << data.size()) - 1;
4246    store->unrm = true;
4247    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4248    store->disable_wqm = true;
4249    store->barrier = barrier_image;
4250    ctx->program->needs_exact = true;
4251    ctx->block->instructions.emplace_back(std::move(store));
4252    return;
4253 }
4254
4255 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4256 {
4257    /* return the previous value if dest is ever used */
4258    bool return_previous = false;
4259    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4260       return_previous = true;
4261       break;
4262    }
4263    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4264       return_previous = true;
4265       break;
4266    }
4267
4268    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4269    const struct glsl_type *type = glsl_without_array(var->type);
4270    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4271    bool is_array = glsl_sampler_type_is_array(type);
4272    Builder bld(ctx->program, ctx->block);
4273
4274    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4275    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4276
4277    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4278       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4279
4280    aco_opcode buf_op, image_op;
4281    switch (instr->intrinsic) {
4282       case nir_intrinsic_image_deref_atomic_add:
4283          buf_op = aco_opcode::buffer_atomic_add;
4284          image_op = aco_opcode::image_atomic_add;
4285          break;
4286       case nir_intrinsic_image_deref_atomic_umin:
4287          buf_op = aco_opcode::buffer_atomic_umin;
4288          image_op = aco_opcode::image_atomic_umin;
4289          break;
4290       case nir_intrinsic_image_deref_atomic_imin:
4291          buf_op = aco_opcode::buffer_atomic_smin;
4292          image_op = aco_opcode::image_atomic_smin;
4293          break;
4294       case nir_intrinsic_image_deref_atomic_umax:
4295          buf_op = aco_opcode::buffer_atomic_umax;
4296          image_op = aco_opcode::image_atomic_umax;
4297          break;
4298       case nir_intrinsic_image_deref_atomic_imax:
4299          buf_op = aco_opcode::buffer_atomic_smax;
4300          image_op = aco_opcode::image_atomic_smax;
4301          break;
4302       case nir_intrinsic_image_deref_atomic_and:
4303          buf_op = aco_opcode::buffer_atomic_and;
4304          image_op = aco_opcode::image_atomic_and;
4305          break;
4306       case nir_intrinsic_image_deref_atomic_or:
4307          buf_op = aco_opcode::buffer_atomic_or;
4308          image_op = aco_opcode::image_atomic_or;
4309          break;
4310       case nir_intrinsic_image_deref_atomic_xor:
4311          buf_op = aco_opcode::buffer_atomic_xor;
4312          image_op = aco_opcode::image_atomic_xor;
4313          break;
4314       case nir_intrinsic_image_deref_atomic_exchange:
4315          buf_op = aco_opcode::buffer_atomic_swap;
4316          image_op = aco_opcode::image_atomic_swap;
4317          break;
4318       case nir_intrinsic_image_deref_atomic_comp_swap:
4319          buf_op = aco_opcode::buffer_atomic_cmpswap;
4320          image_op = aco_opcode::image_atomic_cmpswap;
4321          break;
4322       default:
4323          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4324    }
4325
4326    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4327
4328    if (dim == GLSL_SAMPLER_DIM_BUF) {
4329       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4330       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4331       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4332       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4333       mubuf->operands[0] = Operand(vindex);
4334       mubuf->operands[1] = Operand(resource);
4335       mubuf->operands[2] = Operand((uint32_t)0);
4336       mubuf->operands[3] = Operand(data);
4337       if (return_previous)
4338          mubuf->definitions[0] = Definition(dst);
4339       mubuf->offset = 0;
4340       mubuf->idxen = true;
4341       mubuf->glc = return_previous;
4342       mubuf->dlc = false; /* Not needed for atomics */
4343       mubuf->disable_wqm = true;
4344       mubuf->barrier = barrier_image;
4345       ctx->program->needs_exact = true;
4346       ctx->block->instructions.emplace_back(std::move(mubuf));
4347       return;
4348    }
4349
4350    Temp coords = get_image_coords(ctx, instr, type);
4351    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4352    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 4, return_previous ? 1 : 0)};
4353    mimg->operands[0] = Operand(coords);
4354    mimg->operands[1] = Operand(resource);
4355    mimg->operands[2] = Operand(s4); /* no sampler */
4356    mimg->operands[3] = Operand(data);
4357    if (return_previous)
4358       mimg->definitions[0] = Definition(dst);
4359    mimg->glc = return_previous;
4360    mimg->dlc = false; /* Not needed for atomics */
4361    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4362    mimg->dmask = (1 << data.size()) - 1;
4363    mimg->unrm = true;
4364    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4365    mimg->disable_wqm = true;
4366    mimg->barrier = barrier_image;
4367    ctx->program->needs_exact = true;
4368    ctx->block->instructions.emplace_back(std::move(mimg));
4369    return;
4370 }
4371
4372 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4373 {
4374    if (in_elements && ctx->options->chip_class == GFX8) {
4375       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
4376       Builder bld(ctx->program, ctx->block);
4377
4378       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4379
4380       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
4381       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
4382
4383       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4384       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4385
4386       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
4387       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
4388
4389       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
4390       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
4391                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
4392       if (dst.type() == RegType::vgpr)
4393          bld.copy(Definition(dst), shr_dst);
4394
4395       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
4396    } else {
4397       emit_extract_vector(ctx, desc, 2, dst);
4398    }
4399 }
4400
4401 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4402 {
4403    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4404    const struct glsl_type *type = glsl_without_array(var->type);
4405    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4406    bool is_array = glsl_sampler_type_is_array(type);
4407    Builder bld(ctx->program, ctx->block);
4408
4409    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4410       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4411       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4412    }
4413
4414    /* LOD */
4415    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4416
4417    /* Resource */
4418    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4419
4420    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4421
4422    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1)};
4423    mimg->operands[0] = Operand(lod);
4424    mimg->operands[1] = Operand(resource);
4425    uint8_t& dmask = mimg->dmask;
4426    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4427    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4428    mimg->da = glsl_sampler_type_is_array(type);
4429    mimg->can_reorder = true;
4430    Definition& def = mimg->definitions[0];
4431    ctx->block->instructions.emplace_back(std::move(mimg));
4432
4433    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4434        glsl_sampler_type_is_array(type)) {
4435
4436       assert(instr->dest.ssa.num_components == 3);
4437       Temp tmp = {ctx->program->allocateId(), v3};
4438       def = Definition(tmp);
4439       emit_split_vector(ctx, tmp, 3);
4440
4441       /* divide 3rd value by 6 by multiplying with magic number */
4442       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4443       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4444
4445       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4446                  emit_extract_vector(ctx, tmp, 0, v1),
4447                  emit_extract_vector(ctx, tmp, 1, v1),
4448                  by_6);
4449
4450    } else if (ctx->options->chip_class == GFX9 &&
4451               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4452               glsl_sampler_type_is_array(type)) {
4453       assert(instr->dest.ssa.num_components == 2);
4454       def = Definition(dst);
4455       dmask = 0x5;
4456    } else {
4457       def = Definition(dst);
4458    }
4459
4460    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4461 }
4462
4463 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4464 {
4465    Builder bld(ctx->program, ctx->block);
4466    unsigned num_components = instr->num_components;
4467
4468    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4469    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4470    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4471
4472    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4473    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4474 }
4475
4476 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4477 {
4478    Builder bld(ctx->program, ctx->block);
4479    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4480    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4481    unsigned writemask = nir_intrinsic_write_mask(instr);
4482    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
4483
4484    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4485    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4486
4487    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4488                ctx->options->chip_class >= GFX8;
4489    if (smem)
4490       offset = bld.as_uniform(offset);
4491    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4492
4493    while (writemask) {
4494       int start, count;
4495       u_bit_scan_consecutive_range(&writemask, &start, &count);
4496       if (count == 3 && smem) {
4497          writemask |= 1u << (start + 2);
4498          count = 2;
4499       }
4500       int num_bytes = count * elem_size_bytes;
4501
4502       if (num_bytes > 16) {
4503          assert(elem_size_bytes == 8);
4504          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4505          count = 2;
4506          num_bytes = 16;
4507       }
4508
4509       // TODO: check alignment of sub-dword stores
4510       // TODO: split 3 bytes. there is no store instruction for that
4511
4512       Temp write_data;
4513       if (count != instr->num_components) {
4514          emit_split_vector(ctx, data, instr->num_components);
4515          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4516          for (int i = 0; i < count; i++) {
4517             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
4518             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
4519          }
4520          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
4521          vec->definitions[0] = Definition(write_data);
4522          ctx->block->instructions.emplace_back(std::move(vec));
4523       } else if (!smem && data.type() != RegType::vgpr) {
4524          assert(num_bytes % 4 == 0);
4525          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
4526       } else if (smem_nonfs && data.type() == RegType::vgpr) {
4527          assert(num_bytes % 4 == 0);
4528          write_data = bld.as_uniform(data);
4529       } else {
4530          write_data = data;
4531       }
4532
4533       aco_opcode vmem_op, smem_op;
4534       switch (num_bytes) {
4535          case 4:
4536             vmem_op = aco_opcode::buffer_store_dword;
4537             smem_op = aco_opcode::s_buffer_store_dword;
4538             break;
4539          case 8:
4540             vmem_op = aco_opcode::buffer_store_dwordx2;
4541             smem_op = aco_opcode::s_buffer_store_dwordx2;
4542             break;
4543          case 12:
4544             vmem_op = aco_opcode::buffer_store_dwordx3;
4545             smem_op = aco_opcode::last_opcode;
4546             assert(!smem);
4547             break;
4548          case 16:
4549             vmem_op = aco_opcode::buffer_store_dwordx4;
4550             smem_op = aco_opcode::s_buffer_store_dwordx4;
4551             break;
4552          default:
4553             unreachable("Store SSBO not implemented for this size.");
4554       }
4555       if (ctx->stage == fragment_fs)
4556          smem_op = aco_opcode::p_fs_buffer_store_smem;
4557
4558       if (smem) {
4559          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
4560          store->operands[0] = Operand(rsrc);
4561          if (start) {
4562             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4563                                 offset, Operand(start * elem_size_bytes));
4564             store->operands[1] = Operand(off);
4565          } else {
4566             store->operands[1] = Operand(offset);
4567          }
4568          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
4569             store->operands[1].setFixed(m0);
4570          store->operands[2] = Operand(write_data);
4571          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4572          store->dlc = false;
4573          store->disable_wqm = true;
4574          store->barrier = barrier_buffer;
4575          ctx->block->instructions.emplace_back(std::move(store));
4576          ctx->program->wb_smem_l1_on_end = true;
4577          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
4578             ctx->block->kind |= block_kind_needs_lowering;
4579             ctx->program->needs_exact = true;
4580          }
4581       } else {
4582          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
4583          store->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4584          store->operands[1] = Operand(rsrc);
4585          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4586          store->operands[3] = Operand(write_data);
4587          store->offset = start * elem_size_bytes;
4588          store->offen = (offset.type() == RegType::vgpr);
4589          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4590          store->dlc = false;
4591          store->disable_wqm = true;
4592          store->barrier = barrier_buffer;
4593          ctx->program->needs_exact = true;
4594          ctx->block->instructions.emplace_back(std::move(store));
4595       }
4596    }
4597 }
4598
4599 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4600 {
4601    /* return the previous value if dest is ever used */
4602    bool return_previous = false;
4603    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4604       return_previous = true;
4605       break;
4606    }
4607    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4608       return_previous = true;
4609       break;
4610    }
4611
4612    Builder bld(ctx->program, ctx->block);
4613    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
4614
4615    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
4616       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4617                         get_ssa_temp(ctx, instr->src[3].ssa), data);
4618
4619    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
4620    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4621    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4622
4623    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4624
4625    aco_opcode op32, op64;
4626    switch (instr->intrinsic) {
4627       case nir_intrinsic_ssbo_atomic_add:
4628          op32 = aco_opcode::buffer_atomic_add;
4629          op64 = aco_opcode::buffer_atomic_add_x2;
4630          break;
4631       case nir_intrinsic_ssbo_atomic_imin:
4632          op32 = aco_opcode::buffer_atomic_smin;
4633          op64 = aco_opcode::buffer_atomic_smin_x2;
4634          break;
4635       case nir_intrinsic_ssbo_atomic_umin:
4636          op32 = aco_opcode::buffer_atomic_umin;
4637          op64 = aco_opcode::buffer_atomic_umin_x2;
4638          break;
4639       case nir_intrinsic_ssbo_atomic_imax:
4640          op32 = aco_opcode::buffer_atomic_smax;
4641          op64 = aco_opcode::buffer_atomic_smax_x2;
4642          break;
4643       case nir_intrinsic_ssbo_atomic_umax:
4644          op32 = aco_opcode::buffer_atomic_umax;
4645          op64 = aco_opcode::buffer_atomic_umax_x2;
4646          break;
4647       case nir_intrinsic_ssbo_atomic_and:
4648          op32 = aco_opcode::buffer_atomic_and;
4649          op64 = aco_opcode::buffer_atomic_and_x2;
4650          break;
4651       case nir_intrinsic_ssbo_atomic_or:
4652          op32 = aco_opcode::buffer_atomic_or;
4653          op64 = aco_opcode::buffer_atomic_or_x2;
4654          break;
4655       case nir_intrinsic_ssbo_atomic_xor:
4656          op32 = aco_opcode::buffer_atomic_xor;
4657          op64 = aco_opcode::buffer_atomic_xor_x2;
4658          break;
4659       case nir_intrinsic_ssbo_atomic_exchange:
4660          op32 = aco_opcode::buffer_atomic_swap;
4661          op64 = aco_opcode::buffer_atomic_swap_x2;
4662          break;
4663       case nir_intrinsic_ssbo_atomic_comp_swap:
4664          op32 = aco_opcode::buffer_atomic_cmpswap;
4665          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
4666          break;
4667       default:
4668          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4669    }
4670    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4671    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4672    mubuf->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4673    mubuf->operands[1] = Operand(rsrc);
4674    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4675    mubuf->operands[3] = Operand(data);
4676    if (return_previous)
4677       mubuf->definitions[0] = Definition(dst);
4678    mubuf->offset = 0;
4679    mubuf->offen = (offset.type() == RegType::vgpr);
4680    mubuf->glc = return_previous;
4681    mubuf->dlc = false; /* Not needed for atomics */
4682    mubuf->disable_wqm = true;
4683    mubuf->barrier = barrier_buffer;
4684    ctx->program->needs_exact = true;
4685    ctx->block->instructions.emplace_back(std::move(mubuf));
4686 }
4687
4688 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
4689
4690    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4691    Builder bld(ctx->program, ctx->block);
4692    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
4693    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
4694 }
4695
4696 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
4697 {
4698    Builder bld(ctx->program, ctx->block);
4699    unsigned num_components = instr->num_components;
4700    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
4701
4702    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4703    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
4704
4705    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4706    bool dlc = glc && ctx->options->chip_class >= GFX10;
4707    aco_opcode op;
4708    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
4709       bool global = ctx->options->chip_class >= GFX9;
4710       aco_opcode op;
4711       switch (num_bytes) {
4712       case 4:
4713          op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
4714          break;
4715       case 8:
4716          op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
4717          break;
4718       case 12:
4719          op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
4720          break;
4721       case 16:
4722          op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
4723          break;
4724       default:
4725          unreachable("load_global not implemented for this size.");
4726       }
4727       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
4728       flat->operands[0] = Operand(addr);
4729       flat->operands[1] = Operand(s1);
4730       flat->glc = glc;
4731       flat->dlc = dlc;
4732       flat->barrier = barrier_buffer;
4733
4734       if (dst.type() == RegType::sgpr) {
4735          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4736          flat->definitions[0] = Definition(vec);
4737          ctx->block->instructions.emplace_back(std::move(flat));
4738          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
4739       } else {
4740          flat->definitions[0] = Definition(dst);
4741          ctx->block->instructions.emplace_back(std::move(flat));
4742       }
4743       emit_split_vector(ctx, dst, num_components);
4744    } else {
4745       switch (num_bytes) {
4746          case 4:
4747             op = aco_opcode::s_load_dword;
4748             break;
4749          case 8:
4750             op = aco_opcode::s_load_dwordx2;
4751             break;
4752          case 12:
4753          case 16:
4754             op = aco_opcode::s_load_dwordx4;
4755             break;
4756          default:
4757             unreachable("load_global not implemented for this size.");
4758       }
4759       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4760       load->operands[0] = Operand(addr);
4761       load->operands[1] = Operand(0u);
4762       load->definitions[0] = Definition(dst);
4763       load->glc = glc;
4764       load->dlc = dlc;
4765       load->barrier = barrier_buffer;
4766       assert(ctx->options->chip_class >= GFX8 || !glc);
4767
4768       if (dst.size() == 3) {
4769          /* trim vector */
4770          Temp vec = bld.tmp(s4);
4771          load->definitions[0] = Definition(vec);
4772          ctx->block->instructions.emplace_back(std::move(load));
4773          emit_split_vector(ctx, vec, 4);
4774
4775          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4776                     emit_extract_vector(ctx, vec, 0, s1),
4777                     emit_extract_vector(ctx, vec, 1, s1),
4778                     emit_extract_vector(ctx, vec, 2, s1));
4779       } else {
4780          ctx->block->instructions.emplace_back(std::move(load));
4781       }
4782    }
4783 }
4784
4785 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
4786 {
4787    Builder bld(ctx->program, ctx->block);
4788    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4789
4790    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4791    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4792
4793    unsigned writemask = nir_intrinsic_write_mask(instr);
4794    while (writemask) {
4795       int start, count;
4796       u_bit_scan_consecutive_range(&writemask, &start, &count);
4797       unsigned num_bytes = count * elem_size_bytes;
4798
4799       Temp write_data = data;
4800       if (count != instr->num_components) {
4801          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4802          for (int i = 0; i < count; i++)
4803             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
4804          write_data = bld.tmp(RegType::vgpr, count);
4805          vec->definitions[0] = Definition(write_data);
4806          ctx->block->instructions.emplace_back(std::move(vec));
4807       }
4808
4809       unsigned offset = start * elem_size_bytes;
4810       if (offset > 0 && ctx->options->chip_class < GFX9) {
4811          Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
4812          Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
4813          Temp carry = bld.tmp(bld.lm);
4814          bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
4815
4816          bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
4817                   Operand(offset), addr0);
4818          bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
4819                   Operand(0u), addr1,
4820                   carry).def(1).setHint(vcc);
4821
4822          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
4823
4824          offset = 0;
4825       }
4826
4827       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4828       bool global = ctx->options->chip_class >= GFX9;
4829       aco_opcode op;
4830       switch (num_bytes) {
4831       case 4:
4832          op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
4833          break;
4834       case 8:
4835          op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
4836          break;
4837       case 12:
4838          op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
4839          break;
4840       case 16:
4841          op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
4842          break;
4843       default:
4844          unreachable("store_global not implemented for this size.");
4845       }
4846       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
4847       flat->operands[0] = Operand(addr);
4848       flat->operands[1] = Operand(s1);
4849       flat->operands[2] = Operand(data);
4850       flat->glc = glc;
4851       flat->dlc = false;
4852       flat->offset = offset;
4853       flat->disable_wqm = true;
4854       flat->barrier = barrier_buffer;
4855       ctx->program->needs_exact = true;
4856       ctx->block->instructions.emplace_back(std::move(flat));
4857    }
4858 }
4859
4860 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4861 {
4862    /* return the previous value if dest is ever used */
4863    bool return_previous = false;
4864    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4865       return_previous = true;
4866       break;
4867    }
4868    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4869       return_previous = true;
4870       break;
4871    }
4872
4873    Builder bld(ctx->program, ctx->block);
4874    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4875    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4876
4877    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
4878       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4879                         get_ssa_temp(ctx, instr->src[2].ssa), data);
4880
4881    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4882
4883    bool global = ctx->options->chip_class >= GFX9;
4884    aco_opcode op32, op64;
4885    switch (instr->intrinsic) {
4886       case nir_intrinsic_global_atomic_add:
4887          op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
4888          op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
4889          break;
4890       case nir_intrinsic_global_atomic_imin:
4891          op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
4892          op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
4893          break;
4894       case nir_intrinsic_global_atomic_umin:
4895          op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
4896          op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
4897          break;
4898       case nir_intrinsic_global_atomic_imax:
4899          op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
4900          op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
4901          break;
4902       case nir_intrinsic_global_atomic_umax:
4903          op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
4904          op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
4905          break;
4906       case nir_intrinsic_global_atomic_and:
4907          op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
4908          op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
4909          break;
4910       case nir_intrinsic_global_atomic_or:
4911          op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
4912          op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
4913          break;
4914       case nir_intrinsic_global_atomic_xor:
4915          op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
4916          op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
4917          break;
4918       case nir_intrinsic_global_atomic_exchange:
4919          op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
4920          op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
4921          break;
4922       case nir_intrinsic_global_atomic_comp_swap:
4923          op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
4924          op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
4925          break;
4926       default:
4927          unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
4928    }
4929    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4930    aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
4931    flat->operands[0] = Operand(addr);
4932    flat->operands[1] = Operand(s1);
4933    flat->operands[2] = Operand(data);
4934    if (return_previous)
4935       flat->definitions[0] = Definition(dst);
4936    flat->glc = return_previous;
4937    flat->dlc = false; /* Not needed for atomics */
4938    flat->offset = 0;
4939    flat->disable_wqm = true;
4940    flat->barrier = barrier_buffer;
4941    ctx->program->needs_exact = true;
4942    ctx->block->instructions.emplace_back(std::move(flat));
4943 }
4944
4945 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
4946    Builder bld(ctx->program, ctx->block);
4947    switch(instr->intrinsic) {
4948       case nir_intrinsic_group_memory_barrier:
4949       case nir_intrinsic_memory_barrier:
4950          bld.barrier(aco_opcode::p_memory_barrier_all);
4951          break;
4952       case nir_intrinsic_memory_barrier_buffer:
4953          bld.barrier(aco_opcode::p_memory_barrier_buffer);
4954          break;
4955       case nir_intrinsic_memory_barrier_image:
4956          bld.barrier(aco_opcode::p_memory_barrier_image);
4957          break;
4958       case nir_intrinsic_memory_barrier_shared:
4959          bld.barrier(aco_opcode::p_memory_barrier_shared);
4960          break;
4961       default:
4962          unreachable("Unimplemented memory barrier intrinsic");
4963          break;
4964    }
4965 }
4966
4967 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4968 {
4969    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
4970    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4971    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
4972    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4973    Builder bld(ctx->program, ctx->block);
4974
4975    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
4976    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4977    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
4978 }
4979
4980 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4981 {
4982    unsigned writemask = nir_intrinsic_write_mask(instr);
4983    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4984    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4985    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4986    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
4987
4988    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4989    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
4990 }
4991
4992 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4993 {
4994    unsigned offset = nir_intrinsic_base(instr);
4995    Operand m = load_lds_size_m0(ctx);
4996    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4997    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4998
4999    unsigned num_operands = 3;
5000    aco_opcode op32, op64, op32_rtn, op64_rtn;
5001    switch(instr->intrinsic) {
5002       case nir_intrinsic_shared_atomic_add:
5003          op32 = aco_opcode::ds_add_u32;
5004          op64 = aco_opcode::ds_add_u64;
5005          op32_rtn = aco_opcode::ds_add_rtn_u32;
5006          op64_rtn = aco_opcode::ds_add_rtn_u64;
5007          break;
5008       case nir_intrinsic_shared_atomic_imin:
5009          op32 = aco_opcode::ds_min_i32;
5010          op64 = aco_opcode::ds_min_i64;
5011          op32_rtn = aco_opcode::ds_min_rtn_i32;
5012          op64_rtn = aco_opcode::ds_min_rtn_i64;
5013          break;
5014       case nir_intrinsic_shared_atomic_umin:
5015          op32 = aco_opcode::ds_min_u32;
5016          op64 = aco_opcode::ds_min_u64;
5017          op32_rtn = aco_opcode::ds_min_rtn_u32;
5018          op64_rtn = aco_opcode::ds_min_rtn_u64;
5019          break;
5020       case nir_intrinsic_shared_atomic_imax:
5021          op32 = aco_opcode::ds_max_i32;
5022          op64 = aco_opcode::ds_max_i64;
5023          op32_rtn = aco_opcode::ds_max_rtn_i32;
5024          op64_rtn = aco_opcode::ds_max_rtn_i64;
5025          break;
5026       case nir_intrinsic_shared_atomic_umax:
5027          op32 = aco_opcode::ds_max_u32;
5028          op64 = aco_opcode::ds_max_u64;
5029          op32_rtn = aco_opcode::ds_max_rtn_u32;
5030          op64_rtn = aco_opcode::ds_max_rtn_u64;
5031          break;
5032       case nir_intrinsic_shared_atomic_and:
5033          op32 = aco_opcode::ds_and_b32;
5034          op64 = aco_opcode::ds_and_b64;
5035          op32_rtn = aco_opcode::ds_and_rtn_b32;
5036          op64_rtn = aco_opcode::ds_and_rtn_b64;
5037          break;
5038       case nir_intrinsic_shared_atomic_or:
5039          op32 = aco_opcode::ds_or_b32;
5040          op64 = aco_opcode::ds_or_b64;
5041          op32_rtn = aco_opcode::ds_or_rtn_b32;
5042          op64_rtn = aco_opcode::ds_or_rtn_b64;
5043          break;
5044       case nir_intrinsic_shared_atomic_xor:
5045          op32 = aco_opcode::ds_xor_b32;
5046          op64 = aco_opcode::ds_xor_b64;
5047          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5048          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5049          break;
5050       case nir_intrinsic_shared_atomic_exchange:
5051          op32 = aco_opcode::ds_write_b32;
5052          op64 = aco_opcode::ds_write_b64;
5053          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5054          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5055          break;
5056       case nir_intrinsic_shared_atomic_comp_swap:
5057          op32 = aco_opcode::ds_cmpst_b32;
5058          op64 = aco_opcode::ds_cmpst_b64;
5059          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
5060          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
5061          num_operands = 4;
5062          break;
5063       default:
5064          unreachable("Unhandled shared atomic intrinsic");
5065    }
5066
5067    /* return the previous value if dest is ever used */
5068    bool return_previous = false;
5069    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5070       return_previous = true;
5071       break;
5072    }
5073    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5074       return_previous = true;
5075       break;
5076    }
5077
5078    aco_opcode op;
5079    if (data.size() == 1) {
5080       assert(instr->dest.ssa.bit_size == 32);
5081       op = return_previous ? op32_rtn : op32;
5082    } else {
5083       assert(instr->dest.ssa.bit_size == 64);
5084       op = return_previous ? op64_rtn : op64;
5085    }
5086
5087    if (offset > 65535) {
5088       Builder bld(ctx->program, ctx->block);
5089       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5090       offset = 0;
5091    }
5092
5093    aco_ptr<DS_instruction> ds;
5094    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5095    ds->operands[0] = Operand(address);
5096    ds->operands[1] = Operand(data);
5097    if (num_operands == 4)
5098       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5099    ds->operands[num_operands - 1] = m;
5100    ds->offset0 = offset;
5101    if (return_previous)
5102       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5103    ctx->block->instructions.emplace_back(std::move(ds));
5104 }
5105
5106 Temp get_scratch_resource(isel_context *ctx)
5107 {
5108    Builder bld(ctx->program, ctx->block);
5109    Temp scratch_addr = ctx->program->private_segment_buffer;
5110    if (ctx->stage != compute_cs)
5111       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
5112
5113    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
5114                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
5115
5116    if (ctx->program->chip_class >= GFX10) {
5117       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5118                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
5119                    S_008F0C_RESOURCE_LEVEL(1);
5120    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5121       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5122                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5123    }
5124
5125    /* older generations need element size = 16 bytes. element size removed in GFX9 */
5126    if (ctx->program->chip_class <= GFX8)
5127       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
5128
5129    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
5130 }
5131
5132 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5133    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
5134    Builder bld(ctx->program, ctx->block);
5135    Temp rsrc = get_scratch_resource(ctx);
5136    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5137    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5138
5139    aco_opcode op;
5140    switch (dst.size()) {
5141       case 1:
5142          op = aco_opcode::buffer_load_dword;
5143          break;
5144       case 2:
5145          op = aco_opcode::buffer_load_dwordx2;
5146          break;
5147       case 3:
5148          op = aco_opcode::buffer_load_dwordx3;
5149          break;
5150       case 4:
5151          op = aco_opcode::buffer_load_dwordx4;
5152          break;
5153       case 6:
5154       case 8: {
5155          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
5156          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
5157                                 bld.def(v4), offset, rsrc,
5158                                 ctx->program->scratch_offset, 0, true);
5159          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
5160                                                   aco_opcode::buffer_load_dwordx4,
5161                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
5162                                 offset, rsrc, ctx->program->scratch_offset, 16, true);
5163          emit_split_vector(ctx, lower, 2);
5164          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
5165          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
5166          if (dst.size() == 8) {
5167             emit_split_vector(ctx, upper, 2);
5168             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
5169             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
5170          } else {
5171             elems[2] = upper;
5172          }
5173
5174          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
5175                                                                          Format::PSEUDO, dst.size() / 2, 1)};
5176          for (unsigned i = 0; i < dst.size() / 2; i++)
5177             vec->operands[i] = Operand(elems[i]);
5178          vec->definitions[0] = Definition(dst);
5179          bld.insert(std::move(vec));
5180          ctx->allocated_vec.emplace(dst.id(), elems);
5181          return;
5182       }
5183       default:
5184          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5185    }
5186
5187    bld.mubuf(op, Definition(dst), offset, rsrc, ctx->program->scratch_offset, 0, true);
5188    emit_split_vector(ctx, dst, instr->num_components);
5189 }
5190
5191 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5192    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5193    Builder bld(ctx->program, ctx->block);
5194    Temp rsrc = get_scratch_resource(ctx);
5195    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5196    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5197
5198    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5199    unsigned writemask = nir_intrinsic_write_mask(instr);
5200
5201    while (writemask) {
5202       int start, count;
5203       u_bit_scan_consecutive_range(&writemask, &start, &count);
5204       int num_bytes = count * elem_size_bytes;
5205
5206       if (num_bytes > 16) {
5207          assert(elem_size_bytes == 8);
5208          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5209          count = 2;
5210          num_bytes = 16;
5211       }
5212
5213       // TODO: check alignment of sub-dword stores
5214       // TODO: split 3 bytes. there is no store instruction for that
5215
5216       Temp write_data;
5217       if (count != instr->num_components) {
5218          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5219          for (int i = 0; i < count; i++) {
5220             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5221             vec->operands[i] = Operand(elem);
5222          }
5223          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5224          vec->definitions[0] = Definition(write_data);
5225          ctx->block->instructions.emplace_back(std::move(vec));
5226       } else {
5227          write_data = data;
5228       }
5229
5230       aco_opcode op;
5231       switch (num_bytes) {
5232          case 4:
5233             op = aco_opcode::buffer_store_dword;
5234             break;
5235          case 8:
5236             op = aco_opcode::buffer_store_dwordx2;
5237             break;
5238          case 12:
5239             op = aco_opcode::buffer_store_dwordx3;
5240             break;
5241          case 16:
5242             op = aco_opcode::buffer_store_dwordx4;
5243             break;
5244          default:
5245             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5246       }
5247
5248       bld.mubuf(op, offset, rsrc, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5249    }
5250 }
5251
5252 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5253    uint8_t log2_ps_iter_samples;
5254    if (ctx->program->info->ps.force_persample) {
5255       log2_ps_iter_samples =
5256          util_logbase2(ctx->options->key.fs.num_samples);
5257    } else {
5258       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5259    }
5260
5261    /* The bit pattern matches that used by fixed function fragment
5262     * processing. */
5263    static const unsigned ps_iter_masks[] = {
5264       0xffff, /* not used */
5265       0x5555,
5266       0x1111,
5267       0x0101,
5268       0x0001,
5269    };
5270    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5271
5272    Builder bld(ctx->program, ctx->block);
5273
5274    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
5275                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5276    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5277    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5278    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5279    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
5280 }
5281
5282 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
5283 {
5284    Builder bld(ctx->program, ctx->block);
5285
5286    if (cluster_size == 1) {
5287       return src;
5288    } if (op == nir_op_iand && cluster_size == 4) {
5289       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5290       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5291       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
5292                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
5293    } else if (op == nir_op_ior && cluster_size == 4) {
5294       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5295       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
5296                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
5297    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
5298       //subgroupAnd(val) -> (exec & ~val) == 0
5299       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5300       return bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(0u), Operand(-1u), bld.scc(tmp));
5301    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
5302       //subgroupOr(val) -> (val & exec) != 0
5303       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
5304       return bool_to_vector_condition(ctx, tmp);
5305    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
5306       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5307       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5308       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
5309       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
5310       return bool_to_vector_condition(ctx, tmp);
5311    } else {
5312       //subgroupClustered{And,Or,Xor}(val, n) ->
5313       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
5314       //cluster_offset = ~(n - 1) & lane_id
5315       //cluster_mask = ((1 << n) - 1)
5316       //subgroupClusteredAnd():
5317       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5318       //subgroupClusteredOr():
5319       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
5320       //subgroupClusteredXor():
5321       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5322       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
5323       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
5324
5325       Temp tmp;
5326       if (op == nir_op_iand)
5327          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5328       else
5329          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5330
5331       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
5332
5333       if (ctx->program->chip_class <= GFX7)
5334          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
5335       else if (ctx->program->wave_size == 64)
5336          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
5337       else
5338          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
5339       tmp = emit_extract_vector(ctx, tmp, 0, v1);
5340       if (cluster_mask != 0xffffffff)
5341          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
5342
5343       Definition cmp_def = Definition();
5344       if (op == nir_op_iand) {
5345          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
5346       } else if (op == nir_op_ior) {
5347          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5348       } else if (op == nir_op_ixor) {
5349          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
5350                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
5351          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5352       }
5353       cmp_def.setHint(vcc);
5354       return cmp_def.getTemp();
5355    }
5356 }
5357
5358 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
5359 {
5360    Builder bld(ctx->program, ctx->block);
5361
5362    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5363    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5364    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5365    Temp tmp;
5366    if (op == nir_op_iand)
5367       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5368    else
5369       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
5370
5371    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
5372    Temp lo = lohi.def(0).getTemp();
5373    Temp hi = lohi.def(1).getTemp();
5374    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
5375
5376    Definition cmp_def = Definition();
5377    if (op == nir_op_iand)
5378       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5379    else if (op == nir_op_ior)
5380       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5381    else if (op == nir_op_ixor)
5382       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
5383                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
5384    cmp_def.setHint(vcc);
5385    return cmp_def.getTemp();
5386 }
5387
5388 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
5389 {
5390    Builder bld(ctx->program, ctx->block);
5391
5392    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5393    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5394    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5395    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
5396    if (op == nir_op_iand)
5397       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5398    else if (op == nir_op_ior)
5399       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5400    else if (op == nir_op_ixor)
5401       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5402
5403    assert(false);
5404    return Temp();
5405 }
5406
5407 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
5408 {
5409    Builder bld(ctx->program, ctx->block);
5410    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
5411    if (src.regClass().type() == RegType::vgpr) {
5412       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
5413    } else if (src.regClass() == s1) {
5414       bld.sop1(aco_opcode::s_mov_b32, dst, src);
5415    } else if (src.regClass() == s2) {
5416       bld.sop1(aco_opcode::s_mov_b64, dst, src);
5417    } else {
5418       fprintf(stderr, "Unimplemented NIR instr bit size: ");
5419       nir_print_instr(&instr->instr, stderr);
5420       fprintf(stderr, "\n");
5421    }
5422 }
5423
5424 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
5425 {
5426    Builder bld(ctx->program, ctx->block);
5427    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
5428    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
5429    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
5430
5431    Temp ddx_1, ddx_2, ddy_1, ddy_2;
5432    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
5433    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
5434    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
5435
5436    /* Build DD X/Y */
5437    if (ctx->program->chip_class >= GFX8) {
5438       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
5439       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
5440       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
5441       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
5442       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
5443       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
5444    } else {
5445       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
5446       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
5447       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
5448       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
5449       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
5450       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
5451       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
5452       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
5453       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
5454       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
5455    }
5456
5457    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5458    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
5459    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
5460    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
5461    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
5462    Temp wqm1 = bld.tmp(v1);
5463    emit_wqm(ctx, tmp1, wqm1, true);
5464    Temp wqm2 = bld.tmp(v1);
5465    emit_wqm(ctx, tmp2, wqm2, true);
5466    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
5467    return;
5468 }
5469
5470 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
5471 {
5472    Builder bld(ctx->program, ctx->block);
5473    switch(instr->intrinsic) {
5474    case nir_intrinsic_load_barycentric_sample:
5475    case nir_intrinsic_load_barycentric_pixel:
5476    case nir_intrinsic_load_barycentric_centroid: {
5477       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
5478       Temp bary = Temp(0, s2);
5479       switch (mode) {
5480       case INTERP_MODE_SMOOTH:
5481       case INTERP_MODE_NONE:
5482          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
5483             bary = get_arg(ctx, ctx->args->ac.persp_center);
5484          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
5485             bary = ctx->persp_centroid;
5486          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
5487             bary = get_arg(ctx, ctx->args->ac.persp_sample);
5488          break;
5489       case INTERP_MODE_NOPERSPECTIVE:
5490          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
5491             bary = get_arg(ctx, ctx->args->ac.linear_center);
5492          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
5493             bary = ctx->linear_centroid;
5494          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
5495             bary = get_arg(ctx, ctx->args->ac.linear_sample);
5496          break;
5497       default:
5498          break;
5499       }
5500       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5501       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
5502       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
5503       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5504                  Operand(p1), Operand(p2));
5505       emit_split_vector(ctx, dst, 2);
5506       break;
5507    }
5508    case nir_intrinsic_load_barycentric_at_sample: {
5509       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
5510       switch (ctx->options->key.fs.num_samples) {
5511          case 2: sample_pos_offset += 1 << 3; break;
5512          case 4: sample_pos_offset += 3 << 3; break;
5513          case 8: sample_pos_offset += 7 << 3; break;
5514          default: break;
5515       }
5516       Temp sample_pos;
5517       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5518       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
5519       Temp private_segment_buffer = ctx->program->private_segment_buffer;
5520       if (addr.type() == RegType::sgpr) {
5521          Operand offset;
5522          if (const_addr) {
5523             sample_pos_offset += const_addr->u32 << 3;
5524             offset = Operand(sample_pos_offset);
5525          } else if (ctx->options->chip_class >= GFX9) {
5526             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5527          } else {
5528             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
5529             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5530          }
5531          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, Operand(offset));
5532
5533       } else if (ctx->options->chip_class >= GFX9) {
5534          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5535          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
5536       } else {
5537          /* addr += private_segment_buffer + sample_pos_offset */
5538          Temp tmp0 = bld.tmp(s1);
5539          Temp tmp1 = bld.tmp(s1);
5540          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
5541          Definition scc_tmp = bld.def(s1, scc);
5542          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
5543          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
5544          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5545          Temp pck0 = bld.tmp(v1);
5546          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
5547          tmp1 = as_vgpr(ctx, tmp1);
5548          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
5549          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
5550
5551          /* sample_pos = flat_load_dwordx2 addr */
5552          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
5553       }
5554
5555       /* sample_pos -= 0.5 */
5556       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
5557       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
5558       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
5559       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
5560       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
5561
5562       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5563       break;
5564    }
5565    case nir_intrinsic_load_barycentric_at_offset: {
5566       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
5567       RegClass rc = RegClass(offset.type(), 1);
5568       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
5569       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
5570       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5571       break;
5572    }
5573    case nir_intrinsic_load_front_face: {
5574       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5575                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
5576       break;
5577    }
5578    case nir_intrinsic_load_view_index:
5579    case nir_intrinsic_load_layer_id: {
5580       if (instr->intrinsic == nir_intrinsic_load_view_index && (ctx->stage & sw_vs)) {
5581          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5582          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
5583          break;
5584       }
5585
5586       unsigned idx = nir_intrinsic_base(instr);
5587       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5588                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
5589       break;
5590    }
5591    case nir_intrinsic_load_frag_coord: {
5592       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
5593       break;
5594    }
5595    case nir_intrinsic_load_sample_pos: {
5596       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
5597       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
5598       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5599                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
5600                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
5601       break;
5602    }
5603    case nir_intrinsic_load_interpolated_input:
5604       visit_load_interpolated_input(ctx, instr);
5605       break;
5606    case nir_intrinsic_store_output:
5607       visit_store_output(ctx, instr);
5608       break;
5609    case nir_intrinsic_load_input:
5610       visit_load_input(ctx, instr);
5611       break;
5612    case nir_intrinsic_load_ubo:
5613       visit_load_ubo(ctx, instr);
5614       break;
5615    case nir_intrinsic_load_push_constant:
5616       visit_load_push_constant(ctx, instr);
5617       break;
5618    case nir_intrinsic_load_constant:
5619       visit_load_constant(ctx, instr);
5620       break;
5621    case nir_intrinsic_vulkan_resource_index:
5622       visit_load_resource(ctx, instr);
5623       break;
5624    case nir_intrinsic_discard:
5625       visit_discard(ctx, instr);
5626       break;
5627    case nir_intrinsic_discard_if:
5628       visit_discard_if(ctx, instr);
5629       break;
5630    case nir_intrinsic_load_shared:
5631       visit_load_shared(ctx, instr);
5632       break;
5633    case nir_intrinsic_store_shared:
5634       visit_store_shared(ctx, instr);
5635       break;
5636    case nir_intrinsic_shared_atomic_add:
5637    case nir_intrinsic_shared_atomic_imin:
5638    case nir_intrinsic_shared_atomic_umin:
5639    case nir_intrinsic_shared_atomic_imax:
5640    case nir_intrinsic_shared_atomic_umax:
5641    case nir_intrinsic_shared_atomic_and:
5642    case nir_intrinsic_shared_atomic_or:
5643    case nir_intrinsic_shared_atomic_xor:
5644    case nir_intrinsic_shared_atomic_exchange:
5645    case nir_intrinsic_shared_atomic_comp_swap:
5646       visit_shared_atomic(ctx, instr);
5647       break;
5648    case nir_intrinsic_image_deref_load:
5649       visit_image_load(ctx, instr);
5650       break;
5651    case nir_intrinsic_image_deref_store:
5652       visit_image_store(ctx, instr);
5653       break;
5654    case nir_intrinsic_image_deref_atomic_add:
5655    case nir_intrinsic_image_deref_atomic_umin:
5656    case nir_intrinsic_image_deref_atomic_imin:
5657    case nir_intrinsic_image_deref_atomic_umax:
5658    case nir_intrinsic_image_deref_atomic_imax:
5659    case nir_intrinsic_image_deref_atomic_and:
5660    case nir_intrinsic_image_deref_atomic_or:
5661    case nir_intrinsic_image_deref_atomic_xor:
5662    case nir_intrinsic_image_deref_atomic_exchange:
5663    case nir_intrinsic_image_deref_atomic_comp_swap:
5664       visit_image_atomic(ctx, instr);
5665       break;
5666    case nir_intrinsic_image_deref_size:
5667       visit_image_size(ctx, instr);
5668       break;
5669    case nir_intrinsic_load_ssbo:
5670       visit_load_ssbo(ctx, instr);
5671       break;
5672    case nir_intrinsic_store_ssbo:
5673       visit_store_ssbo(ctx, instr);
5674       break;
5675    case nir_intrinsic_load_global:
5676       visit_load_global(ctx, instr);
5677       break;
5678    case nir_intrinsic_store_global:
5679       visit_store_global(ctx, instr);
5680       break;
5681    case nir_intrinsic_global_atomic_add:
5682    case nir_intrinsic_global_atomic_imin:
5683    case nir_intrinsic_global_atomic_umin:
5684    case nir_intrinsic_global_atomic_imax:
5685    case nir_intrinsic_global_atomic_umax:
5686    case nir_intrinsic_global_atomic_and:
5687    case nir_intrinsic_global_atomic_or:
5688    case nir_intrinsic_global_atomic_xor:
5689    case nir_intrinsic_global_atomic_exchange:
5690    case nir_intrinsic_global_atomic_comp_swap:
5691       visit_global_atomic(ctx, instr);
5692       break;
5693    case nir_intrinsic_ssbo_atomic_add:
5694    case nir_intrinsic_ssbo_atomic_imin:
5695    case nir_intrinsic_ssbo_atomic_umin:
5696    case nir_intrinsic_ssbo_atomic_imax:
5697    case nir_intrinsic_ssbo_atomic_umax:
5698    case nir_intrinsic_ssbo_atomic_and:
5699    case nir_intrinsic_ssbo_atomic_or:
5700    case nir_intrinsic_ssbo_atomic_xor:
5701    case nir_intrinsic_ssbo_atomic_exchange:
5702    case nir_intrinsic_ssbo_atomic_comp_swap:
5703       visit_atomic_ssbo(ctx, instr);
5704       break;
5705    case nir_intrinsic_load_scratch:
5706       visit_load_scratch(ctx, instr);
5707       break;
5708    case nir_intrinsic_store_scratch:
5709       visit_store_scratch(ctx, instr);
5710       break;
5711    case nir_intrinsic_get_buffer_size:
5712       visit_get_buffer_size(ctx, instr);
5713       break;
5714    case nir_intrinsic_control_barrier: {
5715       unsigned* bsize = ctx->program->info->cs.block_size;
5716       unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
5717       if (workgroup_size > ctx->program->wave_size)
5718          bld.sopp(aco_opcode::s_barrier);
5719       break;
5720    }
5721    case nir_intrinsic_group_memory_barrier:
5722    case nir_intrinsic_memory_barrier:
5723    case nir_intrinsic_memory_barrier_buffer:
5724    case nir_intrinsic_memory_barrier_image:
5725    case nir_intrinsic_memory_barrier_shared:
5726       emit_memory_barrier(ctx, instr);
5727       break;
5728    case nir_intrinsic_memory_barrier_tcs_patch:
5729       break;
5730    case nir_intrinsic_load_num_work_groups: {
5731       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5732       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
5733       emit_split_vector(ctx, dst, 3);
5734       break;
5735    }
5736    case nir_intrinsic_load_local_invocation_id: {
5737       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5738       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
5739       emit_split_vector(ctx, dst, 3);
5740       break;
5741    }
5742    case nir_intrinsic_load_work_group_id: {
5743       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5744       struct ac_arg *args = ctx->args->ac.workgroup_ids;
5745       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5746                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
5747                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
5748                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
5749       emit_split_vector(ctx, dst, 3);
5750       break;
5751    }
5752    case nir_intrinsic_load_local_invocation_index: {
5753       Temp id = emit_mbcnt(ctx, bld.def(v1));
5754
5755       /* The tg_size bits [6:11] contain the subgroup id,
5756        * we need this multiplied by the wave size, and then OR the thread id to it.
5757        */
5758       if (ctx->program->wave_size == 64) {
5759          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
5760          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
5761                                 get_arg(ctx, ctx->args->ac.tg_size));
5762          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
5763       } else {
5764          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
5765          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
5766                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
5767          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
5768       }
5769       break;
5770    }
5771    case nir_intrinsic_load_subgroup_id: {
5772       if (ctx->stage == compute_cs) {
5773          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
5774                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
5775       } else {
5776          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
5777       }
5778       break;
5779    }
5780    case nir_intrinsic_load_subgroup_invocation: {
5781       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
5782       break;
5783    }
5784    case nir_intrinsic_load_num_subgroups: {
5785       if (ctx->stage == compute_cs)
5786          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
5787                   get_arg(ctx, ctx->args->ac.tg_size));
5788       else
5789          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
5790       break;
5791    }
5792    case nir_intrinsic_ballot: {
5793       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5794       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5795       Definition tmp = bld.def(dst.regClass());
5796       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
5797       if (instr->src[0].ssa->bit_size == 1) {
5798          assert(src.regClass() == bld.lm);
5799          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
5800       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
5801          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
5802       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
5803          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
5804       } else {
5805          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5806          nir_print_instr(&instr->instr, stderr);
5807          fprintf(stderr, "\n");
5808       }
5809       if (dst.size() != bld.lm.size()) {
5810          /* Wave32 with ballot size set to 64 */
5811          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
5812       }
5813       emit_wqm(ctx, tmp.getTemp(), dst);
5814       break;
5815    }
5816    case nir_intrinsic_shuffle:
5817    case nir_intrinsic_read_invocation: {
5818       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5819       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
5820          emit_uniform_subgroup(ctx, instr, src);
5821       } else {
5822          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
5823          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
5824             tid = bld.as_uniform(tid);
5825          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5826          if (src.regClass() == v1) {
5827             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
5828          } else if (src.regClass() == v2) {
5829             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5830             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5831             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
5832             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
5833             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5834             emit_split_vector(ctx, dst, 2);
5835          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
5836             assert(src.regClass() == bld.lm);
5837             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
5838             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5839          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
5840             assert(src.regClass() == bld.lm);
5841             Temp tmp;
5842             if (ctx->program->chip_class <= GFX7)
5843                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
5844             else if (ctx->program->wave_size == 64)
5845                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
5846             else
5847                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
5848             tmp = emit_extract_vector(ctx, tmp, 0, v1);
5849             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
5850             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
5851          } else {
5852             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5853             nir_print_instr(&instr->instr, stderr);
5854             fprintf(stderr, "\n");
5855          }
5856       }
5857       break;
5858    }
5859    case nir_intrinsic_load_sample_id: {
5860       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5861                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5862       break;
5863    }
5864    case nir_intrinsic_load_sample_mask_in: {
5865       visit_load_sample_mask_in(ctx, instr);
5866       break;
5867    }
5868    case nir_intrinsic_read_first_invocation: {
5869       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5870       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5871       if (src.regClass() == v1) {
5872          emit_wqm(ctx,
5873                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
5874                   dst);
5875       } else if (src.regClass() == v2) {
5876          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5877          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5878          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
5879          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
5880          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5881          emit_split_vector(ctx, dst, 2);
5882       } else if (instr->dest.ssa.bit_size == 1) {
5883          assert(src.regClass() == bld.lm);
5884          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
5885                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
5886          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5887       } else if (src.regClass() == s1) {
5888          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
5889       } else if (src.regClass() == s2) {
5890          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
5891       } else {
5892          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5893          nir_print_instr(&instr->instr, stderr);
5894          fprintf(stderr, "\n");
5895       }
5896       break;
5897    }
5898    case nir_intrinsic_vote_all: {
5899       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5900       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5901       assert(src.regClass() == bld.lm);
5902       assert(dst.regClass() == bld.lm);
5903
5904       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5905       Temp val = bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(0u), Operand(-1u), bld.scc(tmp));
5906       emit_wqm(ctx, val, dst);
5907       break;
5908    }
5909    case nir_intrinsic_vote_any: {
5910       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5911       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5912       assert(src.regClass() == bld.lm);
5913       assert(dst.regClass() == bld.lm);
5914
5915       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5916       Temp val = bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(-1u), Operand(0u), bld.scc(tmp));
5917       emit_wqm(ctx, val, dst);
5918       break;
5919    }
5920    case nir_intrinsic_reduce:
5921    case nir_intrinsic_inclusive_scan:
5922    case nir_intrinsic_exclusive_scan: {
5923       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5924       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5925       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
5926       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
5927          nir_intrinsic_cluster_size(instr) : 0;
5928       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
5929
5930       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
5931          emit_uniform_subgroup(ctx, instr, src);
5932       } else if (instr->dest.ssa.bit_size == 1) {
5933          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
5934             op = nir_op_iand;
5935          else if (op == nir_op_iadd)
5936             op = nir_op_ixor;
5937          else if (op == nir_op_umax || op == nir_op_imax)
5938             op = nir_op_ior;
5939          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
5940
5941          switch (instr->intrinsic) {
5942          case nir_intrinsic_reduce:
5943             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
5944             break;
5945          case nir_intrinsic_exclusive_scan:
5946             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
5947             break;
5948          case nir_intrinsic_inclusive_scan:
5949             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
5950             break;
5951          default:
5952             assert(false);
5953          }
5954       } else if (cluster_size == 1) {
5955          bld.copy(Definition(dst), src);
5956       } else {
5957          src = as_vgpr(ctx, src);
5958
5959          ReduceOp reduce_op;
5960          switch (op) {
5961          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
5962             CASE(iadd)
5963             CASE(imul)
5964             CASE(fadd)
5965             CASE(fmul)
5966             CASE(imin)
5967             CASE(umin)
5968             CASE(fmin)
5969             CASE(imax)
5970             CASE(umax)
5971             CASE(fmax)
5972             CASE(iand)
5973             CASE(ior)
5974             CASE(ixor)
5975             default:
5976                unreachable("unknown reduction op");
5977          #undef CASE
5978          }
5979
5980          aco_opcode aco_op;
5981          switch (instr->intrinsic) {
5982             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
5983             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
5984             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
5985             default:
5986                unreachable("unknown reduce intrinsic");
5987          }
5988
5989          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
5990          reduce->operands[0] = Operand(src);
5991          // filled in by aco_reduce_assign.cpp, used internally as part of the
5992          // reduce sequence
5993          assert(dst.size() == 1 || dst.size() == 2);
5994          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
5995          reduce->operands[2] = Operand(v1.as_linear());
5996
5997          Temp tmp_dst = bld.tmp(dst.regClass());
5998          reduce->definitions[0] = Definition(tmp_dst);
5999          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
6000          reduce->definitions[2] = Definition();
6001          reduce->definitions[3] = Definition(scc, s1);
6002          reduce->definitions[4] = Definition();
6003          reduce->reduce_op = reduce_op;
6004          reduce->cluster_size = cluster_size;
6005          ctx->block->instructions.emplace_back(std::move(reduce));
6006
6007          emit_wqm(ctx, tmp_dst, dst);
6008       }
6009       break;
6010    }
6011    case nir_intrinsic_quad_broadcast: {
6012       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6013       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6014          emit_uniform_subgroup(ctx, instr, src);
6015       } else {
6016          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6017          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
6018          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
6019
6020          if (instr->dest.ssa.bit_size == 1) {
6021             assert(src.regClass() == bld.lm);
6022             assert(dst.regClass() == bld.lm);
6023             uint32_t half_mask = 0x11111111u << lane;
6024             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
6025             Temp tmp = bld.tmp(bld.lm);
6026             bld.sop1(Builder::s_wqm, Definition(tmp),
6027                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
6028                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
6029             emit_wqm(ctx, tmp, dst);
6030          } else if (instr->dest.ssa.bit_size == 32) {
6031             if (ctx->program->chip_class >= GFX8)
6032                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
6033             else
6034                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
6035          } else if (instr->dest.ssa.bit_size == 64) {
6036             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6037             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6038             if (ctx->program->chip_class >= GFX8) {
6039                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6040                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6041             } else {
6042                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
6043                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
6044             }
6045             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6046             emit_split_vector(ctx, dst, 2);
6047          } else {
6048             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6049             nir_print_instr(&instr->instr, stderr);
6050             fprintf(stderr, "\n");
6051          }
6052       }
6053       break;
6054    }
6055    case nir_intrinsic_quad_swap_horizontal:
6056    case nir_intrinsic_quad_swap_vertical:
6057    case nir_intrinsic_quad_swap_diagonal:
6058    case nir_intrinsic_quad_swizzle_amd: {
6059       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6060       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6061          emit_uniform_subgroup(ctx, instr, src);
6062          break;
6063       }
6064       uint16_t dpp_ctrl = 0;
6065       switch (instr->intrinsic) {
6066       case nir_intrinsic_quad_swap_horizontal:
6067          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
6068          break;
6069       case nir_intrinsic_quad_swap_vertical:
6070          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
6071          break;
6072       case nir_intrinsic_quad_swap_diagonal:
6073          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
6074          break;
6075       case nir_intrinsic_quad_swizzle_amd:
6076          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
6077          break;
6078       default:
6079          break;
6080       }
6081       if (ctx->program->chip_class < GFX8)
6082          dpp_ctrl |= (1 << 15);
6083
6084       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6085       if (instr->dest.ssa.bit_size == 1) {
6086          assert(src.regClass() == bld.lm);
6087          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
6088          if (ctx->program->chip_class >= GFX8)
6089             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6090          else
6091             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6092          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
6093          emit_wqm(ctx, tmp, dst);
6094       } else if (instr->dest.ssa.bit_size == 32) {
6095          Temp tmp;
6096          if (ctx->program->chip_class >= GFX8)
6097             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6098          else
6099             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6100          emit_wqm(ctx, tmp, dst);
6101       } else if (instr->dest.ssa.bit_size == 64) {
6102          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6103          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6104          if (ctx->program->chip_class >= GFX8) {
6105             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6106             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6107          } else {
6108             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
6109             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
6110          }
6111          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6112          emit_split_vector(ctx, dst, 2);
6113       } else {
6114          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6115          nir_print_instr(&instr->instr, stderr);
6116          fprintf(stderr, "\n");
6117       }
6118       break;
6119    }
6120    case nir_intrinsic_masked_swizzle_amd: {
6121       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6122       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6123          emit_uniform_subgroup(ctx, instr, src);
6124          break;
6125       }
6126       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6127       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
6128       if (dst.regClass() == v1) {
6129          emit_wqm(ctx,
6130                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
6131                   dst);
6132       } else if (dst.regClass() == v2) {
6133          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6134          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6135          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
6136          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
6137          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6138          emit_split_vector(ctx, dst, 2);
6139       } else {
6140          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6141          nir_print_instr(&instr->instr, stderr);
6142          fprintf(stderr, "\n");
6143       }
6144       break;
6145    }
6146    case nir_intrinsic_write_invocation_amd: {
6147       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6148       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
6149       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
6150       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6151       if (dst.regClass() == v1) {
6152          /* src2 is ignored for writelane. RA assigns the same reg for dst */
6153          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
6154       } else if (dst.regClass() == v2) {
6155          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
6156          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
6157          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
6158          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
6159          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
6160          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
6161          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6162          emit_split_vector(ctx, dst, 2);
6163       } else {
6164          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6165          nir_print_instr(&instr->instr, stderr);
6166          fprintf(stderr, "\n");
6167       }
6168       break;
6169    }
6170    case nir_intrinsic_mbcnt_amd: {
6171       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6172       RegClass rc = RegClass(src.type(), 1);
6173       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
6174       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
6175       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6176       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
6177       emit_wqm(ctx, wqm_tmp, dst);
6178       break;
6179    }
6180    case nir_intrinsic_load_helper_invocation: {
6181       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6182       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
6183       ctx->block->kind |= block_kind_needs_lowering;
6184       ctx->program->needs_exact = true;
6185       break;
6186    }
6187    case nir_intrinsic_is_helper_invocation: {
6188       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6189       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
6190       ctx->block->kind |= block_kind_needs_lowering;
6191       ctx->program->needs_exact = true;
6192       break;
6193    }
6194    case nir_intrinsic_demote:
6195       bld.pseudo(aco_opcode::p_demote_to_helper);
6196
6197       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
6198          ctx->cf_info.exec_potentially_empty = true;
6199       ctx->block->kind |= block_kind_uses_demote;
6200       ctx->program->needs_exact = true;
6201       break;
6202    case nir_intrinsic_demote_if: {
6203       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6204       assert(src.regClass() == bld.lm);
6205       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6206       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
6207
6208       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
6209          ctx->cf_info.exec_potentially_empty = true;
6210       ctx->block->kind |= block_kind_uses_demote;
6211       ctx->program->needs_exact = true;
6212       break;
6213    }
6214    case nir_intrinsic_first_invocation: {
6215       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
6216                get_ssa_temp(ctx, &instr->dest.ssa));
6217       break;
6218    }
6219    case nir_intrinsic_shader_clock:
6220       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
6221       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
6222       break;
6223    case nir_intrinsic_load_vertex_id_zero_base: {
6224       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6225       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
6226       break;
6227    }
6228    case nir_intrinsic_load_first_vertex: {
6229       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6230       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
6231       break;
6232    }
6233    case nir_intrinsic_load_base_instance: {
6234       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6235       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
6236       break;
6237    }
6238    case nir_intrinsic_load_instance_id: {
6239       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6240       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
6241       break;
6242    }
6243    case nir_intrinsic_load_draw_id: {
6244       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6245       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
6246       break;
6247    }
6248    default:
6249       fprintf(stderr, "Unimplemented intrinsic instr: ");
6250       nir_print_instr(&instr->instr, stderr);
6251       fprintf(stderr, "\n");
6252       abort();
6253
6254       break;
6255    }
6256 }
6257
6258
6259 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
6260                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
6261                     enum glsl_base_type *stype)
6262 {
6263    nir_deref_instr *texture_deref_instr = NULL;
6264    nir_deref_instr *sampler_deref_instr = NULL;
6265    int plane = -1;
6266
6267    for (unsigned i = 0; i < instr->num_srcs; i++) {
6268       switch (instr->src[i].src_type) {
6269       case nir_tex_src_texture_deref:
6270          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
6271          break;
6272       case nir_tex_src_sampler_deref:
6273          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
6274          break;
6275       case nir_tex_src_plane:
6276          plane = nir_src_as_int(instr->src[i].src);
6277          break;
6278       default:
6279          break;
6280       }
6281    }
6282
6283    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
6284
6285    if (!sampler_deref_instr)
6286       sampler_deref_instr = texture_deref_instr;
6287
6288    if (plane >= 0) {
6289       assert(instr->op != nir_texop_txf_ms &&
6290              instr->op != nir_texop_samples_identical);
6291       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
6292       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
6293    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
6294       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
6295    } else {
6296       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
6297    }
6298    if (samp_ptr) {
6299       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
6300
6301       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
6302          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
6303          Builder bld(ctx->program, ctx->block);
6304
6305          /* to avoid unnecessary moves, we split and recombine sampler and image */
6306          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
6307                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6308          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6309          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
6310                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
6311                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
6312          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
6313                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
6314
6315          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
6316          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
6317                                img[0], img[1], img[2], img[3],
6318                                img[4], img[5], img[6], img[7]);
6319          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6320                                 samp[0], samp[1], samp[2], samp[3]);
6321       }
6322    }
6323    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
6324                      instr->op == nir_texop_samples_identical))
6325       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
6326 }
6327
6328 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
6329                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
6330 {
6331    Builder bld(ctx->program, ctx->block);
6332
6333    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
6334    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
6335    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
6336
6337    Operand neg_one(0xbf800000u);
6338    Operand one(0x3f800000u);
6339    Operand two(0x40000000u);
6340    Operand four(0x40800000u);
6341
6342    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
6343    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
6344    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
6345
6346    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
6347    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
6348    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
6349    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
6350
6351    // select sc
6352    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
6353    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
6354                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
6355                        one, is_ma_y);
6356    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6357
6358    // select tc
6359    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
6360    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
6361    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6362
6363    // select ma
6364    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6365                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
6366                   deriv_z, is_ma_z);
6367    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
6368    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
6369 }
6370
6371 void prepare_cube_coords(isel_context *ctx, Temp* coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
6372 {
6373    Builder bld(ctx->program, ctx->block);
6374    Temp coord_args[4], ma, tc, sc, id;
6375    for (unsigned i = 0; i < (is_array ? 4 : 3); i++)
6376       coord_args[i] = emit_extract_vector(ctx, *coords, i, v1);
6377
6378    if (is_array) {
6379       coord_args[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_args[3]);
6380
6381       // see comment in ac_prepare_cube_coords()
6382       if (ctx->options->chip_class <= GFX8)
6383          coord_args[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coord_args[3]);
6384    }
6385
6386    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6387
6388    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
6389    vop3a->operands[0] = Operand(ma);
6390    vop3a->abs[0] = true;
6391    Temp invma = bld.tmp(v1);
6392    vop3a->definitions[0] = Definition(invma);
6393    ctx->block->instructions.emplace_back(std::move(vop3a));
6394
6395    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6396    if (!is_deriv)
6397       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
6398
6399    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6400    if (!is_deriv)
6401       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
6402
6403    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6404
6405    if (is_deriv) {
6406       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
6407       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
6408
6409       for (unsigned i = 0; i < 2; i++) {
6410          // see comment in ac_prepare_cube_coords()
6411          Temp deriv_ma;
6412          Temp deriv_sc, deriv_tc;
6413          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
6414                            &deriv_ma, &deriv_sc, &deriv_tc);
6415
6416          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
6417
6418          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6419                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
6420                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
6421          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6422                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
6423                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
6424          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
6425       }
6426
6427       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
6428       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
6429    }
6430
6431    if (is_array)
6432       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coord_args[3], id, Operand(0x41000000u/*8.0*/));
6433    *coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), sc, tc, id);
6434
6435 }
6436
6437 Temp apply_round_slice(isel_context *ctx, Temp coords, unsigned idx)
6438 {
6439    Temp coord_vec[3];
6440    for (unsigned i = 0; i < coords.size(); i++)
6441       coord_vec[i] = emit_extract_vector(ctx, coords, i, v1);
6442
6443    Builder bld(ctx->program, ctx->block);
6444    coord_vec[idx] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_vec[idx]);
6445
6446    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6447    for (unsigned i = 0; i < coords.size(); i++)
6448       vec->operands[i] = Operand(coord_vec[i]);
6449    Temp res = bld.tmp(RegType::vgpr, coords.size());
6450    vec->definitions[0] = Definition(res);
6451    ctx->block->instructions.emplace_back(std::move(vec));
6452    return res;
6453 }
6454
6455 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
6456 {
6457    if (vec->parent_instr->type != nir_instr_type_alu)
6458       return;
6459    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
6460    if (vec_instr->op != nir_op_vec(vec->num_components))
6461       return;
6462
6463    for (unsigned i = 0; i < vec->num_components; i++) {
6464       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
6465               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
6466    }
6467 }
6468
6469 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
6470 {
6471    Builder bld(ctx->program, ctx->block);
6472    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
6473         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
6474    Temp resource, sampler, fmask_ptr, bias = Temp(), coords, compare = Temp(), sample_index = Temp(),
6475         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp(), derivs = Temp();
6476    nir_const_value *sample_index_cv = NULL;
6477    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
6478    enum glsl_base_type stype;
6479    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
6480
6481    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
6482                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
6483    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
6484                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
6485
6486    for (unsigned i = 0; i < instr->num_srcs; i++) {
6487       switch (instr->src[i].src_type) {
6488       case nir_tex_src_coord:
6489          coords = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[i].src.ssa));
6490          break;
6491       case nir_tex_src_bias:
6492          if (instr->op == nir_texop_txb) {
6493             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
6494             has_bias = true;
6495          }
6496          break;
6497       case nir_tex_src_lod: {
6498          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
6499
6500          if (val && val->f32 <= 0.0) {
6501             level_zero = true;
6502          } else {
6503             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
6504             has_lod = true;
6505          }
6506          break;
6507       }
6508       case nir_tex_src_comparator:
6509          if (instr->is_shadow) {
6510             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
6511             has_compare = true;
6512          }
6513          break;
6514       case nir_tex_src_offset:
6515          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
6516          get_const_vec(instr->src[i].src.ssa, const_offset);
6517          has_offset = true;
6518          break;
6519       case nir_tex_src_ddx:
6520          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
6521          has_ddx = true;
6522          break;
6523       case nir_tex_src_ddy:
6524          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
6525          has_ddy = true;
6526          break;
6527       case nir_tex_src_ms_index:
6528          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
6529          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
6530          has_sample_index = true;
6531          break;
6532       case nir_tex_src_texture_offset:
6533       case nir_tex_src_sampler_offset:
6534       default:
6535          break;
6536       }
6537    }
6538 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
6539    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
6540       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
6541
6542    if (instr->op == nir_texop_texture_samples) {
6543       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
6544
6545       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
6546       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
6547       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
6548       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
6549
6550       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6551                samples, Operand(1u), bld.scc(is_msaa));
6552       return;
6553    }
6554
6555    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
6556       aco_ptr<Instruction> tmp_instr;
6557       Temp acc, pack = Temp();
6558
6559       uint32_t pack_const = 0;
6560       for (unsigned i = 0; i < offset.size(); i++) {
6561          if (!const_offset[i])
6562             continue;
6563          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
6564       }
6565
6566       if (offset.type() == RegType::sgpr) {
6567          for (unsigned i = 0; i < offset.size(); i++) {
6568             if (const_offset[i])
6569                continue;
6570
6571             acc = emit_extract_vector(ctx, offset, i, s1);
6572             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
6573
6574             if (i) {
6575                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
6576             }
6577
6578             if (pack == Temp()) {
6579                pack = acc;
6580             } else {
6581                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
6582             }
6583          }
6584
6585          if (pack_const && pack != Temp())
6586             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
6587       } else {
6588          for (unsigned i = 0; i < offset.size(); i++) {
6589             if (const_offset[i])
6590                continue;
6591
6592             acc = emit_extract_vector(ctx, offset, i, v1);
6593             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
6594
6595             if (i) {
6596                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
6597             }
6598
6599             if (pack == Temp()) {
6600                pack = acc;
6601             } else {
6602                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
6603             }
6604          }
6605
6606          if (pack_const && pack != Temp())
6607             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
6608       }
6609       if (pack_const && pack == Temp())
6610          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
6611       else if (pack == Temp())
6612          has_offset = false;
6613       else
6614          offset = pack;
6615    }
6616
6617    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
6618       prepare_cube_coords(ctx, &coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
6619
6620    /* pack derivatives */
6621    if (has_ddx || has_ddy) {
6622       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
6623          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(v4),
6624                              ddx, Operand(0u), ddy, Operand(0u));
6625       } else {
6626          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, ddx.size() + ddy.size()), ddx, ddy);
6627       }
6628       has_derivs = true;
6629    }
6630
6631    if (instr->coord_components > 1 &&
6632        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6633        instr->is_array &&
6634        instr->op != nir_texop_txf)
6635       coords = apply_round_slice(ctx, coords, 1);
6636
6637    if (instr->coord_components > 2 &&
6638       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
6639        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6640        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
6641        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6642        instr->is_array &&
6643        instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms)
6644       coords = apply_round_slice(ctx, coords, 2);
6645
6646    if (ctx->options->chip_class == GFX9 &&
6647        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6648        instr->op != nir_texop_lod && instr->coord_components) {
6649       assert(coords.size() > 0 && coords.size() < 3);
6650
6651       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size() + 1, 1)};
6652       vec->operands[0] = Operand(emit_extract_vector(ctx, coords, 0, v1));
6653       vec->operands[1] = instr->op == nir_texop_txf ? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
6654       if (coords.size() > 1)
6655          vec->operands[2] = Operand(emit_extract_vector(ctx, coords, 1, v1));
6656       coords = bld.tmp(RegType::vgpr, coords.size() + 1);
6657       vec->definitions[0] = Definition(coords);
6658       ctx->block->instructions.emplace_back(std::move(vec));
6659    }
6660
6661    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
6662
6663    if (instr->op == nir_texop_samples_identical)
6664       resource = fmask_ptr;
6665
6666    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6667              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6668             instr->op != nir_texop_txs) {
6669       assert(has_sample_index);
6670       Operand op(sample_index);
6671       if (sample_index_cv)
6672          op = Operand(sample_index_cv->u32);
6673       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
6674    }
6675
6676    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
6677       Temp split_coords[coords.size()];
6678       emit_split_vector(ctx, coords, coords.size());
6679       for (unsigned i = 0; i < coords.size(); i++)
6680          split_coords[i] = emit_extract_vector(ctx, coords, i, v1);
6681
6682       unsigned i = 0;
6683       for (; i < std::min(offset.size(), instr->coord_components); i++) {
6684          Temp off = emit_extract_vector(ctx, offset, i, v1);
6685          split_coords[i] = bld.vadd32(bld.def(v1), split_coords[i], off);
6686       }
6687
6688       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6689       for (unsigned i = 0; i < coords.size(); i++)
6690          vec->operands[i] = Operand(split_coords[i]);
6691       coords = bld.tmp(coords.regClass());
6692       vec->definitions[0] = Definition(coords);
6693       ctx->block->instructions.emplace_back(std::move(vec));
6694
6695       has_offset = false;
6696    }
6697
6698    /* Build tex instruction */
6699    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
6700    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
6701                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
6702                   : 0;
6703    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6704    Temp tmp_dst = dst;
6705
6706    /* gather4 selects the component by dmask and always returns vec4 */
6707    if (instr->op == nir_texop_tg4) {
6708       assert(instr->dest.ssa.num_components == 4);
6709       if (instr->is_shadow)
6710          dmask = 1;
6711       else
6712          dmask = 1 << instr->component;
6713       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
6714          tmp_dst = bld.tmp(v4);
6715    } else if (instr->op == nir_texop_samples_identical) {
6716       tmp_dst = bld.tmp(v1);
6717    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
6718       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
6719    }
6720
6721    aco_ptr<MIMG_instruction> tex;
6722    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
6723       if (!has_lod)
6724          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6725
6726       bool div_by_6 = instr->op == nir_texop_txs &&
6727                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
6728                       instr->is_array &&
6729                       (dmask & (1 << 2));
6730       if (tmp_dst.id() == dst.id() && div_by_6)
6731          tmp_dst = bld.tmp(tmp_dst.regClass());
6732
6733       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6734       tex->operands[0] = Operand(as_vgpr(ctx,lod));
6735       tex->operands[1] = Operand(resource);
6736       if (ctx->options->chip_class == GFX9 &&
6737           instr->op == nir_texop_txs &&
6738           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6739           instr->is_array) {
6740          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
6741       } else if (instr->op == nir_texop_query_levels) {
6742          tex->dmask = 1 << 3;
6743       } else {
6744          tex->dmask = dmask;
6745       }
6746       tex->da = da;
6747       tex->definitions[0] = Definition(tmp_dst);
6748       tex->dim = dim;
6749       tex->can_reorder = true;
6750       ctx->block->instructions.emplace_back(std::move(tex));
6751
6752       if (div_by_6) {
6753          /* divide 3rd value by 6 by multiplying with magic number */
6754          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6755          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
6756          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
6757          assert(instr->dest.ssa.num_components == 3);
6758          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
6759          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6760                               emit_extract_vector(ctx, tmp_dst, 0, v1),
6761                               emit_extract_vector(ctx, tmp_dst, 1, v1),
6762                               by_6);
6763
6764       }
6765
6766       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6767       return;
6768    }
6769
6770    Temp tg4_compare_cube_wa64 = Temp();
6771
6772    if (tg4_integer_workarounds) {
6773       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6774       tex->operands[0] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6775       tex->operands[1] = Operand(resource);
6776       tex->dim = dim;
6777       tex->dmask = 0x3;
6778       tex->da = da;
6779       Temp size = bld.tmp(v2);
6780       tex->definitions[0] = Definition(size);
6781       tex->can_reorder = true;
6782       ctx->block->instructions.emplace_back(std::move(tex));
6783       emit_split_vector(ctx, size, size.size());
6784
6785       Temp half_texel[2];
6786       for (unsigned i = 0; i < 2; i++) {
6787          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
6788          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
6789          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
6790          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
6791       }
6792
6793       Temp orig_coords[2] = {
6794          emit_extract_vector(ctx, coords, 0, v1),
6795          emit_extract_vector(ctx, coords, 1, v1)};
6796       Temp new_coords[2] = {
6797          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[0], half_texel[0]),
6798          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[1], half_texel[1])
6799       };
6800
6801       if (tg4_integer_cube_workaround) {
6802          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
6803          Temp desc[resource.size()];
6804          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
6805                                                                            Format::PSEUDO, 1, resource.size())};
6806          split->operands[0] = Operand(resource);
6807          for (unsigned i = 0; i < resource.size(); i++) {
6808             desc[i] = bld.tmp(s1);
6809             split->definitions[i] = Definition(desc[i]);
6810          }
6811          ctx->block->instructions.emplace_back(std::move(split));
6812
6813          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
6814          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
6815                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
6816
6817          Temp nfmt;
6818          if (stype == GLSL_TYPE_UINT) {
6819             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6820                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
6821                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
6822                             bld.scc(compare_cube_wa));
6823          } else {
6824             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6825                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
6826                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
6827                             bld.scc(compare_cube_wa));
6828          }
6829          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
6830          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
6831
6832          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
6833
6834          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
6835                             Operand((uint32_t)C_008F14_NUM_FORMAT));
6836          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
6837
6838          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6839                                                                          Format::PSEUDO, resource.size(), 1)};
6840          for (unsigned i = 0; i < resource.size(); i++)
6841             vec->operands[i] = Operand(desc[i]);
6842          resource = bld.tmp(resource.regClass());
6843          vec->definitions[0] = Definition(resource);
6844          ctx->block->instructions.emplace_back(std::move(vec));
6845
6846          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6847                                   new_coords[0], orig_coords[0], tg4_compare_cube_wa64);
6848          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6849                                   new_coords[1], orig_coords[1], tg4_compare_cube_wa64);
6850       }
6851
6852       if (coords.size() == 3) {
6853          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3),
6854                              new_coords[0], new_coords[1],
6855                              emit_extract_vector(ctx, coords, 2, v1));
6856       } else {
6857          assert(coords.size() == 2);
6858          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2),
6859                              new_coords[0], new_coords[1]);
6860       }
6861    }
6862
6863    std::vector<Operand> args;
6864    if (has_offset)
6865       args.emplace_back(Operand(offset));
6866    if (has_bias)
6867       args.emplace_back(Operand(bias));
6868    if (has_compare)
6869       args.emplace_back(Operand(compare));
6870    if (has_derivs)
6871       args.emplace_back(Operand(derivs));
6872    args.emplace_back(Operand(coords));
6873    if (has_sample_index)
6874       args.emplace_back(Operand(sample_index));
6875    if (has_lod)
6876       args.emplace_back(lod);
6877
6878    Temp arg;
6879    if (args.size() > 1) {
6880       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
6881       unsigned size = 0;
6882       for (unsigned i = 0; i < args.size(); i++) {
6883          size += args[i].size();
6884          vec->operands[i] = args[i];
6885       }
6886       RegClass rc = RegClass(RegType::vgpr, size);
6887       Temp tmp = bld.tmp(rc);
6888       vec->definitions[0] = Definition(tmp);
6889       ctx->block->instructions.emplace_back(std::move(vec));
6890       arg = tmp;
6891    } else {
6892       assert(args[0].isTemp());
6893       arg = as_vgpr(ctx, args[0].getTemp());
6894    }
6895
6896    /* we don't need the bias, sample index, compare value or offset to be
6897     * computed in WQM but if the p_create_vector copies the coordinates, then it
6898     * needs to be in WQM */
6899    if (!(has_ddx && has_ddy) && !has_lod && !level_zero &&
6900        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
6901        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
6902       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
6903
6904    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
6905       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
6906
6907       assert(coords.size() == 1);
6908       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
6909       aco_opcode op;
6910       switch (last_bit) {
6911       case 1:
6912          op = aco_opcode::buffer_load_format_x; break;
6913       case 2:
6914          op = aco_opcode::buffer_load_format_xy; break;
6915       case 3:
6916          op = aco_opcode::buffer_load_format_xyz; break;
6917       case 4:
6918          op = aco_opcode::buffer_load_format_xyzw; break;
6919       default:
6920          unreachable("Tex instruction loads more than 4 components.");
6921       }
6922
6923       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
6924       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
6925          tmp_dst = dst;
6926       else
6927          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
6928
6929       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
6930       mubuf->operands[0] = Operand(coords);
6931       mubuf->operands[1] = Operand(resource);
6932       mubuf->operands[2] = Operand((uint32_t) 0);
6933       mubuf->definitions[0] = Definition(tmp_dst);
6934       mubuf->idxen = true;
6935       mubuf->can_reorder = true;
6936       ctx->block->instructions.emplace_back(std::move(mubuf));
6937
6938       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
6939       return;
6940    }
6941
6942
6943    if (instr->op == nir_texop_txf ||
6944        instr->op == nir_texop_txf_ms ||
6945        instr->op == nir_texop_samples_identical) {
6946       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
6947       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 2, 1));
6948       tex->operands[0] = Operand(arg);
6949       tex->operands[1] = Operand(resource);
6950       tex->dim = dim;
6951       tex->dmask = dmask;
6952       tex->unrm = true;
6953       tex->da = da;
6954       tex->definitions[0] = Definition(tmp_dst);
6955       tex->can_reorder = true;
6956       ctx->block->instructions.emplace_back(std::move(tex));
6957
6958       if (instr->op == nir_texop_samples_identical) {
6959          assert(dmask == 1 && dst.regClass() == v1);
6960          assert(dst.id() != tmp_dst.id());
6961
6962          Temp tmp = bld.tmp(bld.lm);
6963          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
6964          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
6965
6966       } else {
6967          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6968       }
6969       return;
6970    }
6971
6972    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
6973    aco_opcode opcode = aco_opcode::image_sample;
6974    if (has_offset) { /* image_sample_*_o */
6975       if (has_compare) {
6976          opcode = aco_opcode::image_sample_c_o;
6977          if (has_derivs)
6978             opcode = aco_opcode::image_sample_c_d_o;
6979          if (has_bias)
6980             opcode = aco_opcode::image_sample_c_b_o;
6981          if (level_zero)
6982             opcode = aco_opcode::image_sample_c_lz_o;
6983          if (has_lod)
6984             opcode = aco_opcode::image_sample_c_l_o;
6985       } else {
6986          opcode = aco_opcode::image_sample_o;
6987          if (has_derivs)
6988             opcode = aco_opcode::image_sample_d_o;
6989          if (has_bias)
6990             opcode = aco_opcode::image_sample_b_o;
6991          if (level_zero)
6992             opcode = aco_opcode::image_sample_lz_o;
6993          if (has_lod)
6994             opcode = aco_opcode::image_sample_l_o;
6995       }
6996    } else { /* no offset */
6997       if (has_compare) {
6998          opcode = aco_opcode::image_sample_c;
6999          if (has_derivs)
7000             opcode = aco_opcode::image_sample_c_d;
7001          if (has_bias)
7002             opcode = aco_opcode::image_sample_c_b;
7003          if (level_zero)
7004             opcode = aco_opcode::image_sample_c_lz;
7005          if (has_lod)
7006             opcode = aco_opcode::image_sample_c_l;
7007       } else {
7008          opcode = aco_opcode::image_sample;
7009          if (has_derivs)
7010             opcode = aco_opcode::image_sample_d;
7011          if (has_bias)
7012             opcode = aco_opcode::image_sample_b;
7013          if (level_zero)
7014             opcode = aco_opcode::image_sample_lz;
7015          if (has_lod)
7016             opcode = aco_opcode::image_sample_l;
7017       }
7018    }
7019
7020    if (instr->op == nir_texop_tg4) {
7021       if (has_offset) {
7022          opcode = aco_opcode::image_gather4_lz_o;
7023          if (has_compare)
7024             opcode = aco_opcode::image_gather4_c_lz_o;
7025       } else {
7026          opcode = aco_opcode::image_gather4_lz;
7027          if (has_compare)
7028             opcode = aco_opcode::image_gather4_c_lz;
7029       }
7030    } else if (instr->op == nir_texop_lod) {
7031       opcode = aco_opcode::image_get_lod;
7032    }
7033
7034    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
7035    tex->operands[0] = Operand(arg);
7036    tex->operands[1] = Operand(resource);
7037    tex->operands[2] = Operand(sampler);
7038    tex->dim = dim;
7039    tex->dmask = dmask;
7040    tex->da = da;
7041    tex->definitions[0] = Definition(tmp_dst);
7042    tex->can_reorder = true;
7043    ctx->block->instructions.emplace_back(std::move(tex));
7044
7045    if (tg4_integer_cube_workaround) {
7046       assert(tmp_dst.id() != dst.id());
7047       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
7048
7049       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7050       Temp val[4];
7051       for (unsigned i = 0; i < dst.size(); i++) {
7052          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
7053          Temp cvt_val;
7054          if (stype == GLSL_TYPE_UINT)
7055             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
7056          else
7057             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
7058          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
7059       }
7060       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
7061       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7062                            val[0], val[1], val[2], val[3]);
7063    }
7064    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
7065    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
7066
7067 }
7068
7069
7070 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
7071 {
7072    Temp tmp = get_ssa_temp(ctx, ssa);
7073    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
7074       return Operand(tmp.regClass());
7075    else
7076       return Operand(tmp);
7077 }
7078
7079 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
7080 {
7081    aco_ptr<Pseudo_instruction> phi;
7082    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7083    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
7084
7085    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
7086    logical |= ctx->block->kind & block_kind_merge;
7087    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
7088
7089    /* we want a sorted list of sources, since the predecessor list is also sorted */
7090    std::map<unsigned, nir_ssa_def*> phi_src;
7091    nir_foreach_phi_src(src, instr)
7092       phi_src[src->pred->index] = src->src.ssa;
7093
7094    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
7095    unsigned num_operands = 0;
7096    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
7097    unsigned num_defined = 0;
7098    unsigned cur_pred_idx = 0;
7099    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
7100       if (cur_pred_idx < preds.size()) {
7101          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
7102          unsigned block = ctx->cf_info.nir_to_aco[src.first];
7103          unsigned skipped = 0;
7104          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
7105             skipped++;
7106          if (cur_pred_idx + skipped < preds.size()) {
7107             for (unsigned i = 0; i < skipped; i++)
7108                operands[num_operands++] = Operand(dst.regClass());
7109             cur_pred_idx += skipped;
7110          } else {
7111             continue;
7112          }
7113       }
7114       cur_pred_idx++;
7115       Operand op = get_phi_operand(ctx, src.second);
7116       operands[num_operands++] = op;
7117       num_defined += !op.isUndefined();
7118    }
7119    /* handle block_kind_continue_or_break at loop exit blocks */
7120    while (cur_pred_idx++ < preds.size())
7121       operands[num_operands++] = Operand(dst.regClass());
7122
7123    if (num_defined == 0) {
7124       Builder bld(ctx->program, ctx->block);
7125       if (dst.regClass() == s1) {
7126          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
7127       } else if (dst.regClass() == v1) {
7128          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
7129       } else {
7130          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7131          for (unsigned i = 0; i < dst.size(); i++)
7132             vec->operands[i] = Operand(0u);
7133          vec->definitions[0] = Definition(dst);
7134          ctx->block->instructions.emplace_back(std::move(vec));
7135       }
7136       return;
7137    }
7138
7139    /* we can use a linear phi in some cases if one src is undef */
7140    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
7141       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
7142
7143       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
7144       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
7145       assert(invert->kind & block_kind_invert);
7146
7147       unsigned then_block = invert->linear_preds[0];
7148
7149       Block* insert_block = NULL;
7150       for (unsigned i = 0; i < num_operands; i++) {
7151          Operand op = operands[i];
7152          if (op.isUndefined())
7153             continue;
7154          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
7155          phi->operands[0] = op;
7156          break;
7157       }
7158       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
7159       phi->operands[1] = Operand(dst.regClass());
7160       phi->definitions[0] = Definition(dst);
7161       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
7162       return;
7163    }
7164
7165    /* try to scalarize vector phis */
7166    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
7167       // TODO: scalarize linear phis on divergent ifs
7168       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
7169       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
7170       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
7171          Operand src = operands[i];
7172          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
7173             can_scalarize = false;
7174       }
7175       if (can_scalarize) {
7176          unsigned num_components = instr->dest.ssa.num_components;
7177          assert(dst.size() % num_components == 0);
7178          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
7179
7180          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
7181          for (unsigned k = 0; k < num_components; k++) {
7182             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7183             for (unsigned i = 0; i < num_operands; i++) {
7184                Operand src = operands[i];
7185                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
7186             }
7187             Temp phi_dst = {ctx->program->allocateId(), rc};
7188             phi->definitions[0] = Definition(phi_dst);
7189             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7190             new_vec[k] = phi_dst;
7191             vec->operands[k] = Operand(phi_dst);
7192          }
7193          vec->definitions[0] = Definition(dst);
7194          ctx->block->instructions.emplace_back(std::move(vec));
7195          ctx->allocated_vec.emplace(dst.id(), new_vec);
7196          return;
7197       }
7198    }
7199
7200    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7201    for (unsigned i = 0; i < num_operands; i++)
7202       phi->operands[i] = operands[i];
7203    phi->definitions[0] = Definition(dst);
7204    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7205 }
7206
7207
7208 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
7209 {
7210    Temp dst = get_ssa_temp(ctx, &instr->def);
7211
7212    assert(dst.type() == RegType::sgpr);
7213
7214    if (dst.size() == 1) {
7215       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
7216    } else {
7217       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7218       for (unsigned i = 0; i < dst.size(); i++)
7219          vec->operands[i] = Operand(0u);
7220       vec->definitions[0] = Definition(dst);
7221       ctx->block->instructions.emplace_back(std::move(vec));
7222    }
7223 }
7224
7225 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
7226 {
7227    Builder bld(ctx->program, ctx->block);
7228    Block *logical_target;
7229    append_logical_end(ctx->block);
7230    unsigned idx = ctx->block->index;
7231
7232    switch (instr->type) {
7233    case nir_jump_break:
7234       logical_target = ctx->cf_info.parent_loop.exit;
7235       add_logical_edge(idx, logical_target);
7236       ctx->block->kind |= block_kind_break;
7237
7238       if (!ctx->cf_info.parent_if.is_divergent &&
7239           !ctx->cf_info.parent_loop.has_divergent_continue) {
7240          /* uniform break - directly jump out of the loop */
7241          ctx->block->kind |= block_kind_uniform;
7242          ctx->cf_info.has_branch = true;
7243          bld.branch(aco_opcode::p_branch);
7244          add_linear_edge(idx, logical_target);
7245          return;
7246       }
7247       ctx->cf_info.parent_loop.has_divergent_branch = true;
7248       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7249       break;
7250    case nir_jump_continue:
7251       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7252       add_logical_edge(idx, logical_target);
7253       ctx->block->kind |= block_kind_continue;
7254
7255       if (ctx->cf_info.parent_if.is_divergent) {
7256          /* for potential uniform breaks after this continue,
7257             we must ensure that they are handled correctly */
7258          ctx->cf_info.parent_loop.has_divergent_continue = true;
7259          ctx->cf_info.parent_loop.has_divergent_branch = true;
7260          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7261       } else {
7262          /* uniform continue - directly jump to the loop header */
7263          ctx->block->kind |= block_kind_uniform;
7264          ctx->cf_info.has_branch = true;
7265          bld.branch(aco_opcode::p_branch);
7266          add_linear_edge(idx, logical_target);
7267          return;
7268       }
7269       break;
7270    default:
7271       fprintf(stderr, "Unknown NIR jump instr: ");
7272       nir_print_instr(&instr->instr, stderr);
7273       fprintf(stderr, "\n");
7274       abort();
7275    }
7276
7277    /* remove critical edges from linear CFG */
7278    bld.branch(aco_opcode::p_branch);
7279    Block* break_block = ctx->program->create_and_insert_block();
7280    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7281    break_block->kind |= block_kind_uniform;
7282    add_linear_edge(idx, break_block);
7283    /* the loop_header pointer might be invalidated by this point */
7284    if (instr->type == nir_jump_continue)
7285       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7286    add_linear_edge(break_block->index, logical_target);
7287    bld.reset(break_block);
7288    bld.branch(aco_opcode::p_branch);
7289
7290    Block* continue_block = ctx->program->create_and_insert_block();
7291    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7292    add_linear_edge(idx, continue_block);
7293    append_logical_start(continue_block);
7294    ctx->block = continue_block;
7295    return;
7296 }
7297
7298 void visit_block(isel_context *ctx, nir_block *block)
7299 {
7300    nir_foreach_instr(instr, block) {
7301       switch (instr->type) {
7302       case nir_instr_type_alu:
7303          visit_alu_instr(ctx, nir_instr_as_alu(instr));
7304          break;
7305       case nir_instr_type_load_const:
7306          visit_load_const(ctx, nir_instr_as_load_const(instr));
7307          break;
7308       case nir_instr_type_intrinsic:
7309          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
7310          break;
7311       case nir_instr_type_tex:
7312          visit_tex(ctx, nir_instr_as_tex(instr));
7313          break;
7314       case nir_instr_type_phi:
7315          visit_phi(ctx, nir_instr_as_phi(instr));
7316          break;
7317       case nir_instr_type_ssa_undef:
7318          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
7319          break;
7320       case nir_instr_type_deref:
7321          break;
7322       case nir_instr_type_jump:
7323          visit_jump(ctx, nir_instr_as_jump(instr));
7324          break;
7325       default:
7326          fprintf(stderr, "Unknown NIR instr type: ");
7327          nir_print_instr(instr, stderr);
7328          fprintf(stderr, "\n");
7329          //abort();
7330       }
7331    }
7332
7333    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7334       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
7335 }
7336
7337
7338
7339 static void visit_loop(isel_context *ctx, nir_loop *loop)
7340 {
7341    append_logical_end(ctx->block);
7342    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
7343    Builder bld(ctx->program, ctx->block);
7344    bld.branch(aco_opcode::p_branch);
7345    unsigned loop_preheader_idx = ctx->block->index;
7346
7347    Block loop_exit = Block();
7348    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7349    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
7350
7351    Block* loop_header = ctx->program->create_and_insert_block();
7352    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
7353    loop_header->kind |= block_kind_loop_header;
7354    add_edge(loop_preheader_idx, loop_header);
7355    ctx->block = loop_header;
7356
7357    /* emit loop body */
7358    unsigned loop_header_idx = loop_header->index;
7359    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
7360    append_logical_start(ctx->block);
7361    visit_cf_list(ctx, &loop->body);
7362
7363    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
7364    if (!ctx->cf_info.has_branch) {
7365       append_logical_end(ctx->block);
7366       if (ctx->cf_info.exec_potentially_empty) {
7367          /* Discards can result in code running with an empty exec mask.
7368           * This would result in divergent breaks not ever being taken. As a
7369           * workaround, break the loop when the loop mask is empty instead of
7370           * always continuing. */
7371          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
7372          unsigned block_idx = ctx->block->index;
7373
7374          /* create helper blocks to avoid critical edges */
7375          Block *break_block = ctx->program->create_and_insert_block();
7376          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7377          break_block->kind = block_kind_uniform;
7378          bld.reset(break_block);
7379          bld.branch(aco_opcode::p_branch);
7380          add_linear_edge(block_idx, break_block);
7381          add_linear_edge(break_block->index, &loop_exit);
7382
7383          Block *continue_block = ctx->program->create_and_insert_block();
7384          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7385          continue_block->kind = block_kind_uniform;
7386          bld.reset(continue_block);
7387          bld.branch(aco_opcode::p_branch);
7388          add_linear_edge(block_idx, continue_block);
7389          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
7390
7391          add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
7392          ctx->block = &ctx->program->blocks[block_idx];
7393       } else {
7394          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
7395          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7396             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7397          else
7398             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7399       }
7400
7401       bld.reset(ctx->block);
7402       bld.branch(aco_opcode::p_branch);
7403    }
7404
7405    /* fixup phis in loop header from unreachable blocks */
7406    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
7407       bool linear = ctx->cf_info.has_branch;
7408       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
7409       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
7410          if ((logical && instr->opcode == aco_opcode::p_phi) ||
7411              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
7412             /* the last operand should be the one that needs to be removed */
7413             instr->operands.pop_back();
7414          } else if (!is_phi(instr)) {
7415             break;
7416          }
7417       }
7418    }
7419
7420    ctx->cf_info.has_branch = false;
7421
7422    // TODO: if the loop has not a single exit, we must add one °°
7423    /* emit loop successor block */
7424    ctx->block = ctx->program->insert_block(std::move(loop_exit));
7425    append_logical_start(ctx->block);
7426
7427    #if 0
7428    // TODO: check if it is beneficial to not branch on continues
7429    /* trim linear phis in loop header */
7430    for (auto&& instr : loop_entry->instructions) {
7431       if (instr->opcode == aco_opcode::p_linear_phi) {
7432          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
7433          new_phi->definitions[0] = instr->definitions[0];
7434          for (unsigned i = 0; i < new_phi->operands.size(); i++)
7435             new_phi->operands[i] = instr->operands[i];
7436          /* check that the remaining operands are all the same */
7437          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
7438             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
7439          instr.swap(new_phi);
7440       } else if (instr->opcode == aco_opcode::p_phi) {
7441          continue;
7442       } else {
7443          break;
7444       }
7445    }
7446    #endif
7447 }
7448
7449 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
7450 {
7451    ic->cond = cond;
7452
7453    append_logical_end(ctx->block);
7454    ctx->block->kind |= block_kind_branch;
7455
7456    /* branch to linear then block */
7457    assert(cond.regClass() == ctx->program->lane_mask);
7458    aco_ptr<Pseudo_branch_instruction> branch;
7459    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7460    branch->operands[0] = Operand(cond);
7461    ctx->block->instructions.push_back(std::move(branch));
7462
7463    ic->BB_if_idx = ctx->block->index;
7464    ic->BB_invert = Block();
7465    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7466    /* Invert blocks are intentionally not marked as top level because they
7467     * are not part of the logical cfg. */
7468    ic->BB_invert.kind |= block_kind_invert;
7469    ic->BB_endif = Block();
7470    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7471    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
7472
7473    ic->exec_potentially_empty_old = ctx->cf_info.exec_potentially_empty;
7474    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
7475    ctx->cf_info.parent_if.is_divergent = true;
7476    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7477
7478    /** emit logical then block */
7479    Block* BB_then_logical = ctx->program->create_and_insert_block();
7480    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7481    add_edge(ic->BB_if_idx, BB_then_logical);
7482    ctx->block = BB_then_logical;
7483    append_logical_start(BB_then_logical);
7484 }
7485
7486 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
7487 {
7488    Block *BB_then_logical = ctx->block;
7489    append_logical_end(BB_then_logical);
7490     /* branch from logical then block to invert block */
7491    aco_ptr<Pseudo_branch_instruction> branch;
7492    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7493    BB_then_logical->instructions.emplace_back(std::move(branch));
7494    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
7495    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7496       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
7497    BB_then_logical->kind |= block_kind_uniform;
7498    assert(!ctx->cf_info.has_branch);
7499    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7500    ctx->cf_info.parent_loop.has_divergent_branch = false;
7501
7502    /** emit linear then block */
7503    Block* BB_then_linear = ctx->program->create_and_insert_block();
7504    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7505    BB_then_linear->kind |= block_kind_uniform;
7506    add_linear_edge(ic->BB_if_idx, BB_then_linear);
7507    /* branch from linear then block to invert block */
7508    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7509    BB_then_linear->instructions.emplace_back(std::move(branch));
7510    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
7511
7512    /** emit invert merge block */
7513    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
7514    ic->invert_idx = ctx->block->index;
7515
7516    /* branch to linear else block (skip else) */
7517    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
7518    branch->operands[0] = Operand(ic->cond);
7519    ctx->block->instructions.push_back(std::move(branch));
7520
7521    ic->exec_potentially_empty_old |= ctx->cf_info.exec_potentially_empty;
7522    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7523
7524    /** emit logical else block */
7525    Block* BB_else_logical = ctx->program->create_and_insert_block();
7526    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7527    add_logical_edge(ic->BB_if_idx, BB_else_logical);
7528    add_linear_edge(ic->invert_idx, BB_else_logical);
7529    ctx->block = BB_else_logical;
7530    append_logical_start(BB_else_logical);
7531 }
7532
7533 static void end_divergent_if(isel_context *ctx, if_context *ic)
7534 {
7535    Block *BB_else_logical = ctx->block;
7536    append_logical_end(BB_else_logical);
7537
7538    /* branch from logical else block to endif block */
7539    aco_ptr<Pseudo_branch_instruction> branch;
7540    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7541    BB_else_logical->instructions.emplace_back(std::move(branch));
7542    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
7543    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7544       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
7545    BB_else_logical->kind |= block_kind_uniform;
7546
7547    assert(!ctx->cf_info.has_branch);
7548    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
7549
7550
7551    /** emit linear else block */
7552    Block* BB_else_linear = ctx->program->create_and_insert_block();
7553    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7554    BB_else_linear->kind |= block_kind_uniform;
7555    add_linear_edge(ic->invert_idx, BB_else_linear);
7556
7557    /* branch from linear else block to endif block */
7558    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7559    BB_else_linear->instructions.emplace_back(std::move(branch));
7560    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
7561
7562
7563    /** emit endif merge block */
7564    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
7565    append_logical_start(ctx->block);
7566
7567
7568    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
7569    ctx->cf_info.exec_potentially_empty |= ic->exec_potentially_empty_old;
7570    /* uniform control flow never has an empty exec-mask */
7571    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
7572       ctx->cf_info.exec_potentially_empty = false;
7573 }
7574
7575 static void visit_if(isel_context *ctx, nir_if *if_stmt)
7576 {
7577    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
7578    Builder bld(ctx->program, ctx->block);
7579    aco_ptr<Pseudo_branch_instruction> branch;
7580
7581    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
7582       /**
7583        * Uniform conditionals are represented in the following way*) :
7584        *
7585        * The linear and logical CFG:
7586        *                        BB_IF
7587        *                        /    \
7588        *       BB_THEN (logical)      BB_ELSE (logical)
7589        *                        \    /
7590        *                        BB_ENDIF
7591        *
7592        * *) Exceptions may be due to break and continue statements within loops
7593        *    If a break/continue happens within uniform control flow, it branches
7594        *    to the loop exit/entry block. Otherwise, it branches to the next
7595        *    merge block.
7596        **/
7597       append_logical_end(ctx->block);
7598       ctx->block->kind |= block_kind_uniform;
7599
7600       /* emit branch */
7601       assert(cond.regClass() == bld.lm);
7602       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
7603       cond = bool_to_scalar_condition(ctx, cond);
7604
7605       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7606       branch->operands[0] = Operand(cond);
7607       branch->operands[0].setFixed(scc);
7608       ctx->block->instructions.emplace_back(std::move(branch));
7609
7610       unsigned BB_if_idx = ctx->block->index;
7611       Block BB_endif = Block();
7612       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7613       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
7614
7615       /** emit then block */
7616       Block* BB_then = ctx->program->create_and_insert_block();
7617       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7618       add_edge(BB_if_idx, BB_then);
7619       append_logical_start(BB_then);
7620       ctx->block = BB_then;
7621       visit_cf_list(ctx, &if_stmt->then_list);
7622       BB_then = ctx->block;
7623       bool then_branch = ctx->cf_info.has_branch;
7624       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7625
7626       if (!then_branch) {
7627          append_logical_end(BB_then);
7628          /* branch from then block to endif block */
7629          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7630          BB_then->instructions.emplace_back(std::move(branch));
7631          add_linear_edge(BB_then->index, &BB_endif);
7632          if (!then_branch_divergent)
7633             add_logical_edge(BB_then->index, &BB_endif);
7634          BB_then->kind |= block_kind_uniform;
7635       }
7636
7637       ctx->cf_info.has_branch = false;
7638       ctx->cf_info.parent_loop.has_divergent_branch = false;
7639
7640       /** emit else block */
7641       Block* BB_else = ctx->program->create_and_insert_block();
7642       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7643       add_edge(BB_if_idx, BB_else);
7644       append_logical_start(BB_else);
7645       ctx->block = BB_else;
7646       visit_cf_list(ctx, &if_stmt->else_list);
7647       BB_else = ctx->block;
7648
7649       if (!ctx->cf_info.has_branch) {
7650          append_logical_end(BB_else);
7651          /* branch from then block to endif block */
7652          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7653          BB_else->instructions.emplace_back(std::move(branch));
7654          add_linear_edge(BB_else->index, &BB_endif);
7655          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7656             add_logical_edge(BB_else->index, &BB_endif);
7657          BB_else->kind |= block_kind_uniform;
7658       }
7659
7660       ctx->cf_info.has_branch &= then_branch;
7661       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
7662
7663       /** emit endif merge block */
7664       if (!ctx->cf_info.has_branch) {
7665          ctx->block = ctx->program->insert_block(std::move(BB_endif));
7666          append_logical_start(ctx->block);
7667       }
7668    } else { /* non-uniform condition */
7669       /**
7670        * To maintain a logical and linear CFG without critical edges,
7671        * non-uniform conditionals are represented in the following way*) :
7672        *
7673        * The linear CFG:
7674        *                        BB_IF
7675        *                        /    \
7676        *       BB_THEN (logical)      BB_THEN (linear)
7677        *                        \    /
7678        *                        BB_INVERT (linear)
7679        *                        /    \
7680        *       BB_ELSE (logical)      BB_ELSE (linear)
7681        *                        \    /
7682        *                        BB_ENDIF
7683        *
7684        * The logical CFG:
7685        *                        BB_IF
7686        *                        /    \
7687        *       BB_THEN (logical)      BB_ELSE (logical)
7688        *                        \    /
7689        *                        BB_ENDIF
7690        *
7691        * *) Exceptions may be due to break and continue statements within loops
7692        **/
7693
7694       if_context ic;
7695
7696       begin_divergent_if_then(ctx, &ic, cond);
7697       visit_cf_list(ctx, &if_stmt->then_list);
7698
7699       begin_divergent_if_else(ctx, &ic);
7700       visit_cf_list(ctx, &if_stmt->else_list);
7701
7702       end_divergent_if(ctx, &ic);
7703    }
7704 }
7705
7706 static void visit_cf_list(isel_context *ctx,
7707                           struct exec_list *list)
7708 {
7709    foreach_list_typed(nir_cf_node, node, node, list) {
7710       switch (node->type) {
7711       case nir_cf_node_block:
7712          visit_block(ctx, nir_cf_node_as_block(node));
7713          break;
7714       case nir_cf_node_if:
7715          visit_if(ctx, nir_cf_node_as_if(node));
7716          break;
7717       case nir_cf_node_loop:
7718          visit_loop(ctx, nir_cf_node_as_loop(node));
7719          break;
7720       default:
7721          unreachable("unimplemented cf list type");
7722       }
7723    }
7724 }
7725
7726 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
7727 {
7728    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
7729    uint64_t mask = ctx->vs_output.mask[slot];
7730    if (!is_pos && !mask)
7731       return;
7732    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
7733       return;
7734    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7735    exp->enabled_mask = mask;
7736    for (unsigned i = 0; i < 4; ++i) {
7737       if (mask & (1 << i))
7738          exp->operands[i] = Operand(ctx->vs_output.outputs[slot][i]);
7739       else
7740          exp->operands[i] = Operand(v1);
7741    }
7742    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
7743     * Setting valid_mask=1 prevents it and has no other effect.
7744     */
7745    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
7746    exp->done = false;
7747    exp->compressed = false;
7748    if (is_pos)
7749       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7750    else
7751       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
7752    ctx->block->instructions.emplace_back(std::move(exp));
7753 }
7754
7755 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
7756 {
7757    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7758    exp->enabled_mask = 0;
7759    for (unsigned i = 0; i < 4; ++i)
7760       exp->operands[i] = Operand(v1);
7761    if (ctx->vs_output.mask[VARYING_SLOT_PSIZ]) {
7762       exp->operands[0] = Operand(ctx->vs_output.outputs[VARYING_SLOT_PSIZ][0]);
7763       exp->enabled_mask |= 0x1;
7764    }
7765    if (ctx->vs_output.mask[VARYING_SLOT_LAYER]) {
7766       exp->operands[2] = Operand(ctx->vs_output.outputs[VARYING_SLOT_LAYER][0]);
7767       exp->enabled_mask |= 0x4;
7768    }
7769    if (ctx->vs_output.mask[VARYING_SLOT_VIEWPORT]) {
7770       if (ctx->options->chip_class < GFX9) {
7771          exp->operands[3] = Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]);
7772          exp->enabled_mask |= 0x8;
7773       } else {
7774          Builder bld(ctx->program, ctx->block);
7775
7776          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
7777                              Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]));
7778          if (exp->operands[2].isTemp())
7779             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
7780
7781          exp->operands[2] = Operand(out);
7782          exp->enabled_mask |= 0x4;
7783       }
7784    }
7785    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
7786    exp->done = false;
7787    exp->compressed = false;
7788    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7789    ctx->block->instructions.emplace_back(std::move(exp));
7790 }
7791
7792 static void create_vs_exports(isel_context *ctx)
7793 {
7794    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
7795
7796    if (outinfo->export_prim_id) {
7797       ctx->vs_output.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
7798       ctx->vs_output.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
7799    }
7800
7801    if (ctx->options->key.has_multiview_view_index) {
7802       ctx->vs_output.mask[VARYING_SLOT_LAYER] |= 0x1;
7803       ctx->vs_output.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
7804    }
7805
7806    /* the order these position exports are created is important */
7807    int next_pos = 0;
7808    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
7809    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
7810       export_vs_psiz_layer_viewport(ctx, &next_pos);
7811    }
7812    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7813       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
7814    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7815       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
7816
7817    if (ctx->options->key.vs_common_out.export_clip_dists) {
7818       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7819          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
7820       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7821          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
7822    }
7823
7824    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
7825       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
7826           i != VARYING_SLOT_PRIMITIVE_ID)
7827          continue;
7828
7829       export_vs_varying(ctx, i, false, NULL);
7830    }
7831 }
7832
7833 static void emit_stream_output(isel_context *ctx,
7834                                Temp const *so_buffers,
7835                                Temp const *so_write_offset,
7836                                const struct radv_stream_output *output)
7837 {
7838    unsigned num_comps = util_bitcount(output->component_mask);
7839    unsigned loc = output->location;
7840    unsigned buf = output->buffer;
7841    unsigned offset = output->offset;
7842
7843    assert(num_comps && num_comps <= 4);
7844    if (!num_comps || num_comps > 4)
7845       return;
7846
7847    unsigned start = ffs(output->component_mask) - 1;
7848
7849    Temp out[4];
7850    bool all_undef = true;
7851    assert(ctx->stage == vertex_vs);
7852    for (unsigned i = 0; i < num_comps; i++) {
7853       out[i] = ctx->vs_output.outputs[loc][start + i];
7854       all_undef = all_undef && !out[i].id();
7855    }
7856    if (all_undef)
7857       return;
7858
7859    Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_comps)};
7860    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_comps, 1)};
7861    for (unsigned i = 0; i < num_comps; ++i)
7862       vec->operands[i] = (ctx->vs_output.mask[loc] & 1 << i) ? Operand(out[i]) : Operand(0u);
7863    vec->definitions[0] = Definition(write_data);
7864    ctx->block->instructions.emplace_back(std::move(vec));
7865
7866    aco_opcode opcode;
7867    switch (num_comps) {
7868    case 1:
7869       opcode = aco_opcode::buffer_store_dword;
7870       break;
7871    case 2:
7872       opcode = aco_opcode::buffer_store_dwordx2;
7873       break;
7874    case 3:
7875       opcode = aco_opcode::buffer_store_dwordx3;
7876       break;
7877    case 4:
7878       opcode = aco_opcode::buffer_store_dwordx4;
7879       break;
7880    }
7881
7882    aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
7883    store->operands[0] = Operand(so_write_offset[buf]);
7884    store->operands[1] = Operand(so_buffers[buf]);
7885    store->operands[2] = Operand((uint32_t) 0);
7886    store->operands[3] = Operand(write_data);
7887    if (offset > 4095) {
7888       /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
7889       Builder bld(ctx->program, ctx->block);
7890       store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
7891    } else {
7892       store->offset = offset;
7893    }
7894    store->offen = true;
7895    store->glc = true;
7896    store->dlc = false;
7897    store->slc = true;
7898    store->can_reorder = true;
7899    ctx->block->instructions.emplace_back(std::move(store));
7900 }
7901
7902 static void emit_streamout(isel_context *ctx, unsigned stream)
7903 {
7904    Builder bld(ctx->program, ctx->block);
7905
7906    Temp so_buffers[4];
7907    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
7908    for (unsigned i = 0; i < 4; i++) {
7909       unsigned stride = ctx->program->info->so.strides[i];
7910       if (!stride)
7911          continue;
7912
7913       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, Operand(i * 16u));
7914    }
7915
7916    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
7917                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
7918
7919    Temp tid = emit_mbcnt(ctx, bld.def(v1));
7920
7921    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
7922
7923    if_context ic;
7924    begin_divergent_if_then(ctx, &ic, can_emit);
7925
7926    bld.reset(ctx->block);
7927
7928    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
7929
7930    Temp so_write_offset[4];
7931
7932    for (unsigned i = 0; i < 4; i++) {
7933       unsigned stride = ctx->program->info->so.strides[i];
7934       if (!stride)
7935          continue;
7936
7937       if (stride == 1) {
7938          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
7939                                 get_arg(ctx, ctx->args->streamout_write_idx),
7940                                 get_arg(ctx, ctx->args->streamout_offset[i]));
7941          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
7942
7943          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
7944       } else {
7945          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
7946          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
7947                                  get_arg(ctx, ctx->args->streamout_offset[i]));
7948          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
7949       }
7950    }
7951
7952    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
7953       struct radv_stream_output *output =
7954          &ctx->program->info->so.outputs[i];
7955       if (stream != output->stream)
7956          continue;
7957
7958       emit_stream_output(ctx, so_buffers, so_write_offset, output);
7959    }
7960
7961    begin_divergent_if_else(ctx, &ic);
7962    end_divergent_if(ctx, &ic);
7963 }
7964
7965 } /* end namespace */
7966
7967 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
7968 {
7969    /* Split all arguments except for the first (ring_offsets) and the last
7970     * (exec) so that the dead channels don't stay live throughout the program.
7971     */
7972    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
7973       if (startpgm->definitions[i].regClass().size() > 1) {
7974          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
7975                            startpgm->definitions[i].regClass().size());
7976       }
7977    }
7978 }
7979
7980 void handle_bc_optimize(isel_context *ctx)
7981 {
7982    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
7983    Builder bld(ctx->program, ctx->block);
7984    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
7985    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
7986    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
7987    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
7988    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
7989    if (uses_center && uses_centroid) {
7990       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
7991                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
7992
7993       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
7994          Temp new_coord[2];
7995          for (unsigned i = 0; i < 2; i++) {
7996             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
7997             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
7998             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7999                                     persp_centroid, persp_center, sel);
8000          }
8001          ctx->persp_centroid = bld.tmp(v2);
8002          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
8003                     Operand(new_coord[0]), Operand(new_coord[1]));
8004          emit_split_vector(ctx, ctx->persp_centroid, 2);
8005       }
8006
8007       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
8008          Temp new_coord[2];
8009          for (unsigned i = 0; i < 2; i++) {
8010             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
8011             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
8012             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8013                                     linear_centroid, linear_center, sel);
8014          }
8015          ctx->linear_centroid = bld.tmp(v2);
8016          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
8017                     Operand(new_coord[0]), Operand(new_coord[1]));
8018          emit_split_vector(ctx, ctx->linear_centroid, 2);
8019       }
8020    }
8021 }
8022
8023 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
8024 {
8025    Program *program = ctx->program;
8026
8027    unsigned float_controls = shader->info.float_controls_execution_mode;
8028
8029    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
8030       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
8031    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
8032       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
8033                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
8034
8035    program->next_fp_mode.must_flush_denorms32 =
8036       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
8037    program->next_fp_mode.must_flush_denorms16_64 =
8038       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
8039                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
8040
8041    program->next_fp_mode.care_about_round32 =
8042       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
8043
8044    program->next_fp_mode.care_about_round16_64 =
8045       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
8046                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
8047
8048    /* default to preserving fp16 and fp64 denorms, since it's free */
8049    if (program->next_fp_mode.must_flush_denorms16_64)
8050       program->next_fp_mode.denorm16_64 = 0;
8051    else
8052       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
8053
8054    /* preserving fp32 denorms is expensive, so only do it if asked */
8055    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
8056       program->next_fp_mode.denorm32 = fp_denorm_keep;
8057    else
8058       program->next_fp_mode.denorm32 = 0;
8059
8060    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
8061       program->next_fp_mode.round32 = fp_round_tz;
8062    else
8063       program->next_fp_mode.round32 = fp_round_ne;
8064
8065    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
8066       program->next_fp_mode.round16_64 = fp_round_tz;
8067    else
8068       program->next_fp_mode.round16_64 = fp_round_ne;
8069
8070    ctx->block->fp_mode = program->next_fp_mode;
8071 }
8072
8073 void select_program(Program *program,
8074                     unsigned shader_count,
8075                     struct nir_shader *const *shaders,
8076                     ac_shader_config* config,
8077                     struct radv_shader_args *args)
8078 {
8079    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args);
8080
8081    for (unsigned i = 0; i < shader_count; i++) {
8082       nir_shader *nir = shaders[i];
8083       init_context(&ctx, nir);
8084
8085       setup_fp_mode(&ctx, nir);
8086
8087       if (!i) {
8088          /* needs to be after init_context() for FS */
8089          Pseudo_instruction *startpgm = add_startpgm(&ctx);
8090          append_logical_start(ctx.block);
8091          split_arguments(&ctx, startpgm);
8092       }
8093
8094       if_context ic;
8095       if (shader_count >= 2) {
8096          Builder bld(ctx.program, ctx.block);
8097          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), ctx.merged_wave_info, Operand((8u << 16) | (i * 8u)));
8098          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
8099          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
8100
8101          begin_divergent_if_then(&ctx, &ic, cond);
8102       }
8103
8104       if (i) {
8105          Builder bld(ctx.program, ctx.block);
8106          bld.barrier(aco_opcode::p_memory_barrier_shared); //TODO: different barriers are needed for different stages
8107          bld.sopp(aco_opcode::s_barrier);
8108       }
8109
8110       if (ctx.stage == fragment_fs)
8111          handle_bc_optimize(&ctx);
8112
8113       nir_function_impl *func = nir_shader_get_entrypoint(nir);
8114       visit_cf_list(&ctx, &func->body);
8115
8116       if (ctx.program->info->so.num_outputs/*&& !ctx->is_gs_copy_shader */)
8117          emit_streamout(&ctx, 0);
8118
8119       if (ctx.stage == vertex_vs)
8120          create_vs_exports(&ctx);
8121
8122       if (shader_count >= 2) {
8123          begin_divergent_if_else(&ctx, &ic);
8124          end_divergent_if(&ctx, &ic);
8125       }
8126
8127       ralloc_free(ctx.divergent_vals);
8128    }
8129
8130    program->config->float_mode = program->blocks[0].fp_mode.val;
8131
8132    append_logical_end(ctx.block);
8133    ctx.block->kind |= block_kind_uniform;
8134    Builder bld(ctx.program, ctx.block);
8135    if (ctx.program->wb_smem_l1_on_end)
8136       bld.smem(aco_opcode::s_dcache_wb, false);
8137    bld.sopp(aco_opcode::s_endpgm);
8138
8139    /* cleanup CFG */
8140    for (Block& BB : program->blocks) {
8141       for (unsigned idx : BB.linear_preds)
8142          program->blocks[idx].linear_succs.emplace_back(BB.index);
8143       for (unsigned idx : BB.logical_preds)
8144          program->blocks[idx].logical_succs.emplace_back(BB.index);
8145    }
8146 }
8147 }