2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 #define isel_err(...) _isel_err(ctx, __FILE__, __LINE__, __VA_ARGS__)
43 static void _isel_err(isel_context
*ctx
, const char *file
, unsigned line
,
44 const nir_instr
*instr
, const char *msg
)
48 FILE *memf
= open_memstream(&out
, &outsize
);
50 fprintf(memf
, "%s: ", msg
);
51 nir_print_instr(instr
, memf
);
54 _aco_err(ctx
->program
, file
, line
, out
);
58 class loop_info_RAII
{
60 unsigned header_idx_old
;
62 bool divergent_cont_old
;
63 bool divergent_branch_old
;
64 bool divergent_if_old
;
67 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
69 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
70 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
71 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
72 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
75 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
76 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
77 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
78 ctx
->cf_info
.parent_if
.is_divergent
= false;
79 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
84 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
85 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
86 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
87 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
88 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
89 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
90 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
91 ctx
->cf_info
.exec_potentially_empty_discard
= false;
99 bool exec_potentially_empty_discard_old
;
100 bool exec_potentially_empty_break_old
;
101 uint16_t exec_potentially_empty_break_depth_old
;
105 bool uniform_has_then_branch
;
106 bool then_branch_divergent
;
111 static bool visit_cf_list(struct isel_context
*ctx
,
112 struct exec_list
*list
);
114 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
116 succ
->logical_preds
.emplace_back(pred_idx
);
120 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
122 succ
->linear_preds
.emplace_back(pred_idx
);
125 static void add_edge(unsigned pred_idx
, Block
*succ
)
127 add_logical_edge(pred_idx
, succ
);
128 add_linear_edge(pred_idx
, succ
);
131 static void append_logical_start(Block
*b
)
133 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
136 static void append_logical_end(Block
*b
)
138 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
141 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
143 assert(ctx
->allocated
[def
->index
].id());
144 return ctx
->allocated
[def
->index
];
147 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
148 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
150 Builder
bld(ctx
->program
, ctx
->block
);
151 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
152 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
154 if (ctx
->program
->wave_size
== 32) {
156 } else if (ctx
->program
->chip_class
<= GFX7
) {
157 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
160 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
165 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
167 Builder
bld(ctx
->program
, ctx
->block
);
170 dst
= bld
.tmp(src
.regClass());
172 assert(src
.size() == dst
.size());
174 if (ctx
->stage
!= fragment_fs
) {
178 bld
.copy(Definition(dst
), src
);
182 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
183 ctx
->program
->needs_wqm
|= program_needs_wqm
;
187 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
189 if (index
.regClass() == s1
)
190 return bld
.readlane(bld
.def(s1
), data
, index
);
192 if (ctx
->options
->chip_class
<= GFX7
) {
193 /* GFX6-7: there is no bpermute instruction */
194 Operand
index_op(index
);
195 Operand
input_data(data
);
196 index_op
.setLateKill(true);
197 input_data
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
200 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
201 /* GFX10 wave64 mode: emulate full-wave bpermute */
202 if (!ctx
->has_gfx10_wave64_bpermute
) {
203 ctx
->has_gfx10_wave64_bpermute
= true;
204 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
205 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
208 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
209 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
210 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
211 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
212 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
213 Operand
input_data(data
);
215 index_x4
.setLateKill(true);
216 input_data
.setLateKill(true);
217 same_half
.setLateKill(true);
219 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
221 /* GFX8-9 or GFX10 wave32: bpermute works normally */
222 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
223 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
227 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
229 if (ctx
->options
->chip_class
>= GFX8
) {
230 unsigned and_mask
= mask
& 0x1f;
231 unsigned or_mask
= (mask
>> 5) & 0x1f;
232 unsigned xor_mask
= (mask
>> 10) & 0x1f;
234 uint16_t dpp_ctrl
= 0xffff;
236 // TODO: we could use DPP8 for some swizzles
237 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
238 unsigned res
[4] = {0, 1, 2, 3};
239 for (unsigned i
= 0; i
< 4; i
++)
240 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
241 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
242 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
243 dpp_ctrl
= dpp_row_rr(8);
244 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
245 dpp_ctrl
= dpp_row_mirror
;
246 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
247 dpp_ctrl
= dpp_row_half_mirror
;
250 if (dpp_ctrl
!= 0xffff)
251 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
254 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
257 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
259 if (val
.type() == RegType::sgpr
) {
260 Builder
bld(ctx
->program
, ctx
->block
);
261 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
263 assert(val
.type() == RegType::vgpr
);
267 //assumes a != 0xffffffff
268 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
271 Builder
bld(ctx
->program
, ctx
->block
);
273 if (util_is_power_of_two_or_zero(b
)) {
274 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
278 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
280 assert(info
.multiplier
<= 0xffffffff);
282 bool pre_shift
= info
.pre_shift
!= 0;
283 bool increment
= info
.increment
!= 0;
284 bool multiply
= true;
285 bool post_shift
= info
.post_shift
!= 0;
287 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
288 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
292 Temp pre_shift_dst
= a
;
294 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
298 Temp increment_dst
= pre_shift_dst
;
300 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
301 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
304 Temp multiply_dst
= increment_dst
;
306 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
307 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
308 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
312 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
316 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
318 Builder
bld(ctx
->program
, ctx
->block
);
319 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
323 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
325 /* no need to extract the whole vector */
326 if (src
.regClass() == dst_rc
) {
331 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
332 Builder
bld(ctx
->program
, ctx
->block
);
333 auto it
= ctx
->allocated_vec
.find(src
.id());
334 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
335 if (it
->second
[idx
].regClass() == dst_rc
) {
336 return it
->second
[idx
];
338 assert(!dst_rc
.is_subdword());
339 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
340 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
344 if (dst_rc
.is_subdword())
345 src
= as_vgpr(ctx
, src
);
347 if (src
.bytes() == dst_rc
.bytes()) {
349 return bld
.copy(bld
.def(dst_rc
), src
);
351 Temp dst
= bld
.tmp(dst_rc
);
352 emit_extract_vector(ctx
, src
, idx
, dst
);
357 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
359 if (num_components
== 1)
361 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
364 if (num_components
> vec_src
.size()) {
365 if (vec_src
.type() == RegType::sgpr
) {
366 /* should still help get_alu_src() */
367 emit_split_vector(ctx
, vec_src
, vec_src
.size());
370 /* sub-dword split */
371 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
373 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
375 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
376 split
->operands
[0] = Operand(vec_src
);
377 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
378 for (unsigned i
= 0; i
< num_components
; i
++) {
379 elems
[i
] = {ctx
->program
->allocateId(), rc
};
380 split
->definitions
[i
] = Definition(elems
[i
]);
382 ctx
->block
->instructions
.emplace_back(std::move(split
));
383 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
386 /* This vector expansion uses a mask to determine which elements in the new vector
387 * come from the original vector. The other elements are undefined. */
388 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
390 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
395 Builder
bld(ctx
->program
, ctx
->block
);
396 if (num_components
== 1) {
397 if (dst
.type() == RegType::sgpr
)
398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
400 bld
.copy(Definition(dst
), vec_src
);
404 unsigned component_size
= dst
.size() / num_components
;
405 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
407 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
408 vec
->definitions
[0] = Definition(dst
);
410 for (unsigned i
= 0; i
< num_components
; i
++) {
411 if (mask
& (1 << i
)) {
412 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
413 if (dst
.type() == RegType::sgpr
)
414 src
= bld
.as_uniform(src
);
415 vec
->operands
[i
] = Operand(src
);
417 vec
->operands
[i
] = Operand(0u);
419 elems
[i
] = vec
->operands
[i
].getTemp();
421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
422 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
425 /* adjust misaligned small bit size loads */
426 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
428 Builder
bld(ctx
->program
, ctx
->block
);
430 Temp select
= Temp();
431 if (offset
.isConstant()) {
432 assert(offset
.constantValue() && offset
.constantValue() < 4);
433 shift
= Operand(offset
.constantValue() * 8);
435 /* bit_offset = 8 * (offset & 0x3) */
436 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
437 select
= bld
.tmp(s1
);
438 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
441 if (vec
.size() == 1) {
442 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
443 } else if (vec
.size() == 2) {
444 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
445 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
447 emit_split_vector(ctx
, dst
, 2);
449 emit_extract_vector(ctx
, tmp
, 0, dst
);
450 } else if (vec
.size() == 4) {
451 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
453 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
454 if (select
!= Temp())
455 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
456 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
457 Temp mid
= bld
.tmp(s1
);
458 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
459 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
460 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
461 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
462 emit_split_vector(ctx
, dst
, 2);
466 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
468 Builder
bld(ctx
->program
, ctx
->block
);
469 if (offset
.isTemp()) {
470 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
472 if (vec
.size() == 4) {
473 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
474 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
475 } else if (vec
.size() == 3) {
476 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
477 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
478 } else if (vec
.size() == 2) {
479 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
480 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
482 for (unsigned i
= 0; i
< dst
.size(); i
++)
483 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
487 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
489 offset
= Operand(0u);
492 unsigned num_components
= vec
.bytes() / component_size
;
493 if (vec
.regClass() == dst
.regClass()) {
494 assert(offset
.constantValue() == 0);
495 bld
.copy(Definition(dst
), vec
);
496 emit_split_vector(ctx
, dst
, num_components
);
500 emit_split_vector(ctx
, vec
, num_components
);
501 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
502 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
504 assert(offset
.constantValue() % component_size
== 0);
505 unsigned skip
= offset
.constantValue() / component_size
;
506 for (unsigned i
= skip
; i
< num_components
; i
++)
507 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
509 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
510 if (dst
.type() == RegType::vgpr
) {
511 num_components
= dst
.bytes() / component_size
;
512 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
513 for (unsigned i
= 0; i
< num_components
; i
++)
514 create_vec
->operands
[i
] = Operand(elems
[i
]);
515 create_vec
->definitions
[0] = Definition(dst
);
516 bld
.insert(std::move(create_vec
));
518 /* if dst is sgpr - split the src, but move the original to sgpr. */
520 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
521 byte_align_scalar(ctx
, vec
, offset
, dst
);
523 assert(dst
.size() == vec
.size());
524 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
527 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
530 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
532 Builder
bld(ctx
->program
, ctx
->block
);
534 dst
= bld
.tmp(bld
.lm
);
536 assert(val
.regClass() == s1
);
537 assert(dst
.regClass() == bld
.lm
);
539 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
542 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
544 Builder
bld(ctx
->program
, ctx
->block
);
548 assert(val
.regClass() == bld
.lm
);
549 assert(dst
.regClass() == s1
);
551 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
552 Temp tmp
= bld
.tmp(s1
);
553 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
554 return emit_wqm(ctx
, tmp
, dst
);
557 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
560 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
561 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
563 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
566 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
567 return bld
.copy(Definition(dst
), src
);
568 else if (dst
.bytes() < src
.bytes())
569 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
573 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
576 } else if (src
.regClass() == s1
) {
578 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
580 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
581 } else if (ctx
->options
->chip_class
>= GFX8
) {
582 assert(src_bits
!= 8 || src
.regClass() == v1b
);
583 assert(src_bits
!= 16 || src
.regClass() == v2b
);
584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
585 sdwa
->operands
[0] = Operand(src
);
586 sdwa
->definitions
[0] = Definition(tmp
);
588 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
590 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
591 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
592 bld
.insert(std::move(sdwa
));
594 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
595 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
596 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
599 if (dst_bits
== 64) {
600 if (is_signed
&& dst
.regClass() == s2
) {
601 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
602 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
603 } else if (is_signed
&& dst
.regClass() == v2
) {
604 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
607 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
614 enum sgpr_extract_mode
{
620 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
622 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
623 unsigned src_size
= src
->src
.ssa
->bit_size
;
624 unsigned swizzle
= src
->swizzle
[0];
626 if (vec
.size() > 1) {
627 assert(src_size
== 16);
628 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
629 swizzle
= swizzle
& 1;
632 Builder
bld(ctx
->program
, ctx
->block
);
633 unsigned offset
= src_size
* swizzle
;
634 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
636 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
637 bld
.copy(Definition(tmp
), vec
);
638 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
639 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
640 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
641 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
642 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
643 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
645 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
646 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
649 if (dst
.regClass() == s2
)
650 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
655 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
657 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
658 return get_ssa_temp(ctx
, src
.src
.ssa
);
660 if (src
.src
.ssa
->num_components
== size
) {
661 bool identity_swizzle
= true;
662 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
663 if (src
.swizzle
[i
] != i
)
664 identity_swizzle
= false;
666 if (identity_swizzle
)
667 return get_ssa_temp(ctx
, src
.src
.ssa
);
670 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
671 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
672 assert(elem_size
> 0);
673 assert(vec
.bytes() % elem_size
== 0);
675 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
676 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
678 return extract_8_16_bit_sgpr_element(
679 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
682 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
684 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
687 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
688 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
689 for (unsigned i
= 0; i
< size
; ++i
) {
690 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
691 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
693 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
694 vec_instr
->definitions
[0] = Definition(dst
);
695 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
696 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
701 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
705 Builder
bld(ctx
->program
, ctx
->block
);
706 if (ptr
.type() == RegType::vgpr
)
707 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
708 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
709 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
712 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
714 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
715 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
716 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
717 sop2
->definitions
[0] = Definition(dst
);
718 if (instr
->no_unsigned_wrap
)
719 sop2
->definitions
[0].setNUW(true);
721 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
722 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
725 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
726 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
728 Builder
bld(ctx
->program
, ctx
->block
);
729 bld
.is_precise
= instr
->exact
;
731 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
733 if (src1
.type() == RegType::sgpr
) {
734 if (commutative
&& src0
.type() == RegType::vgpr
) {
739 src1
= as_vgpr(ctx
, src1
);
743 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
744 assert(dst
.size() == 1);
745 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
746 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
748 bld
.vop2(op
, Definition(dst
), src0
, src1
);
752 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
753 aco_opcode op
, Temp dst
)
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.is_precise
= instr
->exact
;
758 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
759 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
761 if (src1
.type() == RegType::sgpr
) {
762 assert(src0
.type() == RegType::vgpr
);
763 std::swap(src0
, src1
);
766 Temp src00
= bld
.tmp(src0
.type(), 1);
767 Temp src01
= bld
.tmp(src0
.type(), 1);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
769 Temp src10
= bld
.tmp(v1
);
770 Temp src11
= bld
.tmp(v1
);
771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
772 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
773 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
777 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
778 bool flush_denorms
= false)
780 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
781 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
782 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
784 /* ensure that the instruction has at most 1 sgpr operand
785 * The optimizer will inline constants for us */
786 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
787 src0
= as_vgpr(ctx
, src0
);
788 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
789 src1
= as_vgpr(ctx
, src1
);
790 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
791 src2
= as_vgpr(ctx
, src2
);
793 Builder
bld(ctx
->program
, ctx
->block
);
794 bld
.is_precise
= instr
->exact
;
795 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
796 assert(dst
.size() == 1);
797 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
798 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
800 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
804 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
806 Builder
bld(ctx
->program
, ctx
->block
);
807 bld
.is_precise
= instr
->exact
;
808 if (dst
.type() == RegType::sgpr
)
809 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
810 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
812 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
815 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
817 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
818 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
819 assert(src0
.size() == src1
.size());
821 aco_ptr
<Instruction
> vopc
;
822 if (src1
.type() == RegType::sgpr
) {
823 if (src0
.type() == RegType::vgpr
) {
824 /* to swap the operands, we might also have to change the opcode */
826 case aco_opcode::v_cmp_lt_f16
:
827 op
= aco_opcode::v_cmp_gt_f16
;
829 case aco_opcode::v_cmp_ge_f16
:
830 op
= aco_opcode::v_cmp_le_f16
;
832 case aco_opcode::v_cmp_lt_i16
:
833 op
= aco_opcode::v_cmp_gt_i16
;
835 case aco_opcode::v_cmp_ge_i16
:
836 op
= aco_opcode::v_cmp_le_i16
;
838 case aco_opcode::v_cmp_lt_u16
:
839 op
= aco_opcode::v_cmp_gt_u16
;
841 case aco_opcode::v_cmp_ge_u16
:
842 op
= aco_opcode::v_cmp_le_u16
;
844 case aco_opcode::v_cmp_lt_f32
:
845 op
= aco_opcode::v_cmp_gt_f32
;
847 case aco_opcode::v_cmp_ge_f32
:
848 op
= aco_opcode::v_cmp_le_f32
;
850 case aco_opcode::v_cmp_lt_i32
:
851 op
= aco_opcode::v_cmp_gt_i32
;
853 case aco_opcode::v_cmp_ge_i32
:
854 op
= aco_opcode::v_cmp_le_i32
;
856 case aco_opcode::v_cmp_lt_u32
:
857 op
= aco_opcode::v_cmp_gt_u32
;
859 case aco_opcode::v_cmp_ge_u32
:
860 op
= aco_opcode::v_cmp_le_u32
;
862 case aco_opcode::v_cmp_lt_f64
:
863 op
= aco_opcode::v_cmp_gt_f64
;
865 case aco_opcode::v_cmp_ge_f64
:
866 op
= aco_opcode::v_cmp_le_f64
;
868 case aco_opcode::v_cmp_lt_i64
:
869 op
= aco_opcode::v_cmp_gt_i64
;
871 case aco_opcode::v_cmp_ge_i64
:
872 op
= aco_opcode::v_cmp_le_i64
;
874 case aco_opcode::v_cmp_lt_u64
:
875 op
= aco_opcode::v_cmp_gt_u64
;
877 case aco_opcode::v_cmp_ge_u64
:
878 op
= aco_opcode::v_cmp_le_u64
;
880 default: /* eq and ne are commutative */
887 src1
= as_vgpr(ctx
, src1
);
891 Builder
bld(ctx
->program
, ctx
->block
);
892 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
895 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
897 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
898 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
899 Builder
bld(ctx
->program
, ctx
->block
);
901 assert(dst
.regClass() == bld
.lm
);
902 assert(src0
.type() == RegType::sgpr
);
903 assert(src1
.type() == RegType::sgpr
);
904 assert(src0
.regClass() == src1
.regClass());
906 /* Emit the SALU comparison instruction */
907 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
908 /* Turn the result into a per-lane bool */
909 bool_to_vector_condition(ctx
, cmp
, dst
);
912 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
913 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
915 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
916 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
917 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
918 nir_dest_is_divergent(instr
->dest
.dest
) ||
919 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
920 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
921 aco_opcode op
= use_valu
? v_op
: s_op
;
922 assert(op
!= aco_opcode::num_opcodes
);
923 assert(dst
.regClass() == ctx
->program
->lane_mask
);
926 emit_vopc_instruction(ctx
, instr
, op
, dst
);
928 emit_sopc_instruction(ctx
, instr
, op
, dst
);
931 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
933 Builder
bld(ctx
->program
, ctx
->block
);
934 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
935 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
937 assert(dst
.regClass() == bld
.lm
);
938 assert(src0
.regClass() == bld
.lm
);
939 assert(src1
.regClass() == bld
.lm
);
941 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
944 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
946 Builder
bld(ctx
->program
, ctx
->block
);
947 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
948 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
949 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
951 assert(cond
.regClass() == bld
.lm
);
953 if (dst
.type() == RegType::vgpr
) {
954 aco_ptr
<Instruction
> bcsel
;
955 if (dst
.size() == 1) {
956 then
= as_vgpr(ctx
, then
);
957 els
= as_vgpr(ctx
, els
);
959 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
960 } else if (dst
.size() == 2) {
961 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
963 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
966 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
967 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
971 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
976 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
977 assert(dst
.regClass() == bld
.lm
);
978 assert(then
.regClass() == bld
.lm
);
979 assert(els
.regClass() == bld
.lm
);
982 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
983 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
984 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
985 assert(dst
.size() == then
.size());
986 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
987 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
989 isel_err(&instr
->instr
, "Unimplemented uniform bcsel bit size");
994 /* divergent boolean bcsel
995 * this implements bcsel on bools: dst = s0 ? s1 : s2
996 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
997 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
999 if (cond
.id() != then
.id())
1000 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
1002 if (cond
.id() == els
.id())
1003 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
1005 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
1006 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
1009 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
1010 aco_opcode op
, uint32_t undo
)
1012 /* multiply by 16777216 to handle denormals */
1013 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1014 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1015 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1016 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1017 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1019 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1021 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1024 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1026 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1027 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1031 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1034 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1036 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1037 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1041 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1044 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1046 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1047 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1051 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1054 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1056 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1057 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1061 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1064 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1066 if (ctx
->options
->chip_class
>= GFX7
)
1067 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1069 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1070 /* TODO: create more efficient code! */
1071 if (val
.type() == RegType::sgpr
)
1072 val
= as_vgpr(ctx
, val
);
1074 /* Split the input value. */
1075 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1078 /* Extract the exponent and compute the unbiased value. */
1079 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1080 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1082 /* Extract the fractional part. */
1083 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1084 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1086 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1089 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1090 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1091 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1092 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1093 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1095 /* Get the sign bit. */
1096 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1098 /* Decide the operation to apply depending on the unbiased exponent. */
1099 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1100 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1101 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1102 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1103 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1104 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1106 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1109 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1111 if (ctx
->options
->chip_class
>= GFX7
)
1112 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1114 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1115 * lowered at NIR level for precision reasons). */
1116 Temp src0
= as_vgpr(ctx
, val
);
1118 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1119 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1121 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1122 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1123 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1125 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1127 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1128 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1130 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1131 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1133 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1135 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1136 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1138 return add
->definitions
[0].getTemp();
1141 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1143 if (!instr
->dest
.dest
.is_ssa
) {
1144 isel_err(&instr
->instr
, "nir alu dst not in ssa");
1147 Builder
bld(ctx
->program
, ctx
->block
);
1148 bld
.is_precise
= instr
->exact
;
1149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1154 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1155 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1156 for (unsigned i
= 0; i
< num
; ++i
)
1157 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1159 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1160 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1161 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1162 for (unsigned i
= 0; i
< num
; ++i
) {
1163 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1164 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1166 vec
->operands
[i
] = Operand
{elems
[i
]};
1168 vec
->definitions
[0] = Definition(dst
);
1169 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1170 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1172 // TODO: that is a bit suboptimal..
1173 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1174 for (unsigned i
= 0; i
< num
- 1; ++i
)
1175 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1176 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1177 for (unsigned i
= 0; i
< num
; ++i
) {
1178 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1179 if (bit
% 32 == 0) {
1180 elems
[bit
/ 32] = elems
[i
];
1182 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1183 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1184 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1187 if (dst
.size() == 1)
1188 bld
.copy(Definition(dst
), elems
[0]);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1195 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1196 aco_ptr
<Instruction
> mov
;
1197 if (dst
.type() == RegType::sgpr
) {
1198 if (src
.type() == RegType::vgpr
)
1199 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1200 else if (src
.regClass() == s1
)
1201 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1202 else if (src
.regClass() == s2
)
1203 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1205 unreachable("wrong src register class for nir_op_imov");
1207 if (dst
.regClass() == v1
)
1208 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1209 else if (dst
.regClass() == v1b
||
1210 dst
.regClass() == v2b
||
1211 dst
.regClass() == v2
)
1212 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1214 unreachable("wrong src register class for nir_op_imov");
1219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1220 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1221 assert(src
.regClass() == bld
.lm
);
1222 assert(dst
.regClass() == bld
.lm
);
1223 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1224 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1225 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1226 } else if (dst
.regClass() == v1
) {
1227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1228 } else if (dst
.regClass() == v2
) {
1229 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1230 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1231 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1232 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1234 } else if (dst
.type() == RegType::sgpr
) {
1235 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1236 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1238 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1243 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1244 if (dst
.regClass() == v1
) {
1245 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1246 } else if (dst
.regClass() == s1
) {
1247 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1248 } else if (dst
.size() == 2) {
1249 Temp src0
= bld
.tmp(dst
.type(), 1);
1250 Temp src1
= bld
.tmp(dst
.type(), 1);
1251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1253 if (dst
.regClass() == s2
) {
1254 Temp carry
= bld
.tmp(s1
);
1255 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1256 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1257 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1259 Temp lower
= bld
.tmp(v1
);
1260 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1261 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1265 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1270 if (dst
.regClass() == s1
) {
1271 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1272 } else if (dst
.regClass() == v1
) {
1273 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1274 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1276 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1280 case nir_op_isign
: {
1281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1282 if (dst
.regClass() == s1
) {
1283 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1284 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1285 } else if (dst
.regClass() == s2
) {
1286 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1288 if (ctx
->program
->chip_class
>= GFX8
)
1289 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1291 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1292 /* SCC gets zero-extended to 64 bit */
1293 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1294 } else if (dst
.regClass() == v1
) {
1295 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1296 } else if (dst
.regClass() == v2
) {
1297 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1298 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1299 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1300 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1301 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1304 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1309 if (dst
.regClass() == v1
) {
1310 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1311 } else if (dst
.regClass() == s1
) {
1312 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1314 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1319 if (dst
.regClass() == v1
) {
1320 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1321 } else if (dst
.regClass() == s1
) {
1322 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1324 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1329 if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1331 } else if (dst
.regClass() == s1
) {
1332 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1334 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1339 if (dst
.regClass() == v1
) {
1340 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1341 } else if (dst
.regClass() == s1
) {
1342 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1344 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1349 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1350 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1351 } else if (dst
.regClass() == v1
) {
1352 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1353 } else if (dst
.regClass() == v2
) {
1354 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1360 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1365 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1366 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1367 } else if (dst
.regClass() == v1
) {
1368 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1369 } else if (dst
.regClass() == v2
) {
1370 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1371 } else if (dst
.regClass() == s1
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1373 } else if (dst
.regClass() == s2
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1376 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1381 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1382 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1383 } else if (dst
.regClass() == v1
) {
1384 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1385 } else if (dst
.regClass() == v2
) {
1386 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1387 } else if (dst
.regClass() == s1
) {
1388 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1392 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1397 if (dst
.regClass() == v1
) {
1398 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1399 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1400 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1401 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1402 } else if (dst
.regClass() == v2
) {
1403 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1404 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1405 } else if (dst
.regClass() == s2
) {
1406 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1407 } else if (dst
.regClass() == s1
) {
1408 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1410 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1415 if (dst
.regClass() == v1
) {
1416 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1417 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1418 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1419 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1420 } else if (dst
.regClass() == v2
) {
1421 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1423 } else if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1425 } else if (dst
.regClass() == s2
) {
1426 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1428 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1433 if (dst
.regClass() == v1
) {
1434 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1435 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1436 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1437 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1438 } else if (dst
.regClass() == v2
) {
1439 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1440 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1441 } else if (dst
.regClass() == s1
) {
1442 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1443 } else if (dst
.regClass() == s2
) {
1444 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1446 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1450 case nir_op_find_lsb
: {
1451 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1452 if (src
.regClass() == s1
) {
1453 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1454 } else if (src
.regClass() == v1
) {
1455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1456 } else if (src
.regClass() == s2
) {
1457 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1459 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1463 case nir_op_ufind_msb
:
1464 case nir_op_ifind_msb
: {
1465 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1466 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1467 aco_opcode op
= src
.regClass() == s2
?
1468 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1469 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1470 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1472 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1473 Operand(src
.size() * 32u - 1u), msb_rev
);
1474 Temp msb
= sub
.def(0).getTemp();
1475 Temp carry
= sub
.def(1).getTemp();
1477 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1478 } else if (src
.regClass() == v1
) {
1479 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1480 Temp msb_rev
= bld
.tmp(v1
);
1481 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1482 Temp msb
= bld
.tmp(v1
);
1483 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1484 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1486 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1490 case nir_op_bitfield_reverse
: {
1491 if (dst
.regClass() == s1
) {
1492 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1493 } else if (dst
.regClass() == v1
) {
1494 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1496 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1501 if (dst
.regClass() == s1
) {
1502 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1506 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1507 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1508 if (dst
.regClass() == v1
) {
1509 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1513 assert(src0
.size() == 2 && src1
.size() == 2);
1514 Temp src00
= bld
.tmp(src0
.type(), 1);
1515 Temp src01
= bld
.tmp(dst
.type(), 1);
1516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1517 Temp src10
= bld
.tmp(src1
.type(), 1);
1518 Temp src11
= bld
.tmp(dst
.type(), 1);
1519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1521 if (dst
.regClass() == s2
) {
1522 Temp carry
= bld
.tmp(s1
);
1523 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1524 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1525 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1526 } else if (dst
.regClass() == v2
) {
1527 Temp dst0
= bld
.tmp(v1
);
1528 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1529 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1530 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1532 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1536 case nir_op_uadd_sat
: {
1537 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1538 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1539 if (dst
.regClass() == s1
) {
1540 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1541 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1543 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1544 } else if (dst
.regClass() == v1
) {
1545 if (ctx
->options
->chip_class
>= GFX9
) {
1546 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1547 add
->operands
[0] = Operand(src0
);
1548 add
->operands
[1] = Operand(src1
);
1549 add
->definitions
[0] = Definition(dst
);
1551 ctx
->block
->instructions
.emplace_back(std::move(add
));
1553 if (src1
.regClass() != v1
)
1554 std::swap(src0
, src1
);
1555 assert(src1
.regClass() == v1
);
1556 Temp tmp
= bld
.tmp(v1
);
1557 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1558 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1561 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1600 if (dst
.regClass() == s1
) {
1601 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1605 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1606 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1607 if (dst
.regClass() == v1
) {
1608 bld
.vsub32(Definition(dst
), src0
, src1
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp carry
= bld
.tmp(s1
);
1620 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1621 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1623 } else if (dst
.regClass() == v2
) {
1624 Temp lower
= bld
.tmp(v1
);
1625 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1626 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1629 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1633 case nir_op_usub_borrow
: {
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == s1
) {
1637 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1639 } else if (dst
.regClass() == v1
) {
1640 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1641 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1645 Temp src00
= bld
.tmp(src0
.type(), 1);
1646 Temp src01
= bld
.tmp(dst
.type(), 1);
1647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1648 Temp src10
= bld
.tmp(src1
.type(), 1);
1649 Temp src11
= bld
.tmp(dst
.type(), 1);
1650 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1651 if (dst
.regClass() == s2
) {
1652 Temp borrow
= bld
.tmp(s1
);
1653 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1654 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1656 } else if (dst
.regClass() == v2
) {
1657 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1658 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1659 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1660 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1662 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1667 if (dst
.regClass() == v1
) {
1668 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1669 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1670 } else if (dst
.regClass() == s1
) {
1671 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1673 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1677 case nir_op_umul_high
: {
1678 if (dst
.regClass() == v1
) {
1679 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1680 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1681 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1682 } else if (dst
.regClass() == s1
) {
1683 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1684 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1685 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1687 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1691 case nir_op_imul_high
: {
1692 if (dst
.regClass() == v1
) {
1693 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1694 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1695 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1696 } else if (dst
.regClass() == s1
) {
1697 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1698 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1699 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1701 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1706 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1707 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1712 } else if (dst
.regClass() == v2
) {
1713 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1715 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1721 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1722 if (dst
.regClass() == v2b
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1726 } else if (dst
.regClass() == v2
) {
1727 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1729 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1736 if (dst
.regClass() == v2b
) {
1737 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1738 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1740 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1741 } else if (dst
.regClass() == v1
) {
1742 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1743 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1746 } else if (dst
.regClass() == v2
) {
1747 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1748 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1749 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1752 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1757 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1758 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1759 if (dst
.regClass() == v2b
) {
1760 // TODO: check fp_mode.must_flush_denorms16_64
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1764 } else if (dst
.regClass() == v2
) {
1765 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1766 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1767 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1769 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1772 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1779 if (dst
.regClass() == v2b
) {
1780 // TODO: check fp_mode.must_flush_denorms16_64
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1782 } else if (dst
.regClass() == v1
) {
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1784 } else if (dst
.regClass() == v2
) {
1785 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1786 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1787 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1789 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1792 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1796 case nir_op_cube_face_coord
: {
1797 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1798 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1799 emit_extract_vector(ctx
, in
, 1, v1
),
1800 emit_extract_vector(ctx
, in
, 2, v1
) };
1801 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1802 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1803 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1804 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1805 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1806 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
), Operand(0x3f000000u
/*0.5*/));
1807 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1808 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
), Operand(0x3f000000u
/*0.5*/));
1809 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1812 case nir_op_cube_face_index
: {
1813 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1814 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1815 emit_extract_vector(ctx
, in
, 1, v1
),
1816 emit_extract_vector(ctx
, in
, 2, v1
) };
1817 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1820 case nir_op_bcsel
: {
1821 emit_bcsel(ctx
, instr
, dst
);
1825 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1826 if (dst
.regClass() == v2b
) {
1827 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1828 } else if (dst
.regClass() == v1
) {
1829 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1830 } else if (dst
.regClass() == v2
) {
1831 /* Lowered at NIR level for precision reasons. */
1832 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1834 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1839 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1840 if (dst
.regClass() == v2b
) {
1841 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1842 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1843 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1844 } else if (dst
.regClass() == v1
) {
1845 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1846 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1847 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1848 } else if (dst
.regClass() == v2
) {
1849 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1850 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1851 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1853 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1854 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1856 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1861 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1862 if (dst
.regClass() == v2b
) {
1863 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1864 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1865 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1866 } else if (dst
.regClass() == v1
) {
1867 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1868 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1869 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1870 } else if (dst
.regClass() == v2
) {
1871 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1872 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1873 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1874 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1875 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1876 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1878 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1883 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1884 if (dst
.regClass() == v2b
) {
1885 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1886 } else if (dst
.regClass() == v1
) {
1887 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1888 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1889 // TODO: confirm that this holds under any circumstances
1890 } else if (dst
.regClass() == v2
) {
1891 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1892 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1895 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1899 case nir_op_flog2
: {
1900 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1901 if (dst
.regClass() == v2b
) {
1902 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1903 } else if (dst
.regClass() == v1
) {
1904 emit_log2(ctx
, bld
, Definition(dst
), src
);
1906 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1911 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1912 if (dst
.regClass() == v2b
) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1914 } else if (dst
.regClass() == v1
) {
1915 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1916 } else if (dst
.regClass() == v2
) {
1917 /* Lowered at NIR level for precision reasons. */
1918 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1920 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1924 case nir_op_fexp2
: {
1925 if (dst
.regClass() == v2b
) {
1926 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1927 } else if (dst
.regClass() == v1
) {
1928 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1930 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1934 case nir_op_fsqrt
: {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 if (dst
.regClass() == v2b
) {
1937 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1940 } else if (dst
.regClass() == v2
) {
1941 /* Lowered at NIR level for precision reasons. */
1942 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1944 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1948 case nir_op_ffract
: {
1949 if (dst
.regClass() == v2b
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1951 } else if (dst
.regClass() == v1
) {
1952 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1953 } else if (dst
.regClass() == v2
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1956 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1960 case nir_op_ffloor
: {
1961 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1962 if (dst
.regClass() == v2b
) {
1963 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1964 } else if (dst
.regClass() == v1
) {
1965 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1966 } else if (dst
.regClass() == v2
) {
1967 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1969 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1973 case nir_op_fceil
: {
1974 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1975 if (dst
.regClass() == v2b
) {
1976 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1977 } else if (dst
.regClass() == v1
) {
1978 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1979 } else if (dst
.regClass() == v2
) {
1980 if (ctx
->options
->chip_class
>= GFX7
) {
1981 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1983 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1984 /* trunc = trunc(src0)
1985 * if (src0 > 0.0 && src0 != trunc)
1988 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1989 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1990 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1991 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1992 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1993 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1994 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1997 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2001 case nir_op_ftrunc
: {
2002 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2003 if (dst
.regClass() == v2b
) {
2004 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2005 } else if (dst
.regClass() == v1
) {
2006 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2007 } else if (dst
.regClass() == v2
) {
2008 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2010 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2014 case nir_op_fround_even
: {
2015 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2016 if (dst
.regClass() == v2b
) {
2017 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2018 } else if (dst
.regClass() == v1
) {
2019 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2020 } else if (dst
.regClass() == v2
) {
2021 if (ctx
->options
->chip_class
>= GFX7
) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2024 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2025 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2026 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2028 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2029 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2030 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2032 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2033 tmp
= sub
->definitions
[0].getTemp();
2035 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2036 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2037 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2038 Temp cond
= vop3
->definitions
[0].getTemp();
2040 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2041 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2042 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2043 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2045 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2048 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2054 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2055 aco_ptr
<Instruction
> norm
;
2056 if (dst
.regClass() == v2b
) {
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2058 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2059 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2060 bld
.vop1(opcode
, Definition(dst
), tmp
);
2061 } else if (dst
.regClass() == v1
) {
2062 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2063 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2065 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2066 if (ctx
->options
->chip_class
< GFX9
)
2067 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2069 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2070 bld
.vop1(opcode
, Definition(dst
), tmp
);
2072 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2076 case nir_op_ldexp
: {
2077 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2078 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2079 if (dst
.regClass() == v2b
) {
2080 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2081 } else if (dst
.regClass() == v1
) {
2082 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2083 } else if (dst
.regClass() == v2
) {
2084 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2086 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2090 case nir_op_frexp_sig
: {
2091 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2092 if (dst
.regClass() == v2b
) {
2093 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2094 } else if (dst
.regClass() == v1
) {
2095 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2096 } else if (dst
.regClass() == v2
) {
2097 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2099 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2103 case nir_op_frexp_exp
: {
2104 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2105 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2106 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2107 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2108 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2109 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2110 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2111 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2112 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2114 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2118 case nir_op_fsign
: {
2119 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2120 if (dst
.regClass() == v2b
) {
2121 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2122 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2123 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2124 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2125 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2126 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2127 } else if (dst
.regClass() == v1
) {
2128 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2129 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2130 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2131 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2132 } else if (dst
.regClass() == v2
) {
2133 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2134 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2135 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2137 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2138 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2139 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2141 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2143 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2148 case nir_op_f2f16_rtne
: {
2149 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2150 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2151 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2152 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2153 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2154 * keep value numbering and the scheduler simpler.
2156 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2158 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2161 case nir_op_f2f16_rtz
: {
2162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2163 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2164 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2165 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2168 case nir_op_f2f32
: {
2169 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2170 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2171 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2172 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2174 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2178 case nir_op_f2f64
: {
2179 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2180 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2181 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2182 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2185 case nir_op_i2f16
: {
2186 assert(dst
.regClass() == v2b
);
2187 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2188 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2189 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2190 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2191 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2192 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2195 case nir_op_i2f32
: {
2196 assert(dst
.size() == 1);
2197 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2198 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2199 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2200 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2203 case nir_op_i2f64
: {
2204 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2207 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2208 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2209 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2210 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2211 RegClass rc
= RegClass(src
.type(), 1);
2212 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2213 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2214 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2215 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2216 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2217 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2220 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2224 case nir_op_u2f16
: {
2225 assert(dst
.regClass() == v2b
);
2226 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2227 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2228 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2229 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2230 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2231 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2234 case nir_op_u2f32
: {
2235 assert(dst
.size() == 1);
2236 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2237 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2238 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2240 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2241 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2242 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2246 case nir_op_u2f64
: {
2247 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2248 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2249 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2250 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2251 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2252 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2253 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2254 RegClass rc
= RegClass(src
.type(), 1);
2255 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2256 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2257 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2258 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2259 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2260 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2262 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2267 case nir_op_f2i16
: {
2268 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2269 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2270 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2271 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2273 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2277 case nir_op_f2u16
: {
2278 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2279 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2280 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2281 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2283 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2286 case nir_op_f2i32
: {
2287 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2288 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2289 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2290 if (dst
.type() == RegType::vgpr
) {
2291 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2293 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2294 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2296 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2297 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2298 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2299 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2301 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2305 case nir_op_f2u32
: {
2306 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2307 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2308 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2309 if (dst
.type() == RegType::vgpr
) {
2310 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2312 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2313 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2315 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2316 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2317 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2318 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2320 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2324 case nir_op_f2i64
: {
2325 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2326 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2327 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2329 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2330 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2331 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2332 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2333 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2334 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2335 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2336 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2337 Temp new_exponent
= bld
.tmp(v1
);
2338 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2339 if (ctx
->program
->chip_class
>= GFX8
)
2340 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2342 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2343 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2344 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2345 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2346 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2347 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2348 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2349 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2350 Temp new_lower
= bld
.tmp(v1
);
2351 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2352 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2353 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2355 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2356 if (src
.type() == RegType::vgpr
)
2357 src
= bld
.as_uniform(src
);
2358 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2359 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2360 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2361 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2362 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2363 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2364 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2365 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2366 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2367 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2368 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2369 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2370 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2371 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2372 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2373 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2374 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2375 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2376 Temp borrow
= bld
.tmp(s1
);
2377 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2378 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2379 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2381 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2382 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2383 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2384 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2385 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2386 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2387 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2388 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2389 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2390 if (dst
.type() == RegType::sgpr
) {
2391 lower
= bld
.as_uniform(lower
);
2392 upper
= bld
.as_uniform(upper
);
2394 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2397 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2401 case nir_op_f2u64
: {
2402 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2403 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2404 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2406 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2407 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2408 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2409 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2410 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2411 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2412 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2413 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2414 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2415 Temp new_exponent
= bld
.tmp(v1
);
2416 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2417 if (ctx
->program
->chip_class
>= GFX8
)
2418 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2420 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2421 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2422 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2423 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2424 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2425 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2426 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2427 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2429 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2430 if (src
.type() == RegType::vgpr
)
2431 src
= bld
.as_uniform(src
);
2432 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2433 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2434 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2435 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2436 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2437 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2438 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2439 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2440 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2441 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2442 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2443 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2444 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2445 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2446 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2447 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2448 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2449 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2451 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2452 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2453 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2454 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2455 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2456 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2457 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2458 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2459 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2460 if (dst
.type() == RegType::sgpr
) {
2461 lower
= bld
.as_uniform(lower
);
2462 upper
= bld
.as_uniform(upper
);
2464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2467 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2471 case nir_op_b2f16
: {
2472 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2473 assert(src
.regClass() == bld
.lm
);
2475 if (dst
.regClass() == s1
) {
2476 src
= bool_to_scalar_condition(ctx
, src
);
2477 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2478 } else if (dst
.regClass() == v2b
) {
2479 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2480 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2482 unreachable("Wrong destination register class for nir_op_b2f16.");
2486 case nir_op_b2f32
: {
2487 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2488 assert(src
.regClass() == bld
.lm
);
2490 if (dst
.regClass() == s1
) {
2491 src
= bool_to_scalar_condition(ctx
, src
);
2492 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2493 } else if (dst
.regClass() == v1
) {
2494 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2496 unreachable("Wrong destination register class for nir_op_b2f32.");
2500 case nir_op_b2f64
: {
2501 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2502 assert(src
.regClass() == bld
.lm
);
2504 if (dst
.regClass() == s2
) {
2505 src
= bool_to_scalar_condition(ctx
, src
);
2506 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2507 } else if (dst
.regClass() == v2
) {
2508 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2509 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2510 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2512 unreachable("Wrong destination register class for nir_op_b2f64.");
2519 case nir_op_i2i64
: {
2520 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2521 /* no need to do the extract in get_alu_src() */
2522 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2523 sgpr_extract_sext
: sgpr_extract_undef
;
2524 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2526 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2527 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2534 case nir_op_u2u64
: {
2535 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2536 /* no need to do the extract in get_alu_src() */
2537 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2538 sgpr_extract_zext
: sgpr_extract_undef
;
2539 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2541 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2542 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2550 case nir_op_b2i64
: {
2551 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2552 assert(src
.regClass() == bld
.lm
);
2554 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2555 if (tmp
.regClass() == s1
) {
2556 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2557 bool_to_scalar_condition(ctx
, src
, tmp
);
2558 } else if (tmp
.type() == RegType::vgpr
) {
2559 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2561 unreachable("Invalid register class for b2i32");
2565 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2570 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2571 assert(dst
.regClass() == bld
.lm
);
2573 if (src
.type() == RegType::vgpr
) {
2574 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2575 assert(dst
.regClass() == bld
.lm
);
2576 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2577 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2579 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2581 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2582 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2584 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2585 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2587 bool_to_vector_condition(ctx
, tmp
, dst
);
2591 case nir_op_pack_64_2x32_split
: {
2592 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2593 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2595 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2598 case nir_op_unpack_64_2x32_split_x
:
2599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2601 case nir_op_unpack_64_2x32_split_y
:
2602 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2604 case nir_op_unpack_32_2x16_split_x
:
2605 if (dst
.type() == RegType::vgpr
) {
2606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2608 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2611 case nir_op_unpack_32_2x16_split_y
:
2612 if (dst
.type() == RegType::vgpr
) {
2613 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2615 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2618 case nir_op_pack_32_2x16_split
: {
2619 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2620 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2621 if (dst
.regClass() == v1
) {
2622 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2623 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2626 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2627 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2628 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2632 case nir_op_pack_half_2x16
: {
2633 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2635 if (dst
.regClass() == v1
) {
2636 Temp src0
= bld
.tmp(v1
);
2637 Temp src1
= bld
.tmp(v1
);
2638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2639 if (0 && (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)) {
2640 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2642 src0
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src0
);
2643 src1
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src1
);
2644 if (ctx
->program
->chip_class
>= GFX10
) {
2645 /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
2646 bld
.vop3(aco_opcode::v_pack_b32_f16
, Definition(dst
), src0
, src1
);
2648 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
), src0
, src1
);
2652 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2656 case nir_op_unpack_half_2x16_split_x
: {
2657 if (dst
.regClass() == v1
) {
2658 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2660 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2664 case nir_op_unpack_half_2x16_split_y
: {
2665 if (dst
.regClass() == v1
) {
2666 /* TODO: use SDWA here */
2667 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2668 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2670 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2674 case nir_op_fquantize2f16
: {
2675 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2676 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2679 if (ctx
->program
->chip_class
>= GFX8
) {
2680 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2681 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2682 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2684 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2685 * so compare the result and flush to 0 if it's smaller.
2687 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2688 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2689 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2690 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2691 cmp_res
= vop3
->definitions
[0].getTemp();
2694 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2695 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2696 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2698 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2703 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2704 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2706 if (dst
.regClass() == s1
) {
2707 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2708 } else if (dst
.regClass() == v1
) {
2709 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2711 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2715 case nir_op_bitfield_select
: {
2716 /* (mask & insert) | (~mask & base) */
2717 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2718 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2719 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2721 /* dst = (insert & bitmask) | (base & ~bitmask) */
2722 if (dst
.regClass() == s1
) {
2723 aco_ptr
<Instruction
> sop2
;
2724 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2725 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2727 if (const_insert
&& const_bitmask
) {
2728 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2730 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2731 lhs
= Operand(insert
);
2735 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2736 if (const_base
&& const_bitmask
) {
2737 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2739 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2740 rhs
= Operand(base
);
2743 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2745 } else if (dst
.regClass() == v1
) {
2746 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2747 base
= as_vgpr(ctx
, base
);
2748 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2749 insert
= as_vgpr(ctx
, insert
);
2751 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2754 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2760 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2761 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2762 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2764 if (dst
.bytes() != 4)
2765 unreachable("Unsupported BFE bit size");
2767 if (dst
.type() == RegType::sgpr
) {
2768 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2769 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2770 if (const_offset
&& const_bits
) {
2771 uint32_t extract
= (const_bits
->u32
<< 16) | (const_offset
->u32
& 0x1f);
2772 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
2773 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, Operand(extract
));
2774 } else if (instr
->op
== nir_op_ubfe
) {
2775 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b32
, bld
.def(s1
), bits
, offset
);
2776 Temp masked
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, mask
);
2777 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), masked
, offset
);
2779 Operand bits_op
= const_bits
? Operand(const_bits
->u32
<< 16) :
2780 bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2781 Operand offset_op
= const_offset
? Operand(const_offset
->u32
& 0x1fu
) :
2782 bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(0x1fu
));
2784 Temp extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits_op
, offset_op
);
2785 bld
.sop2(aco_opcode::s_bfe_i32
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2789 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::v_bfe_u32
: aco_opcode::v_bfe_i32
;
2790 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2794 case nir_op_bit_count
: {
2795 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2796 if (src
.regClass() == s1
) {
2797 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2798 } else if (src
.regClass() == v1
) {
2799 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2800 } else if (src
.regClass() == v2
) {
2801 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2802 emit_extract_vector(ctx
, src
, 1, v1
),
2803 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2804 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2805 } else if (src
.regClass() == s2
) {
2806 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2808 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2813 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2817 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2821 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2825 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2829 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2833 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2837 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2838 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2840 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2841 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2845 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2846 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2848 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2849 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2853 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2857 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2862 case nir_op_fddx_fine
:
2863 case nir_op_fddy_fine
:
2864 case nir_op_fddx_coarse
:
2865 case nir_op_fddy_coarse
: {
2866 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2867 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2868 if (instr
->op
== nir_op_fddx_fine
) {
2869 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2870 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2871 } else if (instr
->op
== nir_op_fddy_fine
) {
2872 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2873 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2875 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2876 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2877 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2879 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2883 if (ctx
->program
->chip_class
>= GFX8
) {
2884 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2885 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2887 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2888 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2889 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2891 emit_wqm(ctx
, tmp
, dst
, true);
2895 isel_err(&instr
->instr
, "Unknown NIR ALU instr");
2899 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2901 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2903 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2904 // which get truncated the lsb if double and msb if int
2905 // for now, we only use s_mov_b64 with 64bit inline constants
2906 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2907 assert(dst
.type() == RegType::sgpr
);
2909 Builder
bld(ctx
->program
, ctx
->block
);
2911 if (instr
->def
.bit_size
== 1) {
2912 assert(dst
.regClass() == bld
.lm
);
2913 int val
= instr
->value
[0].b
? -1 : 0;
2914 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2915 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2916 } else if (instr
->def
.bit_size
== 8) {
2917 /* ensure that the value is correctly represented in the low byte of the register */
2918 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2919 } else if (instr
->def
.bit_size
== 16) {
2920 /* ensure that the value is correctly represented in the low half of the register */
2921 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2922 } else if (dst
.size() == 1) {
2923 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2925 assert(dst
.size() != 1);
2926 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2927 if (instr
->def
.bit_size
== 64)
2928 for (unsigned i
= 0; i
< dst
.size(); i
++)
2929 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2931 for (unsigned i
= 0; i
< dst
.size(); i
++)
2932 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2934 vec
->definitions
[0] = Definition(dst
);
2935 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2939 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2941 uint32_t new_mask
= 0;
2942 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2943 if (mask
& (1u << i
))
2944 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2948 struct LoadEmitInfo
{
2951 unsigned num_components
;
2952 unsigned component_size
;
2953 Temp resource
= Temp(0, s1
);
2954 unsigned component_stride
= 0;
2955 unsigned const_offset
= 0;
2956 unsigned align_mul
= 0;
2957 unsigned align_offset
= 0;
2960 unsigned swizzle_component_size
= 0;
2961 memory_sync_info sync
;
2962 Temp soffset
= Temp(0, s1
);
2965 using LoadCallback
= Temp(*)(
2966 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
2967 unsigned align
, unsigned const_offset
, Temp dst_hint
);
2969 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
2970 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
2972 unsigned load_size
= info
->num_components
* info
->component_size
;
2973 unsigned component_size
= info
->component_size
;
2975 unsigned num_vals
= 0;
2976 Temp vals
[info
->dst
.bytes()];
2978 unsigned const_offset
= info
->const_offset
;
2980 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
2981 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
2983 unsigned bytes_read
= 0;
2984 while (bytes_read
< load_size
) {
2985 unsigned bytes_needed
= load_size
- bytes_read
;
2987 /* add buffer for unaligned loads */
2988 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
2991 if ((bytes_needed
> 2 ||
2992 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
2993 !supports_8bit_16bit_loads
) && byte_align_loads
) {
2994 if (info
->component_stride
) {
2995 assert(supports_8bit_16bit_loads
&& "unimplemented");
2999 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3000 bytes_needed
= align(bytes_needed
, 4);
3007 if (info
->swizzle_component_size
)
3008 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3009 if (info
->component_stride
)
3010 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3012 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3014 /* reduce constant offset */
3015 Operand offset
= info
->offset
;
3016 unsigned reduced_const_offset
= const_offset
;
3017 bool remove_const_offset_completely
= need_to_align_offset
;
3018 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3019 unsigned to_add
= const_offset
;
3020 if (remove_const_offset_completely
) {
3021 reduced_const_offset
= 0;
3023 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3024 reduced_const_offset
%= max_const_offset_plus_one
;
3026 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3027 if (offset
.isConstant()) {
3028 offset
= Operand(offset
.constantValue() + to_add
);
3029 } else if (offset_tmp
.regClass() == s1
) {
3030 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3031 offset_tmp
, Operand(to_add
));
3032 } else if (offset_tmp
.regClass() == v1
) {
3033 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3035 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3036 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3037 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3039 if (offset_tmp
.regClass() == s2
) {
3040 Temp carry
= bld
.tmp(s1
);
3041 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3042 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3043 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3045 Temp new_lo
= bld
.tmp(v1
);
3046 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3047 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3048 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3053 /* align offset down if needed */
3054 Operand aligned_offset
= offset
;
3055 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3056 if (need_to_align_offset
) {
3058 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3059 if (offset
.isConstant()) {
3060 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3061 } else if (offset_tmp
.regClass() == s1
) {
3062 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3063 } else if (offset_tmp
.regClass() == s2
) {
3064 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3065 } else if (offset_tmp
.regClass() == v1
) {
3066 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3067 } else if (offset_tmp
.regClass() == v2
) {
3068 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3069 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3070 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3071 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3074 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3075 bld
.copy(bld
.def(s1
), aligned_offset
);
3077 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3078 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3080 /* the callback wrote directly to dst */
3081 if (val
== info
->dst
) {
3082 assert(num_vals
== 0);
3083 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3087 /* shift result right if needed */
3088 if (info
->component_size
< 4 && byte_align_loads
) {
3089 Operand
align((uint32_t)byte_align
);
3090 if (byte_align
== -1) {
3091 if (offset
.isConstant())
3092 align
= Operand(offset
.constantValue() % 4u);
3093 else if (offset
.size() == 2)
3094 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3099 assert(val
.bytes() >= load_size
&& "unimplemented");
3100 if (val
.type() == RegType::sgpr
)
3101 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3103 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3107 /* add result to list and advance */
3108 if (info
->component_stride
) {
3109 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3110 const_offset
+= info
->component_stride
;
3111 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3113 const_offset
+= val
.bytes();
3114 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3116 bytes_read
+= val
.bytes();
3117 vals
[num_vals
++] = val
;
3120 /* create array of components */
3121 unsigned components_split
= 0;
3122 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3123 bool has_vgprs
= false;
3124 for (unsigned i
= 0; i
< num_vals
;) {
3126 unsigned num_tmps
= 0;
3127 unsigned tmp_size
= 0;
3128 RegType reg_type
= RegType::sgpr
;
3129 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3130 if (vals
[i
].type() == RegType::vgpr
)
3131 reg_type
= RegType::vgpr
;
3132 tmp_size
+= vals
[i
].bytes();
3133 tmp
[num_tmps
++] = vals
[i
++];
3136 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3137 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3138 for (unsigned i
= 0; i
< num_tmps
; i
++)
3139 vec
->operands
[i
] = Operand(tmp
[i
]);
3140 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3141 vec
->definitions
[0] = Definition(tmp
[0]);
3142 bld
.insert(std::move(vec
));
3145 if (tmp
[0].bytes() % component_size
) {
3147 assert(i
== num_vals
);
3148 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3149 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3152 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3154 unsigned start
= components_split
;
3156 if (tmp_size
== elem_rc
.bytes()) {
3157 allocated_vec
[components_split
++] = tmp
[0];
3159 assert(tmp_size
% elem_rc
.bytes() == 0);
3160 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3161 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3162 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3163 Temp component
= bld
.tmp(elem_rc
);
3164 allocated_vec
[components_split
++] = component
;
3165 split
->definitions
[i
] = Definition(component
);
3167 split
->operands
[0] = Operand(tmp
[0]);
3168 bld
.insert(std::move(split
));
3171 /* try to p_as_uniform early so we can create more optimizable code and
3172 * also update allocated_vec */
3173 for (unsigned j
= start
; j
< components_split
; j
++) {
3174 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3175 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3176 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3180 /* concatenate components and p_as_uniform() result if needed */
3181 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3182 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3184 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3186 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3187 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3188 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3189 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3191 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3192 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3193 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3194 vec
->definitions
[0] = Definition(tmp
);
3195 bld
.insert(std::move(vec
));
3196 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3198 vec
->definitions
[0] = Definition(info
->dst
);
3199 bld
.insert(std::move(vec
));
3203 Operand
load_lds_size_m0(Builder
& bld
)
3205 /* TODO: m0 does not need to be initialized on GFX9+ */
3206 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3209 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3210 Temp offset
, unsigned bytes_needed
,
3211 unsigned align
, unsigned const_offset
,
3214 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3216 Operand m
= load_lds_size_m0(bld
);
3218 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3219 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3224 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3225 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3227 op
= aco_opcode::ds_read_b128
;
3228 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3231 op
= aco_opcode::ds_read2_b64
;
3232 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3234 op
= aco_opcode::ds_read_b96
;
3235 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3237 op
= aco_opcode::ds_read_b64
;
3238 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3241 op
= aco_opcode::ds_read2_b32
;
3242 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3244 op
= aco_opcode::ds_read_b32
;
3245 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3247 op
= aco_opcode::ds_read_u16
;
3250 op
= aco_opcode::ds_read_u8
;
3253 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3254 if (const_offset
>= max_offset_plus_one
) {
3255 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3256 const_offset
%= max_offset_plus_one
;
3260 const_offset
/= (size
/ 2u);
3262 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3263 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3266 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3268 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3269 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3272 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3277 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3279 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3280 Temp offset
, unsigned bytes_needed
,
3281 unsigned align
, unsigned const_offset
,
3286 if (bytes_needed
<= 4) {
3288 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3289 } else if (bytes_needed
<= 8) {
3291 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3292 } else if (bytes_needed
<= 16) {
3294 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3295 } else if (bytes_needed
<= 32) {
3297 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3300 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3302 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3303 if (info
->resource
.id()) {
3304 load
->operands
[0] = Operand(info
->resource
);
3305 load
->operands
[1] = Operand(offset
);
3307 load
->operands
[0] = Operand(offset
);
3308 load
->operands
[1] = Operand(0u);
3310 RegClass
rc(RegType::sgpr
, size
);
3311 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3312 load
->definitions
[0] = Definition(val
);
3313 load
->glc
= info
->glc
;
3314 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3315 load
->sync
= info
->sync
;
3316 bld
.insert(std::move(load
));
3320 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3322 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3323 Temp offset
, unsigned bytes_needed
,
3324 unsigned align_
, unsigned const_offset
,
3327 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3328 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3330 if (info
->soffset
.id()) {
3331 if (soffset
.isTemp())
3332 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3333 soffset
= Operand(info
->soffset
);
3336 unsigned bytes_size
= 0;
3338 if (bytes_needed
== 1 || align_
% 2) {
3340 op
= aco_opcode::buffer_load_ubyte
;
3341 } else if (bytes_needed
== 2 || align_
% 4) {
3343 op
= aco_opcode::buffer_load_ushort
;
3344 } else if (bytes_needed
<= 4) {
3346 op
= aco_opcode::buffer_load_dword
;
3347 } else if (bytes_needed
<= 8) {
3349 op
= aco_opcode::buffer_load_dwordx2
;
3350 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3352 op
= aco_opcode::buffer_load_dwordx3
;
3355 op
= aco_opcode::buffer_load_dwordx4
;
3357 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3358 mubuf
->operands
[0] = Operand(info
->resource
);
3359 mubuf
->operands
[1] = vaddr
;
3360 mubuf
->operands
[2] = soffset
;
3361 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3362 mubuf
->glc
= info
->glc
;
3363 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3364 mubuf
->sync
= info
->sync
;
3365 mubuf
->offset
= const_offset
;
3366 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3367 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3368 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3369 mubuf
->definitions
[0] = Definition(val
);
3370 bld
.insert(std::move(mubuf
));
3375 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3376 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3378 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3380 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3381 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3383 if (addr
.type() == RegType::vgpr
)
3384 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3385 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3388 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3389 Temp offset
, unsigned bytes_needed
,
3390 unsigned align_
, unsigned const_offset
,
3393 unsigned bytes_size
= 0;
3394 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3395 bool global
= bld
.program
->chip_class
>= GFX9
;
3397 if (bytes_needed
== 1) {
3399 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3400 } else if (bytes_needed
== 2) {
3402 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3403 } else if (bytes_needed
<= 4) {
3405 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3406 } else if (bytes_needed
<= 8) {
3408 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3409 } else if (bytes_needed
<= 12 && !mubuf
) {
3411 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3414 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3416 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3417 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3419 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3420 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3421 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3422 mubuf
->operands
[2] = Operand(0u);
3423 mubuf
->glc
= info
->glc
;
3426 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3427 mubuf
->disable_wqm
= false;
3428 mubuf
->sync
= info
->sync
;
3429 mubuf
->definitions
[0] = Definition(val
);
3430 bld
.insert(std::move(mubuf
));
3432 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3434 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3435 flat
->operands
[0] = Operand(offset
);
3436 flat
->operands
[1] = Operand(s1
);
3437 flat
->glc
= info
->glc
;
3438 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3439 flat
->sync
= info
->sync
;
3441 flat
->definitions
[0] = Definition(val
);
3442 bld
.insert(std::move(flat
));
3448 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3450 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3451 Temp address
, unsigned base_offset
, unsigned align
)
3453 assert(util_is_power_of_two_nonzero(align
));
3455 Builder
bld(ctx
->program
, ctx
->block
);
3457 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3458 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3459 info
.align_mul
= align
;
3460 info
.align_offset
= 0;
3461 info
.sync
= memory_sync_info(storage_shared
);
3462 info
.const_offset
= base_offset
;
3463 emit_lds_load(ctx
, bld
, &info
);
3468 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3473 Builder
bld(ctx
->program
, ctx
->block
);
3475 ASSERTED
bool is_subdword
= false;
3476 for (unsigned i
= 0; i
< count
; i
++)
3477 is_subdword
|= offsets
[i
] % 4;
3478 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3479 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3481 /* count == 1 fast path */
3483 if (dst_type
== RegType::sgpr
)
3484 dst
[0] = bld
.as_uniform(src
);
3486 dst
[0] = as_vgpr(ctx
, src
);
3490 for (unsigned i
= 0; i
< count
- 1; i
++)
3491 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3492 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3494 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3495 src
= as_vgpr(ctx
, src
);
3497 /* use allocated_vec if possible */
3498 auto it
= ctx
->allocated_vec
.find(src
.id());
3499 if (it
!= ctx
->allocated_vec
.end()) {
3500 if (!it
->second
[0].id())
3502 unsigned elem_size
= it
->second
[0].bytes();
3503 assert(src
.bytes() % elem_size
== 0);
3505 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3506 if (!it
->second
[i
].id())
3510 for (unsigned i
= 0; i
< count
; i
++) {
3511 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3515 for (unsigned i
= 0; i
< count
; i
++) {
3516 unsigned start_idx
= offsets
[i
] / elem_size
;
3517 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3518 if (op_count
== 1) {
3519 if (dst_type
== RegType::sgpr
)
3520 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3522 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3526 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3527 for (unsigned j
= 0; j
< op_count
; j
++) {
3528 Temp tmp
= it
->second
[start_idx
+ j
];
3529 if (dst_type
== RegType::sgpr
)
3530 tmp
= bld
.as_uniform(tmp
);
3531 vec
->operands
[j
] = Operand(tmp
);
3533 vec
->definitions
[0] = Definition(dst
[i
]);
3534 bld
.insert(std::move(vec
));
3542 if (dst_type
== RegType::sgpr
)
3543 src
= bld
.as_uniform(src
);
3546 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3547 split
->operands
[0] = Operand(src
);
3548 for (unsigned i
= 0; i
< count
; i
++)
3549 split
->definitions
[i
] = Definition(dst
[i
]);
3550 bld
.insert(std::move(split
));
3553 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3554 int *start
, int *count
)
3556 unsigned start_elem
= ffs(todo_mask
) - 1;
3557 bool skip
= !(mask
& (1 << start_elem
));
3559 mask
= ~mask
& todo_mask
;
3563 u_bit_scan_consecutive_range(&mask
, start
, count
);
3568 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3570 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3573 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3574 Temp address
, unsigned base_offset
, unsigned align
)
3576 assert(util_is_power_of_two_nonzero(align
));
3577 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3579 Builder
bld(ctx
->program
, ctx
->block
);
3580 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3581 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3583 unsigned write_count
= 0;
3584 Temp write_datas
[32];
3585 unsigned offsets
[32];
3586 aco_opcode opcodes
[32];
3588 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3590 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3593 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3594 offsets
[write_count
] = offset
;
3595 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3597 advance_write_mask(&todo
, offset
, bytes
);
3601 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3602 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3603 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3604 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3606 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3607 aco_opcode op
= aco_opcode::num_opcodes
;
3608 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3609 op
= aco_opcode::ds_write_b128
;
3611 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3612 op
= aco_opcode::ds_write_b96
;
3614 } else if (bytes
>= 8 && aligned8
) {
3615 op
= aco_opcode::ds_write_b64
;
3617 } else if (bytes
>= 4 && aligned4
) {
3618 op
= aco_opcode::ds_write_b32
;
3620 } else if (bytes
>= 2 && aligned2
) {
3621 op
= aco_opcode::ds_write_b16
;
3623 } else if (bytes
>= 1) {
3624 op
= aco_opcode::ds_write_b8
;
3630 offsets
[write_count
] = offset
;
3631 opcodes
[write_count
] = op
;
3633 advance_write_mask(&todo
, offset
, bytes
);
3636 Operand m
= load_lds_size_m0(bld
);
3638 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3640 for (unsigned i
= 0; i
< write_count
; i
++) {
3641 aco_opcode op
= opcodes
[i
];
3642 if (op
== aco_opcode::num_opcodes
)
3645 Temp data
= write_datas
[i
];
3647 unsigned second
= write_count
;
3648 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3649 for (second
= i
+ 1; second
< write_count
; second
++) {
3650 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3651 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3652 opcodes
[second
] = aco_opcode::num_opcodes
;
3658 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3659 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3661 unsigned inline_offset
= base_offset
+ offsets
[i
];
3662 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3663 Temp address_offset
= address
;
3664 if (inline_offset
> max_offset
) {
3665 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3666 inline_offset
= offsets
[i
];
3668 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3672 Temp second_data
= write_datas
[second
];
3673 inline_offset
/= data
.bytes();
3674 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3676 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3678 static_cast<DS_instruction
*>(instr
)->sync
=
3679 memory_sync_info(storage_shared
);
3683 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3685 unsigned align
= 16;
3687 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3693 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3698 return aco_opcode::buffer_store_byte
;
3701 return aco_opcode::buffer_store_short
;
3703 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3705 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3708 return aco_opcode::buffer_store_dwordx3
;
3710 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3712 unreachable("Unexpected store size");
3713 return aco_opcode::num_opcodes
;
3716 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3717 Temp data
, unsigned writemask
, int swizzle_element_size
,
3718 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3720 unsigned write_count_with_skips
= 0;
3723 /* determine how to split the data */
3724 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3727 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3728 offsets
[write_count_with_skips
] = offset
;
3729 if (skips
[write_count_with_skips
]) {
3730 advance_write_mask(&todo
, offset
, bytes
);
3731 write_count_with_skips
++;
3735 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3736 * larger than swizzle_element_size */
3737 bytes
= MIN2(bytes
, swizzle_element_size
);
3739 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3741 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3742 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3745 /* dword or larger stores have to be dword-aligned */
3746 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3747 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3748 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3750 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3752 advance_write_mask(&todo
, offset
, bytes
);
3753 write_count_with_skips
++;
3756 /* actually split data */
3757 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3760 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3763 write_datas
[*write_count
] = write_datas
[i
];
3764 offsets
[*write_count
] = offsets
[i
];
3769 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3770 unsigned split_cnt
= 0u, Temp dst
= Temp())
3772 Builder
bld(ctx
->program
, ctx
->block
);
3773 unsigned dword_size
= elem_size_bytes
/ 4;
3776 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3778 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3779 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3780 instr
->definitions
[0] = Definition(dst
);
3782 for (unsigned i
= 0; i
< cnt
; ++i
) {
3784 assert(arr
[i
].size() == dword_size
);
3785 allocated_vec
[i
] = arr
[i
];
3786 instr
->operands
[i
] = Operand(arr
[i
]);
3788 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3789 allocated_vec
[i
] = zero
;
3790 instr
->operands
[i
] = Operand(zero
);
3794 bld
.insert(std::move(instr
));
3797 emit_split_vector(ctx
, dst
, split_cnt
);
3799 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3804 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3806 if (const_offset
>= 4096) {
3807 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3808 const_offset
%= 4096u;
3811 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3812 else if (unlikely(voffset
.regClass() == s1
))
3813 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3814 else if (likely(voffset
.regClass() == v1
))
3815 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3817 unreachable("Unsupported register class of voffset");
3820 return const_offset
;
3823 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3824 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
3825 bool slc
= false, bool swizzled
= false)
3828 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3829 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3831 Builder
bld(ctx
->program
, ctx
->block
);
3832 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3833 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3835 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3836 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3837 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3838 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
3839 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
3840 /* dlc*/ false, /* slc */ slc
);
3842 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
3845 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3846 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3847 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
3849 Builder
bld(ctx
->program
, ctx
->block
);
3850 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3852 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3854 unsigned write_count
= 0;
3855 Temp write_datas
[32];
3856 unsigned offsets
[32];
3857 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3858 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3860 for (unsigned i
= 0; i
< write_count
; i
++) {
3861 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3862 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
3866 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3867 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3868 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3870 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3871 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3872 assert(!!stride
!= allow_combining
);
3874 Builder
bld(ctx
->program
, ctx
->block
);
3876 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3877 info
.component_stride
= allow_combining
? 0 : stride
;
3879 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3880 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3881 info
.align_offset
= 0;
3882 info
.soffset
= soffset
;
3883 info
.const_offset
= base_const_offset
;
3884 emit_mubuf_load(ctx
, bld
, &info
);
3887 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3889 Builder
bld(ctx
->program
, ctx
->block
);
3890 Temp offset
= base_offset
.first
;
3891 unsigned const_offset
= base_offset
.second
;
3893 if (!nir_src_is_const(*off_src
)) {
3894 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3897 /* Calculate indirect offset with stride */
3898 if (likely(indirect_offset_arg
.regClass() == v1
))
3899 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3900 else if (indirect_offset_arg
.regClass() == s1
)
3901 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3903 unreachable("Unsupported register class of indirect offset");
3905 /* Add to the supplied base offset */
3906 if (offset
.id() == 0)
3907 offset
= with_stride
;
3908 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3909 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3910 else if (offset
.size() == 1 && with_stride
.size() == 1)
3911 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3913 unreachable("Unsupported register class of indirect offset");
3915 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3916 const_offset
+= const_offset_arg
* stride
;
3919 return std::make_pair(offset
, const_offset
);
3922 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3924 Builder
bld(ctx
->program
, ctx
->block
);
3927 if (off1
.first
.id() && off2
.first
.id()) {
3928 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3929 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3930 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3931 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3933 unreachable("Unsupported register class of indirect offset");
3935 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3938 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3941 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3943 Builder
bld(ctx
->program
, ctx
->block
);
3944 unsigned const_offset
= offs
.second
* multiplier
;
3946 if (!offs
.first
.id())
3947 return std::make_pair(offs
.first
, const_offset
);
3949 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3950 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3951 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
3953 return std::make_pair(offset
, const_offset
);
3956 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3958 Builder
bld(ctx
->program
, ctx
->block
);
3960 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3961 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3962 /* component is in bytes */
3963 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3965 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3966 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3967 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3970 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3972 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3975 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3977 Builder
bld(ctx
->program
, ctx
->block
);
3979 switch (ctx
->shader
->info
.stage
) {
3980 case MESA_SHADER_TESS_CTRL
:
3981 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3982 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3983 case MESA_SHADER_TESS_EVAL
:
3984 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3986 unreachable("Unsupported stage in get_tess_rel_patch_id");
3990 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3992 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3993 Builder
bld(ctx
->program
, ctx
->block
);
3995 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3996 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3998 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4000 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4001 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4003 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4004 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4005 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4007 return offset_mul(ctx
, offs
, 4u);
4010 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4012 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4013 Builder
bld(ctx
->program
, ctx
->block
);
4015 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4016 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4017 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4018 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4020 std::pair
<Temp
, unsigned> offs
= instr
4021 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4022 : std::make_pair(Temp(), 0u);
4024 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4025 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4030 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4031 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4033 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4034 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4036 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4037 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4043 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4045 Builder
bld(ctx
->program
, ctx
->block
);
4047 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4048 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4050 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4052 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4053 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4054 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4056 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4057 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4062 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4064 Builder
bld(ctx
->program
, ctx
->block
);
4066 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4067 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4068 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4069 unsigned attr_stride
= ctx
->tcs_num_patches
;
4071 std::pair
<Temp
, unsigned> offs
= instr
4072 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4073 : std::make_pair(Temp(), 0u);
4075 if (const_base_offset
)
4076 offs
.second
+= const_base_offset
* attr_stride
;
4078 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4079 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4080 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4085 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4087 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4092 unsigned drv_loc
= nir_intrinsic_base(instr
);
4093 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4095 if (!nir_src_is_const(*off_src
)) {
4101 uint64_t slot
= per_vertex
4102 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4103 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4104 return (((uint64_t) 1) << slot
) & mask
;
4107 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4109 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4110 unsigned component
= nir_intrinsic_component(instr
);
4111 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4113 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4114 if (off_instr
->type
!= nir_instr_type_load_const
)
4117 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4118 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4120 if (instr
->src
[0].ssa
->bit_size
== 64)
4121 write_mask
= widen_mask(write_mask
, 2);
4123 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4125 for (unsigned i
= 0; i
< 8; ++i
) {
4126 if (write_mask
& (1 << i
)) {
4127 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4128 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4136 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4138 /* Only TCS per-vertex inputs are supported by this function.
4139 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4141 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4144 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4145 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4146 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4147 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4148 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4149 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4154 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4155 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4156 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4161 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4163 Builder
bld(ctx
->program
, ctx
->block
);
4165 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4166 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4167 bool indirect_write
;
4168 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4169 if (temp_only_input
&& !indirect_write
)
4173 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4174 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4175 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4176 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4178 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4179 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4180 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4181 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4182 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4186 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4187 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4188 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4189 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4190 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4191 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4192 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4193 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4194 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4195 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4196 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4197 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4198 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4200 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4201 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4203 unreachable("Invalid LS or ES stage");
4206 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4207 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4208 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4212 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4217 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4218 return off
== ctx
->tcs_tess_lvl_out_loc
||
4219 off
== ctx
->tcs_tess_lvl_in_loc
;
4223 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4225 uint64_t mask
= per_vertex
4226 ? ctx
->program
->info
->tcs
.tes_inputs_read
4227 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4229 bool indirect_write
= false;
4230 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4231 return indirect_write
|| output_read_by_tes
;
4234 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4236 uint64_t mask
= per_vertex
4237 ? ctx
->shader
->info
.outputs_read
4238 : ctx
->shader
->info
.patch_outputs_read
;
4240 bool indirect_write
= false;
4241 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4242 return indirect_write
|| output_read
;
4245 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4247 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4248 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4250 Builder
bld(ctx
->program
, ctx
->block
);
4252 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4253 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4254 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4256 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4257 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4258 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4260 if (write_to_vmem
) {
4261 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4262 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4263 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4265 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4266 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4267 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4271 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4272 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4273 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4277 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4279 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4280 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4282 Builder
bld(ctx
->program
, ctx
->block
);
4284 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4285 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4286 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4287 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4289 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4292 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4294 if (ctx
->stage
== vertex_vs
||
4295 ctx
->stage
== tess_eval_vs
||
4296 ctx
->stage
== fragment_fs
||
4297 ctx
->stage
== ngg_vertex_gs
||
4298 ctx
->stage
== ngg_tess_eval_gs
||
4299 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4300 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4301 if (!stored_to_temps
) {
4302 isel_err(instr
->src
[1].ssa
->parent_instr
, "Unimplemented output offset instruction");
4305 } else if (ctx
->stage
== vertex_es
||
4306 ctx
->stage
== vertex_ls
||
4307 ctx
->stage
== tess_eval_es
||
4308 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4309 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4310 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4311 visit_store_ls_or_es_output(ctx
, instr
);
4312 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4313 visit_store_tcs_output(ctx
, instr
, false);
4315 unreachable("Shader stage not implemented");
4319 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4321 visit_load_tcs_output(ctx
, instr
, false);
4324 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4326 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4327 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4329 Builder
bld(ctx
->program
, ctx
->block
);
4331 if (dst
.regClass() == v2b
) {
4332 if (ctx
->program
->has_16bank_lds
) {
4333 assert(ctx
->options
->chip_class
<= GFX8
);
4334 Builder::Result interp_p1
=
4335 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4336 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4337 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4338 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4339 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4340 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4342 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4344 if (ctx
->options
->chip_class
== GFX8
)
4345 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4347 Builder::Result interp_p1
=
4348 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4349 coord1
, bld
.m0(prim_mask
), idx
, component
);
4350 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4351 interp_p1
, idx
, component
);
4354 Builder::Result interp_p1
=
4355 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4356 bld
.m0(prim_mask
), idx
, component
);
4358 if (ctx
->program
->has_16bank_lds
)
4359 interp_p1
.instr
->operands
[0].setLateKill(true);
4361 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4362 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4366 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4368 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4369 for (unsigned i
= 0; i
< num_components
; i
++)
4370 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4371 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4372 assert(num_components
== 4);
4373 Builder
bld(ctx
->program
, ctx
->block
);
4374 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4377 for (Operand
& op
: vec
->operands
)
4378 op
= op
.isUndefined() ? Operand(0u) : op
;
4380 vec
->definitions
[0] = Definition(dst
);
4381 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4382 emit_split_vector(ctx
, dst
, num_components
);
4386 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4388 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4389 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4390 unsigned idx
= nir_intrinsic_base(instr
);
4391 unsigned component
= nir_intrinsic_component(instr
);
4392 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4394 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4396 assert(offset
->u32
== 0);
4398 /* the lower 15bit of the prim_mask contain the offset into LDS
4399 * while the upper bits contain the number of prims */
4400 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4401 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4402 Builder
bld(ctx
->program
, ctx
->block
);
4403 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4404 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4405 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4406 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4407 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4410 if (instr
->dest
.ssa
.num_components
== 1) {
4411 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4413 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4414 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4416 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4417 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4418 vec
->operands
[i
] = Operand(tmp
);
4420 vec
->definitions
[0] = Definition(dst
);
4421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4425 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4426 unsigned offset
, unsigned stride
, unsigned channels
)
4428 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4429 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4431 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4432 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4435 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4436 unsigned offset
, unsigned stride
, unsigned *channels
)
4438 if (!vtx_info
->chan_byte_size
) {
4439 *channels
= vtx_info
->num_channels
;
4440 return vtx_info
->chan_format
;
4443 unsigned num_channels
= *channels
;
4444 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4445 unsigned new_channels
= num_channels
+ 1;
4446 /* first, assume more loads is worse and try using a larger data format */
4447 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4449 /* don't make the attribute potentially out-of-bounds */
4450 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4454 if (new_channels
== 5) {
4455 /* then try decreasing load size (at the cost of more loads) */
4456 new_channels
= *channels
;
4457 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4461 if (new_channels
< *channels
)
4462 *channels
= new_channels
;
4463 num_channels
= new_channels
;
4466 switch (vtx_info
->chan_format
) {
4467 case V_008F0C_BUF_DATA_FORMAT_8
:
4468 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4469 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4470 case V_008F0C_BUF_DATA_FORMAT_16
:
4471 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4472 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4473 case V_008F0C_BUF_DATA_FORMAT_32
:
4474 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4475 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4477 unreachable("shouldn't reach here");
4478 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4481 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4482 * so we may need to fix it up. */
4483 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4485 Builder
bld(ctx
->program
, ctx
->block
);
4487 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4488 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4490 /* For the integer-like cases, do a natural sign extension.
4492 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4493 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4496 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4497 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4499 /* Convert back to the right type. */
4500 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4501 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4502 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4503 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4504 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4505 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4511 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4513 Builder
bld(ctx
->program
, ctx
->block
);
4514 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4515 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4517 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4518 if (off_instr
->type
!= nir_instr_type_load_const
) {
4519 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4521 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4523 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4525 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4526 unsigned component
= nir_intrinsic_component(instr
);
4527 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4528 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4529 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4530 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4531 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4533 unsigned dfmt
= attrib_format
& 0xf;
4534 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4535 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4537 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4538 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4539 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4540 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4542 num_channels
= MAX2(num_channels
, 3);
4544 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4545 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4548 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4549 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4550 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4552 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4554 Temp divided
= bld
.tmp(v1
);
4555 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4556 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4558 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4561 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4564 index
= bld
.vadd32(bld
.def(v1
),
4565 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4566 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4569 Temp channels
[num_channels
];
4570 unsigned channel_start
= 0;
4571 bool direct_fetch
= false;
4573 /* skip unused channels at the start */
4574 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4575 channel_start
= ffs(mask
) - 1;
4576 for (unsigned i
= 0; i
< channel_start
; i
++)
4577 channels
[i
] = Temp(0, s1
);
4578 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4579 num_channels
= 3 - (ffs(mask
) - 1);
4583 while (channel_start
< num_channels
) {
4584 unsigned fetch_component
= num_channels
- channel_start
;
4585 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4586 bool expanded
= false;
4588 /* use MUBUF when possible to avoid possible alignment issues */
4589 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4590 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4591 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4592 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4593 vtx_info
->chan_byte_size
== 4;
4594 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4596 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4598 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4599 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4600 fetch_component
= 4;
4605 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4607 Temp fetch_index
= index
;
4608 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4609 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4610 fetch_offset
= fetch_offset
% attrib_stride
;
4613 Operand
soffset(0u);
4614 if (fetch_offset
>= 4096) {
4615 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4616 fetch_offset
%= 4096;
4620 switch (fetch_bytes
) {
4622 assert(!use_mubuf
&& bitsize
== 16);
4623 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4626 if (bitsize
== 16) {
4628 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4630 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4634 assert(!use_mubuf
&& bitsize
== 16);
4635 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4638 if (bitsize
== 16) {
4640 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4642 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4646 assert(ctx
->options
->chip_class
>= GFX7
||
4647 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4648 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4651 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4654 unreachable("Unimplemented load_input vector size");
4658 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4659 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4660 num_channels
<= 3)) {
4661 direct_fetch
= true;
4664 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4669 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4670 fetch_offset
, false, false, true).instr
;
4673 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4674 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4677 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4679 if (fetch_component
== 1) {
4680 channels
[channel_start
] = fetch_dst
;
4682 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4683 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4684 bitsize
== 16 ? v2b
: v1
);
4687 channel_start
+= fetch_component
;
4690 if (!direct_fetch
) {
4691 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4692 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4694 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4695 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4696 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4698 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4699 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4700 unsigned num_temp
= 0;
4701 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4702 unsigned idx
= i
+ component
;
4703 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4704 Temp channel
= channels
[swizzle
[idx
]];
4705 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4706 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4707 vec
->operands
[i
] = Operand(channel
);
4711 } else if (is_float
&& idx
== 3) {
4712 vec
->operands
[i
] = Operand(0x3f800000u
);
4713 } else if (!is_float
&& idx
== 3) {
4714 vec
->operands
[i
] = Operand(1u);
4716 vec
->operands
[i
] = Operand(0u);
4719 vec
->definitions
[0] = Definition(dst
);
4720 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4721 emit_split_vector(ctx
, dst
, dst
.size());
4723 if (num_temp
== dst
.size())
4724 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4726 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4727 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4728 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4729 if (off_instr
->type
!= nir_instr_type_load_const
||
4730 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4731 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4734 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4735 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4737 assert(offset
->u32
== 0);
4739 /* the lower 15bit of the prim_mask contain the offset into LDS
4740 * while the upper bits contain the number of prims */
4741 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4742 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4743 Builder
bld(ctx
->program
, ctx
->block
);
4744 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4745 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4746 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4747 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4748 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4751 unsigned idx
= nir_intrinsic_base(instr
);
4752 unsigned component
= nir_intrinsic_component(instr
);
4753 unsigned vertex_id
= 2; /* P0 */
4755 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4756 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4757 switch (src0
->u32
) {
4759 vertex_id
= 2; /* P0 */
4762 vertex_id
= 0; /* P10 */
4765 vertex_id
= 1; /* P20 */
4768 unreachable("invalid vertex index");
4772 if (dst
.size() == 1) {
4773 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4775 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4776 for (unsigned i
= 0; i
< dst
.size(); i
++)
4777 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4778 vec
->definitions
[0] = Definition(dst
);
4779 bld
.insert(std::move(vec
));
4782 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4783 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4784 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4785 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4786 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4788 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4790 unreachable("Shader stage not implemented");
4794 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4796 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4798 Builder
bld(ctx
->program
, ctx
->block
);
4799 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4802 if (!nir_src_is_const(*vertex_src
)) {
4803 /* better code could be created, but this case probably doesn't happen
4804 * much in practice */
4805 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4806 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4809 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4810 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4812 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4814 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4817 if (vertex_offset
.id()) {
4818 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4819 Operand(i
), indirect_vertex
);
4820 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4822 vertex_offset
= elem
;
4826 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4827 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4829 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4830 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4831 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4832 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4833 Operand((vertex
% 2u) * 16u), Operand(16u));
4835 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4838 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4839 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4840 return offset_mul(ctx
, offs
, 4u);
4843 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4845 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4847 Builder
bld(ctx
->program
, ctx
->block
);
4848 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4849 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4851 if (ctx
->stage
== geometry_gs
) {
4852 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4853 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4854 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4855 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4856 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4857 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4858 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4860 unreachable("Unsupported GS stage.");
4864 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4866 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4868 Builder
bld(ctx
->program
, ctx
->block
);
4869 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4871 if (load_input_from_temps(ctx
, instr
, dst
))
4874 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4875 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4876 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4878 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4881 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4883 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4885 Builder
bld(ctx
->program
, ctx
->block
);
4887 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4888 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4889 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4891 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4892 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4894 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4897 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4899 switch (ctx
->shader
->info
.stage
) {
4900 case MESA_SHADER_GEOMETRY
:
4901 visit_load_gs_per_vertex_input(ctx
, instr
);
4903 case MESA_SHADER_TESS_CTRL
:
4904 visit_load_tcs_per_vertex_input(ctx
, instr
);
4906 case MESA_SHADER_TESS_EVAL
:
4907 visit_load_tes_per_vertex_input(ctx
, instr
);
4910 unreachable("Unimplemented shader stage");
4914 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4916 visit_load_tcs_output(ctx
, instr
, true);
4919 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4921 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4922 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4924 visit_store_tcs_output(ctx
, instr
, true);
4927 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4929 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4931 Builder
bld(ctx
->program
, ctx
->block
);
4932 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4934 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4935 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4938 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4939 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4940 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4941 tes_w
= Operand(tmp
);
4944 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4945 emit_split_vector(ctx
, tess_coord
, 3);
4948 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4950 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4951 Builder
bld(ctx
->program
, ctx
->block
);
4952 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4953 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4954 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4957 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4961 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4963 Builder
bld(ctx
->program
, ctx
->block
);
4964 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4965 if (!nir_dest_is_divergent(instr
->dest
))
4966 index
= bld
.as_uniform(index
);
4967 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4968 unsigned binding
= nir_intrinsic_binding(instr
);
4971 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4972 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4973 unsigned offset
= layout
->binding
[binding
].offset
;
4975 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4976 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4977 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4978 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4979 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4982 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4983 stride
= layout
->binding
[binding
].size
;
4986 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4987 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4989 if (nir_const_index
) {
4990 const_index
= const_index
* stride
;
4991 } else if (index
.type() == RegType::vgpr
) {
4992 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4993 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4995 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4999 if (nir_const_index
) {
5000 const_index
= const_index
+ offset
;
5001 } else if (index
.type() == RegType::vgpr
) {
5002 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5004 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5008 if (nir_const_index
&& const_index
== 0) {
5010 } else if (index
.type() == RegType::vgpr
) {
5011 index
= bld
.vadd32(bld
.def(v1
),
5012 nir_const_index
? Operand(const_index
) : Operand(index
),
5015 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5016 nir_const_index
? Operand(const_index
) : Operand(index
),
5020 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5023 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5024 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5025 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5027 Builder
bld(ctx
->program
, ctx
->block
);
5029 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5031 offset
= bld
.as_uniform(offset
);
5033 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5036 info
.align_mul
= align_mul
;
5037 info
.align_offset
= align_offset
;
5039 emit_smem_load(ctx
, bld
, &info
);
5041 emit_mubuf_load(ctx
, bld
, &info
);
5044 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5046 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5047 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5049 Builder
bld(ctx
->program
, ctx
->block
);
5051 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5052 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5053 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5054 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5056 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5057 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5058 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5059 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5060 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5061 if (ctx
->options
->chip_class
>= GFX10
) {
5062 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5063 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5064 S_008F0C_RESOURCE_LEVEL(1);
5066 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5067 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5069 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5070 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5071 Operand(0xFFFFFFFFu
),
5072 Operand(desc_type
));
5073 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5074 rsrc
, upper_dwords
);
5076 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5077 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5079 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5080 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5081 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5084 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5086 Builder
bld(ctx
->program
, ctx
->block
);
5087 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5088 unsigned offset
= nir_intrinsic_base(instr
);
5089 unsigned count
= instr
->dest
.ssa
.num_components
;
5090 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5092 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5093 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5094 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5095 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5096 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5097 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5098 for (unsigned i
= 0; i
< count
; ++i
) {
5099 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5100 vec
->operands
[i
] = Operand
{elems
[i
]};
5102 vec
->definitions
[0] = Definition(dst
);
5103 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5104 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5109 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5110 if (offset
!= 0) // TODO check if index != 0 as well
5111 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5112 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5115 bool aligned
= true;
5117 if (instr
->dest
.ssa
.bit_size
== 8) {
5118 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5119 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5121 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5122 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5123 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5125 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5130 switch (vec
.size()) {
5132 op
= aco_opcode::s_load_dword
;
5135 op
= aco_opcode::s_load_dwordx2
;
5141 op
= aco_opcode::s_load_dwordx4
;
5147 op
= aco_opcode::s_load_dwordx8
;
5150 unreachable("unimplemented or forbidden load_push_constant.");
5153 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5156 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5157 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5162 emit_split_vector(ctx
, vec
, 4);
5163 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5164 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5165 emit_extract_vector(ctx
, vec
, 0, rc
),
5166 emit_extract_vector(ctx
, vec
, 1, rc
),
5167 emit_extract_vector(ctx
, vec
, 2, rc
));
5170 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5173 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5175 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5177 Builder
bld(ctx
->program
, ctx
->block
);
5179 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5180 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5181 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5182 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5183 if (ctx
->options
->chip_class
>= GFX10
) {
5184 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5185 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5186 S_008F0C_RESOURCE_LEVEL(1);
5188 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5189 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5192 unsigned base
= nir_intrinsic_base(instr
);
5193 unsigned range
= nir_intrinsic_range(instr
);
5195 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5196 if (base
&& offset
.type() == RegType::sgpr
)
5197 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5198 else if (base
&& offset
.type() == RegType::vgpr
)
5199 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5201 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5202 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5203 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5204 Operand(desc_type
));
5205 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5206 // TODO: get alignment information for subdword constants
5207 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5210 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5212 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5213 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5215 ctx
->program
->needs_exact
= true;
5217 // TODO: optimize uniform conditions
5218 Builder
bld(ctx
->program
, ctx
->block
);
5219 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5220 assert(src
.regClass() == bld
.lm
);
5221 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5222 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5223 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5227 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5229 Builder
bld(ctx
->program
, ctx
->block
);
5231 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5232 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5234 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5235 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5237 if (ctx
->block
->loop_nest_depth
&&
5238 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5239 /* we handle discards the same way as jump instructions */
5240 append_logical_end(ctx
->block
);
5242 /* in loops, discard behaves like break */
5243 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5244 ctx
->block
->kind
|= block_kind_discard
;
5247 /* uniform discard - loop ends here */
5248 assert(nir_instr_is_last(&instr
->instr
));
5249 ctx
->block
->kind
|= block_kind_uniform
;
5250 ctx
->cf_info
.has_branch
= true;
5251 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5252 add_linear_edge(ctx
->block
->index
, linear_target
);
5256 /* we add a break right behind the discard() instructions */
5257 ctx
->block
->kind
|= block_kind_break
;
5258 unsigned idx
= ctx
->block
->index
;
5260 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5261 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5263 /* remove critical edges from linear CFG */
5264 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5265 Block
* break_block
= ctx
->program
->create_and_insert_block();
5266 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5267 break_block
->kind
|= block_kind_uniform
;
5268 add_linear_edge(idx
, break_block
);
5269 add_linear_edge(break_block
->index
, linear_target
);
5270 bld
.reset(break_block
);
5271 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5273 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5274 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5275 add_linear_edge(idx
, continue_block
);
5276 append_logical_start(continue_block
);
5277 ctx
->block
= continue_block
;
5282 /* it can currently happen that NIR doesn't remove the unreachable code */
5283 if (!nir_instr_is_last(&instr
->instr
)) {
5284 ctx
->program
->needs_exact
= true;
5285 /* save exec somewhere temporarily so that it doesn't get
5286 * overwritten before the discard from outer exec masks */
5287 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5288 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5289 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5293 /* This condition is incorrect for uniformly branched discards in a loop
5294 * predicated by a divergent condition, but the above code catches that case
5295 * and the discard would end up turning into a discard_if.
5305 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5306 /* program just ends here */
5307 ctx
->block
->kind
|= block_kind_uniform
;
5308 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5309 0 /* enabled mask */, 9 /* dest */,
5310 false /* compressed */, true/* done */, true /* valid mask */);
5311 bld
.sopp(aco_opcode::s_endpgm
);
5312 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5314 ctx
->block
->kind
|= block_kind_discard
;
5315 /* branch and linear edge is added by visit_if() */
5319 enum aco_descriptor_type
{
5330 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5331 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5333 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5334 return dim
== ac_image_cube
||
5335 dim
== ac_image_1darray
||
5336 dim
== ac_image_2darray
||
5337 dim
== ac_image_2darraymsaa
;
5340 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5341 enum aco_descriptor_type desc_type
,
5342 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5344 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5345 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5346 if (it != ctx->tex_desc.end())
5349 Temp index
= Temp();
5350 bool index_set
= false;
5351 unsigned constant_index
= 0;
5352 unsigned descriptor_set
;
5353 unsigned base_index
;
5354 Builder
bld(ctx
->program
, ctx
->block
);
5357 assert(tex_instr
&& !image
);
5359 base_index
= tex_instr
->sampler_index
;
5361 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5362 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5366 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5367 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5369 constant_index
+= array_size
* const_value
->u32
;
5371 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5372 if (indirect
.type() == RegType::vgpr
)
5373 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5375 if (array_size
!= 1)
5376 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5382 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5386 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5388 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5389 base_index
= deref_instr
->var
->data
.binding
;
5392 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5393 list
= convert_pointer_to_64_bit(ctx
, list
);
5395 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5396 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5397 unsigned offset
= binding
->offset
;
5398 unsigned stride
= binding
->size
;
5402 assert(base_index
< layout
->binding_count
);
5404 switch (desc_type
) {
5405 case ACO_DESC_IMAGE
:
5407 opcode
= aco_opcode::s_load_dwordx8
;
5409 case ACO_DESC_FMASK
:
5411 opcode
= aco_opcode::s_load_dwordx8
;
5414 case ACO_DESC_SAMPLER
:
5416 opcode
= aco_opcode::s_load_dwordx4
;
5417 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5418 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5420 case ACO_DESC_BUFFER
:
5422 opcode
= aco_opcode::s_load_dwordx4
;
5424 case ACO_DESC_PLANE_0
:
5425 case ACO_DESC_PLANE_1
:
5427 opcode
= aco_opcode::s_load_dwordx8
;
5428 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5430 case ACO_DESC_PLANE_2
:
5432 opcode
= aco_opcode::s_load_dwordx4
;
5436 unreachable("invalid desc_type\n");
5439 offset
+= constant_index
* stride
;
5441 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5442 (!index_set
|| binding
->immutable_samplers_equal
)) {
5443 if (binding
->immutable_samplers_equal
)
5446 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5447 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5448 Operand(samplers
[constant_index
* 4 + 0]),
5449 Operand(samplers
[constant_index
* 4 + 1]),
5450 Operand(samplers
[constant_index
* 4 + 2]),
5451 Operand(samplers
[constant_index
* 4 + 3]));
5456 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5458 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5459 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5462 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5464 if (desc_type
== ACO_DESC_PLANE_2
) {
5466 for (unsigned i
= 0; i
< 8; i
++)
5467 components
[i
] = bld
.tmp(s1
);
5468 bld
.pseudo(aco_opcode::p_split_vector
,
5469 Definition(components
[0]),
5470 Definition(components
[1]),
5471 Definition(components
[2]),
5472 Definition(components
[3]),
5475 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5476 bld
.pseudo(aco_opcode::p_split_vector
,
5477 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5478 Definition(components
[4]),
5479 Definition(components
[5]),
5480 Definition(components
[6]),
5481 Definition(components
[7]),
5484 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5485 components
[0], components
[1], components
[2], components
[3],
5486 components
[4], components
[5], components
[6], components
[7]);
5492 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5495 case GLSL_SAMPLER_DIM_BUF
:
5497 case GLSL_SAMPLER_DIM_1D
:
5498 return array
? 2 : 1;
5499 case GLSL_SAMPLER_DIM_2D
:
5500 return array
? 3 : 2;
5501 case GLSL_SAMPLER_DIM_MS
:
5502 return array
? 4 : 3;
5503 case GLSL_SAMPLER_DIM_3D
:
5504 case GLSL_SAMPLER_DIM_CUBE
:
5506 case GLSL_SAMPLER_DIM_RECT
:
5507 case GLSL_SAMPLER_DIM_SUBPASS
:
5509 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5518 /* Adjust the sample index according to FMASK.
5520 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5521 * which is the identity mapping. Each nibble says which physical sample
5522 * should be fetched to get that sample.
5524 * For example, 0x11111100 means there are only 2 samples stored and
5525 * the second sample covers 3/4 of the pixel. When reading samples 0
5526 * and 1, return physical sample 0 (determined by the first two 0s
5527 * in FMASK), otherwise return physical sample 1.
5529 * The sample index should be adjusted as follows:
5530 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5532 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5534 Builder
bld(ctx
->program
, ctx
->block
);
5535 Temp fmask
= bld
.tmp(v1
);
5536 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5537 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5540 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5541 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5542 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5543 load
->operands
[0] = Operand(fmask_desc_ptr
);
5544 load
->operands
[1] = Operand(s4
); /* no sampler */
5545 load
->operands
[2] = Operand(coord
);
5546 load
->definitions
[0] = Definition(fmask
);
5553 ctx
->block
->instructions
.emplace_back(std::move(load
));
5555 Operand sample_index4
;
5556 if (sample_index
.isConstant()) {
5557 if (sample_index
.constantValue() < 16) {
5558 sample_index4
= Operand(sample_index
.constantValue() << 2);
5560 sample_index4
= Operand(0u);
5562 } else if (sample_index
.regClass() == s1
) {
5563 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5565 assert(sample_index
.regClass() == v1
);
5566 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5570 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5571 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5572 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5573 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5575 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5577 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5578 * resource descriptor is 0 (invalid),
5580 Temp compare
= bld
.tmp(bld
.lm
);
5581 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5582 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5584 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5586 /* Replace the MSAA sample index. */
5587 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5590 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5593 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5594 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5595 bool is_array
= glsl_sampler_type_is_array(type
);
5596 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5597 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5598 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5599 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5600 int count
= image_type_to_components_count(dim
, is_array
);
5601 std::vector
<Temp
> coords(count
);
5602 Builder
bld(ctx
->program
, ctx
->block
);
5606 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5607 /* get sample index */
5608 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5609 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5610 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5611 std::vector
<Temp
> fmask_load_address
;
5612 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5613 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5615 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5616 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5618 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5623 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5624 coords
.resize(coords
.size() + 1);
5625 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5627 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5629 for (int i
= 0; i
< count
; i
++)
5630 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5633 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5634 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5635 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5636 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5639 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5642 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5643 for (unsigned i
= 0; i
< coords
.size(); i
++)
5644 vec
->operands
[i
] = Operand(coords
[i
]);
5645 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5646 vec
->definitions
[0] = Definition(res
);
5647 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5652 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5654 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5655 if (semantics
& semantic_atomicrmw
)
5656 return memory_sync_info(storage
, semantics
);
5658 unsigned access
= nir_intrinsic_access(instr
);
5660 if (access
& ACCESS_VOLATILE
)
5661 semantics
|= semantic_volatile
;
5662 if (access
& ACCESS_CAN_REORDER
)
5663 semantics
|= semantic_can_reorder
| semantic_private
;
5665 return memory_sync_info(storage
, semantics
);
5668 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5670 Builder
bld(ctx
->program
, ctx
->block
);
5671 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5672 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5673 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5674 bool is_array
= glsl_sampler_type_is_array(type
);
5675 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5677 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5678 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5680 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5681 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5682 unsigned num_channels
= util_last_bit(mask
);
5683 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5684 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5687 switch (num_channels
) {
5689 opcode
= aco_opcode::buffer_load_format_x
;
5692 opcode
= aco_opcode::buffer_load_format_xy
;
5695 opcode
= aco_opcode::buffer_load_format_xyz
;
5698 opcode
= aco_opcode::buffer_load_format_xyzw
;
5701 unreachable(">4 channel buffer image load");
5703 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5704 load
->operands
[0] = Operand(rsrc
);
5705 load
->operands
[1] = Operand(vindex
);
5706 load
->operands
[2] = Operand((uint32_t) 0);
5708 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5711 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5712 load
->definitions
[0] = Definition(tmp
);
5714 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5715 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5717 ctx
->block
->instructions
.emplace_back(std::move(load
));
5719 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5723 Temp coords
= get_image_coords(ctx
, instr
, type
);
5724 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5726 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5727 unsigned num_components
= util_bitcount(dmask
);
5729 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5732 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5734 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5735 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5737 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5738 load
->operands
[0] = Operand(resource
);
5739 load
->operands
[1] = Operand(s4
); /* no sampler */
5740 load
->operands
[2] = Operand(coords
);
5741 load
->definitions
[0] = Definition(tmp
);
5742 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5743 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5744 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5745 load
->dmask
= dmask
;
5747 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5749 ctx
->block
->instructions
.emplace_back(std::move(load
));
5751 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5755 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5757 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5758 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5759 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5760 bool is_array
= glsl_sampler_type_is_array(type
);
5761 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5763 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5764 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5765 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5767 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5768 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5769 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5771 switch (data
.size()) {
5773 opcode
= aco_opcode::buffer_store_format_x
;
5776 opcode
= aco_opcode::buffer_store_format_xy
;
5779 opcode
= aco_opcode::buffer_store_format_xyz
;
5782 opcode
= aco_opcode::buffer_store_format_xyzw
;
5785 unreachable(">4 channel buffer image store");
5787 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5788 store
->operands
[0] = Operand(rsrc
);
5789 store
->operands
[1] = Operand(vindex
);
5790 store
->operands
[2] = Operand((uint32_t) 0);
5791 store
->operands
[3] = Operand(data
);
5792 store
->idxen
= true;
5795 store
->disable_wqm
= true;
5797 ctx
->program
->needs_exact
= true;
5798 ctx
->block
->instructions
.emplace_back(std::move(store
));
5802 assert(data
.type() == RegType::vgpr
);
5803 Temp coords
= get_image_coords(ctx
, instr
, type
);
5804 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5806 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5807 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5809 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5810 store
->operands
[0] = Operand(resource
);
5811 store
->operands
[1] = Operand(data
);
5812 store
->operands
[2] = Operand(coords
);
5815 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5816 store
->dmask
= (1 << data
.size()) - 1;
5818 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5819 store
->disable_wqm
= true;
5821 ctx
->program
->needs_exact
= true;
5822 ctx
->block
->instructions
.emplace_back(std::move(store
));
5826 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5828 /* return the previous value if dest is ever used */
5829 bool return_previous
= false;
5830 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5831 return_previous
= true;
5834 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5835 return_previous
= true;
5839 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5840 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5841 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5842 bool is_array
= glsl_sampler_type_is_array(type
);
5843 Builder
bld(ctx
->program
, ctx
->block
);
5845 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5846 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5848 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5849 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5851 aco_opcode buf_op
, image_op
;
5852 switch (instr
->intrinsic
) {
5853 case nir_intrinsic_image_deref_atomic_add
:
5854 buf_op
= aco_opcode::buffer_atomic_add
;
5855 image_op
= aco_opcode::image_atomic_add
;
5857 case nir_intrinsic_image_deref_atomic_umin
:
5858 buf_op
= aco_opcode::buffer_atomic_umin
;
5859 image_op
= aco_opcode::image_atomic_umin
;
5861 case nir_intrinsic_image_deref_atomic_imin
:
5862 buf_op
= aco_opcode::buffer_atomic_smin
;
5863 image_op
= aco_opcode::image_atomic_smin
;
5865 case nir_intrinsic_image_deref_atomic_umax
:
5866 buf_op
= aco_opcode::buffer_atomic_umax
;
5867 image_op
= aco_opcode::image_atomic_umax
;
5869 case nir_intrinsic_image_deref_atomic_imax
:
5870 buf_op
= aco_opcode::buffer_atomic_smax
;
5871 image_op
= aco_opcode::image_atomic_smax
;
5873 case nir_intrinsic_image_deref_atomic_and
:
5874 buf_op
= aco_opcode::buffer_atomic_and
;
5875 image_op
= aco_opcode::image_atomic_and
;
5877 case nir_intrinsic_image_deref_atomic_or
:
5878 buf_op
= aco_opcode::buffer_atomic_or
;
5879 image_op
= aco_opcode::image_atomic_or
;
5881 case nir_intrinsic_image_deref_atomic_xor
:
5882 buf_op
= aco_opcode::buffer_atomic_xor
;
5883 image_op
= aco_opcode::image_atomic_xor
;
5885 case nir_intrinsic_image_deref_atomic_exchange
:
5886 buf_op
= aco_opcode::buffer_atomic_swap
;
5887 image_op
= aco_opcode::image_atomic_swap
;
5889 case nir_intrinsic_image_deref_atomic_comp_swap
:
5890 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5891 image_op
= aco_opcode::image_atomic_cmpswap
;
5894 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5897 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5898 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
5900 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5901 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5902 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5903 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5904 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5905 mubuf
->operands
[0] = Operand(resource
);
5906 mubuf
->operands
[1] = Operand(vindex
);
5907 mubuf
->operands
[2] = Operand((uint32_t)0);
5908 mubuf
->operands
[3] = Operand(data
);
5909 if (return_previous
)
5910 mubuf
->definitions
[0] = Definition(dst
);
5912 mubuf
->idxen
= true;
5913 mubuf
->glc
= return_previous
;
5914 mubuf
->dlc
= false; /* Not needed for atomics */
5915 mubuf
->disable_wqm
= true;
5917 ctx
->program
->needs_exact
= true;
5918 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5922 Temp coords
= get_image_coords(ctx
, instr
, type
);
5923 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5924 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5925 mimg
->operands
[0] = Operand(resource
);
5926 mimg
->operands
[1] = Operand(data
);
5927 mimg
->operands
[2] = Operand(coords
);
5928 if (return_previous
)
5929 mimg
->definitions
[0] = Definition(dst
);
5930 mimg
->glc
= return_previous
;
5931 mimg
->dlc
= false; /* Not needed for atomics */
5932 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5933 mimg
->dmask
= (1 << data
.size()) - 1;
5935 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5936 mimg
->disable_wqm
= true;
5938 ctx
->program
->needs_exact
= true;
5939 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5943 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5945 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5946 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5947 Builder
bld(ctx
->program
, ctx
->block
);
5949 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5951 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5952 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5954 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5955 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5957 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5958 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5960 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5961 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5962 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5963 if (dst
.type() == RegType::vgpr
)
5964 bld
.copy(Definition(dst
), shr_dst
);
5966 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5968 emit_extract_vector(ctx
, desc
, 2, dst
);
5972 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5974 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5975 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5976 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5977 bool is_array
= glsl_sampler_type_is_array(type
);
5978 Builder
bld(ctx
->program
, ctx
->block
);
5980 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5981 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5982 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5986 assert(nir_src_as_uint(instr
->src
[1]) == 0);
5987 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5990 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5992 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5994 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5995 mimg
->operands
[0] = Operand(resource
);
5996 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5997 mimg
->operands
[2] = Operand(lod
);
5998 uint8_t& dmask
= mimg
->dmask
;
5999 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6000 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6001 mimg
->da
= glsl_sampler_type_is_array(type
);
6002 Definition
& def
= mimg
->definitions
[0];
6003 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6005 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6006 glsl_sampler_type_is_array(type
)) {
6008 assert(instr
->dest
.ssa
.num_components
== 3);
6009 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6010 def
= Definition(tmp
);
6011 emit_split_vector(ctx
, tmp
, 3);
6013 /* divide 3rd value by 6 by multiplying with magic number */
6014 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6015 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6017 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6018 emit_extract_vector(ctx
, tmp
, 0, v1
),
6019 emit_extract_vector(ctx
, tmp
, 1, v1
),
6022 } else if (ctx
->options
->chip_class
== GFX9
&&
6023 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6024 glsl_sampler_type_is_array(type
)) {
6025 assert(instr
->dest
.ssa
.num_components
== 2);
6026 def
= Definition(dst
);
6029 def
= Definition(dst
);
6032 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6035 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6037 Builder
bld(ctx
->program
, ctx
->block
);
6038 unsigned num_components
= instr
->num_components
;
6040 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6041 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6042 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6044 unsigned access
= nir_intrinsic_access(instr
);
6045 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6046 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6048 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6049 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6050 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6052 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6053 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6055 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6056 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6057 get_memory_sync_info(instr
, storage_buffer
, 0));
6060 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6062 Builder
bld(ctx
->program
, ctx
->block
);
6063 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6064 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6065 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6066 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6068 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6069 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6071 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6072 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6073 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6074 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6075 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6077 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6079 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6080 ctx
->options
->chip_class
>= GFX8
&&
6081 ctx
->options
->chip_class
< GFX10_3
&&
6082 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6085 offset
= bld
.as_uniform(offset
);
6086 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6088 unsigned write_count
= 0;
6089 Temp write_datas
[32];
6090 unsigned offsets
[32];
6091 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6092 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6094 for (unsigned i
= 0; i
< write_count
; i
++) {
6095 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6096 if (smem
&& ctx
->stage
== fragment_fs
)
6097 op
= aco_opcode::p_fs_buffer_store_smem
;
6100 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6101 store
->operands
[0] = Operand(rsrc
);
6103 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6104 offset
, Operand(offsets
[i
]));
6105 store
->operands
[1] = Operand(off
);
6107 store
->operands
[1] = Operand(offset
);
6109 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6110 store
->operands
[1].setFixed(m0
);
6111 store
->operands
[2] = Operand(write_datas
[i
]);
6114 store
->disable_wqm
= true;
6116 ctx
->block
->instructions
.emplace_back(std::move(store
));
6117 ctx
->program
->wb_smem_l1_on_end
= true;
6118 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6119 ctx
->block
->kind
|= block_kind_needs_lowering
;
6120 ctx
->program
->needs_exact
= true;
6123 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6124 store
->operands
[0] = Operand(rsrc
);
6125 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6126 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6127 store
->operands
[3] = Operand(write_datas
[i
]);
6128 store
->offset
= offsets
[i
];
6129 store
->offen
= (offset
.type() == RegType::vgpr
);
6132 store
->disable_wqm
= true;
6134 ctx
->program
->needs_exact
= true;
6135 ctx
->block
->instructions
.emplace_back(std::move(store
));
6140 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6142 /* return the previous value if dest is ever used */
6143 bool return_previous
= false;
6144 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6145 return_previous
= true;
6148 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6149 return_previous
= true;
6153 Builder
bld(ctx
->program
, ctx
->block
);
6154 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6156 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6157 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6158 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6160 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6161 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6162 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6164 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6166 aco_opcode op32
, op64
;
6167 switch (instr
->intrinsic
) {
6168 case nir_intrinsic_ssbo_atomic_add
:
6169 op32
= aco_opcode::buffer_atomic_add
;
6170 op64
= aco_opcode::buffer_atomic_add_x2
;
6172 case nir_intrinsic_ssbo_atomic_imin
:
6173 op32
= aco_opcode::buffer_atomic_smin
;
6174 op64
= aco_opcode::buffer_atomic_smin_x2
;
6176 case nir_intrinsic_ssbo_atomic_umin
:
6177 op32
= aco_opcode::buffer_atomic_umin
;
6178 op64
= aco_opcode::buffer_atomic_umin_x2
;
6180 case nir_intrinsic_ssbo_atomic_imax
:
6181 op32
= aco_opcode::buffer_atomic_smax
;
6182 op64
= aco_opcode::buffer_atomic_smax_x2
;
6184 case nir_intrinsic_ssbo_atomic_umax
:
6185 op32
= aco_opcode::buffer_atomic_umax
;
6186 op64
= aco_opcode::buffer_atomic_umax_x2
;
6188 case nir_intrinsic_ssbo_atomic_and
:
6189 op32
= aco_opcode::buffer_atomic_and
;
6190 op64
= aco_opcode::buffer_atomic_and_x2
;
6192 case nir_intrinsic_ssbo_atomic_or
:
6193 op32
= aco_opcode::buffer_atomic_or
;
6194 op64
= aco_opcode::buffer_atomic_or_x2
;
6196 case nir_intrinsic_ssbo_atomic_xor
:
6197 op32
= aco_opcode::buffer_atomic_xor
;
6198 op64
= aco_opcode::buffer_atomic_xor_x2
;
6200 case nir_intrinsic_ssbo_atomic_exchange
:
6201 op32
= aco_opcode::buffer_atomic_swap
;
6202 op64
= aco_opcode::buffer_atomic_swap_x2
;
6204 case nir_intrinsic_ssbo_atomic_comp_swap
:
6205 op32
= aco_opcode::buffer_atomic_cmpswap
;
6206 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6209 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6211 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6212 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6213 mubuf
->operands
[0] = Operand(rsrc
);
6214 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6215 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6216 mubuf
->operands
[3] = Operand(data
);
6217 if (return_previous
)
6218 mubuf
->definitions
[0] = Definition(dst
);
6220 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6221 mubuf
->glc
= return_previous
;
6222 mubuf
->dlc
= false; /* Not needed for atomics */
6223 mubuf
->disable_wqm
= true;
6224 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6225 ctx
->program
->needs_exact
= true;
6226 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6229 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6231 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6232 Builder
bld(ctx
->program
, ctx
->block
);
6233 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6234 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6237 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6239 Builder
bld(ctx
->program
, ctx
->block
);
6240 unsigned num_components
= instr
->num_components
;
6241 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6243 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6244 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6245 num_components
, component_size
};
6246 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6247 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6248 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6249 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6250 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6251 * it's safe to use SMEM */
6252 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6253 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6254 emit_global_load(ctx
, bld
, &info
);
6256 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6257 emit_smem_load(ctx
, bld
, &info
);
6261 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6263 Builder
bld(ctx
->program
, ctx
->block
);
6264 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6265 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6267 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6268 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6269 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6270 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6272 if (ctx
->options
->chip_class
>= GFX7
)
6273 addr
= as_vgpr(ctx
, addr
);
6275 unsigned write_count
= 0;
6276 Temp write_datas
[32];
6277 unsigned offsets
[32];
6278 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6279 16, &write_count
, write_datas
, offsets
);
6281 for (unsigned i
= 0; i
< write_count
; i
++) {
6282 if (ctx
->options
->chip_class
>= GFX7
) {
6283 unsigned offset
= offsets
[i
];
6284 Temp store_addr
= addr
;
6285 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6286 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6287 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6288 Temp carry
= bld
.tmp(bld
.lm
);
6289 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6291 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6292 Operand(offset
), addr0
);
6293 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6295 carry
).def(1).setHint(vcc
);
6297 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6302 bool global
= ctx
->options
->chip_class
>= GFX9
;
6304 switch (write_datas
[i
].bytes()) {
6306 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6309 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6312 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6315 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6318 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6321 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6324 unreachable("store_global not implemented for this size.");
6327 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6328 flat
->operands
[0] = Operand(store_addr
);
6329 flat
->operands
[1] = Operand(s1
);
6330 flat
->operands
[2] = Operand(write_datas
[i
]);
6333 flat
->offset
= offset
;
6334 flat
->disable_wqm
= true;
6336 ctx
->program
->needs_exact
= true;
6337 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6339 assert(ctx
->options
->chip_class
== GFX6
);
6341 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6343 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6345 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6346 mubuf
->operands
[0] = Operand(rsrc
);
6347 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6348 mubuf
->operands
[2] = Operand(0u);
6349 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6352 mubuf
->offset
= offsets
[i
];
6353 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6354 mubuf
->disable_wqm
= true;
6356 ctx
->program
->needs_exact
= true;
6357 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6362 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6364 /* return the previous value if dest is ever used */
6365 bool return_previous
= false;
6366 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6367 return_previous
= true;
6370 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6371 return_previous
= true;
6375 Builder
bld(ctx
->program
, ctx
->block
);
6376 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6377 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6379 if (ctx
->options
->chip_class
>= GFX7
)
6380 addr
= as_vgpr(ctx
, addr
);
6382 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6383 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6384 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6386 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6388 aco_opcode op32
, op64
;
6390 if (ctx
->options
->chip_class
>= GFX7
) {
6391 bool global
= ctx
->options
->chip_class
>= GFX9
;
6392 switch (instr
->intrinsic
) {
6393 case nir_intrinsic_global_atomic_add
:
6394 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6395 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6397 case nir_intrinsic_global_atomic_imin
:
6398 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6399 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6401 case nir_intrinsic_global_atomic_umin
:
6402 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6403 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6405 case nir_intrinsic_global_atomic_imax
:
6406 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6407 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6409 case nir_intrinsic_global_atomic_umax
:
6410 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6411 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6413 case nir_intrinsic_global_atomic_and
:
6414 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6415 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6417 case nir_intrinsic_global_atomic_or
:
6418 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6419 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6421 case nir_intrinsic_global_atomic_xor
:
6422 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6423 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6425 case nir_intrinsic_global_atomic_exchange
:
6426 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6427 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6429 case nir_intrinsic_global_atomic_comp_swap
:
6430 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6431 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6434 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6437 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6438 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6439 flat
->operands
[0] = Operand(addr
);
6440 flat
->operands
[1] = Operand(s1
);
6441 flat
->operands
[2] = Operand(data
);
6442 if (return_previous
)
6443 flat
->definitions
[0] = Definition(dst
);
6444 flat
->glc
= return_previous
;
6445 flat
->dlc
= false; /* Not needed for atomics */
6447 flat
->disable_wqm
= true;
6448 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6449 ctx
->program
->needs_exact
= true;
6450 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6452 assert(ctx
->options
->chip_class
== GFX6
);
6454 switch (instr
->intrinsic
) {
6455 case nir_intrinsic_global_atomic_add
:
6456 op32
= aco_opcode::buffer_atomic_add
;
6457 op64
= aco_opcode::buffer_atomic_add_x2
;
6459 case nir_intrinsic_global_atomic_imin
:
6460 op32
= aco_opcode::buffer_atomic_smin
;
6461 op64
= aco_opcode::buffer_atomic_smin_x2
;
6463 case nir_intrinsic_global_atomic_umin
:
6464 op32
= aco_opcode::buffer_atomic_umin
;
6465 op64
= aco_opcode::buffer_atomic_umin_x2
;
6467 case nir_intrinsic_global_atomic_imax
:
6468 op32
= aco_opcode::buffer_atomic_smax
;
6469 op64
= aco_opcode::buffer_atomic_smax_x2
;
6471 case nir_intrinsic_global_atomic_umax
:
6472 op32
= aco_opcode::buffer_atomic_umax
;
6473 op64
= aco_opcode::buffer_atomic_umax_x2
;
6475 case nir_intrinsic_global_atomic_and
:
6476 op32
= aco_opcode::buffer_atomic_and
;
6477 op64
= aco_opcode::buffer_atomic_and_x2
;
6479 case nir_intrinsic_global_atomic_or
:
6480 op32
= aco_opcode::buffer_atomic_or
;
6481 op64
= aco_opcode::buffer_atomic_or_x2
;
6483 case nir_intrinsic_global_atomic_xor
:
6484 op32
= aco_opcode::buffer_atomic_xor
;
6485 op64
= aco_opcode::buffer_atomic_xor_x2
;
6487 case nir_intrinsic_global_atomic_exchange
:
6488 op32
= aco_opcode::buffer_atomic_swap
;
6489 op64
= aco_opcode::buffer_atomic_swap_x2
;
6491 case nir_intrinsic_global_atomic_comp_swap
:
6492 op32
= aco_opcode::buffer_atomic_cmpswap
;
6493 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6496 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6499 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6501 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6503 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6504 mubuf
->operands
[0] = Operand(rsrc
);
6505 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6506 mubuf
->operands
[2] = Operand(0u);
6507 mubuf
->operands
[3] = Operand(data
);
6508 if (return_previous
)
6509 mubuf
->definitions
[0] = Definition(dst
);
6510 mubuf
->glc
= return_previous
;
6513 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6514 mubuf
->disable_wqm
= true;
6515 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6516 ctx
->program
->needs_exact
= true;
6517 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6521 sync_scope
translate_nir_scope(nir_scope scope
)
6524 case NIR_SCOPE_NONE
:
6525 case NIR_SCOPE_INVOCATION
:
6526 return scope_invocation
;
6527 case NIR_SCOPE_SUBGROUP
:
6528 return scope_subgroup
;
6529 case NIR_SCOPE_WORKGROUP
:
6530 return scope_workgroup
;
6531 case NIR_SCOPE_QUEUE_FAMILY
:
6532 return scope_queuefamily
;
6533 case NIR_SCOPE_DEVICE
:
6534 return scope_device
;
6536 unreachable("invalid scope");
6539 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6540 Builder
bld(ctx
->program
, ctx
->block
);
6542 unsigned semantics
= 0;
6543 unsigned storage
= 0;
6544 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6545 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6547 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6548 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6549 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6550 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6551 storage
|= storage_shared
;
6552 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6553 storage
|= storage_shared
;
6555 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6556 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6557 semantics
|= semantic_acquire
| semantic_release
;
6558 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6559 semantics
|= semantic_acquire
| semantic_release
;
6561 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6563 bld
.barrier(aco_opcode::p_barrier
,
6564 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6568 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6570 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6571 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6572 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6573 Builder
bld(ctx
->program
, ctx
->block
);
6575 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6576 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6577 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6580 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6582 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6583 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6584 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6585 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6587 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6588 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6591 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6593 unsigned offset
= nir_intrinsic_base(instr
);
6594 Builder
bld(ctx
->program
, ctx
->block
);
6595 Operand m
= load_lds_size_m0(bld
);
6596 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6597 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6599 unsigned num_operands
= 3;
6600 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6601 switch(instr
->intrinsic
) {
6602 case nir_intrinsic_shared_atomic_add
:
6603 op32
= aco_opcode::ds_add_u32
;
6604 op64
= aco_opcode::ds_add_u64
;
6605 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6606 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6608 case nir_intrinsic_shared_atomic_imin
:
6609 op32
= aco_opcode::ds_min_i32
;
6610 op64
= aco_opcode::ds_min_i64
;
6611 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6612 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6614 case nir_intrinsic_shared_atomic_umin
:
6615 op32
= aco_opcode::ds_min_u32
;
6616 op64
= aco_opcode::ds_min_u64
;
6617 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6618 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6620 case nir_intrinsic_shared_atomic_imax
:
6621 op32
= aco_opcode::ds_max_i32
;
6622 op64
= aco_opcode::ds_max_i64
;
6623 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6624 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6626 case nir_intrinsic_shared_atomic_umax
:
6627 op32
= aco_opcode::ds_max_u32
;
6628 op64
= aco_opcode::ds_max_u64
;
6629 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6630 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6632 case nir_intrinsic_shared_atomic_and
:
6633 op32
= aco_opcode::ds_and_b32
;
6634 op64
= aco_opcode::ds_and_b64
;
6635 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6636 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6638 case nir_intrinsic_shared_atomic_or
:
6639 op32
= aco_opcode::ds_or_b32
;
6640 op64
= aco_opcode::ds_or_b64
;
6641 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6642 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6644 case nir_intrinsic_shared_atomic_xor
:
6645 op32
= aco_opcode::ds_xor_b32
;
6646 op64
= aco_opcode::ds_xor_b64
;
6647 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6648 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6650 case nir_intrinsic_shared_atomic_exchange
:
6651 op32
= aco_opcode::ds_write_b32
;
6652 op64
= aco_opcode::ds_write_b64
;
6653 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6654 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6656 case nir_intrinsic_shared_atomic_comp_swap
:
6657 op32
= aco_opcode::ds_cmpst_b32
;
6658 op64
= aco_opcode::ds_cmpst_b64
;
6659 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6660 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6663 case nir_intrinsic_shared_atomic_fadd
:
6664 op32
= aco_opcode::ds_add_f32
;
6665 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6666 op64
= aco_opcode::num_opcodes
;
6667 op64_rtn
= aco_opcode::num_opcodes
;
6670 unreachable("Unhandled shared atomic intrinsic");
6673 /* return the previous value if dest is ever used */
6674 bool return_previous
= false;
6675 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6676 return_previous
= true;
6679 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6680 return_previous
= true;
6685 if (data
.size() == 1) {
6686 assert(instr
->dest
.ssa
.bit_size
== 32);
6687 op
= return_previous
? op32_rtn
: op32
;
6689 assert(instr
->dest
.ssa
.bit_size
== 64);
6690 op
= return_previous
? op64_rtn
: op64
;
6693 if (offset
> 65535) {
6694 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6698 aco_ptr
<DS_instruction
> ds
;
6699 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6700 ds
->operands
[0] = Operand(address
);
6701 ds
->operands
[1] = Operand(data
);
6702 if (num_operands
== 4)
6703 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6704 ds
->operands
[num_operands
- 1] = m
;
6705 ds
->offset0
= offset
;
6706 if (return_previous
)
6707 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6708 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6709 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6712 Temp
get_scratch_resource(isel_context
*ctx
)
6714 Builder
bld(ctx
->program
, ctx
->block
);
6715 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6716 if (ctx
->stage
!= compute_cs
)
6717 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6719 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6720 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6722 if (ctx
->program
->chip_class
>= GFX10
) {
6723 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6724 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6725 S_008F0C_RESOURCE_LEVEL(1);
6726 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6727 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6728 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6731 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6732 if (ctx
->program
->chip_class
<= GFX8
)
6733 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6735 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6738 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6739 Builder
bld(ctx
->program
, ctx
->block
);
6740 Temp rsrc
= get_scratch_resource(ctx
);
6741 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6742 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6744 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6745 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6746 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6747 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6748 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6749 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6750 info
.soffset
= ctx
->program
->scratch_offset
;
6751 emit_scratch_load(ctx
, bld
, &info
);
6754 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6755 Builder
bld(ctx
->program
, ctx
->block
);
6756 Temp rsrc
= get_scratch_resource(ctx
);
6757 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6758 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6760 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6761 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6763 unsigned write_count
= 0;
6764 Temp write_datas
[32];
6765 unsigned offsets
[32];
6766 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6767 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6768 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6770 for (unsigned i
= 0; i
< write_count
; i
++) {
6771 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6772 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6773 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6777 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6778 uint8_t log2_ps_iter_samples
;
6779 if (ctx
->program
->info
->ps
.force_persample
) {
6780 log2_ps_iter_samples
=
6781 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6783 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6786 /* The bit pattern matches that used by fixed function fragment
6788 static const unsigned ps_iter_masks
[] = {
6789 0xffff, /* not used */
6795 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6797 Builder
bld(ctx
->program
, ctx
->block
);
6799 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6800 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6801 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6802 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6803 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6804 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6807 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6808 Builder
bld(ctx
->program
, ctx
->block
);
6810 unsigned stream
= nir_intrinsic_stream_id(instr
);
6811 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6812 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6813 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6816 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6818 unsigned num_components
=
6819 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6820 assert(num_components
);
6822 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6823 unsigned stream_offset
= 0;
6824 for (unsigned i
= 0; i
< stream
; i
++) {
6825 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6826 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6829 /* Limit on the stride field for <= GFX7. */
6830 assert(stride
< (1 << 14));
6832 Temp gsvs_dwords
[4];
6833 for (unsigned i
= 0; i
< 4; i
++)
6834 gsvs_dwords
[i
] = bld
.tmp(s1
);
6835 bld
.pseudo(aco_opcode::p_split_vector
,
6836 Definition(gsvs_dwords
[0]),
6837 Definition(gsvs_dwords
[1]),
6838 Definition(gsvs_dwords
[2]),
6839 Definition(gsvs_dwords
[3]),
6842 if (stream_offset
) {
6843 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6845 Temp carry
= bld
.tmp(s1
);
6846 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6847 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6850 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6851 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6853 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6854 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6856 unsigned offset
= 0;
6857 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6858 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6861 for (unsigned j
= 0; j
< 4; j
++) {
6862 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6865 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6866 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6867 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6868 if (const_offset
>= 4096u) {
6869 if (vaddr_offset
.isUndefined())
6870 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6872 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6873 const_offset
%= 4096u;
6876 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6877 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6878 mtbuf
->operands
[1] = vaddr_offset
;
6879 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6880 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6881 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6882 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6883 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6884 mtbuf
->offset
= const_offset
;
6887 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
6888 bld
.insert(std::move(mtbuf
));
6891 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6894 /* outputs for the next vertex are undefined and keeping them around can
6895 * create invalid IR with control flow */
6896 ctx
->outputs
.mask
[i
] = 0;
6899 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6902 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6904 Builder
bld(ctx
->program
, ctx
->block
);
6906 if (cluster_size
== 1) {
6908 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6909 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6910 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6911 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6912 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6913 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6914 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6915 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6916 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6917 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6918 //subgroupAnd(val) -> (exec & ~val) == 0
6919 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6920 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6921 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6922 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6923 //subgroupOr(val) -> (val & exec) != 0
6924 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6925 return bool_to_vector_condition(ctx
, tmp
);
6926 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6927 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6928 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6929 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6930 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6931 return bool_to_vector_condition(ctx
, tmp
);
6933 //subgroupClustered{And,Or,Xor}(val, n) ->
6934 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6935 //cluster_offset = ~(n - 1) & lane_id
6936 //cluster_mask = ((1 << n) - 1)
6937 //subgroupClusteredAnd():
6938 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6939 //subgroupClusteredOr():
6940 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6941 //subgroupClusteredXor():
6942 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6943 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6944 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6947 if (op
== nir_op_iand
)
6948 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6950 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6952 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6954 if (ctx
->program
->chip_class
<= GFX7
)
6955 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6956 else if (ctx
->program
->wave_size
== 64)
6957 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6959 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6960 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6961 if (cluster_mask
!= 0xffffffff)
6962 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6964 Definition cmp_def
= Definition();
6965 if (op
== nir_op_iand
) {
6966 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6967 } else if (op
== nir_op_ior
) {
6968 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6969 } else if (op
== nir_op_ixor
) {
6970 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6971 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6972 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6974 cmp_def
.setHint(vcc
);
6975 return cmp_def
.getTemp();
6979 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6981 Builder
bld(ctx
->program
, ctx
->block
);
6983 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6984 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6985 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6987 if (op
== nir_op_iand
)
6988 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6990 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6992 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6993 Temp lo
= lohi
.def(0).getTemp();
6994 Temp hi
= lohi
.def(1).getTemp();
6995 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6997 Definition cmp_def
= Definition();
6998 if (op
== nir_op_iand
)
6999 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7000 else if (op
== nir_op_ior
)
7001 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7002 else if (op
== nir_op_ixor
)
7003 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7004 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7005 cmp_def
.setHint(vcc
);
7006 return cmp_def
.getTemp();
7009 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7011 Builder
bld(ctx
->program
, ctx
->block
);
7013 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7014 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7015 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7016 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7017 if (op
== nir_op_iand
)
7018 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7019 else if (op
== nir_op_ior
)
7020 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7021 else if (op
== nir_op_ixor
)
7022 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7028 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7030 Builder
bld(ctx
->program
, ctx
->block
);
7031 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7032 if (src
.regClass().type() == RegType::vgpr
) {
7033 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7034 } else if (src
.regClass() == s1
) {
7035 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7036 } else if (src
.regClass() == s2
) {
7037 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7039 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7043 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7045 Builder
bld(ctx
->program
, ctx
->block
);
7046 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7047 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7048 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7050 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7051 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7052 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7053 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7056 if (ctx
->program
->chip_class
>= GFX8
) {
7057 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7058 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7059 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7060 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7061 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7062 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7064 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7065 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7066 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7067 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7068 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7069 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7070 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7071 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7072 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7073 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7076 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7077 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7078 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7079 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7080 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7081 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7082 Temp wqm1
= bld
.tmp(v1
);
7083 emit_wqm(ctx
, tmp1
, wqm1
, true);
7084 Temp wqm2
= bld
.tmp(v1
);
7085 emit_wqm(ctx
, tmp2
, wqm2
, true);
7086 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7090 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7092 Builder
bld(ctx
->program
, ctx
->block
);
7093 switch(instr
->intrinsic
) {
7094 case nir_intrinsic_load_barycentric_sample
:
7095 case nir_intrinsic_load_barycentric_pixel
:
7096 case nir_intrinsic_load_barycentric_centroid
: {
7097 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7098 Temp bary
= Temp(0, s2
);
7100 case INTERP_MODE_SMOOTH
:
7101 case INTERP_MODE_NONE
:
7102 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7103 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7104 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7105 bary
= ctx
->persp_centroid
;
7106 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7107 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7109 case INTERP_MODE_NOPERSPECTIVE
:
7110 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7111 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7112 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7113 bary
= ctx
->linear_centroid
;
7114 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7115 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7120 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7121 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7122 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7123 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7124 Operand(p1
), Operand(p2
));
7125 emit_split_vector(ctx
, dst
, 2);
7128 case nir_intrinsic_load_barycentric_model
: {
7129 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7131 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7132 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7133 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7134 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7135 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7136 Operand(p1
), Operand(p2
), Operand(p3
));
7137 emit_split_vector(ctx
, dst
, 3);
7140 case nir_intrinsic_load_barycentric_at_sample
: {
7141 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7142 switch (ctx
->options
->key
.fs
.num_samples
) {
7143 case 2: sample_pos_offset
+= 1 << 3; break;
7144 case 4: sample_pos_offset
+= 3 << 3; break;
7145 case 8: sample_pos_offset
+= 7 << 3; break;
7149 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7150 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7151 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7152 //TODO: bounds checking?
7153 if (addr
.type() == RegType::sgpr
) {
7156 sample_pos_offset
+= const_addr
->u32
<< 3;
7157 offset
= Operand(sample_pos_offset
);
7158 } else if (ctx
->options
->chip_class
>= GFX9
) {
7159 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7161 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7162 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7165 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7166 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7168 } else if (ctx
->options
->chip_class
>= GFX9
) {
7169 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7170 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7171 } else if (ctx
->options
->chip_class
>= GFX7
) {
7172 /* addr += private_segment_buffer + sample_pos_offset */
7173 Temp tmp0
= bld
.tmp(s1
);
7174 Temp tmp1
= bld
.tmp(s1
);
7175 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7176 Definition scc_tmp
= bld
.def(s1
, scc
);
7177 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7178 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7179 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7180 Temp pck0
= bld
.tmp(v1
);
7181 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7182 tmp1
= as_vgpr(ctx
, tmp1
);
7183 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7184 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7186 /* sample_pos = flat_load_dwordx2 addr */
7187 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7189 assert(ctx
->options
->chip_class
== GFX6
);
7191 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7192 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7193 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7195 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7196 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7198 sample_pos
= bld
.tmp(v2
);
7200 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7201 load
->definitions
[0] = Definition(sample_pos
);
7202 load
->operands
[0] = Operand(rsrc
);
7203 load
->operands
[1] = Operand(addr
);
7204 load
->operands
[2] = Operand(0u);
7205 load
->offset
= sample_pos_offset
;
7207 load
->addr64
= true;
7210 load
->disable_wqm
= false;
7211 ctx
->block
->instructions
.emplace_back(std::move(load
));
7214 /* sample_pos -= 0.5 */
7215 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7216 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7217 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7218 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7219 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7221 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7224 case nir_intrinsic_load_barycentric_at_offset
: {
7225 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7226 RegClass rc
= RegClass(offset
.type(), 1);
7227 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7228 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7229 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7232 case nir_intrinsic_load_front_face
: {
7233 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7234 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7237 case nir_intrinsic_load_view_index
: {
7238 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7239 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7240 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7246 case nir_intrinsic_load_layer_id
: {
7247 unsigned idx
= nir_intrinsic_base(instr
);
7248 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7249 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7252 case nir_intrinsic_load_frag_coord
: {
7253 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7256 case nir_intrinsic_load_sample_pos
: {
7257 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7258 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7259 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7260 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7261 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7264 case nir_intrinsic_load_tess_coord
:
7265 visit_load_tess_coord(ctx
, instr
);
7267 case nir_intrinsic_load_interpolated_input
:
7268 visit_load_interpolated_input(ctx
, instr
);
7270 case nir_intrinsic_store_output
:
7271 visit_store_output(ctx
, instr
);
7273 case nir_intrinsic_load_input
:
7274 case nir_intrinsic_load_input_vertex
:
7275 visit_load_input(ctx
, instr
);
7277 case nir_intrinsic_load_output
:
7278 visit_load_output(ctx
, instr
);
7280 case nir_intrinsic_load_per_vertex_input
:
7281 visit_load_per_vertex_input(ctx
, instr
);
7283 case nir_intrinsic_load_per_vertex_output
:
7284 visit_load_per_vertex_output(ctx
, instr
);
7286 case nir_intrinsic_store_per_vertex_output
:
7287 visit_store_per_vertex_output(ctx
, instr
);
7289 case nir_intrinsic_load_ubo
:
7290 visit_load_ubo(ctx
, instr
);
7292 case nir_intrinsic_load_push_constant
:
7293 visit_load_push_constant(ctx
, instr
);
7295 case nir_intrinsic_load_constant
:
7296 visit_load_constant(ctx
, instr
);
7298 case nir_intrinsic_vulkan_resource_index
:
7299 visit_load_resource(ctx
, instr
);
7301 case nir_intrinsic_discard
:
7302 visit_discard(ctx
, instr
);
7304 case nir_intrinsic_discard_if
:
7305 visit_discard_if(ctx
, instr
);
7307 case nir_intrinsic_load_shared
:
7308 visit_load_shared(ctx
, instr
);
7310 case nir_intrinsic_store_shared
:
7311 visit_store_shared(ctx
, instr
);
7313 case nir_intrinsic_shared_atomic_add
:
7314 case nir_intrinsic_shared_atomic_imin
:
7315 case nir_intrinsic_shared_atomic_umin
:
7316 case nir_intrinsic_shared_atomic_imax
:
7317 case nir_intrinsic_shared_atomic_umax
:
7318 case nir_intrinsic_shared_atomic_and
:
7319 case nir_intrinsic_shared_atomic_or
:
7320 case nir_intrinsic_shared_atomic_xor
:
7321 case nir_intrinsic_shared_atomic_exchange
:
7322 case nir_intrinsic_shared_atomic_comp_swap
:
7323 case nir_intrinsic_shared_atomic_fadd
:
7324 visit_shared_atomic(ctx
, instr
);
7326 case nir_intrinsic_image_deref_load
:
7327 visit_image_load(ctx
, instr
);
7329 case nir_intrinsic_image_deref_store
:
7330 visit_image_store(ctx
, instr
);
7332 case nir_intrinsic_image_deref_atomic_add
:
7333 case nir_intrinsic_image_deref_atomic_umin
:
7334 case nir_intrinsic_image_deref_atomic_imin
:
7335 case nir_intrinsic_image_deref_atomic_umax
:
7336 case nir_intrinsic_image_deref_atomic_imax
:
7337 case nir_intrinsic_image_deref_atomic_and
:
7338 case nir_intrinsic_image_deref_atomic_or
:
7339 case nir_intrinsic_image_deref_atomic_xor
:
7340 case nir_intrinsic_image_deref_atomic_exchange
:
7341 case nir_intrinsic_image_deref_atomic_comp_swap
:
7342 visit_image_atomic(ctx
, instr
);
7344 case nir_intrinsic_image_deref_size
:
7345 visit_image_size(ctx
, instr
);
7347 case nir_intrinsic_load_ssbo
:
7348 visit_load_ssbo(ctx
, instr
);
7350 case nir_intrinsic_store_ssbo
:
7351 visit_store_ssbo(ctx
, instr
);
7353 case nir_intrinsic_load_global
:
7354 visit_load_global(ctx
, instr
);
7356 case nir_intrinsic_store_global
:
7357 visit_store_global(ctx
, instr
);
7359 case nir_intrinsic_global_atomic_add
:
7360 case nir_intrinsic_global_atomic_imin
:
7361 case nir_intrinsic_global_atomic_umin
:
7362 case nir_intrinsic_global_atomic_imax
:
7363 case nir_intrinsic_global_atomic_umax
:
7364 case nir_intrinsic_global_atomic_and
:
7365 case nir_intrinsic_global_atomic_or
:
7366 case nir_intrinsic_global_atomic_xor
:
7367 case nir_intrinsic_global_atomic_exchange
:
7368 case nir_intrinsic_global_atomic_comp_swap
:
7369 visit_global_atomic(ctx
, instr
);
7371 case nir_intrinsic_ssbo_atomic_add
:
7372 case nir_intrinsic_ssbo_atomic_imin
:
7373 case nir_intrinsic_ssbo_atomic_umin
:
7374 case nir_intrinsic_ssbo_atomic_imax
:
7375 case nir_intrinsic_ssbo_atomic_umax
:
7376 case nir_intrinsic_ssbo_atomic_and
:
7377 case nir_intrinsic_ssbo_atomic_or
:
7378 case nir_intrinsic_ssbo_atomic_xor
:
7379 case nir_intrinsic_ssbo_atomic_exchange
:
7380 case nir_intrinsic_ssbo_atomic_comp_swap
:
7381 visit_atomic_ssbo(ctx
, instr
);
7383 case nir_intrinsic_load_scratch
:
7384 visit_load_scratch(ctx
, instr
);
7386 case nir_intrinsic_store_scratch
:
7387 visit_store_scratch(ctx
, instr
);
7389 case nir_intrinsic_get_buffer_size
:
7390 visit_get_buffer_size(ctx
, instr
);
7392 case nir_intrinsic_scoped_barrier
:
7393 emit_scoped_barrier(ctx
, instr
);
7395 case nir_intrinsic_load_num_work_groups
: {
7396 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7397 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7398 emit_split_vector(ctx
, dst
, 3);
7401 case nir_intrinsic_load_local_invocation_id
: {
7402 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7403 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7404 emit_split_vector(ctx
, dst
, 3);
7407 case nir_intrinsic_load_work_group_id
: {
7408 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7409 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7410 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7411 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7412 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7413 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7414 emit_split_vector(ctx
, dst
, 3);
7417 case nir_intrinsic_load_local_invocation_index
: {
7418 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7420 /* The tg_size bits [6:11] contain the subgroup id,
7421 * we need this multiplied by the wave size, and then OR the thread id to it.
7423 if (ctx
->program
->wave_size
== 64) {
7424 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7425 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7426 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7427 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7429 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7430 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7431 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7432 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7436 case nir_intrinsic_load_subgroup_id
: {
7437 if (ctx
->stage
== compute_cs
) {
7438 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7439 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7441 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7445 case nir_intrinsic_load_subgroup_invocation
: {
7446 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7449 case nir_intrinsic_load_num_subgroups
: {
7450 if (ctx
->stage
== compute_cs
)
7451 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7452 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7454 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7457 case nir_intrinsic_ballot
: {
7458 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7459 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7460 Definition tmp
= bld
.def(dst
.regClass());
7461 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7462 if (instr
->src
[0].ssa
->bit_size
== 1) {
7463 assert(src
.regClass() == bld
.lm
);
7464 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7465 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7466 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7467 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7468 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7470 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7472 if (dst
.size() != bld
.lm
.size()) {
7473 /* Wave32 with ballot size set to 64 */
7474 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7476 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7479 case nir_intrinsic_shuffle
:
7480 case nir_intrinsic_read_invocation
: {
7481 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7482 if (!nir_src_is_divergent(instr
->src
[0])) {
7483 emit_uniform_subgroup(ctx
, instr
, src
);
7485 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7486 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7487 tid
= bld
.as_uniform(tid
);
7488 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7489 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7490 Temp tmp
= bld
.tmp(v1
);
7491 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7492 if (dst
.type() == RegType::vgpr
)
7493 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7495 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7496 } else if (src
.regClass() == v1
) {
7497 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7498 } else if (src
.regClass() == v2
) {
7499 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7500 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7501 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7502 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7503 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7504 emit_split_vector(ctx
, dst
, 2);
7505 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7506 assert(src
.regClass() == bld
.lm
);
7507 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7508 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7509 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7510 assert(src
.regClass() == bld
.lm
);
7512 if (ctx
->program
->chip_class
<= GFX7
)
7513 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7514 else if (ctx
->program
->wave_size
== 64)
7515 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7517 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7518 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7519 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7520 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7522 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7527 case nir_intrinsic_load_sample_id
: {
7528 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7529 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7532 case nir_intrinsic_load_sample_mask_in
: {
7533 visit_load_sample_mask_in(ctx
, instr
);
7536 case nir_intrinsic_read_first_invocation
: {
7537 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7538 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7539 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7541 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7543 } else if (src
.regClass() == v2
) {
7544 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7545 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7546 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7547 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7548 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7549 emit_split_vector(ctx
, dst
, 2);
7550 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7551 assert(src
.regClass() == bld
.lm
);
7552 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7553 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7554 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7555 } else if (src
.regClass() == s1
) {
7556 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7557 } else if (src
.regClass() == s2
) {
7558 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7560 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7564 case nir_intrinsic_vote_all
: {
7565 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7566 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7567 assert(src
.regClass() == bld
.lm
);
7568 assert(dst
.regClass() == bld
.lm
);
7570 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7571 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7572 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7575 case nir_intrinsic_vote_any
: {
7576 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7577 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7578 assert(src
.regClass() == bld
.lm
);
7579 assert(dst
.regClass() == bld
.lm
);
7581 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7582 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7585 case nir_intrinsic_reduce
:
7586 case nir_intrinsic_inclusive_scan
:
7587 case nir_intrinsic_exclusive_scan
: {
7588 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7589 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7590 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7591 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7592 nir_intrinsic_cluster_size(instr
) : 0;
7593 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7595 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7596 emit_uniform_subgroup(ctx
, instr
, src
);
7597 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7598 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7600 else if (op
== nir_op_iadd
)
7602 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7604 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7606 switch (instr
->intrinsic
) {
7607 case nir_intrinsic_reduce
:
7608 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7610 case nir_intrinsic_exclusive_scan
:
7611 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7613 case nir_intrinsic_inclusive_scan
:
7614 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7619 } else if (cluster_size
== 1) {
7620 bld
.copy(Definition(dst
), src
);
7622 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7624 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7628 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7629 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7644 unreachable("unknown reduction op");
7650 switch (instr
->intrinsic
) {
7651 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7652 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7653 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7655 unreachable("unknown reduce intrinsic");
7658 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7659 reduce
->operands
[0] = Operand(src
);
7660 // filled in by aco_reduce_assign.cpp, used internally as part of the
7662 assert(dst
.size() == 1 || dst
.size() == 2);
7663 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7664 reduce
->operands
[2] = Operand(v1
.as_linear());
7666 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7667 reduce
->definitions
[0] = Definition(tmp_dst
);
7668 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7669 reduce
->definitions
[2] = Definition();
7670 reduce
->definitions
[3] = Definition(scc
, s1
);
7671 reduce
->definitions
[4] = Definition();
7672 reduce
->reduce_op
= reduce_op
;
7673 reduce
->cluster_size
= cluster_size
;
7674 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7676 emit_wqm(ctx
, tmp_dst
, dst
);
7680 case nir_intrinsic_quad_broadcast
: {
7681 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7682 if (!nir_dest_is_divergent(instr
->dest
)) {
7683 emit_uniform_subgroup(ctx
, instr
, src
);
7685 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7686 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7687 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7689 if (instr
->dest
.ssa
.bit_size
== 1) {
7690 assert(src
.regClass() == bld
.lm
);
7691 assert(dst
.regClass() == bld
.lm
);
7692 uint32_t half_mask
= 0x11111111u
<< lane
;
7693 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7694 Temp tmp
= bld
.tmp(bld
.lm
);
7695 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7696 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7697 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7698 emit_wqm(ctx
, tmp
, dst
);
7699 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7700 Temp tmp
= bld
.tmp(v1
);
7701 if (ctx
->program
->chip_class
>= GFX8
)
7702 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7704 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7705 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7706 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7707 Temp tmp
= bld
.tmp(v1
);
7708 if (ctx
->program
->chip_class
>= GFX8
)
7709 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7711 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7712 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7713 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7714 if (ctx
->program
->chip_class
>= GFX8
)
7715 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7717 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7718 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7719 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7720 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7721 if (ctx
->program
->chip_class
>= GFX8
) {
7722 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7723 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7725 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7726 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7728 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7729 emit_split_vector(ctx
, dst
, 2);
7731 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7736 case nir_intrinsic_quad_swap_horizontal
:
7737 case nir_intrinsic_quad_swap_vertical
:
7738 case nir_intrinsic_quad_swap_diagonal
:
7739 case nir_intrinsic_quad_swizzle_amd
: {
7740 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7741 if (!nir_dest_is_divergent(instr
->dest
)) {
7742 emit_uniform_subgroup(ctx
, instr
, src
);
7745 uint16_t dpp_ctrl
= 0;
7746 switch (instr
->intrinsic
) {
7747 case nir_intrinsic_quad_swap_horizontal
:
7748 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7750 case nir_intrinsic_quad_swap_vertical
:
7751 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7753 case nir_intrinsic_quad_swap_diagonal
:
7754 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7756 case nir_intrinsic_quad_swizzle_amd
:
7757 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7762 if (ctx
->program
->chip_class
< GFX8
)
7763 dpp_ctrl
|= (1 << 15);
7765 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7766 if (instr
->dest
.ssa
.bit_size
== 1) {
7767 assert(src
.regClass() == bld
.lm
);
7768 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7769 if (ctx
->program
->chip_class
>= GFX8
)
7770 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7772 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7773 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7774 emit_wqm(ctx
, tmp
, dst
);
7775 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7776 Temp tmp
= bld
.tmp(v1
);
7777 if (ctx
->program
->chip_class
>= GFX8
)
7778 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7780 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7781 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7782 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7783 Temp tmp
= bld
.tmp(v1
);
7784 if (ctx
->program
->chip_class
>= GFX8
)
7785 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7787 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7788 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7789 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7791 if (ctx
->program
->chip_class
>= GFX8
)
7792 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7794 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7795 emit_wqm(ctx
, tmp
, dst
);
7796 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7797 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7798 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7799 if (ctx
->program
->chip_class
>= GFX8
) {
7800 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7801 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7803 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7804 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7806 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7807 emit_split_vector(ctx
, dst
, 2);
7809 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7813 case nir_intrinsic_masked_swizzle_amd
: {
7814 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7815 if (!nir_dest_is_divergent(instr
->dest
)) {
7816 emit_uniform_subgroup(ctx
, instr
, src
);
7819 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7820 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7821 if (instr
->dest
.ssa
.bit_size
== 1) {
7822 assert(src
.regClass() == bld
.lm
);
7823 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7824 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7825 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7826 emit_wqm(ctx
, tmp
, dst
);
7827 } else if (dst
.regClass() == v1b
) {
7828 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7829 emit_extract_vector(ctx
, tmp
, 0, dst
);
7830 } else if (dst
.regClass() == v2b
) {
7831 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7832 emit_extract_vector(ctx
, tmp
, 0, dst
);
7833 } else if (dst
.regClass() == v1
) {
7834 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7835 } else if (dst
.regClass() == v2
) {
7836 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7837 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7838 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7839 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7840 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7841 emit_split_vector(ctx
, dst
, 2);
7843 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7847 case nir_intrinsic_write_invocation_amd
: {
7848 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7849 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7850 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7851 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7852 if (dst
.regClass() == v1
) {
7853 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7854 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7855 } else if (dst
.regClass() == v2
) {
7856 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7857 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7858 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7859 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7860 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7861 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7862 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7863 emit_split_vector(ctx
, dst
, 2);
7865 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7869 case nir_intrinsic_mbcnt_amd
: {
7870 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7871 RegClass rc
= RegClass(src
.type(), 1);
7872 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7873 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7874 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7875 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7876 emit_wqm(ctx
, wqm_tmp
, dst
);
7879 case nir_intrinsic_load_helper_invocation
: {
7880 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7881 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7882 ctx
->block
->kind
|= block_kind_needs_lowering
;
7883 ctx
->program
->needs_exact
= true;
7886 case nir_intrinsic_is_helper_invocation
: {
7887 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7888 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7889 ctx
->block
->kind
|= block_kind_needs_lowering
;
7890 ctx
->program
->needs_exact
= true;
7893 case nir_intrinsic_demote
:
7894 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7896 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7897 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7898 ctx
->block
->kind
|= block_kind_uses_demote
;
7899 ctx
->program
->needs_exact
= true;
7901 case nir_intrinsic_demote_if
: {
7902 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7903 assert(src
.regClass() == bld
.lm
);
7904 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7905 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7907 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7908 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7909 ctx
->block
->kind
|= block_kind_uses_demote
;
7910 ctx
->program
->needs_exact
= true;
7913 case nir_intrinsic_first_invocation
: {
7914 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7915 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7918 case nir_intrinsic_shader_clock
: {
7919 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7920 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
7921 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
7922 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
7923 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
7926 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7927 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7928 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
7930 emit_split_vector(ctx
, dst
, 2);
7933 case nir_intrinsic_load_vertex_id_zero_base
: {
7934 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7935 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7938 case nir_intrinsic_load_first_vertex
: {
7939 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7940 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7943 case nir_intrinsic_load_base_instance
: {
7944 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7945 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7948 case nir_intrinsic_load_instance_id
: {
7949 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7950 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7953 case nir_intrinsic_load_draw_id
: {
7954 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7955 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7958 case nir_intrinsic_load_invocation_id
: {
7959 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7961 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7962 if (ctx
->options
->chip_class
>= GFX10
)
7963 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7965 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7966 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7967 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7968 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7970 unreachable("Unsupported stage for load_invocation_id");
7975 case nir_intrinsic_load_primitive_id
: {
7976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7978 switch (ctx
->shader
->info
.stage
) {
7979 case MESA_SHADER_GEOMETRY
:
7980 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7982 case MESA_SHADER_TESS_CTRL
:
7983 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7985 case MESA_SHADER_TESS_EVAL
:
7986 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7989 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7994 case nir_intrinsic_load_patch_vertices_in
: {
7995 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7996 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7998 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7999 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8002 case nir_intrinsic_emit_vertex_with_counter
: {
8003 visit_emit_vertex_with_counter(ctx
, instr
);
8006 case nir_intrinsic_end_primitive_with_counter
: {
8007 unsigned stream
= nir_intrinsic_stream_id(instr
);
8008 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8011 case nir_intrinsic_set_vertex_count
: {
8012 /* unused, the HW keeps track of this for us */
8016 isel_err(&instr
->instr
, "Unimplemented intrinsic instr");
8024 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8025 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8026 enum glsl_base_type
*stype
)
8028 nir_deref_instr
*texture_deref_instr
= NULL
;
8029 nir_deref_instr
*sampler_deref_instr
= NULL
;
8032 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8033 switch (instr
->src
[i
].src_type
) {
8034 case nir_tex_src_texture_deref
:
8035 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8037 case nir_tex_src_sampler_deref
:
8038 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8040 case nir_tex_src_plane
:
8041 plane
= nir_src_as_int(instr
->src
[i
].src
);
8048 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8050 if (!sampler_deref_instr
)
8051 sampler_deref_instr
= texture_deref_instr
;
8054 assert(instr
->op
!= nir_texop_txf_ms
&&
8055 instr
->op
!= nir_texop_samples_identical
);
8056 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8057 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8058 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8059 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8060 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8061 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8063 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8066 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8068 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8069 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8070 Builder
bld(ctx
->program
, ctx
->block
);
8072 /* to avoid unnecessary moves, we split and recombine sampler and image */
8073 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8074 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8075 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8077 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8078 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8079 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8080 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8082 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8083 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8084 img
[0], img
[1], img
[2], img
[3],
8085 img
[4], img
[5], img
[6], img
[7]);
8086 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8087 samp
[0], samp
[1], samp
[2], samp
[3]);
8090 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8091 instr
->op
== nir_texop_samples_identical
))
8092 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8095 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8096 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8098 Builder
bld(ctx
->program
, ctx
->block
);
8100 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8101 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8102 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8104 Operand
neg_one(0xbf800000u
);
8105 Operand
one(0x3f800000u
);
8106 Operand
two(0x40000000u
);
8107 Operand
four(0x40800000u
);
8109 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8110 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8111 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8113 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8114 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8115 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8116 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8119 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8120 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8121 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8123 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8126 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8127 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8128 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8131 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8132 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8134 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8135 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8138 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8140 Builder
bld(ctx
->program
, ctx
->block
);
8141 Temp ma
, tc
, sc
, id
;
8142 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8143 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8146 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8148 // see comment in ac_prepare_cube_coords()
8149 if (ctx
->options
->chip_class
<= GFX8
)
8150 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8153 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8155 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8156 vop3a
->operands
[0] = Operand(ma
);
8157 vop3a
->abs
[0] = true;
8158 Temp invma
= bld
.tmp(v1
);
8159 vop3a
->definitions
[0] = Definition(invma
);
8160 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8162 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8164 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8166 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8168 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8170 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8173 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8174 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8176 for (unsigned i
= 0; i
< 2; i
++) {
8177 // see comment in ac_prepare_cube_coords()
8179 Temp deriv_sc
, deriv_tc
;
8180 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8181 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8183 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8185 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8186 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8187 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8188 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8189 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8190 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8191 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8194 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8195 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8199 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8206 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8208 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8210 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8211 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8214 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8215 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8216 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8220 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8222 Builder
bld(ctx
->program
, ctx
->block
);
8223 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8224 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8225 has_clamped_lod
= false;
8226 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8227 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8228 clamped_lod
= Temp();
8229 std::vector
<Temp
> coords
;
8230 std::vector
<Temp
> derivs
;
8231 nir_const_value
*sample_index_cv
= NULL
;
8232 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8233 enum glsl_base_type stype
;
8234 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8236 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8237 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8238 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8239 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8241 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8242 switch (instr
->src
[i
].src_type
) {
8243 case nir_tex_src_coord
: {
8244 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8245 for (unsigned i
= 0; i
< coord
.size(); i
++)
8246 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8249 case nir_tex_src_bias
:
8250 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8253 case nir_tex_src_lod
: {
8254 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8256 if (val
&& val
->f32
<= 0.0) {
8259 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8264 case nir_tex_src_min_lod
:
8265 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8266 has_clamped_lod
= true;
8268 case nir_tex_src_comparator
:
8269 if (instr
->is_shadow
) {
8270 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8274 case nir_tex_src_offset
:
8275 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8276 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8279 case nir_tex_src_ddx
:
8280 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8283 case nir_tex_src_ddy
:
8284 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8287 case nir_tex_src_ms_index
:
8288 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8289 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8290 has_sample_index
= true;
8292 case nir_tex_src_texture_offset
:
8293 case nir_tex_src_sampler_offset
:
8299 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8300 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8302 if (instr
->op
== nir_texop_texture_samples
) {
8303 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8305 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8306 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8307 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8309 Operand default_sample
= Operand(1u);
8310 if (ctx
->options
->robust_buffer_access
) {
8311 /* Extract the second dword of the descriptor, if it's
8312 * all zero, then it's a null descriptor.
8314 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8315 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8316 default_sample
= Operand(is_non_null_descriptor
);
8319 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8320 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8321 samples
, default_sample
, bld
.scc(is_msaa
));
8325 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8326 aco_ptr
<Instruction
> tmp_instr
;
8327 Temp acc
, pack
= Temp();
8329 uint32_t pack_const
= 0;
8330 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8331 if (!const_offset
[i
])
8333 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8336 if (offset
.type() == RegType::sgpr
) {
8337 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8338 if (const_offset
[i
])
8341 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8342 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8345 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8348 if (pack
== Temp()) {
8351 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8355 if (pack_const
&& pack
!= Temp())
8356 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8358 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8359 if (const_offset
[i
])
8362 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8363 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8366 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8369 if (pack
== Temp()) {
8372 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8376 if (pack_const
&& pack
!= Temp())
8377 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8379 if (pack_const
&& pack
== Temp())
8380 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8381 else if (pack
== Temp())
8387 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8388 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8390 /* pack derivatives */
8391 if (has_ddx
|| has_ddy
) {
8392 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8393 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8394 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8395 derivs
= {ddx
, zero
, ddy
, zero
};
8397 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8398 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8399 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8400 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8405 if (instr
->coord_components
> 1 &&
8406 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8408 instr
->op
!= nir_texop_txf
)
8409 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8411 if (instr
->coord_components
> 2 &&
8412 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8413 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8414 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8415 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8417 instr
->op
!= nir_texop_txf
&&
8418 instr
->op
!= nir_texop_txf_ms
&&
8419 instr
->op
!= nir_texop_fragment_fetch
&&
8420 instr
->op
!= nir_texop_fragment_mask_fetch
)
8421 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8423 if (ctx
->options
->chip_class
== GFX9
&&
8424 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8425 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8426 assert(coords
.size() > 0 && coords
.size() < 3);
8428 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8429 Operand((uint32_t) 0) :
8430 Operand((uint32_t) 0x3f000000)));
8433 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8435 if (instr
->op
== nir_texop_samples_identical
)
8436 resource
= fmask_ptr
;
8438 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8439 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8440 instr
->op
!= nir_texop_txs
&&
8441 instr
->op
!= nir_texop_fragment_fetch
&&
8442 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8443 assert(has_sample_index
);
8444 Operand
op(sample_index
);
8445 if (sample_index_cv
)
8446 op
= Operand(sample_index_cv
->u32
);
8447 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8450 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8451 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8452 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8453 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8458 /* Build tex instruction */
8459 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8460 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8461 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8463 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8466 /* gather4 selects the component by dmask and always returns vec4 */
8467 if (instr
->op
== nir_texop_tg4
) {
8468 assert(instr
->dest
.ssa
.num_components
== 4);
8469 if (instr
->is_shadow
)
8472 dmask
= 1 << instr
->component
;
8473 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8474 tmp_dst
= bld
.tmp(v4
);
8475 } else if (instr
->op
== nir_texop_samples_identical
) {
8476 tmp_dst
= bld
.tmp(v1
);
8477 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8478 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8481 aco_ptr
<MIMG_instruction
> tex
;
8482 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8484 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8486 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8487 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8490 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8491 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8493 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8494 tex
->operands
[0] = Operand(resource
);
8495 tex
->operands
[1] = Operand(s4
); /* no sampler */
8496 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8497 if (ctx
->options
->chip_class
== GFX9
&&
8498 instr
->op
== nir_texop_txs
&&
8499 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8501 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8502 } else if (instr
->op
== nir_texop_query_levels
) {
8503 tex
->dmask
= 1 << 3;
8508 tex
->definitions
[0] = Definition(tmp_dst
);
8510 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8513 /* divide 3rd value by 6 by multiplying with magic number */
8514 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8515 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8516 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8517 assert(instr
->dest
.ssa
.num_components
== 3);
8518 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8519 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8520 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8521 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8526 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8530 Temp tg4_compare_cube_wa64
= Temp();
8532 if (tg4_integer_workarounds
) {
8533 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8534 tex
->operands
[0] = Operand(resource
);
8535 tex
->operands
[1] = Operand(s4
); /* no sampler */
8536 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8540 Temp size
= bld
.tmp(v2
);
8541 tex
->definitions
[0] = Definition(size
);
8542 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8543 emit_split_vector(ctx
, size
, size
.size());
8546 for (unsigned i
= 0; i
< 2; i
++) {
8547 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8548 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8549 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8550 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8553 Temp new_coords
[2] = {
8554 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8555 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8558 if (tg4_integer_cube_workaround
) {
8559 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8560 Temp desc
[resource
.size()];
8561 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8562 Format::PSEUDO
, 1, resource
.size())};
8563 split
->operands
[0] = Operand(resource
);
8564 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8565 desc
[i
] = bld
.tmp(s1
);
8566 split
->definitions
[i
] = Definition(desc
[i
]);
8568 ctx
->block
->instructions
.emplace_back(std::move(split
));
8570 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8571 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8572 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8575 if (stype
== GLSL_TYPE_UINT
) {
8576 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8577 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8578 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8579 bld
.scc(compare_cube_wa
));
8581 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8582 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8583 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8584 bld
.scc(compare_cube_wa
));
8586 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8587 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8589 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8591 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8592 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8593 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8595 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8596 Format::PSEUDO
, resource
.size(), 1)};
8597 for (unsigned i
= 0; i
< resource
.size(); i
++)
8598 vec
->operands
[i
] = Operand(desc
[i
]);
8599 resource
= bld
.tmp(resource
.regClass());
8600 vec
->definitions
[0] = Definition(resource
);
8601 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8603 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8604 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8605 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8606 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8608 coords
[0] = new_coords
[0];
8609 coords
[1] = new_coords
[1];
8612 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8613 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8615 assert(coords
.size() == 1);
8616 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8620 op
= aco_opcode::buffer_load_format_x
; break;
8622 op
= aco_opcode::buffer_load_format_xy
; break;
8624 op
= aco_opcode::buffer_load_format_xyz
; break;
8626 op
= aco_opcode::buffer_load_format_xyzw
; break;
8628 unreachable("Tex instruction loads more than 4 components.");
8631 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8632 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8635 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8637 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8638 mubuf
->operands
[0] = Operand(resource
);
8639 mubuf
->operands
[1] = Operand(coords
[0]);
8640 mubuf
->operands
[2] = Operand((uint32_t) 0);
8641 mubuf
->definitions
[0] = Definition(tmp_dst
);
8642 mubuf
->idxen
= true;
8643 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8645 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8649 /* gather MIMG address components */
8650 std::vector
<Temp
> args
;
8652 args
.emplace_back(offset
);
8654 args
.emplace_back(bias
);
8656 args
.emplace_back(compare
);
8658 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8660 args
.insert(args
.end(), coords
.begin(), coords
.end());
8661 if (has_sample_index
)
8662 args
.emplace_back(sample_index
);
8664 args
.emplace_back(lod
);
8665 if (has_clamped_lod
)
8666 args
.emplace_back(clamped_lod
);
8668 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8669 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8670 vec
->definitions
[0] = Definition(arg
);
8671 for (unsigned i
= 0; i
< args
.size(); i
++)
8672 vec
->operands
[i
] = Operand(args
[i
]);
8673 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8676 if (instr
->op
== nir_texop_txf
||
8677 instr
->op
== nir_texop_txf_ms
||
8678 instr
->op
== nir_texop_samples_identical
||
8679 instr
->op
== nir_texop_fragment_fetch
||
8680 instr
->op
== nir_texop_fragment_mask_fetch
) {
8681 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8682 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8683 tex
->operands
[0] = Operand(resource
);
8684 tex
->operands
[1] = Operand(s4
); /* no sampler */
8685 tex
->operands
[2] = Operand(arg
);
8690 tex
->definitions
[0] = Definition(tmp_dst
);
8691 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8693 if (instr
->op
== nir_texop_samples_identical
) {
8694 assert(dmask
== 1 && dst
.regClass() == v1
);
8695 assert(dst
.id() != tmp_dst
.id());
8697 Temp tmp
= bld
.tmp(bld
.lm
);
8698 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8699 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8702 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8707 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8708 aco_opcode opcode
= aco_opcode::image_sample
;
8709 if (has_offset
) { /* image_sample_*_o */
8710 if (has_clamped_lod
) {
8712 opcode
= aco_opcode::image_sample_c_cl_o
;
8714 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8716 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8718 opcode
= aco_opcode::image_sample_cl_o
;
8720 opcode
= aco_opcode::image_sample_d_cl_o
;
8722 opcode
= aco_opcode::image_sample_b_cl_o
;
8724 } else if (has_compare
) {
8725 opcode
= aco_opcode::image_sample_c_o
;
8727 opcode
= aco_opcode::image_sample_c_d_o
;
8729 opcode
= aco_opcode::image_sample_c_b_o
;
8731 opcode
= aco_opcode::image_sample_c_lz_o
;
8733 opcode
= aco_opcode::image_sample_c_l_o
;
8735 opcode
= aco_opcode::image_sample_o
;
8737 opcode
= aco_opcode::image_sample_d_o
;
8739 opcode
= aco_opcode::image_sample_b_o
;
8741 opcode
= aco_opcode::image_sample_lz_o
;
8743 opcode
= aco_opcode::image_sample_l_o
;
8745 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8747 opcode
= aco_opcode::image_sample_c_cl
;
8749 opcode
= aco_opcode::image_sample_c_d_cl
;
8751 opcode
= aco_opcode::image_sample_c_b_cl
;
8753 opcode
= aco_opcode::image_sample_cl
;
8755 opcode
= aco_opcode::image_sample_d_cl
;
8757 opcode
= aco_opcode::image_sample_b_cl
;
8759 } else { /* no offset */
8761 opcode
= aco_opcode::image_sample_c
;
8763 opcode
= aco_opcode::image_sample_c_d
;
8765 opcode
= aco_opcode::image_sample_c_b
;
8767 opcode
= aco_opcode::image_sample_c_lz
;
8769 opcode
= aco_opcode::image_sample_c_l
;
8771 opcode
= aco_opcode::image_sample
;
8773 opcode
= aco_opcode::image_sample_d
;
8775 opcode
= aco_opcode::image_sample_b
;
8777 opcode
= aco_opcode::image_sample_lz
;
8779 opcode
= aco_opcode::image_sample_l
;
8783 if (instr
->op
== nir_texop_tg4
) {
8784 if (has_offset
) { /* image_gather4_*_o */
8786 opcode
= aco_opcode::image_gather4_c_lz_o
;
8788 opcode
= aco_opcode::image_gather4_c_l_o
;
8790 opcode
= aco_opcode::image_gather4_c_b_o
;
8792 opcode
= aco_opcode::image_gather4_lz_o
;
8794 opcode
= aco_opcode::image_gather4_l_o
;
8796 opcode
= aco_opcode::image_gather4_b_o
;
8800 opcode
= aco_opcode::image_gather4_c_lz
;
8802 opcode
= aco_opcode::image_gather4_c_l
;
8804 opcode
= aco_opcode::image_gather4_c_b
;
8806 opcode
= aco_opcode::image_gather4_lz
;
8808 opcode
= aco_opcode::image_gather4_l
;
8810 opcode
= aco_opcode::image_gather4_b
;
8813 } else if (instr
->op
== nir_texop_lod
) {
8814 opcode
= aco_opcode::image_get_lod
;
8817 /* we don't need the bias, sample index, compare value or offset to be
8818 * computed in WQM but if the p_create_vector copies the coordinates, then it
8819 * needs to be in WQM */
8820 if (ctx
->stage
== fragment_fs
&&
8821 !has_derivs
&& !has_lod
&& !level_zero
&&
8822 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8823 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8824 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8826 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8827 tex
->operands
[0] = Operand(resource
);
8828 tex
->operands
[1] = Operand(sampler
);
8829 tex
->operands
[2] = Operand(arg
);
8833 tex
->definitions
[0] = Definition(tmp_dst
);
8834 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8836 if (tg4_integer_cube_workaround
) {
8837 assert(tmp_dst
.id() != dst
.id());
8838 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8840 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8842 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8843 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8845 if (stype
== GLSL_TYPE_UINT
)
8846 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8848 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8849 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8851 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8852 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8853 val
[0], val
[1], val
[2], val
[3]);
8855 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8856 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8861 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8863 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8864 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8866 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8867 if (ctx
->program
->wave_size
== 64)
8868 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8870 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8872 return Operand(tmp
);
8876 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8878 aco_ptr
<Pseudo_instruction
> phi
;
8879 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8880 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8882 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8883 logical
|= ctx
->block
->kind
& block_kind_merge
;
8884 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8886 /* we want a sorted list of sources, since the predecessor list is also sorted */
8887 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8888 nir_foreach_phi_src(src
, instr
)
8889 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8891 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8892 unsigned num_operands
= 0;
8893 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8894 unsigned num_defined
= 0;
8895 unsigned cur_pred_idx
= 0;
8896 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8897 if (cur_pred_idx
< preds
.size()) {
8898 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8899 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8900 unsigned skipped
= 0;
8901 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8903 if (cur_pred_idx
+ skipped
< preds
.size()) {
8904 for (unsigned i
= 0; i
< skipped
; i
++)
8905 operands
[num_operands
++] = Operand(dst
.regClass());
8906 cur_pred_idx
+= skipped
;
8911 /* Handle missing predecessors at the end. This shouldn't happen with loop
8912 * headers and we can't ignore these sources for loop header phis. */
8913 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8916 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
8917 operands
[num_operands
++] = op
;
8918 num_defined
+= !op
.isUndefined();
8920 /* handle block_kind_continue_or_break at loop exit blocks */
8921 while (cur_pred_idx
++ < preds
.size())
8922 operands
[num_operands
++] = Operand(dst
.regClass());
8924 /* If the loop ends with a break, still add a linear continue edge in case
8925 * that break is divergent or continue_or_break is used. We'll either remove
8926 * this operand later in visit_loop() if it's not necessary or replace the
8927 * undef with something correct. */
8928 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8929 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8930 nir_block
*last
= nir_loop_last_block(loop
);
8931 if (last
->successors
[0] != instr
->instr
.block
)
8932 operands
[num_operands
++] = Operand(RegClass());
8935 if (num_defined
== 0) {
8936 Builder
bld(ctx
->program
, ctx
->block
);
8937 if (dst
.regClass() == s1
) {
8938 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8939 } else if (dst
.regClass() == v1
) {
8940 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8942 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8943 for (unsigned i
= 0; i
< dst
.size(); i
++)
8944 vec
->operands
[i
] = Operand(0u);
8945 vec
->definitions
[0] = Definition(dst
);
8946 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8951 /* we can use a linear phi in some cases if one src is undef */
8952 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8953 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8955 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8956 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8957 assert(invert
->kind
& block_kind_invert
);
8959 unsigned then_block
= invert
->linear_preds
[0];
8961 Block
* insert_block
= NULL
;
8962 for (unsigned i
= 0; i
< num_operands
; i
++) {
8963 Operand op
= operands
[i
];
8964 if (op
.isUndefined())
8966 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8967 phi
->operands
[0] = op
;
8970 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8971 phi
->operands
[1] = Operand(dst
.regClass());
8972 phi
->definitions
[0] = Definition(dst
);
8973 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8977 /* try to scalarize vector phis */
8978 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8979 // TODO: scalarize linear phis on divergent ifs
8980 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8981 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8982 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8983 Operand src
= operands
[i
];
8984 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8985 can_scalarize
= false;
8987 if (can_scalarize
) {
8988 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8989 assert(dst
.size() % num_components
== 0);
8990 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8992 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8993 for (unsigned k
= 0; k
< num_components
; k
++) {
8994 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8995 for (unsigned i
= 0; i
< num_operands
; i
++) {
8996 Operand src
= operands
[i
];
8997 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8999 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9000 phi
->definitions
[0] = Definition(phi_dst
);
9001 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9002 new_vec
[k
] = phi_dst
;
9003 vec
->operands
[k
] = Operand(phi_dst
);
9005 vec
->definitions
[0] = Definition(dst
);
9006 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9007 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9012 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9013 for (unsigned i
= 0; i
< num_operands
; i
++)
9014 phi
->operands
[i
] = operands
[i
];
9015 phi
->definitions
[0] = Definition(dst
);
9016 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9020 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9022 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9024 assert(dst
.type() == RegType::sgpr
);
9026 if (dst
.size() == 1) {
9027 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9029 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9030 for (unsigned i
= 0; i
< dst
.size(); i
++)
9031 vec
->operands
[i
] = Operand(0u);
9032 vec
->definitions
[0] = Definition(dst
);
9033 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9037 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9039 Builder
bld(ctx
->program
, ctx
->block
);
9040 Block
*logical_target
;
9041 append_logical_end(ctx
->block
);
9042 unsigned idx
= ctx
->block
->index
;
9044 switch (instr
->type
) {
9045 case nir_jump_break
:
9046 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9047 add_logical_edge(idx
, logical_target
);
9048 ctx
->block
->kind
|= block_kind_break
;
9050 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9051 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9052 /* uniform break - directly jump out of the loop */
9053 ctx
->block
->kind
|= block_kind_uniform
;
9054 ctx
->cf_info
.has_branch
= true;
9055 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9056 add_linear_edge(idx
, logical_target
);
9059 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9060 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9062 case nir_jump_continue
:
9063 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9064 add_logical_edge(idx
, logical_target
);
9065 ctx
->block
->kind
|= block_kind_continue
;
9067 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9068 /* for potential uniform breaks after this continue,
9069 we must ensure that they are handled correctly */
9070 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9071 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9072 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9074 /* uniform continue - directly jump to the loop header */
9075 ctx
->block
->kind
|= block_kind_uniform
;
9076 ctx
->cf_info
.has_branch
= true;
9077 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9078 add_linear_edge(idx
, logical_target
);
9083 isel_err(&instr
->instr
, "Unknown NIR jump instr");
9087 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9088 ctx
->cf_info
.exec_potentially_empty_break
= true;
9089 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9092 /* remove critical edges from linear CFG */
9093 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9094 Block
* break_block
= ctx
->program
->create_and_insert_block();
9095 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9096 break_block
->kind
|= block_kind_uniform
;
9097 add_linear_edge(idx
, break_block
);
9098 /* the loop_header pointer might be invalidated by this point */
9099 if (instr
->type
== nir_jump_continue
)
9100 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9101 add_linear_edge(break_block
->index
, logical_target
);
9102 bld
.reset(break_block
);
9103 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9105 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9106 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9107 add_linear_edge(idx
, continue_block
);
9108 append_logical_start(continue_block
);
9109 ctx
->block
= continue_block
;
9113 void visit_block(isel_context
*ctx
, nir_block
*block
)
9115 nir_foreach_instr(instr
, block
) {
9116 switch (instr
->type
) {
9117 case nir_instr_type_alu
:
9118 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9120 case nir_instr_type_load_const
:
9121 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9123 case nir_instr_type_intrinsic
:
9124 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9126 case nir_instr_type_tex
:
9127 visit_tex(ctx
, nir_instr_as_tex(instr
));
9129 case nir_instr_type_phi
:
9130 visit_phi(ctx
, nir_instr_as_phi(instr
));
9132 case nir_instr_type_ssa_undef
:
9133 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9135 case nir_instr_type_deref
:
9137 case nir_instr_type_jump
:
9138 visit_jump(ctx
, nir_instr_as_jump(instr
));
9141 isel_err(instr
, "Unknown NIR instr type");
9146 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9147 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9152 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9153 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9155 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9156 RegClass rc
= vals
[0].regClass();
9158 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9160 unsigned next_pred
= 1;
9162 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9163 Block
& block
= ctx
->program
->blocks
[idx
];
9164 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9165 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9169 if (block
.kind
& block_kind_continue
) {
9170 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9175 bool all_same
= true;
9176 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9177 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9181 val
= vals
[block
.linear_preds
[0] - first
];
9183 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9184 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9185 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9186 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9187 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9188 phi
->definitions
[0] = Definition(val
.getTemp());
9189 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9191 vals
[idx
- first
] = val
;
9194 return vals
[last
- first
];
9197 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9199 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9200 append_logical_end(ctx
->block
);
9201 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9202 Builder
bld(ctx
->program
, ctx
->block
);
9203 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9204 unsigned loop_preheader_idx
= ctx
->block
->index
;
9206 Block loop_exit
= Block();
9207 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9208 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9210 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9211 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9212 loop_header
->kind
|= block_kind_loop_header
;
9213 add_edge(loop_preheader_idx
, loop_header
);
9214 ctx
->block
= loop_header
;
9216 /* emit loop body */
9217 unsigned loop_header_idx
= loop_header
->index
;
9218 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9219 append_logical_start(ctx
->block
);
9220 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9222 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9223 if (!ctx
->cf_info
.has_branch
) {
9224 append_logical_end(ctx
->block
);
9225 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9226 /* Discards can result in code running with an empty exec mask.
9227 * This would result in divergent breaks not ever being taken. As a
9228 * workaround, break the loop when the loop mask is empty instead of
9229 * always continuing. */
9230 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9231 unsigned block_idx
= ctx
->block
->index
;
9233 /* create helper blocks to avoid critical edges */
9234 Block
*break_block
= ctx
->program
->create_and_insert_block();
9235 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9236 break_block
->kind
= block_kind_uniform
;
9237 bld
.reset(break_block
);
9238 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9239 add_linear_edge(block_idx
, break_block
);
9240 add_linear_edge(break_block
->index
, &loop_exit
);
9242 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9243 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9244 continue_block
->kind
= block_kind_uniform
;
9245 bld
.reset(continue_block
);
9246 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9247 add_linear_edge(block_idx
, continue_block
);
9248 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9250 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9251 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9252 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9254 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9255 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9256 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9258 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9261 bld
.reset(ctx
->block
);
9262 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9265 /* Fixup phis in loop header from unreachable blocks.
9266 * has_branch/has_divergent_branch also indicates if the loop ends with a
9267 * break/continue instruction, but we don't emit those if unreachable=true */
9269 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9270 bool linear
= ctx
->cf_info
.has_branch
;
9271 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9272 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9273 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9274 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9275 /* the last operand should be the one that needs to be removed */
9276 instr
->operands
.pop_back();
9277 } else if (!is_phi(instr
)) {
9283 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9284 * and the previous one shouldn't both happen at once because a break in the
9285 * merge block would get CSE'd */
9286 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9287 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9288 Operand vals
[num_vals
];
9289 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9290 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9291 if (ctx
->cf_info
.has_branch
)
9292 instr
->operands
.pop_back();
9294 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9295 } else if (!is_phi(instr
)) {
9301 ctx
->cf_info
.has_branch
= false;
9303 // TODO: if the loop has not a single exit, we must add one °°
9304 /* emit loop successor block */
9305 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9306 append_logical_start(ctx
->block
);
9309 // TODO: check if it is beneficial to not branch on continues
9310 /* trim linear phis in loop header */
9311 for (auto&& instr
: loop_entry
->instructions
) {
9312 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9313 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9314 new_phi
->definitions
[0] = instr
->definitions
[0];
9315 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9316 new_phi
->operands
[i
] = instr
->operands
[i
];
9317 /* check that the remaining operands are all the same */
9318 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9319 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9320 instr
.swap(new_phi
);
9321 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9330 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9334 append_logical_end(ctx
->block
);
9335 ctx
->block
->kind
|= block_kind_branch
;
9337 /* branch to linear then block */
9338 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9339 aco_ptr
<Pseudo_branch_instruction
> branch
;
9340 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 1));
9341 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9342 branch
->definitions
[0].setHint(vcc
);
9343 branch
->operands
[0] = Operand(cond
);
9344 ctx
->block
->instructions
.push_back(std::move(branch
));
9346 ic
->BB_if_idx
= ctx
->block
->index
;
9347 ic
->BB_invert
= Block();
9348 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9349 /* Invert blocks are intentionally not marked as top level because they
9350 * are not part of the logical cfg. */
9351 ic
->BB_invert
.kind
|= block_kind_invert
;
9352 ic
->BB_endif
= Block();
9353 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9354 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9356 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9357 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9358 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9359 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9360 ctx
->cf_info
.parent_if
.is_divergent
= true;
9362 /* divergent branches use cbranch_execz */
9363 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9364 ctx
->cf_info
.exec_potentially_empty_break
= false;
9365 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9367 /** emit logical then block */
9368 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9369 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9370 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9371 ctx
->block
= BB_then_logical
;
9372 append_logical_start(BB_then_logical
);
9375 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9377 Block
*BB_then_logical
= ctx
->block
;
9378 append_logical_end(BB_then_logical
);
9379 /* branch from logical then block to invert block */
9380 aco_ptr
<Pseudo_branch_instruction
> branch
;
9381 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9382 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9383 branch
->definitions
[0].setHint(vcc
);
9384 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9385 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9386 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9387 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9388 BB_then_logical
->kind
|= block_kind_uniform
;
9389 assert(!ctx
->cf_info
.has_branch
);
9390 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9391 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9393 /** emit linear then block */
9394 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9395 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9396 BB_then_linear
->kind
|= block_kind_uniform
;
9397 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9398 /* branch from linear then block to invert block */
9399 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9400 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9401 branch
->definitions
[0].setHint(vcc
);
9402 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9403 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9405 /** emit invert merge block */
9406 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9407 ic
->invert_idx
= ctx
->block
->index
;
9409 /* branch to linear else block (skip else) */
9410 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 1));
9411 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9412 branch
->definitions
[0].setHint(vcc
);
9413 branch
->operands
[0] = Operand(ic
->cond
);
9414 ctx
->block
->instructions
.push_back(std::move(branch
));
9416 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9417 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9418 ic
->exec_potentially_empty_break_depth_old
=
9419 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9420 /* divergent branches use cbranch_execz */
9421 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9422 ctx
->cf_info
.exec_potentially_empty_break
= false;
9423 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9425 /** emit logical else block */
9426 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9427 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9428 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9429 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9430 ctx
->block
= BB_else_logical
;
9431 append_logical_start(BB_else_logical
);
9434 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9436 Block
*BB_else_logical
= ctx
->block
;
9437 append_logical_end(BB_else_logical
);
9439 /* branch from logical else block to endif block */
9440 aco_ptr
<Pseudo_branch_instruction
> branch
;
9441 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9442 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9443 branch
->definitions
[0].setHint(vcc
);
9444 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9445 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9446 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9447 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9448 BB_else_logical
->kind
|= block_kind_uniform
;
9450 assert(!ctx
->cf_info
.has_branch
);
9451 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9454 /** emit linear else block */
9455 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9456 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9457 BB_else_linear
->kind
|= block_kind_uniform
;
9458 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9460 /* branch from linear else block to endif block */
9461 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9462 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9463 branch
->definitions
[0].setHint(vcc
);
9464 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9465 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9468 /** emit endif merge block */
9469 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9470 append_logical_start(ctx
->block
);
9473 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9474 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9475 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9476 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9477 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9478 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9479 !ctx
->cf_info
.parent_if
.is_divergent
) {
9480 ctx
->cf_info
.exec_potentially_empty_break
= false;
9481 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9483 /* uniform control flow never has an empty exec-mask */
9484 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9485 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9486 ctx
->cf_info
.exec_potentially_empty_break
= false;
9487 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9491 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9493 assert(cond
.regClass() == s1
);
9495 append_logical_end(ctx
->block
);
9496 ctx
->block
->kind
|= block_kind_uniform
;
9498 aco_ptr
<Pseudo_branch_instruction
> branch
;
9499 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9500 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 1));
9501 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9502 branch
->definitions
[0].setHint(vcc
);
9503 branch
->operands
[0] = Operand(cond
);
9504 branch
->operands
[0].setFixed(scc
);
9505 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9507 ic
->BB_if_idx
= ctx
->block
->index
;
9508 ic
->BB_endif
= Block();
9509 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9510 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9512 ctx
->cf_info
.has_branch
= false;
9513 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9515 /** emit then block */
9516 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9517 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9518 add_edge(ic
->BB_if_idx
, BB_then
);
9519 append_logical_start(BB_then
);
9520 ctx
->block
= BB_then
;
9523 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9525 Block
*BB_then
= ctx
->block
;
9527 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9528 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9530 if (!ic
->uniform_has_then_branch
) {
9531 append_logical_end(BB_then
);
9532 /* branch from then block to endif block */
9533 aco_ptr
<Pseudo_branch_instruction
> branch
;
9534 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9535 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9536 branch
->definitions
[0].setHint(vcc
);
9537 BB_then
->instructions
.emplace_back(std::move(branch
));
9538 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9539 if (!ic
->then_branch_divergent
)
9540 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9541 BB_then
->kind
|= block_kind_uniform
;
9544 ctx
->cf_info
.has_branch
= false;
9545 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9547 /** emit else block */
9548 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9549 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9550 add_edge(ic
->BB_if_idx
, BB_else
);
9551 append_logical_start(BB_else
);
9552 ctx
->block
= BB_else
;
9555 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9557 Block
*BB_else
= ctx
->block
;
9559 if (!ctx
->cf_info
.has_branch
) {
9560 append_logical_end(BB_else
);
9561 /* branch from then block to endif block */
9562 aco_ptr
<Pseudo_branch_instruction
> branch
;
9563 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9564 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9565 branch
->definitions
[0].setHint(vcc
);
9566 BB_else
->instructions
.emplace_back(std::move(branch
));
9567 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9568 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9569 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9570 BB_else
->kind
|= block_kind_uniform
;
9573 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9574 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9576 /** emit endif merge block */
9577 if (!ctx
->cf_info
.has_branch
) {
9578 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9579 append_logical_start(ctx
->block
);
9583 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9585 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9586 Builder
bld(ctx
->program
, ctx
->block
);
9587 aco_ptr
<Pseudo_branch_instruction
> branch
;
9590 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9592 * Uniform conditionals are represented in the following way*) :
9594 * The linear and logical CFG:
9597 * BB_THEN (logical) BB_ELSE (logical)
9601 * *) Exceptions may be due to break and continue statements within loops
9602 * If a break/continue happens within uniform control flow, it branches
9603 * to the loop exit/entry block. Otherwise, it branches to the next
9607 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9608 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9609 cond
= bool_to_scalar_condition(ctx
, cond
);
9611 begin_uniform_if_then(ctx
, &ic
, cond
);
9612 visit_cf_list(ctx
, &if_stmt
->then_list
);
9614 begin_uniform_if_else(ctx
, &ic
);
9615 visit_cf_list(ctx
, &if_stmt
->else_list
);
9617 end_uniform_if(ctx
, &ic
);
9618 } else { /* non-uniform condition */
9620 * To maintain a logical and linear CFG without critical edges,
9621 * non-uniform conditionals are represented in the following way*) :
9626 * BB_THEN (logical) BB_THEN (linear)
9628 * BB_INVERT (linear)
9630 * BB_ELSE (logical) BB_ELSE (linear)
9637 * BB_THEN (logical) BB_ELSE (logical)
9641 * *) Exceptions may be due to break and continue statements within loops
9644 begin_divergent_if_then(ctx
, &ic
, cond
);
9645 visit_cf_list(ctx
, &if_stmt
->then_list
);
9647 begin_divergent_if_else(ctx
, &ic
);
9648 visit_cf_list(ctx
, &if_stmt
->else_list
);
9650 end_divergent_if(ctx
, &ic
);
9653 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9656 static bool visit_cf_list(isel_context
*ctx
,
9657 struct exec_list
*list
)
9659 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9660 switch (node
->type
) {
9661 case nir_cf_node_block
:
9662 visit_block(ctx
, nir_cf_node_as_block(node
));
9664 case nir_cf_node_if
:
9665 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9668 case nir_cf_node_loop
:
9669 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9672 unreachable("unimplemented cf list type");
9678 static void create_null_export(isel_context
*ctx
)
9680 /* Some shader stages always need to have exports.
9681 * So when there is none, we need to add a null export.
9684 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9685 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9686 Builder
bld(ctx
->program
, ctx
->block
);
9687 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9688 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9691 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9693 assert(ctx
->stage
== vertex_vs
||
9694 ctx
->stage
== tess_eval_vs
||
9695 ctx
->stage
== gs_copy_vs
||
9696 ctx
->stage
== ngg_vertex_gs
||
9697 ctx
->stage
== ngg_tess_eval_gs
);
9699 int offset
= (ctx
->stage
& sw_tes
)
9700 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9701 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9702 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9703 if (!is_pos
&& !mask
)
9705 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9707 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9708 exp
->enabled_mask
= mask
;
9709 for (unsigned i
= 0; i
< 4; ++i
) {
9710 if (mask
& (1 << i
))
9711 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9713 exp
->operands
[i
] = Operand(v1
);
9715 /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9716 * Setting valid_mask=1 prevents it and has no other effect.
9718 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& is_pos
&& *next_pos
== 0;
9720 exp
->compressed
= false;
9722 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9724 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9725 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9730 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9732 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9733 exp
->enabled_mask
= 0;
9734 for (unsigned i
= 0; i
< 4; ++i
)
9735 exp
->operands
[i
] = Operand(v1
);
9736 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9737 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9738 exp
->enabled_mask
|= 0x1;
9740 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9741 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9742 exp
->enabled_mask
|= 0x4;
9744 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9745 if (ctx
->options
->chip_class
< GFX9
) {
9746 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9747 exp
->enabled_mask
|= 0x8;
9749 Builder
bld(ctx
->program
, ctx
->block
);
9751 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9752 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9753 if (exp
->operands
[2].isTemp())
9754 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9756 exp
->operands
[2] = Operand(out
);
9757 exp
->enabled_mask
|= 0x4;
9760 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& *next_pos
== 0;
9762 exp
->compressed
= false;
9763 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9764 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9767 static void create_export_phis(isel_context
*ctx
)
9769 /* Used when exports are needed, but the output temps are defined in a preceding block.
9770 * This function will set up phis in order to access the outputs in the next block.
9773 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9774 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9775 ctx
->block
->instructions
.pop_back();
9777 Builder
bld(ctx
->program
, ctx
->block
);
9779 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9780 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9781 for (unsigned i
= 0; i
< 4; ++i
) {
9782 if (!(mask
& (1 << i
)))
9785 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9786 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9787 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9791 bld
.insert(std::move(logical_start
));
9794 static void create_vs_exports(isel_context
*ctx
)
9796 assert(ctx
->stage
== vertex_vs
||
9797 ctx
->stage
== tess_eval_vs
||
9798 ctx
->stage
== gs_copy_vs
||
9799 ctx
->stage
== ngg_vertex_gs
||
9800 ctx
->stage
== ngg_tess_eval_gs
);
9802 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9803 ? &ctx
->program
->info
->tes
.outinfo
9804 : &ctx
->program
->info
->vs
.outinfo
;
9806 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9807 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9808 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9811 if (ctx
->options
->key
.has_multiview_view_index
) {
9812 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9813 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9816 /* the order these position exports are created is important */
9818 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9819 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9820 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9821 exported_pos
= true;
9823 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9824 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9825 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9826 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9828 if (ctx
->export_clip_dists
) {
9829 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9830 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9831 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9832 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9835 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9836 if (i
< VARYING_SLOT_VAR0
&&
9837 i
!= VARYING_SLOT_LAYER
&&
9838 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9839 i
!= VARYING_SLOT_VIEWPORT
)
9842 export_vs_varying(ctx
, i
, false, NULL
);
9846 create_null_export(ctx
);
9849 static bool export_fs_mrt_z(isel_context
*ctx
)
9851 Builder
bld(ctx
->program
, ctx
->block
);
9852 unsigned enabled_channels
= 0;
9856 for (unsigned i
= 0; i
< 4; ++i
) {
9857 values
[i
] = Operand(v1
);
9860 /* Both stencil and sample mask only need 16-bits. */
9861 if (!ctx
->program
->info
->ps
.writes_z
&&
9862 (ctx
->program
->info
->ps
.writes_stencil
||
9863 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9864 compr
= true; /* COMPR flag */
9866 if (ctx
->program
->info
->ps
.writes_stencil
) {
9867 /* Stencil should be in X[23:16]. */
9868 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9869 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9870 enabled_channels
|= 0x3;
9873 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9874 /* SampleMask should be in Y[15:0]. */
9875 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9876 enabled_channels
|= 0xc;
9879 if (ctx
->program
->info
->ps
.writes_z
) {
9880 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9881 enabled_channels
|= 0x1;
9884 if (ctx
->program
->info
->ps
.writes_stencil
) {
9885 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9886 enabled_channels
|= 0x2;
9889 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9890 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9891 enabled_channels
|= 0x4;
9895 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9896 * writemask component.
9898 if (ctx
->options
->chip_class
== GFX6
&&
9899 ctx
->options
->family
!= CHIP_OLAND
&&
9900 ctx
->options
->family
!= CHIP_HAINAN
) {
9901 enabled_channels
|= 0x1;
9904 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9905 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9910 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9912 Builder
bld(ctx
->program
, ctx
->block
);
9913 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9916 for (unsigned i
= 0; i
< 4; ++i
) {
9917 if (write_mask
& (1 << i
)) {
9918 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9920 values
[i
] = Operand(v1
);
9924 unsigned target
, col_format
;
9925 unsigned enabled_channels
= 0;
9926 aco_opcode compr_op
= (aco_opcode
)0;
9928 slot
-= FRAG_RESULT_DATA0
;
9929 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9930 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9932 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9933 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9934 bool is_16bit
= values
[0].regClass() == v2b
;
9938 case V_028714_SPI_SHADER_ZERO
:
9939 enabled_channels
= 0; /* writemask */
9940 target
= V_008DFC_SQ_EXP_NULL
;
9943 case V_028714_SPI_SHADER_32_R
:
9944 enabled_channels
= 1;
9947 case V_028714_SPI_SHADER_32_GR
:
9948 enabled_channels
= 0x3;
9951 case V_028714_SPI_SHADER_32_AR
:
9952 if (ctx
->options
->chip_class
>= GFX10
) {
9953 /* Special case: on GFX10, the outputs are different for 32_AR */
9954 enabled_channels
= 0x3;
9955 values
[1] = values
[3];
9956 values
[3] = Operand(v1
);
9958 enabled_channels
= 0x9;
9962 case V_028714_SPI_SHADER_FP16_ABGR
:
9963 enabled_channels
= 0x5;
9964 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9966 if (ctx
->options
->chip_class
>= GFX9
) {
9967 /* Pack the FP16 values together instead of converting them to
9968 * FP32 and back to FP16.
9969 * TODO: use p_create_vector and let the compiler optimizes.
9971 compr_op
= aco_opcode::v_pack_b32_f16
;
9973 for (unsigned i
= 0; i
< 4; i
++) {
9974 if ((write_mask
>> i
) & 1)
9975 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9981 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9982 enabled_channels
= 0x5;
9983 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9984 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9986 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9990 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9991 enabled_channels
= 0x5;
9992 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9993 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
9995 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9999 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10000 enabled_channels
= 0x5;
10001 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10002 if (is_int8
|| is_int10
) {
10004 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10005 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10007 for (unsigned i
= 0; i
< 4; i
++) {
10008 if ((write_mask
>> i
) & 1) {
10009 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10010 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10014 } else if (is_16bit
) {
10015 for (unsigned i
= 0; i
< 4; i
++) {
10016 if ((write_mask
>> i
) & 1) {
10017 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10018 values
[i
] = Operand(tmp
);
10025 case V_028714_SPI_SHADER_SINT16_ABGR
:
10026 enabled_channels
= 0x5;
10027 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10028 if (is_int8
|| is_int10
) {
10030 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10031 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10032 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10033 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10035 for (unsigned i
= 0; i
< 4; i
++) {
10036 if ((write_mask
>> i
) & 1) {
10037 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10038 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10040 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10041 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10045 } else if (is_16bit
) {
10046 for (unsigned i
= 0; i
< 4; i
++) {
10047 if ((write_mask
>> i
) & 1) {
10048 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10049 values
[i
] = Operand(tmp
);
10055 case V_028714_SPI_SHADER_32_ABGR
:
10056 enabled_channels
= 0xF;
10063 if (target
== V_008DFC_SQ_EXP_NULL
)
10066 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10067 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10069 (col_format
== V_028714_SPI_SHADER_32_R
||
10070 col_format
== V_028714_SPI_SHADER_32_GR
||
10071 col_format
== V_028714_SPI_SHADER_32_AR
||
10072 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10073 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10074 for (int i
= 0; i
< 4; i
++) {
10075 if (!(write_mask
& (1 << i
)))
10078 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10079 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10080 bld
.copy(bld
.def(v1
), Operand(3u)));
10081 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10082 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10086 if ((bool) compr_op
) {
10087 for (int i
= 0; i
< 2; i
++) {
10088 /* check if at least one of the values to be compressed is enabled */
10089 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10091 enabled_channels
|= enabled
<< (i
*2);
10092 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10093 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10094 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10096 values
[i
] = Operand(v1
);
10099 values
[2] = Operand(v1
);
10100 values
[3] = Operand(v1
);
10102 for (int i
= 0; i
< 4; i
++)
10103 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10106 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10107 enabled_channels
, target
, (bool) compr_op
);
10111 static void create_fs_exports(isel_context
*ctx
)
10113 bool exported
= false;
10115 /* Export depth, stencil and sample mask. */
10116 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10117 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10118 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10119 exported
|= export_fs_mrt_z(ctx
);
10121 /* Export all color render targets. */
10122 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10123 if (ctx
->outputs
.mask
[i
])
10124 exported
|= export_fs_mrt_color(ctx
, i
);
10127 create_null_export(ctx
);
10130 static void create_workgroup_barrier(Builder
& bld
)
10132 bld
.barrier(aco_opcode::p_barrier
,
10133 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10137 static void write_tcs_tess_factors(isel_context
*ctx
)
10139 unsigned outer_comps
;
10140 unsigned inner_comps
;
10142 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10159 Builder
bld(ctx
->program
, ctx
->block
);
10161 create_workgroup_barrier(bld
);
10163 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10164 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10166 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10167 if_context ic_invocation_id_is_zero
;
10168 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10169 bld
.reset(ctx
->block
);
10171 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10173 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10174 unsigned stride
= inner_comps
+ outer_comps
;
10175 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10179 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10181 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10183 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10184 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10185 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10187 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10188 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10190 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10191 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10192 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10193 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10196 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10197 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10198 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10199 unsigned tf_const_offset
= 0;
10201 if (ctx
->program
->chip_class
<= GFX8
) {
10202 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10203 if_context ic_rel_patch_id_is_zero
;
10204 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10205 bld
.reset(ctx
->block
);
10207 /* Store the dynamic HS control word. */
10208 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10209 bld
.mubuf(aco_opcode::buffer_store_dword
,
10210 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10211 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10212 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10213 tf_const_offset
+= 4;
10215 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10216 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10217 bld
.reset(ctx
->block
);
10220 assert(stride
== 2 || stride
== 4 || stride
== 6);
10221 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10222 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10224 /* Store to offchip for TES to read - only if TES reads them */
10225 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10226 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10227 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10229 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10230 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10232 if (likely(inner_comps
)) {
10233 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10234 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10238 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10239 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10242 static void emit_stream_output(isel_context
*ctx
,
10243 Temp
const *so_buffers
,
10244 Temp
const *so_write_offset
,
10245 const struct radv_stream_output
*output
)
10247 unsigned num_comps
= util_bitcount(output
->component_mask
);
10248 unsigned writemask
= (1 << num_comps
) - 1;
10249 unsigned loc
= output
->location
;
10250 unsigned buf
= output
->buffer
;
10252 assert(num_comps
&& num_comps
<= 4);
10253 if (!num_comps
|| num_comps
> 4)
10256 unsigned start
= ffs(output
->component_mask
) - 1;
10259 bool all_undef
= true;
10260 assert(ctx
->stage
& hw_vs
);
10261 for (unsigned i
= 0; i
< num_comps
; i
++) {
10262 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10263 all_undef
= all_undef
&& !out
[i
].id();
10268 while (writemask
) {
10270 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10271 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10272 /* GFX6 doesn't support storing vec3, split it. */
10273 writemask
|= 1u << (start
+ 2);
10277 unsigned offset
= output
->offset
+ start
* 4;
10279 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10280 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10281 for (int i
= 0; i
< count
; ++i
)
10282 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10283 vec
->definitions
[0] = Definition(write_data
);
10284 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10289 opcode
= aco_opcode::buffer_store_dword
;
10292 opcode
= aco_opcode::buffer_store_dwordx2
;
10295 opcode
= aco_opcode::buffer_store_dwordx3
;
10298 opcode
= aco_opcode::buffer_store_dwordx4
;
10301 unreachable("Unsupported dword count.");
10304 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10305 store
->operands
[0] = Operand(so_buffers
[buf
]);
10306 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10307 store
->operands
[2] = Operand((uint32_t) 0);
10308 store
->operands
[3] = Operand(write_data
);
10309 if (offset
> 4095) {
10310 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10311 Builder
bld(ctx
->program
, ctx
->block
);
10312 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10314 store
->offset
= offset
;
10316 store
->offen
= true;
10318 store
->dlc
= false;
10320 ctx
->block
->instructions
.emplace_back(std::move(store
));
10324 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10326 Builder
bld(ctx
->program
, ctx
->block
);
10328 Temp so_buffers
[4];
10329 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10330 for (unsigned i
= 0; i
< 4; i
++) {
10331 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10335 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10336 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10339 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10340 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10342 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10344 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10347 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10349 bld
.reset(ctx
->block
);
10351 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10353 Temp so_write_offset
[4];
10355 for (unsigned i
= 0; i
< 4; i
++) {
10356 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10361 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10362 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10363 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10364 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10366 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10368 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10369 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10370 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10371 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10375 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10376 struct radv_stream_output
*output
=
10377 &ctx
->program
->info
->so
.outputs
[i
];
10378 if (stream
!= output
->stream
)
10381 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10384 begin_divergent_if_else(ctx
, &ic
);
10385 end_divergent_if(ctx
, &ic
);
10388 } /* end namespace */
10390 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10392 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10393 Builder
bld(ctx
->program
, ctx
->block
);
10394 constexpr unsigned hs_idx
= 1u;
10395 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10396 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10397 Operand((8u << 16) | (hs_idx
* 8u)));
10398 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10400 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10402 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10403 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10404 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10405 ls_has_nonzero_hs_threads
);
10406 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10407 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10408 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10409 ls_has_nonzero_hs_threads
);
10410 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10411 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10412 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10413 ls_has_nonzero_hs_threads
);
10415 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10416 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10417 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10420 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10422 /* Split all arguments except for the first (ring_offsets) and the last
10423 * (exec) so that the dead channels don't stay live throughout the program.
10425 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10426 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10427 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10428 startpgm
->definitions
[i
].regClass().size());
10433 void handle_bc_optimize(isel_context
*ctx
)
10435 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10436 Builder
bld(ctx
->program
, ctx
->block
);
10437 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10438 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10439 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10440 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10441 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10442 if (uses_center
&& uses_centroid
) {
10443 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10444 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10446 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10448 for (unsigned i
= 0; i
< 2; i
++) {
10449 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10450 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10451 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10452 persp_centroid
, persp_center
, sel
);
10454 ctx
->persp_centroid
= bld
.tmp(v2
);
10455 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10456 Operand(new_coord
[0]), Operand(new_coord
[1]));
10457 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10460 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10462 for (unsigned i
= 0; i
< 2; i
++) {
10463 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10464 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10465 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10466 linear_centroid
, linear_center
, sel
);
10468 ctx
->linear_centroid
= bld
.tmp(v2
);
10469 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10470 Operand(new_coord
[0]), Operand(new_coord
[1]));
10471 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10476 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10478 Program
*program
= ctx
->program
;
10480 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10482 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10483 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10484 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10485 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10486 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10488 program
->next_fp_mode
.must_flush_denorms32
=
10489 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10490 program
->next_fp_mode
.must_flush_denorms16_64
=
10491 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10492 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10494 program
->next_fp_mode
.care_about_round32
=
10495 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10497 program
->next_fp_mode
.care_about_round16_64
=
10498 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10499 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10501 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10502 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10503 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10504 program
->next_fp_mode
.denorm16_64
= 0;
10506 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10508 /* preserving fp32 denorms is expensive, so only do it if asked */
10509 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10510 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10512 program
->next_fp_mode
.denorm32
= 0;
10514 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10515 program
->next_fp_mode
.round32
= fp_round_tz
;
10517 program
->next_fp_mode
.round32
= fp_round_ne
;
10519 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10520 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10522 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10524 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10527 void cleanup_cfg(Program
*program
)
10529 /* create linear_succs/logical_succs */
10530 for (Block
& BB
: program
->blocks
) {
10531 for (unsigned idx
: BB
.linear_preds
)
10532 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10533 for (unsigned idx
: BB
.logical_preds
)
10534 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10538 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10540 Builder
bld(ctx
->program
, ctx
->block
);
10542 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10543 Temp count
= i
== 0
10544 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10545 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10546 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10548 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10551 if (ctx
->program
->wave_size
== 64) {
10552 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10553 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10554 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10556 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10557 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10563 bool ngg_early_prim_export(isel_context
*ctx
)
10565 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10569 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10571 Builder
bld(ctx
->program
, ctx
->block
);
10573 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10574 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10576 /* Get the id of the current wave within the threadgroup (workgroup) */
10577 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10578 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10580 /* Execute the following code only on the first wave (wave id 0),
10581 * use the SCC def to tell if the wave id is zero or not.
10583 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10585 begin_uniform_if_then(ctx
, &ic
, cond
);
10586 begin_uniform_if_else(ctx
, &ic
);
10587 bld
.reset(ctx
->block
);
10589 /* Number of vertices output by VS/TES */
10590 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10591 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10592 /* Number of primitives output by VS/TES */
10593 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10594 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10596 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10597 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10598 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10600 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10601 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10603 end_uniform_if(ctx
, &ic
);
10605 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10606 bld
.reset(ctx
->block
);
10607 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10610 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10612 Builder
bld(ctx
->program
, ctx
->block
);
10614 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10615 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10618 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10621 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10622 assert(vtxindex
[i
].id());
10625 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10629 /* The initial edge flag is always false in tess eval shaders. */
10630 if (ctx
->stage
== ngg_vertex_gs
) {
10631 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10632 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10636 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10641 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10643 Builder
bld(ctx
->program
, ctx
->block
);
10644 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10646 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10647 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10648 false /* compressed */, true/* done */, false /* valid mask */);
10651 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10653 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10654 * These must always come before VS exports.
10656 * It is recommended to do these as early as possible. They can be at the beginning when
10657 * there is no SW GS and the shader doesn't write edge flags.
10661 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10662 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10664 Builder
bld(ctx
->program
, ctx
->block
);
10665 constexpr unsigned max_vertices_per_primitive
= 3;
10666 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10668 if (ctx
->stage
== ngg_vertex_gs
) {
10669 /* TODO: optimize for points & lines */
10670 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10671 if (ctx
->shader
->info
.tess
.point_mode
)
10672 num_vertices_per_primitive
= 1;
10673 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10674 num_vertices_per_primitive
= 2;
10676 unreachable("Unsupported NGG shader stage");
10679 Temp vtxindex
[max_vertices_per_primitive
];
10680 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10681 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10682 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10683 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10684 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10685 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10686 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10687 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10689 /* Export primitive data to the index buffer. */
10690 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10692 /* Export primitive ID. */
10693 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10694 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10695 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10696 Temp provoking_vtx_index
= vtxindex
[0];
10697 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10699 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10702 begin_divergent_if_else(ctx
, &ic
);
10703 end_divergent_if(ctx
, &ic
);
10706 void ngg_emit_nogs_output(isel_context
*ctx
)
10708 /* Emits NGG GS output, for stages that don't have SW GS. */
10711 Builder
bld(ctx
->program
, ctx
->block
);
10712 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10714 /* NGG streamout is currently disabled by default. */
10715 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10717 if (late_prim_export
) {
10718 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10719 create_export_phis(ctx
);
10720 /* Do what we need to do in the GS threads. */
10721 ngg_emit_nogs_gsthreads(ctx
);
10723 /* What comes next should be executed on ES threads. */
10724 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10725 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10726 bld
.reset(ctx
->block
);
10729 /* Export VS outputs */
10730 ctx
->block
->kind
|= block_kind_export_end
;
10731 create_vs_exports(ctx
);
10733 /* Export primitive ID */
10734 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10737 if (ctx
->stage
== ngg_vertex_gs
) {
10738 /* Wait for GS threads to store primitive ID in LDS. */
10739 create_workgroup_barrier(bld
);
10741 /* Calculate LDS address where the GS threads stored the primitive ID. */
10742 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10743 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10744 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10745 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10746 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10747 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10749 /* Load primitive ID from LDS. */
10750 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10751 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10752 /* TES: Just use the patch ID as the primitive ID. */
10753 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10755 unreachable("unsupported NGG shader stage.");
10758 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10759 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10761 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10764 if (late_prim_export
) {
10765 begin_divergent_if_else(ctx
, &ic
);
10766 end_divergent_if(ctx
, &ic
);
10767 bld
.reset(ctx
->block
);
10771 void select_program(Program
*program
,
10772 unsigned shader_count
,
10773 struct nir_shader
*const *shaders
,
10774 ac_shader_config
* config
,
10775 struct radv_shader_args
*args
)
10777 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10778 if_context ic_merged_wave_info
;
10779 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10781 for (unsigned i
= 0; i
< shader_count
; i
++) {
10782 nir_shader
*nir
= shaders
[i
];
10783 init_context(&ctx
, nir
);
10785 setup_fp_mode(&ctx
, nir
);
10788 /* needs to be after init_context() for FS */
10789 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10790 append_logical_start(ctx
.block
);
10792 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10793 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10795 split_arguments(&ctx
, startpgm
);
10799 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10801 if (ngg_early_prim_export(&ctx
))
10802 ngg_emit_nogs_gsthreads(&ctx
);
10805 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10806 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10807 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10808 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10809 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10810 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10811 ctx
.stage
== tess_eval_geometry_gs
));
10813 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10814 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10815 if (check_merged_wave_info
) {
10816 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10817 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10821 Builder
bld(ctx
.program
, ctx
.block
);
10823 create_workgroup_barrier(bld
);
10825 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10826 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10828 } else if (ctx
.stage
== geometry_gs
)
10829 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10831 if (ctx
.stage
== fragment_fs
)
10832 handle_bc_optimize(&ctx
);
10834 visit_cf_list(&ctx
, &func
->body
);
10836 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10837 emit_streamout(&ctx
, 0);
10839 if (ctx
.stage
& hw_vs
) {
10840 create_vs_exports(&ctx
);
10841 ctx
.block
->kind
|= block_kind_export_end
;
10842 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10843 ngg_emit_nogs_output(&ctx
);
10844 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10845 Builder
bld(ctx
.program
, ctx
.block
);
10846 bld
.barrier(aco_opcode::p_barrier
,
10847 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
10848 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10849 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10850 write_tcs_tess_factors(&ctx
);
10853 if (ctx
.stage
== fragment_fs
) {
10854 create_fs_exports(&ctx
);
10855 ctx
.block
->kind
|= block_kind_export_end
;
10858 if (endif_merged_wave_info
) {
10859 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10860 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10863 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10864 ngg_emit_nogs_output(&ctx
);
10866 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10867 /* Outputs of the previous stage are inputs to the next stage */
10868 ctx
.inputs
= ctx
.outputs
;
10869 ctx
.outputs
= shader_io_state();
10873 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10875 append_logical_end(ctx
.block
);
10876 ctx
.block
->kind
|= block_kind_uniform
;
10877 Builder
bld(ctx
.program
, ctx
.block
);
10878 if (ctx
.program
->wb_smem_l1_on_end
)
10879 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
10880 bld
.sopp(aco_opcode::s_endpgm
);
10882 cleanup_cfg(program
);
10885 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10886 ac_shader_config
* config
,
10887 struct radv_shader_args
*args
)
10889 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10891 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10893 add_startpgm(&ctx
);
10894 append_logical_start(ctx
.block
);
10896 Builder
bld(ctx
.program
, ctx
.block
);
10898 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10900 Operand
stream_id(0u);
10901 if (args
->shader_info
->so
.num_outputs
)
10902 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10903 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10905 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10907 std::stack
<Block
> endif_blocks
;
10909 for (unsigned stream
= 0; stream
< 4; stream
++) {
10910 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10913 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10914 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10917 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10919 unsigned BB_if_idx
= ctx
.block
->index
;
10920 Block BB_endif
= Block();
10921 if (!stream_id
.isConstant()) {
10923 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10924 append_logical_end(ctx
.block
);
10925 ctx
.block
->kind
|= block_kind_uniform
;
10926 bld
.branch(aco_opcode::p_cbranch_z
, bld
.hint_vcc(bld
.def(s2
)), cond
);
10928 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10930 ctx
.block
= ctx
.program
->create_and_insert_block();
10931 add_edge(BB_if_idx
, ctx
.block
);
10932 bld
.reset(ctx
.block
);
10933 append_logical_start(ctx
.block
);
10936 unsigned offset
= 0;
10937 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10938 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10941 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10942 unsigned length
= util_last_bit(output_usage_mask
);
10943 for (unsigned j
= 0; j
< length
; ++j
) {
10944 if (!(output_usage_mask
& (1 << j
)))
10947 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10948 Temp voffset
= vtx_offset
;
10949 if (const_offset
>= 4096u) {
10950 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10951 const_offset
%= 4096u;
10954 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10955 mubuf
->definitions
[0] = bld
.def(v1
);
10956 mubuf
->operands
[0] = Operand(gsvs_ring
);
10957 mubuf
->operands
[1] = Operand(voffset
);
10958 mubuf
->operands
[2] = Operand(0u);
10959 mubuf
->offen
= true;
10960 mubuf
->offset
= const_offset
;
10963 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10965 ctx
.outputs
.mask
[i
] |= 1 << j
;
10966 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10968 bld
.insert(std::move(mubuf
));
10974 if (args
->shader_info
->so
.num_outputs
) {
10975 emit_streamout(&ctx
, stream
);
10976 bld
.reset(ctx
.block
);
10980 create_vs_exports(&ctx
);
10981 ctx
.block
->kind
|= block_kind_export_end
;
10984 if (!stream_id
.isConstant()) {
10985 append_logical_end(ctx
.block
);
10987 /* branch from then block to endif block */
10988 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
10989 add_edge(ctx
.block
->index
, &BB_endif
);
10990 ctx
.block
->kind
|= block_kind_uniform
;
10992 /* emit else block */
10993 ctx
.block
= ctx
.program
->create_and_insert_block();
10994 add_edge(BB_if_idx
, ctx
.block
);
10995 bld
.reset(ctx
.block
);
10996 append_logical_start(ctx
.block
);
10998 endif_blocks
.push(std::move(BB_endif
));
11002 while (!endif_blocks
.empty()) {
11003 Block BB_endif
= std::move(endif_blocks
.top());
11004 endif_blocks
.pop();
11006 Block
*BB_else
= ctx
.block
;
11008 append_logical_end(BB_else
);
11009 /* branch from else block to endif block */
11010 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
11011 add_edge(BB_else
->index
, &BB_endif
);
11012 BB_else
->kind
|= block_kind_uniform
;
11014 /** emit endif merge block */
11015 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11016 bld
.reset(ctx
.block
);
11017 append_logical_start(ctx
.block
);
11020 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11022 append_logical_end(ctx
.block
);
11023 ctx
.block
->kind
|= block_kind_uniform
;
11024 bld
.sopp(aco_opcode::s_endpgm
);
11026 cleanup_cfg(program
);
11029 void select_trap_handler_shader(Program
*program
, struct nir_shader
*shader
,
11030 ac_shader_config
* config
,
11031 struct radv_shader_args
*args
)
11033 assert(args
->options
->chip_class
== GFX8
);
11035 init_program(program
, compute_cs
, args
->shader_info
,
11036 args
->options
->chip_class
, args
->options
->family
, config
);
11038 isel_context ctx
= {};
11039 ctx
.program
= program
;
11041 ctx
.options
= args
->options
;
11042 ctx
.stage
= program
->stage
;
11044 ctx
.block
= ctx
.program
->create_and_insert_block();
11045 ctx
.block
->loop_nest_depth
= 0;
11046 ctx
.block
->kind
= block_kind_top_level
;
11048 program
->workgroup_size
= 1; /* XXX */
11050 add_startpgm(&ctx
);
11051 append_logical_start(ctx
.block
);
11053 Builder
bld(ctx
.program
, ctx
.block
);
11055 /* Load the buffer descriptor from TMA. */
11056 bld
.smem(aco_opcode::s_load_dwordx4
, Definition(PhysReg
{ttmp4
}, s4
),
11057 Operand(PhysReg
{tma
}, s2
), Operand(0u));
11059 /* Store TTMP0-TTMP1. */
11060 bld
.smem(aco_opcode::s_buffer_store_dwordx2
, Operand(PhysReg
{ttmp4
}, s4
),
11061 Operand(0u), Operand(PhysReg
{ttmp0
}, s2
), memory_sync_info(), true);
11063 uint32_t hw_regs_idx
[] = {
11064 2, /* HW_REG_STATUS */
11065 3, /* HW_REG_TRAP_STS */
11066 4, /* HW_REG_HW_ID */
11067 7, /* HW_REG_IB_STS */
11070 /* Store some hardware registers. */
11071 for (unsigned i
= 0; i
< ARRAY_SIZE(hw_regs_idx
); i
++) {
11072 /* "((size - 1) << 11) | register" */
11073 bld
.sopk(aco_opcode::s_getreg_b32
, Definition(PhysReg
{ttmp8
}, s1
),
11074 ((20 - 1) << 11) | hw_regs_idx
[i
]);
11076 bld
.smem(aco_opcode::s_buffer_store_dword
, Operand(PhysReg
{ttmp4
}, s4
),
11077 Operand(8u + i
* 4), Operand(PhysReg
{ttmp8
}, s1
), memory_sync_info(), true);
11080 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11082 append_logical_end(ctx
.block
);
11083 ctx
.block
->kind
|= block_kind_uniform
;
11084 bld
.sopp(aco_opcode::s_endpgm
);
11086 cleanup_cfg(program
);