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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
139 } else if (ctx
->program
->chip_class
<= GFX7
) {
140 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
143 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
148 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
150 Builder
bld(ctx
->program
, ctx
->block
);
153 dst
= bld
.tmp(src
.regClass());
155 assert(src
.size() == dst
.size());
157 if (ctx
->stage
!= fragment_fs
) {
161 bld
.copy(Definition(dst
), src
);
165 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
166 ctx
->program
->needs_wqm
|= program_needs_wqm
;
170 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
172 if (index
.regClass() == s1
)
173 return bld
.readlane(bld
.def(s1
), data
, index
);
175 if (ctx
->options
->chip_class
<= GFX7
) {
176 /* GFX6-7: there is no bpermute instruction */
177 Operand
index_op(index
);
178 Operand
input_data(data
);
179 index_op
.setLateKill(true);
180 input_data
.setLateKill(true);
182 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
183 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
184 /* GFX10 wave64 mode: emulate full-wave bpermute */
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
192 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
193 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
194 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
195 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
196 Operand
input_data(data
);
198 index_x4
.setLateKill(true);
199 input_data
.setLateKill(true);
200 same_half
.setLateKill(true);
202 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
204 /* GFX8-9 or GFX10 wave32: bpermute works normally */
205 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
206 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
210 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
212 if (ctx
->options
->chip_class
>= GFX8
) {
213 unsigned and_mask
= mask
& 0x1f;
214 unsigned or_mask
= (mask
>> 5) & 0x1f;
215 unsigned xor_mask
= (mask
>> 10) & 0x1f;
217 uint16_t dpp_ctrl
= 0xffff;
219 // TODO: we could use DPP8 for some swizzles
220 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
221 unsigned res
[4] = {0, 1, 2, 3};
222 for (unsigned i
= 0; i
< 4; i
++)
223 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
224 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
225 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
226 dpp_ctrl
= dpp_row_rr(8);
227 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
228 dpp_ctrl
= dpp_row_mirror
;
229 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
230 dpp_ctrl
= dpp_row_half_mirror
;
233 if (dpp_ctrl
!= 0xffff)
234 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
237 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
240 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
242 if (val
.type() == RegType::sgpr
) {
243 Builder
bld(ctx
->program
, ctx
->block
);
244 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
246 assert(val
.type() == RegType::vgpr
);
250 //assumes a != 0xffffffff
251 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
254 Builder
bld(ctx
->program
, ctx
->block
);
256 if (util_is_power_of_two_or_zero(b
)) {
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
261 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
263 assert(info
.multiplier
<= 0xffffffff);
265 bool pre_shift
= info
.pre_shift
!= 0;
266 bool increment
= info
.increment
!= 0;
267 bool multiply
= true;
268 bool post_shift
= info
.post_shift
!= 0;
270 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
271 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
275 Temp pre_shift_dst
= a
;
277 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
278 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
281 Temp increment_dst
= pre_shift_dst
;
283 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
284 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
287 Temp multiply_dst
= increment_dst
;
289 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
290 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
291 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
299 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
301 Builder
bld(ctx
->program
, ctx
->block
);
302 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
306 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
308 /* no need to extract the whole vector */
309 if (src
.regClass() == dst_rc
) {
314 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
315 Builder
bld(ctx
->program
, ctx
->block
);
316 auto it
= ctx
->allocated_vec
.find(src
.id());
317 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
318 if (it
->second
[idx
].regClass() == dst_rc
) {
319 return it
->second
[idx
];
321 assert(!dst_rc
.is_subdword());
322 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
323 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
327 if (dst_rc
.is_subdword())
328 src
= as_vgpr(ctx
, src
);
330 if (src
.bytes() == dst_rc
.bytes()) {
332 return bld
.copy(bld
.def(dst_rc
), src
);
334 Temp dst
= bld
.tmp(dst_rc
);
335 emit_extract_vector(ctx
, src
, idx
, dst
);
340 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
342 if (num_components
== 1)
344 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
347 if (num_components
> vec_src
.size()) {
348 if (vec_src
.type() == RegType::sgpr
) {
349 /* should still help get_alu_src() */
350 emit_split_vector(ctx
, vec_src
, vec_src
.size());
353 /* sub-dword split */
354 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
356 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
358 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
359 split
->operands
[0] = Operand(vec_src
);
360 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
361 for (unsigned i
= 0; i
< num_components
; i
++) {
362 elems
[i
] = {ctx
->program
->allocateId(), rc
};
363 split
->definitions
[i
] = Definition(elems
[i
]);
365 ctx
->block
->instructions
.emplace_back(std::move(split
));
366 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
369 /* This vector expansion uses a mask to determine which elements in the new vector
370 * come from the original vector. The other elements are undefined. */
371 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
373 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
378 Builder
bld(ctx
->program
, ctx
->block
);
379 if (num_components
== 1) {
380 if (dst
.type() == RegType::sgpr
)
381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
383 bld
.copy(Definition(dst
), vec_src
);
387 unsigned component_size
= dst
.size() / num_components
;
388 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
390 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
391 vec
->definitions
[0] = Definition(dst
);
393 for (unsigned i
= 0; i
< num_components
; i
++) {
394 if (mask
& (1 << i
)) {
395 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
396 if (dst
.type() == RegType::sgpr
)
397 src
= bld
.as_uniform(src
);
398 vec
->operands
[i
] = Operand(src
);
400 vec
->operands
[i
] = Operand(0u);
402 elems
[i
] = vec
->operands
[i
].getTemp();
404 ctx
->block
->instructions
.emplace_back(std::move(vec
));
405 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
408 /* adjust misaligned small bit size loads */
409 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
411 Builder
bld(ctx
->program
, ctx
->block
);
413 Temp select
= Temp();
414 if (offset
.isConstant()) {
415 assert(offset
.constantValue() && offset
.constantValue() < 4);
416 shift
= Operand(offset
.constantValue() * 8);
418 /* bit_offset = 8 * (offset & 0x3) */
419 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
420 select
= bld
.tmp(s1
);
421 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
424 if (vec
.size() == 1) {
425 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
426 } else if (vec
.size() == 2) {
427 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
428 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
430 emit_split_vector(ctx
, dst
, 2);
432 emit_extract_vector(ctx
, tmp
, 0, dst
);
433 } else if (vec
.size() == 4) {
434 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
435 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
436 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
437 if (select
!= Temp())
438 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
439 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
440 Temp mid
= bld
.tmp(s1
);
441 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
442 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
443 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
444 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
445 emit_split_vector(ctx
, dst
, 2);
449 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
451 Builder
bld(ctx
->program
, ctx
->block
);
452 if (offset
.isTemp()) {
453 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
455 if (vec
.size() == 4) {
456 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
458 } else if (vec
.size() == 3) {
459 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
461 } else if (vec
.size() == 2) {
462 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
465 for (unsigned i
= 0; i
< dst
.size(); i
++)
466 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
470 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
472 offset
= Operand(0u);
475 unsigned num_components
= dst
.bytes() / component_size
;
476 if (vec
.regClass() == dst
.regClass()) {
477 assert(offset
.constantValue() == 0);
478 bld
.copy(Definition(dst
), vec
);
479 emit_split_vector(ctx
, dst
, num_components
);
483 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
484 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
485 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
487 assert(offset
.constantValue() % component_size
== 0);
488 unsigned skip
= offset
.constantValue() / component_size
;
489 for (unsigned i
= 0; i
< num_components
; i
++)
490 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
492 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
493 if (dst
.type() == RegType::vgpr
) {
494 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
495 for (unsigned i
= 0; i
< num_components
; i
++)
496 create_vec
->operands
[i
] = Operand(elems
[i
]);
497 create_vec
->definitions
[0] = Definition(dst
);
498 bld
.insert(std::move(create_vec
));
500 /* if dst is sgpr - split the src, but move the original to sgpr. */
502 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
503 byte_align_scalar(ctx
, vec
, offset
, dst
);
505 assert(dst
.size() == vec
.size());
506 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
509 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
512 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
514 Builder
bld(ctx
->program
, ctx
->block
);
516 dst
= bld
.tmp(bld
.lm
);
518 assert(val
.regClass() == s1
);
519 assert(dst
.regClass() == bld
.lm
);
521 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
524 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
526 Builder
bld(ctx
->program
, ctx
->block
);
530 assert(val
.regClass() == bld
.lm
);
531 assert(dst
.regClass() == s1
);
533 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
534 Temp tmp
= bld
.tmp(s1
);
535 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
536 return emit_wqm(ctx
, tmp
, dst
);
539 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
541 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
542 return get_ssa_temp(ctx
, src
.src
.ssa
);
544 if (src
.src
.ssa
->num_components
== size
) {
545 bool identity_swizzle
= true;
546 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
547 if (src
.swizzle
[i
] != i
)
548 identity_swizzle
= false;
550 if (identity_swizzle
)
551 return get_ssa_temp(ctx
, src
.src
.ssa
);
554 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
555 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
556 assert(elem_size
> 0);
557 assert(vec
.bytes() % elem_size
== 0);
559 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
560 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
562 unsigned swizzle
= src
.swizzle
[0];
563 if (vec
.size() > 1) {
564 assert(src
.src
.ssa
->bit_size
== 16);
565 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
566 swizzle
= swizzle
& 1;
571 Temp dst
{ctx
->program
->allocateId(), s1
};
572 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
573 bfe
->operands
[0] = Operand(vec
);
574 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
575 bfe
->definitions
[0] = Definition(dst
);
576 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
577 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
581 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
583 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
586 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
587 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
588 for (unsigned i
= 0; i
< size
; ++i
) {
589 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
590 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
592 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
593 vec_instr
->definitions
[0] = Definition(dst
);
594 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
595 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
600 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
604 Builder
bld(ctx
->program
, ctx
->block
);
605 if (ptr
.type() == RegType::vgpr
)
606 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
607 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
608 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
611 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
613 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
614 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
615 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
616 sop2
->definitions
[0] = Definition(dst
);
618 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
619 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
622 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
623 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
625 Builder
bld(ctx
->program
, ctx
->block
);
626 bld
.is_precise
= instr
->exact
;
628 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
629 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
630 if (src1
.type() == RegType::sgpr
) {
631 if (commutative
&& src0
.type() == RegType::vgpr
) {
636 src1
= as_vgpr(ctx
, src1
);
640 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
641 assert(dst
.size() == 1);
642 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
643 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
645 bld
.vop2(op
, Definition(dst
), src0
, src1
);
649 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
650 aco_opcode op
, Temp dst
)
652 Builder
bld(ctx
->program
, ctx
->block
);
653 bld
.is_precise
= instr
->exact
;
655 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
656 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
658 if (src1
.type() == RegType::sgpr
) {
659 assert(src0
.type() == RegType::vgpr
);
660 std::swap(src0
, src1
);
663 Temp src00
= bld
.tmp(src0
.type(), 1);
664 Temp src01
= bld
.tmp(src0
.type(), 1);
665 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
666 Temp src10
= bld
.tmp(v1
);
667 Temp src11
= bld
.tmp(v1
);
668 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
669 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
670 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
671 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
674 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
675 bool flush_denorms
= false)
677 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
678 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
679 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
681 /* ensure that the instruction has at most 1 sgpr operand
682 * The optimizer will inline constants for us */
683 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
684 src0
= as_vgpr(ctx
, src0
);
685 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
686 src1
= as_vgpr(ctx
, src1
);
687 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
688 src2
= as_vgpr(ctx
, src2
);
690 Builder
bld(ctx
->program
, ctx
->block
);
691 bld
.is_precise
= instr
->exact
;
692 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
693 assert(dst
.size() == 1);
694 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
695 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
697 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
701 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
703 Builder
bld(ctx
->program
, ctx
->block
);
704 bld
.is_precise
= instr
->exact
;
705 if (dst
.type() == RegType::sgpr
)
706 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
707 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
709 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
712 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
714 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
715 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
716 assert(src0
.size() == src1
.size());
718 aco_ptr
<Instruction
> vopc
;
719 if (src1
.type() == RegType::sgpr
) {
720 if (src0
.type() == RegType::vgpr
) {
721 /* to swap the operands, we might also have to change the opcode */
723 case aco_opcode::v_cmp_lt_f16
:
724 op
= aco_opcode::v_cmp_gt_f16
;
726 case aco_opcode::v_cmp_ge_f16
:
727 op
= aco_opcode::v_cmp_le_f16
;
729 case aco_opcode::v_cmp_lt_i16
:
730 op
= aco_opcode::v_cmp_gt_i16
;
732 case aco_opcode::v_cmp_ge_i16
:
733 op
= aco_opcode::v_cmp_le_i16
;
735 case aco_opcode::v_cmp_lt_u16
:
736 op
= aco_opcode::v_cmp_gt_u16
;
738 case aco_opcode::v_cmp_ge_u16
:
739 op
= aco_opcode::v_cmp_le_u16
;
741 case aco_opcode::v_cmp_lt_f32
:
742 op
= aco_opcode::v_cmp_gt_f32
;
744 case aco_opcode::v_cmp_ge_f32
:
745 op
= aco_opcode::v_cmp_le_f32
;
747 case aco_opcode::v_cmp_lt_i32
:
748 op
= aco_opcode::v_cmp_gt_i32
;
750 case aco_opcode::v_cmp_ge_i32
:
751 op
= aco_opcode::v_cmp_le_i32
;
753 case aco_opcode::v_cmp_lt_u32
:
754 op
= aco_opcode::v_cmp_gt_u32
;
756 case aco_opcode::v_cmp_ge_u32
:
757 op
= aco_opcode::v_cmp_le_u32
;
759 case aco_opcode::v_cmp_lt_f64
:
760 op
= aco_opcode::v_cmp_gt_f64
;
762 case aco_opcode::v_cmp_ge_f64
:
763 op
= aco_opcode::v_cmp_le_f64
;
765 case aco_opcode::v_cmp_lt_i64
:
766 op
= aco_opcode::v_cmp_gt_i64
;
768 case aco_opcode::v_cmp_ge_i64
:
769 op
= aco_opcode::v_cmp_le_i64
;
771 case aco_opcode::v_cmp_lt_u64
:
772 op
= aco_opcode::v_cmp_gt_u64
;
774 case aco_opcode::v_cmp_ge_u64
:
775 op
= aco_opcode::v_cmp_le_u64
;
777 default: /* eq and ne are commutative */
784 src1
= as_vgpr(ctx
, src1
);
788 Builder
bld(ctx
->program
, ctx
->block
);
789 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
792 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
794 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
795 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
796 Builder
bld(ctx
->program
, ctx
->block
);
798 assert(dst
.regClass() == bld
.lm
);
799 assert(src0
.type() == RegType::sgpr
);
800 assert(src1
.type() == RegType::sgpr
);
801 assert(src0
.regClass() == src1
.regClass());
803 /* Emit the SALU comparison instruction */
804 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
805 /* Turn the result into a per-lane bool */
806 bool_to_vector_condition(ctx
, cmp
, dst
);
809 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
810 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
812 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
813 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
814 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
815 nir_dest_is_divergent(instr
->dest
.dest
) ||
816 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
817 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
818 aco_opcode op
= use_valu
? v_op
: s_op
;
819 assert(op
!= aco_opcode::num_opcodes
);
820 assert(dst
.regClass() == ctx
->program
->lane_mask
);
823 emit_vopc_instruction(ctx
, instr
, op
, dst
);
825 emit_sopc_instruction(ctx
, instr
, op
, dst
);
828 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
830 Builder
bld(ctx
->program
, ctx
->block
);
831 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
832 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
834 assert(dst
.regClass() == bld
.lm
);
835 assert(src0
.regClass() == bld
.lm
);
836 assert(src1
.regClass() == bld
.lm
);
838 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
841 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
843 Builder
bld(ctx
->program
, ctx
->block
);
844 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
845 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
846 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
848 assert(cond
.regClass() == bld
.lm
);
850 if (dst
.type() == RegType::vgpr
) {
851 aco_ptr
<Instruction
> bcsel
;
852 if (dst
.size() == 1) {
853 then
= as_vgpr(ctx
, then
);
854 els
= as_vgpr(ctx
, els
);
856 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
857 } else if (dst
.size() == 2) {
858 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
859 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
860 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
863 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
864 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
866 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
868 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
869 nir_print_instr(&instr
->instr
, stderr
);
870 fprintf(stderr
, "\n");
875 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
876 assert(dst
.regClass() == bld
.lm
);
877 assert(then
.regClass() == bld
.lm
);
878 assert(els
.regClass() == bld
.lm
);
881 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
882 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
883 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
884 assert(dst
.size() == then
.size());
885 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
886 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
888 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
889 nir_print_instr(&instr
->instr
, stderr
);
890 fprintf(stderr
, "\n");
895 /* divergent boolean bcsel
896 * this implements bcsel on bools: dst = s0 ? s1 : s2
897 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
898 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
900 if (cond
.id() != then
.id())
901 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
903 if (cond
.id() == els
.id())
904 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
906 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
907 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
910 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
911 aco_opcode op
, uint32_t undo
)
913 /* multiply by 16777216 to handle denormals */
914 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
915 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
916 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
917 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
918 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
920 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
922 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
925 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
927 if (ctx
->block
->fp_mode
.denorm32
== 0) {
928 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
932 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
935 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
937 if (ctx
->block
->fp_mode
.denorm32
== 0) {
938 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
942 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
945 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
947 if (ctx
->block
->fp_mode
.denorm32
== 0) {
948 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
952 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
955 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
957 if (ctx
->block
->fp_mode
.denorm32
== 0) {
958 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
962 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
965 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
967 if (ctx
->options
->chip_class
>= GFX7
)
968 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
970 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
971 /* TODO: create more efficient code! */
972 if (val
.type() == RegType::sgpr
)
973 val
= as_vgpr(ctx
, val
);
975 /* Split the input value. */
976 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
977 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
979 /* Extract the exponent and compute the unbiased value. */
980 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
981 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
983 /* Extract the fractional part. */
984 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
985 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
987 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
988 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
990 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
991 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
992 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
993 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
994 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
996 /* Get the sign bit. */
997 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
999 /* Decide the operation to apply depending on the unbiased exponent. */
1000 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1001 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1002 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1003 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1004 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1005 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1007 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1010 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1012 if (ctx
->options
->chip_class
>= GFX7
)
1013 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1015 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1016 * lowered at NIR level for precision reasons). */
1017 Temp src0
= as_vgpr(ctx
, val
);
1019 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1020 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1022 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1023 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1024 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1026 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1027 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1028 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1031 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1032 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1034 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1036 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1037 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1039 return add
->definitions
[0].getTemp();
1042 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1044 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1045 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1047 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1050 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1051 return bld
.copy(Definition(dst
), src
);
1052 else if (dst
.bytes() < src
.bytes())
1053 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1057 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1060 } else if (src
.regClass() == s1
) {
1062 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1064 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1065 } else if (ctx
->options
->chip_class
>= GFX8
) {
1066 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1067 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1068 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1069 sdwa
->operands
[0] = Operand(src
);
1070 sdwa
->definitions
[0] = Definition(tmp
);
1072 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1074 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1075 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1076 bld
.insert(std::move(sdwa
));
1078 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1079 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1080 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1083 if (dst_bits
== 64) {
1084 if (is_signed
&& dst
.regClass() == s2
) {
1085 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1086 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1087 } else if (is_signed
&& dst
.regClass() == v2
) {
1088 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1089 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1091 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1098 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1100 if (!instr
->dest
.dest
.is_ssa
) {
1101 fprintf(stderr
, "nir alu dst not in ssa: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1106 Builder
bld(ctx
->program
, ctx
->block
);
1107 bld
.is_precise
= instr
->exact
;
1108 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1113 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1114 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1115 for (unsigned i
= 0; i
< num
; ++i
)
1116 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1118 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1119 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1120 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1121 for (unsigned i
= 0; i
< num
; ++i
) {
1122 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1123 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1125 vec
->operands
[i
] = Operand
{elems
[i
]};
1127 vec
->definitions
[0] = Definition(dst
);
1128 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1129 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1131 // TODO: that is a bit suboptimal..
1132 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1133 for (unsigned i
= 0; i
< num
- 1; ++i
)
1134 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1135 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1136 for (unsigned i
= 0; i
< num
; ++i
) {
1137 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1138 if (bit
% 32 == 0) {
1139 elems
[bit
/ 32] = elems
[i
];
1141 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1142 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1143 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1146 if (dst
.size() == 1)
1147 bld
.copy(Definition(dst
), elems
[0]);
1149 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1154 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1155 aco_ptr
<Instruction
> mov
;
1156 if (dst
.type() == RegType::sgpr
) {
1157 if (src
.type() == RegType::vgpr
)
1158 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1159 else if (src
.regClass() == s1
)
1160 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1161 else if (src
.regClass() == s2
)
1162 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1164 unreachable("wrong src register class for nir_op_imov");
1166 if (dst
.regClass() == v1
)
1167 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1168 else if (dst
.regClass() == v1b
||
1169 dst
.regClass() == v2b
||
1170 dst
.regClass() == v2
)
1171 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1173 unreachable("wrong src register class for nir_op_imov");
1178 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1179 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1180 assert(src
.regClass() == bld
.lm
);
1181 assert(dst
.regClass() == bld
.lm
);
1182 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1183 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1184 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1185 } else if (dst
.regClass() == v1
) {
1186 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1187 } else if (dst
.regClass() == v2
) {
1188 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1189 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1190 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1191 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1192 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1193 } else if (dst
.type() == RegType::sgpr
) {
1194 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1195 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1198 nir_print_instr(&instr
->instr
, stderr
);
1199 fprintf(stderr
, "\n");
1204 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1205 if (dst
.regClass() == v1
) {
1206 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1207 } else if (dst
.regClass() == s1
) {
1208 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1209 } else if (dst
.size() == 2) {
1210 Temp src0
= bld
.tmp(dst
.type(), 1);
1211 Temp src1
= bld
.tmp(dst
.type(), 1);
1212 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1214 if (dst
.regClass() == s2
) {
1215 Temp carry
= bld
.tmp(s1
);
1216 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1217 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1218 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1220 Temp lower
= bld
.tmp(v1
);
1221 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1222 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1223 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1226 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1227 nir_print_instr(&instr
->instr
, stderr
);
1228 fprintf(stderr
, "\n");
1233 if (dst
.regClass() == s1
) {
1234 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1235 } else if (dst
.regClass() == v1
) {
1236 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1237 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1239 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1240 nir_print_instr(&instr
->instr
, stderr
);
1241 fprintf(stderr
, "\n");
1245 case nir_op_isign
: {
1246 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1247 if (dst
.regClass() == s1
) {
1248 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1249 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1250 } else if (dst
.regClass() == s2
) {
1251 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1253 if (ctx
->program
->chip_class
>= GFX8
)
1254 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1256 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1257 /* SCC gets zero-extended to 64 bit */
1258 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1259 } else if (dst
.regClass() == v1
) {
1260 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1261 } else if (dst
.regClass() == v2
) {
1262 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1263 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1264 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1265 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1266 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1267 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1276 if (dst
.regClass() == v1
) {
1277 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1278 } else if (dst
.regClass() == s1
) {
1279 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1281 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1282 nir_print_instr(&instr
->instr
, stderr
);
1283 fprintf(stderr
, "\n");
1288 if (dst
.regClass() == v1
) {
1289 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1290 } else if (dst
.regClass() == s1
) {
1291 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1293 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1294 nir_print_instr(&instr
->instr
, stderr
);
1295 fprintf(stderr
, "\n");
1300 if (dst
.regClass() == v1
) {
1301 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1302 } else if (dst
.regClass() == s1
) {
1303 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1305 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1306 nir_print_instr(&instr
->instr
, stderr
);
1307 fprintf(stderr
, "\n");
1312 if (dst
.regClass() == v1
) {
1313 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1314 } else if (dst
.regClass() == s1
) {
1315 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1318 nir_print_instr(&instr
->instr
, stderr
);
1319 fprintf(stderr
, "\n");
1324 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1325 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1326 } else if (dst
.regClass() == v1
) {
1327 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1328 } else if (dst
.regClass() == v2
) {
1329 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1330 } else if (dst
.regClass() == s1
) {
1331 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1332 } else if (dst
.regClass() == s2
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1335 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1336 nir_print_instr(&instr
->instr
, stderr
);
1337 fprintf(stderr
, "\n");
1342 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1343 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1344 } else if (dst
.regClass() == v1
) {
1345 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1346 } else if (dst
.regClass() == v2
) {
1347 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1348 } else if (dst
.regClass() == s1
) {
1349 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1350 } else if (dst
.regClass() == s2
) {
1351 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1353 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1354 nir_print_instr(&instr
->instr
, stderr
);
1355 fprintf(stderr
, "\n");
1360 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1361 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1362 } else if (dst
.regClass() == v1
) {
1363 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1364 } else if (dst
.regClass() == v2
) {
1365 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1366 } else if (dst
.regClass() == s1
) {
1367 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1368 } else if (dst
.regClass() == s2
) {
1369 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1371 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1372 nir_print_instr(&instr
->instr
, stderr
);
1373 fprintf(stderr
, "\n");
1378 if (dst
.regClass() == v1
) {
1379 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1380 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1381 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1382 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1383 } else if (dst
.regClass() == v2
) {
1384 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1385 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1386 } else if (dst
.regClass() == s2
) {
1387 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1388 } else if (dst
.regClass() == s1
) {
1389 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1391 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1392 nir_print_instr(&instr
->instr
, stderr
);
1393 fprintf(stderr
, "\n");
1398 if (dst
.regClass() == v1
) {
1399 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1400 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1401 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1402 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1403 } else if (dst
.regClass() == v2
) {
1404 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1405 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1406 } else if (dst
.regClass() == s1
) {
1407 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1408 } else if (dst
.regClass() == s2
) {
1409 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1412 nir_print_instr(&instr
->instr
, stderr
);
1413 fprintf(stderr
, "\n");
1418 if (dst
.regClass() == v1
) {
1419 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1420 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1421 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1423 } else if (dst
.regClass() == v2
) {
1424 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1425 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1426 } else if (dst
.regClass() == s1
) {
1427 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1428 } else if (dst
.regClass() == s2
) {
1429 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1431 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1432 nir_print_instr(&instr
->instr
, stderr
);
1433 fprintf(stderr
, "\n");
1437 case nir_op_find_lsb
: {
1438 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1439 if (src
.regClass() == s1
) {
1440 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1441 } else if (src
.regClass() == v1
) {
1442 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1443 } else if (src
.regClass() == s2
) {
1444 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1446 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1447 nir_print_instr(&instr
->instr
, stderr
);
1448 fprintf(stderr
, "\n");
1452 case nir_op_ufind_msb
:
1453 case nir_op_ifind_msb
: {
1454 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1455 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1456 aco_opcode op
= src
.regClass() == s2
?
1457 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1458 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1459 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1461 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1462 Operand(src
.size() * 32u - 1u), msb_rev
);
1463 Temp msb
= sub
.def(0).getTemp();
1464 Temp carry
= sub
.def(1).getTemp();
1466 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1467 } else if (src
.regClass() == v1
) {
1468 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1469 Temp msb_rev
= bld
.tmp(v1
);
1470 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1471 Temp msb
= bld
.tmp(v1
);
1472 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1473 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1475 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1476 nir_print_instr(&instr
->instr
, stderr
);
1477 fprintf(stderr
, "\n");
1481 case nir_op_bitfield_reverse
: {
1482 if (dst
.regClass() == s1
) {
1483 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1484 } else if (dst
.regClass() == v1
) {
1485 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1487 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1488 nir_print_instr(&instr
->instr
, stderr
);
1489 fprintf(stderr
, "\n");
1494 if (dst
.regClass() == s1
) {
1495 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1499 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1500 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1501 if (dst
.regClass() == v1
) {
1502 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1506 assert(src0
.size() == 2 && src1
.size() == 2);
1507 Temp src00
= bld
.tmp(src0
.type(), 1);
1508 Temp src01
= bld
.tmp(dst
.type(), 1);
1509 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1510 Temp src10
= bld
.tmp(src1
.type(), 1);
1511 Temp src11
= bld
.tmp(dst
.type(), 1);
1512 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1514 if (dst
.regClass() == s2
) {
1515 Temp carry
= bld
.tmp(s1
);
1516 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1517 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1518 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1519 } else if (dst
.regClass() == v2
) {
1520 Temp dst0
= bld
.tmp(v1
);
1521 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1522 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1526 nir_print_instr(&instr
->instr
, stderr
);
1527 fprintf(stderr
, "\n");
1531 case nir_op_uadd_sat
: {
1532 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1533 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1534 if (dst
.regClass() == s1
) {
1535 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1536 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1538 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1539 } else if (dst
.regClass() == v1
) {
1540 if (ctx
->options
->chip_class
>= GFX9
) {
1541 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1542 add
->operands
[0] = Operand(src0
);
1543 add
->operands
[1] = Operand(src1
);
1544 add
->definitions
[0] = Definition(dst
);
1546 ctx
->block
->instructions
.emplace_back(std::move(add
));
1548 if (src1
.regClass() != v1
)
1549 std::swap(src0
, src1
);
1550 assert(src1
.regClass() == v1
);
1551 Temp tmp
= bld
.tmp(v1
);
1552 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1553 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1556 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1557 nir_print_instr(&instr
->instr
, stderr
);
1558 fprintf(stderr
, "\n");
1562 case nir_op_uadd_carry
: {
1563 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1564 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1565 if (dst
.regClass() == s1
) {
1566 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1569 if (dst
.regClass() == v1
) {
1570 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1571 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1575 Temp src00
= bld
.tmp(src0
.type(), 1);
1576 Temp src01
= bld
.tmp(dst
.type(), 1);
1577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1578 Temp src10
= bld
.tmp(src1
.type(), 1);
1579 Temp src11
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1581 if (dst
.regClass() == s2
) {
1582 Temp carry
= bld
.tmp(s1
);
1583 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1584 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1586 } else if (dst
.regClass() == v2
) {
1587 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1588 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1589 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1592 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1593 nir_print_instr(&instr
->instr
, stderr
);
1594 fprintf(stderr
, "\n");
1599 if (dst
.regClass() == s1
) {
1600 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1604 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1605 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1606 if (dst
.regClass() == v1
) {
1607 bld
.vsub32(Definition(dst
), src0
, src1
);
1611 Temp src00
= bld
.tmp(src0
.type(), 1);
1612 Temp src01
= bld
.tmp(dst
.type(), 1);
1613 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1614 Temp src10
= bld
.tmp(src1
.type(), 1);
1615 Temp src11
= bld
.tmp(dst
.type(), 1);
1616 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1617 if (dst
.regClass() == s2
) {
1618 Temp carry
= bld
.tmp(s1
);
1619 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1620 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1621 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1622 } else if (dst
.regClass() == v2
) {
1623 Temp lower
= bld
.tmp(v1
);
1624 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1625 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1626 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1628 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1629 nir_print_instr(&instr
->instr
, stderr
);
1630 fprintf(stderr
, "\n");
1634 case nir_op_usub_borrow
: {
1635 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1636 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1637 if (dst
.regClass() == s1
) {
1638 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1640 } else if (dst
.regClass() == v1
) {
1641 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1642 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1646 Temp src00
= bld
.tmp(src0
.type(), 1);
1647 Temp src01
= bld
.tmp(dst
.type(), 1);
1648 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1649 Temp src10
= bld
.tmp(src1
.type(), 1);
1650 Temp src11
= bld
.tmp(dst
.type(), 1);
1651 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1652 if (dst
.regClass() == s2
) {
1653 Temp borrow
= bld
.tmp(s1
);
1654 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1655 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1656 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1657 } else if (dst
.regClass() == v2
) {
1658 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1659 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1660 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1661 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1663 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1664 nir_print_instr(&instr
->instr
, stderr
);
1665 fprintf(stderr
, "\n");
1670 if (dst
.regClass() == v1
) {
1671 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1672 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1673 } else if (dst
.regClass() == s1
) {
1674 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1676 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1677 nir_print_instr(&instr
->instr
, stderr
);
1678 fprintf(stderr
, "\n");
1682 case nir_op_umul_high
: {
1683 if (dst
.regClass() == v1
) {
1684 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1685 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1686 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1687 } else if (dst
.regClass() == s1
) {
1688 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1689 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1690 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1692 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1693 nir_print_instr(&instr
->instr
, stderr
);
1694 fprintf(stderr
, "\n");
1698 case nir_op_imul_high
: {
1699 if (dst
.regClass() == v1
) {
1700 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1701 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1702 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1703 } else if (dst
.regClass() == s1
) {
1704 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1705 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1706 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1708 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1709 nir_print_instr(&instr
->instr
, stderr
);
1710 fprintf(stderr
, "\n");
1715 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1716 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1717 if (dst
.regClass() == v2b
) {
1718 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1719 } else if (dst
.regClass() == v1
) {
1720 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1721 } else if (dst
.regClass() == v2
) {
1722 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1724 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1725 nir_print_instr(&instr
->instr
, stderr
);
1726 fprintf(stderr
, "\n");
1731 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1732 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1733 if (dst
.regClass() == v2b
) {
1734 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1735 } else if (dst
.regClass() == v1
) {
1736 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1737 } else if (dst
.regClass() == v2
) {
1738 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1740 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1741 nir_print_instr(&instr
->instr
, stderr
);
1742 fprintf(stderr
, "\n");
1747 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1748 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1749 if (dst
.regClass() == v2b
) {
1750 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1751 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1753 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1754 } else if (dst
.regClass() == v1
) {
1755 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1756 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1758 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1759 } else if (dst
.regClass() == v2
) {
1760 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1761 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1762 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1765 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1766 nir_print_instr(&instr
->instr
, stderr
);
1767 fprintf(stderr
, "\n");
1772 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1773 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1774 if (dst
.regClass() == v2b
) {
1775 // TODO: check fp_mode.must_flush_denorms16_64
1776 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1777 } else if (dst
.regClass() == v1
) {
1778 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1779 } else if (dst
.regClass() == v2
) {
1780 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1781 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1782 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1784 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1794 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1795 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1796 if (dst
.regClass() == v2b
) {
1797 // TODO: check fp_mode.must_flush_denorms16_64
1798 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1799 } else if (dst
.regClass() == v1
) {
1800 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1801 } else if (dst
.regClass() == v2
) {
1802 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1803 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1804 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1806 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1809 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1810 nir_print_instr(&instr
->instr
, stderr
);
1811 fprintf(stderr
, "\n");
1815 case nir_op_fmax3
: {
1816 if (dst
.regClass() == v2b
) {
1817 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1818 } else if (dst
.regClass() == v1
) {
1819 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1821 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1822 nir_print_instr(&instr
->instr
, stderr
);
1823 fprintf(stderr
, "\n");
1827 case nir_op_fmin3
: {
1828 if (dst
.regClass() == v2b
) {
1829 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1830 } else if (dst
.regClass() == v1
) {
1831 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1833 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1834 nir_print_instr(&instr
->instr
, stderr
);
1835 fprintf(stderr
, "\n");
1839 case nir_op_fmed3
: {
1840 if (dst
.regClass() == v2b
) {
1841 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1842 } else if (dst
.regClass() == v1
) {
1843 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1845 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1846 nir_print_instr(&instr
->instr
, stderr
);
1847 fprintf(stderr
, "\n");
1851 case nir_op_umax3
: {
1852 if (dst
.size() == 1) {
1853 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1855 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1856 nir_print_instr(&instr
->instr
, stderr
);
1857 fprintf(stderr
, "\n");
1861 case nir_op_umin3
: {
1862 if (dst
.size() == 1) {
1863 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1865 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1866 nir_print_instr(&instr
->instr
, stderr
);
1867 fprintf(stderr
, "\n");
1871 case nir_op_umed3
: {
1872 if (dst
.size() == 1) {
1873 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1875 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1876 nir_print_instr(&instr
->instr
, stderr
);
1877 fprintf(stderr
, "\n");
1881 case nir_op_imax3
: {
1882 if (dst
.size() == 1) {
1883 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1885 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1886 nir_print_instr(&instr
->instr
, stderr
);
1887 fprintf(stderr
, "\n");
1891 case nir_op_imin3
: {
1892 if (dst
.size() == 1) {
1893 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1895 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1896 nir_print_instr(&instr
->instr
, stderr
);
1897 fprintf(stderr
, "\n");
1901 case nir_op_imed3
: {
1902 if (dst
.size() == 1) {
1903 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_cube_face_coord
: {
1912 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1913 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1914 emit_extract_vector(ctx
, in
, 1, v1
),
1915 emit_extract_vector(ctx
, in
, 2, v1
) };
1916 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1917 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1918 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1919 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1920 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1921 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1922 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1925 case nir_op_cube_face_index
: {
1926 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1927 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1928 emit_extract_vector(ctx
, in
, 1, v1
),
1929 emit_extract_vector(ctx
, in
, 2, v1
) };
1930 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1933 case nir_op_bcsel
: {
1934 emit_bcsel(ctx
, instr
, dst
);
1938 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1939 if (dst
.regClass() == v2b
) {
1940 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1941 } else if (dst
.regClass() == v1
) {
1942 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1943 } else if (dst
.regClass() == v2
) {
1944 /* Lowered at NIR level for precision reasons. */
1945 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1947 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1948 nir_print_instr(&instr
->instr
, stderr
);
1949 fprintf(stderr
, "\n");
1954 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1955 if (dst
.regClass() == v2b
) {
1956 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1957 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1958 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1959 } else if (dst
.regClass() == v1
) {
1960 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1961 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1962 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1963 } else if (dst
.regClass() == v2
) {
1964 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1965 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1966 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1967 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1968 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1971 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1972 nir_print_instr(&instr
->instr
, stderr
);
1973 fprintf(stderr
, "\n");
1978 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1979 if (dst
.regClass() == v2b
) {
1980 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1981 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1982 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1983 } else if (dst
.regClass() == v1
) {
1984 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1985 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1986 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1987 } else if (dst
.regClass() == v2
) {
1988 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1989 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1990 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1991 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1992 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1993 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1995 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1996 nir_print_instr(&instr
->instr
, stderr
);
1997 fprintf(stderr
, "\n");
2002 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2003 if (dst
.regClass() == v2b
) {
2004 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
2005 } else if (dst
.regClass() == v1
) {
2006 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2007 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
2008 // TODO: confirm that this holds under any circumstances
2009 } else if (dst
.regClass() == v2
) {
2010 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
2011 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
2014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2015 nir_print_instr(&instr
->instr
, stderr
);
2016 fprintf(stderr
, "\n");
2020 case nir_op_flog2
: {
2021 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2022 if (dst
.regClass() == v2b
) {
2023 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
2024 } else if (dst
.regClass() == v1
) {
2025 emit_log2(ctx
, bld
, Definition(dst
), src
);
2027 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2028 nir_print_instr(&instr
->instr
, stderr
);
2029 fprintf(stderr
, "\n");
2034 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2035 if (dst
.regClass() == v2b
) {
2036 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2037 } else if (dst
.regClass() == v1
) {
2038 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2039 } else if (dst
.regClass() == v2
) {
2040 /* Lowered at NIR level for precision reasons. */
2041 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2044 nir_print_instr(&instr
->instr
, stderr
);
2045 fprintf(stderr
, "\n");
2049 case nir_op_fexp2
: {
2050 if (dst
.regClass() == v2b
) {
2051 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2052 } else if (dst
.regClass() == v1
) {
2053 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2055 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2056 nir_print_instr(&instr
->instr
, stderr
);
2057 fprintf(stderr
, "\n");
2061 case nir_op_fsqrt
: {
2062 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2063 if (dst
.regClass() == v2b
) {
2064 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2065 } else if (dst
.regClass() == v1
) {
2066 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2067 } else if (dst
.regClass() == v2
) {
2068 /* Lowered at NIR level for precision reasons. */
2069 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2071 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2072 nir_print_instr(&instr
->instr
, stderr
);
2073 fprintf(stderr
, "\n");
2077 case nir_op_ffract
: {
2078 if (dst
.regClass() == v2b
) {
2079 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2080 } else if (dst
.regClass() == v1
) {
2081 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2082 } else if (dst
.regClass() == v2
) {
2083 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2085 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2086 nir_print_instr(&instr
->instr
, stderr
);
2087 fprintf(stderr
, "\n");
2091 case nir_op_ffloor
: {
2092 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2093 if (dst
.regClass() == v2b
) {
2094 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2095 } else if (dst
.regClass() == v1
) {
2096 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2097 } else if (dst
.regClass() == v2
) {
2098 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2100 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2101 nir_print_instr(&instr
->instr
, stderr
);
2102 fprintf(stderr
, "\n");
2106 case nir_op_fceil
: {
2107 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2108 if (dst
.regClass() == v2b
) {
2109 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2110 } else if (dst
.regClass() == v1
) {
2111 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2112 } else if (dst
.regClass() == v2
) {
2113 if (ctx
->options
->chip_class
>= GFX7
) {
2114 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2116 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2117 /* trunc = trunc(src0)
2118 * if (src0 > 0.0 && src0 != trunc)
2121 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2122 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2123 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2124 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2125 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2126 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2127 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2130 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2131 nir_print_instr(&instr
->instr
, stderr
);
2132 fprintf(stderr
, "\n");
2136 case nir_op_ftrunc
: {
2137 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2138 if (dst
.regClass() == v2b
) {
2139 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2140 } else if (dst
.regClass() == v1
) {
2141 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2142 } else if (dst
.regClass() == v2
) {
2143 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2145 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2146 nir_print_instr(&instr
->instr
, stderr
);
2147 fprintf(stderr
, "\n");
2151 case nir_op_fround_even
: {
2152 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2153 if (dst
.regClass() == v2b
) {
2154 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2155 } else if (dst
.regClass() == v1
) {
2156 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2157 } else if (dst
.regClass() == v2
) {
2158 if (ctx
->options
->chip_class
>= GFX7
) {
2159 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2161 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2162 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2163 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2165 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2166 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2167 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2168 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2169 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2170 tmp
= sub
->definitions
[0].getTemp();
2172 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2173 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2174 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2175 Temp cond
= vop3
->definitions
[0].getTemp();
2177 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2178 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2179 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2180 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2182 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2186 nir_print_instr(&instr
->instr
, stderr
);
2187 fprintf(stderr
, "\n");
2193 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2194 aco_ptr
<Instruction
> norm
;
2195 if (dst
.regClass() == v2b
) {
2196 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2197 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2198 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2199 bld
.vop1(opcode
, Definition(dst
), tmp
);
2200 } else if (dst
.regClass() == v1
) {
2201 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2202 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2204 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2205 if (ctx
->options
->chip_class
< GFX9
)
2206 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2208 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2209 bld
.vop1(opcode
, Definition(dst
), tmp
);
2211 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2212 nir_print_instr(&instr
->instr
, stderr
);
2213 fprintf(stderr
, "\n");
2217 case nir_op_ldexp
: {
2218 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2219 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2220 if (dst
.regClass() == v2b
) {
2221 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2222 } else if (dst
.regClass() == v1
) {
2223 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2224 } else if (dst
.regClass() == v2
) {
2225 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2227 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2228 nir_print_instr(&instr
->instr
, stderr
);
2229 fprintf(stderr
, "\n");
2233 case nir_op_frexp_sig
: {
2234 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2235 if (dst
.regClass() == v2b
) {
2236 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2237 } else if (dst
.regClass() == v1
) {
2238 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2239 } else if (dst
.regClass() == v2
) {
2240 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2242 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2243 nir_print_instr(&instr
->instr
, stderr
);
2244 fprintf(stderr
, "\n");
2248 case nir_op_frexp_exp
: {
2249 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2250 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2251 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2252 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2253 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2254 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2255 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2256 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2257 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2259 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2260 nir_print_instr(&instr
->instr
, stderr
);
2261 fprintf(stderr
, "\n");
2265 case nir_op_fsign
: {
2266 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2267 if (dst
.regClass() == v2b
) {
2268 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2269 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2270 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2271 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2272 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2273 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2274 } else if (dst
.regClass() == v1
) {
2275 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2276 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2277 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2278 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2279 } else if (dst
.regClass() == v2
) {
2280 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2281 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2282 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2284 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2285 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2286 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2288 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2290 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2291 nir_print_instr(&instr
->instr
, stderr
);
2292 fprintf(stderr
, "\n");
2297 case nir_op_f2f16_rtne
: {
2298 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2299 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2300 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2301 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2302 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2303 * keep value numbering and the scheduler simpler.
2305 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2307 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2310 case nir_op_f2f16_rtz
: {
2311 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2312 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2313 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2314 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2317 case nir_op_f2f32
: {
2318 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2319 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2320 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2321 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2323 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2324 nir_print_instr(&instr
->instr
, stderr
);
2325 fprintf(stderr
, "\n");
2329 case nir_op_f2f64
: {
2330 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2331 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2332 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2333 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2336 case nir_op_i2f16
: {
2337 assert(dst
.regClass() == v2b
);
2338 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2339 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2340 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2341 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2342 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2343 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2346 case nir_op_i2f32
: {
2347 assert(dst
.size() == 1);
2348 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2349 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2350 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2351 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2354 case nir_op_i2f64
: {
2355 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2356 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2357 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2358 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2359 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2360 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2361 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2362 RegClass rc
= RegClass(src
.type(), 1);
2363 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2364 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2365 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2366 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2367 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2368 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2371 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2372 nir_print_instr(&instr
->instr
, stderr
);
2373 fprintf(stderr
, "\n");
2377 case nir_op_u2f16
: {
2378 assert(dst
.regClass() == v2b
);
2379 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2380 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2381 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2382 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2383 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2384 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2387 case nir_op_u2f32
: {
2388 assert(dst
.size() == 1);
2389 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2390 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2391 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2393 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2394 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2395 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2399 case nir_op_u2f64
: {
2400 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2401 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2402 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2403 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2404 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2405 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2406 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2407 RegClass rc
= RegClass(src
.type(), 1);
2408 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2409 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2410 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2411 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2412 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2413 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2415 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2416 nir_print_instr(&instr
->instr
, stderr
);
2417 fprintf(stderr
, "\n");
2422 case nir_op_f2i16
: {
2423 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2424 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2425 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2426 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2428 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2432 case nir_op_f2u16
: {
2433 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2434 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2435 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2436 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2438 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2441 case nir_op_f2i32
: {
2442 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2443 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2444 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2445 if (dst
.type() == RegType::vgpr
) {
2446 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2448 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2449 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2451 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2452 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2453 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2454 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2456 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2457 nir_print_instr(&instr
->instr
, stderr
);
2458 fprintf(stderr
, "\n");
2462 case nir_op_f2u32
: {
2463 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2464 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2465 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2466 if (dst
.type() == RegType::vgpr
) {
2467 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2469 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2470 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2472 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2473 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2474 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2475 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2478 nir_print_instr(&instr
->instr
, stderr
);
2479 fprintf(stderr
, "\n");
2483 case nir_op_f2i64
: {
2484 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2485 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2486 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2488 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2489 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2490 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2491 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2492 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2493 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2494 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2495 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2496 Temp new_exponent
= bld
.tmp(v1
);
2497 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2498 if (ctx
->program
->chip_class
>= GFX8
)
2499 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2501 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2502 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2503 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2504 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2505 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2506 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2507 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2508 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2509 Temp new_lower
= bld
.tmp(v1
);
2510 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2511 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2512 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2514 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2515 if (src
.type() == RegType::vgpr
)
2516 src
= bld
.as_uniform(src
);
2517 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2518 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2519 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2520 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2521 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2522 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2523 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2524 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2525 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2526 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2527 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2528 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2529 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2530 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2531 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2532 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2533 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2534 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2535 Temp borrow
= bld
.tmp(s1
);
2536 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2537 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2538 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2540 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2541 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2542 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2543 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2544 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2545 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2546 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2547 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2548 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2549 if (dst
.type() == RegType::sgpr
) {
2550 lower
= bld
.as_uniform(lower
);
2551 upper
= bld
.as_uniform(upper
);
2553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2556 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2557 nir_print_instr(&instr
->instr
, stderr
);
2558 fprintf(stderr
, "\n");
2562 case nir_op_f2u64
: {
2563 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2564 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2565 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2567 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2568 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2569 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2570 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2571 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2572 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2573 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2574 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2575 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2576 Temp new_exponent
= bld
.tmp(v1
);
2577 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2578 if (ctx
->program
->chip_class
>= GFX8
)
2579 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2581 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2582 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2584 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2585 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2586 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2587 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2590 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2591 if (src
.type() == RegType::vgpr
)
2592 src
= bld
.as_uniform(src
);
2593 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2594 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2595 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2596 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2597 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2598 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2599 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2600 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2601 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2602 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2603 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2604 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2605 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2607 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2608 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2609 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2610 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2612 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2613 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2614 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2615 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2616 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2617 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2618 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2619 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2620 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2621 if (dst
.type() == RegType::sgpr
) {
2622 lower
= bld
.as_uniform(lower
);
2623 upper
= bld
.as_uniform(upper
);
2625 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2628 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2629 nir_print_instr(&instr
->instr
, stderr
);
2630 fprintf(stderr
, "\n");
2634 case nir_op_b2f16
: {
2635 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2636 assert(src
.regClass() == bld
.lm
);
2638 if (dst
.regClass() == s1
) {
2639 src
= bool_to_scalar_condition(ctx
, src
);
2640 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2641 } else if (dst
.regClass() == v2b
) {
2642 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2643 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2645 unreachable("Wrong destination register class for nir_op_b2f16.");
2649 case nir_op_b2f32
: {
2650 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2651 assert(src
.regClass() == bld
.lm
);
2653 if (dst
.regClass() == s1
) {
2654 src
= bool_to_scalar_condition(ctx
, src
);
2655 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2656 } else if (dst
.regClass() == v1
) {
2657 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2659 unreachable("Wrong destination register class for nir_op_b2f32.");
2663 case nir_op_b2f64
: {
2664 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2665 assert(src
.regClass() == bld
.lm
);
2667 if (dst
.regClass() == s2
) {
2668 src
= bool_to_scalar_condition(ctx
, src
);
2669 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2670 } else if (dst
.regClass() == v2
) {
2671 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2672 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2673 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2675 unreachable("Wrong destination register class for nir_op_b2f64.");
2682 case nir_op_i2i64
: {
2683 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2684 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2690 case nir_op_u2u64
: {
2691 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2692 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2699 case nir_op_b2i64
: {
2700 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2701 assert(src
.regClass() == bld
.lm
);
2703 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2704 if (tmp
.regClass() == s1
) {
2705 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2706 bool_to_scalar_condition(ctx
, src
, tmp
);
2707 } else if (tmp
.type() == RegType::vgpr
) {
2708 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2710 unreachable("Invalid register class for b2i32");
2714 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2719 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2720 assert(dst
.regClass() == bld
.lm
);
2722 if (src
.type() == RegType::vgpr
) {
2723 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2724 assert(dst
.regClass() == bld
.lm
);
2725 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2726 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2728 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2730 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2731 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2733 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2734 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2736 bool_to_vector_condition(ctx
, tmp
, dst
);
2740 case nir_op_pack_64_2x32_split
: {
2741 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2742 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2744 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2747 case nir_op_unpack_64_2x32_split_x
:
2748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2750 case nir_op_unpack_64_2x32_split_y
:
2751 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2753 case nir_op_unpack_32_2x16_split_x
:
2754 if (dst
.type() == RegType::vgpr
) {
2755 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2757 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2760 case nir_op_unpack_32_2x16_split_y
:
2761 if (dst
.type() == RegType::vgpr
) {
2762 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2764 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2767 case nir_op_pack_32_2x16_split
: {
2768 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2769 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2770 if (dst
.regClass() == v1
) {
2771 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2772 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2773 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2775 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2776 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2777 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2781 case nir_op_pack_half_2x16
: {
2782 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2784 if (dst
.regClass() == v1
) {
2785 Temp src0
= bld
.tmp(v1
);
2786 Temp src1
= bld
.tmp(v1
);
2787 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2788 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2789 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2791 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2792 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2793 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2796 nir_print_instr(&instr
->instr
, stderr
);
2797 fprintf(stderr
, "\n");
2801 case nir_op_unpack_half_2x16_split_x
: {
2802 if (dst
.regClass() == v1
) {
2803 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2805 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2806 nir_print_instr(&instr
->instr
, stderr
);
2807 fprintf(stderr
, "\n");
2811 case nir_op_unpack_half_2x16_split_y
: {
2812 if (dst
.regClass() == v1
) {
2813 /* TODO: use SDWA here */
2814 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2815 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2817 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2818 nir_print_instr(&instr
->instr
, stderr
);
2819 fprintf(stderr
, "\n");
2823 case nir_op_fquantize2f16
: {
2824 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2825 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2828 if (ctx
->program
->chip_class
>= GFX8
) {
2829 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2830 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2831 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2833 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2834 * so compare the result and flush to 0 if it's smaller.
2836 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2837 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2838 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2839 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2840 cmp_res
= vop3
->definitions
[0].getTemp();
2843 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2844 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2845 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2847 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2852 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2853 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2855 if (dst
.regClass() == s1
) {
2856 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2857 } else if (dst
.regClass() == v1
) {
2858 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2860 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2861 nir_print_instr(&instr
->instr
, stderr
);
2862 fprintf(stderr
, "\n");
2866 case nir_op_bitfield_select
: {
2867 /* (mask & insert) | (~mask & base) */
2868 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2869 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2870 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2872 /* dst = (insert & bitmask) | (base & ~bitmask) */
2873 if (dst
.regClass() == s1
) {
2874 aco_ptr
<Instruction
> sop2
;
2875 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2876 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2878 if (const_insert
&& const_bitmask
) {
2879 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2881 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2882 lhs
= Operand(insert
);
2886 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2887 if (const_base
&& const_bitmask
) {
2888 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2890 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2891 rhs
= Operand(base
);
2894 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2896 } else if (dst
.regClass() == v1
) {
2897 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2898 base
= as_vgpr(ctx
, base
);
2899 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2900 insert
= as_vgpr(ctx
, insert
);
2902 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2906 nir_print_instr(&instr
->instr
, stderr
);
2907 fprintf(stderr
, "\n");
2913 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2914 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2915 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2917 if (dst
.type() == RegType::sgpr
) {
2919 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2920 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2921 if (const_offset
&& const_bits
) {
2922 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2923 extract
= Operand(const_extract
);
2927 width
= Operand(const_bits
->u32
<< 16);
2929 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2931 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2935 if (dst
.regClass() == s1
) {
2936 if (instr
->op
== nir_op_ubfe
)
2937 opcode
= aco_opcode::s_bfe_u32
;
2939 opcode
= aco_opcode::s_bfe_i32
;
2940 } else if (dst
.regClass() == s2
) {
2941 if (instr
->op
== nir_op_ubfe
)
2942 opcode
= aco_opcode::s_bfe_u64
;
2944 opcode
= aco_opcode::s_bfe_i64
;
2946 unreachable("Unsupported BFE bit size");
2949 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2953 if (dst
.regClass() == v1
) {
2954 if (instr
->op
== nir_op_ubfe
)
2955 opcode
= aco_opcode::v_bfe_u32
;
2957 opcode
= aco_opcode::v_bfe_i32
;
2959 unreachable("Unsupported BFE bit size");
2962 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2966 case nir_op_bit_count
: {
2967 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2968 if (src
.regClass() == s1
) {
2969 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2970 } else if (src
.regClass() == v1
) {
2971 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2972 } else if (src
.regClass() == v2
) {
2973 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2974 emit_extract_vector(ctx
, src
, 1, v1
),
2975 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2976 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2977 } else if (src
.regClass() == s2
) {
2978 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2980 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2981 nir_print_instr(&instr
->instr
, stderr
);
2982 fprintf(stderr
, "\n");
2987 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2991 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2995 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2999 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3003 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3007 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3011 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3012 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3014 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3015 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3019 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3020 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3022 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3023 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3027 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3031 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3036 case nir_op_fddx_fine
:
3037 case nir_op_fddy_fine
:
3038 case nir_op_fddx_coarse
:
3039 case nir_op_fddy_coarse
: {
3040 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3041 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3042 if (instr
->op
== nir_op_fddx_fine
) {
3043 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3044 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3045 } else if (instr
->op
== nir_op_fddy_fine
) {
3046 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3047 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3049 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3050 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3051 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3053 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3057 if (ctx
->program
->chip_class
>= GFX8
) {
3058 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3059 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3061 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3062 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3063 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3065 emit_wqm(ctx
, tmp
, dst
, true);
3069 fprintf(stderr
, "Unknown NIR ALU instr: ");
3070 nir_print_instr(&instr
->instr
, stderr
);
3071 fprintf(stderr
, "\n");
3075 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3077 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3079 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3080 // which get truncated the lsb if double and msb if int
3081 // for now, we only use s_mov_b64 with 64bit inline constants
3082 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3083 assert(dst
.type() == RegType::sgpr
);
3085 Builder
bld(ctx
->program
, ctx
->block
);
3087 if (instr
->def
.bit_size
== 1) {
3088 assert(dst
.regClass() == bld
.lm
);
3089 int val
= instr
->value
[0].b
? -1 : 0;
3090 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3091 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3092 } else if (instr
->def
.bit_size
== 8) {
3093 /* ensure that the value is correctly represented in the low byte of the register */
3094 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3095 } else if (instr
->def
.bit_size
== 16) {
3096 /* ensure that the value is correctly represented in the low half of the register */
3097 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3098 } else if (dst
.size() == 1) {
3099 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3101 assert(dst
.size() != 1);
3102 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3103 if (instr
->def
.bit_size
== 64)
3104 for (unsigned i
= 0; i
< dst
.size(); i
++)
3105 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3107 for (unsigned i
= 0; i
< dst
.size(); i
++)
3108 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3110 vec
->definitions
[0] = Definition(dst
);
3111 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3115 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3117 uint32_t new_mask
= 0;
3118 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3119 if (mask
& (1u << i
))
3120 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3124 struct LoadEmitInfo
{
3127 unsigned num_components
;
3128 unsigned component_size
;
3129 Temp resource
= Temp(0, s1
);
3130 unsigned component_stride
= 0;
3131 unsigned const_offset
= 0;
3132 unsigned align_mul
= 0;
3133 unsigned align_offset
= 0;
3136 unsigned swizzle_component_size
= 0;
3137 barrier_interaction barrier
= barrier_none
;
3138 bool can_reorder
= true;
3139 Temp soffset
= Temp(0, s1
);
3142 using LoadCallback
= Temp(*)(
3143 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3144 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3146 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3147 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3149 unsigned load_size
= info
->num_components
* info
->component_size
;
3150 unsigned component_size
= info
->component_size
;
3152 unsigned num_vals
= 0;
3153 Temp vals
[info
->dst
.bytes()];
3155 unsigned const_offset
= info
->const_offset
;
3157 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3158 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3160 unsigned bytes_read
= 0;
3161 while (bytes_read
< load_size
) {
3162 unsigned bytes_needed
= load_size
- bytes_read
;
3164 /* add buffer for unaligned loads */
3165 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3168 if ((bytes_needed
> 2 ||
3169 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3170 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3171 if (info
->component_stride
) {
3172 assert(supports_8bit_16bit_loads
&& "unimplemented");
3176 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3177 bytes_needed
= align(bytes_needed
, 4);
3184 if (info
->swizzle_component_size
)
3185 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3186 if (info
->component_stride
)
3187 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3189 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3191 /* reduce constant offset */
3192 Operand offset
= info
->offset
;
3193 unsigned reduced_const_offset
= const_offset
;
3194 bool remove_const_offset_completely
= need_to_align_offset
;
3195 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3196 unsigned to_add
= const_offset
;
3197 if (remove_const_offset_completely
) {
3198 reduced_const_offset
= 0;
3200 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3201 reduced_const_offset
%= max_const_offset_plus_one
;
3203 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3204 if (offset
.isConstant()) {
3205 offset
= Operand(offset
.constantValue() + to_add
);
3206 } else if (offset_tmp
.regClass() == s1
) {
3207 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3208 offset_tmp
, Operand(to_add
));
3209 } else if (offset_tmp
.regClass() == v1
) {
3210 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3212 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3213 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3214 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3216 if (offset_tmp
.regClass() == s2
) {
3217 Temp carry
= bld
.tmp(s1
);
3218 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3219 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3220 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3222 Temp new_lo
= bld
.tmp(v1
);
3223 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3224 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3225 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3230 /* align offset down if needed */
3231 Operand aligned_offset
= offset
;
3232 if (need_to_align_offset
) {
3233 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3234 if (offset
.isConstant()) {
3235 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3236 } else if (offset_tmp
.regClass() == s1
) {
3237 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3238 } else if (offset_tmp
.regClass() == s2
) {
3239 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3240 } else if (offset_tmp
.regClass() == v1
) {
3241 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3242 } else if (offset_tmp
.regClass() == v2
) {
3243 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3244 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3245 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3246 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3249 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3250 bld
.copy(bld
.def(s1
), aligned_offset
);
3252 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3253 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3254 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3256 /* the callback wrote directly to dst */
3257 if (val
== info
->dst
) {
3258 assert(num_vals
== 0);
3259 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3263 /* shift result right if needed */
3264 if (info
->component_size
< 4 && byte_align_loads
) {
3265 Operand
align((uint32_t)byte_align
);
3266 if (byte_align
== -1) {
3267 if (offset
.isConstant())
3268 align
= Operand(offset
.constantValue() % 4u);
3269 else if (offset
.size() == 2)
3270 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3275 assert(val
.bytes() >= load_size
&& "unimplemented");
3276 if (val
.type() == RegType::sgpr
)
3277 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3279 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3283 /* add result to list and advance */
3284 if (info
->component_stride
) {
3285 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3286 const_offset
+= info
->component_stride
;
3287 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3289 const_offset
+= val
.bytes();
3290 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3292 bytes_read
+= val
.bytes();
3293 vals
[num_vals
++] = val
;
3296 /* create array of components */
3297 unsigned components_split
= 0;
3298 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3299 bool has_vgprs
= false;
3300 for (unsigned i
= 0; i
< num_vals
;) {
3302 unsigned num_tmps
= 0;
3303 unsigned tmp_size
= 0;
3304 RegType reg_type
= RegType::sgpr
;
3305 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3306 if (vals
[i
].type() == RegType::vgpr
)
3307 reg_type
= RegType::vgpr
;
3308 tmp_size
+= vals
[i
].bytes();
3309 tmp
[num_tmps
++] = vals
[i
++];
3312 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3313 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3314 for (unsigned i
= 0; i
< num_vals
; i
++)
3315 vec
->operands
[i
] = Operand(tmp
[i
]);
3316 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3317 vec
->definitions
[0] = Definition(tmp
[0]);
3318 bld
.insert(std::move(vec
));
3321 if (tmp
[0].bytes() % component_size
) {
3323 assert(i
== num_vals
);
3324 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3325 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3328 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3330 unsigned start
= components_split
;
3332 if (tmp_size
== elem_rc
.bytes()) {
3333 allocated_vec
[components_split
++] = tmp
[0];
3335 assert(tmp_size
% elem_rc
.bytes() == 0);
3336 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3337 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3338 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3339 Temp component
= bld
.tmp(elem_rc
);
3340 allocated_vec
[components_split
++] = component
;
3341 split
->definitions
[i
] = Definition(component
);
3343 split
->operands
[0] = Operand(tmp
[0]);
3344 bld
.insert(std::move(split
));
3347 /* try to p_as_uniform early so we can create more optimizable code and
3348 * also update allocated_vec */
3349 for (unsigned j
= start
; j
< components_split
; j
++) {
3350 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3351 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3352 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3356 /* concatenate components and p_as_uniform() result if needed */
3357 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3358 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3360 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3362 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3363 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3364 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3365 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3367 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3368 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3369 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3370 vec
->definitions
[0] = Definition(tmp
);
3371 bld
.insert(std::move(vec
));
3372 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3374 vec
->definitions
[0] = Definition(info
->dst
);
3375 bld
.insert(std::move(vec
));
3379 Operand
load_lds_size_m0(Builder
& bld
)
3381 /* TODO: m0 does not need to be initialized on GFX9+ */
3382 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3385 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3386 Temp offset
, unsigned bytes_needed
,
3387 unsigned align
, unsigned const_offset
,
3390 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3392 Operand m
= load_lds_size_m0(bld
);
3394 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3395 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3400 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3401 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3403 op
= aco_opcode::ds_read_b128
;
3404 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3407 op
= aco_opcode::ds_read2_b64
;
3408 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3410 op
= aco_opcode::ds_read_b96
;
3411 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3413 op
= aco_opcode::ds_read_b64
;
3414 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3417 op
= aco_opcode::ds_read2_b32
;
3418 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3420 op
= aco_opcode::ds_read_b32
;
3421 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3423 op
= aco_opcode::ds_read_u16
;
3426 op
= aco_opcode::ds_read_u8
;
3429 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3430 if (const_offset
>= max_offset_plus_one
) {
3431 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3432 const_offset
%= max_offset_plus_one
;
3436 const_offset
/= (size
/ 2u);
3438 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3439 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3441 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3443 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3446 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3451 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3453 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3454 Temp offset
, unsigned bytes_needed
,
3455 unsigned align
, unsigned const_offset
,
3460 if (bytes_needed
<= 4) {
3462 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3463 } else if (bytes_needed
<= 8) {
3465 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3466 } else if (bytes_needed
<= 16) {
3468 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3469 } else if (bytes_needed
<= 32) {
3471 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3474 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3476 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3477 if (info
->resource
.id()) {
3478 load
->operands
[0] = Operand(info
->resource
);
3479 load
->operands
[1] = Operand(offset
);
3481 load
->operands
[0] = Operand(offset
);
3482 load
->operands
[1] = Operand(0u);
3484 RegClass
rc(RegType::sgpr
, size
);
3485 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3486 load
->definitions
[0] = Definition(val
);
3487 load
->glc
= info
->glc
;
3488 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3489 load
->barrier
= info
->barrier
;
3490 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3491 bld
.insert(std::move(load
));
3495 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3497 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3498 Temp offset
, unsigned bytes_needed
,
3499 unsigned align_
, unsigned const_offset
,
3502 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3503 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3505 if (info
->soffset
.id()) {
3506 if (soffset
.isTemp())
3507 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3508 soffset
= Operand(info
->soffset
);
3511 unsigned bytes_size
= 0;
3513 if (bytes_needed
== 1) {
3515 op
= aco_opcode::buffer_load_ubyte
;
3516 } else if (bytes_needed
== 2) {
3518 op
= aco_opcode::buffer_load_ushort
;
3519 } else if (bytes_needed
<= 4) {
3521 op
= aco_opcode::buffer_load_dword
;
3522 } else if (bytes_needed
<= 8) {
3524 op
= aco_opcode::buffer_load_dwordx2
;
3525 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3527 op
= aco_opcode::buffer_load_dwordx3
;
3530 op
= aco_opcode::buffer_load_dwordx4
;
3532 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3533 mubuf
->operands
[0] = Operand(info
->resource
);
3534 mubuf
->operands
[1] = vaddr
;
3535 mubuf
->operands
[2] = soffset
;
3536 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3537 mubuf
->glc
= info
->glc
;
3538 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3539 mubuf
->barrier
= info
->barrier
;
3540 mubuf
->can_reorder
= info
->can_reorder
;
3541 mubuf
->offset
= const_offset
;
3542 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3543 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3544 mubuf
->definitions
[0] = Definition(val
);
3545 bld
.insert(std::move(mubuf
));
3550 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3552 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3554 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3555 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3557 if (addr
.type() == RegType::vgpr
)
3558 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3559 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3562 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3563 Temp offset
, unsigned bytes_needed
,
3564 unsigned align_
, unsigned const_offset
,
3567 unsigned bytes_size
= 0;
3568 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3569 bool global
= bld
.program
->chip_class
>= GFX9
;
3571 if (bytes_needed
== 1) {
3573 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3574 } else if (bytes_needed
== 2) {
3576 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3577 } else if (bytes_needed
<= 4) {
3579 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3580 } else if (bytes_needed
<= 8) {
3582 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3583 } else if (bytes_needed
<= 12 && !mubuf
) {
3585 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3588 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3590 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3591 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3593 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3594 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3595 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3596 mubuf
->operands
[2] = Operand(0u);
3597 mubuf
->glc
= info
->glc
;
3600 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3601 mubuf
->disable_wqm
= false;
3602 mubuf
->barrier
= info
->barrier
;
3603 mubuf
->definitions
[0] = Definition(val
);
3604 bld
.insert(std::move(mubuf
));
3606 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3608 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3609 flat
->operands
[0] = Operand(offset
);
3610 flat
->operands
[1] = Operand(s1
);
3611 flat
->glc
= info
->glc
;
3612 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3613 flat
->barrier
= info
->barrier
;
3615 flat
->definitions
[0] = Definition(val
);
3616 bld
.insert(std::move(flat
));
3622 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3624 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3625 Temp address
, unsigned base_offset
, unsigned align
)
3627 assert(util_is_power_of_two_nonzero(align
));
3629 Builder
bld(ctx
->program
, ctx
->block
);
3631 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3632 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3633 info
.align_mul
= align
;
3634 info
.align_offset
= 0;
3635 info
.barrier
= barrier_shared
;
3636 info
.can_reorder
= false;
3637 info
.const_offset
= base_offset
;
3638 emit_lds_load(ctx
, bld
, &info
);
3643 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3648 Builder
bld(ctx
->program
, ctx
->block
);
3650 ASSERTED
bool is_subdword
= false;
3651 for (unsigned i
= 0; i
< count
; i
++)
3652 is_subdword
|= offsets
[i
] % 4;
3653 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3654 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3656 /* count == 1 fast path */
3658 if (dst_type
== RegType::sgpr
)
3659 dst
[0] = bld
.as_uniform(src
);
3661 dst
[0] = as_vgpr(ctx
, src
);
3665 for (unsigned i
= 0; i
< count
- 1; i
++)
3666 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3667 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3669 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3670 src
= as_vgpr(ctx
, src
);
3672 /* use allocated_vec if possible */
3673 auto it
= ctx
->allocated_vec
.find(src
.id());
3674 if (it
!= ctx
->allocated_vec
.end()) {
3675 unsigned total_size
= 0;
3676 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3677 total_size
+= it
->second
[i
].bytes();
3678 if (total_size
!= src
.bytes())
3681 unsigned elem_size
= it
->second
[0].bytes();
3683 for (unsigned i
= 0; i
< count
; i
++) {
3684 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3688 for (unsigned i
= 0; i
< count
; i
++) {
3689 unsigned start_idx
= offsets
[i
] / elem_size
;
3690 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3691 if (op_count
== 1) {
3692 if (dst_type
== RegType::sgpr
)
3693 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3695 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3699 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3700 for (unsigned j
= 0; j
< op_count
; j
++) {
3701 Temp tmp
= it
->second
[start_idx
+ j
];
3702 if (dst_type
== RegType::sgpr
)
3703 tmp
= bld
.as_uniform(tmp
);
3704 vec
->operands
[j
] = Operand(tmp
);
3706 vec
->definitions
[0] = Definition(dst
[i
]);
3707 bld
.insert(std::move(vec
));
3713 if (dst_type
== RegType::sgpr
)
3714 src
= bld
.as_uniform(src
);
3718 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3719 split
->operands
[0] = Operand(src
);
3720 for (unsigned i
= 0; i
< count
; i
++)
3721 split
->definitions
[i
] = Definition(dst
[i
]);
3722 bld
.insert(std::move(split
));
3725 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3726 int *start
, int *count
)
3728 unsigned start_elem
= ffs(todo_mask
) - 1;
3729 bool skip
= !(mask
& (1 << start_elem
));
3731 mask
= ~mask
& todo_mask
;
3735 u_bit_scan_consecutive_range(&mask
, start
, count
);
3740 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3742 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3745 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3746 Temp address
, unsigned base_offset
, unsigned align
)
3748 assert(util_is_power_of_two_nonzero(align
));
3749 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3751 Builder
bld(ctx
->program
, ctx
->block
);
3752 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3753 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3755 unsigned write_count
= 0;
3756 Temp write_datas
[32];
3757 unsigned offsets
[32];
3758 aco_opcode opcodes
[32];
3760 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3762 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3765 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3766 offsets
[write_count
] = offset
;
3767 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3769 advance_write_mask(&todo
, offset
, bytes
);
3773 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3774 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3775 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3776 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3778 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3779 aco_opcode op
= aco_opcode::num_opcodes
;
3780 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3781 op
= aco_opcode::ds_write_b128
;
3783 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3784 op
= aco_opcode::ds_write_b96
;
3786 } else if (bytes
>= 8 && aligned8
) {
3787 op
= aco_opcode::ds_write_b64
;
3789 } else if (bytes
>= 4 && aligned4
) {
3790 op
= aco_opcode::ds_write_b32
;
3792 } else if (bytes
>= 2 && aligned2
) {
3793 op
= aco_opcode::ds_write_b16
;
3795 } else if (bytes
>= 1) {
3796 op
= aco_opcode::ds_write_b8
;
3802 offsets
[write_count
] = offset
;
3803 opcodes
[write_count
] = op
;
3805 advance_write_mask(&todo
, offset
, bytes
);
3808 Operand m
= load_lds_size_m0(bld
);
3810 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3812 for (unsigned i
= 0; i
< write_count
; i
++) {
3813 aco_opcode op
= opcodes
[i
];
3814 if (op
== aco_opcode::num_opcodes
)
3817 Temp data
= write_datas
[i
];
3819 unsigned second
= write_count
;
3820 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3821 for (second
= i
+ 1; second
< write_count
; second
++) {
3822 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3823 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3824 opcodes
[second
] = aco_opcode::num_opcodes
;
3830 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3831 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3833 unsigned inline_offset
= base_offset
+ offsets
[i
];
3834 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3835 Temp address_offset
= address
;
3836 if (inline_offset
> max_offset
) {
3837 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3838 inline_offset
= offsets
[i
];
3840 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3843 Temp second_data
= write_datas
[second
];
3844 inline_offset
/= data
.bytes();
3845 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3847 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3852 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3854 unsigned align
= 16;
3856 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3862 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3867 return aco_opcode::buffer_store_byte
;
3870 return aco_opcode::buffer_store_short
;
3872 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3874 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3877 return aco_opcode::buffer_store_dwordx3
;
3879 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3881 unreachable("Unexpected store size");
3882 return aco_opcode::num_opcodes
;
3885 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3886 Temp data
, unsigned writemask
, int swizzle_element_size
,
3887 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3889 unsigned write_count_with_skips
= 0;
3892 /* determine how to split the data */
3893 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3896 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3897 offsets
[write_count_with_skips
] = offset
;
3898 if (skips
[write_count_with_skips
]) {
3899 advance_write_mask(&todo
, offset
, bytes
);
3900 write_count_with_skips
++;
3904 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3905 * larger than swizzle_element_size */
3906 bytes
= MIN2(bytes
, swizzle_element_size
);
3908 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3910 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3911 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3914 /* dword or larger stores have to be dword-aligned */
3915 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3916 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3917 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3919 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3921 advance_write_mask(&todo
, offset
, bytes
);
3922 write_count_with_skips
++;
3925 /* actually split data */
3926 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3929 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3932 write_datas
[*write_count
] = write_datas
[i
];
3933 offsets
[*write_count
] = offsets
[i
];
3938 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3939 unsigned split_cnt
= 0u, Temp dst
= Temp())
3941 Builder
bld(ctx
->program
, ctx
->block
);
3942 unsigned dword_size
= elem_size_bytes
/ 4;
3945 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3947 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3948 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3949 instr
->definitions
[0] = Definition(dst
);
3951 for (unsigned i
= 0; i
< cnt
; ++i
) {
3953 assert(arr
[i
].size() == dword_size
);
3954 allocated_vec
[i
] = arr
[i
];
3955 instr
->operands
[i
] = Operand(arr
[i
]);
3957 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3958 allocated_vec
[i
] = zero
;
3959 instr
->operands
[i
] = Operand(zero
);
3963 bld
.insert(std::move(instr
));
3966 emit_split_vector(ctx
, dst
, split_cnt
);
3968 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3973 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3975 if (const_offset
>= 4096) {
3976 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3977 const_offset
%= 4096u;
3980 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3981 else if (unlikely(voffset
.regClass() == s1
))
3982 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3983 else if (likely(voffset
.regClass() == v1
))
3984 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3986 unreachable("Unsupported register class of voffset");
3989 return const_offset
;
3992 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3993 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3996 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3997 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3999 Builder
bld(ctx
->program
, ctx
->block
);
4000 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
4001 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
4003 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
4004 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
4005 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
4006 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
4007 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
4009 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
4012 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
4013 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
4014 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
4016 Builder
bld(ctx
->program
, ctx
->block
);
4017 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4019 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
4021 unsigned write_count
= 0;
4022 Temp write_datas
[32];
4023 unsigned offsets
[32];
4024 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
4025 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4027 for (unsigned i
= 0; i
< write_count
; i
++) {
4028 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4029 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
4033 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4034 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4035 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4037 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4038 assert((num_components
* elem_size_bytes
) == dst
.bytes());
4039 assert(!!stride
!= allow_combining
);
4041 Builder
bld(ctx
->program
, ctx
->block
);
4043 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4044 info
.component_stride
= allow_combining
? 0 : stride
;
4046 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4047 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4048 info
.align_offset
= 0;
4049 info
.soffset
= soffset
;
4050 info
.const_offset
= base_const_offset
;
4051 emit_mubuf_load(ctx
, bld
, &info
);
4054 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4056 Builder
bld(ctx
->program
, ctx
->block
);
4057 Temp offset
= base_offset
.first
;
4058 unsigned const_offset
= base_offset
.second
;
4060 if (!nir_src_is_const(*off_src
)) {
4061 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4064 /* Calculate indirect offset with stride */
4065 if (likely(indirect_offset_arg
.regClass() == v1
))
4066 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4067 else if (indirect_offset_arg
.regClass() == s1
)
4068 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4070 unreachable("Unsupported register class of indirect offset");
4072 /* Add to the supplied base offset */
4073 if (offset
.id() == 0)
4074 offset
= with_stride
;
4075 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4076 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4077 else if (offset
.size() == 1 && with_stride
.size() == 1)
4078 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4080 unreachable("Unsupported register class of indirect offset");
4082 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4083 const_offset
+= const_offset_arg
* stride
;
4086 return std::make_pair(offset
, const_offset
);
4089 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4091 Builder
bld(ctx
->program
, ctx
->block
);
4094 if (off1
.first
.id() && off2
.first
.id()) {
4095 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4096 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4097 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4098 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4100 unreachable("Unsupported register class of indirect offset");
4102 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4105 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4108 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4110 Builder
bld(ctx
->program
, ctx
->block
);
4111 unsigned const_offset
= offs
.second
* multiplier
;
4113 if (!offs
.first
.id())
4114 return std::make_pair(offs
.first
, const_offset
);
4116 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4117 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4118 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4120 return std::make_pair(offset
, const_offset
);
4123 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4125 Builder
bld(ctx
->program
, ctx
->block
);
4127 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4128 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4129 /* component is in bytes */
4130 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4132 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4133 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4134 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4137 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4139 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4142 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4144 Builder
bld(ctx
->program
, ctx
->block
);
4146 switch (ctx
->shader
->info
.stage
) {
4147 case MESA_SHADER_TESS_CTRL
:
4148 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4149 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4150 case MESA_SHADER_TESS_EVAL
:
4151 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4153 unreachable("Unsupported stage in get_tess_rel_patch_id");
4157 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4159 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4160 Builder
bld(ctx
->program
, ctx
->block
);
4162 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4163 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4165 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4167 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4168 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4170 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4171 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4172 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4174 return offset_mul(ctx
, offs
, 4u);
4177 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4179 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4180 Builder
bld(ctx
->program
, ctx
->block
);
4182 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4183 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4184 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4185 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4187 std::pair
<Temp
, unsigned> offs
= instr
4188 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4189 : std::make_pair(Temp(), 0u);
4191 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4192 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4197 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4198 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4200 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4201 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4203 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4204 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4210 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4212 Builder
bld(ctx
->program
, ctx
->block
);
4214 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4215 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4217 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4219 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4220 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4221 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4223 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4224 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4229 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4231 Builder
bld(ctx
->program
, ctx
->block
);
4233 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4234 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4235 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4236 unsigned attr_stride
= ctx
->tcs_num_patches
;
4238 std::pair
<Temp
, unsigned> offs
= instr
4239 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4240 : std::make_pair(Temp(), 0u);
4242 if (const_base_offset
)
4243 offs
.second
+= const_base_offset
* attr_stride
;
4245 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4246 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4247 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4252 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4254 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4259 unsigned drv_loc
= nir_intrinsic_base(instr
);
4260 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4262 if (!nir_src_is_const(*off_src
)) {
4268 uint64_t slot
= per_vertex
4269 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4270 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4271 return (((uint64_t) 1) << slot
) & mask
;
4274 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4276 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4277 unsigned component
= nir_intrinsic_component(instr
);
4278 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4280 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4281 if (off_instr
->type
!= nir_instr_type_load_const
)
4284 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4285 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4287 if (instr
->src
[0].ssa
->bit_size
== 64)
4288 write_mask
= widen_mask(write_mask
, 2);
4290 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4292 for (unsigned i
= 0; i
< 8; ++i
) {
4293 if (write_mask
& (1 << i
)) {
4294 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4295 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4303 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4305 /* Only TCS per-vertex inputs are supported by this function.
4306 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4308 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4311 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4312 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4313 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4314 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4315 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4316 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4321 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4322 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4323 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4328 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4330 Builder
bld(ctx
->program
, ctx
->block
);
4332 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4333 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4334 bool indirect_write
;
4335 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4336 if (temp_only_input
&& !indirect_write
)
4340 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4341 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4342 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4343 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4345 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4346 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4347 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4348 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4349 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4353 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4354 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4355 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4356 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4357 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4358 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4359 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4360 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4361 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4362 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4363 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4364 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4365 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4367 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4368 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4370 unreachable("Invalid LS or ES stage");
4373 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4374 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4375 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4379 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4384 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4385 return off
== ctx
->tcs_tess_lvl_out_loc
||
4386 off
== ctx
->tcs_tess_lvl_in_loc
;
4390 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4392 uint64_t mask
= per_vertex
4393 ? ctx
->program
->info
->tcs
.tes_inputs_read
4394 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4396 bool indirect_write
= false;
4397 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4398 return indirect_write
|| output_read_by_tes
;
4401 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4403 uint64_t mask
= per_vertex
4404 ? ctx
->shader
->info
.outputs_read
4405 : ctx
->shader
->info
.patch_outputs_read
;
4407 bool indirect_write
= false;
4408 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4409 return indirect_write
|| output_read
;
4412 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4414 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4415 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4417 Builder
bld(ctx
->program
, ctx
->block
);
4419 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4420 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4421 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4423 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4424 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4425 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4427 if (write_to_vmem
) {
4428 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4429 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4430 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4432 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4433 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4434 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4438 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4439 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4440 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4444 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4446 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4447 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4449 Builder
bld(ctx
->program
, ctx
->block
);
4451 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4452 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4453 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4454 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4456 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4459 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4461 if (ctx
->stage
== vertex_vs
||
4462 ctx
->stage
== tess_eval_vs
||
4463 ctx
->stage
== fragment_fs
||
4464 ctx
->stage
== ngg_vertex_gs
||
4465 ctx
->stage
== ngg_tess_eval_gs
||
4466 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4467 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4468 if (!stored_to_temps
) {
4469 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4470 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4471 fprintf(stderr
, "\n");
4474 } else if (ctx
->stage
== vertex_es
||
4475 ctx
->stage
== vertex_ls
||
4476 ctx
->stage
== tess_eval_es
||
4477 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4478 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4479 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4480 visit_store_ls_or_es_output(ctx
, instr
);
4481 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4482 visit_store_tcs_output(ctx
, instr
, false);
4484 unreachable("Shader stage not implemented");
4488 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4490 visit_load_tcs_output(ctx
, instr
, false);
4493 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4495 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4496 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4498 Builder
bld(ctx
->program
, ctx
->block
);
4500 if (dst
.regClass() == v2b
) {
4501 if (ctx
->program
->has_16bank_lds
) {
4502 assert(ctx
->options
->chip_class
<= GFX8
);
4503 Builder::Result interp_p1
=
4504 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4505 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4506 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4507 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4508 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4509 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4511 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4513 if (ctx
->options
->chip_class
== GFX8
)
4514 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4516 Builder::Result interp_p1
=
4517 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4518 coord1
, bld
.m0(prim_mask
), idx
, component
);
4519 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4520 interp_p1
, idx
, component
);
4523 Builder::Result interp_p1
=
4524 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4525 bld
.m0(prim_mask
), idx
, component
);
4527 if (ctx
->program
->has_16bank_lds
)
4528 interp_p1
.instr
->operands
[0].setLateKill(true);
4530 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4531 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4535 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4537 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4538 for (unsigned i
= 0; i
< num_components
; i
++)
4539 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4540 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4541 assert(num_components
== 4);
4542 Builder
bld(ctx
->program
, ctx
->block
);
4543 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4546 for (Operand
& op
: vec
->operands
)
4547 op
= op
.isUndefined() ? Operand(0u) : op
;
4549 vec
->definitions
[0] = Definition(dst
);
4550 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4551 emit_split_vector(ctx
, dst
, num_components
);
4555 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4557 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4558 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4559 unsigned idx
= nir_intrinsic_base(instr
);
4560 unsigned component
= nir_intrinsic_component(instr
);
4561 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4563 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4565 assert(offset
->u32
== 0);
4567 /* the lower 15bit of the prim_mask contain the offset into LDS
4568 * while the upper bits contain the number of prims */
4569 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4570 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4571 Builder
bld(ctx
->program
, ctx
->block
);
4572 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4573 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4574 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4575 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4576 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4579 if (instr
->dest
.ssa
.num_components
== 1) {
4580 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4582 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4583 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4585 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4586 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4587 vec
->operands
[i
] = Operand(tmp
);
4589 vec
->definitions
[0] = Definition(dst
);
4590 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4594 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4595 unsigned offset
, unsigned stride
, unsigned channels
)
4597 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4598 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4600 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4601 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4604 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4605 unsigned offset
, unsigned stride
, unsigned *channels
)
4607 if (!vtx_info
->chan_byte_size
) {
4608 *channels
= vtx_info
->num_channels
;
4609 return vtx_info
->chan_format
;
4612 unsigned num_channels
= *channels
;
4613 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4614 unsigned new_channels
= num_channels
+ 1;
4615 /* first, assume more loads is worse and try using a larger data format */
4616 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4618 /* don't make the attribute potentially out-of-bounds */
4619 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4623 if (new_channels
== 5) {
4624 /* then try decreasing load size (at the cost of more loads) */
4625 new_channels
= *channels
;
4626 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4630 if (new_channels
< *channels
)
4631 *channels
= new_channels
;
4632 num_channels
= new_channels
;
4635 switch (vtx_info
->chan_format
) {
4636 case V_008F0C_BUF_DATA_FORMAT_8
:
4637 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4638 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4639 case V_008F0C_BUF_DATA_FORMAT_16
:
4640 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4641 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4642 case V_008F0C_BUF_DATA_FORMAT_32
:
4643 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4644 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4646 unreachable("shouldn't reach here");
4647 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4650 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4651 * so we may need to fix it up. */
4652 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4654 Builder
bld(ctx
->program
, ctx
->block
);
4656 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4657 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4659 /* For the integer-like cases, do a natural sign extension.
4661 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4662 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4665 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4666 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4668 /* Convert back to the right type. */
4669 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4670 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4671 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4672 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4673 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4674 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4680 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4682 Builder
bld(ctx
->program
, ctx
->block
);
4683 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4684 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4686 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4687 if (off_instr
->type
!= nir_instr_type_load_const
) {
4688 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4689 nir_print_instr(off_instr
, stderr
);
4690 fprintf(stderr
, "\n");
4692 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4694 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4696 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4697 unsigned component
= nir_intrinsic_component(instr
);
4698 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4699 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4700 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4701 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4702 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4704 unsigned dfmt
= attrib_format
& 0xf;
4705 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4706 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4708 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4709 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4710 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4711 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4713 num_channels
= MAX2(num_channels
, 3);
4715 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4716 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4719 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4720 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4721 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4723 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4725 Temp divided
= bld
.tmp(v1
);
4726 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4727 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4729 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4732 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4735 index
= bld
.vadd32(bld
.def(v1
),
4736 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4737 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4740 Temp channels
[num_channels
];
4741 unsigned channel_start
= 0;
4742 bool direct_fetch
= false;
4744 /* skip unused channels at the start */
4745 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4746 channel_start
= ffs(mask
) - 1;
4747 for (unsigned i
= 0; i
< channel_start
; i
++)
4748 channels
[i
] = Temp(0, s1
);
4749 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4750 num_channels
= 3 - (ffs(mask
) - 1);
4754 while (channel_start
< num_channels
) {
4755 unsigned fetch_component
= num_channels
- channel_start
;
4756 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4757 bool expanded
= false;
4759 /* use MUBUF when possible to avoid possible alignment issues */
4760 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4761 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4762 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4763 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4764 vtx_info
->chan_byte_size
== 4;
4765 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4767 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4769 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4770 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4771 fetch_component
= 4;
4776 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4778 Temp fetch_index
= index
;
4779 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4780 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4781 fetch_offset
= fetch_offset
% attrib_stride
;
4784 Operand
soffset(0u);
4785 if (fetch_offset
>= 4096) {
4786 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4787 fetch_offset
%= 4096;
4791 switch (fetch_bytes
) {
4793 assert(!use_mubuf
&& bitsize
== 16);
4794 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4797 if (bitsize
== 16) {
4799 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4801 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4805 assert(!use_mubuf
&& bitsize
== 16);
4806 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4809 if (bitsize
== 16) {
4811 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4813 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4817 assert(ctx
->options
->chip_class
>= GFX7
||
4818 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4819 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4822 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4825 unreachable("Unimplemented load_input vector size");
4829 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4830 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4831 num_channels
<= 3)) {
4832 direct_fetch
= true;
4835 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4839 Instruction
*mubuf
= bld
.mubuf(opcode
,
4840 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4841 fetch_offset
, false, true).instr
;
4842 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4844 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4845 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4846 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4847 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4850 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4852 if (fetch_component
== 1) {
4853 channels
[channel_start
] = fetch_dst
;
4855 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4856 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4857 bitsize
== 16 ? v2b
: v1
);
4860 channel_start
+= fetch_component
;
4863 if (!direct_fetch
) {
4864 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4865 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4867 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4868 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4869 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4871 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4872 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4873 unsigned num_temp
= 0;
4874 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4875 unsigned idx
= i
+ component
;
4876 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4877 Temp channel
= channels
[swizzle
[idx
]];
4878 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4879 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4880 vec
->operands
[i
] = Operand(channel
);
4884 } else if (is_float
&& idx
== 3) {
4885 vec
->operands
[i
] = Operand(0x3f800000u
);
4886 } else if (!is_float
&& idx
== 3) {
4887 vec
->operands
[i
] = Operand(1u);
4889 vec
->operands
[i
] = Operand(0u);
4892 vec
->definitions
[0] = Definition(dst
);
4893 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4894 emit_split_vector(ctx
, dst
, dst
.size());
4896 if (num_temp
== dst
.size())
4897 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4899 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4900 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4901 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4902 if (off_instr
->type
!= nir_instr_type_load_const
||
4903 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4904 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4905 nir_print_instr(off_instr
, stderr
);
4906 fprintf(stderr
, "\n");
4909 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4910 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4912 assert(offset
->u32
== 0);
4914 /* the lower 15bit of the prim_mask contain the offset into LDS
4915 * while the upper bits contain the number of prims */
4916 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4917 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4918 Builder
bld(ctx
->program
, ctx
->block
);
4919 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4920 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4921 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4922 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4923 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4926 unsigned idx
= nir_intrinsic_base(instr
);
4927 unsigned component
= nir_intrinsic_component(instr
);
4928 unsigned vertex_id
= 2; /* P0 */
4930 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4931 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4932 switch (src0
->u32
) {
4934 vertex_id
= 2; /* P0 */
4937 vertex_id
= 0; /* P10 */
4940 vertex_id
= 1; /* P20 */
4943 unreachable("invalid vertex index");
4947 if (dst
.size() == 1) {
4948 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4950 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4951 for (unsigned i
= 0; i
< dst
.size(); i
++)
4952 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4953 vec
->definitions
[0] = Definition(dst
);
4954 bld
.insert(std::move(vec
));
4957 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4958 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4959 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4960 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4961 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4963 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4965 unreachable("Shader stage not implemented");
4969 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4971 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4973 Builder
bld(ctx
->program
, ctx
->block
);
4974 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4977 if (!nir_src_is_const(*vertex_src
)) {
4978 /* better code could be created, but this case probably doesn't happen
4979 * much in practice */
4980 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4981 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4984 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4985 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4987 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4989 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4992 if (vertex_offset
.id()) {
4993 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4994 Operand(i
), indirect_vertex
);
4995 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4997 vertex_offset
= elem
;
5001 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5002 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
5004 unsigned vertex
= nir_src_as_uint(*vertex_src
);
5005 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5006 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5007 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
5008 Operand((vertex
% 2u) * 16u), Operand(16u));
5010 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
5013 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
5014 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
5015 return offset_mul(ctx
, offs
, 4u);
5018 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5020 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5022 Builder
bld(ctx
->program
, ctx
->block
);
5023 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5024 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5026 if (ctx
->stage
== geometry_gs
) {
5027 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
5028 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
5029 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
5030 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5031 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
5032 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5033 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5035 unreachable("Unsupported GS stage.");
5039 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5041 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5043 Builder
bld(ctx
->program
, ctx
->block
);
5044 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5046 if (load_input_from_temps(ctx
, instr
, dst
))
5049 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5050 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5051 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5053 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5056 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5058 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5060 Builder
bld(ctx
->program
, ctx
->block
);
5062 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5063 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5064 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5066 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5067 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5069 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5072 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5074 switch (ctx
->shader
->info
.stage
) {
5075 case MESA_SHADER_GEOMETRY
:
5076 visit_load_gs_per_vertex_input(ctx
, instr
);
5078 case MESA_SHADER_TESS_CTRL
:
5079 visit_load_tcs_per_vertex_input(ctx
, instr
);
5081 case MESA_SHADER_TESS_EVAL
:
5082 visit_load_tes_per_vertex_input(ctx
, instr
);
5085 unreachable("Unimplemented shader stage");
5089 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5091 visit_load_tcs_output(ctx
, instr
, true);
5094 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5096 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5097 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5099 visit_store_tcs_output(ctx
, instr
, true);
5102 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5104 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5106 Builder
bld(ctx
->program
, ctx
->block
);
5107 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5109 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5110 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5113 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5114 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5115 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5116 tes_w
= Operand(tmp
);
5119 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5120 emit_split_vector(ctx
, tess_coord
, 3);
5123 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5125 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5126 Builder
bld(ctx
->program
, ctx
->block
);
5127 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5128 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5129 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5132 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5136 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5138 Builder
bld(ctx
->program
, ctx
->block
);
5139 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5140 if (!nir_dest_is_divergent(instr
->dest
))
5141 index
= bld
.as_uniform(index
);
5142 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5143 unsigned binding
= nir_intrinsic_binding(instr
);
5146 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5147 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5148 unsigned offset
= layout
->binding
[binding
].offset
;
5150 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5151 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5152 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5153 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5154 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5157 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5158 stride
= layout
->binding
[binding
].size
;
5161 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5162 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5164 if (nir_const_index
) {
5165 const_index
= const_index
* stride
;
5166 } else if (index
.type() == RegType::vgpr
) {
5167 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5168 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5170 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5174 if (nir_const_index
) {
5175 const_index
= const_index
+ offset
;
5176 } else if (index
.type() == RegType::vgpr
) {
5177 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5179 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5183 if (nir_const_index
&& const_index
== 0) {
5185 } else if (index
.type() == RegType::vgpr
) {
5186 index
= bld
.vadd32(bld
.def(v1
),
5187 nir_const_index
? Operand(const_index
) : Operand(index
),
5190 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5191 nir_const_index
? Operand(const_index
) : Operand(index
),
5195 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5198 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5199 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5200 bool glc
=false, bool readonly
=true, bool allow_smem
=true)
5202 Builder
bld(ctx
->program
, ctx
->block
);
5204 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5206 offset
= bld
.as_uniform(offset
);
5208 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5210 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5211 info
.can_reorder
= readonly
;
5212 info
.align_mul
= align_mul
;
5213 info
.align_offset
= align_offset
;
5215 emit_smem_load(ctx
, bld
, &info
);
5217 emit_mubuf_load(ctx
, bld
, &info
);
5220 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5222 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5223 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5225 Builder
bld(ctx
->program
, ctx
->block
);
5227 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5228 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5229 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5230 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5232 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5233 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5234 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5235 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5236 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5237 if (ctx
->options
->chip_class
>= GFX10
) {
5238 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5239 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5240 S_008F0C_RESOURCE_LEVEL(1);
5242 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5243 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5245 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5246 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5247 Operand(0xFFFFFFFFu
),
5248 Operand(desc_type
));
5249 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5250 rsrc
, upper_dwords
);
5252 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5253 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5255 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5256 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5257 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5260 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5262 Builder
bld(ctx
->program
, ctx
->block
);
5263 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5264 unsigned offset
= nir_intrinsic_base(instr
);
5265 unsigned count
= instr
->dest
.ssa
.num_components
;
5266 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5268 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5269 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5270 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5271 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5272 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5273 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5274 for (unsigned i
= 0; i
< count
; ++i
) {
5275 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5276 vec
->operands
[i
] = Operand
{elems
[i
]};
5278 vec
->definitions
[0] = Definition(dst
);
5279 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5280 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5285 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5286 if (offset
!= 0) // TODO check if index != 0 as well
5287 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5288 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5291 bool aligned
= true;
5293 if (instr
->dest
.ssa
.bit_size
== 8) {
5294 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5295 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5297 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5298 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5299 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5301 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5306 switch (vec
.size()) {
5308 op
= aco_opcode::s_load_dword
;
5311 op
= aco_opcode::s_load_dwordx2
;
5317 op
= aco_opcode::s_load_dwordx4
;
5323 op
= aco_opcode::s_load_dwordx8
;
5326 unreachable("unimplemented or forbidden load_push_constant.");
5329 bld
.smem(op
, Definition(vec
), ptr
, index
);
5332 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5333 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5338 emit_split_vector(ctx
, vec
, 4);
5339 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5340 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5341 emit_extract_vector(ctx
, vec
, 0, rc
),
5342 emit_extract_vector(ctx
, vec
, 1, rc
),
5343 emit_extract_vector(ctx
, vec
, 2, rc
));
5346 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5349 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5351 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5353 Builder
bld(ctx
->program
, ctx
->block
);
5355 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5356 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5357 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5358 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5359 if (ctx
->options
->chip_class
>= GFX10
) {
5360 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5361 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5362 S_008F0C_RESOURCE_LEVEL(1);
5364 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5365 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5368 unsigned base
= nir_intrinsic_base(instr
);
5369 unsigned range
= nir_intrinsic_range(instr
);
5371 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5372 if (base
&& offset
.type() == RegType::sgpr
)
5373 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5374 else if (base
&& offset
.type() == RegType::vgpr
)
5375 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5377 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5378 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5379 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5380 Operand(desc_type
));
5381 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5382 // TODO: get alignment information for subdword constants
5383 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5386 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5388 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5389 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5391 ctx
->program
->needs_exact
= true;
5393 // TODO: optimize uniform conditions
5394 Builder
bld(ctx
->program
, ctx
->block
);
5395 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5396 assert(src
.regClass() == bld
.lm
);
5397 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5398 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5399 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5403 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5405 Builder
bld(ctx
->program
, ctx
->block
);
5407 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5408 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5410 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5411 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5413 if (ctx
->block
->loop_nest_depth
&&
5414 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5415 /* we handle discards the same way as jump instructions */
5416 append_logical_end(ctx
->block
);
5418 /* in loops, discard behaves like break */
5419 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5420 ctx
->block
->kind
|= block_kind_discard
;
5423 /* uniform discard - loop ends here */
5424 assert(nir_instr_is_last(&instr
->instr
));
5425 ctx
->block
->kind
|= block_kind_uniform
;
5426 ctx
->cf_info
.has_branch
= true;
5427 bld
.branch(aco_opcode::p_branch
);
5428 add_linear_edge(ctx
->block
->index
, linear_target
);
5432 /* we add a break right behind the discard() instructions */
5433 ctx
->block
->kind
|= block_kind_break
;
5434 unsigned idx
= ctx
->block
->index
;
5436 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5437 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5439 /* remove critical edges from linear CFG */
5440 bld
.branch(aco_opcode::p_branch
);
5441 Block
* break_block
= ctx
->program
->create_and_insert_block();
5442 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5443 break_block
->kind
|= block_kind_uniform
;
5444 add_linear_edge(idx
, break_block
);
5445 add_linear_edge(break_block
->index
, linear_target
);
5446 bld
.reset(break_block
);
5447 bld
.branch(aco_opcode::p_branch
);
5449 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5450 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5451 add_linear_edge(idx
, continue_block
);
5452 append_logical_start(continue_block
);
5453 ctx
->block
= continue_block
;
5458 /* it can currently happen that NIR doesn't remove the unreachable code */
5459 if (!nir_instr_is_last(&instr
->instr
)) {
5460 ctx
->program
->needs_exact
= true;
5461 /* save exec somewhere temporarily so that it doesn't get
5462 * overwritten before the discard from outer exec masks */
5463 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5464 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5465 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5469 /* This condition is incorrect for uniformly branched discards in a loop
5470 * predicated by a divergent condition, but the above code catches that case
5471 * and the discard would end up turning into a discard_if.
5481 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5482 /* program just ends here */
5483 ctx
->block
->kind
|= block_kind_uniform
;
5484 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5485 0 /* enabled mask */, 9 /* dest */,
5486 false /* compressed */, true/* done */, true /* valid mask */);
5487 bld
.sopp(aco_opcode::s_endpgm
);
5488 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5490 ctx
->block
->kind
|= block_kind_discard
;
5491 /* branch and linear edge is added by visit_if() */
5495 enum aco_descriptor_type
{
5506 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5507 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5509 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5510 return dim
== ac_image_cube
||
5511 dim
== ac_image_1darray
||
5512 dim
== ac_image_2darray
||
5513 dim
== ac_image_2darraymsaa
;
5516 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5517 enum aco_descriptor_type desc_type
,
5518 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5520 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5521 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5522 if (it != ctx->tex_desc.end())
5525 Temp index
= Temp();
5526 bool index_set
= false;
5527 unsigned constant_index
= 0;
5528 unsigned descriptor_set
;
5529 unsigned base_index
;
5530 Builder
bld(ctx
->program
, ctx
->block
);
5533 assert(tex_instr
&& !image
);
5535 base_index
= tex_instr
->sampler_index
;
5537 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5538 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5542 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5543 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5545 constant_index
+= array_size
* const_value
->u32
;
5547 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5548 if (indirect
.type() == RegType::vgpr
)
5549 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5551 if (array_size
!= 1)
5552 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5558 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5562 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5564 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5565 base_index
= deref_instr
->var
->data
.binding
;
5568 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5569 list
= convert_pointer_to_64_bit(ctx
, list
);
5571 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5572 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5573 unsigned offset
= binding
->offset
;
5574 unsigned stride
= binding
->size
;
5578 assert(base_index
< layout
->binding_count
);
5580 switch (desc_type
) {
5581 case ACO_DESC_IMAGE
:
5583 opcode
= aco_opcode::s_load_dwordx8
;
5585 case ACO_DESC_FMASK
:
5587 opcode
= aco_opcode::s_load_dwordx8
;
5590 case ACO_DESC_SAMPLER
:
5592 opcode
= aco_opcode::s_load_dwordx4
;
5593 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5594 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5596 case ACO_DESC_BUFFER
:
5598 opcode
= aco_opcode::s_load_dwordx4
;
5600 case ACO_DESC_PLANE_0
:
5601 case ACO_DESC_PLANE_1
:
5603 opcode
= aco_opcode::s_load_dwordx8
;
5604 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5606 case ACO_DESC_PLANE_2
:
5608 opcode
= aco_opcode::s_load_dwordx4
;
5612 unreachable("invalid desc_type\n");
5615 offset
+= constant_index
* stride
;
5617 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5618 (!index_set
|| binding
->immutable_samplers_equal
)) {
5619 if (binding
->immutable_samplers_equal
)
5622 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5623 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5624 Operand(samplers
[constant_index
* 4 + 0]),
5625 Operand(samplers
[constant_index
* 4 + 1]),
5626 Operand(samplers
[constant_index
* 4 + 2]),
5627 Operand(samplers
[constant_index
* 4 + 3]));
5632 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5634 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5635 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5638 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5640 if (desc_type
== ACO_DESC_PLANE_2
) {
5642 for (unsigned i
= 0; i
< 8; i
++)
5643 components
[i
] = bld
.tmp(s1
);
5644 bld
.pseudo(aco_opcode::p_split_vector
,
5645 Definition(components
[0]),
5646 Definition(components
[1]),
5647 Definition(components
[2]),
5648 Definition(components
[3]),
5651 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5652 bld
.pseudo(aco_opcode::p_split_vector
,
5653 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5654 Definition(components
[4]),
5655 Definition(components
[5]),
5656 Definition(components
[6]),
5657 Definition(components
[7]),
5660 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5661 components
[0], components
[1], components
[2], components
[3],
5662 components
[4], components
[5], components
[6], components
[7]);
5668 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5671 case GLSL_SAMPLER_DIM_BUF
:
5673 case GLSL_SAMPLER_DIM_1D
:
5674 return array
? 2 : 1;
5675 case GLSL_SAMPLER_DIM_2D
:
5676 return array
? 3 : 2;
5677 case GLSL_SAMPLER_DIM_MS
:
5678 return array
? 4 : 3;
5679 case GLSL_SAMPLER_DIM_3D
:
5680 case GLSL_SAMPLER_DIM_CUBE
:
5682 case GLSL_SAMPLER_DIM_RECT
:
5683 case GLSL_SAMPLER_DIM_SUBPASS
:
5685 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5694 /* Adjust the sample index according to FMASK.
5696 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5697 * which is the identity mapping. Each nibble says which physical sample
5698 * should be fetched to get that sample.
5700 * For example, 0x11111100 means there are only 2 samples stored and
5701 * the second sample covers 3/4 of the pixel. When reading samples 0
5702 * and 1, return physical sample 0 (determined by the first two 0s
5703 * in FMASK), otherwise return physical sample 1.
5705 * The sample index should be adjusted as follows:
5706 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5708 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5710 Builder
bld(ctx
->program
, ctx
->block
);
5711 Temp fmask
= bld
.tmp(v1
);
5712 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5713 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5716 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5717 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5718 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5719 load
->operands
[0] = Operand(fmask_desc_ptr
);
5720 load
->operands
[1] = Operand(s4
); /* no sampler */
5721 load
->operands
[2] = Operand(coord
);
5722 load
->definitions
[0] = Definition(fmask
);
5729 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5730 ctx
->block
->instructions
.emplace_back(std::move(load
));
5732 Operand sample_index4
;
5733 if (sample_index
.isConstant()) {
5734 if (sample_index
.constantValue() < 16) {
5735 sample_index4
= Operand(sample_index
.constantValue() << 2);
5737 sample_index4
= Operand(0u);
5739 } else if (sample_index
.regClass() == s1
) {
5740 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5742 assert(sample_index
.regClass() == v1
);
5743 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5747 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5748 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5749 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5750 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5752 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5754 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5755 * resource descriptor is 0 (invalid),
5757 Temp compare
= bld
.tmp(bld
.lm
);
5758 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5759 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5761 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5763 /* Replace the MSAA sample index. */
5764 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5767 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5770 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5771 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5772 bool is_array
= glsl_sampler_type_is_array(type
);
5773 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5774 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5775 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5776 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5777 int count
= image_type_to_components_count(dim
, is_array
);
5778 std::vector
<Temp
> coords(count
);
5779 Builder
bld(ctx
->program
, ctx
->block
);
5783 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5784 /* get sample index */
5785 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5786 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5787 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5788 std::vector
<Temp
> fmask_load_address
;
5789 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5790 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5792 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5793 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5795 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5800 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5801 coords
.resize(coords
.size() + 1);
5802 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5804 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5806 for (int i
= 0; i
< count
; i
++)
5807 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5810 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5811 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5812 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5813 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5816 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5819 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5820 for (unsigned i
= 0; i
< coords
.size(); i
++)
5821 vec
->operands
[i
] = Operand(coords
[i
]);
5822 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5823 vec
->definitions
[0] = Definition(res
);
5824 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5829 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5831 Builder
bld(ctx
->program
, ctx
->block
);
5832 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5833 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5834 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5835 bool is_array
= glsl_sampler_type_is_array(type
);
5836 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5838 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5839 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5840 unsigned num_channels
= util_last_bit(mask
);
5841 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5842 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5845 switch (num_channels
) {
5847 opcode
= aco_opcode::buffer_load_format_x
;
5850 opcode
= aco_opcode::buffer_load_format_xy
;
5853 opcode
= aco_opcode::buffer_load_format_xyz
;
5856 opcode
= aco_opcode::buffer_load_format_xyzw
;
5859 unreachable(">4 channel buffer image load");
5861 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5862 load
->operands
[0] = Operand(rsrc
);
5863 load
->operands
[1] = Operand(vindex
);
5864 load
->operands
[2] = Operand((uint32_t) 0);
5866 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5869 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5870 load
->definitions
[0] = Definition(tmp
);
5872 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5873 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5874 load
->barrier
= barrier_image
;
5875 ctx
->block
->instructions
.emplace_back(std::move(load
));
5877 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5881 Temp coords
= get_image_coords(ctx
, instr
, type
);
5882 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5884 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5885 unsigned num_components
= util_bitcount(dmask
);
5887 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5890 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5892 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5893 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5895 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5896 load
->operands
[0] = Operand(resource
);
5897 load
->operands
[1] = Operand(s4
); /* no sampler */
5898 load
->operands
[2] = Operand(coords
);
5899 load
->definitions
[0] = Definition(tmp
);
5900 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5901 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5902 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5903 load
->dmask
= dmask
;
5905 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5906 load
->barrier
= barrier_image
;
5907 ctx
->block
->instructions
.emplace_back(std::move(load
));
5909 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5913 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5915 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5916 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5917 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5918 bool is_array
= glsl_sampler_type_is_array(type
);
5919 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5921 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5923 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5924 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5925 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5927 switch (data
.size()) {
5929 opcode
= aco_opcode::buffer_store_format_x
;
5932 opcode
= aco_opcode::buffer_store_format_xy
;
5935 opcode
= aco_opcode::buffer_store_format_xyz
;
5938 opcode
= aco_opcode::buffer_store_format_xyzw
;
5941 unreachable(">4 channel buffer image store");
5943 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5944 store
->operands
[0] = Operand(rsrc
);
5945 store
->operands
[1] = Operand(vindex
);
5946 store
->operands
[2] = Operand((uint32_t) 0);
5947 store
->operands
[3] = Operand(data
);
5948 store
->idxen
= true;
5951 store
->disable_wqm
= true;
5952 store
->barrier
= barrier_image
;
5953 ctx
->program
->needs_exact
= true;
5954 ctx
->block
->instructions
.emplace_back(std::move(store
));
5958 assert(data
.type() == RegType::vgpr
);
5959 Temp coords
= get_image_coords(ctx
, instr
, type
);
5960 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5962 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5963 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5965 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5966 store
->operands
[0] = Operand(resource
);
5967 store
->operands
[1] = Operand(data
);
5968 store
->operands
[2] = Operand(coords
);
5971 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5972 store
->dmask
= (1 << data
.size()) - 1;
5974 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5975 store
->disable_wqm
= true;
5976 store
->barrier
= barrier_image
;
5977 ctx
->program
->needs_exact
= true;
5978 ctx
->block
->instructions
.emplace_back(std::move(store
));
5982 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5984 /* return the previous value if dest is ever used */
5985 bool return_previous
= false;
5986 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5987 return_previous
= true;
5990 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5991 return_previous
= true;
5995 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5996 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5997 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5998 bool is_array
= glsl_sampler_type_is_array(type
);
5999 Builder
bld(ctx
->program
, ctx
->block
);
6001 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
6002 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
6004 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
6005 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
6007 aco_opcode buf_op
, image_op
;
6008 switch (instr
->intrinsic
) {
6009 case nir_intrinsic_image_deref_atomic_add
:
6010 buf_op
= aco_opcode::buffer_atomic_add
;
6011 image_op
= aco_opcode::image_atomic_add
;
6013 case nir_intrinsic_image_deref_atomic_umin
:
6014 buf_op
= aco_opcode::buffer_atomic_umin
;
6015 image_op
= aco_opcode::image_atomic_umin
;
6017 case nir_intrinsic_image_deref_atomic_imin
:
6018 buf_op
= aco_opcode::buffer_atomic_smin
;
6019 image_op
= aco_opcode::image_atomic_smin
;
6021 case nir_intrinsic_image_deref_atomic_umax
:
6022 buf_op
= aco_opcode::buffer_atomic_umax
;
6023 image_op
= aco_opcode::image_atomic_umax
;
6025 case nir_intrinsic_image_deref_atomic_imax
:
6026 buf_op
= aco_opcode::buffer_atomic_smax
;
6027 image_op
= aco_opcode::image_atomic_smax
;
6029 case nir_intrinsic_image_deref_atomic_and
:
6030 buf_op
= aco_opcode::buffer_atomic_and
;
6031 image_op
= aco_opcode::image_atomic_and
;
6033 case nir_intrinsic_image_deref_atomic_or
:
6034 buf_op
= aco_opcode::buffer_atomic_or
;
6035 image_op
= aco_opcode::image_atomic_or
;
6037 case nir_intrinsic_image_deref_atomic_xor
:
6038 buf_op
= aco_opcode::buffer_atomic_xor
;
6039 image_op
= aco_opcode::image_atomic_xor
;
6041 case nir_intrinsic_image_deref_atomic_exchange
:
6042 buf_op
= aco_opcode::buffer_atomic_swap
;
6043 image_op
= aco_opcode::image_atomic_swap
;
6045 case nir_intrinsic_image_deref_atomic_comp_swap
:
6046 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
6047 image_op
= aco_opcode::image_atomic_cmpswap
;
6050 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6053 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6055 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6056 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6057 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6058 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6059 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6060 mubuf
->operands
[0] = Operand(resource
);
6061 mubuf
->operands
[1] = Operand(vindex
);
6062 mubuf
->operands
[2] = Operand((uint32_t)0);
6063 mubuf
->operands
[3] = Operand(data
);
6064 if (return_previous
)
6065 mubuf
->definitions
[0] = Definition(dst
);
6067 mubuf
->idxen
= true;
6068 mubuf
->glc
= return_previous
;
6069 mubuf
->dlc
= false; /* Not needed for atomics */
6070 mubuf
->disable_wqm
= true;
6071 mubuf
->barrier
= barrier_image
;
6072 ctx
->program
->needs_exact
= true;
6073 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6077 Temp coords
= get_image_coords(ctx
, instr
, type
);
6078 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6079 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6080 mimg
->operands
[0] = Operand(resource
);
6081 mimg
->operands
[1] = Operand(data
);
6082 mimg
->operands
[2] = Operand(coords
);
6083 if (return_previous
)
6084 mimg
->definitions
[0] = Definition(dst
);
6085 mimg
->glc
= return_previous
;
6086 mimg
->dlc
= false; /* Not needed for atomics */
6087 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6088 mimg
->dmask
= (1 << data
.size()) - 1;
6090 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6091 mimg
->disable_wqm
= true;
6092 mimg
->barrier
= barrier_image
;
6093 ctx
->program
->needs_exact
= true;
6094 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6098 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6100 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6101 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6102 Builder
bld(ctx
->program
, ctx
->block
);
6104 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6106 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6107 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6109 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6110 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6112 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6113 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6115 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6116 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6117 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6118 if (dst
.type() == RegType::vgpr
)
6119 bld
.copy(Definition(dst
), shr_dst
);
6121 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6123 emit_extract_vector(ctx
, desc
, 2, dst
);
6127 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6129 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6130 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6131 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6132 bool is_array
= glsl_sampler_type_is_array(type
);
6133 Builder
bld(ctx
->program
, ctx
->block
);
6135 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6136 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6137 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6141 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6144 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6146 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6148 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6149 mimg
->operands
[0] = Operand(resource
);
6150 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6151 mimg
->operands
[2] = Operand(lod
);
6152 uint8_t& dmask
= mimg
->dmask
;
6153 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6154 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6155 mimg
->da
= glsl_sampler_type_is_array(type
);
6156 mimg
->can_reorder
= true;
6157 Definition
& def
= mimg
->definitions
[0];
6158 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6160 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6161 glsl_sampler_type_is_array(type
)) {
6163 assert(instr
->dest
.ssa
.num_components
== 3);
6164 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6165 def
= Definition(tmp
);
6166 emit_split_vector(ctx
, tmp
, 3);
6168 /* divide 3rd value by 6 by multiplying with magic number */
6169 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6170 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6172 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6173 emit_extract_vector(ctx
, tmp
, 0, v1
),
6174 emit_extract_vector(ctx
, tmp
, 1, v1
),
6177 } else if (ctx
->options
->chip_class
== GFX9
&&
6178 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6179 glsl_sampler_type_is_array(type
)) {
6180 assert(instr
->dest
.ssa
.num_components
== 2);
6181 def
= Definition(dst
);
6184 def
= Definition(dst
);
6187 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6190 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6192 Builder
bld(ctx
->program
, ctx
->block
);
6193 unsigned num_components
= instr
->num_components
;
6195 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6196 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6197 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6199 unsigned access
= nir_intrinsic_access(instr
);
6200 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6201 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6203 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6204 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6205 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6207 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6208 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6210 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6211 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false, allow_smem
);
6214 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6216 Builder
bld(ctx
->program
, ctx
->block
);
6217 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6218 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6219 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6220 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6222 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6223 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6225 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6226 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6227 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6228 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6230 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6232 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6233 ctx
->options
->chip_class
>= GFX8
&&
6234 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6237 offset
= bld
.as_uniform(offset
);
6238 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6240 unsigned write_count
= 0;
6241 Temp write_datas
[32];
6242 unsigned offsets
[32];
6243 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6244 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6246 for (unsigned i
= 0; i
< write_count
; i
++) {
6247 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6248 if (smem
&& ctx
->stage
== fragment_fs
)
6249 op
= aco_opcode::p_fs_buffer_store_smem
;
6252 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6253 store
->operands
[0] = Operand(rsrc
);
6255 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6256 offset
, Operand(offsets
[i
]));
6257 store
->operands
[1] = Operand(off
);
6259 store
->operands
[1] = Operand(offset
);
6261 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6262 store
->operands
[1].setFixed(m0
);
6263 store
->operands
[2] = Operand(write_datas
[i
]);
6266 store
->disable_wqm
= true;
6267 store
->barrier
= barrier_buffer
;
6268 ctx
->block
->instructions
.emplace_back(std::move(store
));
6269 ctx
->program
->wb_smem_l1_on_end
= true;
6270 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6271 ctx
->block
->kind
|= block_kind_needs_lowering
;
6272 ctx
->program
->needs_exact
= true;
6275 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6276 store
->operands
[0] = Operand(rsrc
);
6277 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6278 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6279 store
->operands
[3] = Operand(write_datas
[i
]);
6280 store
->offset
= offsets
[i
];
6281 store
->offen
= (offset
.type() == RegType::vgpr
);
6284 store
->disable_wqm
= true;
6285 store
->barrier
= barrier_buffer
;
6286 ctx
->program
->needs_exact
= true;
6287 ctx
->block
->instructions
.emplace_back(std::move(store
));
6292 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6294 /* return the previous value if dest is ever used */
6295 bool return_previous
= false;
6296 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6297 return_previous
= true;
6300 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6301 return_previous
= true;
6305 Builder
bld(ctx
->program
, ctx
->block
);
6306 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6308 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6309 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6310 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6312 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6313 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6314 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6316 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6318 aco_opcode op32
, op64
;
6319 switch (instr
->intrinsic
) {
6320 case nir_intrinsic_ssbo_atomic_add
:
6321 op32
= aco_opcode::buffer_atomic_add
;
6322 op64
= aco_opcode::buffer_atomic_add_x2
;
6324 case nir_intrinsic_ssbo_atomic_imin
:
6325 op32
= aco_opcode::buffer_atomic_smin
;
6326 op64
= aco_opcode::buffer_atomic_smin_x2
;
6328 case nir_intrinsic_ssbo_atomic_umin
:
6329 op32
= aco_opcode::buffer_atomic_umin
;
6330 op64
= aco_opcode::buffer_atomic_umin_x2
;
6332 case nir_intrinsic_ssbo_atomic_imax
:
6333 op32
= aco_opcode::buffer_atomic_smax
;
6334 op64
= aco_opcode::buffer_atomic_smax_x2
;
6336 case nir_intrinsic_ssbo_atomic_umax
:
6337 op32
= aco_opcode::buffer_atomic_umax
;
6338 op64
= aco_opcode::buffer_atomic_umax_x2
;
6340 case nir_intrinsic_ssbo_atomic_and
:
6341 op32
= aco_opcode::buffer_atomic_and
;
6342 op64
= aco_opcode::buffer_atomic_and_x2
;
6344 case nir_intrinsic_ssbo_atomic_or
:
6345 op32
= aco_opcode::buffer_atomic_or
;
6346 op64
= aco_opcode::buffer_atomic_or_x2
;
6348 case nir_intrinsic_ssbo_atomic_xor
:
6349 op32
= aco_opcode::buffer_atomic_xor
;
6350 op64
= aco_opcode::buffer_atomic_xor_x2
;
6352 case nir_intrinsic_ssbo_atomic_exchange
:
6353 op32
= aco_opcode::buffer_atomic_swap
;
6354 op64
= aco_opcode::buffer_atomic_swap_x2
;
6356 case nir_intrinsic_ssbo_atomic_comp_swap
:
6357 op32
= aco_opcode::buffer_atomic_cmpswap
;
6358 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6361 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6363 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6364 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6365 mubuf
->operands
[0] = Operand(rsrc
);
6366 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6367 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6368 mubuf
->operands
[3] = Operand(data
);
6369 if (return_previous
)
6370 mubuf
->definitions
[0] = Definition(dst
);
6372 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6373 mubuf
->glc
= return_previous
;
6374 mubuf
->dlc
= false; /* Not needed for atomics */
6375 mubuf
->disable_wqm
= true;
6376 mubuf
->barrier
= barrier_buffer
;
6377 ctx
->program
->needs_exact
= true;
6378 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6381 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6383 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6384 Builder
bld(ctx
->program
, ctx
->block
);
6385 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6386 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6389 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6391 Builder
bld(ctx
->program
, ctx
->block
);
6392 unsigned num_components
= instr
->num_components
;
6393 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6395 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6396 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6397 num_components
, component_size
};
6398 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6399 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6400 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6401 info
.barrier
= barrier_buffer
;
6402 info
.can_reorder
= false;
6403 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6404 * it's safe to use SMEM */
6405 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6406 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6407 emit_global_load(ctx
, bld
, &info
);
6409 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6410 emit_smem_load(ctx
, bld
, &info
);
6414 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6416 Builder
bld(ctx
->program
, ctx
->block
);
6417 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6418 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6420 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6421 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6422 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6424 if (ctx
->options
->chip_class
>= GFX7
)
6425 addr
= as_vgpr(ctx
, addr
);
6427 unsigned write_count
= 0;
6428 Temp write_datas
[32];
6429 unsigned offsets
[32];
6430 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6431 16, &write_count
, write_datas
, offsets
);
6433 for (unsigned i
= 0; i
< write_count
; i
++) {
6434 if (ctx
->options
->chip_class
>= GFX7
) {
6435 unsigned offset
= offsets
[i
];
6436 Temp store_addr
= addr
;
6437 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6438 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6439 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6440 Temp carry
= bld
.tmp(bld
.lm
);
6441 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6443 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6444 Operand(offset
), addr0
);
6445 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6447 carry
).def(1).setHint(vcc
);
6449 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6454 bool global
= ctx
->options
->chip_class
>= GFX9
;
6456 switch (write_datas
[i
].bytes()) {
6458 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6461 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6464 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6467 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6470 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6473 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6476 unreachable("store_global not implemented for this size.");
6479 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6480 flat
->operands
[0] = Operand(store_addr
);
6481 flat
->operands
[1] = Operand(s1
);
6482 flat
->operands
[2] = Operand(write_datas
[i
]);
6485 flat
->offset
= offset
;
6486 flat
->disable_wqm
= true;
6487 flat
->barrier
= barrier_buffer
;
6488 ctx
->program
->needs_exact
= true;
6489 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6491 assert(ctx
->options
->chip_class
== GFX6
);
6493 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6495 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6497 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6498 mubuf
->operands
[0] = Operand(rsrc
);
6499 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6500 mubuf
->operands
[2] = Operand(0u);
6501 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6504 mubuf
->offset
= offsets
[i
];
6505 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6506 mubuf
->disable_wqm
= true;
6507 mubuf
->barrier
= barrier_buffer
;
6508 ctx
->program
->needs_exact
= true;
6509 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6514 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6516 /* return the previous value if dest is ever used */
6517 bool return_previous
= false;
6518 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6519 return_previous
= true;
6522 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6523 return_previous
= true;
6527 Builder
bld(ctx
->program
, ctx
->block
);
6528 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6529 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6531 if (ctx
->options
->chip_class
>= GFX7
)
6532 addr
= as_vgpr(ctx
, addr
);
6534 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6535 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6536 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6538 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6540 aco_opcode op32
, op64
;
6542 if (ctx
->options
->chip_class
>= GFX7
) {
6543 bool global
= ctx
->options
->chip_class
>= GFX9
;
6544 switch (instr
->intrinsic
) {
6545 case nir_intrinsic_global_atomic_add
:
6546 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6547 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6549 case nir_intrinsic_global_atomic_imin
:
6550 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6551 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6553 case nir_intrinsic_global_atomic_umin
:
6554 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6555 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6557 case nir_intrinsic_global_atomic_imax
:
6558 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6559 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6561 case nir_intrinsic_global_atomic_umax
:
6562 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6563 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6565 case nir_intrinsic_global_atomic_and
:
6566 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6567 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6569 case nir_intrinsic_global_atomic_or
:
6570 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6571 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6573 case nir_intrinsic_global_atomic_xor
:
6574 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6575 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6577 case nir_intrinsic_global_atomic_exchange
:
6578 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6579 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6581 case nir_intrinsic_global_atomic_comp_swap
:
6582 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6583 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6586 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6589 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6590 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6591 flat
->operands
[0] = Operand(addr
);
6592 flat
->operands
[1] = Operand(s1
);
6593 flat
->operands
[2] = Operand(data
);
6594 if (return_previous
)
6595 flat
->definitions
[0] = Definition(dst
);
6596 flat
->glc
= return_previous
;
6597 flat
->dlc
= false; /* Not needed for atomics */
6599 flat
->disable_wqm
= true;
6600 flat
->barrier
= barrier_buffer
;
6601 ctx
->program
->needs_exact
= true;
6602 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6604 assert(ctx
->options
->chip_class
== GFX6
);
6606 switch (instr
->intrinsic
) {
6607 case nir_intrinsic_global_atomic_add
:
6608 op32
= aco_opcode::buffer_atomic_add
;
6609 op64
= aco_opcode::buffer_atomic_add_x2
;
6611 case nir_intrinsic_global_atomic_imin
:
6612 op32
= aco_opcode::buffer_atomic_smin
;
6613 op64
= aco_opcode::buffer_atomic_smin_x2
;
6615 case nir_intrinsic_global_atomic_umin
:
6616 op32
= aco_opcode::buffer_atomic_umin
;
6617 op64
= aco_opcode::buffer_atomic_umin_x2
;
6619 case nir_intrinsic_global_atomic_imax
:
6620 op32
= aco_opcode::buffer_atomic_smax
;
6621 op64
= aco_opcode::buffer_atomic_smax_x2
;
6623 case nir_intrinsic_global_atomic_umax
:
6624 op32
= aco_opcode::buffer_atomic_umax
;
6625 op64
= aco_opcode::buffer_atomic_umax_x2
;
6627 case nir_intrinsic_global_atomic_and
:
6628 op32
= aco_opcode::buffer_atomic_and
;
6629 op64
= aco_opcode::buffer_atomic_and_x2
;
6631 case nir_intrinsic_global_atomic_or
:
6632 op32
= aco_opcode::buffer_atomic_or
;
6633 op64
= aco_opcode::buffer_atomic_or_x2
;
6635 case nir_intrinsic_global_atomic_xor
:
6636 op32
= aco_opcode::buffer_atomic_xor
;
6637 op64
= aco_opcode::buffer_atomic_xor_x2
;
6639 case nir_intrinsic_global_atomic_exchange
:
6640 op32
= aco_opcode::buffer_atomic_swap
;
6641 op64
= aco_opcode::buffer_atomic_swap_x2
;
6643 case nir_intrinsic_global_atomic_comp_swap
:
6644 op32
= aco_opcode::buffer_atomic_cmpswap
;
6645 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6648 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6651 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6653 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6655 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6656 mubuf
->operands
[0] = Operand(rsrc
);
6657 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6658 mubuf
->operands
[2] = Operand(0u);
6659 mubuf
->operands
[3] = Operand(data
);
6660 if (return_previous
)
6661 mubuf
->definitions
[0] = Definition(dst
);
6662 mubuf
->glc
= return_previous
;
6665 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6666 mubuf
->disable_wqm
= true;
6667 mubuf
->barrier
= barrier_buffer
;
6668 ctx
->program
->needs_exact
= true;
6669 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6673 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6674 Builder
bld(ctx
->program
, ctx
->block
);
6675 switch(instr
->intrinsic
) {
6676 case nir_intrinsic_group_memory_barrier
:
6677 case nir_intrinsic_memory_barrier
:
6678 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6680 case nir_intrinsic_memory_barrier_buffer
:
6681 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6683 case nir_intrinsic_memory_barrier_image
:
6684 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6686 case nir_intrinsic_memory_barrier_tcs_patch
:
6687 case nir_intrinsic_memory_barrier_shared
:
6688 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6691 unreachable("Unimplemented memory barrier intrinsic");
6696 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6698 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6699 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6700 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6701 Builder
bld(ctx
->program
, ctx
->block
);
6703 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6704 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6705 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6708 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6710 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6711 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6712 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6713 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6715 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6716 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6719 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6721 unsigned offset
= nir_intrinsic_base(instr
);
6722 Builder
bld(ctx
->program
, ctx
->block
);
6723 Operand m
= load_lds_size_m0(bld
);
6724 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6725 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6727 unsigned num_operands
= 3;
6728 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6729 switch(instr
->intrinsic
) {
6730 case nir_intrinsic_shared_atomic_add
:
6731 op32
= aco_opcode::ds_add_u32
;
6732 op64
= aco_opcode::ds_add_u64
;
6733 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6734 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6736 case nir_intrinsic_shared_atomic_imin
:
6737 op32
= aco_opcode::ds_min_i32
;
6738 op64
= aco_opcode::ds_min_i64
;
6739 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6740 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6742 case nir_intrinsic_shared_atomic_umin
:
6743 op32
= aco_opcode::ds_min_u32
;
6744 op64
= aco_opcode::ds_min_u64
;
6745 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6746 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6748 case nir_intrinsic_shared_atomic_imax
:
6749 op32
= aco_opcode::ds_max_i32
;
6750 op64
= aco_opcode::ds_max_i64
;
6751 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6752 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6754 case nir_intrinsic_shared_atomic_umax
:
6755 op32
= aco_opcode::ds_max_u32
;
6756 op64
= aco_opcode::ds_max_u64
;
6757 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6758 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6760 case nir_intrinsic_shared_atomic_and
:
6761 op32
= aco_opcode::ds_and_b32
;
6762 op64
= aco_opcode::ds_and_b64
;
6763 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6764 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6766 case nir_intrinsic_shared_atomic_or
:
6767 op32
= aco_opcode::ds_or_b32
;
6768 op64
= aco_opcode::ds_or_b64
;
6769 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6770 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6772 case nir_intrinsic_shared_atomic_xor
:
6773 op32
= aco_opcode::ds_xor_b32
;
6774 op64
= aco_opcode::ds_xor_b64
;
6775 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6776 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6778 case nir_intrinsic_shared_atomic_exchange
:
6779 op32
= aco_opcode::ds_write_b32
;
6780 op64
= aco_opcode::ds_write_b64
;
6781 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6782 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6784 case nir_intrinsic_shared_atomic_comp_swap
:
6785 op32
= aco_opcode::ds_cmpst_b32
;
6786 op64
= aco_opcode::ds_cmpst_b64
;
6787 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6788 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6792 unreachable("Unhandled shared atomic intrinsic");
6795 /* return the previous value if dest is ever used */
6796 bool return_previous
= false;
6797 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6798 return_previous
= true;
6801 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6802 return_previous
= true;
6807 if (data
.size() == 1) {
6808 assert(instr
->dest
.ssa
.bit_size
== 32);
6809 op
= return_previous
? op32_rtn
: op32
;
6811 assert(instr
->dest
.ssa
.bit_size
== 64);
6812 op
= return_previous
? op64_rtn
: op64
;
6815 if (offset
> 65535) {
6816 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6820 aco_ptr
<DS_instruction
> ds
;
6821 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6822 ds
->operands
[0] = Operand(address
);
6823 ds
->operands
[1] = Operand(data
);
6824 if (num_operands
== 4)
6825 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6826 ds
->operands
[num_operands
- 1] = m
;
6827 ds
->offset0
= offset
;
6828 if (return_previous
)
6829 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6830 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6833 Temp
get_scratch_resource(isel_context
*ctx
)
6835 Builder
bld(ctx
->program
, ctx
->block
);
6836 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6837 if (ctx
->stage
!= compute_cs
)
6838 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6840 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6841 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6843 if (ctx
->program
->chip_class
>= GFX10
) {
6844 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6845 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6846 S_008F0C_RESOURCE_LEVEL(1);
6847 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6848 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6849 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6852 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6853 if (ctx
->program
->chip_class
<= GFX8
)
6854 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6856 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6859 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6860 Builder
bld(ctx
->program
, ctx
->block
);
6861 Temp rsrc
= get_scratch_resource(ctx
);
6862 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6863 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6865 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6866 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6867 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6868 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6869 info
.swizzle_component_size
= 16;
6870 info
.can_reorder
= false;
6871 info
.soffset
= ctx
->program
->scratch_offset
;
6872 emit_mubuf_load(ctx
, bld
, &info
);
6875 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6876 Builder
bld(ctx
->program
, ctx
->block
);
6877 Temp rsrc
= get_scratch_resource(ctx
);
6878 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6879 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6881 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6882 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6884 unsigned write_count
= 0;
6885 Temp write_datas
[32];
6886 unsigned offsets
[32];
6887 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6888 16, &write_count
, write_datas
, offsets
);
6890 for (unsigned i
= 0; i
< write_count
; i
++) {
6891 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6892 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6896 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6897 uint8_t log2_ps_iter_samples
;
6898 if (ctx
->program
->info
->ps
.force_persample
) {
6899 log2_ps_iter_samples
=
6900 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6902 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6905 /* The bit pattern matches that used by fixed function fragment
6907 static const unsigned ps_iter_masks
[] = {
6908 0xffff, /* not used */
6914 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6916 Builder
bld(ctx
->program
, ctx
->block
);
6918 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6919 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6920 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6921 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6922 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6923 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6926 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6927 Builder
bld(ctx
->program
, ctx
->block
);
6929 unsigned stream
= nir_intrinsic_stream_id(instr
);
6930 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6931 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6932 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6935 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6937 unsigned num_components
=
6938 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6939 assert(num_components
);
6941 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6942 unsigned stream_offset
= 0;
6943 for (unsigned i
= 0; i
< stream
; i
++) {
6944 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6945 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6948 /* Limit on the stride field for <= GFX7. */
6949 assert(stride
< (1 << 14));
6951 Temp gsvs_dwords
[4];
6952 for (unsigned i
= 0; i
< 4; i
++)
6953 gsvs_dwords
[i
] = bld
.tmp(s1
);
6954 bld
.pseudo(aco_opcode::p_split_vector
,
6955 Definition(gsvs_dwords
[0]),
6956 Definition(gsvs_dwords
[1]),
6957 Definition(gsvs_dwords
[2]),
6958 Definition(gsvs_dwords
[3]),
6961 if (stream_offset
) {
6962 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6964 Temp carry
= bld
.tmp(s1
);
6965 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6966 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6969 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6970 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6972 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6973 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6975 unsigned offset
= 0;
6976 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6977 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6980 for (unsigned j
= 0; j
< 4; j
++) {
6981 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6984 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6985 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6986 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6987 if (const_offset
>= 4096u) {
6988 if (vaddr_offset
.isUndefined())
6989 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6991 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6992 const_offset
%= 4096u;
6995 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6996 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6997 mtbuf
->operands
[1] = vaddr_offset
;
6998 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6999 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7000 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7001 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7002 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7003 mtbuf
->offset
= const_offset
;
7006 mtbuf
->barrier
= barrier_gs_data
;
7007 mtbuf
->can_reorder
= true;
7008 bld
.insert(std::move(mtbuf
));
7011 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7014 /* outputs for the next vertex are undefined and keeping them around can
7015 * create invalid IR with control flow */
7016 ctx
->outputs
.mask
[i
] = 0;
7019 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7022 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7024 Builder
bld(ctx
->program
, ctx
->block
);
7026 if (cluster_size
== 1) {
7028 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7029 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7030 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7031 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7032 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7033 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7034 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7035 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7036 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7037 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7038 //subgroupAnd(val) -> (exec & ~val) == 0
7039 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7040 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7041 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7042 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7043 //subgroupOr(val) -> (val & exec) != 0
7044 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7045 return bool_to_vector_condition(ctx
, tmp
);
7046 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7047 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7048 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7049 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7050 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7051 return bool_to_vector_condition(ctx
, tmp
);
7053 //subgroupClustered{And,Or,Xor}(val, n) ->
7054 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7055 //cluster_offset = ~(n - 1) & lane_id
7056 //cluster_mask = ((1 << n) - 1)
7057 //subgroupClusteredAnd():
7058 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7059 //subgroupClusteredOr():
7060 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7061 //subgroupClusteredXor():
7062 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7063 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7064 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7067 if (op
== nir_op_iand
)
7068 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7070 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7072 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7074 if (ctx
->program
->chip_class
<= GFX7
)
7075 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7076 else if (ctx
->program
->wave_size
== 64)
7077 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7079 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7080 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7081 if (cluster_mask
!= 0xffffffff)
7082 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7084 Definition cmp_def
= Definition();
7085 if (op
== nir_op_iand
) {
7086 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7087 } else if (op
== nir_op_ior
) {
7088 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7089 } else if (op
== nir_op_ixor
) {
7090 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7091 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7092 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7094 cmp_def
.setHint(vcc
);
7095 return cmp_def
.getTemp();
7099 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7101 Builder
bld(ctx
->program
, ctx
->block
);
7103 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7104 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7105 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7107 if (op
== nir_op_iand
)
7108 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7110 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7112 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7113 Temp lo
= lohi
.def(0).getTemp();
7114 Temp hi
= lohi
.def(1).getTemp();
7115 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7117 Definition cmp_def
= Definition();
7118 if (op
== nir_op_iand
)
7119 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7120 else if (op
== nir_op_ior
)
7121 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7122 else if (op
== nir_op_ixor
)
7123 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7124 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7125 cmp_def
.setHint(vcc
);
7126 return cmp_def
.getTemp();
7129 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7131 Builder
bld(ctx
->program
, ctx
->block
);
7133 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7134 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7135 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7136 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7137 if (op
== nir_op_iand
)
7138 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7139 else if (op
== nir_op_ior
)
7140 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7141 else if (op
== nir_op_ixor
)
7142 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7148 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7150 Builder
bld(ctx
->program
, ctx
->block
);
7151 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7152 if (src
.regClass().type() == RegType::vgpr
) {
7153 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7154 } else if (src
.regClass() == s1
) {
7155 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7156 } else if (src
.regClass() == s2
) {
7157 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7159 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7160 nir_print_instr(&instr
->instr
, stderr
);
7161 fprintf(stderr
, "\n");
7165 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7167 Builder
bld(ctx
->program
, ctx
->block
);
7168 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7169 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7170 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7172 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7173 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7174 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7175 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7178 if (ctx
->program
->chip_class
>= GFX8
) {
7179 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7180 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7181 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7182 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7183 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7184 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7186 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7187 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7188 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7189 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7190 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7191 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7192 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7193 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7194 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7195 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7198 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7199 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7200 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7201 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7202 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7203 Temp wqm1
= bld
.tmp(v1
);
7204 emit_wqm(ctx
, tmp1
, wqm1
, true);
7205 Temp wqm2
= bld
.tmp(v1
);
7206 emit_wqm(ctx
, tmp2
, wqm2
, true);
7207 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7211 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7213 Builder
bld(ctx
->program
, ctx
->block
);
7214 switch(instr
->intrinsic
) {
7215 case nir_intrinsic_load_barycentric_sample
:
7216 case nir_intrinsic_load_barycentric_pixel
:
7217 case nir_intrinsic_load_barycentric_centroid
: {
7218 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7219 Temp bary
= Temp(0, s2
);
7221 case INTERP_MODE_SMOOTH
:
7222 case INTERP_MODE_NONE
:
7223 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7224 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7225 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7226 bary
= ctx
->persp_centroid
;
7227 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7228 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7230 case INTERP_MODE_NOPERSPECTIVE
:
7231 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7232 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7233 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7234 bary
= ctx
->linear_centroid
;
7235 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7236 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7241 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7242 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7243 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7244 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7245 Operand(p1
), Operand(p2
));
7246 emit_split_vector(ctx
, dst
, 2);
7249 case nir_intrinsic_load_barycentric_model
: {
7250 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7252 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7253 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7254 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7255 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7256 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7257 Operand(p1
), Operand(p2
), Operand(p3
));
7258 emit_split_vector(ctx
, dst
, 3);
7261 case nir_intrinsic_load_barycentric_at_sample
: {
7262 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7263 switch (ctx
->options
->key
.fs
.num_samples
) {
7264 case 2: sample_pos_offset
+= 1 << 3; break;
7265 case 4: sample_pos_offset
+= 3 << 3; break;
7266 case 8: sample_pos_offset
+= 7 << 3; break;
7270 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7271 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7272 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7273 if (addr
.type() == RegType::sgpr
) {
7276 sample_pos_offset
+= const_addr
->u32
<< 3;
7277 offset
= Operand(sample_pos_offset
);
7278 } else if (ctx
->options
->chip_class
>= GFX9
) {
7279 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7281 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7282 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7285 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7286 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7288 } else if (ctx
->options
->chip_class
>= GFX9
) {
7289 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7290 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7291 } else if (ctx
->options
->chip_class
>= GFX7
) {
7292 /* addr += private_segment_buffer + sample_pos_offset */
7293 Temp tmp0
= bld
.tmp(s1
);
7294 Temp tmp1
= bld
.tmp(s1
);
7295 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7296 Definition scc_tmp
= bld
.def(s1
, scc
);
7297 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7298 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7299 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7300 Temp pck0
= bld
.tmp(v1
);
7301 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7302 tmp1
= as_vgpr(ctx
, tmp1
);
7303 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7304 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7306 /* sample_pos = flat_load_dwordx2 addr */
7307 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7309 assert(ctx
->options
->chip_class
== GFX6
);
7311 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7312 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7313 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7315 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7316 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7318 sample_pos
= bld
.tmp(v2
);
7320 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7321 load
->definitions
[0] = Definition(sample_pos
);
7322 load
->operands
[0] = Operand(rsrc
);
7323 load
->operands
[1] = Operand(addr
);
7324 load
->operands
[2] = Operand(0u);
7325 load
->offset
= sample_pos_offset
;
7327 load
->addr64
= true;
7330 load
->disable_wqm
= false;
7331 load
->barrier
= barrier_none
;
7332 load
->can_reorder
= true;
7333 ctx
->block
->instructions
.emplace_back(std::move(load
));
7336 /* sample_pos -= 0.5 */
7337 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7338 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7339 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7340 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7341 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7343 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7346 case nir_intrinsic_load_barycentric_at_offset
: {
7347 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7348 RegClass rc
= RegClass(offset
.type(), 1);
7349 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7350 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7351 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7354 case nir_intrinsic_load_front_face
: {
7355 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7356 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7359 case nir_intrinsic_load_view_index
: {
7360 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7361 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7362 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7368 case nir_intrinsic_load_layer_id
: {
7369 unsigned idx
= nir_intrinsic_base(instr
);
7370 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7371 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7374 case nir_intrinsic_load_frag_coord
: {
7375 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7378 case nir_intrinsic_load_sample_pos
: {
7379 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7380 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7381 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7382 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7383 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7386 case nir_intrinsic_load_tess_coord
:
7387 visit_load_tess_coord(ctx
, instr
);
7389 case nir_intrinsic_load_interpolated_input
:
7390 visit_load_interpolated_input(ctx
, instr
);
7392 case nir_intrinsic_store_output
:
7393 visit_store_output(ctx
, instr
);
7395 case nir_intrinsic_load_input
:
7396 case nir_intrinsic_load_input_vertex
:
7397 visit_load_input(ctx
, instr
);
7399 case nir_intrinsic_load_output
:
7400 visit_load_output(ctx
, instr
);
7402 case nir_intrinsic_load_per_vertex_input
:
7403 visit_load_per_vertex_input(ctx
, instr
);
7405 case nir_intrinsic_load_per_vertex_output
:
7406 visit_load_per_vertex_output(ctx
, instr
);
7408 case nir_intrinsic_store_per_vertex_output
:
7409 visit_store_per_vertex_output(ctx
, instr
);
7411 case nir_intrinsic_load_ubo
:
7412 visit_load_ubo(ctx
, instr
);
7414 case nir_intrinsic_load_push_constant
:
7415 visit_load_push_constant(ctx
, instr
);
7417 case nir_intrinsic_load_constant
:
7418 visit_load_constant(ctx
, instr
);
7420 case nir_intrinsic_vulkan_resource_index
:
7421 visit_load_resource(ctx
, instr
);
7423 case nir_intrinsic_discard
:
7424 visit_discard(ctx
, instr
);
7426 case nir_intrinsic_discard_if
:
7427 visit_discard_if(ctx
, instr
);
7429 case nir_intrinsic_load_shared
:
7430 visit_load_shared(ctx
, instr
);
7432 case nir_intrinsic_store_shared
:
7433 visit_store_shared(ctx
, instr
);
7435 case nir_intrinsic_shared_atomic_add
:
7436 case nir_intrinsic_shared_atomic_imin
:
7437 case nir_intrinsic_shared_atomic_umin
:
7438 case nir_intrinsic_shared_atomic_imax
:
7439 case nir_intrinsic_shared_atomic_umax
:
7440 case nir_intrinsic_shared_atomic_and
:
7441 case nir_intrinsic_shared_atomic_or
:
7442 case nir_intrinsic_shared_atomic_xor
:
7443 case nir_intrinsic_shared_atomic_exchange
:
7444 case nir_intrinsic_shared_atomic_comp_swap
:
7445 visit_shared_atomic(ctx
, instr
);
7447 case nir_intrinsic_image_deref_load
:
7448 visit_image_load(ctx
, instr
);
7450 case nir_intrinsic_image_deref_store
:
7451 visit_image_store(ctx
, instr
);
7453 case nir_intrinsic_image_deref_atomic_add
:
7454 case nir_intrinsic_image_deref_atomic_umin
:
7455 case nir_intrinsic_image_deref_atomic_imin
:
7456 case nir_intrinsic_image_deref_atomic_umax
:
7457 case nir_intrinsic_image_deref_atomic_imax
:
7458 case nir_intrinsic_image_deref_atomic_and
:
7459 case nir_intrinsic_image_deref_atomic_or
:
7460 case nir_intrinsic_image_deref_atomic_xor
:
7461 case nir_intrinsic_image_deref_atomic_exchange
:
7462 case nir_intrinsic_image_deref_atomic_comp_swap
:
7463 visit_image_atomic(ctx
, instr
);
7465 case nir_intrinsic_image_deref_size
:
7466 visit_image_size(ctx
, instr
);
7468 case nir_intrinsic_load_ssbo
:
7469 visit_load_ssbo(ctx
, instr
);
7471 case nir_intrinsic_store_ssbo
:
7472 visit_store_ssbo(ctx
, instr
);
7474 case nir_intrinsic_load_global
:
7475 visit_load_global(ctx
, instr
);
7477 case nir_intrinsic_store_global
:
7478 visit_store_global(ctx
, instr
);
7480 case nir_intrinsic_global_atomic_add
:
7481 case nir_intrinsic_global_atomic_imin
:
7482 case nir_intrinsic_global_atomic_umin
:
7483 case nir_intrinsic_global_atomic_imax
:
7484 case nir_intrinsic_global_atomic_umax
:
7485 case nir_intrinsic_global_atomic_and
:
7486 case nir_intrinsic_global_atomic_or
:
7487 case nir_intrinsic_global_atomic_xor
:
7488 case nir_intrinsic_global_atomic_exchange
:
7489 case nir_intrinsic_global_atomic_comp_swap
:
7490 visit_global_atomic(ctx
, instr
);
7492 case nir_intrinsic_ssbo_atomic_add
:
7493 case nir_intrinsic_ssbo_atomic_imin
:
7494 case nir_intrinsic_ssbo_atomic_umin
:
7495 case nir_intrinsic_ssbo_atomic_imax
:
7496 case nir_intrinsic_ssbo_atomic_umax
:
7497 case nir_intrinsic_ssbo_atomic_and
:
7498 case nir_intrinsic_ssbo_atomic_or
:
7499 case nir_intrinsic_ssbo_atomic_xor
:
7500 case nir_intrinsic_ssbo_atomic_exchange
:
7501 case nir_intrinsic_ssbo_atomic_comp_swap
:
7502 visit_atomic_ssbo(ctx
, instr
);
7504 case nir_intrinsic_load_scratch
:
7505 visit_load_scratch(ctx
, instr
);
7507 case nir_intrinsic_store_scratch
:
7508 visit_store_scratch(ctx
, instr
);
7510 case nir_intrinsic_get_buffer_size
:
7511 visit_get_buffer_size(ctx
, instr
);
7513 case nir_intrinsic_control_barrier
: {
7514 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7515 /* GFX6 only (thanks to a hw bug workaround):
7516 * The real barrier instruction isn’t needed, because an entire patch
7517 * always fits into a single wave.
7522 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7523 bld
.sopp(aco_opcode::s_barrier
);
7527 case nir_intrinsic_memory_barrier_tcs_patch
:
7528 case nir_intrinsic_group_memory_barrier
:
7529 case nir_intrinsic_memory_barrier
:
7530 case nir_intrinsic_memory_barrier_buffer
:
7531 case nir_intrinsic_memory_barrier_image
:
7532 case nir_intrinsic_memory_barrier_shared
:
7533 emit_memory_barrier(ctx
, instr
);
7535 case nir_intrinsic_load_num_work_groups
: {
7536 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7537 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7538 emit_split_vector(ctx
, dst
, 3);
7541 case nir_intrinsic_load_local_invocation_id
: {
7542 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7543 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7544 emit_split_vector(ctx
, dst
, 3);
7547 case nir_intrinsic_load_work_group_id
: {
7548 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7549 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7550 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7551 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7552 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7553 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7554 emit_split_vector(ctx
, dst
, 3);
7557 case nir_intrinsic_load_local_invocation_index
: {
7558 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7560 /* The tg_size bits [6:11] contain the subgroup id,
7561 * we need this multiplied by the wave size, and then OR the thread id to it.
7563 if (ctx
->program
->wave_size
== 64) {
7564 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7565 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7566 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7567 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7569 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7570 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7571 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7572 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7576 case nir_intrinsic_load_subgroup_id
: {
7577 if (ctx
->stage
== compute_cs
) {
7578 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7579 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7581 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7585 case nir_intrinsic_load_subgroup_invocation
: {
7586 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7589 case nir_intrinsic_load_num_subgroups
: {
7590 if (ctx
->stage
== compute_cs
)
7591 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7592 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7594 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7597 case nir_intrinsic_ballot
: {
7598 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7599 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7600 Definition tmp
= bld
.def(dst
.regClass());
7601 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7602 if (instr
->src
[0].ssa
->bit_size
== 1) {
7603 assert(src
.regClass() == bld
.lm
);
7604 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7605 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7606 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7607 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7608 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7610 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7611 nir_print_instr(&instr
->instr
, stderr
);
7612 fprintf(stderr
, "\n");
7614 if (dst
.size() != bld
.lm
.size()) {
7615 /* Wave32 with ballot size set to 64 */
7616 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7618 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7621 case nir_intrinsic_shuffle
:
7622 case nir_intrinsic_read_invocation
: {
7623 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7624 if (!nir_src_is_divergent(instr
->src
[0])) {
7625 emit_uniform_subgroup(ctx
, instr
, src
);
7627 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7628 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7629 tid
= bld
.as_uniform(tid
);
7630 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7631 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7632 Temp tmp
= bld
.tmp(v1
);
7633 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7634 if (dst
.type() == RegType::vgpr
)
7635 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7637 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7638 } else if (src
.regClass() == v1
) {
7639 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7640 } else if (src
.regClass() == v2
) {
7641 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7642 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7643 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7644 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7645 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7646 emit_split_vector(ctx
, dst
, 2);
7647 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7648 assert(src
.regClass() == bld
.lm
);
7649 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7650 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7651 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7652 assert(src
.regClass() == bld
.lm
);
7654 if (ctx
->program
->chip_class
<= GFX7
)
7655 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7656 else if (ctx
->program
->wave_size
== 64)
7657 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7659 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7660 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7661 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7662 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7664 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7665 nir_print_instr(&instr
->instr
, stderr
);
7666 fprintf(stderr
, "\n");
7671 case nir_intrinsic_load_sample_id
: {
7672 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7673 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7676 case nir_intrinsic_load_sample_mask_in
: {
7677 visit_load_sample_mask_in(ctx
, instr
);
7680 case nir_intrinsic_read_first_invocation
: {
7681 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7682 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7683 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7685 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7687 } else if (src
.regClass() == v2
) {
7688 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7689 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7690 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7691 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7692 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7693 emit_split_vector(ctx
, dst
, 2);
7694 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7695 assert(src
.regClass() == bld
.lm
);
7696 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7697 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7698 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7699 } else if (src
.regClass() == s1
) {
7700 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7701 } else if (src
.regClass() == s2
) {
7702 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7704 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7705 nir_print_instr(&instr
->instr
, stderr
);
7706 fprintf(stderr
, "\n");
7710 case nir_intrinsic_vote_all
: {
7711 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7712 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7713 assert(src
.regClass() == bld
.lm
);
7714 assert(dst
.regClass() == bld
.lm
);
7716 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7717 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7718 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7721 case nir_intrinsic_vote_any
: {
7722 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7723 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7724 assert(src
.regClass() == bld
.lm
);
7725 assert(dst
.regClass() == bld
.lm
);
7727 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7728 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7731 case nir_intrinsic_reduce
:
7732 case nir_intrinsic_inclusive_scan
:
7733 case nir_intrinsic_exclusive_scan
: {
7734 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7735 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7736 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7737 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7738 nir_intrinsic_cluster_size(instr
) : 0;
7739 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7741 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7742 emit_uniform_subgroup(ctx
, instr
, src
);
7743 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7744 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7746 else if (op
== nir_op_iadd
)
7748 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7750 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7752 switch (instr
->intrinsic
) {
7753 case nir_intrinsic_reduce
:
7754 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7756 case nir_intrinsic_exclusive_scan
:
7757 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7759 case nir_intrinsic_inclusive_scan
:
7760 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7765 } else if (cluster_size
== 1) {
7766 bld
.copy(Definition(dst
), src
);
7768 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7770 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7774 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7775 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7790 unreachable("unknown reduction op");
7796 switch (instr
->intrinsic
) {
7797 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7798 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7799 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7801 unreachable("unknown reduce intrinsic");
7804 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7805 reduce
->operands
[0] = Operand(src
);
7806 // filled in by aco_reduce_assign.cpp, used internally as part of the
7808 assert(dst
.size() == 1 || dst
.size() == 2);
7809 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7810 reduce
->operands
[2] = Operand(v1
.as_linear());
7812 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7813 reduce
->definitions
[0] = Definition(tmp_dst
);
7814 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7815 reduce
->definitions
[2] = Definition();
7816 reduce
->definitions
[3] = Definition(scc
, s1
);
7817 reduce
->definitions
[4] = Definition();
7818 reduce
->reduce_op
= reduce_op
;
7819 reduce
->cluster_size
= cluster_size
;
7820 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7822 emit_wqm(ctx
, tmp_dst
, dst
);
7826 case nir_intrinsic_quad_broadcast
: {
7827 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7828 if (!nir_dest_is_divergent(instr
->dest
)) {
7829 emit_uniform_subgroup(ctx
, instr
, src
);
7831 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7832 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7833 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7835 if (instr
->dest
.ssa
.bit_size
== 1) {
7836 assert(src
.regClass() == bld
.lm
);
7837 assert(dst
.regClass() == bld
.lm
);
7838 uint32_t half_mask
= 0x11111111u
<< lane
;
7839 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7840 Temp tmp
= bld
.tmp(bld
.lm
);
7841 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7842 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7843 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7844 emit_wqm(ctx
, tmp
, dst
);
7845 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7846 Temp tmp
= bld
.tmp(v1
);
7847 if (ctx
->program
->chip_class
>= GFX8
)
7848 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7850 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7851 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7852 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7853 Temp tmp
= bld
.tmp(v1
);
7854 if (ctx
->program
->chip_class
>= GFX8
)
7855 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7857 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7858 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7859 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7860 if (ctx
->program
->chip_class
>= GFX8
)
7861 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7863 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7864 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7865 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7867 if (ctx
->program
->chip_class
>= GFX8
) {
7868 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7869 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7871 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7872 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7874 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7875 emit_split_vector(ctx
, dst
, 2);
7877 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7878 nir_print_instr(&instr
->instr
, stderr
);
7879 fprintf(stderr
, "\n");
7884 case nir_intrinsic_quad_swap_horizontal
:
7885 case nir_intrinsic_quad_swap_vertical
:
7886 case nir_intrinsic_quad_swap_diagonal
:
7887 case nir_intrinsic_quad_swizzle_amd
: {
7888 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7889 if (!nir_dest_is_divergent(instr
->dest
)) {
7890 emit_uniform_subgroup(ctx
, instr
, src
);
7893 uint16_t dpp_ctrl
= 0;
7894 switch (instr
->intrinsic
) {
7895 case nir_intrinsic_quad_swap_horizontal
:
7896 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7898 case nir_intrinsic_quad_swap_vertical
:
7899 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7901 case nir_intrinsic_quad_swap_diagonal
:
7902 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7904 case nir_intrinsic_quad_swizzle_amd
:
7905 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7910 if (ctx
->program
->chip_class
< GFX8
)
7911 dpp_ctrl
|= (1 << 15);
7913 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7914 if (instr
->dest
.ssa
.bit_size
== 1) {
7915 assert(src
.regClass() == bld
.lm
);
7916 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7917 if (ctx
->program
->chip_class
>= GFX8
)
7918 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7920 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7921 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7922 emit_wqm(ctx
, tmp
, dst
);
7923 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7924 Temp tmp
= bld
.tmp(v1
);
7925 if (ctx
->program
->chip_class
>= GFX8
)
7926 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7928 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7929 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7930 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7931 Temp tmp
= bld
.tmp(v1
);
7932 if (ctx
->program
->chip_class
>= GFX8
)
7933 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7935 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7936 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7937 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7939 if (ctx
->program
->chip_class
>= GFX8
)
7940 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7942 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7943 emit_wqm(ctx
, tmp
, dst
);
7944 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7945 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7946 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7947 if (ctx
->program
->chip_class
>= GFX8
) {
7948 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7949 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7951 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7952 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7954 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7955 emit_split_vector(ctx
, dst
, 2);
7957 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7958 nir_print_instr(&instr
->instr
, stderr
);
7959 fprintf(stderr
, "\n");
7963 case nir_intrinsic_masked_swizzle_amd
: {
7964 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7965 if (!nir_dest_is_divergent(instr
->dest
)) {
7966 emit_uniform_subgroup(ctx
, instr
, src
);
7969 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7970 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7971 if (instr
->dest
.ssa
.bit_size
== 1) {
7972 assert(src
.regClass() == bld
.lm
);
7973 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7974 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7975 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7976 emit_wqm(ctx
, tmp
, dst
);
7977 } else if (dst
.regClass() == v1b
) {
7978 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7979 emit_extract_vector(ctx
, tmp
, 0, dst
);
7980 } else if (dst
.regClass() == v2b
) {
7981 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7982 emit_extract_vector(ctx
, tmp
, 0, dst
);
7983 } else if (dst
.regClass() == v1
) {
7984 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7985 } else if (dst
.regClass() == v2
) {
7986 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7987 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7988 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7989 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7990 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7991 emit_split_vector(ctx
, dst
, 2);
7993 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7994 nir_print_instr(&instr
->instr
, stderr
);
7995 fprintf(stderr
, "\n");
7999 case nir_intrinsic_write_invocation_amd
: {
8000 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8001 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8002 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8003 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8004 if (dst
.regClass() == v1
) {
8005 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8006 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8007 } else if (dst
.regClass() == v2
) {
8008 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8009 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8010 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8011 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8012 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8013 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8014 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8015 emit_split_vector(ctx
, dst
, 2);
8017 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8018 nir_print_instr(&instr
->instr
, stderr
);
8019 fprintf(stderr
, "\n");
8023 case nir_intrinsic_mbcnt_amd
: {
8024 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8025 RegClass rc
= RegClass(src
.type(), 1);
8026 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8027 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8028 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8029 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8030 emit_wqm(ctx
, wqm_tmp
, dst
);
8033 case nir_intrinsic_load_helper_invocation
: {
8034 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8035 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8036 ctx
->block
->kind
|= block_kind_needs_lowering
;
8037 ctx
->program
->needs_exact
= true;
8040 case nir_intrinsic_is_helper_invocation
: {
8041 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8042 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8043 ctx
->block
->kind
|= block_kind_needs_lowering
;
8044 ctx
->program
->needs_exact
= true;
8047 case nir_intrinsic_demote
:
8048 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8050 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8051 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8052 ctx
->block
->kind
|= block_kind_uses_demote
;
8053 ctx
->program
->needs_exact
= true;
8055 case nir_intrinsic_demote_if
: {
8056 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8057 assert(src
.regClass() == bld
.lm
);
8058 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8059 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8061 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8062 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8063 ctx
->block
->kind
|= block_kind_uses_demote
;
8064 ctx
->program
->needs_exact
= true;
8067 case nir_intrinsic_first_invocation
: {
8068 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8069 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8072 case nir_intrinsic_shader_clock
: {
8074 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8075 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8076 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8077 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8080 case nir_intrinsic_load_vertex_id_zero_base
: {
8081 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8082 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8085 case nir_intrinsic_load_first_vertex
: {
8086 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8087 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8090 case nir_intrinsic_load_base_instance
: {
8091 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8092 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8095 case nir_intrinsic_load_instance_id
: {
8096 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8097 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8100 case nir_intrinsic_load_draw_id
: {
8101 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8102 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8105 case nir_intrinsic_load_invocation_id
: {
8106 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8108 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8109 if (ctx
->options
->chip_class
>= GFX10
)
8110 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8112 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8113 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8114 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8115 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8117 unreachable("Unsupported stage for load_invocation_id");
8122 case nir_intrinsic_load_primitive_id
: {
8123 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8125 switch (ctx
->shader
->info
.stage
) {
8126 case MESA_SHADER_GEOMETRY
:
8127 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8129 case MESA_SHADER_TESS_CTRL
:
8130 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8132 case MESA_SHADER_TESS_EVAL
:
8133 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8136 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8141 case nir_intrinsic_load_patch_vertices_in
: {
8142 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8143 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8145 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8146 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8149 case nir_intrinsic_emit_vertex_with_counter
: {
8150 visit_emit_vertex_with_counter(ctx
, instr
);
8153 case nir_intrinsic_end_primitive_with_counter
: {
8154 unsigned stream
= nir_intrinsic_stream_id(instr
);
8155 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8158 case nir_intrinsic_set_vertex_count
: {
8159 /* unused, the HW keeps track of this for us */
8163 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8164 nir_print_instr(&instr
->instr
, stderr
);
8165 fprintf(stderr
, "\n");
8173 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8174 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8175 enum glsl_base_type
*stype
)
8177 nir_deref_instr
*texture_deref_instr
= NULL
;
8178 nir_deref_instr
*sampler_deref_instr
= NULL
;
8181 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8182 switch (instr
->src
[i
].src_type
) {
8183 case nir_tex_src_texture_deref
:
8184 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8186 case nir_tex_src_sampler_deref
:
8187 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8189 case nir_tex_src_plane
:
8190 plane
= nir_src_as_int(instr
->src
[i
].src
);
8197 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8199 if (!sampler_deref_instr
)
8200 sampler_deref_instr
= texture_deref_instr
;
8203 assert(instr
->op
!= nir_texop_txf_ms
&&
8204 instr
->op
!= nir_texop_samples_identical
);
8205 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8206 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8207 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8208 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8209 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8210 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8212 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8215 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8217 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8218 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8219 Builder
bld(ctx
->program
, ctx
->block
);
8221 /* to avoid unnecessary moves, we split and recombine sampler and image */
8222 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8223 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8224 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8225 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8226 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8227 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8228 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8229 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8231 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8232 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8233 img
[0], img
[1], img
[2], img
[3],
8234 img
[4], img
[5], img
[6], img
[7]);
8235 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8236 samp
[0], samp
[1], samp
[2], samp
[3]);
8239 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8240 instr
->op
== nir_texop_samples_identical
))
8241 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8244 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8245 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8247 Builder
bld(ctx
->program
, ctx
->block
);
8249 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8250 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8251 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8253 Operand
neg_one(0xbf800000u
);
8254 Operand
one(0x3f800000u
);
8255 Operand
two(0x40000000u
);
8256 Operand
four(0x40800000u
);
8258 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8259 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8260 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8262 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8263 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8264 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8265 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8268 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8269 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8270 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8272 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8275 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8276 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8277 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8280 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8281 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8283 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8284 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8287 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8289 Builder
bld(ctx
->program
, ctx
->block
);
8290 Temp ma
, tc
, sc
, id
;
8293 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8295 // see comment in ac_prepare_cube_coords()
8296 if (ctx
->options
->chip_class
<= GFX8
)
8297 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8300 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8302 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8303 vop3a
->operands
[0] = Operand(ma
);
8304 vop3a
->abs
[0] = true;
8305 Temp invma
= bld
.tmp(v1
);
8306 vop3a
->definitions
[0] = Definition(invma
);
8307 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8309 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8311 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8313 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8315 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8317 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8320 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8321 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8323 for (unsigned i
= 0; i
< 2; i
++) {
8324 // see comment in ac_prepare_cube_coords()
8326 Temp deriv_sc
, deriv_tc
;
8327 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8328 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8330 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8332 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8333 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8334 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8335 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8336 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8337 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8338 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8341 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8342 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8346 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8353 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8355 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8357 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8358 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8361 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8362 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8363 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8367 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8369 Builder
bld(ctx
->program
, ctx
->block
);
8370 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8371 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8372 has_clamped_lod
= false;
8373 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8374 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8375 clamped_lod
= Temp();
8376 std::vector
<Temp
> coords
;
8377 std::vector
<Temp
> derivs
;
8378 nir_const_value
*sample_index_cv
= NULL
;
8379 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8380 enum glsl_base_type stype
;
8381 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8383 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8384 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8385 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8386 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8388 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8389 switch (instr
->src
[i
].src_type
) {
8390 case nir_tex_src_coord
: {
8391 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8392 for (unsigned i
= 0; i
< coord
.size(); i
++)
8393 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8396 case nir_tex_src_bias
:
8397 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8400 case nir_tex_src_lod
: {
8401 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8403 if (val
&& val
->f32
<= 0.0) {
8406 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8411 case nir_tex_src_min_lod
:
8412 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8413 has_clamped_lod
= true;
8415 case nir_tex_src_comparator
:
8416 if (instr
->is_shadow
) {
8417 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8421 case nir_tex_src_offset
:
8422 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8423 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8426 case nir_tex_src_ddx
:
8427 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8430 case nir_tex_src_ddy
:
8431 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8434 case nir_tex_src_ms_index
:
8435 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8436 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8437 has_sample_index
= true;
8439 case nir_tex_src_texture_offset
:
8440 case nir_tex_src_sampler_offset
:
8446 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8447 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8449 if (instr
->op
== nir_texop_texture_samples
) {
8450 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8452 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8453 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8454 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8456 Operand default_sample
= Operand(1u);
8457 if (ctx
->options
->robust_buffer_access
) {
8458 /* Extract the second dword of the descriptor, if it's
8459 * all zero, then it's a null descriptor.
8461 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8462 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8463 default_sample
= Operand(is_non_null_descriptor
);
8466 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8467 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8468 samples
, default_sample
, bld
.scc(is_msaa
));
8472 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8473 aco_ptr
<Instruction
> tmp_instr
;
8474 Temp acc
, pack
= Temp();
8476 uint32_t pack_const
= 0;
8477 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8478 if (!const_offset
[i
])
8480 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8483 if (offset
.type() == RegType::sgpr
) {
8484 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8485 if (const_offset
[i
])
8488 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8489 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8492 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8495 if (pack
== Temp()) {
8498 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8502 if (pack_const
&& pack
!= Temp())
8503 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8505 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8506 if (const_offset
[i
])
8509 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8510 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8513 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8516 if (pack
== Temp()) {
8519 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8523 if (pack_const
&& pack
!= Temp())
8524 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8526 if (pack_const
&& pack
== Temp())
8527 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8528 else if (pack
== Temp())
8534 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8535 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8537 /* pack derivatives */
8538 if (has_ddx
|| has_ddy
) {
8539 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8540 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8541 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8542 derivs
= {ddx
, zero
, ddy
, zero
};
8544 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8545 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8546 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8547 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8552 if (instr
->coord_components
> 1 &&
8553 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8555 instr
->op
!= nir_texop_txf
)
8556 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8558 if (instr
->coord_components
> 2 &&
8559 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8560 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8561 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8562 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8564 instr
->op
!= nir_texop_txf
&&
8565 instr
->op
!= nir_texop_txf_ms
&&
8566 instr
->op
!= nir_texop_fragment_fetch
&&
8567 instr
->op
!= nir_texop_fragment_mask_fetch
)
8568 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8570 if (ctx
->options
->chip_class
== GFX9
&&
8571 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8572 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8573 assert(coords
.size() > 0 && coords
.size() < 3);
8575 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8576 Operand((uint32_t) 0) :
8577 Operand((uint32_t) 0x3f000000)));
8580 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8582 if (instr
->op
== nir_texop_samples_identical
)
8583 resource
= fmask_ptr
;
8585 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8586 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8587 instr
->op
!= nir_texop_txs
&&
8588 instr
->op
!= nir_texop_fragment_fetch
&&
8589 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8590 assert(has_sample_index
);
8591 Operand
op(sample_index
);
8592 if (sample_index_cv
)
8593 op
= Operand(sample_index_cv
->u32
);
8594 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8597 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8598 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8599 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8600 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8605 /* Build tex instruction */
8606 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8607 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8608 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8610 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8613 /* gather4 selects the component by dmask and always returns vec4 */
8614 if (instr
->op
== nir_texop_tg4
) {
8615 assert(instr
->dest
.ssa
.num_components
== 4);
8616 if (instr
->is_shadow
)
8619 dmask
= 1 << instr
->component
;
8620 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8621 tmp_dst
= bld
.tmp(v4
);
8622 } else if (instr
->op
== nir_texop_samples_identical
) {
8623 tmp_dst
= bld
.tmp(v1
);
8624 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8625 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8628 aco_ptr
<MIMG_instruction
> tex
;
8629 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8631 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8633 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8634 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8637 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8638 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8640 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8641 tex
->operands
[0] = Operand(resource
);
8642 tex
->operands
[1] = Operand(s4
); /* no sampler */
8643 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8644 if (ctx
->options
->chip_class
== GFX9
&&
8645 instr
->op
== nir_texop_txs
&&
8646 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8648 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8649 } else if (instr
->op
== nir_texop_query_levels
) {
8650 tex
->dmask
= 1 << 3;
8655 tex
->definitions
[0] = Definition(tmp_dst
);
8657 tex
->can_reorder
= true;
8658 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8661 /* divide 3rd value by 6 by multiplying with magic number */
8662 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8663 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8664 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8665 assert(instr
->dest
.ssa
.num_components
== 3);
8666 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8667 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8668 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8669 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8674 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8678 Temp tg4_compare_cube_wa64
= Temp();
8680 if (tg4_integer_workarounds
) {
8681 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8682 tex
->operands
[0] = Operand(resource
);
8683 tex
->operands
[1] = Operand(s4
); /* no sampler */
8684 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8688 Temp size
= bld
.tmp(v2
);
8689 tex
->definitions
[0] = Definition(size
);
8690 tex
->can_reorder
= true;
8691 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8692 emit_split_vector(ctx
, size
, size
.size());
8695 for (unsigned i
= 0; i
< 2; i
++) {
8696 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8697 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8698 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8699 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8702 Temp new_coords
[2] = {
8703 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8704 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8707 if (tg4_integer_cube_workaround
) {
8708 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8709 Temp desc
[resource
.size()];
8710 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8711 Format::PSEUDO
, 1, resource
.size())};
8712 split
->operands
[0] = Operand(resource
);
8713 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8714 desc
[i
] = bld
.tmp(s1
);
8715 split
->definitions
[i
] = Definition(desc
[i
]);
8717 ctx
->block
->instructions
.emplace_back(std::move(split
));
8719 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8720 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8721 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8724 if (stype
== GLSL_TYPE_UINT
) {
8725 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8726 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8727 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8728 bld
.scc(compare_cube_wa
));
8730 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8731 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8732 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8733 bld
.scc(compare_cube_wa
));
8735 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8736 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8738 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8740 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8741 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8742 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8744 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8745 Format::PSEUDO
, resource
.size(), 1)};
8746 for (unsigned i
= 0; i
< resource
.size(); i
++)
8747 vec
->operands
[i
] = Operand(desc
[i
]);
8748 resource
= bld
.tmp(resource
.regClass());
8749 vec
->definitions
[0] = Definition(resource
);
8750 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8752 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8753 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8754 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8755 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8757 coords
[0] = new_coords
[0];
8758 coords
[1] = new_coords
[1];
8761 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8762 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8764 assert(coords
.size() == 1);
8765 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8769 op
= aco_opcode::buffer_load_format_x
; break;
8771 op
= aco_opcode::buffer_load_format_xy
; break;
8773 op
= aco_opcode::buffer_load_format_xyz
; break;
8775 op
= aco_opcode::buffer_load_format_xyzw
; break;
8777 unreachable("Tex instruction loads more than 4 components.");
8780 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8781 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8784 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8786 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8787 mubuf
->operands
[0] = Operand(resource
);
8788 mubuf
->operands
[1] = Operand(coords
[0]);
8789 mubuf
->operands
[2] = Operand((uint32_t) 0);
8790 mubuf
->definitions
[0] = Definition(tmp_dst
);
8791 mubuf
->idxen
= true;
8792 mubuf
->can_reorder
= true;
8793 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8795 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8799 /* gather MIMG address components */
8800 std::vector
<Temp
> args
;
8802 args
.emplace_back(offset
);
8804 args
.emplace_back(bias
);
8806 args
.emplace_back(compare
);
8808 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8810 args
.insert(args
.end(), coords
.begin(), coords
.end());
8811 if (has_sample_index
)
8812 args
.emplace_back(sample_index
);
8814 args
.emplace_back(lod
);
8815 if (has_clamped_lod
)
8816 args
.emplace_back(clamped_lod
);
8818 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8819 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8820 vec
->definitions
[0] = Definition(arg
);
8821 for (unsigned i
= 0; i
< args
.size(); i
++)
8822 vec
->operands
[i
] = Operand(args
[i
]);
8823 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8826 if (instr
->op
== nir_texop_txf
||
8827 instr
->op
== nir_texop_txf_ms
||
8828 instr
->op
== nir_texop_samples_identical
||
8829 instr
->op
== nir_texop_fragment_fetch
||
8830 instr
->op
== nir_texop_fragment_mask_fetch
) {
8831 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8832 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8833 tex
->operands
[0] = Operand(resource
);
8834 tex
->operands
[1] = Operand(s4
); /* no sampler */
8835 tex
->operands
[2] = Operand(arg
);
8840 tex
->definitions
[0] = Definition(tmp_dst
);
8841 tex
->can_reorder
= true;
8842 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8844 if (instr
->op
== nir_texop_samples_identical
) {
8845 assert(dmask
== 1 && dst
.regClass() == v1
);
8846 assert(dst
.id() != tmp_dst
.id());
8848 Temp tmp
= bld
.tmp(bld
.lm
);
8849 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8850 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8853 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8858 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8859 aco_opcode opcode
= aco_opcode::image_sample
;
8860 if (has_offset
) { /* image_sample_*_o */
8861 if (has_clamped_lod
) {
8863 opcode
= aco_opcode::image_sample_c_cl_o
;
8865 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8867 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8869 opcode
= aco_opcode::image_sample_cl_o
;
8871 opcode
= aco_opcode::image_sample_d_cl_o
;
8873 opcode
= aco_opcode::image_sample_b_cl_o
;
8875 } else if (has_compare
) {
8876 opcode
= aco_opcode::image_sample_c_o
;
8878 opcode
= aco_opcode::image_sample_c_d_o
;
8880 opcode
= aco_opcode::image_sample_c_b_o
;
8882 opcode
= aco_opcode::image_sample_c_lz_o
;
8884 opcode
= aco_opcode::image_sample_c_l_o
;
8886 opcode
= aco_opcode::image_sample_o
;
8888 opcode
= aco_opcode::image_sample_d_o
;
8890 opcode
= aco_opcode::image_sample_b_o
;
8892 opcode
= aco_opcode::image_sample_lz_o
;
8894 opcode
= aco_opcode::image_sample_l_o
;
8896 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8898 opcode
= aco_opcode::image_sample_c_cl
;
8900 opcode
= aco_opcode::image_sample_c_d_cl
;
8902 opcode
= aco_opcode::image_sample_c_b_cl
;
8904 opcode
= aco_opcode::image_sample_cl
;
8906 opcode
= aco_opcode::image_sample_d_cl
;
8908 opcode
= aco_opcode::image_sample_b_cl
;
8910 } else { /* no offset */
8912 opcode
= aco_opcode::image_sample_c
;
8914 opcode
= aco_opcode::image_sample_c_d
;
8916 opcode
= aco_opcode::image_sample_c_b
;
8918 opcode
= aco_opcode::image_sample_c_lz
;
8920 opcode
= aco_opcode::image_sample_c_l
;
8922 opcode
= aco_opcode::image_sample
;
8924 opcode
= aco_opcode::image_sample_d
;
8926 opcode
= aco_opcode::image_sample_b
;
8928 opcode
= aco_opcode::image_sample_lz
;
8930 opcode
= aco_opcode::image_sample_l
;
8934 if (instr
->op
== nir_texop_tg4
) {
8935 if (has_offset
) { /* image_gather4_*_o */
8937 opcode
= aco_opcode::image_gather4_c_lz_o
;
8939 opcode
= aco_opcode::image_gather4_c_l_o
;
8941 opcode
= aco_opcode::image_gather4_c_b_o
;
8943 opcode
= aco_opcode::image_gather4_lz_o
;
8945 opcode
= aco_opcode::image_gather4_l_o
;
8947 opcode
= aco_opcode::image_gather4_b_o
;
8951 opcode
= aco_opcode::image_gather4_c_lz
;
8953 opcode
= aco_opcode::image_gather4_c_l
;
8955 opcode
= aco_opcode::image_gather4_c_b
;
8957 opcode
= aco_opcode::image_gather4_lz
;
8959 opcode
= aco_opcode::image_gather4_l
;
8961 opcode
= aco_opcode::image_gather4_b
;
8964 } else if (instr
->op
== nir_texop_lod
) {
8965 opcode
= aco_opcode::image_get_lod
;
8968 /* we don't need the bias, sample index, compare value or offset to be
8969 * computed in WQM but if the p_create_vector copies the coordinates, then it
8970 * needs to be in WQM */
8971 if (ctx
->stage
== fragment_fs
&&
8972 !has_derivs
&& !has_lod
&& !level_zero
&&
8973 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8974 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8975 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8977 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8978 tex
->operands
[0] = Operand(resource
);
8979 tex
->operands
[1] = Operand(sampler
);
8980 tex
->operands
[2] = Operand(arg
);
8984 tex
->definitions
[0] = Definition(tmp_dst
);
8985 tex
->can_reorder
= true;
8986 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8988 if (tg4_integer_cube_workaround
) {
8989 assert(tmp_dst
.id() != dst
.id());
8990 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8992 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8994 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8995 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8997 if (stype
== GLSL_TYPE_UINT
)
8998 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
9000 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
9001 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
9003 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
9004 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
9005 val
[0], val
[1], val
[2], val
[3]);
9007 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
9008 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
9013 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
9015 Temp tmp
= get_ssa_temp(ctx
, ssa
);
9016 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
9018 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
9019 if (ctx
->program
->wave_size
== 64)
9020 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
9022 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
9024 return Operand(tmp
);
9028 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9030 aco_ptr
<Pseudo_instruction
> phi
;
9031 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9032 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9034 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
9035 logical
|= ctx
->block
->kind
& block_kind_merge
;
9036 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9038 /* we want a sorted list of sources, since the predecessor list is also sorted */
9039 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9040 nir_foreach_phi_src(src
, instr
)
9041 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9043 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9044 unsigned num_operands
= 0;
9045 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9046 unsigned num_defined
= 0;
9047 unsigned cur_pred_idx
= 0;
9048 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9049 if (cur_pred_idx
< preds
.size()) {
9050 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9051 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9052 unsigned skipped
= 0;
9053 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9055 if (cur_pred_idx
+ skipped
< preds
.size()) {
9056 for (unsigned i
= 0; i
< skipped
; i
++)
9057 operands
[num_operands
++] = Operand(dst
.regClass());
9058 cur_pred_idx
+= skipped
;
9063 /* Handle missing predecessors at the end. This shouldn't happen with loop
9064 * headers and we can't ignore these sources for loop header phis. */
9065 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9068 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9069 operands
[num_operands
++] = op
;
9070 num_defined
+= !op
.isUndefined();
9072 /* handle block_kind_continue_or_break at loop exit blocks */
9073 while (cur_pred_idx
++ < preds
.size())
9074 operands
[num_operands
++] = Operand(dst
.regClass());
9076 /* If the loop ends with a break, still add a linear continue edge in case
9077 * that break is divergent or continue_or_break is used. We'll either remove
9078 * this operand later in visit_loop() if it's not necessary or replace the
9079 * undef with something correct. */
9080 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9081 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9082 nir_block
*last
= nir_loop_last_block(loop
);
9083 if (last
->successors
[0] != instr
->instr
.block
)
9084 operands
[num_operands
++] = Operand(RegClass());
9087 if (num_defined
== 0) {
9088 Builder
bld(ctx
->program
, ctx
->block
);
9089 if (dst
.regClass() == s1
) {
9090 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9091 } else if (dst
.regClass() == v1
) {
9092 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9094 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9095 for (unsigned i
= 0; i
< dst
.size(); i
++)
9096 vec
->operands
[i
] = Operand(0u);
9097 vec
->definitions
[0] = Definition(dst
);
9098 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9103 /* we can use a linear phi in some cases if one src is undef */
9104 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9105 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9107 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9108 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9109 assert(invert
->kind
& block_kind_invert
);
9111 unsigned then_block
= invert
->linear_preds
[0];
9113 Block
* insert_block
= NULL
;
9114 for (unsigned i
= 0; i
< num_operands
; i
++) {
9115 Operand op
= operands
[i
];
9116 if (op
.isUndefined())
9118 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9119 phi
->operands
[0] = op
;
9122 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9123 phi
->operands
[1] = Operand(dst
.regClass());
9124 phi
->definitions
[0] = Definition(dst
);
9125 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9129 /* try to scalarize vector phis */
9130 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9131 // TODO: scalarize linear phis on divergent ifs
9132 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9133 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9134 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9135 Operand src
= operands
[i
];
9136 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9137 can_scalarize
= false;
9139 if (can_scalarize
) {
9140 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9141 assert(dst
.size() % num_components
== 0);
9142 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9144 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9145 for (unsigned k
= 0; k
< num_components
; k
++) {
9146 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9147 for (unsigned i
= 0; i
< num_operands
; i
++) {
9148 Operand src
= operands
[i
];
9149 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9151 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9152 phi
->definitions
[0] = Definition(phi_dst
);
9153 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9154 new_vec
[k
] = phi_dst
;
9155 vec
->operands
[k
] = Operand(phi_dst
);
9157 vec
->definitions
[0] = Definition(dst
);
9158 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9159 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9164 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9165 for (unsigned i
= 0; i
< num_operands
; i
++)
9166 phi
->operands
[i
] = operands
[i
];
9167 phi
->definitions
[0] = Definition(dst
);
9168 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9172 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9174 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9176 assert(dst
.type() == RegType::sgpr
);
9178 if (dst
.size() == 1) {
9179 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9181 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9182 for (unsigned i
= 0; i
< dst
.size(); i
++)
9183 vec
->operands
[i
] = Operand(0u);
9184 vec
->definitions
[0] = Definition(dst
);
9185 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9189 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9191 Builder
bld(ctx
->program
, ctx
->block
);
9192 Block
*logical_target
;
9193 append_logical_end(ctx
->block
);
9194 unsigned idx
= ctx
->block
->index
;
9196 switch (instr
->type
) {
9197 case nir_jump_break
:
9198 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9199 add_logical_edge(idx
, logical_target
);
9200 ctx
->block
->kind
|= block_kind_break
;
9202 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9203 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9204 /* uniform break - directly jump out of the loop */
9205 ctx
->block
->kind
|= block_kind_uniform
;
9206 ctx
->cf_info
.has_branch
= true;
9207 bld
.branch(aco_opcode::p_branch
);
9208 add_linear_edge(idx
, logical_target
);
9211 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9212 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9214 case nir_jump_continue
:
9215 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9216 add_logical_edge(idx
, logical_target
);
9217 ctx
->block
->kind
|= block_kind_continue
;
9219 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9220 /* for potential uniform breaks after this continue,
9221 we must ensure that they are handled correctly */
9222 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9223 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9224 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9226 /* uniform continue - directly jump to the loop header */
9227 ctx
->block
->kind
|= block_kind_uniform
;
9228 ctx
->cf_info
.has_branch
= true;
9229 bld
.branch(aco_opcode::p_branch
);
9230 add_linear_edge(idx
, logical_target
);
9235 fprintf(stderr
, "Unknown NIR jump instr: ");
9236 nir_print_instr(&instr
->instr
, stderr
);
9237 fprintf(stderr
, "\n");
9241 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9242 ctx
->cf_info
.exec_potentially_empty_break
= true;
9243 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9246 /* remove critical edges from linear CFG */
9247 bld
.branch(aco_opcode::p_branch
);
9248 Block
* break_block
= ctx
->program
->create_and_insert_block();
9249 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9250 break_block
->kind
|= block_kind_uniform
;
9251 add_linear_edge(idx
, break_block
);
9252 /* the loop_header pointer might be invalidated by this point */
9253 if (instr
->type
== nir_jump_continue
)
9254 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9255 add_linear_edge(break_block
->index
, logical_target
);
9256 bld
.reset(break_block
);
9257 bld
.branch(aco_opcode::p_branch
);
9259 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9260 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9261 add_linear_edge(idx
, continue_block
);
9262 append_logical_start(continue_block
);
9263 ctx
->block
= continue_block
;
9267 void visit_block(isel_context
*ctx
, nir_block
*block
)
9269 nir_foreach_instr(instr
, block
) {
9270 switch (instr
->type
) {
9271 case nir_instr_type_alu
:
9272 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9274 case nir_instr_type_load_const
:
9275 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9277 case nir_instr_type_intrinsic
:
9278 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9280 case nir_instr_type_tex
:
9281 visit_tex(ctx
, nir_instr_as_tex(instr
));
9283 case nir_instr_type_phi
:
9284 visit_phi(ctx
, nir_instr_as_phi(instr
));
9286 case nir_instr_type_ssa_undef
:
9287 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9289 case nir_instr_type_deref
:
9291 case nir_instr_type_jump
:
9292 visit_jump(ctx
, nir_instr_as_jump(instr
));
9295 fprintf(stderr
, "Unknown NIR instr type: ");
9296 nir_print_instr(instr
, stderr
);
9297 fprintf(stderr
, "\n");
9302 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9303 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9308 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9309 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9311 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9312 RegClass rc
= vals
[0].regClass();
9314 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9316 unsigned next_pred
= 1;
9318 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9319 Block
& block
= ctx
->program
->blocks
[idx
];
9320 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9321 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9325 if (block
.kind
& block_kind_continue
) {
9326 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9331 bool all_same
= true;
9332 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9333 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9337 val
= vals
[block
.linear_preds
[0] - first
];
9339 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9340 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9341 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9342 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9343 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9344 phi
->definitions
[0] = Definition(val
.getTemp());
9345 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9347 vals
[idx
- first
] = val
;
9350 return vals
[last
- first
];
9353 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9355 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9356 append_logical_end(ctx
->block
);
9357 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9358 Builder
bld(ctx
->program
, ctx
->block
);
9359 bld
.branch(aco_opcode::p_branch
);
9360 unsigned loop_preheader_idx
= ctx
->block
->index
;
9362 Block loop_exit
= Block();
9363 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9364 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9366 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9367 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9368 loop_header
->kind
|= block_kind_loop_header
;
9369 add_edge(loop_preheader_idx
, loop_header
);
9370 ctx
->block
= loop_header
;
9372 /* emit loop body */
9373 unsigned loop_header_idx
= loop_header
->index
;
9374 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9375 append_logical_start(ctx
->block
);
9376 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9378 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9379 if (!ctx
->cf_info
.has_branch
) {
9380 append_logical_end(ctx
->block
);
9381 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9382 /* Discards can result in code running with an empty exec mask.
9383 * This would result in divergent breaks not ever being taken. As a
9384 * workaround, break the loop when the loop mask is empty instead of
9385 * always continuing. */
9386 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9387 unsigned block_idx
= ctx
->block
->index
;
9389 /* create helper blocks to avoid critical edges */
9390 Block
*break_block
= ctx
->program
->create_and_insert_block();
9391 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9392 break_block
->kind
= block_kind_uniform
;
9393 bld
.reset(break_block
);
9394 bld
.branch(aco_opcode::p_branch
);
9395 add_linear_edge(block_idx
, break_block
);
9396 add_linear_edge(break_block
->index
, &loop_exit
);
9398 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9399 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9400 continue_block
->kind
= block_kind_uniform
;
9401 bld
.reset(continue_block
);
9402 bld
.branch(aco_opcode::p_branch
);
9403 add_linear_edge(block_idx
, continue_block
);
9404 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9406 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9407 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9408 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9410 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9411 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9412 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9414 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9417 bld
.reset(ctx
->block
);
9418 bld
.branch(aco_opcode::p_branch
);
9421 /* Fixup phis in loop header from unreachable blocks.
9422 * has_branch/has_divergent_branch also indicates if the loop ends with a
9423 * break/continue instruction, but we don't emit those if unreachable=true */
9425 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9426 bool linear
= ctx
->cf_info
.has_branch
;
9427 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9428 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9429 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9430 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9431 /* the last operand should be the one that needs to be removed */
9432 instr
->operands
.pop_back();
9433 } else if (!is_phi(instr
)) {
9439 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9440 * and the previous one shouldn't both happen at once because a break in the
9441 * merge block would get CSE'd */
9442 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9443 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9444 Operand vals
[num_vals
];
9445 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9446 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9447 if (ctx
->cf_info
.has_branch
)
9448 instr
->operands
.pop_back();
9450 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9451 } else if (!is_phi(instr
)) {
9457 ctx
->cf_info
.has_branch
= false;
9459 // TODO: if the loop has not a single exit, we must add one °°
9460 /* emit loop successor block */
9461 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9462 append_logical_start(ctx
->block
);
9465 // TODO: check if it is beneficial to not branch on continues
9466 /* trim linear phis in loop header */
9467 for (auto&& instr
: loop_entry
->instructions
) {
9468 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9469 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9470 new_phi
->definitions
[0] = instr
->definitions
[0];
9471 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9472 new_phi
->operands
[i
] = instr
->operands
[i
];
9473 /* check that the remaining operands are all the same */
9474 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9475 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9476 instr
.swap(new_phi
);
9477 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9486 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9490 append_logical_end(ctx
->block
);
9491 ctx
->block
->kind
|= block_kind_branch
;
9493 /* branch to linear then block */
9494 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9495 aco_ptr
<Pseudo_branch_instruction
> branch
;
9496 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9497 branch
->operands
[0] = Operand(cond
);
9498 ctx
->block
->instructions
.push_back(std::move(branch
));
9500 ic
->BB_if_idx
= ctx
->block
->index
;
9501 ic
->BB_invert
= Block();
9502 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9503 /* Invert blocks are intentionally not marked as top level because they
9504 * are not part of the logical cfg. */
9505 ic
->BB_invert
.kind
|= block_kind_invert
;
9506 ic
->BB_endif
= Block();
9507 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9508 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9510 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9511 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9512 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9513 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9514 ctx
->cf_info
.parent_if
.is_divergent
= true;
9516 /* divergent branches use cbranch_execz */
9517 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9518 ctx
->cf_info
.exec_potentially_empty_break
= false;
9519 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9521 /** emit logical then block */
9522 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9523 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9524 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9525 ctx
->block
= BB_then_logical
;
9526 append_logical_start(BB_then_logical
);
9529 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9531 Block
*BB_then_logical
= ctx
->block
;
9532 append_logical_end(BB_then_logical
);
9533 /* branch from logical then block to invert block */
9534 aco_ptr
<Pseudo_branch_instruction
> branch
;
9535 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9536 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9537 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9538 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9539 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9540 BB_then_logical
->kind
|= block_kind_uniform
;
9541 assert(!ctx
->cf_info
.has_branch
);
9542 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9543 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9545 /** emit linear then block */
9546 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9547 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9548 BB_then_linear
->kind
|= block_kind_uniform
;
9549 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9550 /* branch from linear then block to invert block */
9551 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9552 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9553 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9555 /** emit invert merge block */
9556 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9557 ic
->invert_idx
= ctx
->block
->index
;
9559 /* branch to linear else block (skip else) */
9560 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9561 branch
->operands
[0] = Operand(ic
->cond
);
9562 ctx
->block
->instructions
.push_back(std::move(branch
));
9564 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9565 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9566 ic
->exec_potentially_empty_break_depth_old
=
9567 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9568 /* divergent branches use cbranch_execz */
9569 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9570 ctx
->cf_info
.exec_potentially_empty_break
= false;
9571 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9573 /** emit logical else block */
9574 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9575 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9576 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9577 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9578 ctx
->block
= BB_else_logical
;
9579 append_logical_start(BB_else_logical
);
9582 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9584 Block
*BB_else_logical
= ctx
->block
;
9585 append_logical_end(BB_else_logical
);
9587 /* branch from logical else block to endif block */
9588 aco_ptr
<Pseudo_branch_instruction
> branch
;
9589 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9590 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9591 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9592 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9593 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9594 BB_else_logical
->kind
|= block_kind_uniform
;
9596 assert(!ctx
->cf_info
.has_branch
);
9597 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9600 /** emit linear else block */
9601 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9602 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9603 BB_else_linear
->kind
|= block_kind_uniform
;
9604 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9606 /* branch from linear else block to endif block */
9607 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9608 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9609 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9612 /** emit endif merge block */
9613 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9614 append_logical_start(ctx
->block
);
9617 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9618 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9619 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9620 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9621 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9622 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9623 !ctx
->cf_info
.parent_if
.is_divergent
) {
9624 ctx
->cf_info
.exec_potentially_empty_break
= false;
9625 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9627 /* uniform control flow never has an empty exec-mask */
9628 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9629 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9630 ctx
->cf_info
.exec_potentially_empty_break
= false;
9631 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9635 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9637 assert(cond
.regClass() == s1
);
9639 append_logical_end(ctx
->block
);
9640 ctx
->block
->kind
|= block_kind_uniform
;
9642 aco_ptr
<Pseudo_branch_instruction
> branch
;
9643 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9644 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9645 branch
->operands
[0] = Operand(cond
);
9646 branch
->operands
[0].setFixed(scc
);
9647 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9649 ic
->BB_if_idx
= ctx
->block
->index
;
9650 ic
->BB_endif
= Block();
9651 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9652 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9654 ctx
->cf_info
.has_branch
= false;
9655 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9657 /** emit then block */
9658 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9659 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9660 add_edge(ic
->BB_if_idx
, BB_then
);
9661 append_logical_start(BB_then
);
9662 ctx
->block
= BB_then
;
9665 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9667 Block
*BB_then
= ctx
->block
;
9669 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9670 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9672 if (!ic
->uniform_has_then_branch
) {
9673 append_logical_end(BB_then
);
9674 /* branch from then block to endif block */
9675 aco_ptr
<Pseudo_branch_instruction
> branch
;
9676 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9677 BB_then
->instructions
.emplace_back(std::move(branch
));
9678 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9679 if (!ic
->then_branch_divergent
)
9680 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9681 BB_then
->kind
|= block_kind_uniform
;
9684 ctx
->cf_info
.has_branch
= false;
9685 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9687 /** emit else block */
9688 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9689 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9690 add_edge(ic
->BB_if_idx
, BB_else
);
9691 append_logical_start(BB_else
);
9692 ctx
->block
= BB_else
;
9695 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9697 Block
*BB_else
= ctx
->block
;
9699 if (!ctx
->cf_info
.has_branch
) {
9700 append_logical_end(BB_else
);
9701 /* branch from then block to endif block */
9702 aco_ptr
<Pseudo_branch_instruction
> branch
;
9703 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9704 BB_else
->instructions
.emplace_back(std::move(branch
));
9705 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9706 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9707 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9708 BB_else
->kind
|= block_kind_uniform
;
9711 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9712 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9714 /** emit endif merge block */
9715 if (!ctx
->cf_info
.has_branch
) {
9716 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9717 append_logical_start(ctx
->block
);
9721 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9723 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9724 Builder
bld(ctx
->program
, ctx
->block
);
9725 aco_ptr
<Pseudo_branch_instruction
> branch
;
9728 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9730 * Uniform conditionals are represented in the following way*) :
9732 * The linear and logical CFG:
9735 * BB_THEN (logical) BB_ELSE (logical)
9739 * *) Exceptions may be due to break and continue statements within loops
9740 * If a break/continue happens within uniform control flow, it branches
9741 * to the loop exit/entry block. Otherwise, it branches to the next
9745 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9746 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9747 cond
= bool_to_scalar_condition(ctx
, cond
);
9749 begin_uniform_if_then(ctx
, &ic
, cond
);
9750 visit_cf_list(ctx
, &if_stmt
->then_list
);
9752 begin_uniform_if_else(ctx
, &ic
);
9753 visit_cf_list(ctx
, &if_stmt
->else_list
);
9755 end_uniform_if(ctx
, &ic
);
9756 } else { /* non-uniform condition */
9758 * To maintain a logical and linear CFG without critical edges,
9759 * non-uniform conditionals are represented in the following way*) :
9764 * BB_THEN (logical) BB_THEN (linear)
9766 * BB_INVERT (linear)
9768 * BB_ELSE (logical) BB_ELSE (linear)
9775 * BB_THEN (logical) BB_ELSE (logical)
9779 * *) Exceptions may be due to break and continue statements within loops
9782 begin_divergent_if_then(ctx
, &ic
, cond
);
9783 visit_cf_list(ctx
, &if_stmt
->then_list
);
9785 begin_divergent_if_else(ctx
, &ic
);
9786 visit_cf_list(ctx
, &if_stmt
->else_list
);
9788 end_divergent_if(ctx
, &ic
);
9791 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9794 static bool visit_cf_list(isel_context
*ctx
,
9795 struct exec_list
*list
)
9797 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9798 switch (node
->type
) {
9799 case nir_cf_node_block
:
9800 visit_block(ctx
, nir_cf_node_as_block(node
));
9802 case nir_cf_node_if
:
9803 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9806 case nir_cf_node_loop
:
9807 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9810 unreachable("unimplemented cf list type");
9816 static void create_null_export(isel_context
*ctx
)
9818 /* Some shader stages always need to have exports.
9819 * So when there is none, we need to add a null export.
9822 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9823 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9824 Builder
bld(ctx
->program
, ctx
->block
);
9825 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9826 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9829 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9831 assert(ctx
->stage
== vertex_vs
||
9832 ctx
->stage
== tess_eval_vs
||
9833 ctx
->stage
== gs_copy_vs
||
9834 ctx
->stage
== ngg_vertex_gs
||
9835 ctx
->stage
== ngg_tess_eval_gs
);
9837 int offset
= (ctx
->stage
& sw_tes
)
9838 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9839 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9840 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9841 if (!is_pos
&& !mask
)
9843 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9845 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9846 exp
->enabled_mask
= mask
;
9847 for (unsigned i
= 0; i
< 4; ++i
) {
9848 if (mask
& (1 << i
))
9849 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9851 exp
->operands
[i
] = Operand(v1
);
9853 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9854 * Setting valid_mask=1 prevents it and has no other effect.
9856 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9858 exp
->compressed
= false;
9860 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9862 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9863 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9868 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9870 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9871 exp
->enabled_mask
= 0;
9872 for (unsigned i
= 0; i
< 4; ++i
)
9873 exp
->operands
[i
] = Operand(v1
);
9874 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9875 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9876 exp
->enabled_mask
|= 0x1;
9878 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9879 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9880 exp
->enabled_mask
|= 0x4;
9882 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9883 if (ctx
->options
->chip_class
< GFX9
) {
9884 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9885 exp
->enabled_mask
|= 0x8;
9887 Builder
bld(ctx
->program
, ctx
->block
);
9889 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9890 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9891 if (exp
->operands
[2].isTemp())
9892 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9894 exp
->operands
[2] = Operand(out
);
9895 exp
->enabled_mask
|= 0x4;
9898 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9900 exp
->compressed
= false;
9901 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9902 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9905 static void create_export_phis(isel_context
*ctx
)
9907 /* Used when exports are needed, but the output temps are defined in a preceding block.
9908 * This function will set up phis in order to access the outputs in the next block.
9911 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9912 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9913 ctx
->block
->instructions
.pop_back();
9915 Builder
bld(ctx
->program
, ctx
->block
);
9917 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9918 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9919 for (unsigned i
= 0; i
< 4; ++i
) {
9920 if (!(mask
& (1 << i
)))
9923 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9924 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9925 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9929 bld
.insert(std::move(logical_start
));
9932 static void create_vs_exports(isel_context
*ctx
)
9934 assert(ctx
->stage
== vertex_vs
||
9935 ctx
->stage
== tess_eval_vs
||
9936 ctx
->stage
== gs_copy_vs
||
9937 ctx
->stage
== ngg_vertex_gs
||
9938 ctx
->stage
== ngg_tess_eval_gs
);
9940 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9941 ? &ctx
->program
->info
->tes
.outinfo
9942 : &ctx
->program
->info
->vs
.outinfo
;
9944 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9945 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9946 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9949 if (ctx
->options
->key
.has_multiview_view_index
) {
9950 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9951 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9954 /* the order these position exports are created is important */
9956 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9957 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9958 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9959 exported_pos
= true;
9961 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9962 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9963 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9964 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9966 if (ctx
->export_clip_dists
) {
9967 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9968 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9969 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9970 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9973 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9974 if (i
< VARYING_SLOT_VAR0
&&
9975 i
!= VARYING_SLOT_LAYER
&&
9976 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9977 i
!= VARYING_SLOT_VIEWPORT
)
9980 export_vs_varying(ctx
, i
, false, NULL
);
9984 create_null_export(ctx
);
9987 static bool export_fs_mrt_z(isel_context
*ctx
)
9989 Builder
bld(ctx
->program
, ctx
->block
);
9990 unsigned enabled_channels
= 0;
9994 for (unsigned i
= 0; i
< 4; ++i
) {
9995 values
[i
] = Operand(v1
);
9998 /* Both stencil and sample mask only need 16-bits. */
9999 if (!ctx
->program
->info
->ps
.writes_z
&&
10000 (ctx
->program
->info
->ps
.writes_stencil
||
10001 ctx
->program
->info
->ps
.writes_sample_mask
)) {
10002 compr
= true; /* COMPR flag */
10004 if (ctx
->program
->info
->ps
.writes_stencil
) {
10005 /* Stencil should be in X[23:16]. */
10006 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10007 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
10008 enabled_channels
|= 0x3;
10011 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10012 /* SampleMask should be in Y[15:0]. */
10013 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10014 enabled_channels
|= 0xc;
10017 if (ctx
->program
->info
->ps
.writes_z
) {
10018 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
10019 enabled_channels
|= 0x1;
10022 if (ctx
->program
->info
->ps
.writes_stencil
) {
10023 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10024 enabled_channels
|= 0x2;
10027 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10028 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10029 enabled_channels
|= 0x4;
10033 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10034 * writemask component.
10036 if (ctx
->options
->chip_class
== GFX6
&&
10037 ctx
->options
->family
!= CHIP_OLAND
&&
10038 ctx
->options
->family
!= CHIP_HAINAN
) {
10039 enabled_channels
|= 0x1;
10042 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10043 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10048 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10050 Builder
bld(ctx
->program
, ctx
->block
);
10051 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10054 for (unsigned i
= 0; i
< 4; ++i
) {
10055 if (write_mask
& (1 << i
)) {
10056 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10058 values
[i
] = Operand(v1
);
10062 unsigned target
, col_format
;
10063 unsigned enabled_channels
= 0;
10064 aco_opcode compr_op
= (aco_opcode
)0;
10066 slot
-= FRAG_RESULT_DATA0
;
10067 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10068 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10070 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10071 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10072 bool is_16bit
= values
[0].regClass() == v2b
;
10074 switch (col_format
)
10076 case V_028714_SPI_SHADER_ZERO
:
10077 enabled_channels
= 0; /* writemask */
10078 target
= V_008DFC_SQ_EXP_NULL
;
10081 case V_028714_SPI_SHADER_32_R
:
10082 enabled_channels
= 1;
10085 case V_028714_SPI_SHADER_32_GR
:
10086 enabled_channels
= 0x3;
10089 case V_028714_SPI_SHADER_32_AR
:
10090 if (ctx
->options
->chip_class
>= GFX10
) {
10091 /* Special case: on GFX10, the outputs are different for 32_AR */
10092 enabled_channels
= 0x3;
10093 values
[1] = values
[3];
10094 values
[3] = Operand(v1
);
10096 enabled_channels
= 0x9;
10100 case V_028714_SPI_SHADER_FP16_ABGR
:
10101 enabled_channels
= 0x5;
10102 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10104 if (ctx
->options
->chip_class
>= GFX9
) {
10105 /* Pack the FP16 values together instead of converting them to
10106 * FP32 and back to FP16.
10107 * TODO: use p_create_vector and let the compiler optimizes.
10109 compr_op
= aco_opcode::v_pack_b32_f16
;
10111 for (unsigned i
= 0; i
< 4; i
++) {
10112 if ((write_mask
>> i
) & 1)
10113 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10119 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10120 enabled_channels
= 0x5;
10121 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10122 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10124 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10128 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10129 enabled_channels
= 0x5;
10130 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10131 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10133 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10137 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10138 enabled_channels
= 0x5;
10139 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10140 if (is_int8
|| is_int10
) {
10142 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10143 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10145 for (unsigned i
= 0; i
< 4; i
++) {
10146 if ((write_mask
>> i
) & 1) {
10147 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10148 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10152 } else if (is_16bit
) {
10153 for (unsigned i
= 0; i
< 4; i
++) {
10154 if ((write_mask
>> i
) & 1) {
10155 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10156 values
[i
] = Operand(tmp
);
10163 case V_028714_SPI_SHADER_SINT16_ABGR
:
10164 enabled_channels
= 0x5;
10165 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10166 if (is_int8
|| is_int10
) {
10168 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10169 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10170 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10171 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10173 for (unsigned i
= 0; i
< 4; i
++) {
10174 if ((write_mask
>> i
) & 1) {
10175 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10176 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10178 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10179 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10183 } else if (is_16bit
) {
10184 for (unsigned i
= 0; i
< 4; i
++) {
10185 if ((write_mask
>> i
) & 1) {
10186 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10187 values
[i
] = Operand(tmp
);
10193 case V_028714_SPI_SHADER_32_ABGR
:
10194 enabled_channels
= 0xF;
10201 if (target
== V_008DFC_SQ_EXP_NULL
)
10204 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10205 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10207 (col_format
== V_028714_SPI_SHADER_32_R
||
10208 col_format
== V_028714_SPI_SHADER_32_GR
||
10209 col_format
== V_028714_SPI_SHADER_32_AR
||
10210 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10211 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10212 for (int i
= 0; i
< 4; i
++) {
10213 if (!(write_mask
& (1 << i
)))
10216 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10217 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10218 bld
.copy(bld
.def(v1
), Operand(3u)));
10219 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10220 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10224 if ((bool) compr_op
) {
10225 for (int i
= 0; i
< 2; i
++) {
10226 /* check if at least one of the values to be compressed is enabled */
10227 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10229 enabled_channels
|= enabled
<< (i
*2);
10230 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10231 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10232 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10234 values
[i
] = Operand(v1
);
10237 values
[2] = Operand(v1
);
10238 values
[3] = Operand(v1
);
10240 for (int i
= 0; i
< 4; i
++)
10241 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10244 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10245 enabled_channels
, target
, (bool) compr_op
);
10249 static void create_fs_exports(isel_context
*ctx
)
10251 bool exported
= false;
10253 /* Export depth, stencil and sample mask. */
10254 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10255 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10256 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10257 exported
|= export_fs_mrt_z(ctx
);
10259 /* Export all color render targets. */
10260 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10261 if (ctx
->outputs
.mask
[i
])
10262 exported
|= export_fs_mrt_color(ctx
, i
);
10265 create_null_export(ctx
);
10268 static void write_tcs_tess_factors(isel_context
*ctx
)
10270 unsigned outer_comps
;
10271 unsigned inner_comps
;
10273 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10290 Builder
bld(ctx
->program
, ctx
->block
);
10292 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10293 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10294 bld
.sopp(aco_opcode::s_barrier
);
10296 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10297 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10299 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10300 if_context ic_invocation_id_is_zero
;
10301 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10302 bld
.reset(ctx
->block
);
10304 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10306 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10307 unsigned stride
= inner_comps
+ outer_comps
;
10308 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10312 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10314 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10316 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10317 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10318 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10320 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10321 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10323 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10324 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10325 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10326 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10329 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10330 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10331 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10332 unsigned tf_const_offset
= 0;
10334 if (ctx
->program
->chip_class
<= GFX8
) {
10335 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10336 if_context ic_rel_patch_id_is_zero
;
10337 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10338 bld
.reset(ctx
->block
);
10340 /* Store the dynamic HS control word. */
10341 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10342 bld
.mubuf(aco_opcode::buffer_store_dword
,
10343 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10344 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10345 /* disable_wqm */ false, /* glc */ true);
10346 tf_const_offset
+= 4;
10348 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10349 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10350 bld
.reset(ctx
->block
);
10353 assert(stride
== 2 || stride
== 4 || stride
== 6);
10354 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10355 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10357 /* Store to offchip for TES to read - only if TES reads them */
10358 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10359 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10360 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10362 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10363 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10365 if (likely(inner_comps
)) {
10366 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10367 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10371 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10372 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10375 static void emit_stream_output(isel_context
*ctx
,
10376 Temp
const *so_buffers
,
10377 Temp
const *so_write_offset
,
10378 const struct radv_stream_output
*output
)
10380 unsigned num_comps
= util_bitcount(output
->component_mask
);
10381 unsigned writemask
= (1 << num_comps
) - 1;
10382 unsigned loc
= output
->location
;
10383 unsigned buf
= output
->buffer
;
10385 assert(num_comps
&& num_comps
<= 4);
10386 if (!num_comps
|| num_comps
> 4)
10389 unsigned start
= ffs(output
->component_mask
) - 1;
10392 bool all_undef
= true;
10393 assert(ctx
->stage
& hw_vs
);
10394 for (unsigned i
= 0; i
< num_comps
; i
++) {
10395 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10396 all_undef
= all_undef
&& !out
[i
].id();
10401 while (writemask
) {
10403 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10404 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10405 /* GFX6 doesn't support storing vec3, split it. */
10406 writemask
|= 1u << (start
+ 2);
10410 unsigned offset
= output
->offset
+ start
* 4;
10412 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10413 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10414 for (int i
= 0; i
< count
; ++i
)
10415 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10416 vec
->definitions
[0] = Definition(write_data
);
10417 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10422 opcode
= aco_opcode::buffer_store_dword
;
10425 opcode
= aco_opcode::buffer_store_dwordx2
;
10428 opcode
= aco_opcode::buffer_store_dwordx3
;
10431 opcode
= aco_opcode::buffer_store_dwordx4
;
10434 unreachable("Unsupported dword count.");
10437 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10438 store
->operands
[0] = Operand(so_buffers
[buf
]);
10439 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10440 store
->operands
[2] = Operand((uint32_t) 0);
10441 store
->operands
[3] = Operand(write_data
);
10442 if (offset
> 4095) {
10443 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10444 Builder
bld(ctx
->program
, ctx
->block
);
10445 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10447 store
->offset
= offset
;
10449 store
->offen
= true;
10451 store
->dlc
= false;
10453 store
->can_reorder
= true;
10454 ctx
->block
->instructions
.emplace_back(std::move(store
));
10458 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10460 Builder
bld(ctx
->program
, ctx
->block
);
10462 Temp so_buffers
[4];
10463 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10464 for (unsigned i
= 0; i
< 4; i
++) {
10465 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10469 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10470 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10473 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10474 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10476 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10478 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10481 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10483 bld
.reset(ctx
->block
);
10485 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10487 Temp so_write_offset
[4];
10489 for (unsigned i
= 0; i
< 4; i
++) {
10490 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10495 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10496 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10497 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10498 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10500 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10502 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10503 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10504 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10505 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10509 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10510 struct radv_stream_output
*output
=
10511 &ctx
->program
->info
->so
.outputs
[i
];
10512 if (stream
!= output
->stream
)
10515 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10518 begin_divergent_if_else(ctx
, &ic
);
10519 end_divergent_if(ctx
, &ic
);
10522 } /* end namespace */
10524 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10526 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10527 Builder
bld(ctx
->program
, ctx
->block
);
10528 constexpr unsigned hs_idx
= 1u;
10529 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10530 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10531 Operand((8u << 16) | (hs_idx
* 8u)));
10532 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10534 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10536 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10537 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10538 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10539 ls_has_nonzero_hs_threads
);
10540 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10541 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10542 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10543 ls_has_nonzero_hs_threads
);
10544 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10545 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10546 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10547 ls_has_nonzero_hs_threads
);
10549 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10550 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10551 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10554 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10556 /* Split all arguments except for the first (ring_offsets) and the last
10557 * (exec) so that the dead channels don't stay live throughout the program.
10559 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10560 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10561 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10562 startpgm
->definitions
[i
].regClass().size());
10567 void handle_bc_optimize(isel_context
*ctx
)
10569 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10570 Builder
bld(ctx
->program
, ctx
->block
);
10571 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10572 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10573 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10574 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10575 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10576 if (uses_center
&& uses_centroid
) {
10577 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10578 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10580 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10582 for (unsigned i
= 0; i
< 2; i
++) {
10583 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10584 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10585 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10586 persp_centroid
, persp_center
, sel
);
10588 ctx
->persp_centroid
= bld
.tmp(v2
);
10589 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10590 Operand(new_coord
[0]), Operand(new_coord
[1]));
10591 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10594 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10596 for (unsigned i
= 0; i
< 2; i
++) {
10597 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10598 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10599 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10600 linear_centroid
, linear_center
, sel
);
10602 ctx
->linear_centroid
= bld
.tmp(v2
);
10603 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10604 Operand(new_coord
[0]), Operand(new_coord
[1]));
10605 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10610 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10612 Program
*program
= ctx
->program
;
10614 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10616 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10617 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10618 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10619 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10620 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10622 program
->next_fp_mode
.must_flush_denorms32
=
10623 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10624 program
->next_fp_mode
.must_flush_denorms16_64
=
10625 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10626 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10628 program
->next_fp_mode
.care_about_round32
=
10629 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10631 program
->next_fp_mode
.care_about_round16_64
=
10632 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10633 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10635 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10636 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10637 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10638 program
->next_fp_mode
.denorm16_64
= 0;
10640 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10642 /* preserving fp32 denorms is expensive, so only do it if asked */
10643 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10644 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10646 program
->next_fp_mode
.denorm32
= 0;
10648 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10649 program
->next_fp_mode
.round32
= fp_round_tz
;
10651 program
->next_fp_mode
.round32
= fp_round_ne
;
10653 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10654 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10656 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10658 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10661 void cleanup_cfg(Program
*program
)
10663 /* create linear_succs/logical_succs */
10664 for (Block
& BB
: program
->blocks
) {
10665 for (unsigned idx
: BB
.linear_preds
)
10666 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10667 for (unsigned idx
: BB
.logical_preds
)
10668 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10672 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10674 Builder
bld(ctx
->program
, ctx
->block
);
10676 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10677 Temp count
= i
== 0
10678 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10679 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10680 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10682 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10685 if (ctx
->program
->wave_size
== 64) {
10686 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10687 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10688 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10690 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10691 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10697 bool ngg_early_prim_export(isel_context
*ctx
)
10699 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10703 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10705 Builder
bld(ctx
->program
, ctx
->block
);
10707 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10708 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10710 /* Get the id of the current wave within the threadgroup (workgroup) */
10711 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10712 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10714 /* Execute the following code only on the first wave (wave id 0),
10715 * use the SCC def to tell if the wave id is zero or not.
10717 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10719 begin_uniform_if_then(ctx
, &ic
, cond
);
10720 begin_uniform_if_else(ctx
, &ic
);
10721 bld
.reset(ctx
->block
);
10723 /* Number of vertices output by VS/TES */
10724 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10725 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10726 /* Number of primitives output by VS/TES */
10727 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10728 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10730 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10731 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10732 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10734 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10735 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10737 end_uniform_if(ctx
, &ic
);
10739 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10740 bld
.reset(ctx
->block
);
10741 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10744 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10746 Builder
bld(ctx
->program
, ctx
->block
);
10748 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10749 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10752 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10755 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10756 assert(vtxindex
[i
].id());
10759 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10763 /* The initial edge flag is always false in tess eval shaders. */
10764 if (ctx
->stage
== ngg_vertex_gs
) {
10765 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10766 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10770 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10775 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10777 Builder
bld(ctx
->program
, ctx
->block
);
10778 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10780 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10781 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10782 false /* compressed */, true/* done */, false /* valid mask */);
10785 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10787 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10788 * These must always come before VS exports.
10790 * It is recommended to do these as early as possible. They can be at the beginning when
10791 * there is no SW GS and the shader doesn't write edge flags.
10795 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10796 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10798 Builder
bld(ctx
->program
, ctx
->block
);
10799 constexpr unsigned max_vertices_per_primitive
= 3;
10800 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10802 if (ctx
->stage
== ngg_vertex_gs
) {
10803 /* TODO: optimize for points & lines */
10804 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10805 if (ctx
->shader
->info
.tess
.point_mode
)
10806 num_vertices_per_primitive
= 1;
10807 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10808 num_vertices_per_primitive
= 2;
10810 unreachable("Unsupported NGG shader stage");
10813 Temp vtxindex
[max_vertices_per_primitive
];
10814 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10815 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10816 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10817 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10818 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10819 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10820 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10821 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10823 /* Export primitive data to the index buffer. */
10824 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10826 /* Export primitive ID. */
10827 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10828 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10829 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10830 Temp provoking_vtx_index
= vtxindex
[0];
10831 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10833 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10836 begin_divergent_if_else(ctx
, &ic
);
10837 end_divergent_if(ctx
, &ic
);
10840 void ngg_emit_nogs_output(isel_context
*ctx
)
10842 /* Emits NGG GS output, for stages that don't have SW GS. */
10845 Builder
bld(ctx
->program
, ctx
->block
);
10846 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10848 /* NGG streamout is currently disabled by default. */
10849 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10851 if (late_prim_export
) {
10852 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10853 create_export_phis(ctx
);
10854 /* Do what we need to do in the GS threads. */
10855 ngg_emit_nogs_gsthreads(ctx
);
10857 /* What comes next should be executed on ES threads. */
10858 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10859 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10860 bld
.reset(ctx
->block
);
10863 /* Export VS outputs */
10864 ctx
->block
->kind
|= block_kind_export_end
;
10865 create_vs_exports(ctx
);
10867 /* Export primitive ID */
10868 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10871 if (ctx
->stage
== ngg_vertex_gs
) {
10872 /* Wait for GS threads to store primitive ID in LDS. */
10873 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10874 bld
.sopp(aco_opcode::s_barrier
);
10876 /* Calculate LDS address where the GS threads stored the primitive ID. */
10877 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10878 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10879 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10880 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10881 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10882 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10884 /* Load primitive ID from LDS. */
10885 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10886 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10887 /* TES: Just use the patch ID as the primitive ID. */
10888 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10890 unreachable("unsupported NGG shader stage.");
10893 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10894 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10896 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10899 if (late_prim_export
) {
10900 begin_divergent_if_else(ctx
, &ic
);
10901 end_divergent_if(ctx
, &ic
);
10902 bld
.reset(ctx
->block
);
10906 void select_program(Program
*program
,
10907 unsigned shader_count
,
10908 struct nir_shader
*const *shaders
,
10909 ac_shader_config
* config
,
10910 struct radv_shader_args
*args
)
10912 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10913 if_context ic_merged_wave_info
;
10914 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10916 for (unsigned i
= 0; i
< shader_count
; i
++) {
10917 nir_shader
*nir
= shaders
[i
];
10918 init_context(&ctx
, nir
);
10920 setup_fp_mode(&ctx
, nir
);
10923 /* needs to be after init_context() for FS */
10924 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10925 append_logical_start(ctx
.block
);
10927 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10928 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10930 split_arguments(&ctx
, startpgm
);
10934 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10936 if (ngg_early_prim_export(&ctx
))
10937 ngg_emit_nogs_gsthreads(&ctx
);
10940 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10941 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10942 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10943 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10944 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10945 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10946 ctx
.stage
== tess_eval_geometry_gs
));
10948 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10949 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10950 if (check_merged_wave_info
) {
10951 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10952 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10956 Builder
bld(ctx
.program
, ctx
.block
);
10958 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10959 bld
.sopp(aco_opcode::s_barrier
);
10961 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10962 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10964 } else if (ctx
.stage
== geometry_gs
)
10965 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10967 if (ctx
.stage
== fragment_fs
)
10968 handle_bc_optimize(&ctx
);
10970 visit_cf_list(&ctx
, &func
->body
);
10972 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10973 emit_streamout(&ctx
, 0);
10975 if (ctx
.stage
& hw_vs
) {
10976 create_vs_exports(&ctx
);
10977 ctx
.block
->kind
|= block_kind_export_end
;
10978 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10979 ngg_emit_nogs_output(&ctx
);
10980 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10981 Builder
bld(ctx
.program
, ctx
.block
);
10982 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10983 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10984 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10985 write_tcs_tess_factors(&ctx
);
10988 if (ctx
.stage
== fragment_fs
) {
10989 create_fs_exports(&ctx
);
10990 ctx
.block
->kind
|= block_kind_export_end
;
10993 if (endif_merged_wave_info
) {
10994 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10995 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10998 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10999 ngg_emit_nogs_output(&ctx
);
11001 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
11002 /* Outputs of the previous stage are inputs to the next stage */
11003 ctx
.inputs
= ctx
.outputs
;
11004 ctx
.outputs
= shader_io_state();
11008 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11010 append_logical_end(ctx
.block
);
11011 ctx
.block
->kind
|= block_kind_uniform
;
11012 Builder
bld(ctx
.program
, ctx
.block
);
11013 if (ctx
.program
->wb_smem_l1_on_end
)
11014 bld
.smem(aco_opcode::s_dcache_wb
, false);
11015 bld
.sopp(aco_opcode::s_endpgm
);
11017 cleanup_cfg(program
);
11020 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
11021 ac_shader_config
* config
,
11022 struct radv_shader_args
*args
)
11024 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
11026 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
11027 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
11028 program
->next_fp_mode
.must_flush_denorms32
= false;
11029 program
->next_fp_mode
.must_flush_denorms16_64
= false;
11030 program
->next_fp_mode
.care_about_round32
= false;
11031 program
->next_fp_mode
.care_about_round16_64
= false;
11032 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
11033 program
->next_fp_mode
.denorm32
= 0;
11034 program
->next_fp_mode
.round32
= fp_round_ne
;
11035 program
->next_fp_mode
.round16_64
= fp_round_ne
;
11036 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11038 add_startpgm(&ctx
);
11039 append_logical_start(ctx
.block
);
11041 Builder
bld(ctx
.program
, ctx
.block
);
11043 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11045 Operand
stream_id(0u);
11046 if (args
->shader_info
->so
.num_outputs
)
11047 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11048 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11050 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11052 std::stack
<Block
> endif_blocks
;
11054 for (unsigned stream
= 0; stream
< 4; stream
++) {
11055 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11058 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11059 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11062 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11064 unsigned BB_if_idx
= ctx
.block
->index
;
11065 Block BB_endif
= Block();
11066 if (!stream_id
.isConstant()) {
11068 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11069 append_logical_end(ctx
.block
);
11070 ctx
.block
->kind
|= block_kind_uniform
;
11071 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11073 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11075 ctx
.block
= ctx
.program
->create_and_insert_block();
11076 add_edge(BB_if_idx
, ctx
.block
);
11077 bld
.reset(ctx
.block
);
11078 append_logical_start(ctx
.block
);
11081 unsigned offset
= 0;
11082 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11083 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11086 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11087 unsigned length
= util_last_bit(output_usage_mask
);
11088 for (unsigned j
= 0; j
< length
; ++j
) {
11089 if (!(output_usage_mask
& (1 << j
)))
11092 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11093 Temp voffset
= vtx_offset
;
11094 if (const_offset
>= 4096u) {
11095 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11096 const_offset
%= 4096u;
11099 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11100 mubuf
->definitions
[0] = bld
.def(v1
);
11101 mubuf
->operands
[0] = Operand(gsvs_ring
);
11102 mubuf
->operands
[1] = Operand(voffset
);
11103 mubuf
->operands
[2] = Operand(0u);
11104 mubuf
->offen
= true;
11105 mubuf
->offset
= const_offset
;
11108 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11109 mubuf
->barrier
= barrier_none
;
11110 mubuf
->can_reorder
= true;
11112 ctx
.outputs
.mask
[i
] |= 1 << j
;
11113 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11115 bld
.insert(std::move(mubuf
));
11121 if (args
->shader_info
->so
.num_outputs
) {
11122 emit_streamout(&ctx
, stream
);
11123 bld
.reset(ctx
.block
);
11127 create_vs_exports(&ctx
);
11128 ctx
.block
->kind
|= block_kind_export_end
;
11131 if (!stream_id
.isConstant()) {
11132 append_logical_end(ctx
.block
);
11134 /* branch from then block to endif block */
11135 bld
.branch(aco_opcode::p_branch
);
11136 add_edge(ctx
.block
->index
, &BB_endif
);
11137 ctx
.block
->kind
|= block_kind_uniform
;
11139 /* emit else block */
11140 ctx
.block
= ctx
.program
->create_and_insert_block();
11141 add_edge(BB_if_idx
, ctx
.block
);
11142 bld
.reset(ctx
.block
);
11143 append_logical_start(ctx
.block
);
11145 endif_blocks
.push(std::move(BB_endif
));
11149 while (!endif_blocks
.empty()) {
11150 Block BB_endif
= std::move(endif_blocks
.top());
11151 endif_blocks
.pop();
11153 Block
*BB_else
= ctx
.block
;
11155 append_logical_end(BB_else
);
11156 /* branch from else block to endif block */
11157 bld
.branch(aco_opcode::p_branch
);
11158 add_edge(BB_else
->index
, &BB_endif
);
11159 BB_else
->kind
|= block_kind_uniform
;
11161 /** emit endif merge block */
11162 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11163 bld
.reset(ctx
.block
);
11164 append_logical_start(ctx
.block
);
11167 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11169 append_logical_end(ctx
.block
);
11170 ctx
.block
->kind
|= block_kind_uniform
;
11171 bld
.sopp(aco_opcode::s_endpgm
);
11173 cleanup_cfg(program
);