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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.size() == 1) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
746 } else if (dst
.size() == 2) {
747 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
749 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
750 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
752 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
753 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
758 nir_print_instr(&instr
->instr
, stderr
);
759 fprintf(stderr
, "\n");
764 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
765 assert(dst
.regClass() == bld
.lm
);
766 assert(then
.regClass() == bld
.lm
);
767 assert(els
.regClass() == bld
.lm
);
770 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
771 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
772 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
773 assert(dst
.size() == then
.size());
774 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
775 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
777 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
778 nir_print_instr(&instr
->instr
, stderr
);
779 fprintf(stderr
, "\n");
784 /* divergent boolean bcsel
785 * this implements bcsel on bools: dst = s0 ? s1 : s2
786 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
787 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
789 if (cond
.id() != then
.id())
790 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
792 if (cond
.id() == els
.id())
793 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
795 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
796 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
799 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
800 aco_opcode op
, uint32_t undo
)
802 /* multiply by 16777216 to handle denormals */
803 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
804 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
805 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
806 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
807 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
809 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
811 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
814 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
816 if (ctx
->block
->fp_mode
.denorm32
== 0) {
817 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
821 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
824 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
826 if (ctx
->block
->fp_mode
.denorm32
== 0) {
827 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
831 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
834 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
836 if (ctx
->block
->fp_mode
.denorm32
== 0) {
837 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
841 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
844 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
846 if (ctx
->block
->fp_mode
.denorm32
== 0) {
847 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
851 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
854 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
856 if (ctx
->options
->chip_class
>= GFX7
)
857 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
859 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
860 /* TODO: create more efficient code! */
861 if (val
.type() == RegType::sgpr
)
862 val
= as_vgpr(ctx
, val
);
864 /* Split the input value. */
865 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
868 /* Extract the exponent and compute the unbiased value. */
869 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
871 /* Extract the fractional part. */
872 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
873 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
875 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
878 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
879 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
880 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
881 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
882 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
884 /* Get the sign bit. */
885 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
887 /* Decide the operation to apply depending on the unbiased exponent. */
888 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
889 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
890 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
891 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
892 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
893 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
895 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
898 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
900 if (ctx
->options
->chip_class
>= GFX7
)
901 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
903 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
904 Temp src0
= as_vgpr(ctx
, val
);
906 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
907 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
909 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
910 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
911 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
913 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
915 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
918 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
919 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
921 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
923 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
924 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
926 return add
->definitions
[0].getTemp();
929 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
931 if (!instr
->dest
.dest
.is_ssa
) {
932 fprintf(stderr
, "nir alu dst not in ssa: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
937 Builder
bld(ctx
->program
, ctx
->block
);
938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
943 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
944 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
945 for (unsigned i
= 0; i
< num
; ++i
)
946 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
948 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
949 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
950 for (unsigned i
= 0; i
< num
; ++i
)
951 vec
->operands
[i
] = Operand
{elems
[i
]};
952 vec
->definitions
[0] = Definition(dst
);
953 ctx
->block
->instructions
.emplace_back(std::move(vec
));
954 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
956 // TODO: that is a bit suboptimal..
957 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
958 for (unsigned i
= 0; i
< num
- 1; ++i
)
959 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
960 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
961 for (unsigned i
= 0; i
< num
; ++i
) {
962 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
964 elems
[bit
/ 32] = elems
[i
];
966 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
967 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
968 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
972 bld
.copy(Definition(dst
), elems
[0]);
974 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
979 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
980 aco_ptr
<Instruction
> mov
;
981 if (dst
.type() == RegType::sgpr
) {
982 if (src
.type() == RegType::vgpr
)
983 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
984 else if (src
.regClass() == s1
)
985 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
986 else if (src
.regClass() == s2
)
987 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
989 unreachable("wrong src register class for nir_op_imov");
990 } else if (dst
.regClass() == v1
) {
991 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
992 } else if (dst
.regClass() == v2
) {
993 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
995 nir_print_instr(&instr
->instr
, stderr
);
996 unreachable("Should have been lowered to scalar.");
1001 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1002 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1003 assert(src
.regClass() == bld
.lm
);
1004 assert(dst
.regClass() == bld
.lm
);
1005 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1006 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1007 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1008 } else if (dst
.regClass() == v1
) {
1009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1010 } else if (dst
.type() == RegType::sgpr
) {
1011 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1012 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1015 nir_print_instr(&instr
->instr
, stderr
);
1016 fprintf(stderr
, "\n");
1021 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1022 if (dst
.regClass() == v1
) {
1023 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1024 } else if (dst
.regClass() == s1
) {
1025 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1026 } else if (dst
.size() == 2) {
1027 Temp src0
= bld
.tmp(dst
.type(), 1);
1028 Temp src1
= bld
.tmp(dst
.type(), 1);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1031 if (dst
.regClass() == s2
) {
1032 Temp carry
= bld
.tmp(s1
);
1033 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1034 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1035 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1037 Temp lower
= bld
.tmp(v1
);
1038 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1039 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1040 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1044 nir_print_instr(&instr
->instr
, stderr
);
1045 fprintf(stderr
, "\n");
1050 if (dst
.regClass() == s1
) {
1051 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1052 } else if (dst
.regClass() == v1
) {
1053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1054 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1056 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1057 nir_print_instr(&instr
->instr
, stderr
);
1058 fprintf(stderr
, "\n");
1062 case nir_op_isign
: {
1063 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1064 if (dst
.regClass() == s1
) {
1065 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1066 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1067 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1068 } else if (dst
.regClass() == s2
) {
1069 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1071 if (ctx
->program
->chip_class
>= GFX8
)
1072 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1074 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1075 /* SCC gets zero-extended to 64 bit */
1076 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1077 } else if (dst
.regClass() == v1
) {
1078 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1079 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1080 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1081 } else if (dst
.regClass() == v2
) {
1082 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1083 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1084 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1085 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1086 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1087 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 if (dst
.regClass() == v1
) {
1097 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1098 } else if (dst
.regClass() == s1
) {
1099 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1108 if (dst
.regClass() == v1
) {
1109 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1110 } else if (dst
.regClass() == s1
) {
1111 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1145 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1146 } else if (dst
.regClass() == v1
) {
1147 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1148 } else if (dst
.regClass() == s1
) {
1149 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1150 } else if (dst
.regClass() == s2
) {
1151 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1153 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1154 nir_print_instr(&instr
->instr
, stderr
);
1155 fprintf(stderr
, "\n");
1160 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1161 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1162 } else if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1166 } else if (dst
.regClass() == s2
) {
1167 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1176 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1177 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1178 } else if (dst
.regClass() == v1
) {
1179 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1180 } else if (dst
.regClass() == s1
) {
1181 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1182 } else if (dst
.regClass() == s2
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1194 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1195 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1196 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1197 } else if (dst
.regClass() == v2
) {
1198 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1199 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1200 } else if (dst
.regClass() == s2
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1202 } else if (dst
.regClass() == s1
) {
1203 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1212 if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1214 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1215 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1216 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1217 } else if (dst
.regClass() == v2
) {
1218 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1219 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (dst
.regClass() == v1
) {
1233 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1234 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1235 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1236 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1237 } else if (dst
.regClass() == v2
) {
1238 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1239 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1242 } else if (dst
.regClass() == s2
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1246 nir_print_instr(&instr
->instr
, stderr
);
1247 fprintf(stderr
, "\n");
1251 case nir_op_find_lsb
: {
1252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1253 if (src
.regClass() == s1
) {
1254 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1255 } else if (src
.regClass() == v1
) {
1256 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1257 } else if (src
.regClass() == s2
) {
1258 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1266 case nir_op_ufind_msb
:
1267 case nir_op_ifind_msb
: {
1268 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1269 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1270 aco_opcode op
= src
.regClass() == s2
?
1271 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1272 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1273 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1275 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1276 Operand(src
.size() * 32u - 1u), msb_rev
);
1277 Temp msb
= sub
.def(0).getTemp();
1278 Temp carry
= sub
.def(1).getTemp();
1280 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1281 } else if (src
.regClass() == v1
) {
1282 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1283 Temp msb_rev
= bld
.tmp(v1
);
1284 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1285 Temp msb
= bld
.tmp(v1
);
1286 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1287 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1290 nir_print_instr(&instr
->instr
, stderr
);
1291 fprintf(stderr
, "\n");
1295 case nir_op_bitfield_reverse
: {
1296 if (dst
.regClass() == s1
) {
1297 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1298 } else if (dst
.regClass() == v1
) {
1299 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1313 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1314 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1315 if (dst
.regClass() == v1
) {
1316 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1320 assert(src0
.size() == 2 && src1
.size() == 2);
1321 Temp src00
= bld
.tmp(src0
.type(), 1);
1322 Temp src01
= bld
.tmp(dst
.type(), 1);
1323 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1324 Temp src10
= bld
.tmp(src1
.type(), 1);
1325 Temp src11
= bld
.tmp(dst
.type(), 1);
1326 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1328 if (dst
.regClass() == s2
) {
1329 Temp carry
= bld
.tmp(s1
);
1330 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1331 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1333 } else if (dst
.regClass() == v2
) {
1334 Temp dst0
= bld
.tmp(v1
);
1335 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1336 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1340 nir_print_instr(&instr
->instr
, stderr
);
1341 fprintf(stderr
, "\n");
1345 case nir_op_uadd_sat
: {
1346 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1347 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1348 if (dst
.regClass() == s1
) {
1349 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1350 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1353 } else if (dst
.regClass() == v1
) {
1354 if (ctx
->options
->chip_class
>= GFX9
) {
1355 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1356 add
->operands
[0] = Operand(src0
);
1357 add
->operands
[1] = Operand(src1
);
1358 add
->definitions
[0] = Definition(dst
);
1360 ctx
->block
->instructions
.emplace_back(std::move(add
));
1362 if (src1
.regClass() != v1
)
1363 std::swap(src0
, src1
);
1364 assert(src1
.regClass() == v1
);
1365 Temp tmp
= bld
.tmp(v1
);
1366 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1367 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1376 case nir_op_uadd_carry
: {
1377 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1378 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1379 if (dst
.regClass() == s1
) {
1380 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1383 if (dst
.regClass() == v1
) {
1384 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1385 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1389 Temp src00
= bld
.tmp(src0
.type(), 1);
1390 Temp src01
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1392 Temp src10
= bld
.tmp(src1
.type(), 1);
1393 Temp src11
= bld
.tmp(dst
.type(), 1);
1394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1395 if (dst
.regClass() == s2
) {
1396 Temp carry
= bld
.tmp(s1
);
1397 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1398 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1399 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1400 } else if (dst
.regClass() == v2
) {
1401 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1402 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1403 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1406 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1407 nir_print_instr(&instr
->instr
, stderr
);
1408 fprintf(stderr
, "\n");
1413 if (dst
.regClass() == s1
) {
1414 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == v1
) {
1421 bld
.vsub32(Definition(dst
), src0
, src1
);
1425 Temp src00
= bld
.tmp(src0
.type(), 1);
1426 Temp src01
= bld
.tmp(dst
.type(), 1);
1427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1428 Temp src10
= bld
.tmp(src1
.type(), 1);
1429 Temp src11
= bld
.tmp(dst
.type(), 1);
1430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1431 if (dst
.regClass() == s2
) {
1432 Temp carry
= bld
.tmp(s1
);
1433 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1434 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1435 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1436 } else if (dst
.regClass() == v2
) {
1437 Temp lower
= bld
.tmp(v1
);
1438 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1439 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_usub_borrow
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1454 } else if (dst
.regClass() == v1
) {
1455 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1456 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1460 Temp src00
= bld
.tmp(src0
.type(), 1);
1461 Temp src01
= bld
.tmp(dst
.type(), 1);
1462 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1463 Temp src10
= bld
.tmp(src1
.type(), 1);
1464 Temp src11
= bld
.tmp(dst
.type(), 1);
1465 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1466 if (dst
.regClass() == s2
) {
1467 Temp borrow
= bld
.tmp(s1
);
1468 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1469 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1471 } else if (dst
.regClass() == v2
) {
1472 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1473 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1474 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1475 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1478 nir_print_instr(&instr
->instr
, stderr
);
1479 fprintf(stderr
, "\n");
1484 if (dst
.regClass() == v1
) {
1485 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1486 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1487 } else if (dst
.regClass() == s1
) {
1488 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1496 case nir_op_umul_high
: {
1497 if (dst
.regClass() == v1
) {
1498 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1499 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1500 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1501 } else if (dst
.regClass() == s1
) {
1502 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1503 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1504 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1506 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1507 nir_print_instr(&instr
->instr
, stderr
);
1508 fprintf(stderr
, "\n");
1512 case nir_op_imul_high
: {
1513 if (dst
.regClass() == v1
) {
1514 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1515 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1516 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1517 } else if (dst
.regClass() == s1
) {
1518 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1519 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1520 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1529 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1530 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1531 if (dst
.regClass() == v2b
) {
1532 Temp tmp
= bld
.tmp(v1
);
1533 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1534 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1535 } else if (dst
.regClass() == v1
) {
1536 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1537 } else if (dst
.regClass() == v2
) {
1538 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1540 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1541 nir_print_instr(&instr
->instr
, stderr
);
1542 fprintf(stderr
, "\n");
1547 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1548 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1549 if (dst
.regClass() == v2b
) {
1550 Temp tmp
= bld
.tmp(v1
);
1551 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1552 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1553 } else if (dst
.regClass() == v1
) {
1554 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1555 } else if (dst
.regClass() == v2
) {
1556 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1558 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1559 nir_print_instr(&instr
->instr
, stderr
);
1560 fprintf(stderr
, "\n");
1565 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1566 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1567 if (dst
.regClass() == v2b
) {
1568 Temp tmp
= bld
.tmp(v1
);
1569 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1570 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1572 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1573 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1574 } else if (dst
.regClass() == v1
) {
1575 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1576 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1578 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1579 } else if (dst
.regClass() == v2
) {
1580 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1582 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1585 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1586 nir_print_instr(&instr
->instr
, stderr
);
1587 fprintf(stderr
, "\n");
1592 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1593 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1594 if (dst
.regClass() == v2b
) {
1595 // TODO: check fp_mode.must_flush_denorms16_64
1596 Temp tmp
= bld
.tmp(v1
);
1597 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1598 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1599 } else if (dst
.regClass() == v1
) {
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1601 } else if (dst
.regClass() == v2
) {
1602 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1603 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1604 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1606 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1609 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1610 nir_print_instr(&instr
->instr
, stderr
);
1611 fprintf(stderr
, "\n");
1616 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1617 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1618 if (dst
.regClass() == v2b
) {
1619 // TODO: check fp_mode.must_flush_denorms16_64
1620 Temp tmp
= bld
.tmp(v1
);
1621 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1622 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1623 } else if (dst
.regClass() == v1
) {
1624 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1625 } else if (dst
.regClass() == v2
) {
1626 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1627 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1628 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1630 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1634 nir_print_instr(&instr
->instr
, stderr
);
1635 fprintf(stderr
, "\n");
1639 case nir_op_fmax3
: {
1640 if (dst
.size() == 1) {
1641 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1643 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1644 nir_print_instr(&instr
->instr
, stderr
);
1645 fprintf(stderr
, "\n");
1649 case nir_op_fmin3
: {
1650 if (dst
.size() == 1) {
1651 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1653 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1654 nir_print_instr(&instr
->instr
, stderr
);
1655 fprintf(stderr
, "\n");
1659 case nir_op_fmed3
: {
1660 if (dst
.size() == 1) {
1661 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1663 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1664 nir_print_instr(&instr
->instr
, stderr
);
1665 fprintf(stderr
, "\n");
1669 case nir_op_umax3
: {
1670 if (dst
.size() == 1) {
1671 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1673 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1674 nir_print_instr(&instr
->instr
, stderr
);
1675 fprintf(stderr
, "\n");
1679 case nir_op_umin3
: {
1680 if (dst
.size() == 1) {
1681 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1683 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1684 nir_print_instr(&instr
->instr
, stderr
);
1685 fprintf(stderr
, "\n");
1689 case nir_op_umed3
: {
1690 if (dst
.size() == 1) {
1691 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1693 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1694 nir_print_instr(&instr
->instr
, stderr
);
1695 fprintf(stderr
, "\n");
1699 case nir_op_imax3
: {
1700 if (dst
.size() == 1) {
1701 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1703 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1704 nir_print_instr(&instr
->instr
, stderr
);
1705 fprintf(stderr
, "\n");
1709 case nir_op_imin3
: {
1710 if (dst
.size() == 1) {
1711 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1713 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1714 nir_print_instr(&instr
->instr
, stderr
);
1715 fprintf(stderr
, "\n");
1719 case nir_op_imed3
: {
1720 if (dst
.size() == 1) {
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1723 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1724 nir_print_instr(&instr
->instr
, stderr
);
1725 fprintf(stderr
, "\n");
1729 case nir_op_cube_face_coord
: {
1730 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1731 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1732 emit_extract_vector(ctx
, in
, 1, v1
),
1733 emit_extract_vector(ctx
, in
, 2, v1
) };
1734 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1735 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1736 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1737 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1738 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1739 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1740 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1743 case nir_op_cube_face_index
: {
1744 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1745 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1746 emit_extract_vector(ctx
, in
, 1, v1
),
1747 emit_extract_vector(ctx
, in
, 2, v1
) };
1748 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1751 case nir_op_bcsel
: {
1752 emit_bcsel(ctx
, instr
, dst
);
1756 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1757 if (dst
.regClass() == v2b
) {
1758 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1759 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1760 } else if (dst
.regClass() == v1
) {
1761 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1762 } else if (dst
.regClass() == v2
) {
1763 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1765 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1766 nir_print_instr(&instr
->instr
, stderr
);
1767 fprintf(stderr
, "\n");
1772 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1773 if (dst
.regClass() == v2b
) {
1774 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1776 } else if (dst
.regClass() == v1
) {
1777 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1778 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1779 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1780 } else if (dst
.regClass() == v2
) {
1781 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1782 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1783 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1784 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1785 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1786 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1788 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1789 nir_print_instr(&instr
->instr
, stderr
);
1790 fprintf(stderr
, "\n");
1795 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1796 if (dst
.regClass() == v2b
) {
1797 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1798 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1799 } else if (dst
.regClass() == v1
) {
1800 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1801 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1802 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1803 } else if (dst
.regClass() == v2
) {
1804 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1805 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1806 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1807 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1808 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1809 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1811 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1812 nir_print_instr(&instr
->instr
, stderr
);
1813 fprintf(stderr
, "\n");
1818 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1819 if (dst
.regClass() == v2b
) {
1820 Temp one
= bld
.copy(bld
.def(s1
), Operand(0x3c00u
));
1821 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), one
, src
);
1822 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1823 } else if (dst
.regClass() == v1
) {
1824 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1825 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1826 // TODO: confirm that this holds under any circumstances
1827 } else if (dst
.regClass() == v2
) {
1828 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1829 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1832 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1833 nir_print_instr(&instr
->instr
, stderr
);
1834 fprintf(stderr
, "\n");
1838 case nir_op_flog2
: {
1839 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1840 if (dst
.regClass() == v2b
) {
1841 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1842 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1843 } else if (dst
.regClass() == v1
) {
1844 emit_log2(ctx
, bld
, Definition(dst
), src
);
1846 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1847 nir_print_instr(&instr
->instr
, stderr
);
1848 fprintf(stderr
, "\n");
1853 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1854 if (dst
.regClass() == v2b
) {
1855 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1856 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1857 } else if (dst
.regClass() == v1
) {
1858 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1859 } else if (dst
.regClass() == v2
) {
1860 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1862 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1863 nir_print_instr(&instr
->instr
, stderr
);
1864 fprintf(stderr
, "\n");
1868 case nir_op_fexp2
: {
1869 if (dst
.regClass() == v2b
) {
1870 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1871 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1872 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1873 } else if (dst
.regClass() == v1
) {
1874 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1876 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1877 nir_print_instr(&instr
->instr
, stderr
);
1878 fprintf(stderr
, "\n");
1882 case nir_op_fsqrt
: {
1883 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1884 if (dst
.regClass() == v2b
) {
1885 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1886 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1887 } else if (dst
.regClass() == v1
) {
1888 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1889 } else if (dst
.regClass() == v2
) {
1890 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1892 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1893 nir_print_instr(&instr
->instr
, stderr
);
1894 fprintf(stderr
, "\n");
1898 case nir_op_ffract
: {
1899 if (dst
.regClass() == v2b
) {
1900 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1901 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1902 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1903 } else if (dst
.regClass() == v1
) {
1904 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1905 } else if (dst
.regClass() == v2
) {
1906 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_ffloor
: {
1915 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1916 if (dst
.regClass() == v2b
) {
1917 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1918 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1919 } else if (dst
.regClass() == v1
) {
1920 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1921 } else if (dst
.regClass() == v2
) {
1922 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1924 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1925 nir_print_instr(&instr
->instr
, stderr
);
1926 fprintf(stderr
, "\n");
1930 case nir_op_fceil
: {
1931 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1932 if (dst
.regClass() == v2b
) {
1933 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1934 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1935 } else if (dst
.regClass() == v1
) {
1936 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1937 } else if (dst
.regClass() == v2
) {
1938 if (ctx
->options
->chip_class
>= GFX7
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1941 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1942 /* trunc = trunc(src0)
1943 * if (src0 > 0.0 && src0 != trunc)
1946 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1947 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1948 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1949 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1950 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1951 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1952 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1955 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1956 nir_print_instr(&instr
->instr
, stderr
);
1957 fprintf(stderr
, "\n");
1961 case nir_op_ftrunc
: {
1962 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1963 if (dst
.regClass() == v2b
) {
1964 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
1965 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1966 } else if (dst
.regClass() == v1
) {
1967 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1968 } else if (dst
.regClass() == v2
) {
1969 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
1971 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1972 nir_print_instr(&instr
->instr
, stderr
);
1973 fprintf(stderr
, "\n");
1977 case nir_op_fround_even
: {
1978 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1979 if (dst
.regClass() == v2b
) {
1980 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
1981 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1982 } else if (dst
.regClass() == v1
) {
1983 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1984 } else if (dst
.regClass() == v2
) {
1985 if (ctx
->options
->chip_class
>= GFX7
) {
1986 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1988 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1989 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1990 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1992 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1993 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1994 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1995 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1996 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1997 tmp
= sub
->definitions
[0].getTemp();
1999 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2000 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2001 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2002 Temp cond
= vop3
->definitions
[0].getTemp();
2004 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2005 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2006 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2007 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2009 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2012 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2013 nir_print_instr(&instr
->instr
, stderr
);
2014 fprintf(stderr
, "\n");
2020 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2021 aco_ptr
<Instruction
> norm
;
2022 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2023 if (dst
.regClass() == v2b
) {
2024 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2025 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2026 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2027 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2028 } else if (dst
.regClass() == v1
) {
2029 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2031 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2032 if (ctx
->options
->chip_class
< GFX9
)
2033 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2035 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2036 bld
.vop1(opcode
, Definition(dst
), tmp
);
2038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2039 nir_print_instr(&instr
->instr
, stderr
);
2040 fprintf(stderr
, "\n");
2044 case nir_op_ldexp
: {
2045 if (dst
.size() == 1) {
2046 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
2047 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
2048 get_alu_src(ctx
, instr
->src
[1]));
2049 } else if (dst
.size() == 2) {
2050 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
2051 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
2052 get_alu_src(ctx
, instr
->src
[1]));
2054 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2055 nir_print_instr(&instr
->instr
, stderr
);
2056 fprintf(stderr
, "\n");
2060 case nir_op_frexp_sig
: {
2061 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2062 if (dst
.regClass() == v2b
) {
2063 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2064 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2065 } else if (dst
.regClass() == v1
) {
2066 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2067 } else if (dst
.regClass() == v2
) {
2068 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2070 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2071 nir_print_instr(&instr
->instr
, stderr
);
2072 fprintf(stderr
, "\n");
2076 case nir_op_frexp_exp
: {
2077 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2078 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2079 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2080 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2081 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2082 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2083 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2084 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2086 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2087 nir_print_instr(&instr
->instr
, stderr
);
2088 fprintf(stderr
, "\n");
2092 case nir_op_fsign
: {
2093 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2094 if (dst
.regClass() == v2b
) {
2095 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2096 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2097 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2098 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2099 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2100 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2102 } else if (dst
.regClass() == v1
) {
2103 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2104 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2105 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2106 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2107 } else if (dst
.regClass() == v2
) {
2108 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2109 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2110 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2112 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2113 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2114 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2116 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2118 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2119 nir_print_instr(&instr
->instr
, stderr
);
2120 fprintf(stderr
, "\n");
2125 case nir_op_f2f16_rtne
: {
2126 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2127 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2128 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2129 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2130 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2133 case nir_op_f2f16_rtz
: {
2134 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2135 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2136 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2137 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2141 case nir_op_f2f32
: {
2142 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2143 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2144 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2145 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2147 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2148 nir_print_instr(&instr
->instr
, stderr
);
2149 fprintf(stderr
, "\n");
2153 case nir_op_f2f64
: {
2154 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2155 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2156 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2157 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2160 case nir_op_i2f32
: {
2161 assert(dst
.size() == 1);
2162 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2165 case nir_op_i2f64
: {
2166 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2167 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2168 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2169 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2170 RegClass rc
= RegClass(src
.type(), 1);
2171 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2172 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2173 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2174 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2175 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2176 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2179 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2180 nir_print_instr(&instr
->instr
, stderr
);
2181 fprintf(stderr
, "\n");
2185 case nir_op_u2f32
: {
2186 assert(dst
.size() == 1);
2187 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2190 case nir_op_u2f64
: {
2191 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2192 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2193 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2194 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2195 RegClass rc
= RegClass(src
.type(), 1);
2196 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2197 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2198 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2199 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2200 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2201 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2203 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2204 nir_print_instr(&instr
->instr
, stderr
);
2205 fprintf(stderr
, "\n");
2209 case nir_op_f2i16
: {
2210 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2211 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2212 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2213 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2214 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2216 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2218 if (dst
.type() == RegType::vgpr
)
2219 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2221 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2224 case nir_op_f2u16
: {
2225 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2226 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2227 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2228 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2229 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2231 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2233 if (dst
.type() == RegType::vgpr
)
2234 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2236 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2239 case nir_op_f2i32
: {
2240 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2241 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2242 if (dst
.type() == RegType::vgpr
)
2243 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2245 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2246 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2248 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2249 if (dst
.type() == RegType::vgpr
)
2250 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2252 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2253 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2256 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2257 nir_print_instr(&instr
->instr
, stderr
);
2258 fprintf(stderr
, "\n");
2262 case nir_op_f2u32
: {
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2265 if (dst
.type() == RegType::vgpr
)
2266 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2268 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2269 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2271 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2272 if (dst
.type() == RegType::vgpr
)
2273 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2275 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2276 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2279 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2280 nir_print_instr(&instr
->instr
, stderr
);
2281 fprintf(stderr
, "\n");
2285 case nir_op_f2i64
: {
2286 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2287 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2288 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2289 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2290 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2291 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2292 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2293 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2294 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2295 Temp new_exponent
= bld
.tmp(v1
);
2296 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2297 if (ctx
->program
->chip_class
>= GFX8
)
2298 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2300 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2301 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2302 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2303 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2304 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2305 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2306 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2307 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2308 Temp new_lower
= bld
.tmp(v1
);
2309 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2310 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2311 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2313 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2314 if (src
.type() == RegType::vgpr
)
2315 src
= bld
.as_uniform(src
);
2316 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2317 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2318 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2319 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2320 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2321 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2322 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2323 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2324 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2325 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2326 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2327 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2328 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2329 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2330 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2331 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2332 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2333 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2334 Temp borrow
= bld
.tmp(s1
);
2335 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2336 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2339 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2340 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2341 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2342 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2343 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2344 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2345 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2346 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2347 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2348 if (dst
.type() == RegType::sgpr
) {
2349 lower
= bld
.as_uniform(lower
);
2350 upper
= bld
.as_uniform(upper
);
2352 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2355 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2356 nir_print_instr(&instr
->instr
, stderr
);
2357 fprintf(stderr
, "\n");
2361 case nir_op_f2u64
: {
2362 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2363 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2364 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2365 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2366 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2367 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2368 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2369 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2370 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2371 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2372 Temp new_exponent
= bld
.tmp(v1
);
2373 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2374 if (ctx
->program
->chip_class
>= GFX8
)
2375 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2377 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2378 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2379 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2380 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2381 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2382 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2383 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2384 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2386 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2387 if (src
.type() == RegType::vgpr
)
2388 src
= bld
.as_uniform(src
);
2389 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2390 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2391 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2392 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2393 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2394 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2395 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2396 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2397 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2398 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2399 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2400 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2401 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2403 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2404 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2405 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2406 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2408 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2409 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2410 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2411 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2412 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2413 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2414 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2415 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2416 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2417 if (dst
.type() == RegType::sgpr
) {
2418 lower
= bld
.as_uniform(lower
);
2419 upper
= bld
.as_uniform(upper
);
2421 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2424 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2425 nir_print_instr(&instr
->instr
, stderr
);
2426 fprintf(stderr
, "\n");
2430 case nir_op_b2f32
: {
2431 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2432 assert(src
.regClass() == bld
.lm
);
2434 if (dst
.regClass() == s1
) {
2435 src
= bool_to_scalar_condition(ctx
, src
);
2436 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2437 } else if (dst
.regClass() == v1
) {
2438 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2440 unreachable("Wrong destination register class for nir_op_b2f32.");
2444 case nir_op_b2f64
: {
2445 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2446 assert(src
.regClass() == bld
.lm
);
2448 if (dst
.regClass() == s2
) {
2449 src
= bool_to_scalar_condition(ctx
, src
);
2450 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2451 } else if (dst
.regClass() == v2
) {
2452 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2453 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2454 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2456 unreachable("Wrong destination register class for nir_op_b2f64.");
2462 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2463 /* we can actually just say dst = src */
2464 if (src
.regClass() == s1
)
2465 bld
.copy(Definition(dst
), src
);
2467 emit_extract_vector(ctx
, src
, 0, dst
);
2470 case nir_op_i2i16
: {
2471 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2472 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2473 if (dst
.regClass() == s1
) {
2474 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2476 assert(src
.regClass() == v1b
);
2477 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2478 sdwa
->operands
[0] = Operand(src
);
2479 sdwa
->definitions
[0] = Definition(dst
);
2480 sdwa
->sel
[0] = sdwa_sbyte
;
2481 sdwa
->dst_sel
= sdwa_sword
;
2482 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2485 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2486 /* we can actually just say dst = src */
2487 if (src
.regClass() == s1
)
2488 bld
.copy(Definition(dst
), src
);
2490 emit_extract_vector(ctx
, src
, 0, dst
);
2494 case nir_op_u2u16
: {
2495 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2496 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2497 if (dst
.regClass() == s1
)
2498 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2500 assert(src
.regClass() == v1b
);
2501 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2502 sdwa
->operands
[0] = Operand(src
);
2503 sdwa
->definitions
[0] = Definition(dst
);
2504 sdwa
->sel
[0] = sdwa_ubyte
;
2505 sdwa
->dst_sel
= sdwa_uword
;
2506 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2509 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2510 /* we can actually just say dst = src */
2511 if (src
.regClass() == s1
)
2512 bld
.copy(Definition(dst
), src
);
2514 emit_extract_vector(ctx
, src
, 0, dst
);
2518 case nir_op_i2i32
: {
2519 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2520 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2521 if (dst
.regClass() == s1
) {
2522 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2524 assert(src
.regClass() == v1b
);
2525 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2526 sdwa
->operands
[0] = Operand(src
);
2527 sdwa
->definitions
[0] = Definition(dst
);
2528 sdwa
->sel
[0] = sdwa_sbyte
;
2529 sdwa
->dst_sel
= sdwa_sdword
;
2530 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2532 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2533 if (dst
.regClass() == s1
) {
2534 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2536 assert(src
.regClass() == v2b
);
2537 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2538 sdwa
->operands
[0] = Operand(src
);
2539 sdwa
->definitions
[0] = Definition(dst
);
2540 sdwa
->sel
[0] = sdwa_sword
;
2541 sdwa
->dst_sel
= sdwa_udword
;
2542 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2544 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2545 /* we can actually just say dst = src, as it would map the lower register */
2546 emit_extract_vector(ctx
, src
, 0, dst
);
2548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2549 nir_print_instr(&instr
->instr
, stderr
);
2550 fprintf(stderr
, "\n");
2554 case nir_op_u2u32
: {
2555 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2556 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2557 if (dst
.regClass() == s1
)
2558 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2560 assert(src
.regClass() == v1b
);
2561 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2562 sdwa
->operands
[0] = Operand(src
);
2563 sdwa
->definitions
[0] = Definition(dst
);
2564 sdwa
->sel
[0] = sdwa_ubyte
;
2565 sdwa
->dst_sel
= sdwa_udword
;
2566 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2568 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2569 if (dst
.regClass() == s1
) {
2570 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2572 assert(src
.regClass() == v2b
);
2573 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2574 sdwa
->operands
[0] = Operand(src
);
2575 sdwa
->definitions
[0] = Definition(dst
);
2576 sdwa
->sel
[0] = sdwa_uword
;
2577 sdwa
->dst_sel
= sdwa_udword
;
2578 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2580 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2581 /* we can actually just say dst = src, as it would map the lower register */
2582 emit_extract_vector(ctx
, src
, 0, dst
);
2584 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2585 nir_print_instr(&instr
->instr
, stderr
);
2586 fprintf(stderr
, "\n");
2590 case nir_op_i2i64
: {
2591 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2592 if (src
.regClass() == s1
) {
2593 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2594 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2595 } else if (src
.regClass() == v1
) {
2596 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2597 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2599 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2600 nir_print_instr(&instr
->instr
, stderr
);
2601 fprintf(stderr
, "\n");
2605 case nir_op_u2u64
: {
2606 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2607 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2608 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2610 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2611 nir_print_instr(&instr
->instr
, stderr
);
2612 fprintf(stderr
, "\n");
2617 case nir_op_b2i32
: {
2618 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2619 assert(src
.regClass() == bld
.lm
);
2621 if (dst
.regClass() == s1
) {
2622 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2623 bool_to_scalar_condition(ctx
, src
, dst
);
2624 } else if (dst
.regClass() == v1
) {
2625 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2627 unreachable("Invalid register class for b2i32");
2633 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2634 assert(dst
.regClass() == bld
.lm
);
2636 if (src
.type() == RegType::vgpr
) {
2637 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2638 assert(dst
.regClass() == bld
.lm
);
2639 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2640 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2642 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2644 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2645 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2647 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2648 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2650 bool_to_vector_condition(ctx
, tmp
, dst
);
2654 case nir_op_pack_64_2x32_split
: {
2655 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2656 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2658 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2661 case nir_op_unpack_64_2x32_split_x
:
2662 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2664 case nir_op_unpack_64_2x32_split_y
:
2665 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2667 case nir_op_unpack_32_2x16_split_x
:
2668 if (dst
.type() == RegType::vgpr
) {
2669 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2671 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2674 case nir_op_unpack_32_2x16_split_y
:
2675 if (dst
.type() == RegType::vgpr
) {
2676 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2678 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2681 case nir_op_pack_32_2x16_split
: {
2682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2684 if (dst
.regClass() == v1
) {
2685 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2687 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2688 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2689 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2693 case nir_op_pack_half_2x16
: {
2694 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2696 if (dst
.regClass() == v1
) {
2697 Temp src0
= bld
.tmp(v1
);
2698 Temp src1
= bld
.tmp(v1
);
2699 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2700 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2701 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2703 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2704 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2705 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2708 nir_print_instr(&instr
->instr
, stderr
);
2709 fprintf(stderr
, "\n");
2713 case nir_op_unpack_half_2x16_split_x
: {
2714 if (dst
.regClass() == v1
) {
2715 Builder
bld(ctx
->program
, ctx
->block
);
2716 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2718 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2719 nir_print_instr(&instr
->instr
, stderr
);
2720 fprintf(stderr
, "\n");
2724 case nir_op_unpack_half_2x16_split_y
: {
2725 if (dst
.regClass() == v1
) {
2726 Builder
bld(ctx
->program
, ctx
->block
);
2727 /* TODO: use SDWA here */
2728 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2729 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2731 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2732 nir_print_instr(&instr
->instr
, stderr
);
2733 fprintf(stderr
, "\n");
2737 case nir_op_fquantize2f16
: {
2738 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2739 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2742 if (ctx
->program
->chip_class
>= GFX8
) {
2743 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2744 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2745 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2747 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2748 * so compare the result and flush to 0 if it's smaller.
2750 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2751 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2752 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2753 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2754 cmp_res
= vop3
->definitions
[0].getTemp();
2757 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2758 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2759 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2761 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2766 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2767 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2769 if (dst
.regClass() == s1
) {
2770 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2771 } else if (dst
.regClass() == v1
) {
2772 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2774 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2775 nir_print_instr(&instr
->instr
, stderr
);
2776 fprintf(stderr
, "\n");
2780 case nir_op_bitfield_select
: {
2781 /* (mask & insert) | (~mask & base) */
2782 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2783 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2784 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2786 /* dst = (insert & bitmask) | (base & ~bitmask) */
2787 if (dst
.regClass() == s1
) {
2788 aco_ptr
<Instruction
> sop2
;
2789 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2790 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2792 if (const_insert
&& const_bitmask
) {
2793 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2795 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2796 lhs
= Operand(insert
);
2800 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2801 if (const_base
&& const_bitmask
) {
2802 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2804 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2805 rhs
= Operand(base
);
2808 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2810 } else if (dst
.regClass() == v1
) {
2811 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2812 base
= as_vgpr(ctx
, base
);
2813 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2814 insert
= as_vgpr(ctx
, insert
);
2816 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2819 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2820 nir_print_instr(&instr
->instr
, stderr
);
2821 fprintf(stderr
, "\n");
2827 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2828 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2829 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2831 if (dst
.type() == RegType::sgpr
) {
2833 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2834 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2835 if (const_offset
&& const_bits
) {
2836 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2837 extract
= Operand(const_extract
);
2841 width
= Operand(const_bits
->u32
<< 16);
2843 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2845 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2849 if (dst
.regClass() == s1
) {
2850 if (instr
->op
== nir_op_ubfe
)
2851 opcode
= aco_opcode::s_bfe_u32
;
2853 opcode
= aco_opcode::s_bfe_i32
;
2854 } else if (dst
.regClass() == s2
) {
2855 if (instr
->op
== nir_op_ubfe
)
2856 opcode
= aco_opcode::s_bfe_u64
;
2858 opcode
= aco_opcode::s_bfe_i64
;
2860 unreachable("Unsupported BFE bit size");
2863 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2867 if (dst
.regClass() == v1
) {
2868 if (instr
->op
== nir_op_ubfe
)
2869 opcode
= aco_opcode::v_bfe_u32
;
2871 opcode
= aco_opcode::v_bfe_i32
;
2873 unreachable("Unsupported BFE bit size");
2876 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2880 case nir_op_bit_count
: {
2881 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2882 if (src
.regClass() == s1
) {
2883 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2884 } else if (src
.regClass() == v1
) {
2885 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2886 } else if (src
.regClass() == v2
) {
2887 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2888 emit_extract_vector(ctx
, src
, 1, v1
),
2889 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2890 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2891 } else if (src
.regClass() == s2
) {
2892 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2894 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2895 nir_print_instr(&instr
->instr
, stderr
);
2896 fprintf(stderr
, "\n");
2901 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2905 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2909 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2913 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2917 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2921 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2925 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2926 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2928 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2929 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2933 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2934 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2936 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2937 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2941 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2945 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2950 case nir_op_fddx_fine
:
2951 case nir_op_fddy_fine
:
2952 case nir_op_fddx_coarse
:
2953 case nir_op_fddy_coarse
: {
2954 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2955 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2956 if (instr
->op
== nir_op_fddx_fine
) {
2957 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2958 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2959 } else if (instr
->op
== nir_op_fddy_fine
) {
2960 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2961 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2963 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2964 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2965 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2967 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2971 if (ctx
->program
->chip_class
>= GFX8
) {
2972 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2973 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2975 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2976 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2977 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2979 emit_wqm(ctx
, tmp
, dst
, true);
2983 fprintf(stderr
, "Unknown NIR ALU instr: ");
2984 nir_print_instr(&instr
->instr
, stderr
);
2985 fprintf(stderr
, "\n");
2989 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2991 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2993 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2994 // which get truncated the lsb if double and msb if int
2995 // for now, we only use s_mov_b64 with 64bit inline constants
2996 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2997 assert(dst
.type() == RegType::sgpr
);
2999 Builder
bld(ctx
->program
, ctx
->block
);
3001 if (instr
->def
.bit_size
== 1) {
3002 assert(dst
.regClass() == bld
.lm
);
3003 int val
= instr
->value
[0].b
? -1 : 0;
3004 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3005 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3006 } else if (dst
.size() == 1) {
3007 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3009 assert(dst
.size() != 1);
3010 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3011 if (instr
->def
.bit_size
== 64)
3012 for (unsigned i
= 0; i
< dst
.size(); i
++)
3013 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3015 for (unsigned i
= 0; i
< dst
.size(); i
++)
3016 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3018 vec
->definitions
[0] = Definition(dst
);
3019 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3023 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3025 uint32_t new_mask
= 0;
3026 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3027 if (mask
& (1u << i
))
3028 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3032 Operand
load_lds_size_m0(isel_context
*ctx
)
3034 /* TODO: m0 does not need to be initialized on GFX9+ */
3035 Builder
bld(ctx
->program
, ctx
->block
);
3036 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3039 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3040 Temp address
, unsigned base_offset
, unsigned align
)
3042 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3044 Builder
bld(ctx
->program
, ctx
->block
);
3046 Operand m
= load_lds_size_m0(ctx
);
3048 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3049 unsigned bytes_read
= 0;
3050 unsigned result_size
= 0;
3051 unsigned total_bytes
= num_components
* elem_size_bytes
;
3052 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3053 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3054 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3056 while (bytes_read
< total_bytes
) {
3057 unsigned todo
= total_bytes
- bytes_read
;
3058 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3059 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3061 aco_opcode op
= aco_opcode::last_opcode
;
3063 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3064 op
= aco_opcode::ds_read_b128
;
3066 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3067 op
= aco_opcode::ds_read2_b64
;
3070 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3071 op
= aco_opcode::ds_read_b96
;
3073 } else if (todo
>= 8 && aligned8
) {
3074 op
= aco_opcode::ds_read_b64
;
3076 } else if (todo
>= 8 && usable_read2
) {
3077 op
= aco_opcode::ds_read2_b32
;
3080 } else if (todo
>= 4) {
3081 op
= aco_opcode::ds_read_b32
;
3086 assert(todo
% elem_size_bytes
== 0);
3087 unsigned num_elements
= todo
/ elem_size_bytes
;
3088 unsigned offset
= base_offset
+ bytes_read
;
3089 unsigned max_offset
= read2
? 1019 : 65535;
3091 Temp address_offset
= address
;
3092 if (offset
> max_offset
) {
3093 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3094 offset
= bytes_read
;
3096 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3099 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3102 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3105 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3107 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3109 if (num_components
== 1) {
3110 assert(todo
== total_bytes
);
3111 if (dst
.type() == RegType::sgpr
)
3112 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3116 if (dst
.type() == RegType::sgpr
) {
3117 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3118 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3122 if (num_elements
== 1) {
3123 result
[result_size
++] = res
;
3125 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3126 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3127 split
->operands
[0] = Operand(res
);
3128 for (unsigned i
= 0; i
< num_elements
; i
++)
3129 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3130 ctx
->block
->instructions
.emplace_back(std::move(split
));
3136 assert(result_size
== num_components
&& result_size
> 1);
3137 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3138 for (unsigned i
= 0; i
< result_size
; i
++)
3139 vec
->operands
[i
] = Operand(result
[i
]);
3140 vec
->definitions
[0] = Definition(dst
);
3141 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3142 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3147 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3149 if (start
== 0 && size
== data
.size())
3150 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3152 unsigned size_hint
= 1;
3153 auto it
= ctx
->allocated_vec
.find(data
.id());
3154 if (it
!= ctx
->allocated_vec
.end())
3155 size_hint
= it
->second
[0].size();
3156 if (size
% size_hint
|| start
% size_hint
)
3163 for (unsigned i
= 0; i
< size
; i
++)
3164 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3167 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3169 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3170 for (unsigned i
= 0; i
< size
; i
++)
3171 vec
->operands
[i
] = Operand(elems
[i
]);
3172 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3173 vec
->definitions
[0] = Definition(res
);
3174 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3178 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3180 Builder
bld(ctx
->program
, ctx
->block
);
3181 unsigned bytes_written
= 0;
3182 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3183 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3185 while (bytes_written
< total_size
* 4) {
3186 unsigned todo
= total_size
* 4 - bytes_written
;
3187 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3188 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3190 aco_opcode op
= aco_opcode::last_opcode
;
3191 bool write2
= false;
3193 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3194 op
= aco_opcode::ds_write_b128
;
3196 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3197 op
= aco_opcode::ds_write2_b64
;
3200 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3201 op
= aco_opcode::ds_write_b96
;
3203 } else if (todo
>= 8 && aligned8
) {
3204 op
= aco_opcode::ds_write_b64
;
3206 } else if (todo
>= 8 && usable_write2
) {
3207 op
= aco_opcode::ds_write2_b32
;
3210 } else if (todo
>= 4) {
3211 op
= aco_opcode::ds_write_b32
;
3217 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3218 unsigned max_offset
= write2
? 1020 : 65535;
3219 Temp address_offset
= address
;
3220 if (offset
> max_offset
) {
3221 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3222 offset
= offset1
+ bytes_written
;
3224 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3227 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3228 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3229 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3231 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3232 bld
.ds(op
, address_offset
, val
, m
, offset
);
3235 bytes_written
+= size
* 4;
3239 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3240 Temp address
, unsigned base_offset
, unsigned align
)
3242 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3243 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3245 Operand m
= load_lds_size_m0(ctx
);
3247 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3248 assert(wrmask
<= 0x0f);
3249 int start
[2], count
[2];
3250 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3251 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3252 assert(wrmask
== 0);
3254 /* one combined store is sufficient */
3255 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3256 Builder
bld(ctx
->program
, ctx
->block
);
3258 Temp address_offset
= address
;
3259 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3260 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3264 assert(count
[0] == 1);
3265 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3267 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3268 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3269 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3270 base_offset
= base_offset
/ elem_size_bytes
;
3271 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3272 base_offset
+ start
[0], base_offset
+ start
[1]);
3276 for (unsigned i
= 0; i
< 2; i
++) {
3280 unsigned elem_size_words
= elem_size_bytes
/ 4;
3281 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3282 base_offset
, start
[i
] * elem_size_bytes
, align
);
3287 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3289 unsigned align
= 16;
3291 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3297 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3298 unsigned split_cnt
= 0u, Temp dst
= Temp())
3300 Builder
bld(ctx
->program
, ctx
->block
);
3301 unsigned dword_size
= elem_size_bytes
/ 4;
3304 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3306 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3307 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3308 instr
->definitions
[0] = Definition(dst
);
3310 for (unsigned i
= 0; i
< cnt
; ++i
) {
3312 assert(arr
[i
].size() == dword_size
);
3313 allocated_vec
[i
] = arr
[i
];
3314 instr
->operands
[i
] = Operand(arr
[i
]);
3316 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3317 allocated_vec
[i
] = zero
;
3318 instr
->operands
[i
] = Operand(zero
);
3322 bld
.insert(std::move(instr
));
3325 emit_split_vector(ctx
, dst
, split_cnt
);
3327 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3332 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3334 if (const_offset
>= 4096) {
3335 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3336 const_offset
%= 4096u;
3339 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3340 else if (unlikely(voffset
.regClass() == s1
))
3341 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3342 else if (likely(voffset
.regClass() == v1
))
3343 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3345 unreachable("Unsupported register class of voffset");
3348 return const_offset
;
3351 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3352 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3355 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3356 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3358 Builder
bld(ctx
->program
, ctx
->block
);
3359 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3360 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3362 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3363 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3364 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3365 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3366 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3368 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3371 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3372 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3373 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3375 Builder
bld(ctx
->program
, ctx
->block
);
3376 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3379 if (elem_size_bytes
== 8) {
3380 elem_size_bytes
= 4;
3381 write_mask
= widen_mask(write_mask
, 2);
3384 while (write_mask
) {
3387 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3392 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3393 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3395 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3396 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3399 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3400 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3410 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3411 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3413 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3414 assert(size_dwords
>= 1 && size_dwords
<= 4);
3416 Builder
bld(ctx
->program
, ctx
->block
);
3417 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3418 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3419 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3421 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3422 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3423 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3424 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3425 /* disable_wqm */ false, /* glc */ true,
3426 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3428 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3433 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3434 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3435 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3437 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3438 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3439 assert(!!stride
!= allow_combining
);
3441 Builder
bld(ctx
->program
, ctx
->block
);
3442 unsigned split_cnt
= num_components
;
3444 if (elem_size_bytes
== 8) {
3445 elem_size_bytes
= 4;
3446 num_components
*= 2;
3450 stride
= elem_size_bytes
;
3452 unsigned load_size
= 1;
3453 if (allow_combining
) {
3454 if ((num_components
% 4) == 0)
3456 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3458 else if ((num_components
% 2) == 0)
3462 unsigned num_loads
= num_components
/ load_size
;
3463 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3465 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3466 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3467 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3470 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3473 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3475 Builder
bld(ctx
->program
, ctx
->block
);
3476 Temp offset
= base_offset
.first
;
3477 unsigned const_offset
= base_offset
.second
;
3479 if (!nir_src_is_const(*off_src
)) {
3480 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3483 /* Calculate indirect offset with stride */
3484 if (likely(indirect_offset_arg
.regClass() == v1
))
3485 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3486 else if (indirect_offset_arg
.regClass() == s1
)
3487 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3489 unreachable("Unsupported register class of indirect offset");
3491 /* Add to the supplied base offset */
3492 if (offset
.id() == 0)
3493 offset
= with_stride
;
3494 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3495 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3496 else if (offset
.size() == 1 && with_stride
.size() == 1)
3497 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3499 unreachable("Unsupported register class of indirect offset");
3501 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3502 const_offset
+= const_offset_arg
* stride
;
3505 return std::make_pair(offset
, const_offset
);
3508 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3510 Builder
bld(ctx
->program
, ctx
->block
);
3513 if (off1
.first
.id() && off2
.first
.id()) {
3514 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3515 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3516 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3517 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3519 unreachable("Unsupported register class of indirect offset");
3521 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3524 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3527 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3529 Builder
bld(ctx
->program
, ctx
->block
);
3530 unsigned const_offset
= offs
.second
* multiplier
;
3532 if (!offs
.first
.id())
3533 return std::make_pair(offs
.first
, const_offset
);
3535 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3536 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3537 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3539 return std::make_pair(offset
, const_offset
);
3542 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3544 Builder
bld(ctx
->program
, ctx
->block
);
3546 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3547 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3548 /* component is in bytes */
3549 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3551 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3552 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3553 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3556 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3558 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3561 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3563 Builder
bld(ctx
->program
, ctx
->block
);
3565 switch (ctx
->shader
->info
.stage
) {
3566 case MESA_SHADER_TESS_CTRL
:
3567 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3568 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3569 case MESA_SHADER_TESS_EVAL
:
3570 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3572 unreachable("Unsupported stage in get_tess_rel_patch_id");
3576 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3578 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3579 Builder
bld(ctx
->program
, ctx
->block
);
3581 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3582 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3584 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3586 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3587 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3589 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3590 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3591 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3593 return offset_mul(ctx
, offs
, 4u);
3596 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3598 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3599 Builder
bld(ctx
->program
, ctx
->block
);
3601 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3602 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3603 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3604 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3605 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3606 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3608 std::pair
<Temp
, unsigned> offs
= instr
3609 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3610 : std::make_pair(Temp(), 0u);
3612 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3613 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3618 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3619 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3621 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3622 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3624 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3625 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3631 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3633 Builder
bld(ctx
->program
, ctx
->block
);
3635 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3636 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3638 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3640 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3641 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3642 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3644 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3645 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3650 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3652 Builder
bld(ctx
->program
, ctx
->block
);
3654 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3655 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3656 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3658 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3659 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3660 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3661 unsigned attr_stride
= ctx
->tcs_num_patches
;
3663 std::pair
<Temp
, unsigned> offs
= instr
3664 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3665 : std::make_pair(Temp(), 0u);
3667 if (const_base_offset
)
3668 offs
.second
+= const_base_offset
* attr_stride
;
3670 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3671 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3672 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3677 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3679 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3680 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3682 if (!nir_src_is_const(*off_src
)) {
3688 off
+= nir_src_as_uint(*off_src
) * 16u;
3691 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3692 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3699 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3701 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3702 unsigned component
= nir_intrinsic_component(instr
);
3703 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3705 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3706 if (off_instr
->type
!= nir_instr_type_load_const
)
3709 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3710 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3712 if (instr
->src
[0].ssa
->bit_size
== 64)
3713 write_mask
= widen_mask(write_mask
, 2);
3715 for (unsigned i
= 0; i
< 8; ++i
) {
3716 if (write_mask
& (1 << i
)) {
3717 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3718 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3726 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3728 /* Only TCS per-vertex inputs are supported by this function.
3729 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3731 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3734 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3735 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3736 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3737 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3738 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3739 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3744 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3745 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3746 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3747 assert(vec
.size() == dst
.size());
3749 Builder
bld(ctx
->program
, ctx
->block
);
3750 bld
.copy(Definition(dst
), vec
);
3754 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3756 Builder
bld(ctx
->program
, ctx
->block
);
3758 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3759 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3760 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3761 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3763 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3764 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3765 bool indirect_write
;
3766 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3767 if (temp_only_input
&& !indirect_write
)
3771 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3772 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3773 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3774 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3775 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3779 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3780 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3781 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3782 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3783 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3784 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3785 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3786 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3787 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3788 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3789 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3790 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3791 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3793 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3794 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3795 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3797 unreachable("Invalid LS or ES stage");
3800 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3801 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3802 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3806 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3808 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3809 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3810 off
!= ctx
->tcs_tess_lvl_in_loc
;
3813 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3815 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3816 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3819 uint64_t mask
= per_vertex
3820 ? ctx
->shader
->info
.outputs_read
3821 : ctx
->shader
->info
.patch_outputs_read
;
3822 bool indirect_write
;
3823 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3824 return indirect_write
|| output_read
;
3827 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3829 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3830 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3832 Builder
bld(ctx
->program
, ctx
->block
);
3834 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3835 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3836 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3838 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3839 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3840 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3841 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3843 if (write_to_vmem
) {
3844 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3845 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3846 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3848 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3849 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3850 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3854 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3855 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3856 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3860 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3862 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3863 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3865 Builder
bld(ctx
->program
, ctx
->block
);
3867 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3868 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3869 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3870 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3872 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3875 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3877 if (ctx
->stage
== vertex_vs
||
3878 ctx
->stage
== tess_eval_vs
||
3879 ctx
->stage
== fragment_fs
||
3880 ctx
->stage
== ngg_vertex_gs
||
3881 ctx
->stage
== ngg_tess_eval_gs
||
3882 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3883 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3884 if (!stored_to_temps
) {
3885 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3886 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3887 fprintf(stderr
, "\n");
3890 } else if (ctx
->stage
== vertex_es
||
3891 ctx
->stage
== vertex_ls
||
3892 ctx
->stage
== tess_eval_es
||
3893 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3894 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3895 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3896 visit_store_ls_or_es_output(ctx
, instr
);
3897 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3898 visit_store_tcs_output(ctx
, instr
, false);
3900 unreachable("Shader stage not implemented");
3904 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3906 visit_load_tcs_output(ctx
, instr
, false);
3909 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3911 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3912 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3914 Builder
bld(ctx
->program
, ctx
->block
);
3915 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3916 if (ctx
->program
->has_16bank_lds
)
3917 interp_p1
.instr
->operands
[0].setLateKill(true);
3918 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3921 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3923 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3924 for (unsigned i
= 0; i
< num_components
; i
++)
3925 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3926 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3927 assert(num_components
== 4);
3928 Builder
bld(ctx
->program
, ctx
->block
);
3929 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3932 for (Operand
& op
: vec
->operands
)
3933 op
= op
.isUndefined() ? Operand(0u) : op
;
3935 vec
->definitions
[0] = Definition(dst
);
3936 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3937 emit_split_vector(ctx
, dst
, num_components
);
3941 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3943 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3944 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3945 unsigned idx
= nir_intrinsic_base(instr
);
3946 unsigned component
= nir_intrinsic_component(instr
);
3947 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3949 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3951 assert(offset
->u32
== 0);
3953 /* the lower 15bit of the prim_mask contain the offset into LDS
3954 * while the upper bits contain the number of prims */
3955 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3956 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3957 Builder
bld(ctx
->program
, ctx
->block
);
3958 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3959 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3960 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3961 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3962 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3965 if (instr
->dest
.ssa
.num_components
== 1) {
3966 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3968 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3969 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3971 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3972 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3973 vec
->operands
[i
] = Operand(tmp
);
3975 vec
->definitions
[0] = Definition(dst
);
3976 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3980 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3981 unsigned offset
, unsigned stride
, unsigned channels
)
3983 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3984 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3986 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3987 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3990 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3991 unsigned offset
, unsigned stride
, unsigned *channels
)
3993 if (!vtx_info
->chan_byte_size
) {
3994 *channels
= vtx_info
->num_channels
;
3995 return vtx_info
->chan_format
;
3998 unsigned num_channels
= *channels
;
3999 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4000 unsigned new_channels
= num_channels
+ 1;
4001 /* first, assume more loads is worse and try using a larger data format */
4002 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4004 /* don't make the attribute potentially out-of-bounds */
4005 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4009 if (new_channels
== 5) {
4010 /* then try decreasing load size (at the cost of more loads) */
4011 new_channels
= *channels
;
4012 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4016 if (new_channels
< *channels
)
4017 *channels
= new_channels
;
4018 num_channels
= new_channels
;
4021 switch (vtx_info
->chan_format
) {
4022 case V_008F0C_BUF_DATA_FORMAT_8
:
4023 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4024 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4025 case V_008F0C_BUF_DATA_FORMAT_16
:
4026 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4027 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4028 case V_008F0C_BUF_DATA_FORMAT_32
:
4029 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4030 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4032 unreachable("shouldn't reach here");
4033 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4036 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4037 * so we may need to fix it up. */
4038 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4040 Builder
bld(ctx
->program
, ctx
->block
);
4042 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4043 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4045 /* For the integer-like cases, do a natural sign extension.
4047 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4048 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4051 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4052 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4054 /* Convert back to the right type. */
4055 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4056 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4057 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4058 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4059 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4060 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4066 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4068 Builder
bld(ctx
->program
, ctx
->block
);
4069 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4070 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4072 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4073 if (off_instr
->type
!= nir_instr_type_load_const
) {
4074 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4075 nir_print_instr(off_instr
, stderr
);
4076 fprintf(stderr
, "\n");
4078 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4080 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4082 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4083 unsigned component
= nir_intrinsic_component(instr
);
4084 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4085 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4086 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4087 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4089 unsigned dfmt
= attrib_format
& 0xf;
4090 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4091 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4093 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4094 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4095 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4096 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4098 num_channels
= MAX2(num_channels
, 3);
4100 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4101 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4104 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4105 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4106 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4108 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4110 Temp divided
= bld
.tmp(v1
);
4111 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4112 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4114 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4117 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4120 index
= bld
.vadd32(bld
.def(v1
),
4121 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4122 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4125 Temp channels
[num_channels
];
4126 unsigned channel_start
= 0;
4127 bool direct_fetch
= false;
4129 /* skip unused channels at the start */
4130 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4131 channel_start
= ffs(mask
) - 1;
4132 for (unsigned i
= 0; i
< channel_start
; i
++)
4133 channels
[i
] = Temp(0, s1
);
4134 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4135 num_channels
= 3 - (ffs(mask
) - 1);
4139 while (channel_start
< num_channels
) {
4140 unsigned fetch_size
= num_channels
- channel_start
;
4141 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4142 bool expanded
= false;
4144 /* use MUBUF when possible to avoid possible alignment issues */
4145 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4146 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4147 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4148 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4149 vtx_info
->chan_byte_size
== 4;
4150 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4152 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4154 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4155 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4161 Temp fetch_index
= index
;
4162 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4163 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4164 fetch_offset
= fetch_offset
% attrib_stride
;
4167 Operand
soffset(0u);
4168 if (fetch_offset
>= 4096) {
4169 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4170 fetch_offset
%= 4096;
4174 switch (fetch_size
) {
4176 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4179 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4182 assert(ctx
->options
->chip_class
>= GFX7
||
4183 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4184 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4187 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4190 unreachable("Unimplemented load_input vector size");
4194 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4195 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4196 num_channels
<= 3)) {
4197 direct_fetch
= true;
4200 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4204 Instruction
*mubuf
= bld
.mubuf(opcode
,
4205 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4206 fetch_offset
, false, true).instr
;
4207 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4209 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4210 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4211 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4212 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4215 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4217 if (fetch_size
== 1) {
4218 channels
[channel_start
] = fetch_dst
;
4220 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4221 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4224 channel_start
+= fetch_size
;
4227 if (!direct_fetch
) {
4228 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4229 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4231 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4232 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4233 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4235 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4236 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4237 unsigned num_temp
= 0;
4238 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4239 unsigned idx
= i
+ component
;
4240 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4241 Temp channel
= channels
[swizzle
[idx
]];
4242 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4243 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4244 vec
->operands
[i
] = Operand(channel
);
4248 } else if (is_float
&& idx
== 3) {
4249 vec
->operands
[i
] = Operand(0x3f800000u
);
4250 } else if (!is_float
&& idx
== 3) {
4251 vec
->operands
[i
] = Operand(1u);
4253 vec
->operands
[i
] = Operand(0u);
4256 vec
->definitions
[0] = Definition(dst
);
4257 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4258 emit_split_vector(ctx
, dst
, dst
.size());
4260 if (num_temp
== dst
.size())
4261 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4263 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4264 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4265 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4266 if (off_instr
->type
!= nir_instr_type_load_const
||
4267 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4268 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4269 nir_print_instr(off_instr
, stderr
);
4270 fprintf(stderr
, "\n");
4273 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4274 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4276 assert(offset
->u32
== 0);
4278 /* the lower 15bit of the prim_mask contain the offset into LDS
4279 * while the upper bits contain the number of prims */
4280 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4281 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4282 Builder
bld(ctx
->program
, ctx
->block
);
4283 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4284 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4285 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4286 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4287 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4290 unsigned idx
= nir_intrinsic_base(instr
);
4291 unsigned component
= nir_intrinsic_component(instr
);
4292 unsigned vertex_id
= 2; /* P0 */
4294 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4295 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4296 switch (src0
->u32
) {
4298 vertex_id
= 2; /* P0 */
4301 vertex_id
= 0; /* P10 */
4304 vertex_id
= 1; /* P20 */
4307 unreachable("invalid vertex index");
4311 if (dst
.size() == 1) {
4312 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4314 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4315 for (unsigned i
= 0; i
< dst
.size(); i
++)
4316 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4317 vec
->definitions
[0] = Definition(dst
);
4318 bld
.insert(std::move(vec
));
4321 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4322 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4323 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4324 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4325 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4327 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4329 unreachable("Shader stage not implemented");
4333 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4335 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4337 Builder
bld(ctx
->program
, ctx
->block
);
4338 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4341 if (!nir_src_is_const(*vertex_src
)) {
4342 /* better code could be created, but this case probably doesn't happen
4343 * much in practice */
4344 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4345 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4348 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4349 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4351 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4353 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4356 if (vertex_offset
.id()) {
4357 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4358 Operand(i
), indirect_vertex
);
4359 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4361 vertex_offset
= elem
;
4365 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4366 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4368 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4369 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4370 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4371 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4372 Operand((vertex
% 2u) * 16u), Operand(16u));
4374 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4377 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4378 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4379 return offset_mul(ctx
, offs
, 4u);
4382 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4384 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4386 Builder
bld(ctx
->program
, ctx
->block
);
4387 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4388 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4390 if (ctx
->stage
== geometry_gs
) {
4391 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4392 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4393 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4394 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4395 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4396 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4397 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4399 unreachable("Unsupported GS stage.");
4403 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4405 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4407 Builder
bld(ctx
->program
, ctx
->block
);
4408 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4410 if (load_input_from_temps(ctx
, instr
, dst
))
4413 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4414 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4415 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4417 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4420 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4422 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4424 Builder
bld(ctx
->program
, ctx
->block
);
4426 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4427 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4428 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4430 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4431 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4433 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4436 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4438 switch (ctx
->shader
->info
.stage
) {
4439 case MESA_SHADER_GEOMETRY
:
4440 visit_load_gs_per_vertex_input(ctx
, instr
);
4442 case MESA_SHADER_TESS_CTRL
:
4443 visit_load_tcs_per_vertex_input(ctx
, instr
);
4445 case MESA_SHADER_TESS_EVAL
:
4446 visit_load_tes_per_vertex_input(ctx
, instr
);
4449 unreachable("Unimplemented shader stage");
4453 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4455 visit_load_tcs_output(ctx
, instr
, true);
4458 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4460 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4461 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4463 visit_store_tcs_output(ctx
, instr
, true);
4466 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4468 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4470 Builder
bld(ctx
->program
, ctx
->block
);
4471 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4473 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4474 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4477 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4478 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4479 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4480 tes_w
= Operand(tmp
);
4483 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4484 emit_split_vector(ctx
, tess_coord
, 3);
4487 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4489 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4490 Builder
bld(ctx
->program
, ctx
->block
);
4491 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4492 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4493 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4496 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4500 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4502 Builder
bld(ctx
->program
, ctx
->block
);
4503 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4504 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4505 index
= bld
.as_uniform(index
);
4506 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4507 unsigned binding
= nir_intrinsic_binding(instr
);
4510 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4511 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4512 unsigned offset
= layout
->binding
[binding
].offset
;
4514 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4515 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4516 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4517 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4518 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4521 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4522 stride
= layout
->binding
[binding
].size
;
4525 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4526 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4528 if (nir_const_index
) {
4529 const_index
= const_index
* stride
;
4530 } else if (index
.type() == RegType::vgpr
) {
4531 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4532 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4534 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4538 if (nir_const_index
) {
4539 const_index
= const_index
+ offset
;
4540 } else if (index
.type() == RegType::vgpr
) {
4541 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4543 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4547 if (nir_const_index
&& const_index
== 0) {
4549 } else if (index
.type() == RegType::vgpr
) {
4550 index
= bld
.vadd32(bld
.def(v1
),
4551 nir_const_index
? Operand(const_index
) : Operand(index
),
4554 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4555 nir_const_index
? Operand(const_index
) : Operand(index
),
4559 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4562 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4563 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4564 bool glc
=false, bool readonly
=true)
4566 Builder
bld(ctx
->program
, ctx
->block
);
4567 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4568 unsigned num_bytes
= num_components
* component_size
;
4571 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4572 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4573 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4574 unsigned const_offset
= 0;
4576 /* for small bit sizes add buffer for unaligned loads */
4579 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4584 Temp lower
= Temp();
4585 if (num_bytes
> 16) {
4586 assert(num_components
== 3 || num_components
== 4);
4587 op
= aco_opcode::buffer_load_dwordx4
;
4588 lower
= bld
.tmp(v4
);
4589 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4590 mubuf
->definitions
[0] = Definition(lower
);
4591 mubuf
->operands
[0] = Operand(rsrc
);
4592 mubuf
->operands
[1] = vaddr
;
4593 mubuf
->operands
[2] = soffset
;
4594 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4597 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4598 mubuf
->can_reorder
= readonly
;
4599 bld
.insert(std::move(mubuf
));
4600 emit_split_vector(ctx
, lower
, 2);
4603 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4604 /* GFX6 doesn't support loading vec3, expand to vec4. */
4608 switch (num_bytes
) {
4610 op
= aco_opcode::buffer_load_ubyte
;
4613 op
= aco_opcode::buffer_load_ushort
;
4617 op
= aco_opcode::buffer_load_dword
;
4623 op
= aco_opcode::buffer_load_dwordx2
;
4627 assert(ctx
->options
->chip_class
> GFX6
);
4628 op
= aco_opcode::buffer_load_dwordx3
;
4631 op
= aco_opcode::buffer_load_dwordx4
;
4634 unreachable("Load SSBO not implemented for this size.");
4636 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4637 mubuf
->operands
[0] = Operand(rsrc
);
4638 mubuf
->operands
[1] = vaddr
;
4639 mubuf
->operands
[2] = soffset
;
4640 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4643 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4644 mubuf
->can_reorder
= readonly
;
4645 mubuf
->offset
= const_offset
;
4646 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4648 if (component_size
< 4) {
4649 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4650 instr
->definitions
[0] = Definition(vec
);
4651 bld
.insert(std::move(instr
));
4653 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4654 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4655 Temp tmp
[3] = {vec
, vec
, vec
};
4657 if (vec
.size() == 3) {
4658 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4659 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4660 } else if (vec
.size() == 2) {
4661 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4662 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4664 for (unsigned i
= 0; i
< dst
.size(); i
++)
4665 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4668 if (dst
.size() == 2)
4669 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4674 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4675 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4677 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4682 } else if (dst
.size() > 4) {
4683 assert(lower
!= Temp());
4684 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4685 instr
->definitions
[0] = Definition(upper
);
4686 bld
.insert(std::move(instr
));
4687 if (dst
.size() == 8)
4688 emit_split_vector(ctx
, upper
, 2);
4689 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4690 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4691 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4692 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4693 if (dst
.size() == 8)
4694 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4695 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4696 Temp vec
= bld
.tmp(v4
);
4697 instr
->definitions
[0] = Definition(vec
);
4698 bld
.insert(std::move(instr
));
4699 emit_split_vector(ctx
, vec
, 4);
4701 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4702 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4703 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4704 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4707 if (dst
.type() == RegType::sgpr
) {
4708 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4709 instr
->definitions
[0] = Definition(vec
);
4710 bld
.insert(std::move(instr
));
4711 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4713 instr
->definitions
[0] = Definition(dst
);
4714 bld
.insert(std::move(instr
));
4715 emit_split_vector(ctx
, dst
, num_components
);
4718 /* for small bit sizes add buffer for unaligned loads */
4720 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4722 switch (num_bytes
) {
4727 op
= aco_opcode::s_buffer_load_dword
;
4733 op
= aco_opcode::s_buffer_load_dwordx2
;
4738 op
= aco_opcode::s_buffer_load_dwordx4
;
4742 op
= aco_opcode::s_buffer_load_dwordx8
;
4745 unreachable("Load SSBO not implemented for this size.");
4747 offset
= bld
.as_uniform(offset
);
4748 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4749 load
->operands
[0] = Operand(rsrc
);
4750 load
->operands
[1] = Operand(offset
);
4751 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4752 load
->definitions
[0] = Definition(dst
);
4755 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4756 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4757 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4759 /* adjust misaligned small bit size loads */
4761 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4762 load
->definitions
[0] = Definition(vec
);
4763 bld
.insert(std::move(load
));
4764 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4765 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4768 } else if (dst
.size() == 3) {
4769 Temp vec
= bld
.tmp(s4
);
4770 load
->definitions
[0] = Definition(vec
);
4771 bld
.insert(std::move(load
));
4772 emit_split_vector(ctx
, vec
, 4);
4774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4775 emit_extract_vector(ctx
, vec
, 0, s1
),
4776 emit_extract_vector(ctx
, vec
, 1, s1
),
4777 emit_extract_vector(ctx
, vec
, 2, s1
));
4778 } else if (dst
.size() == 6) {
4779 Temp vec
= bld
.tmp(s8
);
4780 load
->definitions
[0] = Definition(vec
);
4781 bld
.insert(std::move(load
));
4782 emit_split_vector(ctx
, vec
, 4);
4784 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4785 emit_extract_vector(ctx
, vec
, 0, s2
),
4786 emit_extract_vector(ctx
, vec
, 1, s2
),
4787 emit_extract_vector(ctx
, vec
, 2, s2
));
4789 bld
.insert(std::move(load
));
4791 emit_split_vector(ctx
, dst
, num_components
);
4795 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4797 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4798 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4800 Builder
bld(ctx
->program
, ctx
->block
);
4802 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4803 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4804 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4805 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4807 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4808 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4809 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4810 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4811 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4812 if (ctx
->options
->chip_class
>= GFX10
) {
4813 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4814 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4815 S_008F0C_RESOURCE_LEVEL(1);
4817 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4818 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4820 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4821 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4822 Operand(0xFFFFFFFFu
),
4823 Operand(desc_type
));
4824 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4825 rsrc
, upper_dwords
);
4827 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4828 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4830 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4833 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4834 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4835 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4837 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4840 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4842 Builder
bld(ctx
->program
, ctx
->block
);
4843 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4844 unsigned offset
= nir_intrinsic_base(instr
);
4845 unsigned count
= instr
->dest
.ssa
.num_components
;
4846 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4848 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4849 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4850 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4851 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4852 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4853 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4854 for (unsigned i
= 0; i
< count
; ++i
) {
4855 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4856 vec
->operands
[i
] = Operand
{elems
[i
]};
4858 vec
->definitions
[0] = Definition(dst
);
4859 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4860 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4865 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4866 if (offset
!= 0) // TODO check if index != 0 as well
4867 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4868 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4871 bool aligned
= true;
4873 if (instr
->dest
.ssa
.bit_size
== 8) {
4874 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4875 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4877 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4878 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4879 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4881 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4886 switch (vec
.size()) {
4888 op
= aco_opcode::s_load_dword
;
4891 op
= aco_opcode::s_load_dwordx2
;
4897 op
= aco_opcode::s_load_dwordx4
;
4903 op
= aco_opcode::s_load_dwordx8
;
4906 unreachable("unimplemented or forbidden load_push_constant.");
4909 bld
.smem(op
, Definition(vec
), ptr
, index
);
4912 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4913 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4918 emit_split_vector(ctx
, vec
, 4);
4919 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4920 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4921 emit_extract_vector(ctx
, vec
, 0, rc
),
4922 emit_extract_vector(ctx
, vec
, 1, rc
),
4923 emit_extract_vector(ctx
, vec
, 2, rc
));
4926 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4929 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4931 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4933 Builder
bld(ctx
->program
, ctx
->block
);
4935 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4936 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4937 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4938 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4939 if (ctx
->options
->chip_class
>= GFX10
) {
4940 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4941 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4942 S_008F0C_RESOURCE_LEVEL(1);
4944 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4945 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4948 unsigned base
= nir_intrinsic_base(instr
);
4949 unsigned range
= nir_intrinsic_range(instr
);
4951 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4952 if (base
&& offset
.type() == RegType::sgpr
)
4953 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4954 else if (base
&& offset
.type() == RegType::vgpr
)
4955 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4957 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4958 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4959 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4960 Operand(desc_type
));
4961 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4962 // TODO: get alignment information for subdword constants
4963 unsigned byte_align
= size
< 4 ? -1 : 0;
4964 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
4967 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4969 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4970 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4972 ctx
->program
->needs_exact
= true;
4974 // TODO: optimize uniform conditions
4975 Builder
bld(ctx
->program
, ctx
->block
);
4976 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4977 assert(src
.regClass() == bld
.lm
);
4978 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4979 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4980 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4984 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4986 Builder
bld(ctx
->program
, ctx
->block
);
4988 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4989 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4991 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4992 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4994 if (ctx
->block
->loop_nest_depth
&&
4995 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4996 /* we handle discards the same way as jump instructions */
4997 append_logical_end(ctx
->block
);
4999 /* in loops, discard behaves like break */
5000 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5001 ctx
->block
->kind
|= block_kind_discard
;
5004 /* uniform discard - loop ends here */
5005 assert(nir_instr_is_last(&instr
->instr
));
5006 ctx
->block
->kind
|= block_kind_uniform
;
5007 ctx
->cf_info
.has_branch
= true;
5008 bld
.branch(aco_opcode::p_branch
);
5009 add_linear_edge(ctx
->block
->index
, linear_target
);
5013 /* we add a break right behind the discard() instructions */
5014 ctx
->block
->kind
|= block_kind_break
;
5015 unsigned idx
= ctx
->block
->index
;
5017 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5018 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5020 /* remove critical edges from linear CFG */
5021 bld
.branch(aco_opcode::p_branch
);
5022 Block
* break_block
= ctx
->program
->create_and_insert_block();
5023 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5024 break_block
->kind
|= block_kind_uniform
;
5025 add_linear_edge(idx
, break_block
);
5026 add_linear_edge(break_block
->index
, linear_target
);
5027 bld
.reset(break_block
);
5028 bld
.branch(aco_opcode::p_branch
);
5030 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5031 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5032 add_linear_edge(idx
, continue_block
);
5033 append_logical_start(continue_block
);
5034 ctx
->block
= continue_block
;
5039 /* it can currently happen that NIR doesn't remove the unreachable code */
5040 if (!nir_instr_is_last(&instr
->instr
)) {
5041 ctx
->program
->needs_exact
= true;
5042 /* save exec somewhere temporarily so that it doesn't get
5043 * overwritten before the discard from outer exec masks */
5044 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5045 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5046 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5050 /* This condition is incorrect for uniformly branched discards in a loop
5051 * predicated by a divergent condition, but the above code catches that case
5052 * and the discard would end up turning into a discard_if.
5062 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5063 /* program just ends here */
5064 ctx
->block
->kind
|= block_kind_uniform
;
5065 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5066 0 /* enabled mask */, 9 /* dest */,
5067 false /* compressed */, true/* done */, true /* valid mask */);
5068 bld
.sopp(aco_opcode::s_endpgm
);
5069 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5071 ctx
->block
->kind
|= block_kind_discard
;
5072 /* branch and linear edge is added by visit_if() */
5076 enum aco_descriptor_type
{
5087 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5088 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5090 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5091 return dim
== ac_image_cube
||
5092 dim
== ac_image_1darray
||
5093 dim
== ac_image_2darray
||
5094 dim
== ac_image_2darraymsaa
;
5097 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5098 enum aco_descriptor_type desc_type
,
5099 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5101 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5102 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5103 if (it != ctx->tex_desc.end())
5106 Temp index
= Temp();
5107 bool index_set
= false;
5108 unsigned constant_index
= 0;
5109 unsigned descriptor_set
;
5110 unsigned base_index
;
5111 Builder
bld(ctx
->program
, ctx
->block
);
5114 assert(tex_instr
&& !image
);
5116 base_index
= tex_instr
->sampler_index
;
5118 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5119 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5123 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5124 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5126 constant_index
+= array_size
* const_value
->u32
;
5128 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5129 if (indirect
.type() == RegType::vgpr
)
5130 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5132 if (array_size
!= 1)
5133 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5139 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5143 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5145 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5146 base_index
= deref_instr
->var
->data
.binding
;
5149 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5150 list
= convert_pointer_to_64_bit(ctx
, list
);
5152 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5153 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5154 unsigned offset
= binding
->offset
;
5155 unsigned stride
= binding
->size
;
5159 assert(base_index
< layout
->binding_count
);
5161 switch (desc_type
) {
5162 case ACO_DESC_IMAGE
:
5164 opcode
= aco_opcode::s_load_dwordx8
;
5166 case ACO_DESC_FMASK
:
5168 opcode
= aco_opcode::s_load_dwordx8
;
5171 case ACO_DESC_SAMPLER
:
5173 opcode
= aco_opcode::s_load_dwordx4
;
5174 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5175 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5177 case ACO_DESC_BUFFER
:
5179 opcode
= aco_opcode::s_load_dwordx4
;
5181 case ACO_DESC_PLANE_0
:
5182 case ACO_DESC_PLANE_1
:
5184 opcode
= aco_opcode::s_load_dwordx8
;
5185 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5187 case ACO_DESC_PLANE_2
:
5189 opcode
= aco_opcode::s_load_dwordx4
;
5193 unreachable("invalid desc_type\n");
5196 offset
+= constant_index
* stride
;
5198 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5199 (!index_set
|| binding
->immutable_samplers_equal
)) {
5200 if (binding
->immutable_samplers_equal
)
5203 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5204 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5205 Operand(samplers
[constant_index
* 4 + 0]),
5206 Operand(samplers
[constant_index
* 4 + 1]),
5207 Operand(samplers
[constant_index
* 4 + 2]),
5208 Operand(samplers
[constant_index
* 4 + 3]));
5213 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5215 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5216 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5219 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5221 if (desc_type
== ACO_DESC_PLANE_2
) {
5223 for (unsigned i
= 0; i
< 8; i
++)
5224 components
[i
] = bld
.tmp(s1
);
5225 bld
.pseudo(aco_opcode::p_split_vector
,
5226 Definition(components
[0]),
5227 Definition(components
[1]),
5228 Definition(components
[2]),
5229 Definition(components
[3]),
5232 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5233 bld
.pseudo(aco_opcode::p_split_vector
,
5234 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5235 Definition(components
[4]),
5236 Definition(components
[5]),
5237 Definition(components
[6]),
5238 Definition(components
[7]),
5241 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5242 components
[0], components
[1], components
[2], components
[3],
5243 components
[4], components
[5], components
[6], components
[7]);
5249 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5252 case GLSL_SAMPLER_DIM_BUF
:
5254 case GLSL_SAMPLER_DIM_1D
:
5255 return array
? 2 : 1;
5256 case GLSL_SAMPLER_DIM_2D
:
5257 return array
? 3 : 2;
5258 case GLSL_SAMPLER_DIM_MS
:
5259 return array
? 4 : 3;
5260 case GLSL_SAMPLER_DIM_3D
:
5261 case GLSL_SAMPLER_DIM_CUBE
:
5263 case GLSL_SAMPLER_DIM_RECT
:
5264 case GLSL_SAMPLER_DIM_SUBPASS
:
5266 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5275 /* Adjust the sample index according to FMASK.
5277 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5278 * which is the identity mapping. Each nibble says which physical sample
5279 * should be fetched to get that sample.
5281 * For example, 0x11111100 means there are only 2 samples stored and
5282 * the second sample covers 3/4 of the pixel. When reading samples 0
5283 * and 1, return physical sample 0 (determined by the first two 0s
5284 * in FMASK), otherwise return physical sample 1.
5286 * The sample index should be adjusted as follows:
5287 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5289 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5291 Builder
bld(ctx
->program
, ctx
->block
);
5292 Temp fmask
= bld
.tmp(v1
);
5293 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5294 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5297 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5298 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5299 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5300 load
->operands
[0] = Operand(fmask_desc_ptr
);
5301 load
->operands
[1] = Operand(s4
); /* no sampler */
5302 load
->operands
[2] = Operand(coord
);
5303 load
->definitions
[0] = Definition(fmask
);
5310 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5311 ctx
->block
->instructions
.emplace_back(std::move(load
));
5313 Operand sample_index4
;
5314 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5315 sample_index4
= Operand(sample_index
.constantValue() << 2);
5316 } else if (sample_index
.regClass() == s1
) {
5317 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5319 assert(sample_index
.regClass() == v1
);
5320 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5324 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5325 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5326 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5327 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5329 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5331 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5332 * resource descriptor is 0 (invalid),
5334 Temp compare
= bld
.tmp(bld
.lm
);
5335 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5336 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5338 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5340 /* Replace the MSAA sample index. */
5341 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5344 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5347 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5348 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5349 bool is_array
= glsl_sampler_type_is_array(type
);
5350 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5351 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5352 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5353 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5354 int count
= image_type_to_components_count(dim
, is_array
);
5355 std::vector
<Temp
> coords(count
);
5356 Builder
bld(ctx
->program
, ctx
->block
);
5360 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5361 /* get sample index */
5362 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5363 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5364 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5365 std::vector
<Temp
> fmask_load_address
;
5366 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5367 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5369 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5370 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5372 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5377 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5378 coords
.resize(coords
.size() + 1);
5379 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5381 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5383 for (int i
= 0; i
< count
; i
++)
5384 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5387 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5388 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5389 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5390 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5393 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5396 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5397 for (unsigned i
= 0; i
< coords
.size(); i
++)
5398 vec
->operands
[i
] = Operand(coords
[i
]);
5399 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5400 vec
->definitions
[0] = Definition(res
);
5401 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5406 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5408 Builder
bld(ctx
->program
, ctx
->block
);
5409 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5410 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5411 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5412 bool is_array
= glsl_sampler_type_is_array(type
);
5413 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5415 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5416 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5417 unsigned num_channels
= util_last_bit(mask
);
5418 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5419 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5422 switch (num_channels
) {
5424 opcode
= aco_opcode::buffer_load_format_x
;
5427 opcode
= aco_opcode::buffer_load_format_xy
;
5430 opcode
= aco_opcode::buffer_load_format_xyz
;
5433 opcode
= aco_opcode::buffer_load_format_xyzw
;
5436 unreachable(">4 channel buffer image load");
5438 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5439 load
->operands
[0] = Operand(rsrc
);
5440 load
->operands
[1] = Operand(vindex
);
5441 load
->operands
[2] = Operand((uint32_t) 0);
5443 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5446 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5447 load
->definitions
[0] = Definition(tmp
);
5449 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5450 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5451 load
->barrier
= barrier_image
;
5452 ctx
->block
->instructions
.emplace_back(std::move(load
));
5454 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5458 Temp coords
= get_image_coords(ctx
, instr
, type
);
5459 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5461 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5462 unsigned num_components
= util_bitcount(dmask
);
5464 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5467 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5469 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5470 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5472 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5473 load
->operands
[0] = Operand(resource
);
5474 load
->operands
[1] = Operand(s4
); /* no sampler */
5475 load
->operands
[2] = Operand(coords
);
5476 load
->definitions
[0] = Definition(tmp
);
5477 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5478 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5479 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5480 load
->dmask
= dmask
;
5482 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5483 load
->barrier
= barrier_image
;
5484 ctx
->block
->instructions
.emplace_back(std::move(load
));
5486 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5490 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5492 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5493 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5494 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5495 bool is_array
= glsl_sampler_type_is_array(type
);
5496 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5498 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5500 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5501 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5502 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5504 switch (data
.size()) {
5506 opcode
= aco_opcode::buffer_store_format_x
;
5509 opcode
= aco_opcode::buffer_store_format_xy
;
5512 opcode
= aco_opcode::buffer_store_format_xyz
;
5515 opcode
= aco_opcode::buffer_store_format_xyzw
;
5518 unreachable(">4 channel buffer image store");
5520 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5521 store
->operands
[0] = Operand(rsrc
);
5522 store
->operands
[1] = Operand(vindex
);
5523 store
->operands
[2] = Operand((uint32_t) 0);
5524 store
->operands
[3] = Operand(data
);
5525 store
->idxen
= true;
5528 store
->disable_wqm
= true;
5529 store
->barrier
= barrier_image
;
5530 ctx
->program
->needs_exact
= true;
5531 ctx
->block
->instructions
.emplace_back(std::move(store
));
5535 assert(data
.type() == RegType::vgpr
);
5536 Temp coords
= get_image_coords(ctx
, instr
, type
);
5537 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5539 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5540 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5542 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5543 store
->operands
[0] = Operand(resource
);
5544 store
->operands
[1] = Operand(data
);
5545 store
->operands
[2] = Operand(coords
);
5548 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5549 store
->dmask
= (1 << data
.size()) - 1;
5551 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5552 store
->disable_wqm
= true;
5553 store
->barrier
= barrier_image
;
5554 ctx
->program
->needs_exact
= true;
5555 ctx
->block
->instructions
.emplace_back(std::move(store
));
5559 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5561 /* return the previous value if dest is ever used */
5562 bool return_previous
= false;
5563 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5564 return_previous
= true;
5567 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5568 return_previous
= true;
5572 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5573 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5574 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5575 bool is_array
= glsl_sampler_type_is_array(type
);
5576 Builder
bld(ctx
->program
, ctx
->block
);
5578 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5579 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5581 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5582 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5584 aco_opcode buf_op
, image_op
;
5585 switch (instr
->intrinsic
) {
5586 case nir_intrinsic_image_deref_atomic_add
:
5587 buf_op
= aco_opcode::buffer_atomic_add
;
5588 image_op
= aco_opcode::image_atomic_add
;
5590 case nir_intrinsic_image_deref_atomic_umin
:
5591 buf_op
= aco_opcode::buffer_atomic_umin
;
5592 image_op
= aco_opcode::image_atomic_umin
;
5594 case nir_intrinsic_image_deref_atomic_imin
:
5595 buf_op
= aco_opcode::buffer_atomic_smin
;
5596 image_op
= aco_opcode::image_atomic_smin
;
5598 case nir_intrinsic_image_deref_atomic_umax
:
5599 buf_op
= aco_opcode::buffer_atomic_umax
;
5600 image_op
= aco_opcode::image_atomic_umax
;
5602 case nir_intrinsic_image_deref_atomic_imax
:
5603 buf_op
= aco_opcode::buffer_atomic_smax
;
5604 image_op
= aco_opcode::image_atomic_smax
;
5606 case nir_intrinsic_image_deref_atomic_and
:
5607 buf_op
= aco_opcode::buffer_atomic_and
;
5608 image_op
= aco_opcode::image_atomic_and
;
5610 case nir_intrinsic_image_deref_atomic_or
:
5611 buf_op
= aco_opcode::buffer_atomic_or
;
5612 image_op
= aco_opcode::image_atomic_or
;
5614 case nir_intrinsic_image_deref_atomic_xor
:
5615 buf_op
= aco_opcode::buffer_atomic_xor
;
5616 image_op
= aco_opcode::image_atomic_xor
;
5618 case nir_intrinsic_image_deref_atomic_exchange
:
5619 buf_op
= aco_opcode::buffer_atomic_swap
;
5620 image_op
= aco_opcode::image_atomic_swap
;
5622 case nir_intrinsic_image_deref_atomic_comp_swap
:
5623 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5624 image_op
= aco_opcode::image_atomic_cmpswap
;
5627 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5630 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5632 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5633 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5634 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5635 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5636 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5637 mubuf
->operands
[0] = Operand(resource
);
5638 mubuf
->operands
[1] = Operand(vindex
);
5639 mubuf
->operands
[2] = Operand((uint32_t)0);
5640 mubuf
->operands
[3] = Operand(data
);
5641 if (return_previous
)
5642 mubuf
->definitions
[0] = Definition(dst
);
5644 mubuf
->idxen
= true;
5645 mubuf
->glc
= return_previous
;
5646 mubuf
->dlc
= false; /* Not needed for atomics */
5647 mubuf
->disable_wqm
= true;
5648 mubuf
->barrier
= barrier_image
;
5649 ctx
->program
->needs_exact
= true;
5650 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5654 Temp coords
= get_image_coords(ctx
, instr
, type
);
5655 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5656 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5657 mimg
->operands
[0] = Operand(resource
);
5658 mimg
->operands
[1] = Operand(data
);
5659 mimg
->operands
[2] = Operand(coords
);
5660 if (return_previous
)
5661 mimg
->definitions
[0] = Definition(dst
);
5662 mimg
->glc
= return_previous
;
5663 mimg
->dlc
= false; /* Not needed for atomics */
5664 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5665 mimg
->dmask
= (1 << data
.size()) - 1;
5667 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5668 mimg
->disable_wqm
= true;
5669 mimg
->barrier
= barrier_image
;
5670 ctx
->program
->needs_exact
= true;
5671 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5675 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5677 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5678 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5679 Builder
bld(ctx
->program
, ctx
->block
);
5681 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5683 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5684 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5686 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5687 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5689 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5690 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5692 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5693 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5694 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5695 if (dst
.type() == RegType::vgpr
)
5696 bld
.copy(Definition(dst
), shr_dst
);
5698 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5700 emit_extract_vector(ctx
, desc
, 2, dst
);
5704 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5706 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5707 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5708 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5709 bool is_array
= glsl_sampler_type_is_array(type
);
5710 Builder
bld(ctx
->program
, ctx
->block
);
5712 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5713 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5714 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5718 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5721 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5723 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5725 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5726 mimg
->operands
[0] = Operand(resource
);
5727 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5728 mimg
->operands
[2] = Operand(lod
);
5729 uint8_t& dmask
= mimg
->dmask
;
5730 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5731 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5732 mimg
->da
= glsl_sampler_type_is_array(type
);
5733 mimg
->can_reorder
= true;
5734 Definition
& def
= mimg
->definitions
[0];
5735 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5737 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5738 glsl_sampler_type_is_array(type
)) {
5740 assert(instr
->dest
.ssa
.num_components
== 3);
5741 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5742 def
= Definition(tmp
);
5743 emit_split_vector(ctx
, tmp
, 3);
5745 /* divide 3rd value by 6 by multiplying with magic number */
5746 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5747 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5749 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5750 emit_extract_vector(ctx
, tmp
, 0, v1
),
5751 emit_extract_vector(ctx
, tmp
, 1, v1
),
5754 } else if (ctx
->options
->chip_class
== GFX9
&&
5755 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5756 glsl_sampler_type_is_array(type
)) {
5757 assert(instr
->dest
.ssa
.num_components
== 2);
5758 def
= Definition(dst
);
5761 def
= Definition(dst
);
5764 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5767 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5769 Builder
bld(ctx
->program
, ctx
->block
);
5770 unsigned num_components
= instr
->num_components
;
5772 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5773 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5774 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5776 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5777 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5780 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5781 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5782 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5784 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5787 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5789 Builder
bld(ctx
->program
, ctx
->block
);
5790 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5791 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5792 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5793 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5795 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5796 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5798 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5799 ctx
->options
->chip_class
>= GFX8
&&
5800 elem_size_bytes
>= 4;
5802 offset
= bld
.as_uniform(offset
);
5803 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5807 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5808 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5809 /* GFX6 doesn't support storing vec3, split it. */
5810 writemask
|= 1u << (start
+ 2);
5813 int num_bytes
= count
* elem_size_bytes
;
5815 /* dword or larger stores have to be dword-aligned */
5816 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5817 // TODO: improve alignment check of sub-dword stores
5818 unsigned count_new
= 2 / elem_size_bytes
;
5819 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5824 if (num_bytes
> 16) {
5825 assert(elem_size_bytes
== 8);
5826 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5832 if (elem_size_bytes
< 4) {
5833 if (data
.type() == RegType::sgpr
) {
5834 data
= as_vgpr(ctx
, data
);
5835 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5837 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5838 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5839 for (int i
= 0; i
< count
; i
++)
5840 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5841 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5842 vec
->definitions
[0] = Definition(write_data
);
5843 bld
.insert(std::move(vec
));
5844 } else if (count
!= instr
->num_components
) {
5845 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5846 for (int i
= 0; i
< count
; i
++) {
5847 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5848 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5850 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5851 vec
->definitions
[0] = Definition(write_data
);
5852 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5853 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5854 assert(num_bytes
% 4 == 0);
5855 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5856 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5857 assert(num_bytes
% 4 == 0);
5858 write_data
= bld
.as_uniform(data
);
5863 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5864 switch (num_bytes
) {
5866 vmem_op
= aco_opcode::buffer_store_byte
;
5869 vmem_op
= aco_opcode::buffer_store_short
;
5872 vmem_op
= aco_opcode::buffer_store_dword
;
5873 smem_op
= aco_opcode::s_buffer_store_dword
;
5876 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5877 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5880 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5881 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5884 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5885 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5888 unreachable("Store SSBO not implemented for this size.");
5890 if (ctx
->stage
== fragment_fs
)
5891 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5894 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5895 store
->operands
[0] = Operand(rsrc
);
5897 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5898 offset
, Operand(start
* elem_size_bytes
));
5899 store
->operands
[1] = Operand(off
);
5901 store
->operands
[1] = Operand(offset
);
5903 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5904 store
->operands
[1].setFixed(m0
);
5905 store
->operands
[2] = Operand(write_data
);
5906 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5908 store
->disable_wqm
= true;
5909 store
->barrier
= barrier_buffer
;
5910 ctx
->block
->instructions
.emplace_back(std::move(store
));
5911 ctx
->program
->wb_smem_l1_on_end
= true;
5912 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5913 ctx
->block
->kind
|= block_kind_needs_lowering
;
5914 ctx
->program
->needs_exact
= true;
5917 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5918 store
->operands
[0] = Operand(rsrc
);
5919 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5920 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5921 store
->operands
[3] = Operand(write_data
);
5922 store
->offset
= start
* elem_size_bytes
;
5923 store
->offen
= (offset
.type() == RegType::vgpr
);
5924 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5926 store
->disable_wqm
= true;
5927 store
->barrier
= barrier_buffer
;
5928 ctx
->program
->needs_exact
= true;
5929 ctx
->block
->instructions
.emplace_back(std::move(store
));
5934 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5936 /* return the previous value if dest is ever used */
5937 bool return_previous
= false;
5938 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5939 return_previous
= true;
5942 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5943 return_previous
= true;
5947 Builder
bld(ctx
->program
, ctx
->block
);
5948 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5950 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5951 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5952 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5954 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5955 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5956 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5958 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5960 aco_opcode op32
, op64
;
5961 switch (instr
->intrinsic
) {
5962 case nir_intrinsic_ssbo_atomic_add
:
5963 op32
= aco_opcode::buffer_atomic_add
;
5964 op64
= aco_opcode::buffer_atomic_add_x2
;
5966 case nir_intrinsic_ssbo_atomic_imin
:
5967 op32
= aco_opcode::buffer_atomic_smin
;
5968 op64
= aco_opcode::buffer_atomic_smin_x2
;
5970 case nir_intrinsic_ssbo_atomic_umin
:
5971 op32
= aco_opcode::buffer_atomic_umin
;
5972 op64
= aco_opcode::buffer_atomic_umin_x2
;
5974 case nir_intrinsic_ssbo_atomic_imax
:
5975 op32
= aco_opcode::buffer_atomic_smax
;
5976 op64
= aco_opcode::buffer_atomic_smax_x2
;
5978 case nir_intrinsic_ssbo_atomic_umax
:
5979 op32
= aco_opcode::buffer_atomic_umax
;
5980 op64
= aco_opcode::buffer_atomic_umax_x2
;
5982 case nir_intrinsic_ssbo_atomic_and
:
5983 op32
= aco_opcode::buffer_atomic_and
;
5984 op64
= aco_opcode::buffer_atomic_and_x2
;
5986 case nir_intrinsic_ssbo_atomic_or
:
5987 op32
= aco_opcode::buffer_atomic_or
;
5988 op64
= aco_opcode::buffer_atomic_or_x2
;
5990 case nir_intrinsic_ssbo_atomic_xor
:
5991 op32
= aco_opcode::buffer_atomic_xor
;
5992 op64
= aco_opcode::buffer_atomic_xor_x2
;
5994 case nir_intrinsic_ssbo_atomic_exchange
:
5995 op32
= aco_opcode::buffer_atomic_swap
;
5996 op64
= aco_opcode::buffer_atomic_swap_x2
;
5998 case nir_intrinsic_ssbo_atomic_comp_swap
:
5999 op32
= aco_opcode::buffer_atomic_cmpswap
;
6000 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6003 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6005 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6006 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6007 mubuf
->operands
[0] = Operand(rsrc
);
6008 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6009 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6010 mubuf
->operands
[3] = Operand(data
);
6011 if (return_previous
)
6012 mubuf
->definitions
[0] = Definition(dst
);
6014 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6015 mubuf
->glc
= return_previous
;
6016 mubuf
->dlc
= false; /* Not needed for atomics */
6017 mubuf
->disable_wqm
= true;
6018 mubuf
->barrier
= barrier_buffer
;
6019 ctx
->program
->needs_exact
= true;
6020 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6023 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6025 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6026 Builder
bld(ctx
->program
, ctx
->block
);
6027 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6028 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6031 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6033 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6034 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6036 if (addr
.type() == RegType::vgpr
)
6037 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6038 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6041 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6043 Builder
bld(ctx
->program
, ctx
->block
);
6044 unsigned num_components
= instr
->num_components
;
6045 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6047 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6048 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6050 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6051 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6053 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6054 bool global
= ctx
->options
->chip_class
>= GFX9
;
6056 if (ctx
->options
->chip_class
>= GFX7
) {
6058 switch (num_bytes
) {
6060 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6063 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6066 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6069 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6072 unreachable("load_global not implemented for this size.");
6075 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6076 flat
->operands
[0] = Operand(addr
);
6077 flat
->operands
[1] = Operand(s1
);
6080 flat
->barrier
= barrier_buffer
;
6082 if (dst
.type() == RegType::sgpr
) {
6083 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6084 flat
->definitions
[0] = Definition(vec
);
6085 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6086 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6088 flat
->definitions
[0] = Definition(dst
);
6089 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6091 emit_split_vector(ctx
, dst
, num_components
);
6093 assert(ctx
->options
->chip_class
== GFX6
);
6095 /* GFX6 doesn't support loading vec3, expand to vec4. */
6096 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6099 switch (num_bytes
) {
6101 op
= aco_opcode::buffer_load_dword
;
6104 op
= aco_opcode::buffer_load_dwordx2
;
6107 op
= aco_opcode::buffer_load_dwordx4
;
6110 unreachable("load_global not implemented for this size.");
6113 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6115 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6116 mubuf
->operands
[0] = Operand(rsrc
);
6117 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6118 mubuf
->operands
[2] = Operand(0u);
6122 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6123 mubuf
->disable_wqm
= false;
6124 mubuf
->barrier
= barrier_buffer
;
6125 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6128 if (dst
.size() == 3) {
6129 Temp vec
= bld
.tmp(v4
);
6130 instr
->definitions
[0] = Definition(vec
);
6131 bld
.insert(std::move(instr
));
6132 emit_split_vector(ctx
, vec
, 4);
6134 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6135 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6136 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6137 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6140 if (dst
.type() == RegType::sgpr
) {
6141 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6142 instr
->definitions
[0] = Definition(vec
);
6143 bld
.insert(std::move(instr
));
6144 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6145 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6147 instr
->definitions
[0] = Definition(dst
);
6148 bld
.insert(std::move(instr
));
6149 emit_split_vector(ctx
, dst
, num_components
);
6153 switch (num_bytes
) {
6155 op
= aco_opcode::s_load_dword
;
6158 op
= aco_opcode::s_load_dwordx2
;
6162 op
= aco_opcode::s_load_dwordx4
;
6165 unreachable("load_global not implemented for this size.");
6167 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6168 load
->operands
[0] = Operand(addr
);
6169 load
->operands
[1] = Operand(0u);
6170 load
->definitions
[0] = Definition(dst
);
6173 load
->barrier
= barrier_buffer
;
6174 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6176 if (dst
.size() == 3) {
6178 Temp vec
= bld
.tmp(s4
);
6179 load
->definitions
[0] = Definition(vec
);
6180 ctx
->block
->instructions
.emplace_back(std::move(load
));
6181 emit_split_vector(ctx
, vec
, 4);
6183 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6184 emit_extract_vector(ctx
, vec
, 0, s1
),
6185 emit_extract_vector(ctx
, vec
, 1, s1
),
6186 emit_extract_vector(ctx
, vec
, 2, s1
));
6188 ctx
->block
->instructions
.emplace_back(std::move(load
));
6193 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6195 Builder
bld(ctx
->program
, ctx
->block
);
6196 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6198 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6199 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6201 if (ctx
->options
->chip_class
>= GFX7
)
6202 addr
= as_vgpr(ctx
, addr
);
6204 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6207 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6208 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6209 /* GFX6 doesn't support storing vec3, split it. */
6210 writemask
|= 1u << (start
+ 2);
6213 unsigned num_bytes
= count
* elem_size_bytes
;
6215 Temp write_data
= data
;
6216 if (count
!= instr
->num_components
) {
6217 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6218 for (int i
= 0; i
< count
; i
++)
6219 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6220 write_data
= bld
.tmp(RegType::vgpr
, count
);
6221 vec
->definitions
[0] = Definition(write_data
);
6222 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6225 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6226 unsigned offset
= start
* elem_size_bytes
;
6228 if (ctx
->options
->chip_class
>= GFX7
) {
6229 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6230 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6231 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6232 Temp carry
= bld
.tmp(bld
.lm
);
6233 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6235 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6236 Operand(offset
), addr0
);
6237 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6239 carry
).def(1).setHint(vcc
);
6241 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6246 bool global
= ctx
->options
->chip_class
>= GFX9
;
6248 switch (num_bytes
) {
6250 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6253 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6256 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6259 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6262 unreachable("store_global not implemented for this size.");
6265 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6266 flat
->operands
[0] = Operand(addr
);
6267 flat
->operands
[1] = Operand(s1
);
6268 flat
->operands
[2] = Operand(data
);
6271 flat
->offset
= offset
;
6272 flat
->disable_wqm
= true;
6273 flat
->barrier
= barrier_buffer
;
6274 ctx
->program
->needs_exact
= true;
6275 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6277 assert(ctx
->options
->chip_class
== GFX6
);
6280 switch (num_bytes
) {
6282 op
= aco_opcode::buffer_store_dword
;
6285 op
= aco_opcode::buffer_store_dwordx2
;
6288 op
= aco_opcode::buffer_store_dwordx4
;
6291 unreachable("store_global not implemented for this size.");
6294 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6296 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6297 mubuf
->operands
[0] = Operand(rsrc
);
6298 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6299 mubuf
->operands
[2] = Operand(0u);
6300 mubuf
->operands
[3] = Operand(write_data
);
6303 mubuf
->offset
= offset
;
6304 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6305 mubuf
->disable_wqm
= true;
6306 mubuf
->barrier
= barrier_buffer
;
6307 ctx
->program
->needs_exact
= true;
6308 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6313 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6315 /* return the previous value if dest is ever used */
6316 bool return_previous
= false;
6317 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6318 return_previous
= true;
6321 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6322 return_previous
= true;
6326 Builder
bld(ctx
->program
, ctx
->block
);
6327 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6328 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6330 if (ctx
->options
->chip_class
>= GFX7
)
6331 addr
= as_vgpr(ctx
, addr
);
6333 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6334 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6335 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6337 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6339 aco_opcode op32
, op64
;
6341 if (ctx
->options
->chip_class
>= GFX7
) {
6342 bool global
= ctx
->options
->chip_class
>= GFX9
;
6343 switch (instr
->intrinsic
) {
6344 case nir_intrinsic_global_atomic_add
:
6345 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6346 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6348 case nir_intrinsic_global_atomic_imin
:
6349 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6350 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6352 case nir_intrinsic_global_atomic_umin
:
6353 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6354 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6356 case nir_intrinsic_global_atomic_imax
:
6357 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6358 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6360 case nir_intrinsic_global_atomic_umax
:
6361 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6362 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6364 case nir_intrinsic_global_atomic_and
:
6365 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6366 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6368 case nir_intrinsic_global_atomic_or
:
6369 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6370 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6372 case nir_intrinsic_global_atomic_xor
:
6373 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6374 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6376 case nir_intrinsic_global_atomic_exchange
:
6377 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6378 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6380 case nir_intrinsic_global_atomic_comp_swap
:
6381 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6382 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6385 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6388 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6389 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6390 flat
->operands
[0] = Operand(addr
);
6391 flat
->operands
[1] = Operand(s1
);
6392 flat
->operands
[2] = Operand(data
);
6393 if (return_previous
)
6394 flat
->definitions
[0] = Definition(dst
);
6395 flat
->glc
= return_previous
;
6396 flat
->dlc
= false; /* Not needed for atomics */
6398 flat
->disable_wqm
= true;
6399 flat
->barrier
= barrier_buffer
;
6400 ctx
->program
->needs_exact
= true;
6401 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6403 assert(ctx
->options
->chip_class
== GFX6
);
6405 switch (instr
->intrinsic
) {
6406 case nir_intrinsic_global_atomic_add
:
6407 op32
= aco_opcode::buffer_atomic_add
;
6408 op64
= aco_opcode::buffer_atomic_add_x2
;
6410 case nir_intrinsic_global_atomic_imin
:
6411 op32
= aco_opcode::buffer_atomic_smin
;
6412 op64
= aco_opcode::buffer_atomic_smin_x2
;
6414 case nir_intrinsic_global_atomic_umin
:
6415 op32
= aco_opcode::buffer_atomic_umin
;
6416 op64
= aco_opcode::buffer_atomic_umin_x2
;
6418 case nir_intrinsic_global_atomic_imax
:
6419 op32
= aco_opcode::buffer_atomic_smax
;
6420 op64
= aco_opcode::buffer_atomic_smax_x2
;
6422 case nir_intrinsic_global_atomic_umax
:
6423 op32
= aco_opcode::buffer_atomic_umax
;
6424 op64
= aco_opcode::buffer_atomic_umax_x2
;
6426 case nir_intrinsic_global_atomic_and
:
6427 op32
= aco_opcode::buffer_atomic_and
;
6428 op64
= aco_opcode::buffer_atomic_and_x2
;
6430 case nir_intrinsic_global_atomic_or
:
6431 op32
= aco_opcode::buffer_atomic_or
;
6432 op64
= aco_opcode::buffer_atomic_or_x2
;
6434 case nir_intrinsic_global_atomic_xor
:
6435 op32
= aco_opcode::buffer_atomic_xor
;
6436 op64
= aco_opcode::buffer_atomic_xor_x2
;
6438 case nir_intrinsic_global_atomic_exchange
:
6439 op32
= aco_opcode::buffer_atomic_swap
;
6440 op64
= aco_opcode::buffer_atomic_swap_x2
;
6442 case nir_intrinsic_global_atomic_comp_swap
:
6443 op32
= aco_opcode::buffer_atomic_cmpswap
;
6444 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6447 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6450 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6452 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6454 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6455 mubuf
->operands
[0] = Operand(rsrc
);
6456 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6457 mubuf
->operands
[2] = Operand(0u);
6458 mubuf
->operands
[3] = Operand(data
);
6459 if (return_previous
)
6460 mubuf
->definitions
[0] = Definition(dst
);
6461 mubuf
->glc
= return_previous
;
6464 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6465 mubuf
->disable_wqm
= true;
6466 mubuf
->barrier
= barrier_buffer
;
6467 ctx
->program
->needs_exact
= true;
6468 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6472 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6473 Builder
bld(ctx
->program
, ctx
->block
);
6474 switch(instr
->intrinsic
) {
6475 case nir_intrinsic_group_memory_barrier
:
6476 case nir_intrinsic_memory_barrier
:
6477 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6479 case nir_intrinsic_memory_barrier_buffer
:
6480 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6482 case nir_intrinsic_memory_barrier_image
:
6483 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6485 case nir_intrinsic_memory_barrier_tcs_patch
:
6486 case nir_intrinsic_memory_barrier_shared
:
6487 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6490 unreachable("Unimplemented memory barrier intrinsic");
6495 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6497 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6498 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6499 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6500 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6501 Builder
bld(ctx
->program
, ctx
->block
);
6503 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6504 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6505 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6508 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6510 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6511 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6512 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6513 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6514 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6516 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6517 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6520 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6522 unsigned offset
= nir_intrinsic_base(instr
);
6523 Operand m
= load_lds_size_m0(ctx
);
6524 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6525 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6527 unsigned num_operands
= 3;
6528 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6529 switch(instr
->intrinsic
) {
6530 case nir_intrinsic_shared_atomic_add
:
6531 op32
= aco_opcode::ds_add_u32
;
6532 op64
= aco_opcode::ds_add_u64
;
6533 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6534 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6536 case nir_intrinsic_shared_atomic_imin
:
6537 op32
= aco_opcode::ds_min_i32
;
6538 op64
= aco_opcode::ds_min_i64
;
6539 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6540 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6542 case nir_intrinsic_shared_atomic_umin
:
6543 op32
= aco_opcode::ds_min_u32
;
6544 op64
= aco_opcode::ds_min_u64
;
6545 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6546 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6548 case nir_intrinsic_shared_atomic_imax
:
6549 op32
= aco_opcode::ds_max_i32
;
6550 op64
= aco_opcode::ds_max_i64
;
6551 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6552 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6554 case nir_intrinsic_shared_atomic_umax
:
6555 op32
= aco_opcode::ds_max_u32
;
6556 op64
= aco_opcode::ds_max_u64
;
6557 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6558 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6560 case nir_intrinsic_shared_atomic_and
:
6561 op32
= aco_opcode::ds_and_b32
;
6562 op64
= aco_opcode::ds_and_b64
;
6563 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6564 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6566 case nir_intrinsic_shared_atomic_or
:
6567 op32
= aco_opcode::ds_or_b32
;
6568 op64
= aco_opcode::ds_or_b64
;
6569 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6570 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6572 case nir_intrinsic_shared_atomic_xor
:
6573 op32
= aco_opcode::ds_xor_b32
;
6574 op64
= aco_opcode::ds_xor_b64
;
6575 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6576 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6578 case nir_intrinsic_shared_atomic_exchange
:
6579 op32
= aco_opcode::ds_write_b32
;
6580 op64
= aco_opcode::ds_write_b64
;
6581 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6582 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6584 case nir_intrinsic_shared_atomic_comp_swap
:
6585 op32
= aco_opcode::ds_cmpst_b32
;
6586 op64
= aco_opcode::ds_cmpst_b64
;
6587 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6588 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6592 unreachable("Unhandled shared atomic intrinsic");
6595 /* return the previous value if dest is ever used */
6596 bool return_previous
= false;
6597 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6598 return_previous
= true;
6601 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6602 return_previous
= true;
6607 if (data
.size() == 1) {
6608 assert(instr
->dest
.ssa
.bit_size
== 32);
6609 op
= return_previous
? op32_rtn
: op32
;
6611 assert(instr
->dest
.ssa
.bit_size
== 64);
6612 op
= return_previous
? op64_rtn
: op64
;
6615 if (offset
> 65535) {
6616 Builder
bld(ctx
->program
, ctx
->block
);
6617 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6621 aco_ptr
<DS_instruction
> ds
;
6622 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6623 ds
->operands
[0] = Operand(address
);
6624 ds
->operands
[1] = Operand(data
);
6625 if (num_operands
== 4)
6626 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6627 ds
->operands
[num_operands
- 1] = m
;
6628 ds
->offset0
= offset
;
6629 if (return_previous
)
6630 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6631 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6634 Temp
get_scratch_resource(isel_context
*ctx
)
6636 Builder
bld(ctx
->program
, ctx
->block
);
6637 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6638 if (ctx
->stage
!= compute_cs
)
6639 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6641 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6642 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6644 if (ctx
->program
->chip_class
>= GFX10
) {
6645 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6646 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6647 S_008F0C_RESOURCE_LEVEL(1);
6648 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6649 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6650 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6653 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6654 if (ctx
->program
->chip_class
<= GFX8
)
6655 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6657 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6660 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6661 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6662 Builder
bld(ctx
->program
, ctx
->block
);
6663 Temp rsrc
= get_scratch_resource(ctx
);
6664 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6665 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6668 switch (dst
.size()) {
6670 op
= aco_opcode::buffer_load_dword
;
6673 op
= aco_opcode::buffer_load_dwordx2
;
6676 op
= aco_opcode::buffer_load_dwordx3
;
6679 op
= aco_opcode::buffer_load_dwordx4
;
6683 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6684 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6685 bld
.def(v4
), rsrc
, offset
,
6686 ctx
->program
->scratch_offset
, 0, true);
6687 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6688 aco_opcode::buffer_load_dwordx4
,
6689 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6690 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6691 emit_split_vector(ctx
, lower
, 2);
6692 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6693 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6694 if (dst
.size() == 8) {
6695 emit_split_vector(ctx
, upper
, 2);
6696 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6697 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6702 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6703 Format::PSEUDO
, dst
.size() / 2, 1)};
6704 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6705 vec
->operands
[i
] = Operand(elems
[i
]);
6706 vec
->definitions
[0] = Definition(dst
);
6707 bld
.insert(std::move(vec
));
6708 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6712 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6715 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6716 emit_split_vector(ctx
, dst
, instr
->num_components
);
6719 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6720 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6721 Builder
bld(ctx
->program
, ctx
->block
);
6722 Temp rsrc
= get_scratch_resource(ctx
);
6723 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6724 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6726 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6727 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6731 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6732 int num_bytes
= count
* elem_size_bytes
;
6734 if (num_bytes
> 16) {
6735 assert(elem_size_bytes
== 8);
6736 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6741 // TODO: check alignment of sub-dword stores
6742 // TODO: split 3 bytes. there is no store instruction for that
6745 if (count
!= instr
->num_components
) {
6746 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6747 for (int i
= 0; i
< count
; i
++) {
6748 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6749 vec
->operands
[i
] = Operand(elem
);
6751 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6752 vec
->definitions
[0] = Definition(write_data
);
6753 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6759 switch (num_bytes
) {
6761 op
= aco_opcode::buffer_store_dword
;
6764 op
= aco_opcode::buffer_store_dwordx2
;
6767 op
= aco_opcode::buffer_store_dwordx3
;
6770 op
= aco_opcode::buffer_store_dwordx4
;
6773 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6776 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6780 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6781 uint8_t log2_ps_iter_samples
;
6782 if (ctx
->program
->info
->ps
.force_persample
) {
6783 log2_ps_iter_samples
=
6784 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6786 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6789 /* The bit pattern matches that used by fixed function fragment
6791 static const unsigned ps_iter_masks
[] = {
6792 0xffff, /* not used */
6798 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6800 Builder
bld(ctx
->program
, ctx
->block
);
6802 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6803 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6804 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6805 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6806 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6807 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6810 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6811 Builder
bld(ctx
->program
, ctx
->block
);
6813 unsigned stream
= nir_intrinsic_stream_id(instr
);
6814 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6815 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6816 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6819 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6821 unsigned num_components
=
6822 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6823 assert(num_components
);
6825 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6826 unsigned stream_offset
= 0;
6827 for (unsigned i
= 0; i
< stream
; i
++) {
6828 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6829 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6832 /* Limit on the stride field for <= GFX7. */
6833 assert(stride
< (1 << 14));
6835 Temp gsvs_dwords
[4];
6836 for (unsigned i
= 0; i
< 4; i
++)
6837 gsvs_dwords
[i
] = bld
.tmp(s1
);
6838 bld
.pseudo(aco_opcode::p_split_vector
,
6839 Definition(gsvs_dwords
[0]),
6840 Definition(gsvs_dwords
[1]),
6841 Definition(gsvs_dwords
[2]),
6842 Definition(gsvs_dwords
[3]),
6845 if (stream_offset
) {
6846 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6848 Temp carry
= bld
.tmp(s1
);
6849 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6850 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6853 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6854 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6856 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6857 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6859 unsigned offset
= 0;
6860 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6861 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6864 for (unsigned j
= 0; j
< 4; j
++) {
6865 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6868 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6869 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6870 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6871 if (const_offset
>= 4096u) {
6872 if (vaddr_offset
.isUndefined())
6873 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6875 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6876 const_offset
%= 4096u;
6879 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6880 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6881 mtbuf
->operands
[1] = vaddr_offset
;
6882 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6883 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6884 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6885 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6886 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6887 mtbuf
->offset
= const_offset
;
6890 mtbuf
->barrier
= barrier_gs_data
;
6891 mtbuf
->can_reorder
= true;
6892 bld
.insert(std::move(mtbuf
));
6895 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6898 /* outputs for the next vertex are undefined and keeping them around can
6899 * create invalid IR with control flow */
6900 ctx
->outputs
.mask
[i
] = 0;
6903 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6906 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6908 Builder
bld(ctx
->program
, ctx
->block
);
6910 if (cluster_size
== 1) {
6912 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6913 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6914 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6915 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6916 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6917 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6918 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6919 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6920 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6921 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6922 //subgroupAnd(val) -> (exec & ~val) == 0
6923 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6924 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6925 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6926 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6927 //subgroupOr(val) -> (val & exec) != 0
6928 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6929 return bool_to_vector_condition(ctx
, tmp
);
6930 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6931 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6932 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6933 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6934 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6935 return bool_to_vector_condition(ctx
, tmp
);
6937 //subgroupClustered{And,Or,Xor}(val, n) ->
6938 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6939 //cluster_offset = ~(n - 1) & lane_id
6940 //cluster_mask = ((1 << n) - 1)
6941 //subgroupClusteredAnd():
6942 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6943 //subgroupClusteredOr():
6944 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6945 //subgroupClusteredXor():
6946 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6947 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6948 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6951 if (op
== nir_op_iand
)
6952 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6954 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6956 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6958 if (ctx
->program
->chip_class
<= GFX7
)
6959 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6960 else if (ctx
->program
->wave_size
== 64)
6961 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6963 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6964 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6965 if (cluster_mask
!= 0xffffffff)
6966 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6968 Definition cmp_def
= Definition();
6969 if (op
== nir_op_iand
) {
6970 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6971 } else if (op
== nir_op_ior
) {
6972 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6973 } else if (op
== nir_op_ixor
) {
6974 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6975 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6976 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6978 cmp_def
.setHint(vcc
);
6979 return cmp_def
.getTemp();
6983 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6985 Builder
bld(ctx
->program
, ctx
->block
);
6987 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6988 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6989 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6991 if (op
== nir_op_iand
)
6992 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6994 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6996 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6997 Temp lo
= lohi
.def(0).getTemp();
6998 Temp hi
= lohi
.def(1).getTemp();
6999 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7001 Definition cmp_def
= Definition();
7002 if (op
== nir_op_iand
)
7003 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7004 else if (op
== nir_op_ior
)
7005 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7006 else if (op
== nir_op_ixor
)
7007 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7008 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7009 cmp_def
.setHint(vcc
);
7010 return cmp_def
.getTemp();
7013 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7015 Builder
bld(ctx
->program
, ctx
->block
);
7017 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7018 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7019 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7020 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7021 if (op
== nir_op_iand
)
7022 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7023 else if (op
== nir_op_ior
)
7024 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7025 else if (op
== nir_op_ixor
)
7026 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7032 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7034 Builder
bld(ctx
->program
, ctx
->block
);
7035 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7036 if (src
.regClass().type() == RegType::vgpr
) {
7037 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7038 } else if (src
.regClass() == s1
) {
7039 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7040 } else if (src
.regClass() == s2
) {
7041 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7044 nir_print_instr(&instr
->instr
, stderr
);
7045 fprintf(stderr
, "\n");
7049 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7051 Builder
bld(ctx
->program
, ctx
->block
);
7052 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7053 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7054 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7056 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7057 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7058 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7059 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7062 if (ctx
->program
->chip_class
>= GFX8
) {
7063 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7064 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7065 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7066 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7067 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7068 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7070 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7071 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7072 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7073 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7074 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7075 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7076 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7077 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7078 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7079 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7082 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7083 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7084 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7085 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7086 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7087 Temp wqm1
= bld
.tmp(v1
);
7088 emit_wqm(ctx
, tmp1
, wqm1
, true);
7089 Temp wqm2
= bld
.tmp(v1
);
7090 emit_wqm(ctx
, tmp2
, wqm2
, true);
7091 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7095 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7097 Builder
bld(ctx
->program
, ctx
->block
);
7098 switch(instr
->intrinsic
) {
7099 case nir_intrinsic_load_barycentric_sample
:
7100 case nir_intrinsic_load_barycentric_pixel
:
7101 case nir_intrinsic_load_barycentric_centroid
: {
7102 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7103 Temp bary
= Temp(0, s2
);
7105 case INTERP_MODE_SMOOTH
:
7106 case INTERP_MODE_NONE
:
7107 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7108 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7109 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7110 bary
= ctx
->persp_centroid
;
7111 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7112 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7114 case INTERP_MODE_NOPERSPECTIVE
:
7115 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7116 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7117 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7118 bary
= ctx
->linear_centroid
;
7119 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7120 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7125 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7126 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7127 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7128 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7129 Operand(p1
), Operand(p2
));
7130 emit_split_vector(ctx
, dst
, 2);
7133 case nir_intrinsic_load_barycentric_model
: {
7134 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7136 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7137 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7138 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7139 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7140 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7141 Operand(p1
), Operand(p2
), Operand(p3
));
7142 emit_split_vector(ctx
, dst
, 3);
7145 case nir_intrinsic_load_barycentric_at_sample
: {
7146 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7147 switch (ctx
->options
->key
.fs
.num_samples
) {
7148 case 2: sample_pos_offset
+= 1 << 3; break;
7149 case 4: sample_pos_offset
+= 3 << 3; break;
7150 case 8: sample_pos_offset
+= 7 << 3; break;
7154 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7155 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7156 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7157 if (addr
.type() == RegType::sgpr
) {
7160 sample_pos_offset
+= const_addr
->u32
<< 3;
7161 offset
= Operand(sample_pos_offset
);
7162 } else if (ctx
->options
->chip_class
>= GFX9
) {
7163 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7165 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7166 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7169 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7170 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7172 } else if (ctx
->options
->chip_class
>= GFX9
) {
7173 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7174 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7175 } else if (ctx
->options
->chip_class
>= GFX7
) {
7176 /* addr += private_segment_buffer + sample_pos_offset */
7177 Temp tmp0
= bld
.tmp(s1
);
7178 Temp tmp1
= bld
.tmp(s1
);
7179 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7180 Definition scc_tmp
= bld
.def(s1
, scc
);
7181 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7182 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7183 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7184 Temp pck0
= bld
.tmp(v1
);
7185 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7186 tmp1
= as_vgpr(ctx
, tmp1
);
7187 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7188 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7190 /* sample_pos = flat_load_dwordx2 addr */
7191 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7193 assert(ctx
->options
->chip_class
== GFX6
);
7195 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7196 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7197 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7199 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7200 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7202 sample_pos
= bld
.tmp(v2
);
7204 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7205 load
->definitions
[0] = Definition(sample_pos
);
7206 load
->operands
[0] = Operand(rsrc
);
7207 load
->operands
[1] = Operand(addr
);
7208 load
->operands
[2] = Operand(0u);
7209 load
->offset
= sample_pos_offset
;
7211 load
->addr64
= true;
7214 load
->disable_wqm
= false;
7215 load
->barrier
= barrier_none
;
7216 load
->can_reorder
= true;
7217 ctx
->block
->instructions
.emplace_back(std::move(load
));
7220 /* sample_pos -= 0.5 */
7221 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7222 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7223 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7224 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7225 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7227 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7230 case nir_intrinsic_load_barycentric_at_offset
: {
7231 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7232 RegClass rc
= RegClass(offset
.type(), 1);
7233 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7234 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7235 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7238 case nir_intrinsic_load_front_face
: {
7239 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7240 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7243 case nir_intrinsic_load_view_index
: {
7244 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7245 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7246 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7252 case nir_intrinsic_load_layer_id
: {
7253 unsigned idx
= nir_intrinsic_base(instr
);
7254 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7255 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7258 case nir_intrinsic_load_frag_coord
: {
7259 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7262 case nir_intrinsic_load_sample_pos
: {
7263 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7264 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7265 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7266 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7267 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7270 case nir_intrinsic_load_tess_coord
:
7271 visit_load_tess_coord(ctx
, instr
);
7273 case nir_intrinsic_load_interpolated_input
:
7274 visit_load_interpolated_input(ctx
, instr
);
7276 case nir_intrinsic_store_output
:
7277 visit_store_output(ctx
, instr
);
7279 case nir_intrinsic_load_input
:
7280 case nir_intrinsic_load_input_vertex
:
7281 visit_load_input(ctx
, instr
);
7283 case nir_intrinsic_load_output
:
7284 visit_load_output(ctx
, instr
);
7286 case nir_intrinsic_load_per_vertex_input
:
7287 visit_load_per_vertex_input(ctx
, instr
);
7289 case nir_intrinsic_load_per_vertex_output
:
7290 visit_load_per_vertex_output(ctx
, instr
);
7292 case nir_intrinsic_store_per_vertex_output
:
7293 visit_store_per_vertex_output(ctx
, instr
);
7295 case nir_intrinsic_load_ubo
:
7296 visit_load_ubo(ctx
, instr
);
7298 case nir_intrinsic_load_push_constant
:
7299 visit_load_push_constant(ctx
, instr
);
7301 case nir_intrinsic_load_constant
:
7302 visit_load_constant(ctx
, instr
);
7304 case nir_intrinsic_vulkan_resource_index
:
7305 visit_load_resource(ctx
, instr
);
7307 case nir_intrinsic_discard
:
7308 visit_discard(ctx
, instr
);
7310 case nir_intrinsic_discard_if
:
7311 visit_discard_if(ctx
, instr
);
7313 case nir_intrinsic_load_shared
:
7314 visit_load_shared(ctx
, instr
);
7316 case nir_intrinsic_store_shared
:
7317 visit_store_shared(ctx
, instr
);
7319 case nir_intrinsic_shared_atomic_add
:
7320 case nir_intrinsic_shared_atomic_imin
:
7321 case nir_intrinsic_shared_atomic_umin
:
7322 case nir_intrinsic_shared_atomic_imax
:
7323 case nir_intrinsic_shared_atomic_umax
:
7324 case nir_intrinsic_shared_atomic_and
:
7325 case nir_intrinsic_shared_atomic_or
:
7326 case nir_intrinsic_shared_atomic_xor
:
7327 case nir_intrinsic_shared_atomic_exchange
:
7328 case nir_intrinsic_shared_atomic_comp_swap
:
7329 visit_shared_atomic(ctx
, instr
);
7331 case nir_intrinsic_image_deref_load
:
7332 visit_image_load(ctx
, instr
);
7334 case nir_intrinsic_image_deref_store
:
7335 visit_image_store(ctx
, instr
);
7337 case nir_intrinsic_image_deref_atomic_add
:
7338 case nir_intrinsic_image_deref_atomic_umin
:
7339 case nir_intrinsic_image_deref_atomic_imin
:
7340 case nir_intrinsic_image_deref_atomic_umax
:
7341 case nir_intrinsic_image_deref_atomic_imax
:
7342 case nir_intrinsic_image_deref_atomic_and
:
7343 case nir_intrinsic_image_deref_atomic_or
:
7344 case nir_intrinsic_image_deref_atomic_xor
:
7345 case nir_intrinsic_image_deref_atomic_exchange
:
7346 case nir_intrinsic_image_deref_atomic_comp_swap
:
7347 visit_image_atomic(ctx
, instr
);
7349 case nir_intrinsic_image_deref_size
:
7350 visit_image_size(ctx
, instr
);
7352 case nir_intrinsic_load_ssbo
:
7353 visit_load_ssbo(ctx
, instr
);
7355 case nir_intrinsic_store_ssbo
:
7356 visit_store_ssbo(ctx
, instr
);
7358 case nir_intrinsic_load_global
:
7359 visit_load_global(ctx
, instr
);
7361 case nir_intrinsic_store_global
:
7362 visit_store_global(ctx
, instr
);
7364 case nir_intrinsic_global_atomic_add
:
7365 case nir_intrinsic_global_atomic_imin
:
7366 case nir_intrinsic_global_atomic_umin
:
7367 case nir_intrinsic_global_atomic_imax
:
7368 case nir_intrinsic_global_atomic_umax
:
7369 case nir_intrinsic_global_atomic_and
:
7370 case nir_intrinsic_global_atomic_or
:
7371 case nir_intrinsic_global_atomic_xor
:
7372 case nir_intrinsic_global_atomic_exchange
:
7373 case nir_intrinsic_global_atomic_comp_swap
:
7374 visit_global_atomic(ctx
, instr
);
7376 case nir_intrinsic_ssbo_atomic_add
:
7377 case nir_intrinsic_ssbo_atomic_imin
:
7378 case nir_intrinsic_ssbo_atomic_umin
:
7379 case nir_intrinsic_ssbo_atomic_imax
:
7380 case nir_intrinsic_ssbo_atomic_umax
:
7381 case nir_intrinsic_ssbo_atomic_and
:
7382 case nir_intrinsic_ssbo_atomic_or
:
7383 case nir_intrinsic_ssbo_atomic_xor
:
7384 case nir_intrinsic_ssbo_atomic_exchange
:
7385 case nir_intrinsic_ssbo_atomic_comp_swap
:
7386 visit_atomic_ssbo(ctx
, instr
);
7388 case nir_intrinsic_load_scratch
:
7389 visit_load_scratch(ctx
, instr
);
7391 case nir_intrinsic_store_scratch
:
7392 visit_store_scratch(ctx
, instr
);
7394 case nir_intrinsic_get_buffer_size
:
7395 visit_get_buffer_size(ctx
, instr
);
7397 case nir_intrinsic_control_barrier
: {
7398 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7399 /* GFX6 only (thanks to a hw bug workaround):
7400 * The real barrier instruction isn’t needed, because an entire patch
7401 * always fits into a single wave.
7406 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7407 bld
.sopp(aco_opcode::s_barrier
);
7411 case nir_intrinsic_memory_barrier_tcs_patch
:
7412 case nir_intrinsic_group_memory_barrier
:
7413 case nir_intrinsic_memory_barrier
:
7414 case nir_intrinsic_memory_barrier_buffer
:
7415 case nir_intrinsic_memory_barrier_image
:
7416 case nir_intrinsic_memory_barrier_shared
:
7417 emit_memory_barrier(ctx
, instr
);
7419 case nir_intrinsic_load_num_work_groups
: {
7420 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7421 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7422 emit_split_vector(ctx
, dst
, 3);
7425 case nir_intrinsic_load_local_invocation_id
: {
7426 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7427 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7428 emit_split_vector(ctx
, dst
, 3);
7431 case nir_intrinsic_load_work_group_id
: {
7432 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7433 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7434 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7435 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7436 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7437 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7438 emit_split_vector(ctx
, dst
, 3);
7441 case nir_intrinsic_load_local_invocation_index
: {
7442 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7444 /* The tg_size bits [6:11] contain the subgroup id,
7445 * we need this multiplied by the wave size, and then OR the thread id to it.
7447 if (ctx
->program
->wave_size
== 64) {
7448 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7449 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7450 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7451 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7453 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7454 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7455 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7456 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7460 case nir_intrinsic_load_subgroup_id
: {
7461 if (ctx
->stage
== compute_cs
) {
7462 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7463 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7465 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7469 case nir_intrinsic_load_subgroup_invocation
: {
7470 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7473 case nir_intrinsic_load_num_subgroups
: {
7474 if (ctx
->stage
== compute_cs
)
7475 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7476 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7478 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7481 case nir_intrinsic_ballot
: {
7482 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7483 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7484 Definition tmp
= bld
.def(dst
.regClass());
7485 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7486 if (instr
->src
[0].ssa
->bit_size
== 1) {
7487 assert(src
.regClass() == bld
.lm
);
7488 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7489 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7490 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7491 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7492 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7494 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7495 nir_print_instr(&instr
->instr
, stderr
);
7496 fprintf(stderr
, "\n");
7498 if (dst
.size() != bld
.lm
.size()) {
7499 /* Wave32 with ballot size set to 64 */
7500 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7502 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7505 case nir_intrinsic_shuffle
:
7506 case nir_intrinsic_read_invocation
: {
7507 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7508 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7509 emit_uniform_subgroup(ctx
, instr
, src
);
7511 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7512 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7513 tid
= bld
.as_uniform(tid
);
7514 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7515 if (src
.regClass() == v1
) {
7516 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7517 } else if (src
.regClass() == v2
) {
7518 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7520 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7521 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7523 emit_split_vector(ctx
, dst
, 2);
7524 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7525 assert(src
.regClass() == bld
.lm
);
7526 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7527 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7528 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7529 assert(src
.regClass() == bld
.lm
);
7531 if (ctx
->program
->chip_class
<= GFX7
)
7532 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7533 else if (ctx
->program
->wave_size
== 64)
7534 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7536 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7537 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7538 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7539 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7541 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7542 nir_print_instr(&instr
->instr
, stderr
);
7543 fprintf(stderr
, "\n");
7548 case nir_intrinsic_load_sample_id
: {
7549 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7550 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7553 case nir_intrinsic_load_sample_mask_in
: {
7554 visit_load_sample_mask_in(ctx
, instr
);
7557 case nir_intrinsic_read_first_invocation
: {
7558 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7559 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7560 if (src
.regClass() == v1
) {
7562 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7564 } else if (src
.regClass() == v2
) {
7565 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7566 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7567 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7568 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7569 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7570 emit_split_vector(ctx
, dst
, 2);
7571 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7572 assert(src
.regClass() == bld
.lm
);
7573 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7574 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7575 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7576 } else if (src
.regClass() == s1
) {
7577 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7578 } else if (src
.regClass() == s2
) {
7579 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7581 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7582 nir_print_instr(&instr
->instr
, stderr
);
7583 fprintf(stderr
, "\n");
7587 case nir_intrinsic_vote_all
: {
7588 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7589 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7590 assert(src
.regClass() == bld
.lm
);
7591 assert(dst
.regClass() == bld
.lm
);
7593 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7594 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7595 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7598 case nir_intrinsic_vote_any
: {
7599 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7600 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7601 assert(src
.regClass() == bld
.lm
);
7602 assert(dst
.regClass() == bld
.lm
);
7604 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7605 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7608 case nir_intrinsic_reduce
:
7609 case nir_intrinsic_inclusive_scan
:
7610 case nir_intrinsic_exclusive_scan
: {
7611 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7612 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7613 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7614 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7615 nir_intrinsic_cluster_size(instr
) : 0;
7616 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7618 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7619 emit_uniform_subgroup(ctx
, instr
, src
);
7620 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7621 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7623 else if (op
== nir_op_iadd
)
7625 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7627 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7629 switch (instr
->intrinsic
) {
7630 case nir_intrinsic_reduce
:
7631 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7633 case nir_intrinsic_exclusive_scan
:
7634 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7636 case nir_intrinsic_inclusive_scan
:
7637 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7642 } else if (cluster_size
== 1) {
7643 bld
.copy(Definition(dst
), src
);
7645 src
= as_vgpr(ctx
, src
);
7649 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7664 unreachable("unknown reduction op");
7669 switch (instr
->intrinsic
) {
7670 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7671 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7672 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7674 unreachable("unknown reduce intrinsic");
7677 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7678 reduce
->operands
[0] = Operand(src
);
7679 // filled in by aco_reduce_assign.cpp, used internally as part of the
7681 assert(dst
.size() == 1 || dst
.size() == 2);
7682 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7683 reduce
->operands
[2] = Operand(v1
.as_linear());
7685 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7686 reduce
->definitions
[0] = Definition(tmp_dst
);
7687 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7688 reduce
->definitions
[2] = Definition();
7689 reduce
->definitions
[3] = Definition(scc
, s1
);
7690 reduce
->definitions
[4] = Definition();
7691 reduce
->reduce_op
= reduce_op
;
7692 reduce
->cluster_size
= cluster_size
;
7693 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7695 emit_wqm(ctx
, tmp_dst
, dst
);
7699 case nir_intrinsic_quad_broadcast
: {
7700 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7701 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7702 emit_uniform_subgroup(ctx
, instr
, src
);
7704 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7705 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7706 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7708 if (instr
->dest
.ssa
.bit_size
== 1) {
7709 assert(src
.regClass() == bld
.lm
);
7710 assert(dst
.regClass() == bld
.lm
);
7711 uint32_t half_mask
= 0x11111111u
<< lane
;
7712 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7713 Temp tmp
= bld
.tmp(bld
.lm
);
7714 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7715 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7716 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7717 emit_wqm(ctx
, tmp
, dst
);
7718 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7719 if (ctx
->program
->chip_class
>= GFX8
)
7720 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7722 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7723 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7724 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7725 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7726 if (ctx
->program
->chip_class
>= GFX8
) {
7727 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7728 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7730 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7731 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7733 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7734 emit_split_vector(ctx
, dst
, 2);
7736 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7737 nir_print_instr(&instr
->instr
, stderr
);
7738 fprintf(stderr
, "\n");
7743 case nir_intrinsic_quad_swap_horizontal
:
7744 case nir_intrinsic_quad_swap_vertical
:
7745 case nir_intrinsic_quad_swap_diagonal
:
7746 case nir_intrinsic_quad_swizzle_amd
: {
7747 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7748 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7749 emit_uniform_subgroup(ctx
, instr
, src
);
7752 uint16_t dpp_ctrl
= 0;
7753 switch (instr
->intrinsic
) {
7754 case nir_intrinsic_quad_swap_horizontal
:
7755 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7757 case nir_intrinsic_quad_swap_vertical
:
7758 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7760 case nir_intrinsic_quad_swap_diagonal
:
7761 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7763 case nir_intrinsic_quad_swizzle_amd
:
7764 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7769 if (ctx
->program
->chip_class
< GFX8
)
7770 dpp_ctrl
|= (1 << 15);
7772 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7773 if (instr
->dest
.ssa
.bit_size
== 1) {
7774 assert(src
.regClass() == bld
.lm
);
7775 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7776 if (ctx
->program
->chip_class
>= GFX8
)
7777 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7779 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7780 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7781 emit_wqm(ctx
, tmp
, dst
);
7782 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7784 if (ctx
->program
->chip_class
>= GFX8
)
7785 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7787 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7788 emit_wqm(ctx
, tmp
, dst
);
7789 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7790 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7791 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7792 if (ctx
->program
->chip_class
>= GFX8
) {
7793 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7794 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7796 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7797 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7799 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7800 emit_split_vector(ctx
, dst
, 2);
7802 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7803 nir_print_instr(&instr
->instr
, stderr
);
7804 fprintf(stderr
, "\n");
7808 case nir_intrinsic_masked_swizzle_amd
: {
7809 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7810 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7811 emit_uniform_subgroup(ctx
, instr
, src
);
7814 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7815 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7816 if (dst
.regClass() == v1
) {
7818 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7820 } else if (dst
.regClass() == v2
) {
7821 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7822 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7823 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7824 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7825 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7826 emit_split_vector(ctx
, dst
, 2);
7828 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7829 nir_print_instr(&instr
->instr
, stderr
);
7830 fprintf(stderr
, "\n");
7834 case nir_intrinsic_write_invocation_amd
: {
7835 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7836 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7837 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7838 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7839 if (dst
.regClass() == v1
) {
7840 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7841 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7842 } else if (dst
.regClass() == v2
) {
7843 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7844 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7845 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7846 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7847 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7848 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7849 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7850 emit_split_vector(ctx
, dst
, 2);
7852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7853 nir_print_instr(&instr
->instr
, stderr
);
7854 fprintf(stderr
, "\n");
7858 case nir_intrinsic_mbcnt_amd
: {
7859 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7860 RegClass rc
= RegClass(src
.type(), 1);
7861 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7863 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7864 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7865 emit_wqm(ctx
, wqm_tmp
, dst
);
7868 case nir_intrinsic_load_helper_invocation
: {
7869 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7870 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7871 ctx
->block
->kind
|= block_kind_needs_lowering
;
7872 ctx
->program
->needs_exact
= true;
7875 case nir_intrinsic_is_helper_invocation
: {
7876 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7877 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7878 ctx
->block
->kind
|= block_kind_needs_lowering
;
7879 ctx
->program
->needs_exact
= true;
7882 case nir_intrinsic_demote
:
7883 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7885 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7886 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7887 ctx
->block
->kind
|= block_kind_uses_demote
;
7888 ctx
->program
->needs_exact
= true;
7890 case nir_intrinsic_demote_if
: {
7891 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7892 assert(src
.regClass() == bld
.lm
);
7893 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7894 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7896 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7897 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7898 ctx
->block
->kind
|= block_kind_uses_demote
;
7899 ctx
->program
->needs_exact
= true;
7902 case nir_intrinsic_first_invocation
: {
7903 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7904 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7907 case nir_intrinsic_shader_clock
:
7908 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7909 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7911 case nir_intrinsic_load_vertex_id_zero_base
: {
7912 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7913 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7916 case nir_intrinsic_load_first_vertex
: {
7917 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7918 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7921 case nir_intrinsic_load_base_instance
: {
7922 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7923 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7926 case nir_intrinsic_load_instance_id
: {
7927 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7928 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7931 case nir_intrinsic_load_draw_id
: {
7932 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7933 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7936 case nir_intrinsic_load_invocation_id
: {
7937 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7939 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7940 if (ctx
->options
->chip_class
>= GFX10
)
7941 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7943 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7944 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7945 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7946 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7948 unreachable("Unsupported stage for load_invocation_id");
7953 case nir_intrinsic_load_primitive_id
: {
7954 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7956 switch (ctx
->shader
->info
.stage
) {
7957 case MESA_SHADER_GEOMETRY
:
7958 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7960 case MESA_SHADER_TESS_CTRL
:
7961 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7963 case MESA_SHADER_TESS_EVAL
:
7964 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7967 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7972 case nir_intrinsic_load_patch_vertices_in
: {
7973 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7974 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7977 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7980 case nir_intrinsic_emit_vertex_with_counter
: {
7981 visit_emit_vertex_with_counter(ctx
, instr
);
7984 case nir_intrinsic_end_primitive_with_counter
: {
7985 unsigned stream
= nir_intrinsic_stream_id(instr
);
7986 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7989 case nir_intrinsic_set_vertex_count
: {
7990 /* unused, the HW keeps track of this for us */
7994 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7995 nir_print_instr(&instr
->instr
, stderr
);
7996 fprintf(stderr
, "\n");
8004 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8005 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8006 enum glsl_base_type
*stype
)
8008 nir_deref_instr
*texture_deref_instr
= NULL
;
8009 nir_deref_instr
*sampler_deref_instr
= NULL
;
8012 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8013 switch (instr
->src
[i
].src_type
) {
8014 case nir_tex_src_texture_deref
:
8015 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8017 case nir_tex_src_sampler_deref
:
8018 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8020 case nir_tex_src_plane
:
8021 plane
= nir_src_as_int(instr
->src
[i
].src
);
8028 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8030 if (!sampler_deref_instr
)
8031 sampler_deref_instr
= texture_deref_instr
;
8034 assert(instr
->op
!= nir_texop_txf_ms
&&
8035 instr
->op
!= nir_texop_samples_identical
);
8036 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8037 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8038 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8039 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8040 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8041 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8043 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8046 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8048 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8049 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8050 Builder
bld(ctx
->program
, ctx
->block
);
8052 /* to avoid unnecessary moves, we split and recombine sampler and image */
8053 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8054 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8055 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8056 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8057 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8058 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8059 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8060 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8062 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8063 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8064 img
[0], img
[1], img
[2], img
[3],
8065 img
[4], img
[5], img
[6], img
[7]);
8066 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8067 samp
[0], samp
[1], samp
[2], samp
[3]);
8070 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8071 instr
->op
== nir_texop_samples_identical
))
8072 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8075 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8076 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8078 Builder
bld(ctx
->program
, ctx
->block
);
8080 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8081 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8082 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8084 Operand
neg_one(0xbf800000u
);
8085 Operand
one(0x3f800000u
);
8086 Operand
two(0x40000000u
);
8087 Operand
four(0x40800000u
);
8089 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8090 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8091 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8093 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8094 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8095 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8096 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8099 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8100 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8101 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8103 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8106 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8107 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8108 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8111 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8112 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8114 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8115 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8118 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8120 Builder
bld(ctx
->program
, ctx
->block
);
8121 Temp ma
, tc
, sc
, id
;
8124 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8126 // see comment in ac_prepare_cube_coords()
8127 if (ctx
->options
->chip_class
<= GFX8
)
8128 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8131 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8133 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8134 vop3a
->operands
[0] = Operand(ma
);
8135 vop3a
->abs
[0] = true;
8136 Temp invma
= bld
.tmp(v1
);
8137 vop3a
->definitions
[0] = Definition(invma
);
8138 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8140 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8142 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8144 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8146 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8148 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8151 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8152 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8154 for (unsigned i
= 0; i
< 2; i
++) {
8155 // see comment in ac_prepare_cube_coords()
8157 Temp deriv_sc
, deriv_tc
;
8158 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8159 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8161 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8163 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8164 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8165 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8166 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8167 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8168 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8169 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8172 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8173 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8177 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8184 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8186 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8188 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8189 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8192 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8193 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8194 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8198 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8200 Builder
bld(ctx
->program
, ctx
->block
);
8201 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8202 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8203 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8204 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8205 std::vector
<Temp
> coords
;
8206 std::vector
<Temp
> derivs
;
8207 nir_const_value
*sample_index_cv
= NULL
;
8208 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8209 enum glsl_base_type stype
;
8210 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8212 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8213 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8214 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8215 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8217 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8218 switch (instr
->src
[i
].src_type
) {
8219 case nir_tex_src_coord
: {
8220 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8221 for (unsigned i
= 0; i
< coord
.size(); i
++)
8222 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8225 case nir_tex_src_bias
:
8226 if (instr
->op
== nir_texop_txb
) {
8227 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8231 case nir_tex_src_lod
: {
8232 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8234 if (val
&& val
->f32
<= 0.0) {
8237 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8242 case nir_tex_src_comparator
:
8243 if (instr
->is_shadow
) {
8244 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8248 case nir_tex_src_offset
:
8249 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8250 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8253 case nir_tex_src_ddx
:
8254 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8257 case nir_tex_src_ddy
:
8258 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8261 case nir_tex_src_ms_index
:
8262 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8263 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8264 has_sample_index
= true;
8266 case nir_tex_src_texture_offset
:
8267 case nir_tex_src_sampler_offset
:
8273 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8274 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8276 if (instr
->op
== nir_texop_texture_samples
) {
8277 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8279 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8280 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8281 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8282 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8284 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8285 samples
, Operand(1u), bld
.scc(is_msaa
));
8289 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8290 aco_ptr
<Instruction
> tmp_instr
;
8291 Temp acc
, pack
= Temp();
8293 uint32_t pack_const
= 0;
8294 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8295 if (!const_offset
[i
])
8297 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8300 if (offset
.type() == RegType::sgpr
) {
8301 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8302 if (const_offset
[i
])
8305 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8306 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8309 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8312 if (pack
== Temp()) {
8315 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8319 if (pack_const
&& pack
!= Temp())
8320 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8322 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8323 if (const_offset
[i
])
8326 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8327 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8330 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8333 if (pack
== Temp()) {
8336 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8340 if (pack_const
&& pack
!= Temp())
8341 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8343 if (pack_const
&& pack
== Temp())
8344 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8345 else if (pack
== Temp())
8351 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8352 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8354 /* pack derivatives */
8355 if (has_ddx
|| has_ddy
) {
8356 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8357 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8358 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8359 derivs
= {ddy
, zero
, ddy
, zero
};
8361 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8362 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8363 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8364 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8369 if (instr
->coord_components
> 1 &&
8370 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8372 instr
->op
!= nir_texop_txf
)
8373 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8375 if (instr
->coord_components
> 2 &&
8376 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8377 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8378 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8379 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8381 instr
->op
!= nir_texop_txf
&&
8382 instr
->op
!= nir_texop_txf_ms
&&
8383 instr
->op
!= nir_texop_fragment_fetch
&&
8384 instr
->op
!= nir_texop_fragment_mask_fetch
)
8385 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8387 if (ctx
->options
->chip_class
== GFX9
&&
8388 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8389 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8390 assert(coords
.size() > 0 && coords
.size() < 3);
8392 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8393 Operand((uint32_t) 0) :
8394 Operand((uint32_t) 0x3f000000)));
8397 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8399 if (instr
->op
== nir_texop_samples_identical
)
8400 resource
= fmask_ptr
;
8402 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8403 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8404 instr
->op
!= nir_texop_txs
&&
8405 instr
->op
!= nir_texop_fragment_fetch
&&
8406 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8407 assert(has_sample_index
);
8408 Operand
op(sample_index
);
8409 if (sample_index_cv
)
8410 op
= Operand(sample_index_cv
->u32
);
8411 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8414 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8415 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8416 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8417 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8422 /* Build tex instruction */
8423 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8424 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8425 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8427 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8430 /* gather4 selects the component by dmask and always returns vec4 */
8431 if (instr
->op
== nir_texop_tg4
) {
8432 assert(instr
->dest
.ssa
.num_components
== 4);
8433 if (instr
->is_shadow
)
8436 dmask
= 1 << instr
->component
;
8437 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8438 tmp_dst
= bld
.tmp(v4
);
8439 } else if (instr
->op
== nir_texop_samples_identical
) {
8440 tmp_dst
= bld
.tmp(v1
);
8441 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8442 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8445 aco_ptr
<MIMG_instruction
> tex
;
8446 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8448 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8450 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8451 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8454 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8455 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8457 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8458 tex
->operands
[0] = Operand(resource
);
8459 tex
->operands
[1] = Operand(s4
); /* no sampler */
8460 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8461 if (ctx
->options
->chip_class
== GFX9
&&
8462 instr
->op
== nir_texop_txs
&&
8463 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8465 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8466 } else if (instr
->op
== nir_texop_query_levels
) {
8467 tex
->dmask
= 1 << 3;
8472 tex
->definitions
[0] = Definition(tmp_dst
);
8474 tex
->can_reorder
= true;
8475 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8478 /* divide 3rd value by 6 by multiplying with magic number */
8479 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8480 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8481 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8482 assert(instr
->dest
.ssa
.num_components
== 3);
8483 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8484 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8485 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8486 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8491 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8495 Temp tg4_compare_cube_wa64
= Temp();
8497 if (tg4_integer_workarounds
) {
8498 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8499 tex
->operands
[0] = Operand(resource
);
8500 tex
->operands
[1] = Operand(s4
); /* no sampler */
8501 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8505 Temp size
= bld
.tmp(v2
);
8506 tex
->definitions
[0] = Definition(size
);
8507 tex
->can_reorder
= true;
8508 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8509 emit_split_vector(ctx
, size
, size
.size());
8512 for (unsigned i
= 0; i
< 2; i
++) {
8513 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8514 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8515 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8516 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8519 Temp new_coords
[2] = {
8520 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8521 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8524 if (tg4_integer_cube_workaround
) {
8525 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8526 Temp desc
[resource
.size()];
8527 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8528 Format::PSEUDO
, 1, resource
.size())};
8529 split
->operands
[0] = Operand(resource
);
8530 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8531 desc
[i
] = bld
.tmp(s1
);
8532 split
->definitions
[i
] = Definition(desc
[i
]);
8534 ctx
->block
->instructions
.emplace_back(std::move(split
));
8536 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8537 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8538 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8541 if (stype
== GLSL_TYPE_UINT
) {
8542 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8543 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8544 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8545 bld
.scc(compare_cube_wa
));
8547 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8548 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8549 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8550 bld
.scc(compare_cube_wa
));
8552 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8553 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8555 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8557 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8558 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8559 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8561 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8562 Format::PSEUDO
, resource
.size(), 1)};
8563 for (unsigned i
= 0; i
< resource
.size(); i
++)
8564 vec
->operands
[i
] = Operand(desc
[i
]);
8565 resource
= bld
.tmp(resource
.regClass());
8566 vec
->definitions
[0] = Definition(resource
);
8567 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8569 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8570 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8571 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8572 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8574 coords
[0] = new_coords
[0];
8575 coords
[1] = new_coords
[1];
8578 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8579 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8581 assert(coords
.size() == 1);
8582 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8586 op
= aco_opcode::buffer_load_format_x
; break;
8588 op
= aco_opcode::buffer_load_format_xy
; break;
8590 op
= aco_opcode::buffer_load_format_xyz
; break;
8592 op
= aco_opcode::buffer_load_format_xyzw
; break;
8594 unreachable("Tex instruction loads more than 4 components.");
8597 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8598 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8601 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8603 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8604 mubuf
->operands
[0] = Operand(resource
);
8605 mubuf
->operands
[1] = Operand(coords
[0]);
8606 mubuf
->operands
[2] = Operand((uint32_t) 0);
8607 mubuf
->definitions
[0] = Definition(tmp_dst
);
8608 mubuf
->idxen
= true;
8609 mubuf
->can_reorder
= true;
8610 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8612 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8616 /* gather MIMG address components */
8617 std::vector
<Temp
> args
;
8619 args
.emplace_back(offset
);
8621 args
.emplace_back(bias
);
8623 args
.emplace_back(compare
);
8625 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8627 args
.insert(args
.end(), coords
.begin(), coords
.end());
8628 if (has_sample_index
)
8629 args
.emplace_back(sample_index
);
8631 args
.emplace_back(lod
);
8633 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8634 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8635 vec
->definitions
[0] = Definition(arg
);
8636 for (unsigned i
= 0; i
< args
.size(); i
++)
8637 vec
->operands
[i
] = Operand(args
[i
]);
8638 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8641 if (instr
->op
== nir_texop_txf
||
8642 instr
->op
== nir_texop_txf_ms
||
8643 instr
->op
== nir_texop_samples_identical
||
8644 instr
->op
== nir_texop_fragment_fetch
||
8645 instr
->op
== nir_texop_fragment_mask_fetch
) {
8646 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8647 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8648 tex
->operands
[0] = Operand(resource
);
8649 tex
->operands
[1] = Operand(s4
); /* no sampler */
8650 tex
->operands
[2] = Operand(arg
);
8655 tex
->definitions
[0] = Definition(tmp_dst
);
8656 tex
->can_reorder
= true;
8657 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8659 if (instr
->op
== nir_texop_samples_identical
) {
8660 assert(dmask
== 1 && dst
.regClass() == v1
);
8661 assert(dst
.id() != tmp_dst
.id());
8663 Temp tmp
= bld
.tmp(bld
.lm
);
8664 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8665 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8668 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8673 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8674 aco_opcode opcode
= aco_opcode::image_sample
;
8675 if (has_offset
) { /* image_sample_*_o */
8677 opcode
= aco_opcode::image_sample_c_o
;
8679 opcode
= aco_opcode::image_sample_c_d_o
;
8681 opcode
= aco_opcode::image_sample_c_b_o
;
8683 opcode
= aco_opcode::image_sample_c_lz_o
;
8685 opcode
= aco_opcode::image_sample_c_l_o
;
8687 opcode
= aco_opcode::image_sample_o
;
8689 opcode
= aco_opcode::image_sample_d_o
;
8691 opcode
= aco_opcode::image_sample_b_o
;
8693 opcode
= aco_opcode::image_sample_lz_o
;
8695 opcode
= aco_opcode::image_sample_l_o
;
8697 } else { /* no offset */
8699 opcode
= aco_opcode::image_sample_c
;
8701 opcode
= aco_opcode::image_sample_c_d
;
8703 opcode
= aco_opcode::image_sample_c_b
;
8705 opcode
= aco_opcode::image_sample_c_lz
;
8707 opcode
= aco_opcode::image_sample_c_l
;
8709 opcode
= aco_opcode::image_sample
;
8711 opcode
= aco_opcode::image_sample_d
;
8713 opcode
= aco_opcode::image_sample_b
;
8715 opcode
= aco_opcode::image_sample_lz
;
8717 opcode
= aco_opcode::image_sample_l
;
8721 if (instr
->op
== nir_texop_tg4
) {
8723 opcode
= aco_opcode::image_gather4_lz_o
;
8725 opcode
= aco_opcode::image_gather4_c_lz_o
;
8727 opcode
= aco_opcode::image_gather4_lz
;
8729 opcode
= aco_opcode::image_gather4_c_lz
;
8731 } else if (instr
->op
== nir_texop_lod
) {
8732 opcode
= aco_opcode::image_get_lod
;
8735 /* we don't need the bias, sample index, compare value or offset to be
8736 * computed in WQM but if the p_create_vector copies the coordinates, then it
8737 * needs to be in WQM */
8738 if (ctx
->stage
== fragment_fs
&&
8739 !has_derivs
&& !has_lod
&& !level_zero
&&
8740 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8741 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8742 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8744 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8745 tex
->operands
[0] = Operand(resource
);
8746 tex
->operands
[1] = Operand(sampler
);
8747 tex
->operands
[2] = Operand(arg
);
8751 tex
->definitions
[0] = Definition(tmp_dst
);
8752 tex
->can_reorder
= true;
8753 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8755 if (tg4_integer_cube_workaround
) {
8756 assert(tmp_dst
.id() != dst
.id());
8757 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8759 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8761 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8762 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8764 if (stype
== GLSL_TYPE_UINT
)
8765 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8767 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8768 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8770 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8771 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8772 val
[0], val
[1], val
[2], val
[3]);
8774 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8775 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8780 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8782 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8783 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8784 return Operand(tmp
.regClass());
8786 return Operand(tmp
);
8789 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8791 aco_ptr
<Pseudo_instruction
> phi
;
8792 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8793 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8795 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8796 logical
|= ctx
->block
->kind
& block_kind_merge
;
8797 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8799 /* we want a sorted list of sources, since the predecessor list is also sorted */
8800 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8801 nir_foreach_phi_src(src
, instr
)
8802 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8804 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8805 unsigned num_operands
= 0;
8806 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8807 unsigned num_defined
= 0;
8808 unsigned cur_pred_idx
= 0;
8809 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8810 if (cur_pred_idx
< preds
.size()) {
8811 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8812 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8813 unsigned skipped
= 0;
8814 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8816 if (cur_pred_idx
+ skipped
< preds
.size()) {
8817 for (unsigned i
= 0; i
< skipped
; i
++)
8818 operands
[num_operands
++] = Operand(dst
.regClass());
8819 cur_pred_idx
+= skipped
;
8824 /* Handle missing predecessors at the end. This shouldn't happen with loop
8825 * headers and we can't ignore these sources for loop header phis. */
8826 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8829 Operand op
= get_phi_operand(ctx
, src
.second
);
8830 operands
[num_operands
++] = op
;
8831 num_defined
+= !op
.isUndefined();
8833 /* handle block_kind_continue_or_break at loop exit blocks */
8834 while (cur_pred_idx
++ < preds
.size())
8835 operands
[num_operands
++] = Operand(dst
.regClass());
8837 /* If the loop ends with a break, still add a linear continue edge in case
8838 * that break is divergent or continue_or_break is used. We'll either remove
8839 * this operand later in visit_loop() if it's not necessary or replace the
8840 * undef with something correct. */
8841 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8842 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8843 nir_block
*last
= nir_loop_last_block(loop
);
8844 if (last
->successors
[0] != instr
->instr
.block
)
8845 operands
[num_operands
++] = Operand(RegClass());
8848 if (num_defined
== 0) {
8849 Builder
bld(ctx
->program
, ctx
->block
);
8850 if (dst
.regClass() == s1
) {
8851 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8852 } else if (dst
.regClass() == v1
) {
8853 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8855 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8856 for (unsigned i
= 0; i
< dst
.size(); i
++)
8857 vec
->operands
[i
] = Operand(0u);
8858 vec
->definitions
[0] = Definition(dst
);
8859 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8864 /* we can use a linear phi in some cases if one src is undef */
8865 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8866 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8868 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8869 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8870 assert(invert
->kind
& block_kind_invert
);
8872 unsigned then_block
= invert
->linear_preds
[0];
8874 Block
* insert_block
= NULL
;
8875 for (unsigned i
= 0; i
< num_operands
; i
++) {
8876 Operand op
= operands
[i
];
8877 if (op
.isUndefined())
8879 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8880 phi
->operands
[0] = op
;
8883 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8884 phi
->operands
[1] = Operand(dst
.regClass());
8885 phi
->definitions
[0] = Definition(dst
);
8886 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8890 /* try to scalarize vector phis */
8891 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8892 // TODO: scalarize linear phis on divergent ifs
8893 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8894 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8895 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8896 Operand src
= operands
[i
];
8897 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8898 can_scalarize
= false;
8900 if (can_scalarize
) {
8901 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8902 assert(dst
.size() % num_components
== 0);
8903 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8905 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8906 for (unsigned k
= 0; k
< num_components
; k
++) {
8907 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8908 for (unsigned i
= 0; i
< num_operands
; i
++) {
8909 Operand src
= operands
[i
];
8910 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8912 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8913 phi
->definitions
[0] = Definition(phi_dst
);
8914 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8915 new_vec
[k
] = phi_dst
;
8916 vec
->operands
[k
] = Operand(phi_dst
);
8918 vec
->definitions
[0] = Definition(dst
);
8919 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8920 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8925 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8926 for (unsigned i
= 0; i
< num_operands
; i
++)
8927 phi
->operands
[i
] = operands
[i
];
8928 phi
->definitions
[0] = Definition(dst
);
8929 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8933 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8935 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8937 assert(dst
.type() == RegType::sgpr
);
8939 if (dst
.size() == 1) {
8940 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8942 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8943 for (unsigned i
= 0; i
< dst
.size(); i
++)
8944 vec
->operands
[i
] = Operand(0u);
8945 vec
->definitions
[0] = Definition(dst
);
8946 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8950 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8952 Builder
bld(ctx
->program
, ctx
->block
);
8953 Block
*logical_target
;
8954 append_logical_end(ctx
->block
);
8955 unsigned idx
= ctx
->block
->index
;
8957 switch (instr
->type
) {
8958 case nir_jump_break
:
8959 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8960 add_logical_edge(idx
, logical_target
);
8961 ctx
->block
->kind
|= block_kind_break
;
8963 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8964 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8965 /* uniform break - directly jump out of the loop */
8966 ctx
->block
->kind
|= block_kind_uniform
;
8967 ctx
->cf_info
.has_branch
= true;
8968 bld
.branch(aco_opcode::p_branch
);
8969 add_linear_edge(idx
, logical_target
);
8972 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8973 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8975 case nir_jump_continue
:
8976 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8977 add_logical_edge(idx
, logical_target
);
8978 ctx
->block
->kind
|= block_kind_continue
;
8980 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8981 /* for potential uniform breaks after this continue,
8982 we must ensure that they are handled correctly */
8983 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8984 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8985 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8987 /* uniform continue - directly jump to the loop header */
8988 ctx
->block
->kind
|= block_kind_uniform
;
8989 ctx
->cf_info
.has_branch
= true;
8990 bld
.branch(aco_opcode::p_branch
);
8991 add_linear_edge(idx
, logical_target
);
8996 fprintf(stderr
, "Unknown NIR jump instr: ");
8997 nir_print_instr(&instr
->instr
, stderr
);
8998 fprintf(stderr
, "\n");
9002 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9003 ctx
->cf_info
.exec_potentially_empty_break
= true;
9004 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9007 /* remove critical edges from linear CFG */
9008 bld
.branch(aco_opcode::p_branch
);
9009 Block
* break_block
= ctx
->program
->create_and_insert_block();
9010 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9011 break_block
->kind
|= block_kind_uniform
;
9012 add_linear_edge(idx
, break_block
);
9013 /* the loop_header pointer might be invalidated by this point */
9014 if (instr
->type
== nir_jump_continue
)
9015 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9016 add_linear_edge(break_block
->index
, logical_target
);
9017 bld
.reset(break_block
);
9018 bld
.branch(aco_opcode::p_branch
);
9020 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9021 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9022 add_linear_edge(idx
, continue_block
);
9023 append_logical_start(continue_block
);
9024 ctx
->block
= continue_block
;
9028 void visit_block(isel_context
*ctx
, nir_block
*block
)
9030 nir_foreach_instr(instr
, block
) {
9031 switch (instr
->type
) {
9032 case nir_instr_type_alu
:
9033 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9035 case nir_instr_type_load_const
:
9036 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9038 case nir_instr_type_intrinsic
:
9039 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9041 case nir_instr_type_tex
:
9042 visit_tex(ctx
, nir_instr_as_tex(instr
));
9044 case nir_instr_type_phi
:
9045 visit_phi(ctx
, nir_instr_as_phi(instr
));
9047 case nir_instr_type_ssa_undef
:
9048 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9050 case nir_instr_type_deref
:
9052 case nir_instr_type_jump
:
9053 visit_jump(ctx
, nir_instr_as_jump(instr
));
9056 fprintf(stderr
, "Unknown NIR instr type: ");
9057 nir_print_instr(instr
, stderr
);
9058 fprintf(stderr
, "\n");
9063 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9064 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9069 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9070 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9072 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9073 RegClass rc
= vals
[0].regClass();
9075 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9077 unsigned next_pred
= 1;
9079 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9080 Block
& block
= ctx
->program
->blocks
[idx
];
9081 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9082 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9086 if (block
.kind
& block_kind_continue
) {
9087 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9092 bool all_same
= true;
9093 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9094 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9098 val
= vals
[block
.linear_preds
[0] - first
];
9100 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9101 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9102 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9103 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9104 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9105 phi
->definitions
[0] = Definition(val
.getTemp());
9106 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9108 vals
[idx
- first
] = val
;
9111 return vals
[last
- first
];
9114 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9116 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9117 append_logical_end(ctx
->block
);
9118 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9119 Builder
bld(ctx
->program
, ctx
->block
);
9120 bld
.branch(aco_opcode::p_branch
);
9121 unsigned loop_preheader_idx
= ctx
->block
->index
;
9123 Block loop_exit
= Block();
9124 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9125 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9127 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9128 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9129 loop_header
->kind
|= block_kind_loop_header
;
9130 add_edge(loop_preheader_idx
, loop_header
);
9131 ctx
->block
= loop_header
;
9133 /* emit loop body */
9134 unsigned loop_header_idx
= loop_header
->index
;
9135 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9136 append_logical_start(ctx
->block
);
9137 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9139 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9140 if (!ctx
->cf_info
.has_branch
) {
9141 append_logical_end(ctx
->block
);
9142 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9143 /* Discards can result in code running with an empty exec mask.
9144 * This would result in divergent breaks not ever being taken. As a
9145 * workaround, break the loop when the loop mask is empty instead of
9146 * always continuing. */
9147 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9148 unsigned block_idx
= ctx
->block
->index
;
9150 /* create helper blocks to avoid critical edges */
9151 Block
*break_block
= ctx
->program
->create_and_insert_block();
9152 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9153 break_block
->kind
= block_kind_uniform
;
9154 bld
.reset(break_block
);
9155 bld
.branch(aco_opcode::p_branch
);
9156 add_linear_edge(block_idx
, break_block
);
9157 add_linear_edge(break_block
->index
, &loop_exit
);
9159 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9160 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9161 continue_block
->kind
= block_kind_uniform
;
9162 bld
.reset(continue_block
);
9163 bld
.branch(aco_opcode::p_branch
);
9164 add_linear_edge(block_idx
, continue_block
);
9165 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9167 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9168 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9169 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9171 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9172 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9173 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9175 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9178 bld
.reset(ctx
->block
);
9179 bld
.branch(aco_opcode::p_branch
);
9182 /* Fixup phis in loop header from unreachable blocks.
9183 * has_branch/has_divergent_branch also indicates if the loop ends with a
9184 * break/continue instruction, but we don't emit those if unreachable=true */
9186 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9187 bool linear
= ctx
->cf_info
.has_branch
;
9188 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9189 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9190 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9191 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9192 /* the last operand should be the one that needs to be removed */
9193 instr
->operands
.pop_back();
9194 } else if (!is_phi(instr
)) {
9200 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9201 * and the previous one shouldn't both happen at once because a break in the
9202 * merge block would get CSE'd */
9203 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9204 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9205 Operand vals
[num_vals
];
9206 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9207 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9208 if (ctx
->cf_info
.has_branch
)
9209 instr
->operands
.pop_back();
9211 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9212 } else if (!is_phi(instr
)) {
9218 ctx
->cf_info
.has_branch
= false;
9220 // TODO: if the loop has not a single exit, we must add one °°
9221 /* emit loop successor block */
9222 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9223 append_logical_start(ctx
->block
);
9226 // TODO: check if it is beneficial to not branch on continues
9227 /* trim linear phis in loop header */
9228 for (auto&& instr
: loop_entry
->instructions
) {
9229 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9230 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9231 new_phi
->definitions
[0] = instr
->definitions
[0];
9232 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9233 new_phi
->operands
[i
] = instr
->operands
[i
];
9234 /* check that the remaining operands are all the same */
9235 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9236 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9237 instr
.swap(new_phi
);
9238 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9247 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9251 append_logical_end(ctx
->block
);
9252 ctx
->block
->kind
|= block_kind_branch
;
9254 /* branch to linear then block */
9255 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9256 aco_ptr
<Pseudo_branch_instruction
> branch
;
9257 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9258 branch
->operands
[0] = Operand(cond
);
9259 ctx
->block
->instructions
.push_back(std::move(branch
));
9261 ic
->BB_if_idx
= ctx
->block
->index
;
9262 ic
->BB_invert
= Block();
9263 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9264 /* Invert blocks are intentionally not marked as top level because they
9265 * are not part of the logical cfg. */
9266 ic
->BB_invert
.kind
|= block_kind_invert
;
9267 ic
->BB_endif
= Block();
9268 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9269 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9271 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9272 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9273 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9274 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9275 ctx
->cf_info
.parent_if
.is_divergent
= true;
9277 /* divergent branches use cbranch_execz */
9278 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9279 ctx
->cf_info
.exec_potentially_empty_break
= false;
9280 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9282 /** emit logical then block */
9283 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9284 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9285 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9286 ctx
->block
= BB_then_logical
;
9287 append_logical_start(BB_then_logical
);
9290 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9292 Block
*BB_then_logical
= ctx
->block
;
9293 append_logical_end(BB_then_logical
);
9294 /* branch from logical then block to invert block */
9295 aco_ptr
<Pseudo_branch_instruction
> branch
;
9296 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9297 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9298 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9299 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9300 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9301 BB_then_logical
->kind
|= block_kind_uniform
;
9302 assert(!ctx
->cf_info
.has_branch
);
9303 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9304 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9306 /** emit linear then block */
9307 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9308 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9309 BB_then_linear
->kind
|= block_kind_uniform
;
9310 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9311 /* branch from linear then block to invert block */
9312 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9313 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9314 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9316 /** emit invert merge block */
9317 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9318 ic
->invert_idx
= ctx
->block
->index
;
9320 /* branch to linear else block (skip else) */
9321 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9322 branch
->operands
[0] = Operand(ic
->cond
);
9323 ctx
->block
->instructions
.push_back(std::move(branch
));
9325 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9326 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9327 ic
->exec_potentially_empty_break_depth_old
=
9328 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9329 /* divergent branches use cbranch_execz */
9330 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9331 ctx
->cf_info
.exec_potentially_empty_break
= false;
9332 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9334 /** emit logical else block */
9335 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9336 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9337 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9338 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9339 ctx
->block
= BB_else_logical
;
9340 append_logical_start(BB_else_logical
);
9343 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9345 Block
*BB_else_logical
= ctx
->block
;
9346 append_logical_end(BB_else_logical
);
9348 /* branch from logical else block to endif block */
9349 aco_ptr
<Pseudo_branch_instruction
> branch
;
9350 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9351 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9352 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9353 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9354 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9355 BB_else_logical
->kind
|= block_kind_uniform
;
9357 assert(!ctx
->cf_info
.has_branch
);
9358 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9361 /** emit linear else block */
9362 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9363 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9364 BB_else_linear
->kind
|= block_kind_uniform
;
9365 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9367 /* branch from linear else block to endif block */
9368 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9369 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9370 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9373 /** emit endif merge block */
9374 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9375 append_logical_start(ctx
->block
);
9378 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9379 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9380 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9381 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9382 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9383 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9384 !ctx
->cf_info
.parent_if
.is_divergent
) {
9385 ctx
->cf_info
.exec_potentially_empty_break
= false;
9386 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9388 /* uniform control flow never has an empty exec-mask */
9389 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9390 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9391 ctx
->cf_info
.exec_potentially_empty_break
= false;
9392 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9396 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9398 assert(cond
.regClass() == s1
);
9400 append_logical_end(ctx
->block
);
9401 ctx
->block
->kind
|= block_kind_uniform
;
9403 aco_ptr
<Pseudo_branch_instruction
> branch
;
9404 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9405 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9406 branch
->operands
[0] = Operand(cond
);
9407 branch
->operands
[0].setFixed(scc
);
9408 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9410 ic
->BB_if_idx
= ctx
->block
->index
;
9411 ic
->BB_endif
= Block();
9412 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9413 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9415 ctx
->cf_info
.has_branch
= false;
9416 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9418 /** emit then block */
9419 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9420 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9421 add_edge(ic
->BB_if_idx
, BB_then
);
9422 append_logical_start(BB_then
);
9423 ctx
->block
= BB_then
;
9426 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9428 Block
*BB_then
= ctx
->block
;
9430 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9431 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9433 if (!ic
->uniform_has_then_branch
) {
9434 append_logical_end(BB_then
);
9435 /* branch from then block to endif block */
9436 aco_ptr
<Pseudo_branch_instruction
> branch
;
9437 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9438 BB_then
->instructions
.emplace_back(std::move(branch
));
9439 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9440 if (!ic
->then_branch_divergent
)
9441 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9442 BB_then
->kind
|= block_kind_uniform
;
9445 ctx
->cf_info
.has_branch
= false;
9446 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9448 /** emit else block */
9449 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9450 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9451 add_edge(ic
->BB_if_idx
, BB_else
);
9452 append_logical_start(BB_else
);
9453 ctx
->block
= BB_else
;
9456 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9458 Block
*BB_else
= ctx
->block
;
9460 if (!ctx
->cf_info
.has_branch
) {
9461 append_logical_end(BB_else
);
9462 /* branch from then block to endif block */
9463 aco_ptr
<Pseudo_branch_instruction
> branch
;
9464 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9465 BB_else
->instructions
.emplace_back(std::move(branch
));
9466 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9467 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9468 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9469 BB_else
->kind
|= block_kind_uniform
;
9472 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9473 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9475 /** emit endif merge block */
9476 if (!ctx
->cf_info
.has_branch
) {
9477 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9478 append_logical_start(ctx
->block
);
9482 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9484 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9485 Builder
bld(ctx
->program
, ctx
->block
);
9486 aco_ptr
<Pseudo_branch_instruction
> branch
;
9489 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9491 * Uniform conditionals are represented in the following way*) :
9493 * The linear and logical CFG:
9496 * BB_THEN (logical) BB_ELSE (logical)
9500 * *) Exceptions may be due to break and continue statements within loops
9501 * If a break/continue happens within uniform control flow, it branches
9502 * to the loop exit/entry block. Otherwise, it branches to the next
9506 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9507 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9508 cond
= bool_to_scalar_condition(ctx
, cond
);
9510 begin_uniform_if_then(ctx
, &ic
, cond
);
9511 visit_cf_list(ctx
, &if_stmt
->then_list
);
9513 begin_uniform_if_else(ctx
, &ic
);
9514 visit_cf_list(ctx
, &if_stmt
->else_list
);
9516 end_uniform_if(ctx
, &ic
);
9518 return !ctx
->cf_info
.has_branch
;
9519 } else { /* non-uniform condition */
9521 * To maintain a logical and linear CFG without critical edges,
9522 * non-uniform conditionals are represented in the following way*) :
9527 * BB_THEN (logical) BB_THEN (linear)
9529 * BB_INVERT (linear)
9531 * BB_ELSE (logical) BB_ELSE (linear)
9538 * BB_THEN (logical) BB_ELSE (logical)
9542 * *) Exceptions may be due to break and continue statements within loops
9545 begin_divergent_if_then(ctx
, &ic
, cond
);
9546 visit_cf_list(ctx
, &if_stmt
->then_list
);
9548 begin_divergent_if_else(ctx
, &ic
);
9549 visit_cf_list(ctx
, &if_stmt
->else_list
);
9551 end_divergent_if(ctx
, &ic
);
9557 static bool visit_cf_list(isel_context
*ctx
,
9558 struct exec_list
*list
)
9560 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9561 switch (node
->type
) {
9562 case nir_cf_node_block
:
9563 visit_block(ctx
, nir_cf_node_as_block(node
));
9565 case nir_cf_node_if
:
9566 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9569 case nir_cf_node_loop
:
9570 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9573 unreachable("unimplemented cf list type");
9579 static void create_null_export(isel_context
*ctx
)
9581 /* Some shader stages always need to have exports.
9582 * So when there is none, we need to add a null export.
9585 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9586 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9587 Builder
bld(ctx
->program
, ctx
->block
);
9588 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9589 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9592 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9594 assert(ctx
->stage
== vertex_vs
||
9595 ctx
->stage
== tess_eval_vs
||
9596 ctx
->stage
== gs_copy_vs
||
9597 ctx
->stage
== ngg_vertex_gs
||
9598 ctx
->stage
== ngg_tess_eval_gs
);
9600 int offset
= (ctx
->stage
& sw_tes
)
9601 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9602 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9603 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9604 if (!is_pos
&& !mask
)
9606 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9608 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9609 exp
->enabled_mask
= mask
;
9610 for (unsigned i
= 0; i
< 4; ++i
) {
9611 if (mask
& (1 << i
))
9612 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9614 exp
->operands
[i
] = Operand(v1
);
9616 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9617 * Setting valid_mask=1 prevents it and has no other effect.
9619 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9621 exp
->compressed
= false;
9623 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9625 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9626 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9631 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9633 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9634 exp
->enabled_mask
= 0;
9635 for (unsigned i
= 0; i
< 4; ++i
)
9636 exp
->operands
[i
] = Operand(v1
);
9637 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9638 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9639 exp
->enabled_mask
|= 0x1;
9641 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9642 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9643 exp
->enabled_mask
|= 0x4;
9645 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9646 if (ctx
->options
->chip_class
< GFX9
) {
9647 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9648 exp
->enabled_mask
|= 0x8;
9650 Builder
bld(ctx
->program
, ctx
->block
);
9652 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9653 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9654 if (exp
->operands
[2].isTemp())
9655 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9657 exp
->operands
[2] = Operand(out
);
9658 exp
->enabled_mask
|= 0x4;
9661 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9663 exp
->compressed
= false;
9664 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9665 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9668 static void create_export_phis(isel_context
*ctx
)
9670 /* Used when exports are needed, but the output temps are defined in a preceding block.
9671 * This function will set up phis in order to access the outputs in the next block.
9674 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9675 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9676 ctx
->block
->instructions
.pop_back();
9678 Builder
bld(ctx
->program
, ctx
->block
);
9680 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9681 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9682 for (unsigned i
= 0; i
< 4; ++i
) {
9683 if (!(mask
& (1 << i
)))
9686 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9687 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9688 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9692 bld
.insert(std::move(logical_start
));
9695 static void create_vs_exports(isel_context
*ctx
)
9697 assert(ctx
->stage
== vertex_vs
||
9698 ctx
->stage
== tess_eval_vs
||
9699 ctx
->stage
== gs_copy_vs
||
9700 ctx
->stage
== ngg_vertex_gs
||
9701 ctx
->stage
== ngg_tess_eval_gs
);
9703 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9704 ? &ctx
->program
->info
->tes
.outinfo
9705 : &ctx
->program
->info
->vs
.outinfo
;
9707 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9708 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9709 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9712 if (ctx
->options
->key
.has_multiview_view_index
) {
9713 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9714 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9717 /* the order these position exports are created is important */
9719 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9720 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9721 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9722 exported_pos
= true;
9724 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9725 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9726 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9727 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9729 if (ctx
->export_clip_dists
) {
9730 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9731 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9732 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9733 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9736 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9737 if (i
< VARYING_SLOT_VAR0
&&
9738 i
!= VARYING_SLOT_LAYER
&&
9739 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9742 export_vs_varying(ctx
, i
, false, NULL
);
9746 create_null_export(ctx
);
9749 static bool export_fs_mrt_z(isel_context
*ctx
)
9751 Builder
bld(ctx
->program
, ctx
->block
);
9752 unsigned enabled_channels
= 0;
9756 for (unsigned i
= 0; i
< 4; ++i
) {
9757 values
[i
] = Operand(v1
);
9760 /* Both stencil and sample mask only need 16-bits. */
9761 if (!ctx
->program
->info
->ps
.writes_z
&&
9762 (ctx
->program
->info
->ps
.writes_stencil
||
9763 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9764 compr
= true; /* COMPR flag */
9766 if (ctx
->program
->info
->ps
.writes_stencil
) {
9767 /* Stencil should be in X[23:16]. */
9768 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9769 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9770 enabled_channels
|= 0x3;
9773 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9774 /* SampleMask should be in Y[15:0]. */
9775 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9776 enabled_channels
|= 0xc;
9779 if (ctx
->program
->info
->ps
.writes_z
) {
9780 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9781 enabled_channels
|= 0x1;
9784 if (ctx
->program
->info
->ps
.writes_stencil
) {
9785 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9786 enabled_channels
|= 0x2;
9789 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9790 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9791 enabled_channels
|= 0x4;
9795 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9796 * writemask component.
9798 if (ctx
->options
->chip_class
== GFX6
&&
9799 ctx
->options
->family
!= CHIP_OLAND
&&
9800 ctx
->options
->family
!= CHIP_HAINAN
) {
9801 enabled_channels
|= 0x1;
9804 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9805 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9810 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9812 Builder
bld(ctx
->program
, ctx
->block
);
9813 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9816 for (unsigned i
= 0; i
< 4; ++i
) {
9817 if (write_mask
& (1 << i
)) {
9818 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9820 values
[i
] = Operand(v1
);
9824 unsigned target
, col_format
;
9825 unsigned enabled_channels
= 0;
9826 aco_opcode compr_op
= (aco_opcode
)0;
9828 slot
-= FRAG_RESULT_DATA0
;
9829 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9830 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9832 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9833 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9837 case V_028714_SPI_SHADER_ZERO
:
9838 enabled_channels
= 0; /* writemask */
9839 target
= V_008DFC_SQ_EXP_NULL
;
9842 case V_028714_SPI_SHADER_32_R
:
9843 enabled_channels
= 1;
9846 case V_028714_SPI_SHADER_32_GR
:
9847 enabled_channels
= 0x3;
9850 case V_028714_SPI_SHADER_32_AR
:
9851 if (ctx
->options
->chip_class
>= GFX10
) {
9852 /* Special case: on GFX10, the outputs are different for 32_AR */
9853 enabled_channels
= 0x3;
9854 values
[1] = values
[3];
9855 values
[3] = Operand(v1
);
9857 enabled_channels
= 0x9;
9861 case V_028714_SPI_SHADER_FP16_ABGR
:
9862 enabled_channels
= 0x5;
9863 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9866 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9867 enabled_channels
= 0x5;
9868 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9871 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9872 enabled_channels
= 0x5;
9873 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9876 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9877 enabled_channels
= 0x5;
9878 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9879 if (is_int8
|| is_int10
) {
9881 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9882 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9884 for (unsigned i
= 0; i
< 4; i
++) {
9885 if ((write_mask
>> i
) & 1) {
9886 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9887 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9895 case V_028714_SPI_SHADER_SINT16_ABGR
:
9896 enabled_channels
= 0x5;
9897 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9898 if (is_int8
|| is_int10
) {
9900 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9901 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9902 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9903 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9905 for (unsigned i
= 0; i
< 4; i
++) {
9906 if ((write_mask
>> i
) & 1) {
9907 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9908 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9910 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9911 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9918 case V_028714_SPI_SHADER_32_ABGR
:
9919 enabled_channels
= 0xF;
9926 if (target
== V_008DFC_SQ_EXP_NULL
)
9929 if ((bool) compr_op
) {
9930 for (int i
= 0; i
< 2; i
++) {
9931 /* check if at least one of the values to be compressed is enabled */
9932 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9934 enabled_channels
|= enabled
<< (i
*2);
9935 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9936 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9937 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9939 values
[i
] = Operand(v1
);
9942 values
[2] = Operand(v1
);
9943 values
[3] = Operand(v1
);
9945 for (int i
= 0; i
< 4; i
++)
9946 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9949 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9950 enabled_channels
, target
, (bool) compr_op
);
9954 static void create_fs_exports(isel_context
*ctx
)
9956 bool exported
= false;
9958 /* Export depth, stencil and sample mask. */
9959 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9960 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9961 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9962 exported
|= export_fs_mrt_z(ctx
);
9964 /* Export all color render targets. */
9965 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9966 if (ctx
->outputs
.mask
[i
])
9967 exported
|= export_fs_mrt_color(ctx
, i
);
9970 create_null_export(ctx
);
9973 static void write_tcs_tess_factors(isel_context
*ctx
)
9975 unsigned outer_comps
;
9976 unsigned inner_comps
;
9978 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9995 Builder
bld(ctx
->program
, ctx
->block
);
9997 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9998 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9999 bld
.sopp(aco_opcode::s_barrier
);
10001 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10002 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10004 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10005 if_context ic_invocation_id_is_zero
;
10006 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10007 bld
.reset(ctx
->block
);
10009 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10011 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10012 unsigned stride
= inner_comps
+ outer_comps
;
10013 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10017 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10019 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10021 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10022 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10023 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10025 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10026 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10028 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10029 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10030 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10031 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10034 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10035 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10036 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10037 unsigned tf_const_offset
= 0;
10039 if (ctx
->program
->chip_class
<= GFX8
) {
10040 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10041 if_context ic_rel_patch_id_is_zero
;
10042 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10043 bld
.reset(ctx
->block
);
10045 /* Store the dynamic HS control word. */
10046 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10047 bld
.mubuf(aco_opcode::buffer_store_dword
,
10048 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10049 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10050 /* disable_wqm */ false, /* glc */ true);
10051 tf_const_offset
+= 4;
10053 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10054 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10055 bld
.reset(ctx
->block
);
10058 assert(stride
== 2 || stride
== 4 || stride
== 6);
10059 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10060 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10062 /* Store to offchip for TES to read - only if TES reads them */
10063 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10064 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10065 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10067 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10068 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10070 if (likely(inner_comps
)) {
10071 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10072 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10076 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10077 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10080 static void emit_stream_output(isel_context
*ctx
,
10081 Temp
const *so_buffers
,
10082 Temp
const *so_write_offset
,
10083 const struct radv_stream_output
*output
)
10085 unsigned num_comps
= util_bitcount(output
->component_mask
);
10086 unsigned writemask
= (1 << num_comps
) - 1;
10087 unsigned loc
= output
->location
;
10088 unsigned buf
= output
->buffer
;
10090 assert(num_comps
&& num_comps
<= 4);
10091 if (!num_comps
|| num_comps
> 4)
10094 unsigned start
= ffs(output
->component_mask
) - 1;
10097 bool all_undef
= true;
10098 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10099 for (unsigned i
= 0; i
< num_comps
; i
++) {
10100 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10101 all_undef
= all_undef
&& !out
[i
].id();
10106 while (writemask
) {
10108 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10109 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10110 /* GFX6 doesn't support storing vec3, split it. */
10111 writemask
|= 1u << (start
+ 2);
10115 unsigned offset
= output
->offset
+ start
* 4;
10117 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10118 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10119 for (int i
= 0; i
< count
; ++i
)
10120 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10121 vec
->definitions
[0] = Definition(write_data
);
10122 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10127 opcode
= aco_opcode::buffer_store_dword
;
10130 opcode
= aco_opcode::buffer_store_dwordx2
;
10133 opcode
= aco_opcode::buffer_store_dwordx3
;
10136 opcode
= aco_opcode::buffer_store_dwordx4
;
10139 unreachable("Unsupported dword count.");
10142 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10143 store
->operands
[0] = Operand(so_buffers
[buf
]);
10144 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10145 store
->operands
[2] = Operand((uint32_t) 0);
10146 store
->operands
[3] = Operand(write_data
);
10147 if (offset
> 4095) {
10148 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10149 Builder
bld(ctx
->program
, ctx
->block
);
10150 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10152 store
->offset
= offset
;
10154 store
->offen
= true;
10156 store
->dlc
= false;
10158 store
->can_reorder
= true;
10159 ctx
->block
->instructions
.emplace_back(std::move(store
));
10163 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10165 Builder
bld(ctx
->program
, ctx
->block
);
10167 Temp so_buffers
[4];
10168 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10169 for (unsigned i
= 0; i
< 4; i
++) {
10170 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10174 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10175 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10178 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10179 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10181 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10183 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10186 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10188 bld
.reset(ctx
->block
);
10190 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10192 Temp so_write_offset
[4];
10194 for (unsigned i
= 0; i
< 4; i
++) {
10195 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10200 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10201 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10202 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10203 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10205 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10207 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10208 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10209 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10210 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10214 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10215 struct radv_stream_output
*output
=
10216 &ctx
->program
->info
->so
.outputs
[i
];
10217 if (stream
!= output
->stream
)
10220 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10223 begin_divergent_if_else(ctx
, &ic
);
10224 end_divergent_if(ctx
, &ic
);
10227 } /* end namespace */
10229 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10231 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10232 Builder
bld(ctx
->program
, ctx
->block
);
10233 constexpr unsigned hs_idx
= 1u;
10234 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10235 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10236 Operand((8u << 16) | (hs_idx
* 8u)));
10237 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10239 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10241 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10242 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10243 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10244 ls_has_nonzero_hs_threads
);
10245 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10246 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10247 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10248 ls_has_nonzero_hs_threads
);
10249 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10250 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10251 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10252 ls_has_nonzero_hs_threads
);
10254 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10255 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10256 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10259 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10261 /* Split all arguments except for the first (ring_offsets) and the last
10262 * (exec) so that the dead channels don't stay live throughout the program.
10264 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10265 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10266 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10267 startpgm
->definitions
[i
].regClass().size());
10272 void handle_bc_optimize(isel_context
*ctx
)
10274 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10275 Builder
bld(ctx
->program
, ctx
->block
);
10276 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10277 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10278 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10279 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10280 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10281 if (uses_center
&& uses_centroid
) {
10282 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10283 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10285 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10287 for (unsigned i
= 0; i
< 2; i
++) {
10288 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10289 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10290 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10291 persp_centroid
, persp_center
, sel
);
10293 ctx
->persp_centroid
= bld
.tmp(v2
);
10294 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10295 Operand(new_coord
[0]), Operand(new_coord
[1]));
10296 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10299 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10301 for (unsigned i
= 0; i
< 2; i
++) {
10302 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10303 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10304 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10305 linear_centroid
, linear_center
, sel
);
10307 ctx
->linear_centroid
= bld
.tmp(v2
);
10308 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10309 Operand(new_coord
[0]), Operand(new_coord
[1]));
10310 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10315 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10317 Program
*program
= ctx
->program
;
10319 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10321 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10322 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10323 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10324 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10325 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10327 program
->next_fp_mode
.must_flush_denorms32
=
10328 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10329 program
->next_fp_mode
.must_flush_denorms16_64
=
10330 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10331 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10333 program
->next_fp_mode
.care_about_round32
=
10334 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10336 program
->next_fp_mode
.care_about_round16_64
=
10337 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10338 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10340 /* default to preserving fp16 and fp64 denorms, since it's free */
10341 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10342 program
->next_fp_mode
.denorm16_64
= 0;
10344 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10346 /* preserving fp32 denorms is expensive, so only do it if asked */
10347 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10348 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10350 program
->next_fp_mode
.denorm32
= 0;
10352 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10353 program
->next_fp_mode
.round32
= fp_round_tz
;
10355 program
->next_fp_mode
.round32
= fp_round_ne
;
10357 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10358 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10360 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10362 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10365 void cleanup_cfg(Program
*program
)
10367 /* create linear_succs/logical_succs */
10368 for (Block
& BB
: program
->blocks
) {
10369 for (unsigned idx
: BB
.linear_preds
)
10370 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10371 for (unsigned idx
: BB
.logical_preds
)
10372 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10376 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10378 Builder
bld(ctx
->program
, ctx
->block
);
10380 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10381 Temp count
= i
== 0
10382 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10383 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10384 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10386 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10389 if (ctx
->program
->wave_size
== 64) {
10390 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10391 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10392 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10394 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10395 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10401 bool ngg_early_prim_export(isel_context
*ctx
)
10403 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10407 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10409 Builder
bld(ctx
->program
, ctx
->block
);
10411 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10412 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10414 /* Get the id of the current wave within the threadgroup (workgroup) */
10415 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10416 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10418 /* Execute the following code only on the first wave (wave id 0),
10419 * use the SCC def to tell if the wave id is zero or not.
10421 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10423 begin_uniform_if_then(ctx
, &ic
, cond
);
10424 begin_uniform_if_else(ctx
, &ic
);
10425 bld
.reset(ctx
->block
);
10427 /* Number of vertices output by VS/TES */
10428 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10429 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10430 /* Number of primitives output by VS/TES */
10431 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10432 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10434 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10435 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10436 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10438 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10439 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10441 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10442 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10444 end_uniform_if(ctx
, &ic
);
10447 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10449 Builder
bld(ctx
->program
, ctx
->block
);
10451 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10452 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10455 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10458 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10459 assert(vtxindex
[i
].id());
10462 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10466 /* The initial edge flag is always false in tess eval shaders. */
10467 if (ctx
->stage
== ngg_vertex_gs
) {
10468 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10469 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10473 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10478 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10480 Builder
bld(ctx
->program
, ctx
->block
);
10481 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10483 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10484 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10485 false /* compressed */, true/* done */, false /* valid mask */);
10488 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10490 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10491 * These must always come before VS exports.
10493 * It is recommended to do these as early as possible. They can be at the beginning when
10494 * there is no SW GS and the shader doesn't write edge flags.
10498 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10499 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10501 Builder
bld(ctx
->program
, ctx
->block
);
10502 constexpr unsigned max_vertices_per_primitive
= 3;
10503 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10505 if (ctx
->stage
== ngg_vertex_gs
) {
10506 /* TODO: optimize for points & lines */
10507 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10508 if (ctx
->shader
->info
.tess
.point_mode
)
10509 num_vertices_per_primitive
= 1;
10510 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10511 num_vertices_per_primitive
= 2;
10513 unreachable("Unsupported NGG shader stage");
10516 Temp vtxindex
[max_vertices_per_primitive
];
10517 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10518 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10519 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10520 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10521 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10522 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10523 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10524 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10526 /* Export primitive data to the index buffer. */
10527 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10529 /* Export primitive ID. */
10530 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10531 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10532 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10533 Temp provoking_vtx_index
= vtxindex
[0];
10534 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10536 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10539 begin_divergent_if_else(ctx
, &ic
);
10540 end_divergent_if(ctx
, &ic
);
10543 void ngg_emit_nogs_output(isel_context
*ctx
)
10545 /* Emits NGG GS output, for stages that don't have SW GS. */
10548 Builder
bld(ctx
->program
, ctx
->block
);
10549 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10551 /* NGG streamout is currently disabled by default. */
10552 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10554 if (late_prim_export
) {
10555 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10556 create_export_phis(ctx
);
10557 /* Do what we need to do in the GS threads. */
10558 ngg_emit_nogs_gsthreads(ctx
);
10560 /* What comes next should be executed on ES threads. */
10561 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10562 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10563 bld
.reset(ctx
->block
);
10566 /* Export VS outputs */
10567 ctx
->block
->kind
|= block_kind_export_end
;
10568 create_vs_exports(ctx
);
10570 /* Export primitive ID */
10571 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10574 if (ctx
->stage
== ngg_vertex_gs
) {
10575 /* Wait for GS threads to store primitive ID in LDS. */
10576 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10577 bld
.sopp(aco_opcode::s_barrier
);
10579 /* Calculate LDS address where the GS threads stored the primitive ID. */
10580 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10581 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10582 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10583 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10584 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10585 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10587 /* Load primitive ID from LDS. */
10588 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10589 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10590 /* TES: Just use the patch ID as the primitive ID. */
10591 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10593 unreachable("unsupported NGG shader stage.");
10596 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10597 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10599 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10602 if (late_prim_export
) {
10603 begin_divergent_if_else(ctx
, &ic
);
10604 end_divergent_if(ctx
, &ic
);
10605 bld
.reset(ctx
->block
);
10609 void select_program(Program
*program
,
10610 unsigned shader_count
,
10611 struct nir_shader
*const *shaders
,
10612 ac_shader_config
* config
,
10613 struct radv_shader_args
*args
)
10615 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10616 if_context ic_merged_wave_info
;
10617 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10619 for (unsigned i
= 0; i
< shader_count
; i
++) {
10620 nir_shader
*nir
= shaders
[i
];
10621 init_context(&ctx
, nir
);
10623 setup_fp_mode(&ctx
, nir
);
10626 /* needs to be after init_context() for FS */
10627 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10628 append_logical_start(ctx
.block
);
10630 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10631 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10633 split_arguments(&ctx
, startpgm
);
10637 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10639 if (ngg_early_prim_export(&ctx
))
10640 ngg_emit_nogs_gsthreads(&ctx
);
10643 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10644 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10645 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10646 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10647 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10648 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10649 ctx
.stage
== tess_eval_geometry_gs
));
10651 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10652 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10653 if (check_merged_wave_info
) {
10654 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10655 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10659 Builder
bld(ctx
.program
, ctx
.block
);
10661 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10662 bld
.sopp(aco_opcode::s_barrier
);
10664 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10665 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10667 } else if (ctx
.stage
== geometry_gs
)
10668 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10670 if (ctx
.stage
== fragment_fs
)
10671 handle_bc_optimize(&ctx
);
10673 visit_cf_list(&ctx
, &func
->body
);
10675 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10676 emit_streamout(&ctx
, 0);
10678 if (ctx
.stage
& hw_vs
) {
10679 create_vs_exports(&ctx
);
10680 ctx
.block
->kind
|= block_kind_export_end
;
10681 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10682 ngg_emit_nogs_output(&ctx
);
10683 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10684 Builder
bld(ctx
.program
, ctx
.block
);
10685 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10686 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10687 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10688 write_tcs_tess_factors(&ctx
);
10691 if (ctx
.stage
== fragment_fs
) {
10692 create_fs_exports(&ctx
);
10693 ctx
.block
->kind
|= block_kind_export_end
;
10696 if (endif_merged_wave_info
) {
10697 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10698 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10701 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10702 ngg_emit_nogs_output(&ctx
);
10704 ralloc_free(ctx
.divergent_vals
);
10706 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10707 /* Outputs of the previous stage are inputs to the next stage */
10708 ctx
.inputs
= ctx
.outputs
;
10709 ctx
.outputs
= shader_io_state();
10713 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10715 append_logical_end(ctx
.block
);
10716 ctx
.block
->kind
|= block_kind_uniform
;
10717 Builder
bld(ctx
.program
, ctx
.block
);
10718 if (ctx
.program
->wb_smem_l1_on_end
)
10719 bld
.smem(aco_opcode::s_dcache_wb
, false);
10720 bld
.sopp(aco_opcode::s_endpgm
);
10722 cleanup_cfg(program
);
10725 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10726 ac_shader_config
* config
,
10727 struct radv_shader_args
*args
)
10729 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10731 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10732 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10733 program
->next_fp_mode
.must_flush_denorms32
= false;
10734 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10735 program
->next_fp_mode
.care_about_round32
= false;
10736 program
->next_fp_mode
.care_about_round16_64
= false;
10737 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10738 program
->next_fp_mode
.denorm32
= 0;
10739 program
->next_fp_mode
.round32
= fp_round_ne
;
10740 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10741 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10743 add_startpgm(&ctx
);
10744 append_logical_start(ctx
.block
);
10746 Builder
bld(ctx
.program
, ctx
.block
);
10748 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10750 Operand
stream_id(0u);
10751 if (args
->shader_info
->so
.num_outputs
)
10752 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10753 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10755 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10757 std::stack
<Block
> endif_blocks
;
10759 for (unsigned stream
= 0; stream
< 4; stream
++) {
10760 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10763 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10764 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10767 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10769 unsigned BB_if_idx
= ctx
.block
->index
;
10770 Block BB_endif
= Block();
10771 if (!stream_id
.isConstant()) {
10773 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10774 append_logical_end(ctx
.block
);
10775 ctx
.block
->kind
|= block_kind_uniform
;
10776 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10778 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10780 ctx
.block
= ctx
.program
->create_and_insert_block();
10781 add_edge(BB_if_idx
, ctx
.block
);
10782 bld
.reset(ctx
.block
);
10783 append_logical_start(ctx
.block
);
10786 unsigned offset
= 0;
10787 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10788 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10791 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10792 unsigned length
= util_last_bit(output_usage_mask
);
10793 for (unsigned j
= 0; j
< length
; ++j
) {
10794 if (!(output_usage_mask
& (1 << j
)))
10797 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10798 Temp voffset
= vtx_offset
;
10799 if (const_offset
>= 4096u) {
10800 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10801 const_offset
%= 4096u;
10804 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10805 mubuf
->definitions
[0] = bld
.def(v1
);
10806 mubuf
->operands
[0] = Operand(gsvs_ring
);
10807 mubuf
->operands
[1] = Operand(voffset
);
10808 mubuf
->operands
[2] = Operand(0u);
10809 mubuf
->offen
= true;
10810 mubuf
->offset
= const_offset
;
10813 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10814 mubuf
->barrier
= barrier_none
;
10815 mubuf
->can_reorder
= true;
10817 ctx
.outputs
.mask
[i
] |= 1 << j
;
10818 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10820 bld
.insert(std::move(mubuf
));
10826 if (args
->shader_info
->so
.num_outputs
) {
10827 emit_streamout(&ctx
, stream
);
10828 bld
.reset(ctx
.block
);
10832 create_vs_exports(&ctx
);
10833 ctx
.block
->kind
|= block_kind_export_end
;
10836 if (!stream_id
.isConstant()) {
10837 append_logical_end(ctx
.block
);
10839 /* branch from then block to endif block */
10840 bld
.branch(aco_opcode::p_branch
);
10841 add_edge(ctx
.block
->index
, &BB_endif
);
10842 ctx
.block
->kind
|= block_kind_uniform
;
10844 /* emit else block */
10845 ctx
.block
= ctx
.program
->create_and_insert_block();
10846 add_edge(BB_if_idx
, ctx
.block
);
10847 bld
.reset(ctx
.block
);
10848 append_logical_start(ctx
.block
);
10850 endif_blocks
.push(std::move(BB_endif
));
10854 while (!endif_blocks
.empty()) {
10855 Block BB_endif
= std::move(endif_blocks
.top());
10856 endif_blocks
.pop();
10858 Block
*BB_else
= ctx
.block
;
10860 append_logical_end(BB_else
);
10861 /* branch from else block to endif block */
10862 bld
.branch(aco_opcode::p_branch
);
10863 add_edge(BB_else
->index
, &BB_endif
);
10864 BB_else
->kind
|= block_kind_uniform
;
10866 /** emit endif merge block */
10867 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10868 bld
.reset(ctx
.block
);
10869 append_logical_start(ctx
.block
);
10872 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10874 append_logical_end(ctx
.block
);
10875 ctx
.block
->kind
|= block_kind_uniform
;
10876 bld
.sopp(aco_opcode::s_endpgm
);
10878 cleanup_cfg(program
);