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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 bld
.is_precise
= instr
->exact
;
595 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
596 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
597 if (src1
.type() == RegType::sgpr
) {
598 if (commutative
&& src0
.type() == RegType::vgpr
) {
603 src1
= as_vgpr(ctx
, src1
);
607 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
608 assert(dst
.size() == 1);
609 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
610 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
612 bld
.vop2(op
, Definition(dst
), src0
, src1
);
616 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
617 bool flush_denorms
= false)
619 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
620 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
621 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
623 /* ensure that the instruction has at most 1 sgpr operand
624 * The optimizer will inline constants for us */
625 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
626 src0
= as_vgpr(ctx
, src0
);
627 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
628 src1
= as_vgpr(ctx
, src1
);
629 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
630 src2
= as_vgpr(ctx
, src2
);
632 Builder
bld(ctx
->program
, ctx
->block
);
633 bld
.is_precise
= instr
->exact
;
634 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
635 assert(dst
.size() == 1);
636 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
637 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
639 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
643 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
645 Builder
bld(ctx
->program
, ctx
->block
);
646 bld
.is_precise
= instr
->exact
;
647 if (dst
.type() == RegType::sgpr
)
648 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
649 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
651 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
654 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
656 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
657 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
658 assert(src0
.size() == src1
.size());
660 aco_ptr
<Instruction
> vopc
;
661 if (src1
.type() == RegType::sgpr
) {
662 if (src0
.type() == RegType::vgpr
) {
663 /* to swap the operands, we might also have to change the opcode */
665 case aco_opcode::v_cmp_lt_f16
:
666 op
= aco_opcode::v_cmp_gt_f16
;
668 case aco_opcode::v_cmp_ge_f16
:
669 op
= aco_opcode::v_cmp_le_f16
;
671 case aco_opcode::v_cmp_lt_i16
:
672 op
= aco_opcode::v_cmp_gt_i16
;
674 case aco_opcode::v_cmp_ge_i16
:
675 op
= aco_opcode::v_cmp_le_i16
;
677 case aco_opcode::v_cmp_lt_u16
:
678 op
= aco_opcode::v_cmp_gt_u16
;
680 case aco_opcode::v_cmp_ge_u16
:
681 op
= aco_opcode::v_cmp_le_u16
;
683 case aco_opcode::v_cmp_lt_f32
:
684 op
= aco_opcode::v_cmp_gt_f32
;
686 case aco_opcode::v_cmp_ge_f32
:
687 op
= aco_opcode::v_cmp_le_f32
;
689 case aco_opcode::v_cmp_lt_i32
:
690 op
= aco_opcode::v_cmp_gt_i32
;
692 case aco_opcode::v_cmp_ge_i32
:
693 op
= aco_opcode::v_cmp_le_i32
;
695 case aco_opcode::v_cmp_lt_u32
:
696 op
= aco_opcode::v_cmp_gt_u32
;
698 case aco_opcode::v_cmp_ge_u32
:
699 op
= aco_opcode::v_cmp_le_u32
;
701 case aco_opcode::v_cmp_lt_f64
:
702 op
= aco_opcode::v_cmp_gt_f64
;
704 case aco_opcode::v_cmp_ge_f64
:
705 op
= aco_opcode::v_cmp_le_f64
;
707 case aco_opcode::v_cmp_lt_i64
:
708 op
= aco_opcode::v_cmp_gt_i64
;
710 case aco_opcode::v_cmp_ge_i64
:
711 op
= aco_opcode::v_cmp_le_i64
;
713 case aco_opcode::v_cmp_lt_u64
:
714 op
= aco_opcode::v_cmp_gt_u64
;
716 case aco_opcode::v_cmp_ge_u64
:
717 op
= aco_opcode::v_cmp_le_u64
;
719 default: /* eq and ne are commutative */
726 src1
= as_vgpr(ctx
, src1
);
730 Builder
bld(ctx
->program
, ctx
->block
);
731 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
734 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
736 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
737 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
738 Builder
bld(ctx
->program
, ctx
->block
);
740 assert(dst
.regClass() == bld
.lm
);
741 assert(src0
.type() == RegType::sgpr
);
742 assert(src1
.type() == RegType::sgpr
);
743 assert(src0
.regClass() == src1
.regClass());
745 /* Emit the SALU comparison instruction */
746 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
747 /* Turn the result into a per-lane bool */
748 bool_to_vector_condition(ctx
, cmp
, dst
);
751 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
752 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
754 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
755 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
756 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
757 nir_dest_is_divergent(instr
->dest
.dest
) ||
758 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
759 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
760 aco_opcode op
= use_valu
? v_op
: s_op
;
761 assert(op
!= aco_opcode::num_opcodes
);
762 assert(dst
.regClass() == ctx
->program
->lane_mask
);
765 emit_vopc_instruction(ctx
, instr
, op
, dst
);
767 emit_sopc_instruction(ctx
, instr
, op
, dst
);
770 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
772 Builder
bld(ctx
->program
, ctx
->block
);
773 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
774 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
776 assert(dst
.regClass() == bld
.lm
);
777 assert(src0
.regClass() == bld
.lm
);
778 assert(src1
.regClass() == bld
.lm
);
780 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
783 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
785 Builder
bld(ctx
->program
, ctx
->block
);
786 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
787 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
788 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
790 assert(cond
.regClass() == bld
.lm
);
792 if (dst
.type() == RegType::vgpr
) {
793 aco_ptr
<Instruction
> bcsel
;
794 if (dst
.size() == 1) {
795 then
= as_vgpr(ctx
, then
);
796 els
= as_vgpr(ctx
, els
);
798 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
799 } else if (dst
.size() == 2) {
800 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
801 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
802 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
803 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
805 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
806 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
808 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
810 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
811 nir_print_instr(&instr
->instr
, stderr
);
812 fprintf(stderr
, "\n");
817 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
818 assert(dst
.regClass() == bld
.lm
);
819 assert(then
.regClass() == bld
.lm
);
820 assert(els
.regClass() == bld
.lm
);
823 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
824 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
825 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
826 assert(dst
.size() == then
.size());
827 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
828 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
830 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
831 nir_print_instr(&instr
->instr
, stderr
);
832 fprintf(stderr
, "\n");
837 /* divergent boolean bcsel
838 * this implements bcsel on bools: dst = s0 ? s1 : s2
839 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
840 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
842 if (cond
.id() != then
.id())
843 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
845 if (cond
.id() == els
.id())
846 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
848 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
849 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
852 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
853 aco_opcode op
, uint32_t undo
)
855 /* multiply by 16777216 to handle denormals */
856 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
857 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
858 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
859 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
860 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
862 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
864 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
867 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
869 if (ctx
->block
->fp_mode
.denorm32
== 0) {
870 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
874 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
877 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
879 if (ctx
->block
->fp_mode
.denorm32
== 0) {
880 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
884 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
887 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
889 if (ctx
->block
->fp_mode
.denorm32
== 0) {
890 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
894 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
897 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
899 if (ctx
->block
->fp_mode
.denorm32
== 0) {
900 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
904 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
907 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
909 if (ctx
->options
->chip_class
>= GFX7
)
910 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
912 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
913 /* TODO: create more efficient code! */
914 if (val
.type() == RegType::sgpr
)
915 val
= as_vgpr(ctx
, val
);
917 /* Split the input value. */
918 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
919 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
921 /* Extract the exponent and compute the unbiased value. */
922 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
923 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
925 /* Extract the fractional part. */
926 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
927 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
929 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
932 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
933 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
934 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
935 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
936 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
938 /* Get the sign bit. */
939 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
941 /* Decide the operation to apply depending on the unbiased exponent. */
942 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
943 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
944 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
945 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
946 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
947 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
949 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
952 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
954 if (ctx
->options
->chip_class
>= GFX7
)
955 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
957 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
958 Temp src0
= as_vgpr(ctx
, val
);
960 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
961 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
963 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
964 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
965 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
967 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
968 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
969 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
970 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
972 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
973 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
975 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
977 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
978 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
980 return add
->definitions
[0].getTemp();
983 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
985 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
986 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
988 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
991 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
992 return bld
.copy(Definition(dst
), src
);
993 else if (dst
.bytes() < src
.bytes())
994 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
998 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1001 } else if (src
.regClass() == s1
) {
1003 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1005 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1006 } else if (ctx
->options
->chip_class
>= GFX8
) {
1007 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1008 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1009 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1010 sdwa
->operands
[0] = Operand(src
);
1011 sdwa
->definitions
[0] = Definition(tmp
);
1013 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1015 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1016 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1017 bld
.insert(std::move(sdwa
));
1019 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1020 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1021 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1024 if (dst_bits
== 64) {
1025 if (is_signed
&& dst
.regClass() == s2
) {
1026 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1027 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1028 } else if (is_signed
&& dst
.regClass() == v2
) {
1029 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1030 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1032 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1039 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1041 if (!instr
->dest
.dest
.is_ssa
) {
1042 fprintf(stderr
, "nir alu dst not in ssa: ");
1043 nir_print_instr(&instr
->instr
, stderr
);
1044 fprintf(stderr
, "\n");
1047 Builder
bld(ctx
->program
, ctx
->block
);
1048 bld
.is_precise
= instr
->exact
;
1049 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1054 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1055 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1056 for (unsigned i
= 0; i
< num
; ++i
)
1057 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1059 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1060 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1061 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1062 for (unsigned i
= 0; i
< num
; ++i
) {
1063 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1064 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1066 vec
->operands
[i
] = Operand
{elems
[i
]};
1068 vec
->definitions
[0] = Definition(dst
);
1069 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1070 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1072 // TODO: that is a bit suboptimal..
1073 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1074 for (unsigned i
= 0; i
< num
- 1; ++i
)
1075 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1076 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1077 for (unsigned i
= 0; i
< num
; ++i
) {
1078 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1079 if (bit
% 32 == 0) {
1080 elems
[bit
/ 32] = elems
[i
];
1082 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1083 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1084 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1087 if (dst
.size() == 1)
1088 bld
.copy(Definition(dst
), elems
[0]);
1090 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1095 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1096 aco_ptr
<Instruction
> mov
;
1097 if (dst
.type() == RegType::sgpr
) {
1098 if (src
.type() == RegType::vgpr
)
1099 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1100 else if (src
.regClass() == s1
)
1101 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1102 else if (src
.regClass() == s2
)
1103 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1105 unreachable("wrong src register class for nir_op_imov");
1107 if (dst
.regClass() == v1
)
1108 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1109 else if (dst
.regClass() == v1b
||
1110 dst
.regClass() == v2b
||
1111 dst
.regClass() == v2
)
1112 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1114 unreachable("wrong src register class for nir_op_imov");
1119 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1120 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1121 assert(src
.regClass() == bld
.lm
);
1122 assert(dst
.regClass() == bld
.lm
);
1123 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1124 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1125 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1126 } else if (dst
.regClass() == v1
) {
1127 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1128 } else if (dst
.type() == RegType::sgpr
) {
1129 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1130 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1133 nir_print_instr(&instr
->instr
, stderr
);
1134 fprintf(stderr
, "\n");
1139 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1140 if (dst
.regClass() == v1
) {
1141 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1142 } else if (dst
.regClass() == s1
) {
1143 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1144 } else if (dst
.size() == 2) {
1145 Temp src0
= bld
.tmp(dst
.type(), 1);
1146 Temp src1
= bld
.tmp(dst
.type(), 1);
1147 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1149 if (dst
.regClass() == s2
) {
1150 Temp carry
= bld
.tmp(s1
);
1151 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1152 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1155 Temp lower
= bld
.tmp(v1
);
1156 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1157 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (dst
.regClass() == s1
) {
1169 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1170 } else if (dst
.regClass() == v1
) {
1171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1172 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1174 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1175 nir_print_instr(&instr
->instr
, stderr
);
1176 fprintf(stderr
, "\n");
1180 case nir_op_isign
: {
1181 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1182 if (dst
.regClass() == s1
) {
1183 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1184 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1185 } else if (dst
.regClass() == s2
) {
1186 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1188 if (ctx
->program
->chip_class
>= GFX8
)
1189 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1191 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1192 /* SCC gets zero-extended to 64 bit */
1193 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1194 } else if (dst
.regClass() == v1
) {
1195 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1196 } else if (dst
.regClass() == v2
) {
1197 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1198 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1199 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1200 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1201 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1202 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1204 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1205 nir_print_instr(&instr
->instr
, stderr
);
1206 fprintf(stderr
, "\n");
1211 if (dst
.regClass() == v1
) {
1212 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1213 } else if (dst
.regClass() == s1
) {
1214 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1216 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1217 nir_print_instr(&instr
->instr
, stderr
);
1218 fprintf(stderr
, "\n");
1223 if (dst
.regClass() == v1
) {
1224 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1225 } else if (dst
.regClass() == s1
) {
1226 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1228 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1229 nir_print_instr(&instr
->instr
, stderr
);
1230 fprintf(stderr
, "\n");
1235 if (dst
.regClass() == v1
) {
1236 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1237 } else if (dst
.regClass() == s1
) {
1238 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1240 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1241 nir_print_instr(&instr
->instr
, stderr
);
1242 fprintf(stderr
, "\n");
1247 if (dst
.regClass() == v1
) {
1248 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1249 } else if (dst
.regClass() == s1
) {
1250 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1252 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1253 nir_print_instr(&instr
->instr
, stderr
);
1254 fprintf(stderr
, "\n");
1259 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1260 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1261 } else if (dst
.regClass() == v1
) {
1262 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1263 } else if (dst
.regClass() == s1
) {
1264 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1265 } else if (dst
.regClass() == s2
) {
1266 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1268 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1269 nir_print_instr(&instr
->instr
, stderr
);
1270 fprintf(stderr
, "\n");
1275 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1276 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1277 } else if (dst
.regClass() == v1
) {
1278 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1279 } else if (dst
.regClass() == s1
) {
1280 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1281 } else if (dst
.regClass() == s2
) {
1282 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1291 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1292 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1293 } else if (dst
.regClass() == v1
) {
1294 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1295 } else if (dst
.regClass() == s1
) {
1296 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1297 } else if (dst
.regClass() == s2
) {
1298 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1300 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1301 nir_print_instr(&instr
->instr
, stderr
);
1302 fprintf(stderr
, "\n");
1307 if (dst
.regClass() == v1
) {
1308 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1309 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1310 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1311 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1312 } else if (dst
.regClass() == v2
) {
1313 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1314 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1315 } else if (dst
.regClass() == s2
) {
1316 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1317 } else if (dst
.regClass() == s1
) {
1318 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1320 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1321 nir_print_instr(&instr
->instr
, stderr
);
1322 fprintf(stderr
, "\n");
1327 if (dst
.regClass() == v1
) {
1328 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1329 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1330 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1331 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1332 } else if (dst
.regClass() == v2
) {
1333 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1334 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1335 } else if (dst
.regClass() == s1
) {
1336 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1337 } else if (dst
.regClass() == s2
) {
1338 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1340 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1341 nir_print_instr(&instr
->instr
, stderr
);
1342 fprintf(stderr
, "\n");
1347 if (dst
.regClass() == v1
) {
1348 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1349 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1350 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1351 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1352 } else if (dst
.regClass() == v2
) {
1353 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1354 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1360 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1361 nir_print_instr(&instr
->instr
, stderr
);
1362 fprintf(stderr
, "\n");
1366 case nir_op_find_lsb
: {
1367 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1368 if (src
.regClass() == s1
) {
1369 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1370 } else if (src
.regClass() == v1
) {
1371 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1372 } else if (src
.regClass() == s2
) {
1373 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1375 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1376 nir_print_instr(&instr
->instr
, stderr
);
1377 fprintf(stderr
, "\n");
1381 case nir_op_ufind_msb
:
1382 case nir_op_ifind_msb
: {
1383 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1384 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1385 aco_opcode op
= src
.regClass() == s2
?
1386 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1387 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1388 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1390 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1391 Operand(src
.size() * 32u - 1u), msb_rev
);
1392 Temp msb
= sub
.def(0).getTemp();
1393 Temp carry
= sub
.def(1).getTemp();
1395 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1396 } else if (src
.regClass() == v1
) {
1397 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1398 Temp msb_rev
= bld
.tmp(v1
);
1399 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1400 Temp msb
= bld
.tmp(v1
);
1401 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1402 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1404 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1405 nir_print_instr(&instr
->instr
, stderr
);
1406 fprintf(stderr
, "\n");
1410 case nir_op_bitfield_reverse
: {
1411 if (dst
.regClass() == s1
) {
1412 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1413 } else if (dst
.regClass() == v1
) {
1414 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1416 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1417 nir_print_instr(&instr
->instr
, stderr
);
1418 fprintf(stderr
, "\n");
1423 if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1428 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1429 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1430 if (dst
.regClass() == v1
) {
1431 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1435 assert(src0
.size() == 2 && src1
.size() == 2);
1436 Temp src00
= bld
.tmp(src0
.type(), 1);
1437 Temp src01
= bld
.tmp(dst
.type(), 1);
1438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1439 Temp src10
= bld
.tmp(src1
.type(), 1);
1440 Temp src11
= bld
.tmp(dst
.type(), 1);
1441 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1443 if (dst
.regClass() == s2
) {
1444 Temp carry
= bld
.tmp(s1
);
1445 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1446 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1447 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1448 } else if (dst
.regClass() == v2
) {
1449 Temp dst0
= bld
.tmp(v1
);
1450 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1451 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1452 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1454 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1455 nir_print_instr(&instr
->instr
, stderr
);
1456 fprintf(stderr
, "\n");
1460 case nir_op_uadd_sat
: {
1461 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1462 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1463 if (dst
.regClass() == s1
) {
1464 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1465 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1467 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1468 } else if (dst
.regClass() == v1
) {
1469 if (ctx
->options
->chip_class
>= GFX9
) {
1470 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1471 add
->operands
[0] = Operand(src0
);
1472 add
->operands
[1] = Operand(src1
);
1473 add
->definitions
[0] = Definition(dst
);
1475 ctx
->block
->instructions
.emplace_back(std::move(add
));
1477 if (src1
.regClass() != v1
)
1478 std::swap(src0
, src1
);
1479 assert(src1
.regClass() == v1
);
1480 Temp tmp
= bld
.tmp(v1
);
1481 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1482 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1485 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1486 nir_print_instr(&instr
->instr
, stderr
);
1487 fprintf(stderr
, "\n");
1491 case nir_op_uadd_carry
: {
1492 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1493 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1494 if (dst
.regClass() == s1
) {
1495 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1498 if (dst
.regClass() == v1
) {
1499 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1500 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1504 Temp src00
= bld
.tmp(src0
.type(), 1);
1505 Temp src01
= bld
.tmp(dst
.type(), 1);
1506 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1507 Temp src10
= bld
.tmp(src1
.type(), 1);
1508 Temp src11
= bld
.tmp(dst
.type(), 1);
1509 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1510 if (dst
.regClass() == s2
) {
1511 Temp carry
= bld
.tmp(s1
);
1512 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1513 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1514 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1515 } else if (dst
.regClass() == v2
) {
1516 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1517 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1518 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1519 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1521 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1522 nir_print_instr(&instr
->instr
, stderr
);
1523 fprintf(stderr
, "\n");
1528 if (dst
.regClass() == s1
) {
1529 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1533 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1534 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1535 if (dst
.regClass() == v1
) {
1536 bld
.vsub32(Definition(dst
), src0
, src1
);
1540 Temp src00
= bld
.tmp(src0
.type(), 1);
1541 Temp src01
= bld
.tmp(dst
.type(), 1);
1542 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1543 Temp src10
= bld
.tmp(src1
.type(), 1);
1544 Temp src11
= bld
.tmp(dst
.type(), 1);
1545 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1546 if (dst
.regClass() == s2
) {
1547 Temp carry
= bld
.tmp(s1
);
1548 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1549 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1550 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1551 } else if (dst
.regClass() == v2
) {
1552 Temp lower
= bld
.tmp(v1
);
1553 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1554 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1555 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1557 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1558 nir_print_instr(&instr
->instr
, stderr
);
1559 fprintf(stderr
, "\n");
1563 case nir_op_usub_borrow
: {
1564 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1565 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1566 if (dst
.regClass() == s1
) {
1567 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1569 } else if (dst
.regClass() == v1
) {
1570 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1571 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1575 Temp src00
= bld
.tmp(src0
.type(), 1);
1576 Temp src01
= bld
.tmp(dst
.type(), 1);
1577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1578 Temp src10
= bld
.tmp(src1
.type(), 1);
1579 Temp src11
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1581 if (dst
.regClass() == s2
) {
1582 Temp borrow
= bld
.tmp(s1
);
1583 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1584 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1586 } else if (dst
.regClass() == v2
) {
1587 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1588 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1589 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1592 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1593 nir_print_instr(&instr
->instr
, stderr
);
1594 fprintf(stderr
, "\n");
1599 if (dst
.regClass() == v1
) {
1600 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1601 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1602 } else if (dst
.regClass() == s1
) {
1603 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1606 nir_print_instr(&instr
->instr
, stderr
);
1607 fprintf(stderr
, "\n");
1611 case nir_op_umul_high
: {
1612 if (dst
.regClass() == v1
) {
1613 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1614 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1615 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1616 } else if (dst
.regClass() == s1
) {
1617 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1618 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1619 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1627 case nir_op_imul_high
: {
1628 if (dst
.regClass() == v1
) {
1629 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1630 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1631 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1632 } else if (dst
.regClass() == s1
) {
1633 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1634 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1635 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1637 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1638 nir_print_instr(&instr
->instr
, stderr
);
1639 fprintf(stderr
, "\n");
1644 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1645 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1646 if (dst
.regClass() == v2b
) {
1647 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1648 } else if (dst
.regClass() == v1
) {
1649 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1650 } else if (dst
.regClass() == v2
) {
1651 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1653 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1654 nir_print_instr(&instr
->instr
, stderr
);
1655 fprintf(stderr
, "\n");
1660 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1661 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1662 if (dst
.regClass() == v2b
) {
1663 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1664 } else if (dst
.regClass() == v1
) {
1665 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1666 } else if (dst
.regClass() == v2
) {
1667 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1669 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1670 nir_print_instr(&instr
->instr
, stderr
);
1671 fprintf(stderr
, "\n");
1676 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1677 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1678 if (dst
.regClass() == v2b
) {
1679 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1680 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1682 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1683 } else if (dst
.regClass() == v1
) {
1684 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1685 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1687 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1688 } else if (dst
.regClass() == v2
) {
1689 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1690 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1691 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1694 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1695 nir_print_instr(&instr
->instr
, stderr
);
1696 fprintf(stderr
, "\n");
1701 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1702 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1703 if (dst
.regClass() == v2b
) {
1704 // TODO: check fp_mode.must_flush_denorms16_64
1705 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1706 } else if (dst
.regClass() == v1
) {
1707 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1708 } else if (dst
.regClass() == v2
) {
1709 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1710 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1711 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1713 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1716 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1717 nir_print_instr(&instr
->instr
, stderr
);
1718 fprintf(stderr
, "\n");
1723 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1724 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1725 if (dst
.regClass() == v2b
) {
1726 // TODO: check fp_mode.must_flush_denorms16_64
1727 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1728 } else if (dst
.regClass() == v1
) {
1729 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1730 } else if (dst
.regClass() == v2
) {
1731 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1732 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1733 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1735 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1738 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1739 nir_print_instr(&instr
->instr
, stderr
);
1740 fprintf(stderr
, "\n");
1744 case nir_op_fmax3
: {
1745 if (dst
.regClass() == v2b
) {
1746 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1747 } else if (dst
.regClass() == v1
) {
1748 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1751 nir_print_instr(&instr
->instr
, stderr
);
1752 fprintf(stderr
, "\n");
1756 case nir_op_fmin3
: {
1757 if (dst
.regClass() == v2b
) {
1758 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1759 } else if (dst
.regClass() == v1
) {
1760 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1762 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1763 nir_print_instr(&instr
->instr
, stderr
);
1764 fprintf(stderr
, "\n");
1768 case nir_op_fmed3
: {
1769 if (dst
.regClass() == v2b
) {
1770 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1771 } else if (dst
.regClass() == v1
) {
1772 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1774 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1775 nir_print_instr(&instr
->instr
, stderr
);
1776 fprintf(stderr
, "\n");
1780 case nir_op_umax3
: {
1781 if (dst
.size() == 1) {
1782 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1784 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1785 nir_print_instr(&instr
->instr
, stderr
);
1786 fprintf(stderr
, "\n");
1790 case nir_op_umin3
: {
1791 if (dst
.size() == 1) {
1792 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1794 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1795 nir_print_instr(&instr
->instr
, stderr
);
1796 fprintf(stderr
, "\n");
1800 case nir_op_umed3
: {
1801 if (dst
.size() == 1) {
1802 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1804 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1805 nir_print_instr(&instr
->instr
, stderr
);
1806 fprintf(stderr
, "\n");
1810 case nir_op_imax3
: {
1811 if (dst
.size() == 1) {
1812 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1814 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1815 nir_print_instr(&instr
->instr
, stderr
);
1816 fprintf(stderr
, "\n");
1820 case nir_op_imin3
: {
1821 if (dst
.size() == 1) {
1822 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1830 case nir_op_imed3
: {
1831 if (dst
.size() == 1) {
1832 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1834 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1835 nir_print_instr(&instr
->instr
, stderr
);
1836 fprintf(stderr
, "\n");
1840 case nir_op_cube_face_coord
: {
1841 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1842 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1843 emit_extract_vector(ctx
, in
, 1, v1
),
1844 emit_extract_vector(ctx
, in
, 2, v1
) };
1845 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1846 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1847 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1848 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1849 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1850 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1851 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1854 case nir_op_cube_face_index
: {
1855 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1856 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1857 emit_extract_vector(ctx
, in
, 1, v1
),
1858 emit_extract_vector(ctx
, in
, 2, v1
) };
1859 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1862 case nir_op_bcsel
: {
1863 emit_bcsel(ctx
, instr
, dst
);
1867 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1868 if (dst
.regClass() == v2b
) {
1869 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1870 } else if (dst
.regClass() == v1
) {
1871 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1872 } else if (dst
.regClass() == v2
) {
1873 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1875 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1876 nir_print_instr(&instr
->instr
, stderr
);
1877 fprintf(stderr
, "\n");
1882 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1883 if (dst
.regClass() == v2b
) {
1884 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1885 } else if (dst
.regClass() == v1
) {
1886 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1887 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1888 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1889 } else if (dst
.regClass() == v2
) {
1890 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1891 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1892 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1893 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1894 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1895 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1898 nir_print_instr(&instr
->instr
, stderr
);
1899 fprintf(stderr
, "\n");
1904 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1905 if (dst
.regClass() == v2b
) {
1906 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1907 } else if (dst
.regClass() == v1
) {
1908 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1909 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1910 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1911 } else if (dst
.regClass() == v2
) {
1912 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1913 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1914 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1915 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1916 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1917 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1919 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1920 nir_print_instr(&instr
->instr
, stderr
);
1921 fprintf(stderr
, "\n");
1926 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1927 if (dst
.regClass() == v2b
) {
1928 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1929 } else if (dst
.regClass() == v1
) {
1930 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1931 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1932 // TODO: confirm that this holds under any circumstances
1933 } else if (dst
.regClass() == v2
) {
1934 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1935 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1938 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1939 nir_print_instr(&instr
->instr
, stderr
);
1940 fprintf(stderr
, "\n");
1944 case nir_op_flog2
: {
1945 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1946 if (dst
.regClass() == v2b
) {
1947 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1948 } else if (dst
.regClass() == v1
) {
1949 emit_log2(ctx
, bld
, Definition(dst
), src
);
1951 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1952 nir_print_instr(&instr
->instr
, stderr
);
1953 fprintf(stderr
, "\n");
1958 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1959 if (dst
.regClass() == v2b
) {
1960 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1961 } else if (dst
.regClass() == v1
) {
1962 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1963 } else if (dst
.regClass() == v2
) {
1964 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1966 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1967 nir_print_instr(&instr
->instr
, stderr
);
1968 fprintf(stderr
, "\n");
1972 case nir_op_fexp2
: {
1973 if (dst
.regClass() == v2b
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1975 } else if (dst
.regClass() == v1
) {
1976 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1978 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1979 nir_print_instr(&instr
->instr
, stderr
);
1980 fprintf(stderr
, "\n");
1984 case nir_op_fsqrt
: {
1985 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1986 if (dst
.regClass() == v2b
) {
1987 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1988 } else if (dst
.regClass() == v1
) {
1989 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1990 } else if (dst
.regClass() == v2
) {
1991 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1993 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1994 nir_print_instr(&instr
->instr
, stderr
);
1995 fprintf(stderr
, "\n");
1999 case nir_op_ffract
: {
2000 if (dst
.regClass() == v2b
) {
2001 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2002 } else if (dst
.regClass() == v1
) {
2003 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2004 } else if (dst
.regClass() == v2
) {
2005 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2007 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2008 nir_print_instr(&instr
->instr
, stderr
);
2009 fprintf(stderr
, "\n");
2013 case nir_op_ffloor
: {
2014 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2015 if (dst
.regClass() == v2b
) {
2016 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2017 } else if (dst
.regClass() == v1
) {
2018 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2019 } else if (dst
.regClass() == v2
) {
2020 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2022 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2023 nir_print_instr(&instr
->instr
, stderr
);
2024 fprintf(stderr
, "\n");
2028 case nir_op_fceil
: {
2029 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2030 if (dst
.regClass() == v2b
) {
2031 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2032 } else if (dst
.regClass() == v1
) {
2033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2034 } else if (dst
.regClass() == v2
) {
2035 if (ctx
->options
->chip_class
>= GFX7
) {
2036 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2038 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2039 /* trunc = trunc(src0)
2040 * if (src0 > 0.0 && src0 != trunc)
2043 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2044 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2045 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2046 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2047 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2048 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2049 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2052 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2053 nir_print_instr(&instr
->instr
, stderr
);
2054 fprintf(stderr
, "\n");
2058 case nir_op_ftrunc
: {
2059 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2060 if (dst
.regClass() == v2b
) {
2061 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2062 } else if (dst
.regClass() == v1
) {
2063 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2064 } else if (dst
.regClass() == v2
) {
2065 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2068 nir_print_instr(&instr
->instr
, stderr
);
2069 fprintf(stderr
, "\n");
2073 case nir_op_fround_even
: {
2074 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2075 if (dst
.regClass() == v2b
) {
2076 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2077 } else if (dst
.regClass() == v1
) {
2078 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2079 } else if (dst
.regClass() == v2
) {
2080 if (ctx
->options
->chip_class
>= GFX7
) {
2081 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2083 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2084 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2085 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2087 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2088 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2089 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2090 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2091 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2092 tmp
= sub
->definitions
[0].getTemp();
2094 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2095 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2096 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2097 Temp cond
= vop3
->definitions
[0].getTemp();
2099 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2100 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2101 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2102 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2104 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2115 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2116 aco_ptr
<Instruction
> norm
;
2117 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2118 if (dst
.regClass() == v2b
) {
2119 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2120 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2121 bld
.vop1(opcode
, Definition(dst
), tmp
);
2122 } else if (dst
.regClass() == v1
) {
2123 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2125 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2126 if (ctx
->options
->chip_class
< GFX9
)
2127 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2129 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2130 bld
.vop1(opcode
, Definition(dst
), tmp
);
2132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2133 nir_print_instr(&instr
->instr
, stderr
);
2134 fprintf(stderr
, "\n");
2138 case nir_op_ldexp
: {
2139 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2140 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2141 if (dst
.regClass() == v2b
) {
2142 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2143 } else if (dst
.regClass() == v1
) {
2144 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2145 } else if (dst
.regClass() == v2
) {
2146 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_frexp_sig
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (dst
.regClass() == v2b
) {
2157 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2158 } else if (dst
.regClass() == v1
) {
2159 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2160 } else if (dst
.regClass() == v2
) {
2161 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2163 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2164 nir_print_instr(&instr
->instr
, stderr
);
2165 fprintf(stderr
, "\n");
2169 case nir_op_frexp_exp
: {
2170 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2171 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2172 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2173 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2174 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2175 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2176 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2177 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2178 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2180 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2181 nir_print_instr(&instr
->instr
, stderr
);
2182 fprintf(stderr
, "\n");
2186 case nir_op_fsign
: {
2187 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2188 if (dst
.regClass() == v2b
) {
2189 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2190 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2191 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2193 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2194 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2195 } else if (dst
.regClass() == v1
) {
2196 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2197 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2198 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2199 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2200 } else if (dst
.regClass() == v2
) {
2201 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2202 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2203 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2205 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2206 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2207 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2209 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2211 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2212 nir_print_instr(&instr
->instr
, stderr
);
2213 fprintf(stderr
, "\n");
2218 case nir_op_f2f16_rtne
: {
2219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2220 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2221 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2222 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2225 case nir_op_f2f16_rtz
: {
2226 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2227 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2228 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2229 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2232 case nir_op_f2f32
: {
2233 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2234 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2235 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2236 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2238 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2239 nir_print_instr(&instr
->instr
, stderr
);
2240 fprintf(stderr
, "\n");
2244 case nir_op_f2f64
: {
2245 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2246 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2247 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2248 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2251 case nir_op_i2f16
: {
2252 assert(dst
.regClass() == v2b
);
2253 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2254 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2255 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2256 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2257 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2258 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2261 case nir_op_i2f32
: {
2262 assert(dst
.size() == 1);
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2265 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2266 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2269 case nir_op_i2f64
: {
2270 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2271 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2272 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2273 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2274 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2275 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2277 RegClass rc
= RegClass(src
.type(), 1);
2278 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2279 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2280 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2281 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2282 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2283 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2286 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2287 nir_print_instr(&instr
->instr
, stderr
);
2288 fprintf(stderr
, "\n");
2292 case nir_op_u2f16
: {
2293 assert(dst
.regClass() == v2b
);
2294 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2295 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2296 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2297 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2298 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2299 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2302 case nir_op_u2f32
: {
2303 assert(dst
.size() == 1);
2304 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2305 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2306 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2308 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2309 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2310 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2314 case nir_op_u2f64
: {
2315 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2316 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2317 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2318 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2319 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2320 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2321 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2322 RegClass rc
= RegClass(src
.type(), 1);
2323 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2324 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2325 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2326 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2327 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2328 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2330 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2331 nir_print_instr(&instr
->instr
, stderr
);
2332 fprintf(stderr
, "\n");
2337 case nir_op_f2i16
: {
2338 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2339 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2340 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2341 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2343 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2347 case nir_op_f2u16
: {
2348 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2349 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2350 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2351 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2353 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2356 case nir_op_f2i32
: {
2357 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2358 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2359 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2360 if (dst
.type() == RegType::vgpr
) {
2361 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2363 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2364 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2366 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2367 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2368 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2369 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2371 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2372 nir_print_instr(&instr
->instr
, stderr
);
2373 fprintf(stderr
, "\n");
2377 case nir_op_f2u32
: {
2378 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2379 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2380 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2381 if (dst
.type() == RegType::vgpr
) {
2382 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2384 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2385 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2387 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2388 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2389 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2390 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2392 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2393 nir_print_instr(&instr
->instr
, stderr
);
2394 fprintf(stderr
, "\n");
2398 case nir_op_f2i64
: {
2399 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2400 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2401 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2403 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2404 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2405 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2406 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2407 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2408 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2409 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2410 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2411 Temp new_exponent
= bld
.tmp(v1
);
2412 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2413 if (ctx
->program
->chip_class
>= GFX8
)
2414 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2416 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2417 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2418 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2419 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2420 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2421 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2422 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2423 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2424 Temp new_lower
= bld
.tmp(v1
);
2425 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2426 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2427 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2429 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2430 if (src
.type() == RegType::vgpr
)
2431 src
= bld
.as_uniform(src
);
2432 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2433 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2434 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2435 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2436 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2437 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2438 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2439 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2440 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2441 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2442 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2443 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2444 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2445 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2446 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2447 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2448 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2449 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2450 Temp borrow
= bld
.tmp(s1
);
2451 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2452 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2453 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2455 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2456 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2457 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2458 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2459 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2460 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2461 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2462 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2463 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2464 if (dst
.type() == RegType::sgpr
) {
2465 lower
= bld
.as_uniform(lower
);
2466 upper
= bld
.as_uniform(upper
);
2468 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2471 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2472 nir_print_instr(&instr
->instr
, stderr
);
2473 fprintf(stderr
, "\n");
2477 case nir_op_f2u64
: {
2478 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2479 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2480 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2482 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2483 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2484 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2485 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2486 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2487 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2488 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2489 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2490 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2491 Temp new_exponent
= bld
.tmp(v1
);
2492 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2493 if (ctx
->program
->chip_class
>= GFX8
)
2494 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2496 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2497 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2498 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2499 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2500 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2501 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2502 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2503 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2505 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2506 if (src
.type() == RegType::vgpr
)
2507 src
= bld
.as_uniform(src
);
2508 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2509 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2510 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2511 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2512 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2513 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2514 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2515 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2516 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2517 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2518 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2519 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2520 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2521 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2522 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2523 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2524 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2525 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2527 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2528 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2529 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2530 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2531 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2532 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2533 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2534 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2535 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2536 if (dst
.type() == RegType::sgpr
) {
2537 lower
= bld
.as_uniform(lower
);
2538 upper
= bld
.as_uniform(upper
);
2540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2543 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2544 nir_print_instr(&instr
->instr
, stderr
);
2545 fprintf(stderr
, "\n");
2549 case nir_op_b2f16
: {
2550 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2551 assert(src
.regClass() == bld
.lm
);
2553 if (dst
.regClass() == s1
) {
2554 src
= bool_to_scalar_condition(ctx
, src
);
2555 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2556 } else if (dst
.regClass() == v2b
) {
2557 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2558 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2560 unreachable("Wrong destination register class for nir_op_b2f16.");
2564 case nir_op_b2f32
: {
2565 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2566 assert(src
.regClass() == bld
.lm
);
2568 if (dst
.regClass() == s1
) {
2569 src
= bool_to_scalar_condition(ctx
, src
);
2570 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2571 } else if (dst
.regClass() == v1
) {
2572 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2574 unreachable("Wrong destination register class for nir_op_b2f32.");
2578 case nir_op_b2f64
: {
2579 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2580 assert(src
.regClass() == bld
.lm
);
2582 if (dst
.regClass() == s2
) {
2583 src
= bool_to_scalar_condition(ctx
, src
);
2584 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2585 } else if (dst
.regClass() == v2
) {
2586 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2587 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2590 unreachable("Wrong destination register class for nir_op_b2f64.");
2597 case nir_op_i2i64
: {
2598 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2599 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2605 case nir_op_u2u64
: {
2606 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2607 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2611 case nir_op_b2i32
: {
2612 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2613 assert(src
.regClass() == bld
.lm
);
2615 if (dst
.regClass() == s1
) {
2616 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2617 bool_to_scalar_condition(ctx
, src
, dst
);
2618 } else if (dst
.regClass() == v1
) {
2619 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2621 unreachable("Invalid register class for b2i32");
2627 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2628 assert(dst
.regClass() == bld
.lm
);
2630 if (src
.type() == RegType::vgpr
) {
2631 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2632 assert(dst
.regClass() == bld
.lm
);
2633 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2634 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2636 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2638 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2639 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2641 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2642 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2644 bool_to_vector_condition(ctx
, tmp
, dst
);
2648 case nir_op_pack_64_2x32_split
: {
2649 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2650 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2652 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2655 case nir_op_unpack_64_2x32_split_x
:
2656 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2658 case nir_op_unpack_64_2x32_split_y
:
2659 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2661 case nir_op_unpack_32_2x16_split_x
:
2662 if (dst
.type() == RegType::vgpr
) {
2663 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2665 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2668 case nir_op_unpack_32_2x16_split_y
:
2669 if (dst
.type() == RegType::vgpr
) {
2670 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2672 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2675 case nir_op_pack_32_2x16_split
: {
2676 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2677 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2678 if (dst
.regClass() == v1
) {
2679 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2680 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2681 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2683 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2684 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2685 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2689 case nir_op_pack_half_2x16
: {
2690 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2692 if (dst
.regClass() == v1
) {
2693 Temp src0
= bld
.tmp(v1
);
2694 Temp src1
= bld
.tmp(v1
);
2695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2696 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2697 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2699 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2700 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2701 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2703 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2704 nir_print_instr(&instr
->instr
, stderr
);
2705 fprintf(stderr
, "\n");
2709 case nir_op_unpack_half_2x16_split_x
: {
2710 if (dst
.regClass() == v1
) {
2711 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2713 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2714 nir_print_instr(&instr
->instr
, stderr
);
2715 fprintf(stderr
, "\n");
2719 case nir_op_unpack_half_2x16_split_y
: {
2720 if (dst
.regClass() == v1
) {
2721 /* TODO: use SDWA here */
2722 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2723 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2725 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2726 nir_print_instr(&instr
->instr
, stderr
);
2727 fprintf(stderr
, "\n");
2731 case nir_op_fquantize2f16
: {
2732 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2733 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2736 if (ctx
->program
->chip_class
>= GFX8
) {
2737 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2738 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2739 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2741 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2742 * so compare the result and flush to 0 if it's smaller.
2744 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2745 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2746 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2747 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2748 cmp_res
= vop3
->definitions
[0].getTemp();
2751 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2752 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2753 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2755 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2760 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2761 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2763 if (dst
.regClass() == s1
) {
2764 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2765 } else if (dst
.regClass() == v1
) {
2766 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2769 nir_print_instr(&instr
->instr
, stderr
);
2770 fprintf(stderr
, "\n");
2774 case nir_op_bitfield_select
: {
2775 /* (mask & insert) | (~mask & base) */
2776 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2777 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2778 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2780 /* dst = (insert & bitmask) | (base & ~bitmask) */
2781 if (dst
.regClass() == s1
) {
2782 aco_ptr
<Instruction
> sop2
;
2783 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2784 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2786 if (const_insert
&& const_bitmask
) {
2787 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2789 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2790 lhs
= Operand(insert
);
2794 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2795 if (const_base
&& const_bitmask
) {
2796 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2798 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2799 rhs
= Operand(base
);
2802 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2804 } else if (dst
.regClass() == v1
) {
2805 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2806 base
= as_vgpr(ctx
, base
);
2807 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2808 insert
= as_vgpr(ctx
, insert
);
2810 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2813 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2814 nir_print_instr(&instr
->instr
, stderr
);
2815 fprintf(stderr
, "\n");
2821 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2822 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2823 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2825 if (dst
.type() == RegType::sgpr
) {
2827 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2828 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2829 if (const_offset
&& const_bits
) {
2830 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2831 extract
= Operand(const_extract
);
2835 width
= Operand(const_bits
->u32
<< 16);
2837 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2839 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2843 if (dst
.regClass() == s1
) {
2844 if (instr
->op
== nir_op_ubfe
)
2845 opcode
= aco_opcode::s_bfe_u32
;
2847 opcode
= aco_opcode::s_bfe_i32
;
2848 } else if (dst
.regClass() == s2
) {
2849 if (instr
->op
== nir_op_ubfe
)
2850 opcode
= aco_opcode::s_bfe_u64
;
2852 opcode
= aco_opcode::s_bfe_i64
;
2854 unreachable("Unsupported BFE bit size");
2857 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2861 if (dst
.regClass() == v1
) {
2862 if (instr
->op
== nir_op_ubfe
)
2863 opcode
= aco_opcode::v_bfe_u32
;
2865 opcode
= aco_opcode::v_bfe_i32
;
2867 unreachable("Unsupported BFE bit size");
2870 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2874 case nir_op_bit_count
: {
2875 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2876 if (src
.regClass() == s1
) {
2877 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2878 } else if (src
.regClass() == v1
) {
2879 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2880 } else if (src
.regClass() == v2
) {
2881 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2882 emit_extract_vector(ctx
, src
, 1, v1
),
2883 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2884 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2885 } else if (src
.regClass() == s2
) {
2886 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2889 nir_print_instr(&instr
->instr
, stderr
);
2890 fprintf(stderr
, "\n");
2895 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2899 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2903 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2907 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2911 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2915 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2919 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2920 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2922 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2923 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2927 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2928 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2930 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2931 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2935 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2939 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2944 case nir_op_fddx_fine
:
2945 case nir_op_fddy_fine
:
2946 case nir_op_fddx_coarse
:
2947 case nir_op_fddy_coarse
: {
2948 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2949 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2950 if (instr
->op
== nir_op_fddx_fine
) {
2951 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2952 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2953 } else if (instr
->op
== nir_op_fddy_fine
) {
2954 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2955 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2957 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2958 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2959 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2961 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2965 if (ctx
->program
->chip_class
>= GFX8
) {
2966 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2967 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2969 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2970 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2971 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2973 emit_wqm(ctx
, tmp
, dst
, true);
2977 fprintf(stderr
, "Unknown NIR ALU instr: ");
2978 nir_print_instr(&instr
->instr
, stderr
);
2979 fprintf(stderr
, "\n");
2983 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2985 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2987 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2988 // which get truncated the lsb if double and msb if int
2989 // for now, we only use s_mov_b64 with 64bit inline constants
2990 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2991 assert(dst
.type() == RegType::sgpr
);
2993 Builder
bld(ctx
->program
, ctx
->block
);
2995 if (instr
->def
.bit_size
== 1) {
2996 assert(dst
.regClass() == bld
.lm
);
2997 int val
= instr
->value
[0].b
? -1 : 0;
2998 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2999 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3000 } else if (instr
->def
.bit_size
== 8) {
3001 /* ensure that the value is correctly represented in the low byte of the register */
3002 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3003 } else if (instr
->def
.bit_size
== 16) {
3004 /* ensure that the value is correctly represented in the low half of the register */
3005 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3006 } else if (dst
.size() == 1) {
3007 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3009 assert(dst
.size() != 1);
3010 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3011 if (instr
->def
.bit_size
== 64)
3012 for (unsigned i
= 0; i
< dst
.size(); i
++)
3013 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3015 for (unsigned i
= 0; i
< dst
.size(); i
++)
3016 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3018 vec
->definitions
[0] = Definition(dst
);
3019 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3023 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3025 uint32_t new_mask
= 0;
3026 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3027 if (mask
& (1u << i
))
3028 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3032 struct LoadEmitInfo
{
3035 unsigned num_components
;
3036 unsigned component_size
;
3037 Temp resource
= Temp(0, s1
);
3038 unsigned component_stride
= 0;
3039 unsigned const_offset
= 0;
3040 unsigned align_mul
= 0;
3041 unsigned align_offset
= 0;
3044 unsigned swizzle_component_size
= 0;
3045 barrier_interaction barrier
= barrier_none
;
3046 bool can_reorder
= true;
3047 Temp soffset
= Temp(0, s1
);
3050 using LoadCallback
= Temp(*)(
3051 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3052 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3054 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3055 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3057 unsigned load_size
= info
->num_components
* info
->component_size
;
3058 unsigned component_size
= info
->component_size
;
3060 unsigned num_vals
= 0;
3061 Temp vals
[info
->dst
.bytes()];
3063 unsigned const_offset
= info
->const_offset
;
3065 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3066 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3068 unsigned bytes_read
= 0;
3069 while (bytes_read
< load_size
) {
3070 unsigned bytes_needed
= load_size
- bytes_read
;
3072 /* add buffer for unaligned loads */
3073 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3076 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3077 if (info
->component_stride
) {
3078 assert(supports_8bit_16bit_loads
&& "unimplemented");
3082 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3083 bytes_needed
= align(bytes_needed
, 4);
3090 if (info
->swizzle_component_size
)
3091 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3092 if (info
->component_stride
)
3093 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3095 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3097 /* reduce constant offset */
3098 Operand offset
= info
->offset
;
3099 unsigned reduced_const_offset
= const_offset
;
3100 bool remove_const_offset_completely
= need_to_align_offset
;
3101 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3102 unsigned to_add
= const_offset
;
3103 if (remove_const_offset_completely
) {
3104 reduced_const_offset
= 0;
3106 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3107 reduced_const_offset
%= max_const_offset_plus_one
;
3109 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3110 if (offset
.isConstant()) {
3111 offset
= Operand(offset
.constantValue() + to_add
);
3112 } else if (offset_tmp
.regClass() == s1
) {
3113 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3114 offset_tmp
, Operand(to_add
));
3115 } else if (offset_tmp
.regClass() == v1
) {
3116 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3118 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3119 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3120 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3122 if (offset_tmp
.regClass() == s2
) {
3123 Temp carry
= bld
.tmp(s1
);
3124 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3125 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3126 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3128 Temp new_lo
= bld
.tmp(v1
);
3129 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3130 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3131 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3136 /* align offset down if needed */
3137 Operand aligned_offset
= offset
;
3138 if (need_to_align_offset
) {
3139 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3140 if (offset
.isConstant()) {
3141 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3142 } else if (offset_tmp
.regClass() == s1
) {
3143 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3144 } else if (offset_tmp
.regClass() == s2
) {
3145 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3146 } else if (offset_tmp
.regClass() == v1
) {
3147 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3148 } else if (offset_tmp
.regClass() == v2
) {
3149 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3150 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3151 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3152 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3155 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3156 bld
.copy(bld
.def(s1
), aligned_offset
);
3158 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3159 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3160 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3162 /* the callback wrote directly to dst */
3163 if (val
== info
->dst
) {
3164 assert(num_vals
== 0);
3165 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3169 /* shift result right if needed */
3170 if (info
->component_size
< 4 && byte_align_loads
) {
3171 Operand
align((uint32_t)byte_align
);
3172 if (byte_align
== -1) {
3173 if (offset
.isConstant())
3174 align
= Operand(offset
.constantValue() % 4u);
3175 else if (offset
.size() == 2)
3176 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3181 assert(val
.bytes() >= load_size
&& "unimplemented");
3182 if (val
.type() == RegType::sgpr
)
3183 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3185 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3189 /* add result to list and advance */
3190 if (info
->component_stride
) {
3191 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3192 const_offset
+= info
->component_stride
;
3193 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3195 const_offset
+= val
.bytes();
3196 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3198 bytes_read
+= val
.bytes();
3199 vals
[num_vals
++] = val
;
3202 /* create array of components */
3203 unsigned components_split
= 0;
3204 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3205 bool has_vgprs
= false;
3206 for (unsigned i
= 0; i
< num_vals
;) {
3208 unsigned num_tmps
= 0;
3209 unsigned tmp_size
= 0;
3210 RegType reg_type
= RegType::sgpr
;
3211 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3212 if (vals
[i
].type() == RegType::vgpr
)
3213 reg_type
= RegType::vgpr
;
3214 tmp_size
+= vals
[i
].bytes();
3215 tmp
[num_tmps
++] = vals
[i
++];
3218 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3219 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3220 for (unsigned i
= 0; i
< num_vals
; i
++)
3221 vec
->operands
[i
] = Operand(tmp
[i
]);
3222 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3223 vec
->definitions
[0] = Definition(tmp
[0]);
3224 bld
.insert(std::move(vec
));
3227 if (tmp
[0].bytes() % component_size
) {
3229 assert(i
== num_vals
);
3230 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3231 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3234 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3236 unsigned start
= components_split
;
3238 if (tmp_size
== elem_rc
.bytes()) {
3239 allocated_vec
[components_split
++] = tmp
[0];
3241 assert(tmp_size
% elem_rc
.bytes() == 0);
3242 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3243 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3244 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3245 Temp component
= bld
.tmp(elem_rc
);
3246 allocated_vec
[components_split
++] = component
;
3247 split
->definitions
[i
] = Definition(component
);
3249 split
->operands
[0] = Operand(tmp
[0]);
3250 bld
.insert(std::move(split
));
3253 /* try to p_as_uniform early so we can create more optimizable code and
3254 * also update allocated_vec */
3255 for (unsigned j
= start
; j
< components_split
; j
++) {
3256 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3257 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3258 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3262 /* concatenate components and p_as_uniform() result if needed */
3263 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3264 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3266 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3268 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3269 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3270 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3271 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3273 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3274 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3275 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3276 vec
->definitions
[0] = Definition(tmp
);
3277 bld
.insert(std::move(vec
));
3278 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3280 vec
->definitions
[0] = Definition(info
->dst
);
3281 bld
.insert(std::move(vec
));
3285 Operand
load_lds_size_m0(Builder
& bld
)
3287 /* TODO: m0 does not need to be initialized on GFX9+ */
3288 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3291 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3292 Temp offset
, unsigned bytes_needed
,
3293 unsigned align
, unsigned const_offset
,
3296 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3298 Operand m
= load_lds_size_m0(bld
);
3300 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3301 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3306 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3307 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3309 op
= aco_opcode::ds_read_b128
;
3310 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3313 op
= aco_opcode::ds_read2_b64
;
3314 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3316 op
= aco_opcode::ds_read_b96
;
3317 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3319 op
= aco_opcode::ds_read_b64
;
3320 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3323 op
= aco_opcode::ds_read2_b32
;
3324 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3326 op
= aco_opcode::ds_read_b32
;
3327 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3329 op
= aco_opcode::ds_read_u16
;
3332 op
= aco_opcode::ds_read_u8
;
3335 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3336 if (const_offset
>= max_offset_plus_one
) {
3337 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3338 const_offset
%= max_offset_plus_one
;
3342 const_offset
/= (size
/ 2u);
3344 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3345 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3347 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3349 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3352 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3357 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3359 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3360 Temp offset
, unsigned bytes_needed
,
3361 unsigned align
, unsigned const_offset
,
3366 if (bytes_needed
<= 4) {
3368 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3369 } else if (bytes_needed
<= 8) {
3371 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3372 } else if (bytes_needed
<= 16) {
3374 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3375 } else if (bytes_needed
<= 32) {
3377 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3380 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3382 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3383 if (info
->resource
.id()) {
3384 load
->operands
[0] = Operand(info
->resource
);
3385 load
->operands
[1] = Operand(offset
);
3387 load
->operands
[0] = Operand(offset
);
3388 load
->operands
[1] = Operand(0u);
3390 RegClass
rc(RegType::sgpr
, size
);
3391 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3392 load
->definitions
[0] = Definition(val
);
3393 load
->glc
= info
->glc
;
3394 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3395 load
->barrier
= info
->barrier
;
3396 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3397 bld
.insert(std::move(load
));
3401 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3403 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3404 Temp offset
, unsigned bytes_needed
,
3405 unsigned align_
, unsigned const_offset
,
3408 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3409 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3411 if (info
->soffset
.id()) {
3412 if (soffset
.isTemp())
3413 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3414 soffset
= Operand(info
->soffset
);
3417 unsigned bytes_size
= 0;
3419 if (bytes_needed
== 1) {
3421 op
= aco_opcode::buffer_load_ubyte
;
3422 } else if (bytes_needed
== 2) {
3424 op
= aco_opcode::buffer_load_ushort
;
3425 } else if (bytes_needed
<= 4) {
3427 op
= aco_opcode::buffer_load_dword
;
3428 } else if (bytes_needed
<= 8) {
3430 op
= aco_opcode::buffer_load_dwordx2
;
3431 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3433 op
= aco_opcode::buffer_load_dwordx3
;
3436 op
= aco_opcode::buffer_load_dwordx4
;
3438 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3439 mubuf
->operands
[0] = Operand(info
->resource
);
3440 mubuf
->operands
[1] = vaddr
;
3441 mubuf
->operands
[2] = soffset
;
3442 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3443 mubuf
->glc
= info
->glc
;
3444 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3445 mubuf
->barrier
= info
->barrier
;
3446 mubuf
->can_reorder
= info
->can_reorder
;
3447 mubuf
->offset
= const_offset
;
3448 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3449 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3450 mubuf
->definitions
[0] = Definition(val
);
3451 bld
.insert(std::move(mubuf
));
3456 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3458 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3460 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3461 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3463 if (addr
.type() == RegType::vgpr
)
3464 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3465 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3468 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3469 Temp offset
, unsigned bytes_needed
,
3470 unsigned align_
, unsigned const_offset
,
3473 unsigned bytes_size
= 0;
3474 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3475 bool global
= bld
.program
->chip_class
>= GFX9
;
3477 if (bytes_needed
== 1) {
3479 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3480 } else if (bytes_needed
== 2) {
3482 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3483 } else if (bytes_needed
<= 4) {
3485 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3486 } else if (bytes_needed
<= 8) {
3488 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3489 } else if (bytes_needed
<= 12 && !mubuf
) {
3491 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3494 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3496 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3497 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3499 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3500 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3501 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3502 mubuf
->operands
[2] = Operand(0u);
3503 mubuf
->glc
= info
->glc
;
3506 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3507 mubuf
->disable_wqm
= false;
3508 mubuf
->barrier
= info
->barrier
;
3509 mubuf
->definitions
[0] = Definition(val
);
3510 bld
.insert(std::move(mubuf
));
3512 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3514 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3515 flat
->operands
[0] = Operand(offset
);
3516 flat
->operands
[1] = Operand(s1
);
3517 flat
->glc
= info
->glc
;
3518 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3519 flat
->barrier
= info
->barrier
;
3521 flat
->definitions
[0] = Definition(val
);
3522 bld
.insert(std::move(flat
));
3528 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3530 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3531 Temp address
, unsigned base_offset
, unsigned align
)
3533 assert(util_is_power_of_two_nonzero(align
));
3535 Builder
bld(ctx
->program
, ctx
->block
);
3537 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3538 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3539 info
.align_mul
= align
;
3540 info
.align_offset
= 0;
3541 info
.barrier
= barrier_shared
;
3542 info
.can_reorder
= false;
3543 info
.const_offset
= base_offset
;
3544 emit_lds_load(ctx
, bld
, &info
);
3549 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3554 Builder
bld(ctx
->program
, ctx
->block
);
3556 ASSERTED
bool is_subdword
= false;
3557 for (unsigned i
= 0; i
< count
; i
++)
3558 is_subdword
|= offsets
[i
] % 4;
3559 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3560 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3562 /* count == 1 fast path */
3564 if (dst_type
== RegType::sgpr
)
3565 dst
[0] = bld
.as_uniform(src
);
3567 dst
[0] = as_vgpr(ctx
, src
);
3571 for (unsigned i
= 0; i
< count
- 1; i
++)
3572 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3573 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3575 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3576 src
= as_vgpr(ctx
, src
);
3578 /* use allocated_vec if possible */
3579 auto it
= ctx
->allocated_vec
.find(src
.id());
3580 if (it
!= ctx
->allocated_vec
.end()) {
3581 unsigned total_size
= 0;
3582 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3583 total_size
+= it
->second
[i
].bytes();
3584 if (total_size
!= src
.bytes())
3587 unsigned elem_size
= it
->second
[0].bytes();
3589 for (unsigned i
= 0; i
< count
; i
++) {
3590 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3594 for (unsigned i
= 0; i
< count
; i
++) {
3595 unsigned start_idx
= offsets
[i
] / elem_size
;
3596 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3597 if (op_count
== 1) {
3598 if (dst_type
== RegType::sgpr
)
3599 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3601 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3605 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3606 for (unsigned j
= 0; j
< op_count
; j
++) {
3607 Temp tmp
= it
->second
[start_idx
+ j
];
3608 if (dst_type
== RegType::sgpr
)
3609 tmp
= bld
.as_uniform(tmp
);
3610 vec
->operands
[j
] = Operand(tmp
);
3612 vec
->definitions
[0] = Definition(dst
[i
]);
3613 bld
.insert(std::move(vec
));
3619 if (dst_type
== RegType::sgpr
)
3620 src
= bld
.as_uniform(src
);
3624 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3625 split
->operands
[0] = Operand(src
);
3626 for (unsigned i
= 0; i
< count
; i
++)
3627 split
->definitions
[i
] = Definition(dst
[i
]);
3628 bld
.insert(std::move(split
));
3631 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3632 int *start
, int *count
)
3634 unsigned start_elem
= ffs(todo_mask
) - 1;
3635 bool skip
= !(mask
& (1 << start_elem
));
3637 mask
= ~mask
& todo_mask
;
3641 u_bit_scan_consecutive_range(&mask
, start
, count
);
3646 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3648 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3651 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3652 Temp address
, unsigned base_offset
, unsigned align
)
3654 assert(util_is_power_of_two_nonzero(align
));
3655 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3657 Builder
bld(ctx
->program
, ctx
->block
);
3658 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3659 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3661 unsigned write_count
= 0;
3662 Temp write_datas
[32];
3663 unsigned offsets
[32];
3664 aco_opcode opcodes
[32];
3666 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3668 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3671 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3672 offsets
[write_count
] = offset
;
3673 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3675 advance_write_mask(&todo
, offset
, bytes
);
3679 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3680 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3681 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3682 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3684 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3685 aco_opcode op
= aco_opcode::num_opcodes
;
3686 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3687 op
= aco_opcode::ds_write_b128
;
3689 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3690 op
= aco_opcode::ds_write_b96
;
3692 } else if (bytes
>= 8 && aligned8
) {
3693 op
= aco_opcode::ds_write_b64
;
3695 } else if (bytes
>= 4 && aligned4
) {
3696 op
= aco_opcode::ds_write_b32
;
3698 } else if (bytes
>= 2 && aligned2
) {
3699 op
= aco_opcode::ds_write_b16
;
3701 } else if (bytes
>= 1) {
3702 op
= aco_opcode::ds_write_b8
;
3708 offsets
[write_count
] = offset
;
3709 opcodes
[write_count
] = op
;
3711 advance_write_mask(&todo
, offset
, bytes
);
3714 Operand m
= load_lds_size_m0(bld
);
3716 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3718 for (unsigned i
= 0; i
< write_count
; i
++) {
3719 aco_opcode op
= opcodes
[i
];
3720 if (op
== aco_opcode::num_opcodes
)
3723 Temp data
= write_datas
[i
];
3725 unsigned second
= write_count
;
3726 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3727 for (second
= i
+ 1; second
< write_count
; second
++) {
3728 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3729 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3730 opcodes
[second
] = aco_opcode::num_opcodes
;
3736 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3737 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3739 unsigned inline_offset
= base_offset
+ offsets
[i
];
3740 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3741 Temp address_offset
= address
;
3742 if (inline_offset
> max_offset
) {
3743 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3744 inline_offset
= offsets
[i
];
3746 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3749 Temp second_data
= write_datas
[second
];
3750 inline_offset
/= data
.bytes();
3751 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3753 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3758 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3760 unsigned align
= 16;
3762 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3768 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3773 return aco_opcode::buffer_store_byte
;
3776 return aco_opcode::buffer_store_short
;
3778 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3780 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3783 return aco_opcode::buffer_store_dwordx3
;
3785 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3787 unreachable("Unexpected store size");
3788 return aco_opcode::num_opcodes
;
3791 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3792 Temp data
, unsigned writemask
, int swizzle_element_size
,
3793 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3795 unsigned write_count_with_skips
= 0;
3798 /* determine how to split the data */
3799 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3802 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3803 offsets
[write_count_with_skips
] = offset
;
3804 if (skips
[write_count_with_skips
]) {
3805 advance_write_mask(&todo
, offset
, bytes
);
3806 write_count_with_skips
++;
3810 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3811 * larger than swizzle_element_size */
3812 bytes
= MIN2(bytes
, swizzle_element_size
);
3814 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3816 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3817 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3820 /* dword or larger stores have to be dword-aligned */
3821 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3822 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3823 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3824 if (bytes
>= 4 && !dword_aligned
)
3825 bytes
= MIN2(bytes
, 2);
3827 advance_write_mask(&todo
, offset
, bytes
);
3828 write_count_with_skips
++;
3831 /* actually split data */
3832 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3835 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3838 write_datas
[*write_count
] = write_datas
[i
];
3839 offsets
[*write_count
] = offsets
[i
];
3844 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3845 unsigned split_cnt
= 0u, Temp dst
= Temp())
3847 Builder
bld(ctx
->program
, ctx
->block
);
3848 unsigned dword_size
= elem_size_bytes
/ 4;
3851 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3853 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3854 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3855 instr
->definitions
[0] = Definition(dst
);
3857 for (unsigned i
= 0; i
< cnt
; ++i
) {
3859 assert(arr
[i
].size() == dword_size
);
3860 allocated_vec
[i
] = arr
[i
];
3861 instr
->operands
[i
] = Operand(arr
[i
]);
3863 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3864 allocated_vec
[i
] = zero
;
3865 instr
->operands
[i
] = Operand(zero
);
3869 bld
.insert(std::move(instr
));
3872 emit_split_vector(ctx
, dst
, split_cnt
);
3874 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3879 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3881 if (const_offset
>= 4096) {
3882 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3883 const_offset
%= 4096u;
3886 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3887 else if (unlikely(voffset
.regClass() == s1
))
3888 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3889 else if (likely(voffset
.regClass() == v1
))
3890 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3892 unreachable("Unsupported register class of voffset");
3895 return const_offset
;
3898 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3899 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3902 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3903 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3905 Builder
bld(ctx
->program
, ctx
->block
);
3906 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3907 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3909 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3910 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3911 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3912 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3913 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3915 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3918 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3919 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3920 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3922 Builder
bld(ctx
->program
, ctx
->block
);
3923 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3925 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3927 unsigned write_count
= 0;
3928 Temp write_datas
[32];
3929 unsigned offsets
[32];
3930 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3931 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3933 for (unsigned i
= 0; i
< write_count
; i
++) {
3934 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3935 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3939 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3940 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3941 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3943 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3944 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3945 assert(!!stride
!= allow_combining
);
3947 Builder
bld(ctx
->program
, ctx
->block
);
3949 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3950 info
.component_stride
= allow_combining
? 0 : stride
;
3952 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3953 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3954 info
.align_offset
= 0;
3955 info
.soffset
= soffset
;
3956 info
.const_offset
= base_const_offset
;
3957 emit_mubuf_load(ctx
, bld
, &info
);
3960 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3962 Builder
bld(ctx
->program
, ctx
->block
);
3963 Temp offset
= base_offset
.first
;
3964 unsigned const_offset
= base_offset
.second
;
3966 if (!nir_src_is_const(*off_src
)) {
3967 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3970 /* Calculate indirect offset with stride */
3971 if (likely(indirect_offset_arg
.regClass() == v1
))
3972 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3973 else if (indirect_offset_arg
.regClass() == s1
)
3974 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3976 unreachable("Unsupported register class of indirect offset");
3978 /* Add to the supplied base offset */
3979 if (offset
.id() == 0)
3980 offset
= with_stride
;
3981 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3982 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3983 else if (offset
.size() == 1 && with_stride
.size() == 1)
3984 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3986 unreachable("Unsupported register class of indirect offset");
3988 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3989 const_offset
+= const_offset_arg
* stride
;
3992 return std::make_pair(offset
, const_offset
);
3995 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3997 Builder
bld(ctx
->program
, ctx
->block
);
4000 if (off1
.first
.id() && off2
.first
.id()) {
4001 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4002 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4003 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4004 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4006 unreachable("Unsupported register class of indirect offset");
4008 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4011 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4014 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4016 Builder
bld(ctx
->program
, ctx
->block
);
4017 unsigned const_offset
= offs
.second
* multiplier
;
4019 if (!offs
.first
.id())
4020 return std::make_pair(offs
.first
, const_offset
);
4022 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4023 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4024 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4026 return std::make_pair(offset
, const_offset
);
4029 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4031 Builder
bld(ctx
->program
, ctx
->block
);
4033 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4034 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4035 /* component is in bytes */
4036 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4038 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4039 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4040 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4043 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4045 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4048 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4050 Builder
bld(ctx
->program
, ctx
->block
);
4052 switch (ctx
->shader
->info
.stage
) {
4053 case MESA_SHADER_TESS_CTRL
:
4054 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4055 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4056 case MESA_SHADER_TESS_EVAL
:
4057 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4059 unreachable("Unsupported stage in get_tess_rel_patch_id");
4063 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4065 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4066 Builder
bld(ctx
->program
, ctx
->block
);
4068 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4069 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4071 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4073 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4074 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4076 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4077 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4078 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4080 return offset_mul(ctx
, offs
, 4u);
4083 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4085 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4086 Builder
bld(ctx
->program
, ctx
->block
);
4088 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4089 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4090 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4091 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4093 std::pair
<Temp
, unsigned> offs
= instr
4094 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4095 : std::make_pair(Temp(), 0u);
4097 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4098 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4103 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4104 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4106 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4107 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4109 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4110 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4116 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4118 Builder
bld(ctx
->program
, ctx
->block
);
4120 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4121 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4123 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4125 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4126 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4127 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4129 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4130 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4135 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4137 Builder
bld(ctx
->program
, ctx
->block
);
4139 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4140 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4141 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4142 unsigned attr_stride
= ctx
->tcs_num_patches
;
4144 std::pair
<Temp
, unsigned> offs
= instr
4145 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4146 : std::make_pair(Temp(), 0u);
4148 if (const_base_offset
)
4149 offs
.second
+= const_base_offset
* attr_stride
;
4151 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4152 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4153 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4158 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4160 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4165 unsigned drv_loc
= nir_intrinsic_base(instr
);
4166 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4168 if (!nir_src_is_const(*off_src
)) {
4174 uint64_t slot
= per_vertex
4175 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4176 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4177 return (((uint64_t) 1) << slot
) & mask
;
4180 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4182 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4183 unsigned component
= nir_intrinsic_component(instr
);
4184 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4186 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4187 if (off_instr
->type
!= nir_instr_type_load_const
)
4190 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4191 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4193 if (instr
->src
[0].ssa
->bit_size
== 64)
4194 write_mask
= widen_mask(write_mask
, 2);
4196 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4198 for (unsigned i
= 0; i
< 8; ++i
) {
4199 if (write_mask
& (1 << i
)) {
4200 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4201 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4209 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4211 /* Only TCS per-vertex inputs are supported by this function.
4212 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4214 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4217 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4218 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4219 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4220 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4221 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4222 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4227 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4228 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4229 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4234 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4236 Builder
bld(ctx
->program
, ctx
->block
);
4238 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4239 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4240 bool indirect_write
;
4241 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4242 if (temp_only_input
&& !indirect_write
)
4246 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4247 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4248 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4249 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4251 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4252 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4253 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4254 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4255 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4259 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4260 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4261 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4262 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4263 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4264 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4265 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4266 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4267 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4268 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4269 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4270 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4271 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4273 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4274 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4276 unreachable("Invalid LS or ES stage");
4279 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4280 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4281 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4285 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4290 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4291 return off
== ctx
->tcs_tess_lvl_out_loc
||
4292 off
== ctx
->tcs_tess_lvl_in_loc
;
4296 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4298 uint64_t mask
= per_vertex
4299 ? ctx
->program
->info
->tcs
.tes_inputs_read
4300 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4302 bool indirect_write
= false;
4303 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4304 return indirect_write
|| output_read_by_tes
;
4307 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4309 uint64_t mask
= per_vertex
4310 ? ctx
->shader
->info
.outputs_read
4311 : ctx
->shader
->info
.patch_outputs_read
;
4313 bool indirect_write
= false;
4314 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4315 return indirect_write
|| output_read
;
4318 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4320 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4321 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4323 Builder
bld(ctx
->program
, ctx
->block
);
4325 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4326 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4327 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4329 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4330 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4331 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4333 if (write_to_vmem
) {
4334 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4335 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4336 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4338 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4339 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4340 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4344 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4345 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4346 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4350 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4352 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4353 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4355 Builder
bld(ctx
->program
, ctx
->block
);
4357 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4358 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4359 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4360 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4362 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4365 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4367 if (ctx
->stage
== vertex_vs
||
4368 ctx
->stage
== tess_eval_vs
||
4369 ctx
->stage
== fragment_fs
||
4370 ctx
->stage
== ngg_vertex_gs
||
4371 ctx
->stage
== ngg_tess_eval_gs
||
4372 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4373 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4374 if (!stored_to_temps
) {
4375 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4376 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4377 fprintf(stderr
, "\n");
4380 } else if (ctx
->stage
== vertex_es
||
4381 ctx
->stage
== vertex_ls
||
4382 ctx
->stage
== tess_eval_es
||
4383 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4384 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4385 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4386 visit_store_ls_or_es_output(ctx
, instr
);
4387 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4388 visit_store_tcs_output(ctx
, instr
, false);
4390 unreachable("Shader stage not implemented");
4394 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4396 visit_load_tcs_output(ctx
, instr
, false);
4399 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4401 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4402 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4404 Builder
bld(ctx
->program
, ctx
->block
);
4406 if (dst
.regClass() == v2b
) {
4407 if (ctx
->program
->has_16bank_lds
) {
4408 assert(ctx
->options
->chip_class
<= GFX8
);
4409 Builder::Result interp_p1
=
4410 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4411 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4412 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4413 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4414 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4415 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4417 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4419 if (ctx
->options
->chip_class
== GFX8
)
4420 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4422 Builder::Result interp_p1
=
4423 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4424 coord1
, bld
.m0(prim_mask
), idx
, component
);
4425 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4426 interp_p1
, idx
, component
);
4429 Builder::Result interp_p1
=
4430 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4431 bld
.m0(prim_mask
), idx
, component
);
4433 if (ctx
->program
->has_16bank_lds
)
4434 interp_p1
.instr
->operands
[0].setLateKill(true);
4436 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4437 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4441 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4443 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4444 for (unsigned i
= 0; i
< num_components
; i
++)
4445 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4446 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4447 assert(num_components
== 4);
4448 Builder
bld(ctx
->program
, ctx
->block
);
4449 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4452 for (Operand
& op
: vec
->operands
)
4453 op
= op
.isUndefined() ? Operand(0u) : op
;
4455 vec
->definitions
[0] = Definition(dst
);
4456 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4457 emit_split_vector(ctx
, dst
, num_components
);
4461 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4463 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4464 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4465 unsigned idx
= nir_intrinsic_base(instr
);
4466 unsigned component
= nir_intrinsic_component(instr
);
4467 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4469 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4471 assert(offset
->u32
== 0);
4473 /* the lower 15bit of the prim_mask contain the offset into LDS
4474 * while the upper bits contain the number of prims */
4475 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4476 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4477 Builder
bld(ctx
->program
, ctx
->block
);
4478 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4479 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4480 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4481 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4482 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4485 if (instr
->dest
.ssa
.num_components
== 1) {
4486 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4488 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4489 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4491 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4492 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4493 vec
->operands
[i
] = Operand(tmp
);
4495 vec
->definitions
[0] = Definition(dst
);
4496 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4500 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4501 unsigned offset
, unsigned stride
, unsigned channels
)
4503 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4504 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4506 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4507 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4510 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4511 unsigned offset
, unsigned stride
, unsigned *channels
)
4513 if (!vtx_info
->chan_byte_size
) {
4514 *channels
= vtx_info
->num_channels
;
4515 return vtx_info
->chan_format
;
4518 unsigned num_channels
= *channels
;
4519 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4520 unsigned new_channels
= num_channels
+ 1;
4521 /* first, assume more loads is worse and try using a larger data format */
4522 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4524 /* don't make the attribute potentially out-of-bounds */
4525 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4529 if (new_channels
== 5) {
4530 /* then try decreasing load size (at the cost of more loads) */
4531 new_channels
= *channels
;
4532 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4536 if (new_channels
< *channels
)
4537 *channels
= new_channels
;
4538 num_channels
= new_channels
;
4541 switch (vtx_info
->chan_format
) {
4542 case V_008F0C_BUF_DATA_FORMAT_8
:
4543 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4544 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4545 case V_008F0C_BUF_DATA_FORMAT_16
:
4546 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4547 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4548 case V_008F0C_BUF_DATA_FORMAT_32
:
4549 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4550 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4552 unreachable("shouldn't reach here");
4553 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4556 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4557 * so we may need to fix it up. */
4558 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4560 Builder
bld(ctx
->program
, ctx
->block
);
4562 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4563 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4565 /* For the integer-like cases, do a natural sign extension.
4567 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4568 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4571 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4572 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4574 /* Convert back to the right type. */
4575 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4576 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4577 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4578 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4579 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4580 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4586 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4588 Builder
bld(ctx
->program
, ctx
->block
);
4589 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4590 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4592 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4593 if (off_instr
->type
!= nir_instr_type_load_const
) {
4594 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4595 nir_print_instr(off_instr
, stderr
);
4596 fprintf(stderr
, "\n");
4598 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4600 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4602 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4603 unsigned component
= nir_intrinsic_component(instr
);
4604 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4605 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4606 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4607 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4608 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4610 unsigned dfmt
= attrib_format
& 0xf;
4611 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4612 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4614 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4615 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4616 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4617 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4619 num_channels
= MAX2(num_channels
, 3);
4621 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4622 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4625 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4626 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4627 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4629 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4631 Temp divided
= bld
.tmp(v1
);
4632 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4633 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4635 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4638 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4641 index
= bld
.vadd32(bld
.def(v1
),
4642 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4643 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4646 Temp channels
[num_channels
];
4647 unsigned channel_start
= 0;
4648 bool direct_fetch
= false;
4650 /* skip unused channels at the start */
4651 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4652 channel_start
= ffs(mask
) - 1;
4653 for (unsigned i
= 0; i
< channel_start
; i
++)
4654 channels
[i
] = Temp(0, s1
);
4655 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4656 num_channels
= 3 - (ffs(mask
) - 1);
4660 while (channel_start
< num_channels
) {
4661 unsigned fetch_component
= num_channels
- channel_start
;
4662 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4663 bool expanded
= false;
4665 /* use MUBUF when possible to avoid possible alignment issues */
4666 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4667 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4668 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4669 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4670 vtx_info
->chan_byte_size
== 4;
4671 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4673 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4675 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4676 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4677 fetch_component
= 4;
4682 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4684 Temp fetch_index
= index
;
4685 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4686 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4687 fetch_offset
= fetch_offset
% attrib_stride
;
4690 Operand
soffset(0u);
4691 if (fetch_offset
>= 4096) {
4692 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4693 fetch_offset
%= 4096;
4697 switch (fetch_bytes
) {
4699 assert(!use_mubuf
&& bitsize
== 16);
4700 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4703 if (bitsize
== 16) {
4705 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4707 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4711 assert(!use_mubuf
&& bitsize
== 16);
4712 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4715 if (bitsize
== 16) {
4717 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4719 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4723 assert(ctx
->options
->chip_class
>= GFX7
||
4724 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4725 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4728 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4731 unreachable("Unimplemented load_input vector size");
4735 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4736 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4737 num_channels
<= 3)) {
4738 direct_fetch
= true;
4741 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4745 Instruction
*mubuf
= bld
.mubuf(opcode
,
4746 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4747 fetch_offset
, false, true).instr
;
4748 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4750 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4751 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4752 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4753 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4756 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4758 if (fetch_component
== 1) {
4759 channels
[channel_start
] = fetch_dst
;
4761 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4762 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4763 bitsize
== 16 ? v2b
: v1
);
4766 channel_start
+= fetch_component
;
4769 if (!direct_fetch
) {
4770 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4771 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4773 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4774 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4775 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4777 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4778 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4779 unsigned num_temp
= 0;
4780 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4781 unsigned idx
= i
+ component
;
4782 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4783 Temp channel
= channels
[swizzle
[idx
]];
4784 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4785 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4786 vec
->operands
[i
] = Operand(channel
);
4790 } else if (is_float
&& idx
== 3) {
4791 vec
->operands
[i
] = Operand(0x3f800000u
);
4792 } else if (!is_float
&& idx
== 3) {
4793 vec
->operands
[i
] = Operand(1u);
4795 vec
->operands
[i
] = Operand(0u);
4798 vec
->definitions
[0] = Definition(dst
);
4799 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4800 emit_split_vector(ctx
, dst
, dst
.size());
4802 if (num_temp
== dst
.size())
4803 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4805 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4806 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4807 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4808 if (off_instr
->type
!= nir_instr_type_load_const
||
4809 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4810 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4811 nir_print_instr(off_instr
, stderr
);
4812 fprintf(stderr
, "\n");
4815 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4816 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4818 assert(offset
->u32
== 0);
4820 /* the lower 15bit of the prim_mask contain the offset into LDS
4821 * while the upper bits contain the number of prims */
4822 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4823 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4824 Builder
bld(ctx
->program
, ctx
->block
);
4825 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4826 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4827 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4828 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4829 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4832 unsigned idx
= nir_intrinsic_base(instr
);
4833 unsigned component
= nir_intrinsic_component(instr
);
4834 unsigned vertex_id
= 2; /* P0 */
4836 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4837 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4838 switch (src0
->u32
) {
4840 vertex_id
= 2; /* P0 */
4843 vertex_id
= 0; /* P10 */
4846 vertex_id
= 1; /* P20 */
4849 unreachable("invalid vertex index");
4853 if (dst
.size() == 1) {
4854 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4856 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4857 for (unsigned i
= 0; i
< dst
.size(); i
++)
4858 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4859 vec
->definitions
[0] = Definition(dst
);
4860 bld
.insert(std::move(vec
));
4863 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4864 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4865 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4866 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4867 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4869 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4871 unreachable("Shader stage not implemented");
4875 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4877 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4879 Builder
bld(ctx
->program
, ctx
->block
);
4880 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4883 if (!nir_src_is_const(*vertex_src
)) {
4884 /* better code could be created, but this case probably doesn't happen
4885 * much in practice */
4886 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4887 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4890 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4891 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4893 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4895 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4898 if (vertex_offset
.id()) {
4899 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4900 Operand(i
), indirect_vertex
);
4901 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4903 vertex_offset
= elem
;
4907 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4908 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4910 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4911 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4912 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4913 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4914 Operand((vertex
% 2u) * 16u), Operand(16u));
4916 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4919 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4920 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4921 return offset_mul(ctx
, offs
, 4u);
4924 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4926 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4928 Builder
bld(ctx
->program
, ctx
->block
);
4929 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4930 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4932 if (ctx
->stage
== geometry_gs
) {
4933 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4934 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4935 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4936 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4937 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4938 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4939 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4941 unreachable("Unsupported GS stage.");
4945 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4947 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4949 Builder
bld(ctx
->program
, ctx
->block
);
4950 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4952 if (load_input_from_temps(ctx
, instr
, dst
))
4955 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4956 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4957 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4959 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4962 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4964 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4966 Builder
bld(ctx
->program
, ctx
->block
);
4968 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4969 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4970 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4972 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4973 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4975 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4978 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4980 switch (ctx
->shader
->info
.stage
) {
4981 case MESA_SHADER_GEOMETRY
:
4982 visit_load_gs_per_vertex_input(ctx
, instr
);
4984 case MESA_SHADER_TESS_CTRL
:
4985 visit_load_tcs_per_vertex_input(ctx
, instr
);
4987 case MESA_SHADER_TESS_EVAL
:
4988 visit_load_tes_per_vertex_input(ctx
, instr
);
4991 unreachable("Unimplemented shader stage");
4995 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4997 visit_load_tcs_output(ctx
, instr
, true);
5000 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5002 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5003 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5005 visit_store_tcs_output(ctx
, instr
, true);
5008 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5010 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5012 Builder
bld(ctx
->program
, ctx
->block
);
5013 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5015 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5016 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5019 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5020 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5021 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5022 tes_w
= Operand(tmp
);
5025 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5026 emit_split_vector(ctx
, tess_coord
, 3);
5029 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5031 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5032 Builder
bld(ctx
->program
, ctx
->block
);
5033 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5034 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5035 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5038 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5042 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5044 Builder
bld(ctx
->program
, ctx
->block
);
5045 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5046 if (!nir_dest_is_divergent(instr
->dest
))
5047 index
= bld
.as_uniform(index
);
5048 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5049 unsigned binding
= nir_intrinsic_binding(instr
);
5052 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5053 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5054 unsigned offset
= layout
->binding
[binding
].offset
;
5056 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5057 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5058 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5059 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5060 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5063 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5064 stride
= layout
->binding
[binding
].size
;
5067 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5068 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5070 if (nir_const_index
) {
5071 const_index
= const_index
* stride
;
5072 } else if (index
.type() == RegType::vgpr
) {
5073 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5074 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5076 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5080 if (nir_const_index
) {
5081 const_index
= const_index
+ offset
;
5082 } else if (index
.type() == RegType::vgpr
) {
5083 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5085 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5089 if (nir_const_index
&& const_index
== 0) {
5091 } else if (index
.type() == RegType::vgpr
) {
5092 index
= bld
.vadd32(bld
.def(v1
),
5093 nir_const_index
? Operand(const_index
) : Operand(index
),
5096 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5097 nir_const_index
? Operand(const_index
) : Operand(index
),
5101 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5104 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5105 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5106 bool glc
=false, bool readonly
=true)
5108 Builder
bld(ctx
->program
, ctx
->block
);
5110 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5112 offset
= bld
.as_uniform(offset
);
5114 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5116 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5117 info
.can_reorder
= readonly
;
5118 info
.align_mul
= align_mul
;
5119 info
.align_offset
= align_offset
;
5121 emit_smem_load(ctx
, bld
, &info
);
5123 emit_mubuf_load(ctx
, bld
, &info
);
5126 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5128 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5129 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5131 Builder
bld(ctx
->program
, ctx
->block
);
5133 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5134 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5135 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5136 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5138 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5139 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5140 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5141 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5142 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5143 if (ctx
->options
->chip_class
>= GFX10
) {
5144 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5145 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5146 S_008F0C_RESOURCE_LEVEL(1);
5148 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5149 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5151 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5152 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5153 Operand(0xFFFFFFFFu
),
5154 Operand(desc_type
));
5155 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5156 rsrc
, upper_dwords
);
5158 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5159 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5161 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5162 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5163 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5166 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5168 Builder
bld(ctx
->program
, ctx
->block
);
5169 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5170 unsigned offset
= nir_intrinsic_base(instr
);
5171 unsigned count
= instr
->dest
.ssa
.num_components
;
5172 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5174 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5175 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5176 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5177 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5178 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5179 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5180 for (unsigned i
= 0; i
< count
; ++i
) {
5181 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5182 vec
->operands
[i
] = Operand
{elems
[i
]};
5184 vec
->definitions
[0] = Definition(dst
);
5185 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5186 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5191 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5192 if (offset
!= 0) // TODO check if index != 0 as well
5193 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5194 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5197 bool aligned
= true;
5199 if (instr
->dest
.ssa
.bit_size
== 8) {
5200 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5201 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5203 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5204 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5205 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5207 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5212 switch (vec
.size()) {
5214 op
= aco_opcode::s_load_dword
;
5217 op
= aco_opcode::s_load_dwordx2
;
5223 op
= aco_opcode::s_load_dwordx4
;
5229 op
= aco_opcode::s_load_dwordx8
;
5232 unreachable("unimplemented or forbidden load_push_constant.");
5235 bld
.smem(op
, Definition(vec
), ptr
, index
);
5238 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5239 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5244 emit_split_vector(ctx
, vec
, 4);
5245 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5246 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5247 emit_extract_vector(ctx
, vec
, 0, rc
),
5248 emit_extract_vector(ctx
, vec
, 1, rc
),
5249 emit_extract_vector(ctx
, vec
, 2, rc
));
5252 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5255 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5257 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5259 Builder
bld(ctx
->program
, ctx
->block
);
5261 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5262 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5263 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5264 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5265 if (ctx
->options
->chip_class
>= GFX10
) {
5266 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5267 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5268 S_008F0C_RESOURCE_LEVEL(1);
5270 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5271 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5274 unsigned base
= nir_intrinsic_base(instr
);
5275 unsigned range
= nir_intrinsic_range(instr
);
5277 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5278 if (base
&& offset
.type() == RegType::sgpr
)
5279 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5280 else if (base
&& offset
.type() == RegType::vgpr
)
5281 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5283 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5284 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5285 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5286 Operand(desc_type
));
5287 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5288 // TODO: get alignment information for subdword constants
5289 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5292 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5294 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5295 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5297 ctx
->program
->needs_exact
= true;
5299 // TODO: optimize uniform conditions
5300 Builder
bld(ctx
->program
, ctx
->block
);
5301 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5302 assert(src
.regClass() == bld
.lm
);
5303 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5304 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5305 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5309 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5311 Builder
bld(ctx
->program
, ctx
->block
);
5313 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5314 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5316 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5317 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5319 if (ctx
->block
->loop_nest_depth
&&
5320 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5321 /* we handle discards the same way as jump instructions */
5322 append_logical_end(ctx
->block
);
5324 /* in loops, discard behaves like break */
5325 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5326 ctx
->block
->kind
|= block_kind_discard
;
5329 /* uniform discard - loop ends here */
5330 assert(nir_instr_is_last(&instr
->instr
));
5331 ctx
->block
->kind
|= block_kind_uniform
;
5332 ctx
->cf_info
.has_branch
= true;
5333 bld
.branch(aco_opcode::p_branch
);
5334 add_linear_edge(ctx
->block
->index
, linear_target
);
5338 /* we add a break right behind the discard() instructions */
5339 ctx
->block
->kind
|= block_kind_break
;
5340 unsigned idx
= ctx
->block
->index
;
5342 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5343 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5345 /* remove critical edges from linear CFG */
5346 bld
.branch(aco_opcode::p_branch
);
5347 Block
* break_block
= ctx
->program
->create_and_insert_block();
5348 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5349 break_block
->kind
|= block_kind_uniform
;
5350 add_linear_edge(idx
, break_block
);
5351 add_linear_edge(break_block
->index
, linear_target
);
5352 bld
.reset(break_block
);
5353 bld
.branch(aco_opcode::p_branch
);
5355 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5356 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5357 add_linear_edge(idx
, continue_block
);
5358 append_logical_start(continue_block
);
5359 ctx
->block
= continue_block
;
5364 /* it can currently happen that NIR doesn't remove the unreachable code */
5365 if (!nir_instr_is_last(&instr
->instr
)) {
5366 ctx
->program
->needs_exact
= true;
5367 /* save exec somewhere temporarily so that it doesn't get
5368 * overwritten before the discard from outer exec masks */
5369 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5370 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5371 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5375 /* This condition is incorrect for uniformly branched discards in a loop
5376 * predicated by a divergent condition, but the above code catches that case
5377 * and the discard would end up turning into a discard_if.
5387 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5388 /* program just ends here */
5389 ctx
->block
->kind
|= block_kind_uniform
;
5390 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5391 0 /* enabled mask */, 9 /* dest */,
5392 false /* compressed */, true/* done */, true /* valid mask */);
5393 bld
.sopp(aco_opcode::s_endpgm
);
5394 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5396 ctx
->block
->kind
|= block_kind_discard
;
5397 /* branch and linear edge is added by visit_if() */
5401 enum aco_descriptor_type
{
5412 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5413 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5415 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5416 return dim
== ac_image_cube
||
5417 dim
== ac_image_1darray
||
5418 dim
== ac_image_2darray
||
5419 dim
== ac_image_2darraymsaa
;
5422 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5423 enum aco_descriptor_type desc_type
,
5424 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5426 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5427 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5428 if (it != ctx->tex_desc.end())
5431 Temp index
= Temp();
5432 bool index_set
= false;
5433 unsigned constant_index
= 0;
5434 unsigned descriptor_set
;
5435 unsigned base_index
;
5436 Builder
bld(ctx
->program
, ctx
->block
);
5439 assert(tex_instr
&& !image
);
5441 base_index
= tex_instr
->sampler_index
;
5443 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5444 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5448 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5449 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5451 constant_index
+= array_size
* const_value
->u32
;
5453 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5454 if (indirect
.type() == RegType::vgpr
)
5455 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5457 if (array_size
!= 1)
5458 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5464 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5468 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5470 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5471 base_index
= deref_instr
->var
->data
.binding
;
5474 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5475 list
= convert_pointer_to_64_bit(ctx
, list
);
5477 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5478 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5479 unsigned offset
= binding
->offset
;
5480 unsigned stride
= binding
->size
;
5484 assert(base_index
< layout
->binding_count
);
5486 switch (desc_type
) {
5487 case ACO_DESC_IMAGE
:
5489 opcode
= aco_opcode::s_load_dwordx8
;
5491 case ACO_DESC_FMASK
:
5493 opcode
= aco_opcode::s_load_dwordx8
;
5496 case ACO_DESC_SAMPLER
:
5498 opcode
= aco_opcode::s_load_dwordx4
;
5499 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5500 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5502 case ACO_DESC_BUFFER
:
5504 opcode
= aco_opcode::s_load_dwordx4
;
5506 case ACO_DESC_PLANE_0
:
5507 case ACO_DESC_PLANE_1
:
5509 opcode
= aco_opcode::s_load_dwordx8
;
5510 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5512 case ACO_DESC_PLANE_2
:
5514 opcode
= aco_opcode::s_load_dwordx4
;
5518 unreachable("invalid desc_type\n");
5521 offset
+= constant_index
* stride
;
5523 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5524 (!index_set
|| binding
->immutable_samplers_equal
)) {
5525 if (binding
->immutable_samplers_equal
)
5528 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5529 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5530 Operand(samplers
[constant_index
* 4 + 0]),
5531 Operand(samplers
[constant_index
* 4 + 1]),
5532 Operand(samplers
[constant_index
* 4 + 2]),
5533 Operand(samplers
[constant_index
* 4 + 3]));
5538 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5540 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5541 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5544 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5546 if (desc_type
== ACO_DESC_PLANE_2
) {
5548 for (unsigned i
= 0; i
< 8; i
++)
5549 components
[i
] = bld
.tmp(s1
);
5550 bld
.pseudo(aco_opcode::p_split_vector
,
5551 Definition(components
[0]),
5552 Definition(components
[1]),
5553 Definition(components
[2]),
5554 Definition(components
[3]),
5557 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5558 bld
.pseudo(aco_opcode::p_split_vector
,
5559 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5560 Definition(components
[4]),
5561 Definition(components
[5]),
5562 Definition(components
[6]),
5563 Definition(components
[7]),
5566 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5567 components
[0], components
[1], components
[2], components
[3],
5568 components
[4], components
[5], components
[6], components
[7]);
5574 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5577 case GLSL_SAMPLER_DIM_BUF
:
5579 case GLSL_SAMPLER_DIM_1D
:
5580 return array
? 2 : 1;
5581 case GLSL_SAMPLER_DIM_2D
:
5582 return array
? 3 : 2;
5583 case GLSL_SAMPLER_DIM_MS
:
5584 return array
? 4 : 3;
5585 case GLSL_SAMPLER_DIM_3D
:
5586 case GLSL_SAMPLER_DIM_CUBE
:
5588 case GLSL_SAMPLER_DIM_RECT
:
5589 case GLSL_SAMPLER_DIM_SUBPASS
:
5591 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5600 /* Adjust the sample index according to FMASK.
5602 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5603 * which is the identity mapping. Each nibble says which physical sample
5604 * should be fetched to get that sample.
5606 * For example, 0x11111100 means there are only 2 samples stored and
5607 * the second sample covers 3/4 of the pixel. When reading samples 0
5608 * and 1, return physical sample 0 (determined by the first two 0s
5609 * in FMASK), otherwise return physical sample 1.
5611 * The sample index should be adjusted as follows:
5612 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5614 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5616 Builder
bld(ctx
->program
, ctx
->block
);
5617 Temp fmask
= bld
.tmp(v1
);
5618 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5619 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5622 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5623 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5624 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5625 load
->operands
[0] = Operand(fmask_desc_ptr
);
5626 load
->operands
[1] = Operand(s4
); /* no sampler */
5627 load
->operands
[2] = Operand(coord
);
5628 load
->definitions
[0] = Definition(fmask
);
5635 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5636 ctx
->block
->instructions
.emplace_back(std::move(load
));
5638 Operand sample_index4
;
5639 if (sample_index
.isConstant()) {
5640 if (sample_index
.constantValue() < 16) {
5641 sample_index4
= Operand(sample_index
.constantValue() << 2);
5643 sample_index4
= Operand(0u);
5645 } else if (sample_index
.regClass() == s1
) {
5646 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5648 assert(sample_index
.regClass() == v1
);
5649 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5653 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5654 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5655 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5656 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5658 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5660 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5661 * resource descriptor is 0 (invalid),
5663 Temp compare
= bld
.tmp(bld
.lm
);
5664 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5665 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5667 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5669 /* Replace the MSAA sample index. */
5670 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5673 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5676 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5677 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5678 bool is_array
= glsl_sampler_type_is_array(type
);
5679 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5680 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5681 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5682 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5683 int count
= image_type_to_components_count(dim
, is_array
);
5684 std::vector
<Temp
> coords(count
);
5685 Builder
bld(ctx
->program
, ctx
->block
);
5689 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5690 /* get sample index */
5691 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5692 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5693 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5694 std::vector
<Temp
> fmask_load_address
;
5695 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5696 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5698 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5699 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5701 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5706 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5707 coords
.resize(coords
.size() + 1);
5708 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5710 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5712 for (int i
= 0; i
< count
; i
++)
5713 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5716 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5717 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5718 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5719 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5722 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5725 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5726 for (unsigned i
= 0; i
< coords
.size(); i
++)
5727 vec
->operands
[i
] = Operand(coords
[i
]);
5728 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5729 vec
->definitions
[0] = Definition(res
);
5730 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5735 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5737 Builder
bld(ctx
->program
, ctx
->block
);
5738 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5739 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5740 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5741 bool is_array
= glsl_sampler_type_is_array(type
);
5742 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5744 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5745 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5746 unsigned num_channels
= util_last_bit(mask
);
5747 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5748 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5751 switch (num_channels
) {
5753 opcode
= aco_opcode::buffer_load_format_x
;
5756 opcode
= aco_opcode::buffer_load_format_xy
;
5759 opcode
= aco_opcode::buffer_load_format_xyz
;
5762 opcode
= aco_opcode::buffer_load_format_xyzw
;
5765 unreachable(">4 channel buffer image load");
5767 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5768 load
->operands
[0] = Operand(rsrc
);
5769 load
->operands
[1] = Operand(vindex
);
5770 load
->operands
[2] = Operand((uint32_t) 0);
5772 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5775 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5776 load
->definitions
[0] = Definition(tmp
);
5778 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5779 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5780 load
->barrier
= barrier_image
;
5781 ctx
->block
->instructions
.emplace_back(std::move(load
));
5783 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5787 Temp coords
= get_image_coords(ctx
, instr
, type
);
5788 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5790 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5791 unsigned num_components
= util_bitcount(dmask
);
5793 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5796 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5798 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5799 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5801 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5802 load
->operands
[0] = Operand(resource
);
5803 load
->operands
[1] = Operand(s4
); /* no sampler */
5804 load
->operands
[2] = Operand(coords
);
5805 load
->definitions
[0] = Definition(tmp
);
5806 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5807 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5808 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5809 load
->dmask
= dmask
;
5811 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5812 load
->barrier
= barrier_image
;
5813 ctx
->block
->instructions
.emplace_back(std::move(load
));
5815 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5819 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5821 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5822 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5823 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5824 bool is_array
= glsl_sampler_type_is_array(type
);
5825 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5827 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5829 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5830 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5831 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5833 switch (data
.size()) {
5835 opcode
= aco_opcode::buffer_store_format_x
;
5838 opcode
= aco_opcode::buffer_store_format_xy
;
5841 opcode
= aco_opcode::buffer_store_format_xyz
;
5844 opcode
= aco_opcode::buffer_store_format_xyzw
;
5847 unreachable(">4 channel buffer image store");
5849 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5850 store
->operands
[0] = Operand(rsrc
);
5851 store
->operands
[1] = Operand(vindex
);
5852 store
->operands
[2] = Operand((uint32_t) 0);
5853 store
->operands
[3] = Operand(data
);
5854 store
->idxen
= true;
5857 store
->disable_wqm
= true;
5858 store
->barrier
= barrier_image
;
5859 ctx
->program
->needs_exact
= true;
5860 ctx
->block
->instructions
.emplace_back(std::move(store
));
5864 assert(data
.type() == RegType::vgpr
);
5865 Temp coords
= get_image_coords(ctx
, instr
, type
);
5866 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5868 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5869 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5871 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5872 store
->operands
[0] = Operand(resource
);
5873 store
->operands
[1] = Operand(data
);
5874 store
->operands
[2] = Operand(coords
);
5877 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5878 store
->dmask
= (1 << data
.size()) - 1;
5880 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5881 store
->disable_wqm
= true;
5882 store
->barrier
= barrier_image
;
5883 ctx
->program
->needs_exact
= true;
5884 ctx
->block
->instructions
.emplace_back(std::move(store
));
5888 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5890 /* return the previous value if dest is ever used */
5891 bool return_previous
= false;
5892 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5893 return_previous
= true;
5896 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5897 return_previous
= true;
5901 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5902 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5903 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5904 bool is_array
= glsl_sampler_type_is_array(type
);
5905 Builder
bld(ctx
->program
, ctx
->block
);
5907 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5908 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5910 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5911 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5913 aco_opcode buf_op
, image_op
;
5914 switch (instr
->intrinsic
) {
5915 case nir_intrinsic_image_deref_atomic_add
:
5916 buf_op
= aco_opcode::buffer_atomic_add
;
5917 image_op
= aco_opcode::image_atomic_add
;
5919 case nir_intrinsic_image_deref_atomic_umin
:
5920 buf_op
= aco_opcode::buffer_atomic_umin
;
5921 image_op
= aco_opcode::image_atomic_umin
;
5923 case nir_intrinsic_image_deref_atomic_imin
:
5924 buf_op
= aco_opcode::buffer_atomic_smin
;
5925 image_op
= aco_opcode::image_atomic_smin
;
5927 case nir_intrinsic_image_deref_atomic_umax
:
5928 buf_op
= aco_opcode::buffer_atomic_umax
;
5929 image_op
= aco_opcode::image_atomic_umax
;
5931 case nir_intrinsic_image_deref_atomic_imax
:
5932 buf_op
= aco_opcode::buffer_atomic_smax
;
5933 image_op
= aco_opcode::image_atomic_smax
;
5935 case nir_intrinsic_image_deref_atomic_and
:
5936 buf_op
= aco_opcode::buffer_atomic_and
;
5937 image_op
= aco_opcode::image_atomic_and
;
5939 case nir_intrinsic_image_deref_atomic_or
:
5940 buf_op
= aco_opcode::buffer_atomic_or
;
5941 image_op
= aco_opcode::image_atomic_or
;
5943 case nir_intrinsic_image_deref_atomic_xor
:
5944 buf_op
= aco_opcode::buffer_atomic_xor
;
5945 image_op
= aco_opcode::image_atomic_xor
;
5947 case nir_intrinsic_image_deref_atomic_exchange
:
5948 buf_op
= aco_opcode::buffer_atomic_swap
;
5949 image_op
= aco_opcode::image_atomic_swap
;
5951 case nir_intrinsic_image_deref_atomic_comp_swap
:
5952 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5953 image_op
= aco_opcode::image_atomic_cmpswap
;
5956 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5959 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5961 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5962 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5963 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5964 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5965 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5966 mubuf
->operands
[0] = Operand(resource
);
5967 mubuf
->operands
[1] = Operand(vindex
);
5968 mubuf
->operands
[2] = Operand((uint32_t)0);
5969 mubuf
->operands
[3] = Operand(data
);
5970 if (return_previous
)
5971 mubuf
->definitions
[0] = Definition(dst
);
5973 mubuf
->idxen
= true;
5974 mubuf
->glc
= return_previous
;
5975 mubuf
->dlc
= false; /* Not needed for atomics */
5976 mubuf
->disable_wqm
= true;
5977 mubuf
->barrier
= barrier_image
;
5978 ctx
->program
->needs_exact
= true;
5979 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5983 Temp coords
= get_image_coords(ctx
, instr
, type
);
5984 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5985 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5986 mimg
->operands
[0] = Operand(resource
);
5987 mimg
->operands
[1] = Operand(data
);
5988 mimg
->operands
[2] = Operand(coords
);
5989 if (return_previous
)
5990 mimg
->definitions
[0] = Definition(dst
);
5991 mimg
->glc
= return_previous
;
5992 mimg
->dlc
= false; /* Not needed for atomics */
5993 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5994 mimg
->dmask
= (1 << data
.size()) - 1;
5996 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5997 mimg
->disable_wqm
= true;
5998 mimg
->barrier
= barrier_image
;
5999 ctx
->program
->needs_exact
= true;
6000 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6004 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6006 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6007 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6008 Builder
bld(ctx
->program
, ctx
->block
);
6010 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6012 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6013 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6015 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6016 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6018 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6019 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6021 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6022 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6023 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6024 if (dst
.type() == RegType::vgpr
)
6025 bld
.copy(Definition(dst
), shr_dst
);
6027 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6029 emit_extract_vector(ctx
, desc
, 2, dst
);
6033 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6035 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6036 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6037 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6038 bool is_array
= glsl_sampler_type_is_array(type
);
6039 Builder
bld(ctx
->program
, ctx
->block
);
6041 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6042 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6043 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6047 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6050 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6052 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6054 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6055 mimg
->operands
[0] = Operand(resource
);
6056 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6057 mimg
->operands
[2] = Operand(lod
);
6058 uint8_t& dmask
= mimg
->dmask
;
6059 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6060 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6061 mimg
->da
= glsl_sampler_type_is_array(type
);
6062 mimg
->can_reorder
= true;
6063 Definition
& def
= mimg
->definitions
[0];
6064 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6066 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6067 glsl_sampler_type_is_array(type
)) {
6069 assert(instr
->dest
.ssa
.num_components
== 3);
6070 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6071 def
= Definition(tmp
);
6072 emit_split_vector(ctx
, tmp
, 3);
6074 /* divide 3rd value by 6 by multiplying with magic number */
6075 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6076 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6078 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6079 emit_extract_vector(ctx
, tmp
, 0, v1
),
6080 emit_extract_vector(ctx
, tmp
, 1, v1
),
6083 } else if (ctx
->options
->chip_class
== GFX9
&&
6084 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6085 glsl_sampler_type_is_array(type
)) {
6086 assert(instr
->dest
.ssa
.num_components
== 2);
6087 def
= Definition(dst
);
6090 def
= Definition(dst
);
6093 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6096 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6098 Builder
bld(ctx
->program
, ctx
->block
);
6099 unsigned num_components
= instr
->num_components
;
6101 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6102 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6103 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6105 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6106 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6107 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6108 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6111 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6113 Builder
bld(ctx
->program
, ctx
->block
);
6114 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6115 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6116 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6117 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6119 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6120 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6122 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6123 ctx
->options
->chip_class
>= GFX8
&&
6124 elem_size_bytes
>= 4;
6126 offset
= bld
.as_uniform(offset
);
6127 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6129 unsigned write_count
= 0;
6130 Temp write_datas
[32];
6131 unsigned offsets
[32];
6132 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6133 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6135 for (unsigned i
= 0; i
< write_count
; i
++) {
6136 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6137 if (smem
&& ctx
->stage
== fragment_fs
)
6138 op
= aco_opcode::p_fs_buffer_store_smem
;
6141 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6142 store
->operands
[0] = Operand(rsrc
);
6144 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6145 offset
, Operand(offsets
[i
]));
6146 store
->operands
[1] = Operand(off
);
6148 store
->operands
[1] = Operand(offset
);
6150 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6151 store
->operands
[1].setFixed(m0
);
6152 store
->operands
[2] = Operand(write_datas
[i
]);
6153 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6155 store
->disable_wqm
= true;
6156 store
->barrier
= barrier_buffer
;
6157 ctx
->block
->instructions
.emplace_back(std::move(store
));
6158 ctx
->program
->wb_smem_l1_on_end
= true;
6159 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6160 ctx
->block
->kind
|= block_kind_needs_lowering
;
6161 ctx
->program
->needs_exact
= true;
6164 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6165 store
->operands
[0] = Operand(rsrc
);
6166 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6167 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6168 store
->operands
[3] = Operand(write_datas
[i
]);
6169 store
->offset
= offsets
[i
];
6170 store
->offen
= (offset
.type() == RegType::vgpr
);
6171 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6173 store
->disable_wqm
= true;
6174 store
->barrier
= barrier_buffer
;
6175 ctx
->program
->needs_exact
= true;
6176 ctx
->block
->instructions
.emplace_back(std::move(store
));
6181 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6183 /* return the previous value if dest is ever used */
6184 bool return_previous
= false;
6185 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6186 return_previous
= true;
6189 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6190 return_previous
= true;
6194 Builder
bld(ctx
->program
, ctx
->block
);
6195 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6197 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6198 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6199 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6201 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6202 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6203 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6205 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6207 aco_opcode op32
, op64
;
6208 switch (instr
->intrinsic
) {
6209 case nir_intrinsic_ssbo_atomic_add
:
6210 op32
= aco_opcode::buffer_atomic_add
;
6211 op64
= aco_opcode::buffer_atomic_add_x2
;
6213 case nir_intrinsic_ssbo_atomic_imin
:
6214 op32
= aco_opcode::buffer_atomic_smin
;
6215 op64
= aco_opcode::buffer_atomic_smin_x2
;
6217 case nir_intrinsic_ssbo_atomic_umin
:
6218 op32
= aco_opcode::buffer_atomic_umin
;
6219 op64
= aco_opcode::buffer_atomic_umin_x2
;
6221 case nir_intrinsic_ssbo_atomic_imax
:
6222 op32
= aco_opcode::buffer_atomic_smax
;
6223 op64
= aco_opcode::buffer_atomic_smax_x2
;
6225 case nir_intrinsic_ssbo_atomic_umax
:
6226 op32
= aco_opcode::buffer_atomic_umax
;
6227 op64
= aco_opcode::buffer_atomic_umax_x2
;
6229 case nir_intrinsic_ssbo_atomic_and
:
6230 op32
= aco_opcode::buffer_atomic_and
;
6231 op64
= aco_opcode::buffer_atomic_and_x2
;
6233 case nir_intrinsic_ssbo_atomic_or
:
6234 op32
= aco_opcode::buffer_atomic_or
;
6235 op64
= aco_opcode::buffer_atomic_or_x2
;
6237 case nir_intrinsic_ssbo_atomic_xor
:
6238 op32
= aco_opcode::buffer_atomic_xor
;
6239 op64
= aco_opcode::buffer_atomic_xor_x2
;
6241 case nir_intrinsic_ssbo_atomic_exchange
:
6242 op32
= aco_opcode::buffer_atomic_swap
;
6243 op64
= aco_opcode::buffer_atomic_swap_x2
;
6245 case nir_intrinsic_ssbo_atomic_comp_swap
:
6246 op32
= aco_opcode::buffer_atomic_cmpswap
;
6247 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6250 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6252 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6253 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6254 mubuf
->operands
[0] = Operand(rsrc
);
6255 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6256 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6257 mubuf
->operands
[3] = Operand(data
);
6258 if (return_previous
)
6259 mubuf
->definitions
[0] = Definition(dst
);
6261 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6262 mubuf
->glc
= return_previous
;
6263 mubuf
->dlc
= false; /* Not needed for atomics */
6264 mubuf
->disable_wqm
= true;
6265 mubuf
->barrier
= barrier_buffer
;
6266 ctx
->program
->needs_exact
= true;
6267 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6270 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6272 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6273 Builder
bld(ctx
->program
, ctx
->block
);
6274 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6275 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6278 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6280 Builder
bld(ctx
->program
, ctx
->block
);
6281 unsigned num_components
= instr
->num_components
;
6282 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6284 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6285 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6286 num_components
, component_size
};
6287 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6288 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6289 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6290 info
.barrier
= barrier_buffer
;
6291 info
.can_reorder
= false;
6292 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6293 * it's safe to use SMEM */
6294 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6295 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6296 emit_global_load(ctx
, bld
, &info
);
6298 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6299 emit_smem_load(ctx
, bld
, &info
);
6303 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6305 Builder
bld(ctx
->program
, ctx
->block
);
6306 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6307 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6309 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6310 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6311 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6313 if (ctx
->options
->chip_class
>= GFX7
)
6314 addr
= as_vgpr(ctx
, addr
);
6316 unsigned write_count
= 0;
6317 Temp write_datas
[32];
6318 unsigned offsets
[32];
6319 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6320 16, &write_count
, write_datas
, offsets
);
6322 for (unsigned i
= 0; i
< write_count
; i
++) {
6323 if (ctx
->options
->chip_class
>= GFX7
) {
6324 unsigned offset
= offsets
[i
];
6325 Temp store_addr
= addr
;
6326 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6327 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6328 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6329 Temp carry
= bld
.tmp(bld
.lm
);
6330 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6332 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6333 Operand(offset
), addr0
);
6334 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6336 carry
).def(1).setHint(vcc
);
6338 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6343 bool global
= ctx
->options
->chip_class
>= GFX9
;
6345 switch (write_datas
[i
].bytes()) {
6347 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6350 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6353 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6356 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6359 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6362 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6365 unreachable("store_global not implemented for this size.");
6368 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6369 flat
->operands
[0] = Operand(store_addr
);
6370 flat
->operands
[1] = Operand(s1
);
6371 flat
->operands
[2] = Operand(write_datas
[i
]);
6374 flat
->offset
= offset
;
6375 flat
->disable_wqm
= true;
6376 flat
->barrier
= barrier_buffer
;
6377 ctx
->program
->needs_exact
= true;
6378 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6380 assert(ctx
->options
->chip_class
== GFX6
);
6382 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6384 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6386 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6387 mubuf
->operands
[0] = Operand(rsrc
);
6388 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6389 mubuf
->operands
[2] = Operand(0u);
6390 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6393 mubuf
->offset
= offsets
[i
];
6394 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6395 mubuf
->disable_wqm
= true;
6396 mubuf
->barrier
= barrier_buffer
;
6397 ctx
->program
->needs_exact
= true;
6398 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6403 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6405 /* return the previous value if dest is ever used */
6406 bool return_previous
= false;
6407 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6408 return_previous
= true;
6411 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6412 return_previous
= true;
6416 Builder
bld(ctx
->program
, ctx
->block
);
6417 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6418 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6420 if (ctx
->options
->chip_class
>= GFX7
)
6421 addr
= as_vgpr(ctx
, addr
);
6423 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6424 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6425 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6427 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6429 aco_opcode op32
, op64
;
6431 if (ctx
->options
->chip_class
>= GFX7
) {
6432 bool global
= ctx
->options
->chip_class
>= GFX9
;
6433 switch (instr
->intrinsic
) {
6434 case nir_intrinsic_global_atomic_add
:
6435 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6436 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6438 case nir_intrinsic_global_atomic_imin
:
6439 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6440 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6442 case nir_intrinsic_global_atomic_umin
:
6443 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6444 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6446 case nir_intrinsic_global_atomic_imax
:
6447 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6448 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6450 case nir_intrinsic_global_atomic_umax
:
6451 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6452 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6454 case nir_intrinsic_global_atomic_and
:
6455 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6456 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6458 case nir_intrinsic_global_atomic_or
:
6459 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6460 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6462 case nir_intrinsic_global_atomic_xor
:
6463 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6464 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6466 case nir_intrinsic_global_atomic_exchange
:
6467 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6468 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6470 case nir_intrinsic_global_atomic_comp_swap
:
6471 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6472 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6475 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6478 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6479 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6480 flat
->operands
[0] = Operand(addr
);
6481 flat
->operands
[1] = Operand(s1
);
6482 flat
->operands
[2] = Operand(data
);
6483 if (return_previous
)
6484 flat
->definitions
[0] = Definition(dst
);
6485 flat
->glc
= return_previous
;
6486 flat
->dlc
= false; /* Not needed for atomics */
6488 flat
->disable_wqm
= true;
6489 flat
->barrier
= barrier_buffer
;
6490 ctx
->program
->needs_exact
= true;
6491 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6493 assert(ctx
->options
->chip_class
== GFX6
);
6495 switch (instr
->intrinsic
) {
6496 case nir_intrinsic_global_atomic_add
:
6497 op32
= aco_opcode::buffer_atomic_add
;
6498 op64
= aco_opcode::buffer_atomic_add_x2
;
6500 case nir_intrinsic_global_atomic_imin
:
6501 op32
= aco_opcode::buffer_atomic_smin
;
6502 op64
= aco_opcode::buffer_atomic_smin_x2
;
6504 case nir_intrinsic_global_atomic_umin
:
6505 op32
= aco_opcode::buffer_atomic_umin
;
6506 op64
= aco_opcode::buffer_atomic_umin_x2
;
6508 case nir_intrinsic_global_atomic_imax
:
6509 op32
= aco_opcode::buffer_atomic_smax
;
6510 op64
= aco_opcode::buffer_atomic_smax_x2
;
6512 case nir_intrinsic_global_atomic_umax
:
6513 op32
= aco_opcode::buffer_atomic_umax
;
6514 op64
= aco_opcode::buffer_atomic_umax_x2
;
6516 case nir_intrinsic_global_atomic_and
:
6517 op32
= aco_opcode::buffer_atomic_and
;
6518 op64
= aco_opcode::buffer_atomic_and_x2
;
6520 case nir_intrinsic_global_atomic_or
:
6521 op32
= aco_opcode::buffer_atomic_or
;
6522 op64
= aco_opcode::buffer_atomic_or_x2
;
6524 case nir_intrinsic_global_atomic_xor
:
6525 op32
= aco_opcode::buffer_atomic_xor
;
6526 op64
= aco_opcode::buffer_atomic_xor_x2
;
6528 case nir_intrinsic_global_atomic_exchange
:
6529 op32
= aco_opcode::buffer_atomic_swap
;
6530 op64
= aco_opcode::buffer_atomic_swap_x2
;
6532 case nir_intrinsic_global_atomic_comp_swap
:
6533 op32
= aco_opcode::buffer_atomic_cmpswap
;
6534 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6537 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6540 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6542 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6544 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6545 mubuf
->operands
[0] = Operand(rsrc
);
6546 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6547 mubuf
->operands
[2] = Operand(0u);
6548 mubuf
->operands
[3] = Operand(data
);
6549 if (return_previous
)
6550 mubuf
->definitions
[0] = Definition(dst
);
6551 mubuf
->glc
= return_previous
;
6554 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6555 mubuf
->disable_wqm
= true;
6556 mubuf
->barrier
= barrier_buffer
;
6557 ctx
->program
->needs_exact
= true;
6558 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6562 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6563 Builder
bld(ctx
->program
, ctx
->block
);
6564 switch(instr
->intrinsic
) {
6565 case nir_intrinsic_group_memory_barrier
:
6566 case nir_intrinsic_memory_barrier
:
6567 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6569 case nir_intrinsic_memory_barrier_buffer
:
6570 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6572 case nir_intrinsic_memory_barrier_image
:
6573 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6575 case nir_intrinsic_memory_barrier_tcs_patch
:
6576 case nir_intrinsic_memory_barrier_shared
:
6577 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6580 unreachable("Unimplemented memory barrier intrinsic");
6585 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6587 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6588 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6589 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6590 Builder
bld(ctx
->program
, ctx
->block
);
6592 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6593 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6594 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6597 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6599 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6600 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6601 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6602 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6604 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6605 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6608 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6610 unsigned offset
= nir_intrinsic_base(instr
);
6611 Builder
bld(ctx
->program
, ctx
->block
);
6612 Operand m
= load_lds_size_m0(bld
);
6613 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6614 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6616 unsigned num_operands
= 3;
6617 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6618 switch(instr
->intrinsic
) {
6619 case nir_intrinsic_shared_atomic_add
:
6620 op32
= aco_opcode::ds_add_u32
;
6621 op64
= aco_opcode::ds_add_u64
;
6622 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6623 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6625 case nir_intrinsic_shared_atomic_imin
:
6626 op32
= aco_opcode::ds_min_i32
;
6627 op64
= aco_opcode::ds_min_i64
;
6628 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6629 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6631 case nir_intrinsic_shared_atomic_umin
:
6632 op32
= aco_opcode::ds_min_u32
;
6633 op64
= aco_opcode::ds_min_u64
;
6634 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6635 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6637 case nir_intrinsic_shared_atomic_imax
:
6638 op32
= aco_opcode::ds_max_i32
;
6639 op64
= aco_opcode::ds_max_i64
;
6640 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6641 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6643 case nir_intrinsic_shared_atomic_umax
:
6644 op32
= aco_opcode::ds_max_u32
;
6645 op64
= aco_opcode::ds_max_u64
;
6646 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6647 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6649 case nir_intrinsic_shared_atomic_and
:
6650 op32
= aco_opcode::ds_and_b32
;
6651 op64
= aco_opcode::ds_and_b64
;
6652 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6653 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6655 case nir_intrinsic_shared_atomic_or
:
6656 op32
= aco_opcode::ds_or_b32
;
6657 op64
= aco_opcode::ds_or_b64
;
6658 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6659 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6661 case nir_intrinsic_shared_atomic_xor
:
6662 op32
= aco_opcode::ds_xor_b32
;
6663 op64
= aco_opcode::ds_xor_b64
;
6664 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6665 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6667 case nir_intrinsic_shared_atomic_exchange
:
6668 op32
= aco_opcode::ds_write_b32
;
6669 op64
= aco_opcode::ds_write_b64
;
6670 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6671 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6673 case nir_intrinsic_shared_atomic_comp_swap
:
6674 op32
= aco_opcode::ds_cmpst_b32
;
6675 op64
= aco_opcode::ds_cmpst_b64
;
6676 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6677 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6681 unreachable("Unhandled shared atomic intrinsic");
6684 /* return the previous value if dest is ever used */
6685 bool return_previous
= false;
6686 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6687 return_previous
= true;
6690 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6691 return_previous
= true;
6696 if (data
.size() == 1) {
6697 assert(instr
->dest
.ssa
.bit_size
== 32);
6698 op
= return_previous
? op32_rtn
: op32
;
6700 assert(instr
->dest
.ssa
.bit_size
== 64);
6701 op
= return_previous
? op64_rtn
: op64
;
6704 if (offset
> 65535) {
6705 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6709 aco_ptr
<DS_instruction
> ds
;
6710 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6711 ds
->operands
[0] = Operand(address
);
6712 ds
->operands
[1] = Operand(data
);
6713 if (num_operands
== 4)
6714 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6715 ds
->operands
[num_operands
- 1] = m
;
6716 ds
->offset0
= offset
;
6717 if (return_previous
)
6718 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6719 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6722 Temp
get_scratch_resource(isel_context
*ctx
)
6724 Builder
bld(ctx
->program
, ctx
->block
);
6725 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6726 if (ctx
->stage
!= compute_cs
)
6727 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6729 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6730 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6732 if (ctx
->program
->chip_class
>= GFX10
) {
6733 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6734 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6735 S_008F0C_RESOURCE_LEVEL(1);
6736 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6737 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6738 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6741 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6742 if (ctx
->program
->chip_class
<= GFX8
)
6743 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6745 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6748 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6749 Builder
bld(ctx
->program
, ctx
->block
);
6750 Temp rsrc
= get_scratch_resource(ctx
);
6751 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6752 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6754 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6755 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6756 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6757 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6758 info
.swizzle_component_size
= 16;
6759 info
.can_reorder
= false;
6760 info
.soffset
= ctx
->program
->scratch_offset
;
6761 emit_mubuf_load(ctx
, bld
, &info
);
6764 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6765 Builder
bld(ctx
->program
, ctx
->block
);
6766 Temp rsrc
= get_scratch_resource(ctx
);
6767 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6768 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6770 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6771 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6773 unsigned write_count
= 0;
6774 Temp write_datas
[32];
6775 unsigned offsets
[32];
6776 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6777 16, &write_count
, write_datas
, offsets
);
6779 for (unsigned i
= 0; i
< write_count
; i
++) {
6780 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6781 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6785 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6786 uint8_t log2_ps_iter_samples
;
6787 if (ctx
->program
->info
->ps
.force_persample
) {
6788 log2_ps_iter_samples
=
6789 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6791 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6794 /* The bit pattern matches that used by fixed function fragment
6796 static const unsigned ps_iter_masks
[] = {
6797 0xffff, /* not used */
6803 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6805 Builder
bld(ctx
->program
, ctx
->block
);
6807 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6808 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6809 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6810 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6811 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6812 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6815 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6816 Builder
bld(ctx
->program
, ctx
->block
);
6818 unsigned stream
= nir_intrinsic_stream_id(instr
);
6819 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6820 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6821 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6824 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6826 unsigned num_components
=
6827 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6828 assert(num_components
);
6830 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6831 unsigned stream_offset
= 0;
6832 for (unsigned i
= 0; i
< stream
; i
++) {
6833 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6834 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6837 /* Limit on the stride field for <= GFX7. */
6838 assert(stride
< (1 << 14));
6840 Temp gsvs_dwords
[4];
6841 for (unsigned i
= 0; i
< 4; i
++)
6842 gsvs_dwords
[i
] = bld
.tmp(s1
);
6843 bld
.pseudo(aco_opcode::p_split_vector
,
6844 Definition(gsvs_dwords
[0]),
6845 Definition(gsvs_dwords
[1]),
6846 Definition(gsvs_dwords
[2]),
6847 Definition(gsvs_dwords
[3]),
6850 if (stream_offset
) {
6851 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6853 Temp carry
= bld
.tmp(s1
);
6854 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6855 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6858 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6859 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6861 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6862 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6864 unsigned offset
= 0;
6865 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6866 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6869 for (unsigned j
= 0; j
< 4; j
++) {
6870 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6873 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6874 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6875 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6876 if (const_offset
>= 4096u) {
6877 if (vaddr_offset
.isUndefined())
6878 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6880 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6881 const_offset
%= 4096u;
6884 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6885 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6886 mtbuf
->operands
[1] = vaddr_offset
;
6887 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6888 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6889 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6890 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6891 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6892 mtbuf
->offset
= const_offset
;
6895 mtbuf
->barrier
= barrier_gs_data
;
6896 mtbuf
->can_reorder
= true;
6897 bld
.insert(std::move(mtbuf
));
6900 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6903 /* outputs for the next vertex are undefined and keeping them around can
6904 * create invalid IR with control flow */
6905 ctx
->outputs
.mask
[i
] = 0;
6908 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6911 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6913 Builder
bld(ctx
->program
, ctx
->block
);
6915 if (cluster_size
== 1) {
6917 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6918 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6919 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6920 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6921 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6922 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6923 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6924 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6925 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6926 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6927 //subgroupAnd(val) -> (exec & ~val) == 0
6928 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6929 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6930 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6931 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6932 //subgroupOr(val) -> (val & exec) != 0
6933 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6934 return bool_to_vector_condition(ctx
, tmp
);
6935 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6936 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6937 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6938 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6939 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6940 return bool_to_vector_condition(ctx
, tmp
);
6942 //subgroupClustered{And,Or,Xor}(val, n) ->
6943 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6944 //cluster_offset = ~(n - 1) & lane_id
6945 //cluster_mask = ((1 << n) - 1)
6946 //subgroupClusteredAnd():
6947 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6948 //subgroupClusteredOr():
6949 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6950 //subgroupClusteredXor():
6951 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6952 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6953 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6956 if (op
== nir_op_iand
)
6957 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6959 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6961 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6963 if (ctx
->program
->chip_class
<= GFX7
)
6964 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6965 else if (ctx
->program
->wave_size
== 64)
6966 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6968 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6969 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6970 if (cluster_mask
!= 0xffffffff)
6971 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6973 Definition cmp_def
= Definition();
6974 if (op
== nir_op_iand
) {
6975 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6976 } else if (op
== nir_op_ior
) {
6977 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6978 } else if (op
== nir_op_ixor
) {
6979 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6980 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6981 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6983 cmp_def
.setHint(vcc
);
6984 return cmp_def
.getTemp();
6988 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6990 Builder
bld(ctx
->program
, ctx
->block
);
6992 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6993 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6994 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6996 if (op
== nir_op_iand
)
6997 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6999 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7001 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7002 Temp lo
= lohi
.def(0).getTemp();
7003 Temp hi
= lohi
.def(1).getTemp();
7004 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7006 Definition cmp_def
= Definition();
7007 if (op
== nir_op_iand
)
7008 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7009 else if (op
== nir_op_ior
)
7010 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7011 else if (op
== nir_op_ixor
)
7012 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7013 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7014 cmp_def
.setHint(vcc
);
7015 return cmp_def
.getTemp();
7018 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7020 Builder
bld(ctx
->program
, ctx
->block
);
7022 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7023 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7024 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7025 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7026 if (op
== nir_op_iand
)
7027 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7028 else if (op
== nir_op_ior
)
7029 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7030 else if (op
== nir_op_ixor
)
7031 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7037 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7039 Builder
bld(ctx
->program
, ctx
->block
);
7040 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7041 if (src
.regClass().type() == RegType::vgpr
) {
7042 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7043 } else if (src
.regClass() == s1
) {
7044 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7045 } else if (src
.regClass() == s2
) {
7046 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7048 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7049 nir_print_instr(&instr
->instr
, stderr
);
7050 fprintf(stderr
, "\n");
7054 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7056 Builder
bld(ctx
->program
, ctx
->block
);
7057 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7058 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7059 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7061 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7062 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7063 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7064 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7067 if (ctx
->program
->chip_class
>= GFX8
) {
7068 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7069 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7070 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7071 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7072 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7073 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7075 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7076 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7077 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7078 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7079 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7080 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7081 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7082 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7083 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7084 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7087 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7088 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7089 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7090 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7091 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7092 Temp wqm1
= bld
.tmp(v1
);
7093 emit_wqm(ctx
, tmp1
, wqm1
, true);
7094 Temp wqm2
= bld
.tmp(v1
);
7095 emit_wqm(ctx
, tmp2
, wqm2
, true);
7096 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7100 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7102 Builder
bld(ctx
->program
, ctx
->block
);
7103 switch(instr
->intrinsic
) {
7104 case nir_intrinsic_load_barycentric_sample
:
7105 case nir_intrinsic_load_barycentric_pixel
:
7106 case nir_intrinsic_load_barycentric_centroid
: {
7107 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7108 Temp bary
= Temp(0, s2
);
7110 case INTERP_MODE_SMOOTH
:
7111 case INTERP_MODE_NONE
:
7112 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7113 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7114 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7115 bary
= ctx
->persp_centroid
;
7116 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7117 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7119 case INTERP_MODE_NOPERSPECTIVE
:
7120 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7121 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7122 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7123 bary
= ctx
->linear_centroid
;
7124 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7125 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7130 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7131 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7132 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7133 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7134 Operand(p1
), Operand(p2
));
7135 emit_split_vector(ctx
, dst
, 2);
7138 case nir_intrinsic_load_barycentric_model
: {
7139 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7141 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7142 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7143 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7144 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7145 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7146 Operand(p1
), Operand(p2
), Operand(p3
));
7147 emit_split_vector(ctx
, dst
, 3);
7150 case nir_intrinsic_load_barycentric_at_sample
: {
7151 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7152 switch (ctx
->options
->key
.fs
.num_samples
) {
7153 case 2: sample_pos_offset
+= 1 << 3; break;
7154 case 4: sample_pos_offset
+= 3 << 3; break;
7155 case 8: sample_pos_offset
+= 7 << 3; break;
7159 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7160 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7161 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7162 if (addr
.type() == RegType::sgpr
) {
7165 sample_pos_offset
+= const_addr
->u32
<< 3;
7166 offset
= Operand(sample_pos_offset
);
7167 } else if (ctx
->options
->chip_class
>= GFX9
) {
7168 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7170 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7171 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7174 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7175 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7177 } else if (ctx
->options
->chip_class
>= GFX9
) {
7178 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7179 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7180 } else if (ctx
->options
->chip_class
>= GFX7
) {
7181 /* addr += private_segment_buffer + sample_pos_offset */
7182 Temp tmp0
= bld
.tmp(s1
);
7183 Temp tmp1
= bld
.tmp(s1
);
7184 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7185 Definition scc_tmp
= bld
.def(s1
, scc
);
7186 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7187 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7188 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7189 Temp pck0
= bld
.tmp(v1
);
7190 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7191 tmp1
= as_vgpr(ctx
, tmp1
);
7192 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7193 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7195 /* sample_pos = flat_load_dwordx2 addr */
7196 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7198 assert(ctx
->options
->chip_class
== GFX6
);
7200 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7201 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7202 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7204 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7205 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7207 sample_pos
= bld
.tmp(v2
);
7209 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7210 load
->definitions
[0] = Definition(sample_pos
);
7211 load
->operands
[0] = Operand(rsrc
);
7212 load
->operands
[1] = Operand(addr
);
7213 load
->operands
[2] = Operand(0u);
7214 load
->offset
= sample_pos_offset
;
7216 load
->addr64
= true;
7219 load
->disable_wqm
= false;
7220 load
->barrier
= barrier_none
;
7221 load
->can_reorder
= true;
7222 ctx
->block
->instructions
.emplace_back(std::move(load
));
7225 /* sample_pos -= 0.5 */
7226 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7227 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7228 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7229 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7230 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7232 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7235 case nir_intrinsic_load_barycentric_at_offset
: {
7236 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7237 RegClass rc
= RegClass(offset
.type(), 1);
7238 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7239 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7240 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7243 case nir_intrinsic_load_front_face
: {
7244 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7245 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7248 case nir_intrinsic_load_view_index
: {
7249 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7250 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7251 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7257 case nir_intrinsic_load_layer_id
: {
7258 unsigned idx
= nir_intrinsic_base(instr
);
7259 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7260 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7263 case nir_intrinsic_load_frag_coord
: {
7264 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7267 case nir_intrinsic_load_sample_pos
: {
7268 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7269 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7270 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7271 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7272 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7275 case nir_intrinsic_load_tess_coord
:
7276 visit_load_tess_coord(ctx
, instr
);
7278 case nir_intrinsic_load_interpolated_input
:
7279 visit_load_interpolated_input(ctx
, instr
);
7281 case nir_intrinsic_store_output
:
7282 visit_store_output(ctx
, instr
);
7284 case nir_intrinsic_load_input
:
7285 case nir_intrinsic_load_input_vertex
:
7286 visit_load_input(ctx
, instr
);
7288 case nir_intrinsic_load_output
:
7289 visit_load_output(ctx
, instr
);
7291 case nir_intrinsic_load_per_vertex_input
:
7292 visit_load_per_vertex_input(ctx
, instr
);
7294 case nir_intrinsic_load_per_vertex_output
:
7295 visit_load_per_vertex_output(ctx
, instr
);
7297 case nir_intrinsic_store_per_vertex_output
:
7298 visit_store_per_vertex_output(ctx
, instr
);
7300 case nir_intrinsic_load_ubo
:
7301 visit_load_ubo(ctx
, instr
);
7303 case nir_intrinsic_load_push_constant
:
7304 visit_load_push_constant(ctx
, instr
);
7306 case nir_intrinsic_load_constant
:
7307 visit_load_constant(ctx
, instr
);
7309 case nir_intrinsic_vulkan_resource_index
:
7310 visit_load_resource(ctx
, instr
);
7312 case nir_intrinsic_discard
:
7313 visit_discard(ctx
, instr
);
7315 case nir_intrinsic_discard_if
:
7316 visit_discard_if(ctx
, instr
);
7318 case nir_intrinsic_load_shared
:
7319 visit_load_shared(ctx
, instr
);
7321 case nir_intrinsic_store_shared
:
7322 visit_store_shared(ctx
, instr
);
7324 case nir_intrinsic_shared_atomic_add
:
7325 case nir_intrinsic_shared_atomic_imin
:
7326 case nir_intrinsic_shared_atomic_umin
:
7327 case nir_intrinsic_shared_atomic_imax
:
7328 case nir_intrinsic_shared_atomic_umax
:
7329 case nir_intrinsic_shared_atomic_and
:
7330 case nir_intrinsic_shared_atomic_or
:
7331 case nir_intrinsic_shared_atomic_xor
:
7332 case nir_intrinsic_shared_atomic_exchange
:
7333 case nir_intrinsic_shared_atomic_comp_swap
:
7334 visit_shared_atomic(ctx
, instr
);
7336 case nir_intrinsic_image_deref_load
:
7337 visit_image_load(ctx
, instr
);
7339 case nir_intrinsic_image_deref_store
:
7340 visit_image_store(ctx
, instr
);
7342 case nir_intrinsic_image_deref_atomic_add
:
7343 case nir_intrinsic_image_deref_atomic_umin
:
7344 case nir_intrinsic_image_deref_atomic_imin
:
7345 case nir_intrinsic_image_deref_atomic_umax
:
7346 case nir_intrinsic_image_deref_atomic_imax
:
7347 case nir_intrinsic_image_deref_atomic_and
:
7348 case nir_intrinsic_image_deref_atomic_or
:
7349 case nir_intrinsic_image_deref_atomic_xor
:
7350 case nir_intrinsic_image_deref_atomic_exchange
:
7351 case nir_intrinsic_image_deref_atomic_comp_swap
:
7352 visit_image_atomic(ctx
, instr
);
7354 case nir_intrinsic_image_deref_size
:
7355 visit_image_size(ctx
, instr
);
7357 case nir_intrinsic_load_ssbo
:
7358 visit_load_ssbo(ctx
, instr
);
7360 case nir_intrinsic_store_ssbo
:
7361 visit_store_ssbo(ctx
, instr
);
7363 case nir_intrinsic_load_global
:
7364 visit_load_global(ctx
, instr
);
7366 case nir_intrinsic_store_global
:
7367 visit_store_global(ctx
, instr
);
7369 case nir_intrinsic_global_atomic_add
:
7370 case nir_intrinsic_global_atomic_imin
:
7371 case nir_intrinsic_global_atomic_umin
:
7372 case nir_intrinsic_global_atomic_imax
:
7373 case nir_intrinsic_global_atomic_umax
:
7374 case nir_intrinsic_global_atomic_and
:
7375 case nir_intrinsic_global_atomic_or
:
7376 case nir_intrinsic_global_atomic_xor
:
7377 case nir_intrinsic_global_atomic_exchange
:
7378 case nir_intrinsic_global_atomic_comp_swap
:
7379 visit_global_atomic(ctx
, instr
);
7381 case nir_intrinsic_ssbo_atomic_add
:
7382 case nir_intrinsic_ssbo_atomic_imin
:
7383 case nir_intrinsic_ssbo_atomic_umin
:
7384 case nir_intrinsic_ssbo_atomic_imax
:
7385 case nir_intrinsic_ssbo_atomic_umax
:
7386 case nir_intrinsic_ssbo_atomic_and
:
7387 case nir_intrinsic_ssbo_atomic_or
:
7388 case nir_intrinsic_ssbo_atomic_xor
:
7389 case nir_intrinsic_ssbo_atomic_exchange
:
7390 case nir_intrinsic_ssbo_atomic_comp_swap
:
7391 visit_atomic_ssbo(ctx
, instr
);
7393 case nir_intrinsic_load_scratch
:
7394 visit_load_scratch(ctx
, instr
);
7396 case nir_intrinsic_store_scratch
:
7397 visit_store_scratch(ctx
, instr
);
7399 case nir_intrinsic_get_buffer_size
:
7400 visit_get_buffer_size(ctx
, instr
);
7402 case nir_intrinsic_control_barrier
: {
7403 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7404 /* GFX6 only (thanks to a hw bug workaround):
7405 * The real barrier instruction isn’t needed, because an entire patch
7406 * always fits into a single wave.
7411 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7412 bld
.sopp(aco_opcode::s_barrier
);
7416 case nir_intrinsic_memory_barrier_tcs_patch
:
7417 case nir_intrinsic_group_memory_barrier
:
7418 case nir_intrinsic_memory_barrier
:
7419 case nir_intrinsic_memory_barrier_buffer
:
7420 case nir_intrinsic_memory_barrier_image
:
7421 case nir_intrinsic_memory_barrier_shared
:
7422 emit_memory_barrier(ctx
, instr
);
7424 case nir_intrinsic_load_num_work_groups
: {
7425 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7426 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7427 emit_split_vector(ctx
, dst
, 3);
7430 case nir_intrinsic_load_local_invocation_id
: {
7431 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7432 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7433 emit_split_vector(ctx
, dst
, 3);
7436 case nir_intrinsic_load_work_group_id
: {
7437 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7438 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7439 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7440 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7441 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7442 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7443 emit_split_vector(ctx
, dst
, 3);
7446 case nir_intrinsic_load_local_invocation_index
: {
7447 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7449 /* The tg_size bits [6:11] contain the subgroup id,
7450 * we need this multiplied by the wave size, and then OR the thread id to it.
7452 if (ctx
->program
->wave_size
== 64) {
7453 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7454 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7455 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7456 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7458 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7459 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7460 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7461 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7465 case nir_intrinsic_load_subgroup_id
: {
7466 if (ctx
->stage
== compute_cs
) {
7467 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7468 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7470 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7474 case nir_intrinsic_load_subgroup_invocation
: {
7475 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7478 case nir_intrinsic_load_num_subgroups
: {
7479 if (ctx
->stage
== compute_cs
)
7480 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7481 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7483 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7486 case nir_intrinsic_ballot
: {
7487 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7488 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7489 Definition tmp
= bld
.def(dst
.regClass());
7490 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7491 if (instr
->src
[0].ssa
->bit_size
== 1) {
7492 assert(src
.regClass() == bld
.lm
);
7493 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7494 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7495 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7496 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7497 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7499 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7500 nir_print_instr(&instr
->instr
, stderr
);
7501 fprintf(stderr
, "\n");
7503 if (dst
.size() != bld
.lm
.size()) {
7504 /* Wave32 with ballot size set to 64 */
7505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7507 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7510 case nir_intrinsic_shuffle
:
7511 case nir_intrinsic_read_invocation
: {
7512 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7513 if (!nir_src_is_divergent(instr
->src
[0])) {
7514 emit_uniform_subgroup(ctx
, instr
, src
);
7516 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7517 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7518 tid
= bld
.as_uniform(tid
);
7519 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7520 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7521 Temp tmp
= bld
.tmp(v1
);
7522 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7523 if (dst
.type() == RegType::vgpr
)
7524 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7526 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7527 } else if (src
.regClass() == v1
) {
7528 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7529 } else if (src
.regClass() == v2
) {
7530 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7531 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7532 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7533 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7534 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7535 emit_split_vector(ctx
, dst
, 2);
7536 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7537 assert(src
.regClass() == bld
.lm
);
7538 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7539 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7540 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7541 assert(src
.regClass() == bld
.lm
);
7543 if (ctx
->program
->chip_class
<= GFX7
)
7544 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7545 else if (ctx
->program
->wave_size
== 64)
7546 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7548 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7549 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7550 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7551 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7553 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7554 nir_print_instr(&instr
->instr
, stderr
);
7555 fprintf(stderr
, "\n");
7560 case nir_intrinsic_load_sample_id
: {
7561 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7562 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7565 case nir_intrinsic_load_sample_mask_in
: {
7566 visit_load_sample_mask_in(ctx
, instr
);
7569 case nir_intrinsic_read_first_invocation
: {
7570 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7571 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7572 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7574 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7576 } else if (src
.regClass() == v2
) {
7577 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7578 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7579 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7580 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7581 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7582 emit_split_vector(ctx
, dst
, 2);
7583 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7584 assert(src
.regClass() == bld
.lm
);
7585 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7586 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7587 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7588 } else if (src
.regClass() == s1
) {
7589 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7590 } else if (src
.regClass() == s2
) {
7591 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7593 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7594 nir_print_instr(&instr
->instr
, stderr
);
7595 fprintf(stderr
, "\n");
7599 case nir_intrinsic_vote_all
: {
7600 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7601 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7602 assert(src
.regClass() == bld
.lm
);
7603 assert(dst
.regClass() == bld
.lm
);
7605 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7606 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7607 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7610 case nir_intrinsic_vote_any
: {
7611 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7612 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7613 assert(src
.regClass() == bld
.lm
);
7614 assert(dst
.regClass() == bld
.lm
);
7616 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7617 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7620 case nir_intrinsic_reduce
:
7621 case nir_intrinsic_inclusive_scan
:
7622 case nir_intrinsic_exclusive_scan
: {
7623 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7624 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7625 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7626 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7627 nir_intrinsic_cluster_size(instr
) : 0;
7628 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7630 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7631 emit_uniform_subgroup(ctx
, instr
, src
);
7632 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7633 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7635 else if (op
== nir_op_iadd
)
7637 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7639 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7641 switch (instr
->intrinsic
) {
7642 case nir_intrinsic_reduce
:
7643 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7645 case nir_intrinsic_exclusive_scan
:
7646 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7648 case nir_intrinsic_inclusive_scan
:
7649 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7654 } else if (cluster_size
== 1) {
7655 bld
.copy(Definition(dst
), src
);
7657 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7659 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7663 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7664 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7679 unreachable("unknown reduction op");
7685 switch (instr
->intrinsic
) {
7686 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7687 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7688 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7690 unreachable("unknown reduce intrinsic");
7693 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7694 reduce
->operands
[0] = Operand(src
);
7695 // filled in by aco_reduce_assign.cpp, used internally as part of the
7697 assert(dst
.size() == 1 || dst
.size() == 2);
7698 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7699 reduce
->operands
[2] = Operand(v1
.as_linear());
7701 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7702 reduce
->definitions
[0] = Definition(tmp_dst
);
7703 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7704 reduce
->definitions
[2] = Definition();
7705 reduce
->definitions
[3] = Definition(scc
, s1
);
7706 reduce
->definitions
[4] = Definition();
7707 reduce
->reduce_op
= reduce_op
;
7708 reduce
->cluster_size
= cluster_size
;
7709 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7711 emit_wqm(ctx
, tmp_dst
, dst
);
7715 case nir_intrinsic_quad_broadcast
: {
7716 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7717 if (!nir_dest_is_divergent(instr
->dest
)) {
7718 emit_uniform_subgroup(ctx
, instr
, src
);
7720 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7721 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7722 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7724 if (instr
->dest
.ssa
.bit_size
== 1) {
7725 assert(src
.regClass() == bld
.lm
);
7726 assert(dst
.regClass() == bld
.lm
);
7727 uint32_t half_mask
= 0x11111111u
<< lane
;
7728 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7729 Temp tmp
= bld
.tmp(bld
.lm
);
7730 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7731 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7732 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7733 emit_wqm(ctx
, tmp
, dst
);
7734 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7735 Temp tmp
= bld
.tmp(v1
);
7736 if (ctx
->program
->chip_class
>= GFX8
)
7737 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7739 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7740 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7741 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7742 Temp tmp
= bld
.tmp(v1
);
7743 if (ctx
->program
->chip_class
>= GFX8
)
7744 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7746 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7747 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7748 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7749 if (ctx
->program
->chip_class
>= GFX8
)
7750 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7752 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7753 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7754 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7755 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7756 if (ctx
->program
->chip_class
>= GFX8
) {
7757 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7758 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7760 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7761 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7763 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7764 emit_split_vector(ctx
, dst
, 2);
7766 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7767 nir_print_instr(&instr
->instr
, stderr
);
7768 fprintf(stderr
, "\n");
7773 case nir_intrinsic_quad_swap_horizontal
:
7774 case nir_intrinsic_quad_swap_vertical
:
7775 case nir_intrinsic_quad_swap_diagonal
:
7776 case nir_intrinsic_quad_swizzle_amd
: {
7777 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7778 if (!nir_dest_is_divergent(instr
->dest
)) {
7779 emit_uniform_subgroup(ctx
, instr
, src
);
7782 uint16_t dpp_ctrl
= 0;
7783 switch (instr
->intrinsic
) {
7784 case nir_intrinsic_quad_swap_horizontal
:
7785 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7787 case nir_intrinsic_quad_swap_vertical
:
7788 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7790 case nir_intrinsic_quad_swap_diagonal
:
7791 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7793 case nir_intrinsic_quad_swizzle_amd
:
7794 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7799 if (ctx
->program
->chip_class
< GFX8
)
7800 dpp_ctrl
|= (1 << 15);
7802 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7803 if (instr
->dest
.ssa
.bit_size
== 1) {
7804 assert(src
.regClass() == bld
.lm
);
7805 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7806 if (ctx
->program
->chip_class
>= GFX8
)
7807 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7809 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7810 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7811 emit_wqm(ctx
, tmp
, dst
);
7812 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7813 Temp tmp
= bld
.tmp(v1
);
7814 if (ctx
->program
->chip_class
>= GFX8
)
7815 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7817 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7818 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7819 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7820 Temp tmp
= bld
.tmp(v1
);
7821 if (ctx
->program
->chip_class
>= GFX8
)
7822 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7824 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7825 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7826 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7828 if (ctx
->program
->chip_class
>= GFX8
)
7829 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7831 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7832 emit_wqm(ctx
, tmp
, dst
);
7833 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7834 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7835 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7836 if (ctx
->program
->chip_class
>= GFX8
) {
7837 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7838 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7840 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7841 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7843 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7844 emit_split_vector(ctx
, dst
, 2);
7846 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7847 nir_print_instr(&instr
->instr
, stderr
);
7848 fprintf(stderr
, "\n");
7852 case nir_intrinsic_masked_swizzle_amd
: {
7853 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7854 if (!nir_dest_is_divergent(instr
->dest
)) {
7855 emit_uniform_subgroup(ctx
, instr
, src
);
7858 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7859 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7860 if (dst
.regClass() == v1
) {
7862 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7864 } else if (dst
.regClass() == v2
) {
7865 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7867 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7868 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7870 emit_split_vector(ctx
, dst
, 2);
7872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7873 nir_print_instr(&instr
->instr
, stderr
);
7874 fprintf(stderr
, "\n");
7878 case nir_intrinsic_write_invocation_amd
: {
7879 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7880 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7881 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7882 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7883 if (dst
.regClass() == v1
) {
7884 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7885 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7886 } else if (dst
.regClass() == v2
) {
7887 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7888 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7889 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7891 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7892 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7893 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7894 emit_split_vector(ctx
, dst
, 2);
7896 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7897 nir_print_instr(&instr
->instr
, stderr
);
7898 fprintf(stderr
, "\n");
7902 case nir_intrinsic_mbcnt_amd
: {
7903 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7904 RegClass rc
= RegClass(src
.type(), 1);
7905 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7906 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7907 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7908 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7909 emit_wqm(ctx
, wqm_tmp
, dst
);
7912 case nir_intrinsic_load_helper_invocation
: {
7913 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7914 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7915 ctx
->block
->kind
|= block_kind_needs_lowering
;
7916 ctx
->program
->needs_exact
= true;
7919 case nir_intrinsic_is_helper_invocation
: {
7920 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7921 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7922 ctx
->block
->kind
|= block_kind_needs_lowering
;
7923 ctx
->program
->needs_exact
= true;
7926 case nir_intrinsic_demote
:
7927 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7929 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7930 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7931 ctx
->block
->kind
|= block_kind_uses_demote
;
7932 ctx
->program
->needs_exact
= true;
7934 case nir_intrinsic_demote_if
: {
7935 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7936 assert(src
.regClass() == bld
.lm
);
7937 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7938 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7940 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7941 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7942 ctx
->block
->kind
|= block_kind_uses_demote
;
7943 ctx
->program
->needs_exact
= true;
7946 case nir_intrinsic_first_invocation
: {
7947 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7948 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7951 case nir_intrinsic_shader_clock
: {
7953 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7954 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7955 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7956 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7959 case nir_intrinsic_load_vertex_id_zero_base
: {
7960 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7961 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7964 case nir_intrinsic_load_first_vertex
: {
7965 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7966 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7969 case nir_intrinsic_load_base_instance
: {
7970 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7971 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7974 case nir_intrinsic_load_instance_id
: {
7975 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7976 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7979 case nir_intrinsic_load_draw_id
: {
7980 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7981 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7984 case nir_intrinsic_load_invocation_id
: {
7985 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7987 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7988 if (ctx
->options
->chip_class
>= GFX10
)
7989 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7991 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7992 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7993 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7994 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7996 unreachable("Unsupported stage for load_invocation_id");
8001 case nir_intrinsic_load_primitive_id
: {
8002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8004 switch (ctx
->shader
->info
.stage
) {
8005 case MESA_SHADER_GEOMETRY
:
8006 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8008 case MESA_SHADER_TESS_CTRL
:
8009 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8011 case MESA_SHADER_TESS_EVAL
:
8012 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8015 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8020 case nir_intrinsic_load_patch_vertices_in
: {
8021 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8022 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8024 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8025 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8028 case nir_intrinsic_emit_vertex_with_counter
: {
8029 visit_emit_vertex_with_counter(ctx
, instr
);
8032 case nir_intrinsic_end_primitive_with_counter
: {
8033 unsigned stream
= nir_intrinsic_stream_id(instr
);
8034 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8037 case nir_intrinsic_set_vertex_count
: {
8038 /* unused, the HW keeps track of this for us */
8042 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8043 nir_print_instr(&instr
->instr
, stderr
);
8044 fprintf(stderr
, "\n");
8052 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8053 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8054 enum glsl_base_type
*stype
)
8056 nir_deref_instr
*texture_deref_instr
= NULL
;
8057 nir_deref_instr
*sampler_deref_instr
= NULL
;
8060 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8061 switch (instr
->src
[i
].src_type
) {
8062 case nir_tex_src_texture_deref
:
8063 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8065 case nir_tex_src_sampler_deref
:
8066 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8068 case nir_tex_src_plane
:
8069 plane
= nir_src_as_int(instr
->src
[i
].src
);
8076 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8078 if (!sampler_deref_instr
)
8079 sampler_deref_instr
= texture_deref_instr
;
8082 assert(instr
->op
!= nir_texop_txf_ms
&&
8083 instr
->op
!= nir_texop_samples_identical
);
8084 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8085 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8086 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8087 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8088 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8089 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8091 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8094 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8096 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8097 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8098 Builder
bld(ctx
->program
, ctx
->block
);
8100 /* to avoid unnecessary moves, we split and recombine sampler and image */
8101 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8102 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8103 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8104 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8105 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8106 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8107 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8108 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8110 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8111 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8112 img
[0], img
[1], img
[2], img
[3],
8113 img
[4], img
[5], img
[6], img
[7]);
8114 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8115 samp
[0], samp
[1], samp
[2], samp
[3]);
8118 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8119 instr
->op
== nir_texop_samples_identical
))
8120 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8123 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8124 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8126 Builder
bld(ctx
->program
, ctx
->block
);
8128 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8129 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8130 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8132 Operand
neg_one(0xbf800000u
);
8133 Operand
one(0x3f800000u
);
8134 Operand
two(0x40000000u
);
8135 Operand
four(0x40800000u
);
8137 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8138 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8139 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8141 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8142 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8143 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8144 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8147 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8148 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8149 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8151 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8154 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8155 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8156 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8159 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8160 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8162 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8163 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8166 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8168 Builder
bld(ctx
->program
, ctx
->block
);
8169 Temp ma
, tc
, sc
, id
;
8172 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8174 // see comment in ac_prepare_cube_coords()
8175 if (ctx
->options
->chip_class
<= GFX8
)
8176 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8179 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8181 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8182 vop3a
->operands
[0] = Operand(ma
);
8183 vop3a
->abs
[0] = true;
8184 Temp invma
= bld
.tmp(v1
);
8185 vop3a
->definitions
[0] = Definition(invma
);
8186 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8188 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8190 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8192 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8194 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8196 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8199 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8200 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8202 for (unsigned i
= 0; i
< 2; i
++) {
8203 // see comment in ac_prepare_cube_coords()
8205 Temp deriv_sc
, deriv_tc
;
8206 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8207 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8209 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8211 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8212 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8213 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8214 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8215 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8216 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8217 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8220 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8221 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8225 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8232 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8234 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8236 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8237 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8240 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8241 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8242 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8246 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8248 Builder
bld(ctx
->program
, ctx
->block
);
8249 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8250 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8251 has_clamped_lod
= false;
8252 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8253 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8254 clamped_lod
= Temp();
8255 std::vector
<Temp
> coords
;
8256 std::vector
<Temp
> derivs
;
8257 nir_const_value
*sample_index_cv
= NULL
;
8258 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8259 enum glsl_base_type stype
;
8260 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8262 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8263 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8264 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8265 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8267 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8268 switch (instr
->src
[i
].src_type
) {
8269 case nir_tex_src_coord
: {
8270 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8271 for (unsigned i
= 0; i
< coord
.size(); i
++)
8272 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8275 case nir_tex_src_bias
:
8276 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8279 case nir_tex_src_lod
: {
8280 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8282 if (val
&& val
->f32
<= 0.0) {
8285 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8290 case nir_tex_src_min_lod
:
8291 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8292 has_clamped_lod
= true;
8294 case nir_tex_src_comparator
:
8295 if (instr
->is_shadow
) {
8296 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8300 case nir_tex_src_offset
:
8301 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8302 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8305 case nir_tex_src_ddx
:
8306 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8309 case nir_tex_src_ddy
:
8310 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8313 case nir_tex_src_ms_index
:
8314 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8315 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8316 has_sample_index
= true;
8318 case nir_tex_src_texture_offset
:
8319 case nir_tex_src_sampler_offset
:
8325 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8326 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8328 if (instr
->op
== nir_texop_texture_samples
) {
8329 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8331 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8332 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8333 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8335 Operand default_sample
= Operand(1u);
8336 if (ctx
->options
->robust_buffer_access
) {
8337 /* Extract the second dword of the descriptor, if it's
8338 * all zero, then it's a null descriptor.
8340 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8341 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8342 default_sample
= Operand(is_non_null_descriptor
);
8345 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8346 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8347 samples
, default_sample
, bld
.scc(is_msaa
));
8351 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8352 aco_ptr
<Instruction
> tmp_instr
;
8353 Temp acc
, pack
= Temp();
8355 uint32_t pack_const
= 0;
8356 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8357 if (!const_offset
[i
])
8359 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8362 if (offset
.type() == RegType::sgpr
) {
8363 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8364 if (const_offset
[i
])
8367 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8368 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8371 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8374 if (pack
== Temp()) {
8377 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8381 if (pack_const
&& pack
!= Temp())
8382 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8384 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8385 if (const_offset
[i
])
8388 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8389 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8392 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8395 if (pack
== Temp()) {
8398 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8402 if (pack_const
&& pack
!= Temp())
8403 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8405 if (pack_const
&& pack
== Temp())
8406 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8407 else if (pack
== Temp())
8413 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8414 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8416 /* pack derivatives */
8417 if (has_ddx
|| has_ddy
) {
8418 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8419 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8420 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8421 derivs
= {ddx
, zero
, ddy
, zero
};
8423 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8424 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8425 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8426 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8431 if (instr
->coord_components
> 1 &&
8432 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8434 instr
->op
!= nir_texop_txf
)
8435 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8437 if (instr
->coord_components
> 2 &&
8438 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8439 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8440 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8441 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8443 instr
->op
!= nir_texop_txf
&&
8444 instr
->op
!= nir_texop_txf_ms
&&
8445 instr
->op
!= nir_texop_fragment_fetch
&&
8446 instr
->op
!= nir_texop_fragment_mask_fetch
)
8447 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8449 if (ctx
->options
->chip_class
== GFX9
&&
8450 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8451 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8452 assert(coords
.size() > 0 && coords
.size() < 3);
8454 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8455 Operand((uint32_t) 0) :
8456 Operand((uint32_t) 0x3f000000)));
8459 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8461 if (instr
->op
== nir_texop_samples_identical
)
8462 resource
= fmask_ptr
;
8464 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8465 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8466 instr
->op
!= nir_texop_txs
&&
8467 instr
->op
!= nir_texop_fragment_fetch
&&
8468 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8469 assert(has_sample_index
);
8470 Operand
op(sample_index
);
8471 if (sample_index_cv
)
8472 op
= Operand(sample_index_cv
->u32
);
8473 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8476 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8477 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8478 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8479 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8484 /* Build tex instruction */
8485 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8486 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8487 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8489 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8492 /* gather4 selects the component by dmask and always returns vec4 */
8493 if (instr
->op
== nir_texop_tg4
) {
8494 assert(instr
->dest
.ssa
.num_components
== 4);
8495 if (instr
->is_shadow
)
8498 dmask
= 1 << instr
->component
;
8499 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8500 tmp_dst
= bld
.tmp(v4
);
8501 } else if (instr
->op
== nir_texop_samples_identical
) {
8502 tmp_dst
= bld
.tmp(v1
);
8503 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8504 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8507 aco_ptr
<MIMG_instruction
> tex
;
8508 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8510 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8512 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8513 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8516 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8517 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8519 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8520 tex
->operands
[0] = Operand(resource
);
8521 tex
->operands
[1] = Operand(s4
); /* no sampler */
8522 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8523 if (ctx
->options
->chip_class
== GFX9
&&
8524 instr
->op
== nir_texop_txs
&&
8525 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8527 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8528 } else if (instr
->op
== nir_texop_query_levels
) {
8529 tex
->dmask
= 1 << 3;
8534 tex
->definitions
[0] = Definition(tmp_dst
);
8536 tex
->can_reorder
= true;
8537 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8540 /* divide 3rd value by 6 by multiplying with magic number */
8541 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8542 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8543 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8544 assert(instr
->dest
.ssa
.num_components
== 3);
8545 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8546 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8547 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8548 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8553 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8557 Temp tg4_compare_cube_wa64
= Temp();
8559 if (tg4_integer_workarounds
) {
8560 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8561 tex
->operands
[0] = Operand(resource
);
8562 tex
->operands
[1] = Operand(s4
); /* no sampler */
8563 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8567 Temp size
= bld
.tmp(v2
);
8568 tex
->definitions
[0] = Definition(size
);
8569 tex
->can_reorder
= true;
8570 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8571 emit_split_vector(ctx
, size
, size
.size());
8574 for (unsigned i
= 0; i
< 2; i
++) {
8575 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8576 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8577 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8578 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8581 Temp new_coords
[2] = {
8582 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8583 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8586 if (tg4_integer_cube_workaround
) {
8587 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8588 Temp desc
[resource
.size()];
8589 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8590 Format::PSEUDO
, 1, resource
.size())};
8591 split
->operands
[0] = Operand(resource
);
8592 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8593 desc
[i
] = bld
.tmp(s1
);
8594 split
->definitions
[i
] = Definition(desc
[i
]);
8596 ctx
->block
->instructions
.emplace_back(std::move(split
));
8598 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8599 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8600 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8603 if (stype
== GLSL_TYPE_UINT
) {
8604 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8605 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8606 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8607 bld
.scc(compare_cube_wa
));
8609 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8610 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8611 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8612 bld
.scc(compare_cube_wa
));
8614 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8615 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8617 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8619 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8620 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8621 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8623 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8624 Format::PSEUDO
, resource
.size(), 1)};
8625 for (unsigned i
= 0; i
< resource
.size(); i
++)
8626 vec
->operands
[i
] = Operand(desc
[i
]);
8627 resource
= bld
.tmp(resource
.regClass());
8628 vec
->definitions
[0] = Definition(resource
);
8629 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8631 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8632 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8633 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8634 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8636 coords
[0] = new_coords
[0];
8637 coords
[1] = new_coords
[1];
8640 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8641 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8643 assert(coords
.size() == 1);
8644 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8648 op
= aco_opcode::buffer_load_format_x
; break;
8650 op
= aco_opcode::buffer_load_format_xy
; break;
8652 op
= aco_opcode::buffer_load_format_xyz
; break;
8654 op
= aco_opcode::buffer_load_format_xyzw
; break;
8656 unreachable("Tex instruction loads more than 4 components.");
8659 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8660 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8663 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8665 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8666 mubuf
->operands
[0] = Operand(resource
);
8667 mubuf
->operands
[1] = Operand(coords
[0]);
8668 mubuf
->operands
[2] = Operand((uint32_t) 0);
8669 mubuf
->definitions
[0] = Definition(tmp_dst
);
8670 mubuf
->idxen
= true;
8671 mubuf
->can_reorder
= true;
8672 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8674 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8678 /* gather MIMG address components */
8679 std::vector
<Temp
> args
;
8681 args
.emplace_back(offset
);
8683 args
.emplace_back(bias
);
8685 args
.emplace_back(compare
);
8687 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8689 args
.insert(args
.end(), coords
.begin(), coords
.end());
8690 if (has_sample_index
)
8691 args
.emplace_back(sample_index
);
8693 args
.emplace_back(lod
);
8694 if (has_clamped_lod
)
8695 args
.emplace_back(clamped_lod
);
8697 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8698 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8699 vec
->definitions
[0] = Definition(arg
);
8700 for (unsigned i
= 0; i
< args
.size(); i
++)
8701 vec
->operands
[i
] = Operand(args
[i
]);
8702 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8705 if (instr
->op
== nir_texop_txf
||
8706 instr
->op
== nir_texop_txf_ms
||
8707 instr
->op
== nir_texop_samples_identical
||
8708 instr
->op
== nir_texop_fragment_fetch
||
8709 instr
->op
== nir_texop_fragment_mask_fetch
) {
8710 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8711 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8712 tex
->operands
[0] = Operand(resource
);
8713 tex
->operands
[1] = Operand(s4
); /* no sampler */
8714 tex
->operands
[2] = Operand(arg
);
8719 tex
->definitions
[0] = Definition(tmp_dst
);
8720 tex
->can_reorder
= true;
8721 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8723 if (instr
->op
== nir_texop_samples_identical
) {
8724 assert(dmask
== 1 && dst
.regClass() == v1
);
8725 assert(dst
.id() != tmp_dst
.id());
8727 Temp tmp
= bld
.tmp(bld
.lm
);
8728 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8729 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8732 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8737 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8738 aco_opcode opcode
= aco_opcode::image_sample
;
8739 if (has_offset
) { /* image_sample_*_o */
8740 if (has_clamped_lod
) {
8742 opcode
= aco_opcode::image_sample_c_cl_o
;
8744 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8746 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8748 opcode
= aco_opcode::image_sample_cl_o
;
8750 opcode
= aco_opcode::image_sample_d_cl_o
;
8752 opcode
= aco_opcode::image_sample_b_cl_o
;
8754 } else if (has_compare
) {
8755 opcode
= aco_opcode::image_sample_c_o
;
8757 opcode
= aco_opcode::image_sample_c_d_o
;
8759 opcode
= aco_opcode::image_sample_c_b_o
;
8761 opcode
= aco_opcode::image_sample_c_lz_o
;
8763 opcode
= aco_opcode::image_sample_c_l_o
;
8765 opcode
= aco_opcode::image_sample_o
;
8767 opcode
= aco_opcode::image_sample_d_o
;
8769 opcode
= aco_opcode::image_sample_b_o
;
8771 opcode
= aco_opcode::image_sample_lz_o
;
8773 opcode
= aco_opcode::image_sample_l_o
;
8775 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8777 opcode
= aco_opcode::image_sample_c_cl
;
8779 opcode
= aco_opcode::image_sample_c_d_cl
;
8781 opcode
= aco_opcode::image_sample_c_b_cl
;
8783 opcode
= aco_opcode::image_sample_cl
;
8785 opcode
= aco_opcode::image_sample_d_cl
;
8787 opcode
= aco_opcode::image_sample_b_cl
;
8789 } else { /* no offset */
8791 opcode
= aco_opcode::image_sample_c
;
8793 opcode
= aco_opcode::image_sample_c_d
;
8795 opcode
= aco_opcode::image_sample_c_b
;
8797 opcode
= aco_opcode::image_sample_c_lz
;
8799 opcode
= aco_opcode::image_sample_c_l
;
8801 opcode
= aco_opcode::image_sample
;
8803 opcode
= aco_opcode::image_sample_d
;
8805 opcode
= aco_opcode::image_sample_b
;
8807 opcode
= aco_opcode::image_sample_lz
;
8809 opcode
= aco_opcode::image_sample_l
;
8813 if (instr
->op
== nir_texop_tg4
) {
8814 if (has_offset
) { /* image_gather4_*_o */
8816 opcode
= aco_opcode::image_gather4_c_lz_o
;
8818 opcode
= aco_opcode::image_gather4_c_l_o
;
8820 opcode
= aco_opcode::image_gather4_c_b_o
;
8822 opcode
= aco_opcode::image_gather4_lz_o
;
8824 opcode
= aco_opcode::image_gather4_l_o
;
8826 opcode
= aco_opcode::image_gather4_b_o
;
8830 opcode
= aco_opcode::image_gather4_c_lz
;
8832 opcode
= aco_opcode::image_gather4_c_l
;
8834 opcode
= aco_opcode::image_gather4_c_b
;
8836 opcode
= aco_opcode::image_gather4_lz
;
8838 opcode
= aco_opcode::image_gather4_l
;
8840 opcode
= aco_opcode::image_gather4_b
;
8843 } else if (instr
->op
== nir_texop_lod
) {
8844 opcode
= aco_opcode::image_get_lod
;
8847 /* we don't need the bias, sample index, compare value or offset to be
8848 * computed in WQM but if the p_create_vector copies the coordinates, then it
8849 * needs to be in WQM */
8850 if (ctx
->stage
== fragment_fs
&&
8851 !has_derivs
&& !has_lod
&& !level_zero
&&
8852 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8853 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8854 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8856 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8857 tex
->operands
[0] = Operand(resource
);
8858 tex
->operands
[1] = Operand(sampler
);
8859 tex
->operands
[2] = Operand(arg
);
8863 tex
->definitions
[0] = Definition(tmp_dst
);
8864 tex
->can_reorder
= true;
8865 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8867 if (tg4_integer_cube_workaround
) {
8868 assert(tmp_dst
.id() != dst
.id());
8869 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8871 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8873 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8874 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8876 if (stype
== GLSL_TYPE_UINT
)
8877 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8879 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8880 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8882 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8883 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8884 val
[0], val
[1], val
[2], val
[3]);
8886 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8887 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8892 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8894 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8895 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8896 return Operand(tmp
.regClass());
8898 return Operand(tmp
);
8901 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8903 aco_ptr
<Pseudo_instruction
> phi
;
8904 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8905 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8907 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8908 logical
|= ctx
->block
->kind
& block_kind_merge
;
8909 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8911 /* we want a sorted list of sources, since the predecessor list is also sorted */
8912 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8913 nir_foreach_phi_src(src
, instr
)
8914 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8916 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8917 unsigned num_operands
= 0;
8918 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8919 unsigned num_defined
= 0;
8920 unsigned cur_pred_idx
= 0;
8921 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8922 if (cur_pred_idx
< preds
.size()) {
8923 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8924 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8925 unsigned skipped
= 0;
8926 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8928 if (cur_pred_idx
+ skipped
< preds
.size()) {
8929 for (unsigned i
= 0; i
< skipped
; i
++)
8930 operands
[num_operands
++] = Operand(dst
.regClass());
8931 cur_pred_idx
+= skipped
;
8936 /* Handle missing predecessors at the end. This shouldn't happen with loop
8937 * headers and we can't ignore these sources for loop header phis. */
8938 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8941 Operand op
= get_phi_operand(ctx
, src
.second
);
8942 operands
[num_operands
++] = op
;
8943 num_defined
+= !op
.isUndefined();
8945 /* handle block_kind_continue_or_break at loop exit blocks */
8946 while (cur_pred_idx
++ < preds
.size())
8947 operands
[num_operands
++] = Operand(dst
.regClass());
8949 /* If the loop ends with a break, still add a linear continue edge in case
8950 * that break is divergent or continue_or_break is used. We'll either remove
8951 * this operand later in visit_loop() if it's not necessary or replace the
8952 * undef with something correct. */
8953 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8954 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8955 nir_block
*last
= nir_loop_last_block(loop
);
8956 if (last
->successors
[0] != instr
->instr
.block
)
8957 operands
[num_operands
++] = Operand(RegClass());
8960 if (num_defined
== 0) {
8961 Builder
bld(ctx
->program
, ctx
->block
);
8962 if (dst
.regClass() == s1
) {
8963 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8964 } else if (dst
.regClass() == v1
) {
8965 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8967 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8968 for (unsigned i
= 0; i
< dst
.size(); i
++)
8969 vec
->operands
[i
] = Operand(0u);
8970 vec
->definitions
[0] = Definition(dst
);
8971 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8976 /* we can use a linear phi in some cases if one src is undef */
8977 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8978 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8980 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8981 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8982 assert(invert
->kind
& block_kind_invert
);
8984 unsigned then_block
= invert
->linear_preds
[0];
8986 Block
* insert_block
= NULL
;
8987 for (unsigned i
= 0; i
< num_operands
; i
++) {
8988 Operand op
= operands
[i
];
8989 if (op
.isUndefined())
8991 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8992 phi
->operands
[0] = op
;
8995 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8996 phi
->operands
[1] = Operand(dst
.regClass());
8997 phi
->definitions
[0] = Definition(dst
);
8998 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9002 /* try to scalarize vector phis */
9003 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9004 // TODO: scalarize linear phis on divergent ifs
9005 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9006 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9007 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9008 Operand src
= operands
[i
];
9009 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9010 can_scalarize
= false;
9012 if (can_scalarize
) {
9013 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9014 assert(dst
.size() % num_components
== 0);
9015 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9017 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9018 for (unsigned k
= 0; k
< num_components
; k
++) {
9019 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9020 for (unsigned i
= 0; i
< num_operands
; i
++) {
9021 Operand src
= operands
[i
];
9022 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9024 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9025 phi
->definitions
[0] = Definition(phi_dst
);
9026 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9027 new_vec
[k
] = phi_dst
;
9028 vec
->operands
[k
] = Operand(phi_dst
);
9030 vec
->definitions
[0] = Definition(dst
);
9031 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9032 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9037 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9038 for (unsigned i
= 0; i
< num_operands
; i
++)
9039 phi
->operands
[i
] = operands
[i
];
9040 phi
->definitions
[0] = Definition(dst
);
9041 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9045 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9047 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9049 assert(dst
.type() == RegType::sgpr
);
9051 if (dst
.size() == 1) {
9052 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9054 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9055 for (unsigned i
= 0; i
< dst
.size(); i
++)
9056 vec
->operands
[i
] = Operand(0u);
9057 vec
->definitions
[0] = Definition(dst
);
9058 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9062 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9064 Builder
bld(ctx
->program
, ctx
->block
);
9065 Block
*logical_target
;
9066 append_logical_end(ctx
->block
);
9067 unsigned idx
= ctx
->block
->index
;
9069 switch (instr
->type
) {
9070 case nir_jump_break
:
9071 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9072 add_logical_edge(idx
, logical_target
);
9073 ctx
->block
->kind
|= block_kind_break
;
9075 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9076 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9077 /* uniform break - directly jump out of the loop */
9078 ctx
->block
->kind
|= block_kind_uniform
;
9079 ctx
->cf_info
.has_branch
= true;
9080 bld
.branch(aco_opcode::p_branch
);
9081 add_linear_edge(idx
, logical_target
);
9084 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9085 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9087 case nir_jump_continue
:
9088 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9089 add_logical_edge(idx
, logical_target
);
9090 ctx
->block
->kind
|= block_kind_continue
;
9092 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9093 /* for potential uniform breaks after this continue,
9094 we must ensure that they are handled correctly */
9095 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9096 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9097 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9099 /* uniform continue - directly jump to the loop header */
9100 ctx
->block
->kind
|= block_kind_uniform
;
9101 ctx
->cf_info
.has_branch
= true;
9102 bld
.branch(aco_opcode::p_branch
);
9103 add_linear_edge(idx
, logical_target
);
9108 fprintf(stderr
, "Unknown NIR jump instr: ");
9109 nir_print_instr(&instr
->instr
, stderr
);
9110 fprintf(stderr
, "\n");
9114 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9115 ctx
->cf_info
.exec_potentially_empty_break
= true;
9116 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9119 /* remove critical edges from linear CFG */
9120 bld
.branch(aco_opcode::p_branch
);
9121 Block
* break_block
= ctx
->program
->create_and_insert_block();
9122 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9123 break_block
->kind
|= block_kind_uniform
;
9124 add_linear_edge(idx
, break_block
);
9125 /* the loop_header pointer might be invalidated by this point */
9126 if (instr
->type
== nir_jump_continue
)
9127 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9128 add_linear_edge(break_block
->index
, logical_target
);
9129 bld
.reset(break_block
);
9130 bld
.branch(aco_opcode::p_branch
);
9132 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9133 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9134 add_linear_edge(idx
, continue_block
);
9135 append_logical_start(continue_block
);
9136 ctx
->block
= continue_block
;
9140 void visit_block(isel_context
*ctx
, nir_block
*block
)
9142 nir_foreach_instr(instr
, block
) {
9143 switch (instr
->type
) {
9144 case nir_instr_type_alu
:
9145 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9147 case nir_instr_type_load_const
:
9148 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9150 case nir_instr_type_intrinsic
:
9151 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9153 case nir_instr_type_tex
:
9154 visit_tex(ctx
, nir_instr_as_tex(instr
));
9156 case nir_instr_type_phi
:
9157 visit_phi(ctx
, nir_instr_as_phi(instr
));
9159 case nir_instr_type_ssa_undef
:
9160 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9162 case nir_instr_type_deref
:
9164 case nir_instr_type_jump
:
9165 visit_jump(ctx
, nir_instr_as_jump(instr
));
9168 fprintf(stderr
, "Unknown NIR instr type: ");
9169 nir_print_instr(instr
, stderr
);
9170 fprintf(stderr
, "\n");
9175 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9176 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9181 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9182 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9184 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9185 RegClass rc
= vals
[0].regClass();
9187 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9189 unsigned next_pred
= 1;
9191 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9192 Block
& block
= ctx
->program
->blocks
[idx
];
9193 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9194 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9198 if (block
.kind
& block_kind_continue
) {
9199 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9204 bool all_same
= true;
9205 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9206 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9210 val
= vals
[block
.linear_preds
[0] - first
];
9212 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9213 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9214 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9215 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9216 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9217 phi
->definitions
[0] = Definition(val
.getTemp());
9218 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9220 vals
[idx
- first
] = val
;
9223 return vals
[last
- first
];
9226 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9228 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9229 append_logical_end(ctx
->block
);
9230 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9231 Builder
bld(ctx
->program
, ctx
->block
);
9232 bld
.branch(aco_opcode::p_branch
);
9233 unsigned loop_preheader_idx
= ctx
->block
->index
;
9235 Block loop_exit
= Block();
9236 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9237 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9239 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9240 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9241 loop_header
->kind
|= block_kind_loop_header
;
9242 add_edge(loop_preheader_idx
, loop_header
);
9243 ctx
->block
= loop_header
;
9245 /* emit loop body */
9246 unsigned loop_header_idx
= loop_header
->index
;
9247 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9248 append_logical_start(ctx
->block
);
9249 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9251 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9252 if (!ctx
->cf_info
.has_branch
) {
9253 append_logical_end(ctx
->block
);
9254 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9255 /* Discards can result in code running with an empty exec mask.
9256 * This would result in divergent breaks not ever being taken. As a
9257 * workaround, break the loop when the loop mask is empty instead of
9258 * always continuing. */
9259 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9260 unsigned block_idx
= ctx
->block
->index
;
9262 /* create helper blocks to avoid critical edges */
9263 Block
*break_block
= ctx
->program
->create_and_insert_block();
9264 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9265 break_block
->kind
= block_kind_uniform
;
9266 bld
.reset(break_block
);
9267 bld
.branch(aco_opcode::p_branch
);
9268 add_linear_edge(block_idx
, break_block
);
9269 add_linear_edge(break_block
->index
, &loop_exit
);
9271 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9272 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9273 continue_block
->kind
= block_kind_uniform
;
9274 bld
.reset(continue_block
);
9275 bld
.branch(aco_opcode::p_branch
);
9276 add_linear_edge(block_idx
, continue_block
);
9277 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9279 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9280 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9281 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9283 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9284 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9285 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9287 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9290 bld
.reset(ctx
->block
);
9291 bld
.branch(aco_opcode::p_branch
);
9294 /* Fixup phis in loop header from unreachable blocks.
9295 * has_branch/has_divergent_branch also indicates if the loop ends with a
9296 * break/continue instruction, but we don't emit those if unreachable=true */
9298 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9299 bool linear
= ctx
->cf_info
.has_branch
;
9300 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9301 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9302 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9303 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9304 /* the last operand should be the one that needs to be removed */
9305 instr
->operands
.pop_back();
9306 } else if (!is_phi(instr
)) {
9312 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9313 * and the previous one shouldn't both happen at once because a break in the
9314 * merge block would get CSE'd */
9315 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9316 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9317 Operand vals
[num_vals
];
9318 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9319 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9320 if (ctx
->cf_info
.has_branch
)
9321 instr
->operands
.pop_back();
9323 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9324 } else if (!is_phi(instr
)) {
9330 ctx
->cf_info
.has_branch
= false;
9332 // TODO: if the loop has not a single exit, we must add one °°
9333 /* emit loop successor block */
9334 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9335 append_logical_start(ctx
->block
);
9338 // TODO: check if it is beneficial to not branch on continues
9339 /* trim linear phis in loop header */
9340 for (auto&& instr
: loop_entry
->instructions
) {
9341 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9342 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9343 new_phi
->definitions
[0] = instr
->definitions
[0];
9344 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9345 new_phi
->operands
[i
] = instr
->operands
[i
];
9346 /* check that the remaining operands are all the same */
9347 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9348 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9349 instr
.swap(new_phi
);
9350 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9359 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9363 append_logical_end(ctx
->block
);
9364 ctx
->block
->kind
|= block_kind_branch
;
9366 /* branch to linear then block */
9367 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9368 aco_ptr
<Pseudo_branch_instruction
> branch
;
9369 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9370 branch
->operands
[0] = Operand(cond
);
9371 ctx
->block
->instructions
.push_back(std::move(branch
));
9373 ic
->BB_if_idx
= ctx
->block
->index
;
9374 ic
->BB_invert
= Block();
9375 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9376 /* Invert blocks are intentionally not marked as top level because they
9377 * are not part of the logical cfg. */
9378 ic
->BB_invert
.kind
|= block_kind_invert
;
9379 ic
->BB_endif
= Block();
9380 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9381 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9383 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9384 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9385 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9386 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9387 ctx
->cf_info
.parent_if
.is_divergent
= true;
9389 /* divergent branches use cbranch_execz */
9390 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9391 ctx
->cf_info
.exec_potentially_empty_break
= false;
9392 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9394 /** emit logical then block */
9395 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9396 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9397 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9398 ctx
->block
= BB_then_logical
;
9399 append_logical_start(BB_then_logical
);
9402 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9404 Block
*BB_then_logical
= ctx
->block
;
9405 append_logical_end(BB_then_logical
);
9406 /* branch from logical then block to invert block */
9407 aco_ptr
<Pseudo_branch_instruction
> branch
;
9408 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9409 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9410 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9411 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9412 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9413 BB_then_logical
->kind
|= block_kind_uniform
;
9414 assert(!ctx
->cf_info
.has_branch
);
9415 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9416 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9418 /** emit linear then block */
9419 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9420 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9421 BB_then_linear
->kind
|= block_kind_uniform
;
9422 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9423 /* branch from linear then block to invert block */
9424 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9425 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9426 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9428 /** emit invert merge block */
9429 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9430 ic
->invert_idx
= ctx
->block
->index
;
9432 /* branch to linear else block (skip else) */
9433 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9434 branch
->operands
[0] = Operand(ic
->cond
);
9435 ctx
->block
->instructions
.push_back(std::move(branch
));
9437 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9438 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9439 ic
->exec_potentially_empty_break_depth_old
=
9440 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9441 /* divergent branches use cbranch_execz */
9442 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9443 ctx
->cf_info
.exec_potentially_empty_break
= false;
9444 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9446 /** emit logical else block */
9447 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9448 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9449 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9450 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9451 ctx
->block
= BB_else_logical
;
9452 append_logical_start(BB_else_logical
);
9455 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9457 Block
*BB_else_logical
= ctx
->block
;
9458 append_logical_end(BB_else_logical
);
9460 /* branch from logical else block to endif block */
9461 aco_ptr
<Pseudo_branch_instruction
> branch
;
9462 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9463 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9464 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9465 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9466 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9467 BB_else_logical
->kind
|= block_kind_uniform
;
9469 assert(!ctx
->cf_info
.has_branch
);
9470 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9473 /** emit linear else block */
9474 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9475 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9476 BB_else_linear
->kind
|= block_kind_uniform
;
9477 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9479 /* branch from linear else block to endif block */
9480 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9481 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9482 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9485 /** emit endif merge block */
9486 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9487 append_logical_start(ctx
->block
);
9490 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9491 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9492 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9493 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9494 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9495 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9496 !ctx
->cf_info
.parent_if
.is_divergent
) {
9497 ctx
->cf_info
.exec_potentially_empty_break
= false;
9498 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9500 /* uniform control flow never has an empty exec-mask */
9501 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9502 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9503 ctx
->cf_info
.exec_potentially_empty_break
= false;
9504 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9508 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9510 assert(cond
.regClass() == s1
);
9512 append_logical_end(ctx
->block
);
9513 ctx
->block
->kind
|= block_kind_uniform
;
9515 aco_ptr
<Pseudo_branch_instruction
> branch
;
9516 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9517 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9518 branch
->operands
[0] = Operand(cond
);
9519 branch
->operands
[0].setFixed(scc
);
9520 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9522 ic
->BB_if_idx
= ctx
->block
->index
;
9523 ic
->BB_endif
= Block();
9524 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9525 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9527 ctx
->cf_info
.has_branch
= false;
9528 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9530 /** emit then block */
9531 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9532 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9533 add_edge(ic
->BB_if_idx
, BB_then
);
9534 append_logical_start(BB_then
);
9535 ctx
->block
= BB_then
;
9538 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9540 Block
*BB_then
= ctx
->block
;
9542 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9543 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9545 if (!ic
->uniform_has_then_branch
) {
9546 append_logical_end(BB_then
);
9547 /* branch from then block to endif block */
9548 aco_ptr
<Pseudo_branch_instruction
> branch
;
9549 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9550 BB_then
->instructions
.emplace_back(std::move(branch
));
9551 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9552 if (!ic
->then_branch_divergent
)
9553 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9554 BB_then
->kind
|= block_kind_uniform
;
9557 ctx
->cf_info
.has_branch
= false;
9558 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9560 /** emit else block */
9561 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9562 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9563 add_edge(ic
->BB_if_idx
, BB_else
);
9564 append_logical_start(BB_else
);
9565 ctx
->block
= BB_else
;
9568 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9570 Block
*BB_else
= ctx
->block
;
9572 if (!ctx
->cf_info
.has_branch
) {
9573 append_logical_end(BB_else
);
9574 /* branch from then block to endif block */
9575 aco_ptr
<Pseudo_branch_instruction
> branch
;
9576 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9577 BB_else
->instructions
.emplace_back(std::move(branch
));
9578 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9579 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9580 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9581 BB_else
->kind
|= block_kind_uniform
;
9584 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9585 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9587 /** emit endif merge block */
9588 if (!ctx
->cf_info
.has_branch
) {
9589 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9590 append_logical_start(ctx
->block
);
9594 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9596 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9597 Builder
bld(ctx
->program
, ctx
->block
);
9598 aco_ptr
<Pseudo_branch_instruction
> branch
;
9601 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9603 * Uniform conditionals are represented in the following way*) :
9605 * The linear and logical CFG:
9608 * BB_THEN (logical) BB_ELSE (logical)
9612 * *) Exceptions may be due to break and continue statements within loops
9613 * If a break/continue happens within uniform control flow, it branches
9614 * to the loop exit/entry block. Otherwise, it branches to the next
9618 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9619 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9620 cond
= bool_to_scalar_condition(ctx
, cond
);
9622 begin_uniform_if_then(ctx
, &ic
, cond
);
9623 visit_cf_list(ctx
, &if_stmt
->then_list
);
9625 begin_uniform_if_else(ctx
, &ic
);
9626 visit_cf_list(ctx
, &if_stmt
->else_list
);
9628 end_uniform_if(ctx
, &ic
);
9629 } else { /* non-uniform condition */
9631 * To maintain a logical and linear CFG without critical edges,
9632 * non-uniform conditionals are represented in the following way*) :
9637 * BB_THEN (logical) BB_THEN (linear)
9639 * BB_INVERT (linear)
9641 * BB_ELSE (logical) BB_ELSE (linear)
9648 * BB_THEN (logical) BB_ELSE (logical)
9652 * *) Exceptions may be due to break and continue statements within loops
9655 begin_divergent_if_then(ctx
, &ic
, cond
);
9656 visit_cf_list(ctx
, &if_stmt
->then_list
);
9658 begin_divergent_if_else(ctx
, &ic
);
9659 visit_cf_list(ctx
, &if_stmt
->else_list
);
9661 end_divergent_if(ctx
, &ic
);
9664 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9667 static bool visit_cf_list(isel_context
*ctx
,
9668 struct exec_list
*list
)
9670 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9671 switch (node
->type
) {
9672 case nir_cf_node_block
:
9673 visit_block(ctx
, nir_cf_node_as_block(node
));
9675 case nir_cf_node_if
:
9676 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9679 case nir_cf_node_loop
:
9680 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9683 unreachable("unimplemented cf list type");
9689 static void create_null_export(isel_context
*ctx
)
9691 /* Some shader stages always need to have exports.
9692 * So when there is none, we need to add a null export.
9695 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9696 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9697 Builder
bld(ctx
->program
, ctx
->block
);
9698 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9699 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9702 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9704 assert(ctx
->stage
== vertex_vs
||
9705 ctx
->stage
== tess_eval_vs
||
9706 ctx
->stage
== gs_copy_vs
||
9707 ctx
->stage
== ngg_vertex_gs
||
9708 ctx
->stage
== ngg_tess_eval_gs
);
9710 int offset
= (ctx
->stage
& sw_tes
)
9711 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9712 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9713 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9714 if (!is_pos
&& !mask
)
9716 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9718 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9719 exp
->enabled_mask
= mask
;
9720 for (unsigned i
= 0; i
< 4; ++i
) {
9721 if (mask
& (1 << i
))
9722 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9724 exp
->operands
[i
] = Operand(v1
);
9726 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9727 * Setting valid_mask=1 prevents it and has no other effect.
9729 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9731 exp
->compressed
= false;
9733 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9735 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9736 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9741 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9743 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9744 exp
->enabled_mask
= 0;
9745 for (unsigned i
= 0; i
< 4; ++i
)
9746 exp
->operands
[i
] = Operand(v1
);
9747 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9748 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9749 exp
->enabled_mask
|= 0x1;
9751 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9752 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9753 exp
->enabled_mask
|= 0x4;
9755 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9756 if (ctx
->options
->chip_class
< GFX9
) {
9757 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9758 exp
->enabled_mask
|= 0x8;
9760 Builder
bld(ctx
->program
, ctx
->block
);
9762 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9763 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9764 if (exp
->operands
[2].isTemp())
9765 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9767 exp
->operands
[2] = Operand(out
);
9768 exp
->enabled_mask
|= 0x4;
9771 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9773 exp
->compressed
= false;
9774 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9775 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9778 static void create_export_phis(isel_context
*ctx
)
9780 /* Used when exports are needed, but the output temps are defined in a preceding block.
9781 * This function will set up phis in order to access the outputs in the next block.
9784 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9785 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9786 ctx
->block
->instructions
.pop_back();
9788 Builder
bld(ctx
->program
, ctx
->block
);
9790 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9791 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9792 for (unsigned i
= 0; i
< 4; ++i
) {
9793 if (!(mask
& (1 << i
)))
9796 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9797 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9798 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9802 bld
.insert(std::move(logical_start
));
9805 static void create_vs_exports(isel_context
*ctx
)
9807 assert(ctx
->stage
== vertex_vs
||
9808 ctx
->stage
== tess_eval_vs
||
9809 ctx
->stage
== gs_copy_vs
||
9810 ctx
->stage
== ngg_vertex_gs
||
9811 ctx
->stage
== ngg_tess_eval_gs
);
9813 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9814 ? &ctx
->program
->info
->tes
.outinfo
9815 : &ctx
->program
->info
->vs
.outinfo
;
9817 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9818 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9819 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9822 if (ctx
->options
->key
.has_multiview_view_index
) {
9823 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9824 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9827 /* the order these position exports are created is important */
9829 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9830 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9831 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9832 exported_pos
= true;
9834 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9835 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9836 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9837 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9839 if (ctx
->export_clip_dists
) {
9840 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9841 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9842 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9843 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9846 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9847 if (i
< VARYING_SLOT_VAR0
&&
9848 i
!= VARYING_SLOT_LAYER
&&
9849 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9850 i
!= VARYING_SLOT_VIEWPORT
)
9853 export_vs_varying(ctx
, i
, false, NULL
);
9857 create_null_export(ctx
);
9860 static bool export_fs_mrt_z(isel_context
*ctx
)
9862 Builder
bld(ctx
->program
, ctx
->block
);
9863 unsigned enabled_channels
= 0;
9867 for (unsigned i
= 0; i
< 4; ++i
) {
9868 values
[i
] = Operand(v1
);
9871 /* Both stencil and sample mask only need 16-bits. */
9872 if (!ctx
->program
->info
->ps
.writes_z
&&
9873 (ctx
->program
->info
->ps
.writes_stencil
||
9874 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9875 compr
= true; /* COMPR flag */
9877 if (ctx
->program
->info
->ps
.writes_stencil
) {
9878 /* Stencil should be in X[23:16]. */
9879 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9880 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9881 enabled_channels
|= 0x3;
9884 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9885 /* SampleMask should be in Y[15:0]. */
9886 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9887 enabled_channels
|= 0xc;
9890 if (ctx
->program
->info
->ps
.writes_z
) {
9891 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9892 enabled_channels
|= 0x1;
9895 if (ctx
->program
->info
->ps
.writes_stencil
) {
9896 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9897 enabled_channels
|= 0x2;
9900 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9901 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9902 enabled_channels
|= 0x4;
9906 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9907 * writemask component.
9909 if (ctx
->options
->chip_class
== GFX6
&&
9910 ctx
->options
->family
!= CHIP_OLAND
&&
9911 ctx
->options
->family
!= CHIP_HAINAN
) {
9912 enabled_channels
|= 0x1;
9915 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9916 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9921 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9923 Builder
bld(ctx
->program
, ctx
->block
);
9924 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9927 for (unsigned i
= 0; i
< 4; ++i
) {
9928 if (write_mask
& (1 << i
)) {
9929 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9931 values
[i
] = Operand(v1
);
9935 unsigned target
, col_format
;
9936 unsigned enabled_channels
= 0;
9937 aco_opcode compr_op
= (aco_opcode
)0;
9939 slot
-= FRAG_RESULT_DATA0
;
9940 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9941 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9943 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9944 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9945 bool is_16bit
= values
[0].regClass() == v2b
;
9949 case V_028714_SPI_SHADER_ZERO
:
9950 enabled_channels
= 0; /* writemask */
9951 target
= V_008DFC_SQ_EXP_NULL
;
9954 case V_028714_SPI_SHADER_32_R
:
9955 enabled_channels
= 1;
9958 case V_028714_SPI_SHADER_32_GR
:
9959 enabled_channels
= 0x3;
9962 case V_028714_SPI_SHADER_32_AR
:
9963 if (ctx
->options
->chip_class
>= GFX10
) {
9964 /* Special case: on GFX10, the outputs are different for 32_AR */
9965 enabled_channels
= 0x3;
9966 values
[1] = values
[3];
9967 values
[3] = Operand(v1
);
9969 enabled_channels
= 0x9;
9973 case V_028714_SPI_SHADER_FP16_ABGR
:
9974 enabled_channels
= 0x5;
9975 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9977 if (ctx
->options
->chip_class
>= GFX9
) {
9978 /* Pack the FP16 values together instead of converting them to
9979 * FP32 and back to FP16.
9980 * TODO: use p_create_vector and let the compiler optimizes.
9982 compr_op
= aco_opcode::v_pack_b32_f16
;
9984 for (unsigned i
= 0; i
< 4; i
++) {
9985 if ((write_mask
>> i
) & 1)
9986 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9992 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9993 enabled_channels
= 0x5;
9994 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9995 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9997 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10001 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10002 enabled_channels
= 0x5;
10003 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10004 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10006 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10010 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10011 enabled_channels
= 0x5;
10012 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10013 if (is_int8
|| is_int10
) {
10015 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10016 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10018 for (unsigned i
= 0; i
< 4; i
++) {
10019 if ((write_mask
>> i
) & 1) {
10020 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10021 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10025 } else if (is_16bit
) {
10026 for (unsigned i
= 0; i
< 4; i
++) {
10027 if ((write_mask
>> i
) & 1) {
10028 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10029 values
[i
] = Operand(tmp
);
10036 case V_028714_SPI_SHADER_SINT16_ABGR
:
10037 enabled_channels
= 0x5;
10038 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10039 if (is_int8
|| is_int10
) {
10041 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10042 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10043 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10044 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10046 for (unsigned i
= 0; i
< 4; i
++) {
10047 if ((write_mask
>> i
) & 1) {
10048 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10049 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10051 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10052 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10056 } else if (is_16bit
) {
10057 for (unsigned i
= 0; i
< 4; i
++) {
10058 if ((write_mask
>> i
) & 1) {
10059 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10060 values
[i
] = Operand(tmp
);
10066 case V_028714_SPI_SHADER_32_ABGR
:
10067 enabled_channels
= 0xF;
10074 if (target
== V_008DFC_SQ_EXP_NULL
)
10077 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10078 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10080 (col_format
== V_028714_SPI_SHADER_32_R
||
10081 col_format
== V_028714_SPI_SHADER_32_GR
||
10082 col_format
== V_028714_SPI_SHADER_32_AR
||
10083 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10084 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10085 for (int i
= 0; i
< 4; i
++) {
10086 if (!(write_mask
& (1 << i
)))
10089 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10090 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10091 bld
.copy(bld
.def(v1
), Operand(3u)));
10092 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10093 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10097 if ((bool) compr_op
) {
10098 for (int i
= 0; i
< 2; i
++) {
10099 /* check if at least one of the values to be compressed is enabled */
10100 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10102 enabled_channels
|= enabled
<< (i
*2);
10103 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10104 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10105 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10107 values
[i
] = Operand(v1
);
10110 values
[2] = Operand(v1
);
10111 values
[3] = Operand(v1
);
10113 for (int i
= 0; i
< 4; i
++)
10114 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10117 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10118 enabled_channels
, target
, (bool) compr_op
);
10122 static void create_fs_exports(isel_context
*ctx
)
10124 bool exported
= false;
10126 /* Export depth, stencil and sample mask. */
10127 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10128 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10129 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10130 exported
|= export_fs_mrt_z(ctx
);
10132 /* Export all color render targets. */
10133 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10134 if (ctx
->outputs
.mask
[i
])
10135 exported
|= export_fs_mrt_color(ctx
, i
);
10138 create_null_export(ctx
);
10141 static void write_tcs_tess_factors(isel_context
*ctx
)
10143 unsigned outer_comps
;
10144 unsigned inner_comps
;
10146 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10163 Builder
bld(ctx
->program
, ctx
->block
);
10165 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10166 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10167 bld
.sopp(aco_opcode::s_barrier
);
10169 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10170 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10172 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10173 if_context ic_invocation_id_is_zero
;
10174 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10175 bld
.reset(ctx
->block
);
10177 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10179 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10180 unsigned stride
= inner_comps
+ outer_comps
;
10181 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10185 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10187 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10189 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10190 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10191 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10193 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10194 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10196 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10197 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10198 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10199 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10202 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10203 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10204 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10205 unsigned tf_const_offset
= 0;
10207 if (ctx
->program
->chip_class
<= GFX8
) {
10208 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10209 if_context ic_rel_patch_id_is_zero
;
10210 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10211 bld
.reset(ctx
->block
);
10213 /* Store the dynamic HS control word. */
10214 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10215 bld
.mubuf(aco_opcode::buffer_store_dword
,
10216 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10217 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10218 /* disable_wqm */ false, /* glc */ true);
10219 tf_const_offset
+= 4;
10221 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10222 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10223 bld
.reset(ctx
->block
);
10226 assert(stride
== 2 || stride
== 4 || stride
== 6);
10227 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10228 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10230 /* Store to offchip for TES to read - only if TES reads them */
10231 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10232 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10233 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10235 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10236 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10238 if (likely(inner_comps
)) {
10239 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10240 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10244 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10245 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10248 static void emit_stream_output(isel_context
*ctx
,
10249 Temp
const *so_buffers
,
10250 Temp
const *so_write_offset
,
10251 const struct radv_stream_output
*output
)
10253 unsigned num_comps
= util_bitcount(output
->component_mask
);
10254 unsigned writemask
= (1 << num_comps
) - 1;
10255 unsigned loc
= output
->location
;
10256 unsigned buf
= output
->buffer
;
10258 assert(num_comps
&& num_comps
<= 4);
10259 if (!num_comps
|| num_comps
> 4)
10262 unsigned start
= ffs(output
->component_mask
) - 1;
10265 bool all_undef
= true;
10266 assert(ctx
->stage
& hw_vs
);
10267 for (unsigned i
= 0; i
< num_comps
; i
++) {
10268 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10269 all_undef
= all_undef
&& !out
[i
].id();
10274 while (writemask
) {
10276 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10277 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10278 /* GFX6 doesn't support storing vec3, split it. */
10279 writemask
|= 1u << (start
+ 2);
10283 unsigned offset
= output
->offset
+ start
* 4;
10285 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10286 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10287 for (int i
= 0; i
< count
; ++i
)
10288 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10289 vec
->definitions
[0] = Definition(write_data
);
10290 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10295 opcode
= aco_opcode::buffer_store_dword
;
10298 opcode
= aco_opcode::buffer_store_dwordx2
;
10301 opcode
= aco_opcode::buffer_store_dwordx3
;
10304 opcode
= aco_opcode::buffer_store_dwordx4
;
10307 unreachable("Unsupported dword count.");
10310 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10311 store
->operands
[0] = Operand(so_buffers
[buf
]);
10312 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10313 store
->operands
[2] = Operand((uint32_t) 0);
10314 store
->operands
[3] = Operand(write_data
);
10315 if (offset
> 4095) {
10316 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10317 Builder
bld(ctx
->program
, ctx
->block
);
10318 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10320 store
->offset
= offset
;
10322 store
->offen
= true;
10324 store
->dlc
= false;
10326 store
->can_reorder
= true;
10327 ctx
->block
->instructions
.emplace_back(std::move(store
));
10331 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10333 Builder
bld(ctx
->program
, ctx
->block
);
10335 Temp so_buffers
[4];
10336 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10337 for (unsigned i
= 0; i
< 4; i
++) {
10338 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10342 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10343 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10346 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10347 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10349 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10351 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10354 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10356 bld
.reset(ctx
->block
);
10358 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10360 Temp so_write_offset
[4];
10362 for (unsigned i
= 0; i
< 4; i
++) {
10363 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10368 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10369 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10370 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10371 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10373 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10375 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10376 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10377 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10378 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10382 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10383 struct radv_stream_output
*output
=
10384 &ctx
->program
->info
->so
.outputs
[i
];
10385 if (stream
!= output
->stream
)
10388 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10391 begin_divergent_if_else(ctx
, &ic
);
10392 end_divergent_if(ctx
, &ic
);
10395 } /* end namespace */
10397 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10399 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10400 Builder
bld(ctx
->program
, ctx
->block
);
10401 constexpr unsigned hs_idx
= 1u;
10402 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10403 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10404 Operand((8u << 16) | (hs_idx
* 8u)));
10405 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10407 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10409 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10410 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10411 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10412 ls_has_nonzero_hs_threads
);
10413 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10414 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10415 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10416 ls_has_nonzero_hs_threads
);
10417 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10418 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10419 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10420 ls_has_nonzero_hs_threads
);
10422 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10423 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10424 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10427 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10429 /* Split all arguments except for the first (ring_offsets) and the last
10430 * (exec) so that the dead channels don't stay live throughout the program.
10432 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10433 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10434 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10435 startpgm
->definitions
[i
].regClass().size());
10440 void handle_bc_optimize(isel_context
*ctx
)
10442 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10443 Builder
bld(ctx
->program
, ctx
->block
);
10444 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10445 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10446 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10447 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10448 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10449 if (uses_center
&& uses_centroid
) {
10450 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10451 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10453 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10455 for (unsigned i
= 0; i
< 2; i
++) {
10456 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10457 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10458 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10459 persp_centroid
, persp_center
, sel
);
10461 ctx
->persp_centroid
= bld
.tmp(v2
);
10462 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10463 Operand(new_coord
[0]), Operand(new_coord
[1]));
10464 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10467 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10469 for (unsigned i
= 0; i
< 2; i
++) {
10470 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10471 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10472 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10473 linear_centroid
, linear_center
, sel
);
10475 ctx
->linear_centroid
= bld
.tmp(v2
);
10476 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10477 Operand(new_coord
[0]), Operand(new_coord
[1]));
10478 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10483 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10485 Program
*program
= ctx
->program
;
10487 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10489 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10490 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10491 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10492 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10493 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10495 program
->next_fp_mode
.must_flush_denorms32
=
10496 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10497 program
->next_fp_mode
.must_flush_denorms16_64
=
10498 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10499 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10501 program
->next_fp_mode
.care_about_round32
=
10502 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10504 program
->next_fp_mode
.care_about_round16_64
=
10505 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10506 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10508 /* default to preserving fp16 and fp64 denorms, since it's free */
10509 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10510 program
->next_fp_mode
.denorm16_64
= 0;
10512 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10514 /* preserving fp32 denorms is expensive, so only do it if asked */
10515 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10516 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10518 program
->next_fp_mode
.denorm32
= 0;
10520 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10521 program
->next_fp_mode
.round32
= fp_round_tz
;
10523 program
->next_fp_mode
.round32
= fp_round_ne
;
10525 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10526 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10528 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10530 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10533 void cleanup_cfg(Program
*program
)
10535 /* create linear_succs/logical_succs */
10536 for (Block
& BB
: program
->blocks
) {
10537 for (unsigned idx
: BB
.linear_preds
)
10538 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10539 for (unsigned idx
: BB
.logical_preds
)
10540 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10544 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10546 Builder
bld(ctx
->program
, ctx
->block
);
10548 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10549 Temp count
= i
== 0
10550 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10551 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10552 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10554 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10557 if (ctx
->program
->wave_size
== 64) {
10558 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10559 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10560 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10562 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10563 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10569 bool ngg_early_prim_export(isel_context
*ctx
)
10571 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10575 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10577 Builder
bld(ctx
->program
, ctx
->block
);
10579 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10580 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10582 /* Get the id of the current wave within the threadgroup (workgroup) */
10583 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10584 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10586 /* Execute the following code only on the first wave (wave id 0),
10587 * use the SCC def to tell if the wave id is zero or not.
10589 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10591 begin_uniform_if_then(ctx
, &ic
, cond
);
10592 begin_uniform_if_else(ctx
, &ic
);
10593 bld
.reset(ctx
->block
);
10595 /* Number of vertices output by VS/TES */
10596 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10597 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10598 /* Number of primitives output by VS/TES */
10599 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10600 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10602 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10603 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10604 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10606 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10607 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10609 end_uniform_if(ctx
, &ic
);
10611 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10612 bld
.reset(ctx
->block
);
10613 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10616 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10618 Builder
bld(ctx
->program
, ctx
->block
);
10620 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10621 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10624 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10627 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10628 assert(vtxindex
[i
].id());
10631 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10635 /* The initial edge flag is always false in tess eval shaders. */
10636 if (ctx
->stage
== ngg_vertex_gs
) {
10637 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10638 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10642 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10647 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10649 Builder
bld(ctx
->program
, ctx
->block
);
10650 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10652 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10653 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10654 false /* compressed */, true/* done */, false /* valid mask */);
10657 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10659 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10660 * These must always come before VS exports.
10662 * It is recommended to do these as early as possible. They can be at the beginning when
10663 * there is no SW GS and the shader doesn't write edge flags.
10667 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10668 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10670 Builder
bld(ctx
->program
, ctx
->block
);
10671 constexpr unsigned max_vertices_per_primitive
= 3;
10672 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10674 if (ctx
->stage
== ngg_vertex_gs
) {
10675 /* TODO: optimize for points & lines */
10676 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10677 if (ctx
->shader
->info
.tess
.point_mode
)
10678 num_vertices_per_primitive
= 1;
10679 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10680 num_vertices_per_primitive
= 2;
10682 unreachable("Unsupported NGG shader stage");
10685 Temp vtxindex
[max_vertices_per_primitive
];
10686 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10687 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10688 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10689 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10690 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10691 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10692 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10693 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10695 /* Export primitive data to the index buffer. */
10696 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10698 /* Export primitive ID. */
10699 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10700 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10701 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10702 Temp provoking_vtx_index
= vtxindex
[0];
10703 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10705 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10708 begin_divergent_if_else(ctx
, &ic
);
10709 end_divergent_if(ctx
, &ic
);
10712 void ngg_emit_nogs_output(isel_context
*ctx
)
10714 /* Emits NGG GS output, for stages that don't have SW GS. */
10717 Builder
bld(ctx
->program
, ctx
->block
);
10718 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10720 /* NGG streamout is currently disabled by default. */
10721 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10723 if (late_prim_export
) {
10724 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10725 create_export_phis(ctx
);
10726 /* Do what we need to do in the GS threads. */
10727 ngg_emit_nogs_gsthreads(ctx
);
10729 /* What comes next should be executed on ES threads. */
10730 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10731 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10732 bld
.reset(ctx
->block
);
10735 /* Export VS outputs */
10736 ctx
->block
->kind
|= block_kind_export_end
;
10737 create_vs_exports(ctx
);
10739 /* Export primitive ID */
10740 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10743 if (ctx
->stage
== ngg_vertex_gs
) {
10744 /* Wait for GS threads to store primitive ID in LDS. */
10745 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10746 bld
.sopp(aco_opcode::s_barrier
);
10748 /* Calculate LDS address where the GS threads stored the primitive ID. */
10749 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10750 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10751 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10752 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10753 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10754 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10756 /* Load primitive ID from LDS. */
10757 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10758 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10759 /* TES: Just use the patch ID as the primitive ID. */
10760 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10762 unreachable("unsupported NGG shader stage.");
10765 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10766 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10768 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10771 if (late_prim_export
) {
10772 begin_divergent_if_else(ctx
, &ic
);
10773 end_divergent_if(ctx
, &ic
);
10774 bld
.reset(ctx
->block
);
10778 void select_program(Program
*program
,
10779 unsigned shader_count
,
10780 struct nir_shader
*const *shaders
,
10781 ac_shader_config
* config
,
10782 struct radv_shader_args
*args
)
10784 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10785 if_context ic_merged_wave_info
;
10786 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10788 for (unsigned i
= 0; i
< shader_count
; i
++) {
10789 nir_shader
*nir
= shaders
[i
];
10790 init_context(&ctx
, nir
);
10792 setup_fp_mode(&ctx
, nir
);
10795 /* needs to be after init_context() for FS */
10796 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10797 append_logical_start(ctx
.block
);
10799 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10800 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10802 split_arguments(&ctx
, startpgm
);
10806 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10808 if (ngg_early_prim_export(&ctx
))
10809 ngg_emit_nogs_gsthreads(&ctx
);
10812 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10813 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10814 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10815 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10816 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10817 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10818 ctx
.stage
== tess_eval_geometry_gs
));
10820 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10821 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10822 if (check_merged_wave_info
) {
10823 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10824 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10828 Builder
bld(ctx
.program
, ctx
.block
);
10830 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10831 bld
.sopp(aco_opcode::s_barrier
);
10833 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10834 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10836 } else if (ctx
.stage
== geometry_gs
)
10837 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10839 if (ctx
.stage
== fragment_fs
)
10840 handle_bc_optimize(&ctx
);
10842 visit_cf_list(&ctx
, &func
->body
);
10844 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10845 emit_streamout(&ctx
, 0);
10847 if (ctx
.stage
& hw_vs
) {
10848 create_vs_exports(&ctx
);
10849 ctx
.block
->kind
|= block_kind_export_end
;
10850 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10851 ngg_emit_nogs_output(&ctx
);
10852 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10853 Builder
bld(ctx
.program
, ctx
.block
);
10854 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10855 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10856 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10857 write_tcs_tess_factors(&ctx
);
10860 if (ctx
.stage
== fragment_fs
) {
10861 create_fs_exports(&ctx
);
10862 ctx
.block
->kind
|= block_kind_export_end
;
10865 if (endif_merged_wave_info
) {
10866 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10867 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10870 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10871 ngg_emit_nogs_output(&ctx
);
10873 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10874 /* Outputs of the previous stage are inputs to the next stage */
10875 ctx
.inputs
= ctx
.outputs
;
10876 ctx
.outputs
= shader_io_state();
10880 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10882 append_logical_end(ctx
.block
);
10883 ctx
.block
->kind
|= block_kind_uniform
;
10884 Builder
bld(ctx
.program
, ctx
.block
);
10885 if (ctx
.program
->wb_smem_l1_on_end
)
10886 bld
.smem(aco_opcode::s_dcache_wb
, false);
10887 bld
.sopp(aco_opcode::s_endpgm
);
10889 cleanup_cfg(program
);
10892 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10893 ac_shader_config
* config
,
10894 struct radv_shader_args
*args
)
10896 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10898 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10899 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10900 program
->next_fp_mode
.must_flush_denorms32
= false;
10901 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10902 program
->next_fp_mode
.care_about_round32
= false;
10903 program
->next_fp_mode
.care_about_round16_64
= false;
10904 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10905 program
->next_fp_mode
.denorm32
= 0;
10906 program
->next_fp_mode
.round32
= fp_round_ne
;
10907 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10908 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10910 add_startpgm(&ctx
);
10911 append_logical_start(ctx
.block
);
10913 Builder
bld(ctx
.program
, ctx
.block
);
10915 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10917 Operand
stream_id(0u);
10918 if (args
->shader_info
->so
.num_outputs
)
10919 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10920 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10922 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10924 std::stack
<Block
> endif_blocks
;
10926 for (unsigned stream
= 0; stream
< 4; stream
++) {
10927 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10930 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10931 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10934 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10936 unsigned BB_if_idx
= ctx
.block
->index
;
10937 Block BB_endif
= Block();
10938 if (!stream_id
.isConstant()) {
10940 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10941 append_logical_end(ctx
.block
);
10942 ctx
.block
->kind
|= block_kind_uniform
;
10943 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10945 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10947 ctx
.block
= ctx
.program
->create_and_insert_block();
10948 add_edge(BB_if_idx
, ctx
.block
);
10949 bld
.reset(ctx
.block
);
10950 append_logical_start(ctx
.block
);
10953 unsigned offset
= 0;
10954 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10955 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10958 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10959 unsigned length
= util_last_bit(output_usage_mask
);
10960 for (unsigned j
= 0; j
< length
; ++j
) {
10961 if (!(output_usage_mask
& (1 << j
)))
10964 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10965 Temp voffset
= vtx_offset
;
10966 if (const_offset
>= 4096u) {
10967 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10968 const_offset
%= 4096u;
10971 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10972 mubuf
->definitions
[0] = bld
.def(v1
);
10973 mubuf
->operands
[0] = Operand(gsvs_ring
);
10974 mubuf
->operands
[1] = Operand(voffset
);
10975 mubuf
->operands
[2] = Operand(0u);
10976 mubuf
->offen
= true;
10977 mubuf
->offset
= const_offset
;
10980 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10981 mubuf
->barrier
= barrier_none
;
10982 mubuf
->can_reorder
= true;
10984 ctx
.outputs
.mask
[i
] |= 1 << j
;
10985 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10987 bld
.insert(std::move(mubuf
));
10993 if (args
->shader_info
->so
.num_outputs
) {
10994 emit_streamout(&ctx
, stream
);
10995 bld
.reset(ctx
.block
);
10999 create_vs_exports(&ctx
);
11000 ctx
.block
->kind
|= block_kind_export_end
;
11003 if (!stream_id
.isConstant()) {
11004 append_logical_end(ctx
.block
);
11006 /* branch from then block to endif block */
11007 bld
.branch(aco_opcode::p_branch
);
11008 add_edge(ctx
.block
->index
, &BB_endif
);
11009 ctx
.block
->kind
|= block_kind_uniform
;
11011 /* emit else block */
11012 ctx
.block
= ctx
.program
->create_and_insert_block();
11013 add_edge(BB_if_idx
, ctx
.block
);
11014 bld
.reset(ctx
.block
);
11015 append_logical_start(ctx
.block
);
11017 endif_blocks
.push(std::move(BB_endif
));
11021 while (!endif_blocks
.empty()) {
11022 Block BB_endif
= std::move(endif_blocks
.top());
11023 endif_blocks
.pop();
11025 Block
*BB_else
= ctx
.block
;
11027 append_logical_end(BB_else
);
11028 /* branch from else block to endif block */
11029 bld
.branch(aco_opcode::p_branch
);
11030 add_edge(BB_else
->index
, &BB_endif
);
11031 BB_else
->kind
|= block_kind_uniform
;
11033 /** emit endif merge block */
11034 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11035 bld
.reset(ctx
.block
);
11036 append_logical_start(ctx
.block
);
11039 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11041 append_logical_end(ctx
.block
);
11042 ctx
.block
->kind
|= block_kind_uniform
;
11043 bld
.sopp(aco_opcode::s_endpgm
);
11045 cleanup_cfg(program
);