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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 bld
.is_precise
= instr
->exact
;
595 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
596 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
597 if (src1
.type() == RegType::sgpr
) {
598 if (commutative
&& src0
.type() == RegType::vgpr
) {
603 src1
= as_vgpr(ctx
, src1
);
607 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
608 assert(dst
.size() == 1);
609 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
610 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
612 bld
.vop2(op
, Definition(dst
), src0
, src1
);
616 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
617 bool flush_denorms
= false)
619 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
620 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
621 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
623 /* ensure that the instruction has at most 1 sgpr operand
624 * The optimizer will inline constants for us */
625 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
626 src0
= as_vgpr(ctx
, src0
);
627 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
628 src1
= as_vgpr(ctx
, src1
);
629 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
630 src2
= as_vgpr(ctx
, src2
);
632 Builder
bld(ctx
->program
, ctx
->block
);
633 bld
.is_precise
= instr
->exact
;
634 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
635 assert(dst
.size() == 1);
636 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
637 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
639 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
643 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
645 Builder
bld(ctx
->program
, ctx
->block
);
646 bld
.is_precise
= instr
->exact
;
647 if (dst
.type() == RegType::sgpr
)
648 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
649 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
651 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
654 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
656 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
657 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
658 assert(src0
.size() == src1
.size());
660 aco_ptr
<Instruction
> vopc
;
661 if (src1
.type() == RegType::sgpr
) {
662 if (src0
.type() == RegType::vgpr
) {
663 /* to swap the operands, we might also have to change the opcode */
665 case aco_opcode::v_cmp_lt_f16
:
666 op
= aco_opcode::v_cmp_gt_f16
;
668 case aco_opcode::v_cmp_ge_f16
:
669 op
= aco_opcode::v_cmp_le_f16
;
671 case aco_opcode::v_cmp_lt_i16
:
672 op
= aco_opcode::v_cmp_gt_i16
;
674 case aco_opcode::v_cmp_ge_i16
:
675 op
= aco_opcode::v_cmp_le_i16
;
677 case aco_opcode::v_cmp_lt_u16
:
678 op
= aco_opcode::v_cmp_gt_u16
;
680 case aco_opcode::v_cmp_ge_u16
:
681 op
= aco_opcode::v_cmp_le_u16
;
683 case aco_opcode::v_cmp_lt_f32
:
684 op
= aco_opcode::v_cmp_gt_f32
;
686 case aco_opcode::v_cmp_ge_f32
:
687 op
= aco_opcode::v_cmp_le_f32
;
689 case aco_opcode::v_cmp_lt_i32
:
690 op
= aco_opcode::v_cmp_gt_i32
;
692 case aco_opcode::v_cmp_ge_i32
:
693 op
= aco_opcode::v_cmp_le_i32
;
695 case aco_opcode::v_cmp_lt_u32
:
696 op
= aco_opcode::v_cmp_gt_u32
;
698 case aco_opcode::v_cmp_ge_u32
:
699 op
= aco_opcode::v_cmp_le_u32
;
701 case aco_opcode::v_cmp_lt_f64
:
702 op
= aco_opcode::v_cmp_gt_f64
;
704 case aco_opcode::v_cmp_ge_f64
:
705 op
= aco_opcode::v_cmp_le_f64
;
707 case aco_opcode::v_cmp_lt_i64
:
708 op
= aco_opcode::v_cmp_gt_i64
;
710 case aco_opcode::v_cmp_ge_i64
:
711 op
= aco_opcode::v_cmp_le_i64
;
713 case aco_opcode::v_cmp_lt_u64
:
714 op
= aco_opcode::v_cmp_gt_u64
;
716 case aco_opcode::v_cmp_ge_u64
:
717 op
= aco_opcode::v_cmp_le_u64
;
719 default: /* eq and ne are commutative */
726 src1
= as_vgpr(ctx
, src1
);
730 Builder
bld(ctx
->program
, ctx
->block
);
731 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
734 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
736 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
737 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
738 Builder
bld(ctx
->program
, ctx
->block
);
740 assert(dst
.regClass() == bld
.lm
);
741 assert(src0
.type() == RegType::sgpr
);
742 assert(src1
.type() == RegType::sgpr
);
743 assert(src0
.regClass() == src1
.regClass());
745 /* Emit the SALU comparison instruction */
746 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
747 /* Turn the result into a per-lane bool */
748 bool_to_vector_condition(ctx
, cmp
, dst
);
751 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
752 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
754 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
755 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
756 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
757 nir_dest_is_divergent(instr
->dest
.dest
) ||
758 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
759 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
760 aco_opcode op
= use_valu
? v_op
: s_op
;
761 assert(op
!= aco_opcode::num_opcodes
);
762 assert(dst
.regClass() == ctx
->program
->lane_mask
);
765 emit_vopc_instruction(ctx
, instr
, op
, dst
);
767 emit_sopc_instruction(ctx
, instr
, op
, dst
);
770 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
772 Builder
bld(ctx
->program
, ctx
->block
);
773 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
774 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
776 assert(dst
.regClass() == bld
.lm
);
777 assert(src0
.regClass() == bld
.lm
);
778 assert(src1
.regClass() == bld
.lm
);
780 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
783 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
785 Builder
bld(ctx
->program
, ctx
->block
);
786 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
787 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
788 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
790 assert(cond
.regClass() == bld
.lm
);
792 if (dst
.type() == RegType::vgpr
) {
793 aco_ptr
<Instruction
> bcsel
;
794 if (dst
.size() == 1) {
795 then
= as_vgpr(ctx
, then
);
796 els
= as_vgpr(ctx
, els
);
798 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
799 } else if (dst
.size() == 2) {
800 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
801 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
802 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
803 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
805 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
806 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
808 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
810 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
811 nir_print_instr(&instr
->instr
, stderr
);
812 fprintf(stderr
, "\n");
817 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
818 assert(dst
.regClass() == bld
.lm
);
819 assert(then
.regClass() == bld
.lm
);
820 assert(els
.regClass() == bld
.lm
);
823 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
824 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
825 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
826 assert(dst
.size() == then
.size());
827 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
828 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
830 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
831 nir_print_instr(&instr
->instr
, stderr
);
832 fprintf(stderr
, "\n");
837 /* divergent boolean bcsel
838 * this implements bcsel on bools: dst = s0 ? s1 : s2
839 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
840 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
842 if (cond
.id() != then
.id())
843 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
845 if (cond
.id() == els
.id())
846 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
848 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
849 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
852 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
853 aco_opcode op
, uint32_t undo
)
855 /* multiply by 16777216 to handle denormals */
856 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
857 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
858 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
859 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
860 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
862 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
864 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
867 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
869 if (ctx
->block
->fp_mode
.denorm32
== 0) {
870 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
874 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
877 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
879 if (ctx
->block
->fp_mode
.denorm32
== 0) {
880 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
884 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
887 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
889 if (ctx
->block
->fp_mode
.denorm32
== 0) {
890 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
894 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
897 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
899 if (ctx
->block
->fp_mode
.denorm32
== 0) {
900 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
904 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
907 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
909 if (ctx
->options
->chip_class
>= GFX7
)
910 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
912 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
913 /* TODO: create more efficient code! */
914 if (val
.type() == RegType::sgpr
)
915 val
= as_vgpr(ctx
, val
);
917 /* Split the input value. */
918 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
919 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
921 /* Extract the exponent and compute the unbiased value. */
922 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
923 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
925 /* Extract the fractional part. */
926 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
927 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
929 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
932 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
933 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
934 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
935 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
936 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
938 /* Get the sign bit. */
939 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
941 /* Decide the operation to apply depending on the unbiased exponent. */
942 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
943 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
944 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
945 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
946 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
947 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
949 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
952 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
954 if (ctx
->options
->chip_class
>= GFX7
)
955 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
957 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
958 Temp src0
= as_vgpr(ctx
, val
);
960 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
961 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
963 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
964 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
965 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
967 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
968 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
969 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
970 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
972 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
973 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
975 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
977 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
978 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
980 return add
->definitions
[0].getTemp();
983 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
985 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
986 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
988 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
991 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
992 return bld
.copy(Definition(dst
), src
);
993 else if (dst
.bytes() < src
.bytes())
994 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
998 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1001 } else if (src
.regClass() == s1
) {
1003 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1005 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1006 } else if (ctx
->options
->chip_class
>= GFX8
) {
1007 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1008 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1009 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1010 sdwa
->operands
[0] = Operand(src
);
1011 sdwa
->definitions
[0] = Definition(tmp
);
1013 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1015 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1016 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1017 bld
.insert(std::move(sdwa
));
1019 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1020 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1021 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1024 if (dst_bits
== 64) {
1025 if (is_signed
&& dst
.regClass() == s2
) {
1026 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1027 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1028 } else if (is_signed
&& dst
.regClass() == v2
) {
1029 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1030 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1032 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1039 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1041 if (!instr
->dest
.dest
.is_ssa
) {
1042 fprintf(stderr
, "nir alu dst not in ssa: ");
1043 nir_print_instr(&instr
->instr
, stderr
);
1044 fprintf(stderr
, "\n");
1047 Builder
bld(ctx
->program
, ctx
->block
);
1048 bld
.is_precise
= instr
->exact
;
1049 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1054 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1055 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1056 for (unsigned i
= 0; i
< num
; ++i
)
1057 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1059 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1060 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1061 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1062 for (unsigned i
= 0; i
< num
; ++i
) {
1063 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1064 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1066 vec
->operands
[i
] = Operand
{elems
[i
]};
1068 vec
->definitions
[0] = Definition(dst
);
1069 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1070 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1072 // TODO: that is a bit suboptimal..
1073 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1074 for (unsigned i
= 0; i
< num
- 1; ++i
)
1075 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1076 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1077 for (unsigned i
= 0; i
< num
; ++i
) {
1078 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1079 if (bit
% 32 == 0) {
1080 elems
[bit
/ 32] = elems
[i
];
1082 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1083 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1084 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1087 if (dst
.size() == 1)
1088 bld
.copy(Definition(dst
), elems
[0]);
1090 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1095 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1096 aco_ptr
<Instruction
> mov
;
1097 if (dst
.type() == RegType::sgpr
) {
1098 if (src
.type() == RegType::vgpr
)
1099 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1100 else if (src
.regClass() == s1
)
1101 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1102 else if (src
.regClass() == s2
)
1103 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1105 unreachable("wrong src register class for nir_op_imov");
1107 if (dst
.regClass() == v1
)
1108 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1109 else if (dst
.regClass() == v1b
||
1110 dst
.regClass() == v2b
||
1111 dst
.regClass() == v2
)
1112 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1114 unreachable("wrong src register class for nir_op_imov");
1119 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1120 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1121 assert(src
.regClass() == bld
.lm
);
1122 assert(dst
.regClass() == bld
.lm
);
1123 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1124 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1125 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1126 } else if (dst
.regClass() == v1
) {
1127 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1128 } else if (dst
.type() == RegType::sgpr
) {
1129 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1130 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1133 nir_print_instr(&instr
->instr
, stderr
);
1134 fprintf(stderr
, "\n");
1139 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1140 if (dst
.regClass() == v1
) {
1141 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1142 } else if (dst
.regClass() == s1
) {
1143 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1144 } else if (dst
.size() == 2) {
1145 Temp src0
= bld
.tmp(dst
.type(), 1);
1146 Temp src1
= bld
.tmp(dst
.type(), 1);
1147 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1149 if (dst
.regClass() == s2
) {
1150 Temp carry
= bld
.tmp(s1
);
1151 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1152 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1155 Temp lower
= bld
.tmp(v1
);
1156 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1157 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (dst
.regClass() == s1
) {
1169 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1170 } else if (dst
.regClass() == v1
) {
1171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1172 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1174 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1175 nir_print_instr(&instr
->instr
, stderr
);
1176 fprintf(stderr
, "\n");
1180 case nir_op_isign
: {
1181 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1182 if (dst
.regClass() == s1
) {
1183 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1184 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1185 } else if (dst
.regClass() == s2
) {
1186 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1188 if (ctx
->program
->chip_class
>= GFX8
)
1189 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1191 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1192 /* SCC gets zero-extended to 64 bit */
1193 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1194 } else if (dst
.regClass() == v1
) {
1195 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1196 } else if (dst
.regClass() == v2
) {
1197 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1198 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1199 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1200 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1201 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1202 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1204 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1205 nir_print_instr(&instr
->instr
, stderr
);
1206 fprintf(stderr
, "\n");
1211 if (dst
.regClass() == v1
) {
1212 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1213 } else if (dst
.regClass() == s1
) {
1214 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1216 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1217 nir_print_instr(&instr
->instr
, stderr
);
1218 fprintf(stderr
, "\n");
1223 if (dst
.regClass() == v1
) {
1224 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1225 } else if (dst
.regClass() == s1
) {
1226 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1228 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1229 nir_print_instr(&instr
->instr
, stderr
);
1230 fprintf(stderr
, "\n");
1235 if (dst
.regClass() == v1
) {
1236 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1237 } else if (dst
.regClass() == s1
) {
1238 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1240 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1241 nir_print_instr(&instr
->instr
, stderr
);
1242 fprintf(stderr
, "\n");
1247 if (dst
.regClass() == v1
) {
1248 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1249 } else if (dst
.regClass() == s1
) {
1250 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1252 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1253 nir_print_instr(&instr
->instr
, stderr
);
1254 fprintf(stderr
, "\n");
1259 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1260 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1261 } else if (dst
.regClass() == v1
) {
1262 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1263 } else if (dst
.regClass() == s1
) {
1264 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1265 } else if (dst
.regClass() == s2
) {
1266 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1268 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1269 nir_print_instr(&instr
->instr
, stderr
);
1270 fprintf(stderr
, "\n");
1275 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1276 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1277 } else if (dst
.regClass() == v1
) {
1278 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1279 } else if (dst
.regClass() == s1
) {
1280 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1281 } else if (dst
.regClass() == s2
) {
1282 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1291 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1292 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1293 } else if (dst
.regClass() == v1
) {
1294 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1295 } else if (dst
.regClass() == s1
) {
1296 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1297 } else if (dst
.regClass() == s2
) {
1298 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1300 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1301 nir_print_instr(&instr
->instr
, stderr
);
1302 fprintf(stderr
, "\n");
1307 if (dst
.regClass() == v1
) {
1308 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1309 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1310 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1311 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1312 } else if (dst
.regClass() == v2
) {
1313 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1314 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1315 } else if (dst
.regClass() == s2
) {
1316 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1317 } else if (dst
.regClass() == s1
) {
1318 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1320 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1321 nir_print_instr(&instr
->instr
, stderr
);
1322 fprintf(stderr
, "\n");
1327 if (dst
.regClass() == v1
) {
1328 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1329 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1330 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1331 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1332 } else if (dst
.regClass() == v2
) {
1333 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1334 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1335 } else if (dst
.regClass() == s1
) {
1336 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1337 } else if (dst
.regClass() == s2
) {
1338 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1340 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1341 nir_print_instr(&instr
->instr
, stderr
);
1342 fprintf(stderr
, "\n");
1347 if (dst
.regClass() == v1
) {
1348 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1349 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1350 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1351 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1352 } else if (dst
.regClass() == v2
) {
1353 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1354 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1360 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1361 nir_print_instr(&instr
->instr
, stderr
);
1362 fprintf(stderr
, "\n");
1366 case nir_op_find_lsb
: {
1367 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1368 if (src
.regClass() == s1
) {
1369 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1370 } else if (src
.regClass() == v1
) {
1371 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1372 } else if (src
.regClass() == s2
) {
1373 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1375 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1376 nir_print_instr(&instr
->instr
, stderr
);
1377 fprintf(stderr
, "\n");
1381 case nir_op_ufind_msb
:
1382 case nir_op_ifind_msb
: {
1383 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1384 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1385 aco_opcode op
= src
.regClass() == s2
?
1386 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1387 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1388 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1390 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1391 Operand(src
.size() * 32u - 1u), msb_rev
);
1392 Temp msb
= sub
.def(0).getTemp();
1393 Temp carry
= sub
.def(1).getTemp();
1395 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1396 } else if (src
.regClass() == v1
) {
1397 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1398 Temp msb_rev
= bld
.tmp(v1
);
1399 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1400 Temp msb
= bld
.tmp(v1
);
1401 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1402 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1404 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1405 nir_print_instr(&instr
->instr
, stderr
);
1406 fprintf(stderr
, "\n");
1410 case nir_op_bitfield_reverse
: {
1411 if (dst
.regClass() == s1
) {
1412 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1413 } else if (dst
.regClass() == v1
) {
1414 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1416 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1417 nir_print_instr(&instr
->instr
, stderr
);
1418 fprintf(stderr
, "\n");
1423 if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1428 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1429 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1430 if (dst
.regClass() == v1
) {
1431 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1435 assert(src0
.size() == 2 && src1
.size() == 2);
1436 Temp src00
= bld
.tmp(src0
.type(), 1);
1437 Temp src01
= bld
.tmp(dst
.type(), 1);
1438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1439 Temp src10
= bld
.tmp(src1
.type(), 1);
1440 Temp src11
= bld
.tmp(dst
.type(), 1);
1441 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1443 if (dst
.regClass() == s2
) {
1444 Temp carry
= bld
.tmp(s1
);
1445 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1446 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1447 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1448 } else if (dst
.regClass() == v2
) {
1449 Temp dst0
= bld
.tmp(v1
);
1450 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1451 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1452 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1454 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1455 nir_print_instr(&instr
->instr
, stderr
);
1456 fprintf(stderr
, "\n");
1460 case nir_op_uadd_sat
: {
1461 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1462 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1463 if (dst
.regClass() == s1
) {
1464 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1465 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1467 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1468 } else if (dst
.regClass() == v1
) {
1469 if (ctx
->options
->chip_class
>= GFX9
) {
1470 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1471 add
->operands
[0] = Operand(src0
);
1472 add
->operands
[1] = Operand(src1
);
1473 add
->definitions
[0] = Definition(dst
);
1475 ctx
->block
->instructions
.emplace_back(std::move(add
));
1477 if (src1
.regClass() != v1
)
1478 std::swap(src0
, src1
);
1479 assert(src1
.regClass() == v1
);
1480 Temp tmp
= bld
.tmp(v1
);
1481 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1482 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1485 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1486 nir_print_instr(&instr
->instr
, stderr
);
1487 fprintf(stderr
, "\n");
1491 case nir_op_uadd_carry
: {
1492 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1493 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1494 if (dst
.regClass() == s1
) {
1495 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1498 if (dst
.regClass() == v1
) {
1499 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1500 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1504 Temp src00
= bld
.tmp(src0
.type(), 1);
1505 Temp src01
= bld
.tmp(dst
.type(), 1);
1506 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1507 Temp src10
= bld
.tmp(src1
.type(), 1);
1508 Temp src11
= bld
.tmp(dst
.type(), 1);
1509 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1510 if (dst
.regClass() == s2
) {
1511 Temp carry
= bld
.tmp(s1
);
1512 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1513 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1514 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1515 } else if (dst
.regClass() == v2
) {
1516 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1517 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1518 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1519 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1521 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1522 nir_print_instr(&instr
->instr
, stderr
);
1523 fprintf(stderr
, "\n");
1528 if (dst
.regClass() == s1
) {
1529 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1533 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1534 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1535 if (dst
.regClass() == v1
) {
1536 bld
.vsub32(Definition(dst
), src0
, src1
);
1540 Temp src00
= bld
.tmp(src0
.type(), 1);
1541 Temp src01
= bld
.tmp(dst
.type(), 1);
1542 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1543 Temp src10
= bld
.tmp(src1
.type(), 1);
1544 Temp src11
= bld
.tmp(dst
.type(), 1);
1545 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1546 if (dst
.regClass() == s2
) {
1547 Temp carry
= bld
.tmp(s1
);
1548 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1549 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1550 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1551 } else if (dst
.regClass() == v2
) {
1552 Temp lower
= bld
.tmp(v1
);
1553 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1554 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1555 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1557 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1558 nir_print_instr(&instr
->instr
, stderr
);
1559 fprintf(stderr
, "\n");
1563 case nir_op_usub_borrow
: {
1564 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1565 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1566 if (dst
.regClass() == s1
) {
1567 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1569 } else if (dst
.regClass() == v1
) {
1570 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1571 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1575 Temp src00
= bld
.tmp(src0
.type(), 1);
1576 Temp src01
= bld
.tmp(dst
.type(), 1);
1577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1578 Temp src10
= bld
.tmp(src1
.type(), 1);
1579 Temp src11
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1581 if (dst
.regClass() == s2
) {
1582 Temp borrow
= bld
.tmp(s1
);
1583 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1584 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1586 } else if (dst
.regClass() == v2
) {
1587 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1588 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1589 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1592 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1593 nir_print_instr(&instr
->instr
, stderr
);
1594 fprintf(stderr
, "\n");
1599 if (dst
.regClass() == v1
) {
1600 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1601 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1602 } else if (dst
.regClass() == s1
) {
1603 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1606 nir_print_instr(&instr
->instr
, stderr
);
1607 fprintf(stderr
, "\n");
1611 case nir_op_umul_high
: {
1612 if (dst
.regClass() == v1
) {
1613 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1614 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1615 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1616 } else if (dst
.regClass() == s1
) {
1617 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1618 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1619 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1627 case nir_op_imul_high
: {
1628 if (dst
.regClass() == v1
) {
1629 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1630 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1631 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1632 } else if (dst
.regClass() == s1
) {
1633 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1634 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1635 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1637 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1638 nir_print_instr(&instr
->instr
, stderr
);
1639 fprintf(stderr
, "\n");
1644 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1645 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1646 if (dst
.regClass() == v2b
) {
1647 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1648 } else if (dst
.regClass() == v1
) {
1649 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1650 } else if (dst
.regClass() == v2
) {
1651 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1653 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1654 nir_print_instr(&instr
->instr
, stderr
);
1655 fprintf(stderr
, "\n");
1660 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1661 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1662 if (dst
.regClass() == v2b
) {
1663 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1664 } else if (dst
.regClass() == v1
) {
1665 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1666 } else if (dst
.regClass() == v2
) {
1667 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1669 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1670 nir_print_instr(&instr
->instr
, stderr
);
1671 fprintf(stderr
, "\n");
1676 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1677 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1678 if (dst
.regClass() == v2b
) {
1679 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1680 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1682 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1683 } else if (dst
.regClass() == v1
) {
1684 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1685 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1687 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1688 } else if (dst
.regClass() == v2
) {
1689 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1690 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1691 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1694 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1695 nir_print_instr(&instr
->instr
, stderr
);
1696 fprintf(stderr
, "\n");
1701 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1702 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1703 if (dst
.regClass() == v2b
) {
1704 // TODO: check fp_mode.must_flush_denorms16_64
1705 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1706 } else if (dst
.regClass() == v1
) {
1707 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1708 } else if (dst
.regClass() == v2
) {
1709 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1710 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1711 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1713 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1716 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1717 nir_print_instr(&instr
->instr
, stderr
);
1718 fprintf(stderr
, "\n");
1723 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1724 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1725 if (dst
.regClass() == v2b
) {
1726 // TODO: check fp_mode.must_flush_denorms16_64
1727 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1728 } else if (dst
.regClass() == v1
) {
1729 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1730 } else if (dst
.regClass() == v2
) {
1731 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1732 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1733 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1735 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1738 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1739 nir_print_instr(&instr
->instr
, stderr
);
1740 fprintf(stderr
, "\n");
1744 case nir_op_fmax3
: {
1745 if (dst
.regClass() == v2b
) {
1746 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1747 } else if (dst
.regClass() == v1
) {
1748 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1751 nir_print_instr(&instr
->instr
, stderr
);
1752 fprintf(stderr
, "\n");
1756 case nir_op_fmin3
: {
1757 if (dst
.regClass() == v2b
) {
1758 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1759 } else if (dst
.regClass() == v1
) {
1760 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1762 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1763 nir_print_instr(&instr
->instr
, stderr
);
1764 fprintf(stderr
, "\n");
1768 case nir_op_fmed3
: {
1769 if (dst
.regClass() == v2b
) {
1770 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1771 } else if (dst
.regClass() == v1
) {
1772 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1774 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1775 nir_print_instr(&instr
->instr
, stderr
);
1776 fprintf(stderr
, "\n");
1780 case nir_op_umax3
: {
1781 if (dst
.size() == 1) {
1782 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1784 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1785 nir_print_instr(&instr
->instr
, stderr
);
1786 fprintf(stderr
, "\n");
1790 case nir_op_umin3
: {
1791 if (dst
.size() == 1) {
1792 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1794 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1795 nir_print_instr(&instr
->instr
, stderr
);
1796 fprintf(stderr
, "\n");
1800 case nir_op_umed3
: {
1801 if (dst
.size() == 1) {
1802 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1804 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1805 nir_print_instr(&instr
->instr
, stderr
);
1806 fprintf(stderr
, "\n");
1810 case nir_op_imax3
: {
1811 if (dst
.size() == 1) {
1812 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1814 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1815 nir_print_instr(&instr
->instr
, stderr
);
1816 fprintf(stderr
, "\n");
1820 case nir_op_imin3
: {
1821 if (dst
.size() == 1) {
1822 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1830 case nir_op_imed3
: {
1831 if (dst
.size() == 1) {
1832 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1834 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1835 nir_print_instr(&instr
->instr
, stderr
);
1836 fprintf(stderr
, "\n");
1840 case nir_op_cube_face_coord
: {
1841 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1842 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1843 emit_extract_vector(ctx
, in
, 1, v1
),
1844 emit_extract_vector(ctx
, in
, 2, v1
) };
1845 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1846 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1847 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1848 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1849 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1850 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1851 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1854 case nir_op_cube_face_index
: {
1855 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1856 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1857 emit_extract_vector(ctx
, in
, 1, v1
),
1858 emit_extract_vector(ctx
, in
, 2, v1
) };
1859 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1862 case nir_op_bcsel
: {
1863 emit_bcsel(ctx
, instr
, dst
);
1867 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1868 if (dst
.regClass() == v2b
) {
1869 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1870 } else if (dst
.regClass() == v1
) {
1871 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1872 } else if (dst
.regClass() == v2
) {
1873 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1875 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1876 nir_print_instr(&instr
->instr
, stderr
);
1877 fprintf(stderr
, "\n");
1882 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1883 if (dst
.regClass() == v2b
) {
1884 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1885 } else if (dst
.regClass() == v1
) {
1886 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1887 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1888 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1889 } else if (dst
.regClass() == v2
) {
1890 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1891 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1892 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1893 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1894 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1895 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1898 nir_print_instr(&instr
->instr
, stderr
);
1899 fprintf(stderr
, "\n");
1904 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1905 if (dst
.regClass() == v2b
) {
1906 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1907 } else if (dst
.regClass() == v1
) {
1908 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1909 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1910 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1911 } else if (dst
.regClass() == v2
) {
1912 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1913 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1914 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1915 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1916 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1917 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1919 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1920 nir_print_instr(&instr
->instr
, stderr
);
1921 fprintf(stderr
, "\n");
1926 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1927 if (dst
.regClass() == v2b
) {
1928 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1929 } else if (dst
.regClass() == v1
) {
1930 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1931 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1932 // TODO: confirm that this holds under any circumstances
1933 } else if (dst
.regClass() == v2
) {
1934 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1935 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1938 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1939 nir_print_instr(&instr
->instr
, stderr
);
1940 fprintf(stderr
, "\n");
1944 case nir_op_flog2
: {
1945 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1946 if (dst
.regClass() == v2b
) {
1947 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1948 } else if (dst
.regClass() == v1
) {
1949 emit_log2(ctx
, bld
, Definition(dst
), src
);
1951 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1952 nir_print_instr(&instr
->instr
, stderr
);
1953 fprintf(stderr
, "\n");
1958 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1959 if (dst
.regClass() == v2b
) {
1960 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1961 } else if (dst
.regClass() == v1
) {
1962 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1963 } else if (dst
.regClass() == v2
) {
1964 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1966 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1967 nir_print_instr(&instr
->instr
, stderr
);
1968 fprintf(stderr
, "\n");
1972 case nir_op_fexp2
: {
1973 if (dst
.regClass() == v2b
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1975 } else if (dst
.regClass() == v1
) {
1976 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1978 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1979 nir_print_instr(&instr
->instr
, stderr
);
1980 fprintf(stderr
, "\n");
1984 case nir_op_fsqrt
: {
1985 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1986 if (dst
.regClass() == v2b
) {
1987 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1988 } else if (dst
.regClass() == v1
) {
1989 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1990 } else if (dst
.regClass() == v2
) {
1991 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1993 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1994 nir_print_instr(&instr
->instr
, stderr
);
1995 fprintf(stderr
, "\n");
1999 case nir_op_ffract
: {
2000 if (dst
.regClass() == v2b
) {
2001 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2002 } else if (dst
.regClass() == v1
) {
2003 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2004 } else if (dst
.regClass() == v2
) {
2005 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2007 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2008 nir_print_instr(&instr
->instr
, stderr
);
2009 fprintf(stderr
, "\n");
2013 case nir_op_ffloor
: {
2014 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2015 if (dst
.regClass() == v2b
) {
2016 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2017 } else if (dst
.regClass() == v1
) {
2018 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2019 } else if (dst
.regClass() == v2
) {
2020 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2022 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2023 nir_print_instr(&instr
->instr
, stderr
);
2024 fprintf(stderr
, "\n");
2028 case nir_op_fceil
: {
2029 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2030 if (dst
.regClass() == v2b
) {
2031 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2032 } else if (dst
.regClass() == v1
) {
2033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2034 } else if (dst
.regClass() == v2
) {
2035 if (ctx
->options
->chip_class
>= GFX7
) {
2036 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2038 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2039 /* trunc = trunc(src0)
2040 * if (src0 > 0.0 && src0 != trunc)
2043 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2044 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2045 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2046 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2047 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2048 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2049 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2052 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2053 nir_print_instr(&instr
->instr
, stderr
);
2054 fprintf(stderr
, "\n");
2058 case nir_op_ftrunc
: {
2059 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2060 if (dst
.regClass() == v2b
) {
2061 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2062 } else if (dst
.regClass() == v1
) {
2063 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2064 } else if (dst
.regClass() == v2
) {
2065 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2068 nir_print_instr(&instr
->instr
, stderr
);
2069 fprintf(stderr
, "\n");
2073 case nir_op_fround_even
: {
2074 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2075 if (dst
.regClass() == v2b
) {
2076 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2077 } else if (dst
.regClass() == v1
) {
2078 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2079 } else if (dst
.regClass() == v2
) {
2080 if (ctx
->options
->chip_class
>= GFX7
) {
2081 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2083 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2084 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2085 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2087 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2088 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2089 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2090 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2091 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2092 tmp
= sub
->definitions
[0].getTemp();
2094 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2095 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2096 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2097 Temp cond
= vop3
->definitions
[0].getTemp();
2099 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2100 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2101 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2102 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2104 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2115 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2116 aco_ptr
<Instruction
> norm
;
2117 if (dst
.regClass() == v2b
) {
2118 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2119 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2120 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2121 bld
.vop1(opcode
, Definition(dst
), tmp
);
2122 } else if (dst
.regClass() == v1
) {
2123 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2124 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2126 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2127 if (ctx
->options
->chip_class
< GFX9
)
2128 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2130 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2131 bld
.vop1(opcode
, Definition(dst
), tmp
);
2133 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2134 nir_print_instr(&instr
->instr
, stderr
);
2135 fprintf(stderr
, "\n");
2139 case nir_op_ldexp
: {
2140 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2141 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2142 if (dst
.regClass() == v2b
) {
2143 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2144 } else if (dst
.regClass() == v1
) {
2145 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2146 } else if (dst
.regClass() == v2
) {
2147 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2150 nir_print_instr(&instr
->instr
, stderr
);
2151 fprintf(stderr
, "\n");
2155 case nir_op_frexp_sig
: {
2156 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2157 if (dst
.regClass() == v2b
) {
2158 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2159 } else if (dst
.regClass() == v1
) {
2160 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2161 } else if (dst
.regClass() == v2
) {
2162 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2164 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2165 nir_print_instr(&instr
->instr
, stderr
);
2166 fprintf(stderr
, "\n");
2170 case nir_op_frexp_exp
: {
2171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2172 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2173 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2174 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2175 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2176 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2177 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2178 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2179 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2181 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2182 nir_print_instr(&instr
->instr
, stderr
);
2183 fprintf(stderr
, "\n");
2187 case nir_op_fsign
: {
2188 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2189 if (dst
.regClass() == v2b
) {
2190 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2191 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2192 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2193 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2194 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2195 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2196 } else if (dst
.regClass() == v1
) {
2197 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2198 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2199 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2200 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2201 } else if (dst
.regClass() == v2
) {
2202 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2203 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2204 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2206 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2207 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2208 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2210 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2212 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2213 nir_print_instr(&instr
->instr
, stderr
);
2214 fprintf(stderr
, "\n");
2219 case nir_op_f2f16_rtne
: {
2220 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2221 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2222 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2223 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2226 case nir_op_f2f16_rtz
: {
2227 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2228 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2229 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2230 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2233 case nir_op_f2f32
: {
2234 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2235 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2236 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2237 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2239 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2240 nir_print_instr(&instr
->instr
, stderr
);
2241 fprintf(stderr
, "\n");
2245 case nir_op_f2f64
: {
2246 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2247 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2248 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2249 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2252 case nir_op_i2f16
: {
2253 assert(dst
.regClass() == v2b
);
2254 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2255 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2256 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2257 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2258 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2259 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2262 case nir_op_i2f32
: {
2263 assert(dst
.size() == 1);
2264 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2265 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2266 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2267 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2270 case nir_op_i2f64
: {
2271 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2272 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2273 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2274 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2275 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2276 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2277 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2278 RegClass rc
= RegClass(src
.type(), 1);
2279 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2280 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2281 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2282 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2283 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2284 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2287 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2288 nir_print_instr(&instr
->instr
, stderr
);
2289 fprintf(stderr
, "\n");
2293 case nir_op_u2f16
: {
2294 assert(dst
.regClass() == v2b
);
2295 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2296 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2297 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2298 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2299 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2300 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2303 case nir_op_u2f32
: {
2304 assert(dst
.size() == 1);
2305 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2306 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2307 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2309 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2310 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2311 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2315 case nir_op_u2f64
: {
2316 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2318 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2319 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2320 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2321 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2322 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2323 RegClass rc
= RegClass(src
.type(), 1);
2324 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2325 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2326 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2327 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2328 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2329 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2331 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2332 nir_print_instr(&instr
->instr
, stderr
);
2333 fprintf(stderr
, "\n");
2338 case nir_op_f2i16
: {
2339 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2340 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2341 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2342 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2344 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2348 case nir_op_f2u16
: {
2349 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2350 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2351 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2352 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2354 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2357 case nir_op_f2i32
: {
2358 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2359 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2360 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2361 if (dst
.type() == RegType::vgpr
) {
2362 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2364 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2365 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2367 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2368 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2369 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2370 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2372 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2373 nir_print_instr(&instr
->instr
, stderr
);
2374 fprintf(stderr
, "\n");
2378 case nir_op_f2u32
: {
2379 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2380 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2381 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2382 if (dst
.type() == RegType::vgpr
) {
2383 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2385 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2386 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2388 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2389 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2390 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2391 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2393 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2394 nir_print_instr(&instr
->instr
, stderr
);
2395 fprintf(stderr
, "\n");
2399 case nir_op_f2i64
: {
2400 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2401 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2402 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2404 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2405 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2406 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2407 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2408 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2409 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2410 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2411 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2412 Temp new_exponent
= bld
.tmp(v1
);
2413 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2414 if (ctx
->program
->chip_class
>= GFX8
)
2415 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2417 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2418 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2419 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2420 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2421 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2422 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2423 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2424 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2425 Temp new_lower
= bld
.tmp(v1
);
2426 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2427 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2430 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2431 if (src
.type() == RegType::vgpr
)
2432 src
= bld
.as_uniform(src
);
2433 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2434 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2435 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2436 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2437 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2438 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2439 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2440 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2441 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2442 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2443 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2444 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2445 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2446 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2447 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2448 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2449 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2450 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2451 Temp borrow
= bld
.tmp(s1
);
2452 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2453 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2454 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2456 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2457 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2458 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2459 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2460 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2461 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2462 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2463 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2464 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2465 if (dst
.type() == RegType::sgpr
) {
2466 lower
= bld
.as_uniform(lower
);
2467 upper
= bld
.as_uniform(upper
);
2469 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2472 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2473 nir_print_instr(&instr
->instr
, stderr
);
2474 fprintf(stderr
, "\n");
2478 case nir_op_f2u64
: {
2479 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2480 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2481 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2483 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2484 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2485 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2486 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2487 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2488 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2489 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2490 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2491 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2492 Temp new_exponent
= bld
.tmp(v1
);
2493 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2494 if (ctx
->program
->chip_class
>= GFX8
)
2495 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2497 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2498 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2499 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2500 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2501 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2502 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2503 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2504 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2506 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2507 if (src
.type() == RegType::vgpr
)
2508 src
= bld
.as_uniform(src
);
2509 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2510 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2511 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2512 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2513 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2514 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2515 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2516 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2517 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2518 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2519 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2520 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2521 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2522 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2523 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2524 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2525 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2526 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2528 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2529 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2530 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2531 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2532 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2533 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2534 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2535 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2536 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2537 if (dst
.type() == RegType::sgpr
) {
2538 lower
= bld
.as_uniform(lower
);
2539 upper
= bld
.as_uniform(upper
);
2541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2544 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2545 nir_print_instr(&instr
->instr
, stderr
);
2546 fprintf(stderr
, "\n");
2550 case nir_op_b2f16
: {
2551 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2552 assert(src
.regClass() == bld
.lm
);
2554 if (dst
.regClass() == s1
) {
2555 src
= bool_to_scalar_condition(ctx
, src
);
2556 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2557 } else if (dst
.regClass() == v2b
) {
2558 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2559 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2561 unreachable("Wrong destination register class for nir_op_b2f16.");
2565 case nir_op_b2f32
: {
2566 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2567 assert(src
.regClass() == bld
.lm
);
2569 if (dst
.regClass() == s1
) {
2570 src
= bool_to_scalar_condition(ctx
, src
);
2571 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2572 } else if (dst
.regClass() == v1
) {
2573 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2575 unreachable("Wrong destination register class for nir_op_b2f32.");
2579 case nir_op_b2f64
: {
2580 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2581 assert(src
.regClass() == bld
.lm
);
2583 if (dst
.regClass() == s2
) {
2584 src
= bool_to_scalar_condition(ctx
, src
);
2585 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2586 } else if (dst
.regClass() == v2
) {
2587 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2588 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2589 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2591 unreachable("Wrong destination register class for nir_op_b2f64.");
2598 case nir_op_i2i64
: {
2599 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2600 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2606 case nir_op_u2u64
: {
2607 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2608 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2612 case nir_op_b2i32
: {
2613 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2614 assert(src
.regClass() == bld
.lm
);
2616 if (dst
.regClass() == s1
) {
2617 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2618 bool_to_scalar_condition(ctx
, src
, dst
);
2619 } else if (dst
.regClass() == v1
) {
2620 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2622 unreachable("Invalid register class for b2i32");
2628 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2629 assert(dst
.regClass() == bld
.lm
);
2631 if (src
.type() == RegType::vgpr
) {
2632 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2633 assert(dst
.regClass() == bld
.lm
);
2634 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2635 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2637 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2639 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2640 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2642 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2643 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2645 bool_to_vector_condition(ctx
, tmp
, dst
);
2649 case nir_op_pack_64_2x32_split
: {
2650 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2651 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2653 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2656 case nir_op_unpack_64_2x32_split_x
:
2657 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2659 case nir_op_unpack_64_2x32_split_y
:
2660 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2662 case nir_op_unpack_32_2x16_split_x
:
2663 if (dst
.type() == RegType::vgpr
) {
2664 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2666 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2669 case nir_op_unpack_32_2x16_split_y
:
2670 if (dst
.type() == RegType::vgpr
) {
2671 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2673 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2676 case nir_op_pack_32_2x16_split
: {
2677 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2678 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2679 if (dst
.regClass() == v1
) {
2680 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2681 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2682 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2684 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2685 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2686 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2690 case nir_op_pack_half_2x16
: {
2691 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2693 if (dst
.regClass() == v1
) {
2694 Temp src0
= bld
.tmp(v1
);
2695 Temp src1
= bld
.tmp(v1
);
2696 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2697 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2698 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2700 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2701 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2702 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2704 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2705 nir_print_instr(&instr
->instr
, stderr
);
2706 fprintf(stderr
, "\n");
2710 case nir_op_unpack_half_2x16_split_x
: {
2711 if (dst
.regClass() == v1
) {
2712 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2714 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2715 nir_print_instr(&instr
->instr
, stderr
);
2716 fprintf(stderr
, "\n");
2720 case nir_op_unpack_half_2x16_split_y
: {
2721 if (dst
.regClass() == v1
) {
2722 /* TODO: use SDWA here */
2723 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2724 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2727 nir_print_instr(&instr
->instr
, stderr
);
2728 fprintf(stderr
, "\n");
2732 case nir_op_fquantize2f16
: {
2733 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2734 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2737 if (ctx
->program
->chip_class
>= GFX8
) {
2738 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2739 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2740 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2742 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2743 * so compare the result and flush to 0 if it's smaller.
2745 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2746 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2747 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2748 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2749 cmp_res
= vop3
->definitions
[0].getTemp();
2752 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2753 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2754 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2756 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2761 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2762 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2764 if (dst
.regClass() == s1
) {
2765 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2766 } else if (dst
.regClass() == v1
) {
2767 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2769 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2770 nir_print_instr(&instr
->instr
, stderr
);
2771 fprintf(stderr
, "\n");
2775 case nir_op_bitfield_select
: {
2776 /* (mask & insert) | (~mask & base) */
2777 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2778 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2779 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2781 /* dst = (insert & bitmask) | (base & ~bitmask) */
2782 if (dst
.regClass() == s1
) {
2783 aco_ptr
<Instruction
> sop2
;
2784 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2785 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2787 if (const_insert
&& const_bitmask
) {
2788 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2790 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2791 lhs
= Operand(insert
);
2795 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2796 if (const_base
&& const_bitmask
) {
2797 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2799 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2800 rhs
= Operand(base
);
2803 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2805 } else if (dst
.regClass() == v1
) {
2806 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2807 base
= as_vgpr(ctx
, base
);
2808 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2809 insert
= as_vgpr(ctx
, insert
);
2811 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2814 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2815 nir_print_instr(&instr
->instr
, stderr
);
2816 fprintf(stderr
, "\n");
2822 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2823 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2824 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2826 if (dst
.type() == RegType::sgpr
) {
2828 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2829 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2830 if (const_offset
&& const_bits
) {
2831 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2832 extract
= Operand(const_extract
);
2836 width
= Operand(const_bits
->u32
<< 16);
2838 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2840 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2844 if (dst
.regClass() == s1
) {
2845 if (instr
->op
== nir_op_ubfe
)
2846 opcode
= aco_opcode::s_bfe_u32
;
2848 opcode
= aco_opcode::s_bfe_i32
;
2849 } else if (dst
.regClass() == s2
) {
2850 if (instr
->op
== nir_op_ubfe
)
2851 opcode
= aco_opcode::s_bfe_u64
;
2853 opcode
= aco_opcode::s_bfe_i64
;
2855 unreachable("Unsupported BFE bit size");
2858 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2862 if (dst
.regClass() == v1
) {
2863 if (instr
->op
== nir_op_ubfe
)
2864 opcode
= aco_opcode::v_bfe_u32
;
2866 opcode
= aco_opcode::v_bfe_i32
;
2868 unreachable("Unsupported BFE bit size");
2871 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2875 case nir_op_bit_count
: {
2876 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2877 if (src
.regClass() == s1
) {
2878 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2879 } else if (src
.regClass() == v1
) {
2880 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2881 } else if (src
.regClass() == v2
) {
2882 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2883 emit_extract_vector(ctx
, src
, 1, v1
),
2884 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2885 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2886 } else if (src
.regClass() == s2
) {
2887 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2889 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2890 nir_print_instr(&instr
->instr
, stderr
);
2891 fprintf(stderr
, "\n");
2896 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2900 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2904 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2908 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2912 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2916 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2920 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2921 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2923 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2924 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2928 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2929 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2931 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2932 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2936 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2940 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2945 case nir_op_fddx_fine
:
2946 case nir_op_fddy_fine
:
2947 case nir_op_fddx_coarse
:
2948 case nir_op_fddy_coarse
: {
2949 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2950 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2951 if (instr
->op
== nir_op_fddx_fine
) {
2952 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2953 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2954 } else if (instr
->op
== nir_op_fddy_fine
) {
2955 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2956 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2958 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2959 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2960 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2962 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2966 if (ctx
->program
->chip_class
>= GFX8
) {
2967 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2968 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2970 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2971 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2972 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2974 emit_wqm(ctx
, tmp
, dst
, true);
2978 fprintf(stderr
, "Unknown NIR ALU instr: ");
2979 nir_print_instr(&instr
->instr
, stderr
);
2980 fprintf(stderr
, "\n");
2984 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2986 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2988 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2989 // which get truncated the lsb if double and msb if int
2990 // for now, we only use s_mov_b64 with 64bit inline constants
2991 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2992 assert(dst
.type() == RegType::sgpr
);
2994 Builder
bld(ctx
->program
, ctx
->block
);
2996 if (instr
->def
.bit_size
== 1) {
2997 assert(dst
.regClass() == bld
.lm
);
2998 int val
= instr
->value
[0].b
? -1 : 0;
2999 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3000 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3001 } else if (instr
->def
.bit_size
== 8) {
3002 /* ensure that the value is correctly represented in the low byte of the register */
3003 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3004 } else if (instr
->def
.bit_size
== 16) {
3005 /* ensure that the value is correctly represented in the low half of the register */
3006 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3007 } else if (dst
.size() == 1) {
3008 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3010 assert(dst
.size() != 1);
3011 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3012 if (instr
->def
.bit_size
== 64)
3013 for (unsigned i
= 0; i
< dst
.size(); i
++)
3014 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3016 for (unsigned i
= 0; i
< dst
.size(); i
++)
3017 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3019 vec
->definitions
[0] = Definition(dst
);
3020 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3024 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3026 uint32_t new_mask
= 0;
3027 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3028 if (mask
& (1u << i
))
3029 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3033 struct LoadEmitInfo
{
3036 unsigned num_components
;
3037 unsigned component_size
;
3038 Temp resource
= Temp(0, s1
);
3039 unsigned component_stride
= 0;
3040 unsigned const_offset
= 0;
3041 unsigned align_mul
= 0;
3042 unsigned align_offset
= 0;
3045 unsigned swizzle_component_size
= 0;
3046 barrier_interaction barrier
= barrier_none
;
3047 bool can_reorder
= true;
3048 Temp soffset
= Temp(0, s1
);
3051 using LoadCallback
= Temp(*)(
3052 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3053 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3055 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3056 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3058 unsigned load_size
= info
->num_components
* info
->component_size
;
3059 unsigned component_size
= info
->component_size
;
3061 unsigned num_vals
= 0;
3062 Temp vals
[info
->dst
.bytes()];
3064 unsigned const_offset
= info
->const_offset
;
3066 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3067 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3069 unsigned bytes_read
= 0;
3070 while (bytes_read
< load_size
) {
3071 unsigned bytes_needed
= load_size
- bytes_read
;
3073 /* add buffer for unaligned loads */
3074 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3077 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3078 if (info
->component_stride
) {
3079 assert(supports_8bit_16bit_loads
&& "unimplemented");
3083 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3084 bytes_needed
= align(bytes_needed
, 4);
3091 if (info
->swizzle_component_size
)
3092 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3093 if (info
->component_stride
)
3094 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3096 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3098 /* reduce constant offset */
3099 Operand offset
= info
->offset
;
3100 unsigned reduced_const_offset
= const_offset
;
3101 bool remove_const_offset_completely
= need_to_align_offset
;
3102 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3103 unsigned to_add
= const_offset
;
3104 if (remove_const_offset_completely
) {
3105 reduced_const_offset
= 0;
3107 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3108 reduced_const_offset
%= max_const_offset_plus_one
;
3110 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3111 if (offset
.isConstant()) {
3112 offset
= Operand(offset
.constantValue() + to_add
);
3113 } else if (offset_tmp
.regClass() == s1
) {
3114 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3115 offset_tmp
, Operand(to_add
));
3116 } else if (offset_tmp
.regClass() == v1
) {
3117 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3119 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3120 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3121 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3123 if (offset_tmp
.regClass() == s2
) {
3124 Temp carry
= bld
.tmp(s1
);
3125 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3126 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3127 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3129 Temp new_lo
= bld
.tmp(v1
);
3130 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3131 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3132 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3137 /* align offset down if needed */
3138 Operand aligned_offset
= offset
;
3139 if (need_to_align_offset
) {
3140 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3141 if (offset
.isConstant()) {
3142 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3143 } else if (offset_tmp
.regClass() == s1
) {
3144 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3145 } else if (offset_tmp
.regClass() == s2
) {
3146 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3147 } else if (offset_tmp
.regClass() == v1
) {
3148 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3149 } else if (offset_tmp
.regClass() == v2
) {
3150 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3151 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3152 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3153 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3156 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3157 bld
.copy(bld
.def(s1
), aligned_offset
);
3159 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3160 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3161 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3163 /* the callback wrote directly to dst */
3164 if (val
== info
->dst
) {
3165 assert(num_vals
== 0);
3166 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3170 /* shift result right if needed */
3171 if (info
->component_size
< 4 && byte_align_loads
) {
3172 Operand
align((uint32_t)byte_align
);
3173 if (byte_align
== -1) {
3174 if (offset
.isConstant())
3175 align
= Operand(offset
.constantValue() % 4u);
3176 else if (offset
.size() == 2)
3177 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3182 assert(val
.bytes() >= load_size
&& "unimplemented");
3183 if (val
.type() == RegType::sgpr
)
3184 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3186 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3190 /* add result to list and advance */
3191 if (info
->component_stride
) {
3192 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3193 const_offset
+= info
->component_stride
;
3194 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3196 const_offset
+= val
.bytes();
3197 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3199 bytes_read
+= val
.bytes();
3200 vals
[num_vals
++] = val
;
3203 /* create array of components */
3204 unsigned components_split
= 0;
3205 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3206 bool has_vgprs
= false;
3207 for (unsigned i
= 0; i
< num_vals
;) {
3209 unsigned num_tmps
= 0;
3210 unsigned tmp_size
= 0;
3211 RegType reg_type
= RegType::sgpr
;
3212 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3213 if (vals
[i
].type() == RegType::vgpr
)
3214 reg_type
= RegType::vgpr
;
3215 tmp_size
+= vals
[i
].bytes();
3216 tmp
[num_tmps
++] = vals
[i
++];
3219 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3220 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3221 for (unsigned i
= 0; i
< num_vals
; i
++)
3222 vec
->operands
[i
] = Operand(tmp
[i
]);
3223 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3224 vec
->definitions
[0] = Definition(tmp
[0]);
3225 bld
.insert(std::move(vec
));
3228 if (tmp
[0].bytes() % component_size
) {
3230 assert(i
== num_vals
);
3231 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3232 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3235 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3237 unsigned start
= components_split
;
3239 if (tmp_size
== elem_rc
.bytes()) {
3240 allocated_vec
[components_split
++] = tmp
[0];
3242 assert(tmp_size
% elem_rc
.bytes() == 0);
3243 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3244 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3245 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3246 Temp component
= bld
.tmp(elem_rc
);
3247 allocated_vec
[components_split
++] = component
;
3248 split
->definitions
[i
] = Definition(component
);
3250 split
->operands
[0] = Operand(tmp
[0]);
3251 bld
.insert(std::move(split
));
3254 /* try to p_as_uniform early so we can create more optimizable code and
3255 * also update allocated_vec */
3256 for (unsigned j
= start
; j
< components_split
; j
++) {
3257 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3258 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3259 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3263 /* concatenate components and p_as_uniform() result if needed */
3264 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3265 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3267 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3269 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3270 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3271 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3272 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3274 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3275 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3276 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3277 vec
->definitions
[0] = Definition(tmp
);
3278 bld
.insert(std::move(vec
));
3279 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3281 vec
->definitions
[0] = Definition(info
->dst
);
3282 bld
.insert(std::move(vec
));
3286 Operand
load_lds_size_m0(Builder
& bld
)
3288 /* TODO: m0 does not need to be initialized on GFX9+ */
3289 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3292 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3293 Temp offset
, unsigned bytes_needed
,
3294 unsigned align
, unsigned const_offset
,
3297 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3299 Operand m
= load_lds_size_m0(bld
);
3301 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3302 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3307 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3308 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3310 op
= aco_opcode::ds_read_b128
;
3311 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3314 op
= aco_opcode::ds_read2_b64
;
3315 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3317 op
= aco_opcode::ds_read_b96
;
3318 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3320 op
= aco_opcode::ds_read_b64
;
3321 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3324 op
= aco_opcode::ds_read2_b32
;
3325 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3327 op
= aco_opcode::ds_read_b32
;
3328 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3330 op
= aco_opcode::ds_read_u16
;
3333 op
= aco_opcode::ds_read_u8
;
3336 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3337 if (const_offset
>= max_offset_plus_one
) {
3338 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3339 const_offset
%= max_offset_plus_one
;
3343 const_offset
/= (size
/ 2u);
3345 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3346 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3348 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3350 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3353 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3358 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3360 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3361 Temp offset
, unsigned bytes_needed
,
3362 unsigned align
, unsigned const_offset
,
3367 if (bytes_needed
<= 4) {
3369 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3370 } else if (bytes_needed
<= 8) {
3372 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3373 } else if (bytes_needed
<= 16) {
3375 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3376 } else if (bytes_needed
<= 32) {
3378 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3381 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3383 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3384 if (info
->resource
.id()) {
3385 load
->operands
[0] = Operand(info
->resource
);
3386 load
->operands
[1] = Operand(offset
);
3388 load
->operands
[0] = Operand(offset
);
3389 load
->operands
[1] = Operand(0u);
3391 RegClass
rc(RegType::sgpr
, size
);
3392 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3393 load
->definitions
[0] = Definition(val
);
3394 load
->glc
= info
->glc
;
3395 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3396 load
->barrier
= info
->barrier
;
3397 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3398 bld
.insert(std::move(load
));
3402 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3404 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3405 Temp offset
, unsigned bytes_needed
,
3406 unsigned align_
, unsigned const_offset
,
3409 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3410 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3412 if (info
->soffset
.id()) {
3413 if (soffset
.isTemp())
3414 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3415 soffset
= Operand(info
->soffset
);
3418 unsigned bytes_size
= 0;
3420 if (bytes_needed
== 1) {
3422 op
= aco_opcode::buffer_load_ubyte
;
3423 } else if (bytes_needed
== 2) {
3425 op
= aco_opcode::buffer_load_ushort
;
3426 } else if (bytes_needed
<= 4) {
3428 op
= aco_opcode::buffer_load_dword
;
3429 } else if (bytes_needed
<= 8) {
3431 op
= aco_opcode::buffer_load_dwordx2
;
3432 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3434 op
= aco_opcode::buffer_load_dwordx3
;
3437 op
= aco_opcode::buffer_load_dwordx4
;
3439 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3440 mubuf
->operands
[0] = Operand(info
->resource
);
3441 mubuf
->operands
[1] = vaddr
;
3442 mubuf
->operands
[2] = soffset
;
3443 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3444 mubuf
->glc
= info
->glc
;
3445 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3446 mubuf
->barrier
= info
->barrier
;
3447 mubuf
->can_reorder
= info
->can_reorder
;
3448 mubuf
->offset
= const_offset
;
3449 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3450 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3451 mubuf
->definitions
[0] = Definition(val
);
3452 bld
.insert(std::move(mubuf
));
3457 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3459 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3461 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3462 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3464 if (addr
.type() == RegType::vgpr
)
3465 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3466 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3469 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3470 Temp offset
, unsigned bytes_needed
,
3471 unsigned align_
, unsigned const_offset
,
3474 unsigned bytes_size
= 0;
3475 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3476 bool global
= bld
.program
->chip_class
>= GFX9
;
3478 if (bytes_needed
== 1) {
3480 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3481 } else if (bytes_needed
== 2) {
3483 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3484 } else if (bytes_needed
<= 4) {
3486 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3487 } else if (bytes_needed
<= 8) {
3489 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3490 } else if (bytes_needed
<= 12 && !mubuf
) {
3492 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3495 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3497 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3498 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3500 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3501 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3502 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3503 mubuf
->operands
[2] = Operand(0u);
3504 mubuf
->glc
= info
->glc
;
3507 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3508 mubuf
->disable_wqm
= false;
3509 mubuf
->barrier
= info
->barrier
;
3510 mubuf
->definitions
[0] = Definition(val
);
3511 bld
.insert(std::move(mubuf
));
3513 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3515 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3516 flat
->operands
[0] = Operand(offset
);
3517 flat
->operands
[1] = Operand(s1
);
3518 flat
->glc
= info
->glc
;
3519 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3520 flat
->barrier
= info
->barrier
;
3522 flat
->definitions
[0] = Definition(val
);
3523 bld
.insert(std::move(flat
));
3529 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3531 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3532 Temp address
, unsigned base_offset
, unsigned align
)
3534 assert(util_is_power_of_two_nonzero(align
));
3536 Builder
bld(ctx
->program
, ctx
->block
);
3538 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3539 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3540 info
.align_mul
= align
;
3541 info
.align_offset
= 0;
3542 info
.barrier
= barrier_shared
;
3543 info
.can_reorder
= false;
3544 info
.const_offset
= base_offset
;
3545 emit_lds_load(ctx
, bld
, &info
);
3550 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3555 Builder
bld(ctx
->program
, ctx
->block
);
3557 ASSERTED
bool is_subdword
= false;
3558 for (unsigned i
= 0; i
< count
; i
++)
3559 is_subdword
|= offsets
[i
] % 4;
3560 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3561 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3563 /* count == 1 fast path */
3565 if (dst_type
== RegType::sgpr
)
3566 dst
[0] = bld
.as_uniform(src
);
3568 dst
[0] = as_vgpr(ctx
, src
);
3572 for (unsigned i
= 0; i
< count
- 1; i
++)
3573 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3574 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3576 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3577 src
= as_vgpr(ctx
, src
);
3579 /* use allocated_vec if possible */
3580 auto it
= ctx
->allocated_vec
.find(src
.id());
3581 if (it
!= ctx
->allocated_vec
.end()) {
3582 unsigned total_size
= 0;
3583 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3584 total_size
+= it
->second
[i
].bytes();
3585 if (total_size
!= src
.bytes())
3588 unsigned elem_size
= it
->second
[0].bytes();
3590 for (unsigned i
= 0; i
< count
; i
++) {
3591 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3595 for (unsigned i
= 0; i
< count
; i
++) {
3596 unsigned start_idx
= offsets
[i
] / elem_size
;
3597 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3598 if (op_count
== 1) {
3599 if (dst_type
== RegType::sgpr
)
3600 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3602 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3606 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3607 for (unsigned j
= 0; j
< op_count
; j
++) {
3608 Temp tmp
= it
->second
[start_idx
+ j
];
3609 if (dst_type
== RegType::sgpr
)
3610 tmp
= bld
.as_uniform(tmp
);
3611 vec
->operands
[j
] = Operand(tmp
);
3613 vec
->definitions
[0] = Definition(dst
[i
]);
3614 bld
.insert(std::move(vec
));
3620 if (dst_type
== RegType::sgpr
)
3621 src
= bld
.as_uniform(src
);
3625 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3626 split
->operands
[0] = Operand(src
);
3627 for (unsigned i
= 0; i
< count
; i
++)
3628 split
->definitions
[i
] = Definition(dst
[i
]);
3629 bld
.insert(std::move(split
));
3632 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3633 int *start
, int *count
)
3635 unsigned start_elem
= ffs(todo_mask
) - 1;
3636 bool skip
= !(mask
& (1 << start_elem
));
3638 mask
= ~mask
& todo_mask
;
3642 u_bit_scan_consecutive_range(&mask
, start
, count
);
3647 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3649 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3652 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3653 Temp address
, unsigned base_offset
, unsigned align
)
3655 assert(util_is_power_of_two_nonzero(align
));
3656 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3658 Builder
bld(ctx
->program
, ctx
->block
);
3659 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3660 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3662 unsigned write_count
= 0;
3663 Temp write_datas
[32];
3664 unsigned offsets
[32];
3665 aco_opcode opcodes
[32];
3667 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3669 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3672 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3673 offsets
[write_count
] = offset
;
3674 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3676 advance_write_mask(&todo
, offset
, bytes
);
3680 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3681 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3682 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3683 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3685 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3686 aco_opcode op
= aco_opcode::num_opcodes
;
3687 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3688 op
= aco_opcode::ds_write_b128
;
3690 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3691 op
= aco_opcode::ds_write_b96
;
3693 } else if (bytes
>= 8 && aligned8
) {
3694 op
= aco_opcode::ds_write_b64
;
3696 } else if (bytes
>= 4 && aligned4
) {
3697 op
= aco_opcode::ds_write_b32
;
3699 } else if (bytes
>= 2 && aligned2
) {
3700 op
= aco_opcode::ds_write_b16
;
3702 } else if (bytes
>= 1) {
3703 op
= aco_opcode::ds_write_b8
;
3709 offsets
[write_count
] = offset
;
3710 opcodes
[write_count
] = op
;
3712 advance_write_mask(&todo
, offset
, bytes
);
3715 Operand m
= load_lds_size_m0(bld
);
3717 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3719 for (unsigned i
= 0; i
< write_count
; i
++) {
3720 aco_opcode op
= opcodes
[i
];
3721 if (op
== aco_opcode::num_opcodes
)
3724 Temp data
= write_datas
[i
];
3726 unsigned second
= write_count
;
3727 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3728 for (second
= i
+ 1; second
< write_count
; second
++) {
3729 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3730 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3731 opcodes
[second
] = aco_opcode::num_opcodes
;
3737 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3738 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3740 unsigned inline_offset
= base_offset
+ offsets
[i
];
3741 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3742 Temp address_offset
= address
;
3743 if (inline_offset
> max_offset
) {
3744 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3745 inline_offset
= offsets
[i
];
3747 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3750 Temp second_data
= write_datas
[second
];
3751 inline_offset
/= data
.bytes();
3752 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3754 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3759 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3761 unsigned align
= 16;
3763 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3769 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3774 return aco_opcode::buffer_store_byte
;
3777 return aco_opcode::buffer_store_short
;
3779 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3781 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3784 return aco_opcode::buffer_store_dwordx3
;
3786 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3788 unreachable("Unexpected store size");
3789 return aco_opcode::num_opcodes
;
3792 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3793 Temp data
, unsigned writemask
, int swizzle_element_size
,
3794 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3796 unsigned write_count_with_skips
= 0;
3799 /* determine how to split the data */
3800 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3803 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3804 offsets
[write_count_with_skips
] = offset
;
3805 if (skips
[write_count_with_skips
]) {
3806 advance_write_mask(&todo
, offset
, bytes
);
3807 write_count_with_skips
++;
3811 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3812 * larger than swizzle_element_size */
3813 bytes
= MIN2(bytes
, swizzle_element_size
);
3815 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3817 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3818 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3821 /* dword or larger stores have to be dword-aligned */
3822 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3823 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3824 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3825 if (bytes
>= 4 && !dword_aligned
)
3826 bytes
= MIN2(bytes
, 2);
3828 advance_write_mask(&todo
, offset
, bytes
);
3829 write_count_with_skips
++;
3832 /* actually split data */
3833 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3836 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3839 write_datas
[*write_count
] = write_datas
[i
];
3840 offsets
[*write_count
] = offsets
[i
];
3845 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3846 unsigned split_cnt
= 0u, Temp dst
= Temp())
3848 Builder
bld(ctx
->program
, ctx
->block
);
3849 unsigned dword_size
= elem_size_bytes
/ 4;
3852 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3854 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3855 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3856 instr
->definitions
[0] = Definition(dst
);
3858 for (unsigned i
= 0; i
< cnt
; ++i
) {
3860 assert(arr
[i
].size() == dword_size
);
3861 allocated_vec
[i
] = arr
[i
];
3862 instr
->operands
[i
] = Operand(arr
[i
]);
3864 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3865 allocated_vec
[i
] = zero
;
3866 instr
->operands
[i
] = Operand(zero
);
3870 bld
.insert(std::move(instr
));
3873 emit_split_vector(ctx
, dst
, split_cnt
);
3875 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3880 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3882 if (const_offset
>= 4096) {
3883 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3884 const_offset
%= 4096u;
3887 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3888 else if (unlikely(voffset
.regClass() == s1
))
3889 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3890 else if (likely(voffset
.regClass() == v1
))
3891 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3893 unreachable("Unsupported register class of voffset");
3896 return const_offset
;
3899 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3900 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3903 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3904 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3906 Builder
bld(ctx
->program
, ctx
->block
);
3907 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3908 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3910 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3911 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3912 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3913 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3914 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3916 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3919 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3920 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3921 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3923 Builder
bld(ctx
->program
, ctx
->block
);
3924 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3926 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3928 unsigned write_count
= 0;
3929 Temp write_datas
[32];
3930 unsigned offsets
[32];
3931 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3932 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3934 for (unsigned i
= 0; i
< write_count
; i
++) {
3935 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3936 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3940 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3941 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3942 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3944 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3945 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3946 assert(!!stride
!= allow_combining
);
3948 Builder
bld(ctx
->program
, ctx
->block
);
3950 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3951 info
.component_stride
= allow_combining
? 0 : stride
;
3953 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3954 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3955 info
.align_offset
= 0;
3956 info
.soffset
= soffset
;
3957 info
.const_offset
= base_const_offset
;
3958 emit_mubuf_load(ctx
, bld
, &info
);
3961 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3963 Builder
bld(ctx
->program
, ctx
->block
);
3964 Temp offset
= base_offset
.first
;
3965 unsigned const_offset
= base_offset
.second
;
3967 if (!nir_src_is_const(*off_src
)) {
3968 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3971 /* Calculate indirect offset with stride */
3972 if (likely(indirect_offset_arg
.regClass() == v1
))
3973 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3974 else if (indirect_offset_arg
.regClass() == s1
)
3975 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3977 unreachable("Unsupported register class of indirect offset");
3979 /* Add to the supplied base offset */
3980 if (offset
.id() == 0)
3981 offset
= with_stride
;
3982 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3983 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3984 else if (offset
.size() == 1 && with_stride
.size() == 1)
3985 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3987 unreachable("Unsupported register class of indirect offset");
3989 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3990 const_offset
+= const_offset_arg
* stride
;
3993 return std::make_pair(offset
, const_offset
);
3996 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3998 Builder
bld(ctx
->program
, ctx
->block
);
4001 if (off1
.first
.id() && off2
.first
.id()) {
4002 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4003 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4004 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4005 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4007 unreachable("Unsupported register class of indirect offset");
4009 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4012 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4015 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4017 Builder
bld(ctx
->program
, ctx
->block
);
4018 unsigned const_offset
= offs
.second
* multiplier
;
4020 if (!offs
.first
.id())
4021 return std::make_pair(offs
.first
, const_offset
);
4023 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4024 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4025 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4027 return std::make_pair(offset
, const_offset
);
4030 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4032 Builder
bld(ctx
->program
, ctx
->block
);
4034 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4035 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4036 /* component is in bytes */
4037 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4039 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4040 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4041 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4044 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4046 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4049 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4051 Builder
bld(ctx
->program
, ctx
->block
);
4053 switch (ctx
->shader
->info
.stage
) {
4054 case MESA_SHADER_TESS_CTRL
:
4055 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4056 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4057 case MESA_SHADER_TESS_EVAL
:
4058 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4060 unreachable("Unsupported stage in get_tess_rel_patch_id");
4064 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4066 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4067 Builder
bld(ctx
->program
, ctx
->block
);
4069 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4070 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4072 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4074 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4075 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4077 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4078 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4079 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4081 return offset_mul(ctx
, offs
, 4u);
4084 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4086 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4087 Builder
bld(ctx
->program
, ctx
->block
);
4089 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4090 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4091 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4092 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4094 std::pair
<Temp
, unsigned> offs
= instr
4095 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4096 : std::make_pair(Temp(), 0u);
4098 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4099 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4104 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4105 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4107 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4108 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4110 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4111 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4117 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4119 Builder
bld(ctx
->program
, ctx
->block
);
4121 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4122 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4124 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4126 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4127 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4128 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4130 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4131 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4136 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4138 Builder
bld(ctx
->program
, ctx
->block
);
4140 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4141 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4142 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4143 unsigned attr_stride
= ctx
->tcs_num_patches
;
4145 std::pair
<Temp
, unsigned> offs
= instr
4146 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4147 : std::make_pair(Temp(), 0u);
4149 if (const_base_offset
)
4150 offs
.second
+= const_base_offset
* attr_stride
;
4152 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4153 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4154 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4159 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4161 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4166 unsigned drv_loc
= nir_intrinsic_base(instr
);
4167 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4169 if (!nir_src_is_const(*off_src
)) {
4175 uint64_t slot
= per_vertex
4176 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4177 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4178 return (((uint64_t) 1) << slot
) & mask
;
4181 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4183 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4184 unsigned component
= nir_intrinsic_component(instr
);
4185 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4187 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4188 if (off_instr
->type
!= nir_instr_type_load_const
)
4191 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4192 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4194 if (instr
->src
[0].ssa
->bit_size
== 64)
4195 write_mask
= widen_mask(write_mask
, 2);
4197 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4199 for (unsigned i
= 0; i
< 8; ++i
) {
4200 if (write_mask
& (1 << i
)) {
4201 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4202 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4210 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4212 /* Only TCS per-vertex inputs are supported by this function.
4213 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4215 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4218 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4219 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4220 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4221 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4222 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4223 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4228 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4229 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4230 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4235 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4237 Builder
bld(ctx
->program
, ctx
->block
);
4239 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4240 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4241 bool indirect_write
;
4242 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4243 if (temp_only_input
&& !indirect_write
)
4247 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4248 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4249 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4250 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4252 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4253 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4254 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4255 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4256 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4260 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4261 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4262 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4263 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4264 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4265 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4266 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4267 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4268 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4269 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4270 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4271 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4272 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4274 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4275 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4277 unreachable("Invalid LS or ES stage");
4280 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4281 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4282 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4286 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4291 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4292 return off
== ctx
->tcs_tess_lvl_out_loc
||
4293 off
== ctx
->tcs_tess_lvl_in_loc
;
4297 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4299 uint64_t mask
= per_vertex
4300 ? ctx
->program
->info
->tcs
.tes_inputs_read
4301 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4303 bool indirect_write
= false;
4304 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4305 return indirect_write
|| output_read_by_tes
;
4308 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4310 uint64_t mask
= per_vertex
4311 ? ctx
->shader
->info
.outputs_read
4312 : ctx
->shader
->info
.patch_outputs_read
;
4314 bool indirect_write
= false;
4315 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4316 return indirect_write
|| output_read
;
4319 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4321 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4322 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4324 Builder
bld(ctx
->program
, ctx
->block
);
4326 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4327 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4328 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4330 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4331 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4332 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4334 if (write_to_vmem
) {
4335 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4336 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4337 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4339 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4340 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4341 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4345 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4346 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4347 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4351 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4353 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4354 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4356 Builder
bld(ctx
->program
, ctx
->block
);
4358 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4359 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4360 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4361 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4363 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4366 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4368 if (ctx
->stage
== vertex_vs
||
4369 ctx
->stage
== tess_eval_vs
||
4370 ctx
->stage
== fragment_fs
||
4371 ctx
->stage
== ngg_vertex_gs
||
4372 ctx
->stage
== ngg_tess_eval_gs
||
4373 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4374 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4375 if (!stored_to_temps
) {
4376 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4377 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4378 fprintf(stderr
, "\n");
4381 } else if (ctx
->stage
== vertex_es
||
4382 ctx
->stage
== vertex_ls
||
4383 ctx
->stage
== tess_eval_es
||
4384 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4385 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4386 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4387 visit_store_ls_or_es_output(ctx
, instr
);
4388 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4389 visit_store_tcs_output(ctx
, instr
, false);
4391 unreachable("Shader stage not implemented");
4395 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4397 visit_load_tcs_output(ctx
, instr
, false);
4400 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4402 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4403 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4405 Builder
bld(ctx
->program
, ctx
->block
);
4407 if (dst
.regClass() == v2b
) {
4408 if (ctx
->program
->has_16bank_lds
) {
4409 assert(ctx
->options
->chip_class
<= GFX8
);
4410 Builder::Result interp_p1
=
4411 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4412 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4413 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4414 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4415 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4416 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4418 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4420 if (ctx
->options
->chip_class
== GFX8
)
4421 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4423 Builder::Result interp_p1
=
4424 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4425 coord1
, bld
.m0(prim_mask
), idx
, component
);
4426 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4427 interp_p1
, idx
, component
);
4430 Builder::Result interp_p1
=
4431 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4432 bld
.m0(prim_mask
), idx
, component
);
4434 if (ctx
->program
->has_16bank_lds
)
4435 interp_p1
.instr
->operands
[0].setLateKill(true);
4437 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4438 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4442 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4444 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4445 for (unsigned i
= 0; i
< num_components
; i
++)
4446 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4447 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4448 assert(num_components
== 4);
4449 Builder
bld(ctx
->program
, ctx
->block
);
4450 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4453 for (Operand
& op
: vec
->operands
)
4454 op
= op
.isUndefined() ? Operand(0u) : op
;
4456 vec
->definitions
[0] = Definition(dst
);
4457 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4458 emit_split_vector(ctx
, dst
, num_components
);
4462 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4464 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4465 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4466 unsigned idx
= nir_intrinsic_base(instr
);
4467 unsigned component
= nir_intrinsic_component(instr
);
4468 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4470 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4472 assert(offset
->u32
== 0);
4474 /* the lower 15bit of the prim_mask contain the offset into LDS
4475 * while the upper bits contain the number of prims */
4476 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4477 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4478 Builder
bld(ctx
->program
, ctx
->block
);
4479 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4480 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4481 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4482 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4483 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4486 if (instr
->dest
.ssa
.num_components
== 1) {
4487 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4489 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4490 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4492 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4493 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4494 vec
->operands
[i
] = Operand(tmp
);
4496 vec
->definitions
[0] = Definition(dst
);
4497 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4501 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4502 unsigned offset
, unsigned stride
, unsigned channels
)
4504 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4505 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4507 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4508 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4511 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4512 unsigned offset
, unsigned stride
, unsigned *channels
)
4514 if (!vtx_info
->chan_byte_size
) {
4515 *channels
= vtx_info
->num_channels
;
4516 return vtx_info
->chan_format
;
4519 unsigned num_channels
= *channels
;
4520 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4521 unsigned new_channels
= num_channels
+ 1;
4522 /* first, assume more loads is worse and try using a larger data format */
4523 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4525 /* don't make the attribute potentially out-of-bounds */
4526 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4530 if (new_channels
== 5) {
4531 /* then try decreasing load size (at the cost of more loads) */
4532 new_channels
= *channels
;
4533 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4537 if (new_channels
< *channels
)
4538 *channels
= new_channels
;
4539 num_channels
= new_channels
;
4542 switch (vtx_info
->chan_format
) {
4543 case V_008F0C_BUF_DATA_FORMAT_8
:
4544 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4545 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4546 case V_008F0C_BUF_DATA_FORMAT_16
:
4547 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4548 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4549 case V_008F0C_BUF_DATA_FORMAT_32
:
4550 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4551 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4553 unreachable("shouldn't reach here");
4554 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4557 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4558 * so we may need to fix it up. */
4559 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4561 Builder
bld(ctx
->program
, ctx
->block
);
4563 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4564 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4566 /* For the integer-like cases, do a natural sign extension.
4568 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4569 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4572 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4573 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4575 /* Convert back to the right type. */
4576 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4577 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4578 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4579 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4580 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4581 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4587 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4589 Builder
bld(ctx
->program
, ctx
->block
);
4590 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4591 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4593 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4594 if (off_instr
->type
!= nir_instr_type_load_const
) {
4595 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4596 nir_print_instr(off_instr
, stderr
);
4597 fprintf(stderr
, "\n");
4599 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4601 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4603 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4604 unsigned component
= nir_intrinsic_component(instr
);
4605 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4606 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4607 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4608 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4609 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4611 unsigned dfmt
= attrib_format
& 0xf;
4612 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4613 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4615 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4616 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4617 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4618 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4620 num_channels
= MAX2(num_channels
, 3);
4622 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4623 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4626 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4627 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4628 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4630 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4632 Temp divided
= bld
.tmp(v1
);
4633 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4634 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4636 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4639 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4642 index
= bld
.vadd32(bld
.def(v1
),
4643 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4644 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4647 Temp channels
[num_channels
];
4648 unsigned channel_start
= 0;
4649 bool direct_fetch
= false;
4651 /* skip unused channels at the start */
4652 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4653 channel_start
= ffs(mask
) - 1;
4654 for (unsigned i
= 0; i
< channel_start
; i
++)
4655 channels
[i
] = Temp(0, s1
);
4656 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4657 num_channels
= 3 - (ffs(mask
) - 1);
4661 while (channel_start
< num_channels
) {
4662 unsigned fetch_component
= num_channels
- channel_start
;
4663 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4664 bool expanded
= false;
4666 /* use MUBUF when possible to avoid possible alignment issues */
4667 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4668 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4669 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4670 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4671 vtx_info
->chan_byte_size
== 4;
4672 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4674 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4676 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4677 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4678 fetch_component
= 4;
4683 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4685 Temp fetch_index
= index
;
4686 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4687 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4688 fetch_offset
= fetch_offset
% attrib_stride
;
4691 Operand
soffset(0u);
4692 if (fetch_offset
>= 4096) {
4693 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4694 fetch_offset
%= 4096;
4698 switch (fetch_bytes
) {
4700 assert(!use_mubuf
&& bitsize
== 16);
4701 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4704 if (bitsize
== 16) {
4706 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4708 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4712 assert(!use_mubuf
&& bitsize
== 16);
4713 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4716 if (bitsize
== 16) {
4718 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4720 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4724 assert(ctx
->options
->chip_class
>= GFX7
||
4725 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4726 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4729 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4732 unreachable("Unimplemented load_input vector size");
4736 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4737 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4738 num_channels
<= 3)) {
4739 direct_fetch
= true;
4742 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4746 Instruction
*mubuf
= bld
.mubuf(opcode
,
4747 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4748 fetch_offset
, false, true).instr
;
4749 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4751 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4752 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4753 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4754 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4757 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4759 if (fetch_component
== 1) {
4760 channels
[channel_start
] = fetch_dst
;
4762 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4763 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4764 bitsize
== 16 ? v2b
: v1
);
4767 channel_start
+= fetch_component
;
4770 if (!direct_fetch
) {
4771 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4772 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4774 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4775 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4776 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4778 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4779 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4780 unsigned num_temp
= 0;
4781 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4782 unsigned idx
= i
+ component
;
4783 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4784 Temp channel
= channels
[swizzle
[idx
]];
4785 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4786 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4787 vec
->operands
[i
] = Operand(channel
);
4791 } else if (is_float
&& idx
== 3) {
4792 vec
->operands
[i
] = Operand(0x3f800000u
);
4793 } else if (!is_float
&& idx
== 3) {
4794 vec
->operands
[i
] = Operand(1u);
4796 vec
->operands
[i
] = Operand(0u);
4799 vec
->definitions
[0] = Definition(dst
);
4800 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4801 emit_split_vector(ctx
, dst
, dst
.size());
4803 if (num_temp
== dst
.size())
4804 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4806 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4807 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4808 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4809 if (off_instr
->type
!= nir_instr_type_load_const
||
4810 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4811 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4812 nir_print_instr(off_instr
, stderr
);
4813 fprintf(stderr
, "\n");
4816 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4817 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4819 assert(offset
->u32
== 0);
4821 /* the lower 15bit of the prim_mask contain the offset into LDS
4822 * while the upper bits contain the number of prims */
4823 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4824 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4825 Builder
bld(ctx
->program
, ctx
->block
);
4826 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4827 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4828 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4829 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4830 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4833 unsigned idx
= nir_intrinsic_base(instr
);
4834 unsigned component
= nir_intrinsic_component(instr
);
4835 unsigned vertex_id
= 2; /* P0 */
4837 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4838 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4839 switch (src0
->u32
) {
4841 vertex_id
= 2; /* P0 */
4844 vertex_id
= 0; /* P10 */
4847 vertex_id
= 1; /* P20 */
4850 unreachable("invalid vertex index");
4854 if (dst
.size() == 1) {
4855 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4857 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4858 for (unsigned i
= 0; i
< dst
.size(); i
++)
4859 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4860 vec
->definitions
[0] = Definition(dst
);
4861 bld
.insert(std::move(vec
));
4864 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4865 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4866 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4867 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4868 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4870 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4872 unreachable("Shader stage not implemented");
4876 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4878 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4880 Builder
bld(ctx
->program
, ctx
->block
);
4881 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4884 if (!nir_src_is_const(*vertex_src
)) {
4885 /* better code could be created, but this case probably doesn't happen
4886 * much in practice */
4887 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4888 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4891 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4892 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4894 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4896 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4899 if (vertex_offset
.id()) {
4900 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4901 Operand(i
), indirect_vertex
);
4902 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4904 vertex_offset
= elem
;
4908 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4909 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4911 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4912 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4913 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4914 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4915 Operand((vertex
% 2u) * 16u), Operand(16u));
4917 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4920 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4921 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4922 return offset_mul(ctx
, offs
, 4u);
4925 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4927 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4929 Builder
bld(ctx
->program
, ctx
->block
);
4930 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4931 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4933 if (ctx
->stage
== geometry_gs
) {
4934 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4935 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4936 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4937 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4938 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4939 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4940 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4942 unreachable("Unsupported GS stage.");
4946 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4948 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4950 Builder
bld(ctx
->program
, ctx
->block
);
4951 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4953 if (load_input_from_temps(ctx
, instr
, dst
))
4956 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4957 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4958 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4960 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4963 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4965 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4967 Builder
bld(ctx
->program
, ctx
->block
);
4969 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4970 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4973 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4974 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4976 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4979 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4981 switch (ctx
->shader
->info
.stage
) {
4982 case MESA_SHADER_GEOMETRY
:
4983 visit_load_gs_per_vertex_input(ctx
, instr
);
4985 case MESA_SHADER_TESS_CTRL
:
4986 visit_load_tcs_per_vertex_input(ctx
, instr
);
4988 case MESA_SHADER_TESS_EVAL
:
4989 visit_load_tes_per_vertex_input(ctx
, instr
);
4992 unreachable("Unimplemented shader stage");
4996 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4998 visit_load_tcs_output(ctx
, instr
, true);
5001 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5003 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5004 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5006 visit_store_tcs_output(ctx
, instr
, true);
5009 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5011 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5013 Builder
bld(ctx
->program
, ctx
->block
);
5014 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5016 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5017 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5020 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5021 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5022 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5023 tes_w
= Operand(tmp
);
5026 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5027 emit_split_vector(ctx
, tess_coord
, 3);
5030 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5032 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5033 Builder
bld(ctx
->program
, ctx
->block
);
5034 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5035 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5036 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5039 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5043 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5045 Builder
bld(ctx
->program
, ctx
->block
);
5046 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5047 if (!nir_dest_is_divergent(instr
->dest
))
5048 index
= bld
.as_uniform(index
);
5049 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5050 unsigned binding
= nir_intrinsic_binding(instr
);
5053 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5054 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5055 unsigned offset
= layout
->binding
[binding
].offset
;
5057 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5058 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5059 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5060 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5061 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5064 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5065 stride
= layout
->binding
[binding
].size
;
5068 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5069 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5071 if (nir_const_index
) {
5072 const_index
= const_index
* stride
;
5073 } else if (index
.type() == RegType::vgpr
) {
5074 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5075 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5077 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5081 if (nir_const_index
) {
5082 const_index
= const_index
+ offset
;
5083 } else if (index
.type() == RegType::vgpr
) {
5084 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5086 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5090 if (nir_const_index
&& const_index
== 0) {
5092 } else if (index
.type() == RegType::vgpr
) {
5093 index
= bld
.vadd32(bld
.def(v1
),
5094 nir_const_index
? Operand(const_index
) : Operand(index
),
5097 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5098 nir_const_index
? Operand(const_index
) : Operand(index
),
5102 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5105 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5106 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5107 bool glc
=false, bool readonly
=true)
5109 Builder
bld(ctx
->program
, ctx
->block
);
5111 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5113 offset
= bld
.as_uniform(offset
);
5115 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5117 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5118 info
.can_reorder
= readonly
;
5119 info
.align_mul
= align_mul
;
5120 info
.align_offset
= align_offset
;
5122 emit_smem_load(ctx
, bld
, &info
);
5124 emit_mubuf_load(ctx
, bld
, &info
);
5127 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5129 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5130 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5132 Builder
bld(ctx
->program
, ctx
->block
);
5134 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5135 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5136 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5137 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5139 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5140 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5141 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5142 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5143 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5144 if (ctx
->options
->chip_class
>= GFX10
) {
5145 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5146 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5147 S_008F0C_RESOURCE_LEVEL(1);
5149 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5150 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5152 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5153 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5154 Operand(0xFFFFFFFFu
),
5155 Operand(desc_type
));
5156 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5157 rsrc
, upper_dwords
);
5159 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5160 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5162 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5163 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5164 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5167 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5169 Builder
bld(ctx
->program
, ctx
->block
);
5170 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5171 unsigned offset
= nir_intrinsic_base(instr
);
5172 unsigned count
= instr
->dest
.ssa
.num_components
;
5173 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5175 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5176 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5177 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5178 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5179 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5180 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5181 for (unsigned i
= 0; i
< count
; ++i
) {
5182 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5183 vec
->operands
[i
] = Operand
{elems
[i
]};
5185 vec
->definitions
[0] = Definition(dst
);
5186 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5187 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5192 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5193 if (offset
!= 0) // TODO check if index != 0 as well
5194 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5195 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5198 bool aligned
= true;
5200 if (instr
->dest
.ssa
.bit_size
== 8) {
5201 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5202 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5204 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5205 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5206 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5208 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5213 switch (vec
.size()) {
5215 op
= aco_opcode::s_load_dword
;
5218 op
= aco_opcode::s_load_dwordx2
;
5224 op
= aco_opcode::s_load_dwordx4
;
5230 op
= aco_opcode::s_load_dwordx8
;
5233 unreachable("unimplemented or forbidden load_push_constant.");
5236 bld
.smem(op
, Definition(vec
), ptr
, index
);
5239 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5240 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5245 emit_split_vector(ctx
, vec
, 4);
5246 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5247 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5248 emit_extract_vector(ctx
, vec
, 0, rc
),
5249 emit_extract_vector(ctx
, vec
, 1, rc
),
5250 emit_extract_vector(ctx
, vec
, 2, rc
));
5253 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5256 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5258 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5260 Builder
bld(ctx
->program
, ctx
->block
);
5262 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5263 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5264 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5265 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5266 if (ctx
->options
->chip_class
>= GFX10
) {
5267 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5268 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5269 S_008F0C_RESOURCE_LEVEL(1);
5271 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5272 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5275 unsigned base
= nir_intrinsic_base(instr
);
5276 unsigned range
= nir_intrinsic_range(instr
);
5278 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5279 if (base
&& offset
.type() == RegType::sgpr
)
5280 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5281 else if (base
&& offset
.type() == RegType::vgpr
)
5282 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5284 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5285 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5286 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5287 Operand(desc_type
));
5288 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5289 // TODO: get alignment information for subdword constants
5290 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5293 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5295 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5296 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5298 ctx
->program
->needs_exact
= true;
5300 // TODO: optimize uniform conditions
5301 Builder
bld(ctx
->program
, ctx
->block
);
5302 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5303 assert(src
.regClass() == bld
.lm
);
5304 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5305 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5306 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5310 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5312 Builder
bld(ctx
->program
, ctx
->block
);
5314 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5315 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5317 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5318 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5320 if (ctx
->block
->loop_nest_depth
&&
5321 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5322 /* we handle discards the same way as jump instructions */
5323 append_logical_end(ctx
->block
);
5325 /* in loops, discard behaves like break */
5326 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5327 ctx
->block
->kind
|= block_kind_discard
;
5330 /* uniform discard - loop ends here */
5331 assert(nir_instr_is_last(&instr
->instr
));
5332 ctx
->block
->kind
|= block_kind_uniform
;
5333 ctx
->cf_info
.has_branch
= true;
5334 bld
.branch(aco_opcode::p_branch
);
5335 add_linear_edge(ctx
->block
->index
, linear_target
);
5339 /* we add a break right behind the discard() instructions */
5340 ctx
->block
->kind
|= block_kind_break
;
5341 unsigned idx
= ctx
->block
->index
;
5343 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5344 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5346 /* remove critical edges from linear CFG */
5347 bld
.branch(aco_opcode::p_branch
);
5348 Block
* break_block
= ctx
->program
->create_and_insert_block();
5349 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5350 break_block
->kind
|= block_kind_uniform
;
5351 add_linear_edge(idx
, break_block
);
5352 add_linear_edge(break_block
->index
, linear_target
);
5353 bld
.reset(break_block
);
5354 bld
.branch(aco_opcode::p_branch
);
5356 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5357 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5358 add_linear_edge(idx
, continue_block
);
5359 append_logical_start(continue_block
);
5360 ctx
->block
= continue_block
;
5365 /* it can currently happen that NIR doesn't remove the unreachable code */
5366 if (!nir_instr_is_last(&instr
->instr
)) {
5367 ctx
->program
->needs_exact
= true;
5368 /* save exec somewhere temporarily so that it doesn't get
5369 * overwritten before the discard from outer exec masks */
5370 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5371 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5372 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5376 /* This condition is incorrect for uniformly branched discards in a loop
5377 * predicated by a divergent condition, but the above code catches that case
5378 * and the discard would end up turning into a discard_if.
5388 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5389 /* program just ends here */
5390 ctx
->block
->kind
|= block_kind_uniform
;
5391 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5392 0 /* enabled mask */, 9 /* dest */,
5393 false /* compressed */, true/* done */, true /* valid mask */);
5394 bld
.sopp(aco_opcode::s_endpgm
);
5395 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5397 ctx
->block
->kind
|= block_kind_discard
;
5398 /* branch and linear edge is added by visit_if() */
5402 enum aco_descriptor_type
{
5413 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5414 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5416 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5417 return dim
== ac_image_cube
||
5418 dim
== ac_image_1darray
||
5419 dim
== ac_image_2darray
||
5420 dim
== ac_image_2darraymsaa
;
5423 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5424 enum aco_descriptor_type desc_type
,
5425 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5427 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5428 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5429 if (it != ctx->tex_desc.end())
5432 Temp index
= Temp();
5433 bool index_set
= false;
5434 unsigned constant_index
= 0;
5435 unsigned descriptor_set
;
5436 unsigned base_index
;
5437 Builder
bld(ctx
->program
, ctx
->block
);
5440 assert(tex_instr
&& !image
);
5442 base_index
= tex_instr
->sampler_index
;
5444 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5445 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5449 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5450 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5452 constant_index
+= array_size
* const_value
->u32
;
5454 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5455 if (indirect
.type() == RegType::vgpr
)
5456 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5458 if (array_size
!= 1)
5459 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5465 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5469 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5471 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5472 base_index
= deref_instr
->var
->data
.binding
;
5475 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5476 list
= convert_pointer_to_64_bit(ctx
, list
);
5478 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5479 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5480 unsigned offset
= binding
->offset
;
5481 unsigned stride
= binding
->size
;
5485 assert(base_index
< layout
->binding_count
);
5487 switch (desc_type
) {
5488 case ACO_DESC_IMAGE
:
5490 opcode
= aco_opcode::s_load_dwordx8
;
5492 case ACO_DESC_FMASK
:
5494 opcode
= aco_opcode::s_load_dwordx8
;
5497 case ACO_DESC_SAMPLER
:
5499 opcode
= aco_opcode::s_load_dwordx4
;
5500 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5501 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5503 case ACO_DESC_BUFFER
:
5505 opcode
= aco_opcode::s_load_dwordx4
;
5507 case ACO_DESC_PLANE_0
:
5508 case ACO_DESC_PLANE_1
:
5510 opcode
= aco_opcode::s_load_dwordx8
;
5511 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5513 case ACO_DESC_PLANE_2
:
5515 opcode
= aco_opcode::s_load_dwordx4
;
5519 unreachable("invalid desc_type\n");
5522 offset
+= constant_index
* stride
;
5524 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5525 (!index_set
|| binding
->immutable_samplers_equal
)) {
5526 if (binding
->immutable_samplers_equal
)
5529 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5530 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5531 Operand(samplers
[constant_index
* 4 + 0]),
5532 Operand(samplers
[constant_index
* 4 + 1]),
5533 Operand(samplers
[constant_index
* 4 + 2]),
5534 Operand(samplers
[constant_index
* 4 + 3]));
5539 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5541 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5542 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5545 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5547 if (desc_type
== ACO_DESC_PLANE_2
) {
5549 for (unsigned i
= 0; i
< 8; i
++)
5550 components
[i
] = bld
.tmp(s1
);
5551 bld
.pseudo(aco_opcode::p_split_vector
,
5552 Definition(components
[0]),
5553 Definition(components
[1]),
5554 Definition(components
[2]),
5555 Definition(components
[3]),
5558 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5559 bld
.pseudo(aco_opcode::p_split_vector
,
5560 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5561 Definition(components
[4]),
5562 Definition(components
[5]),
5563 Definition(components
[6]),
5564 Definition(components
[7]),
5567 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5568 components
[0], components
[1], components
[2], components
[3],
5569 components
[4], components
[5], components
[6], components
[7]);
5575 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5578 case GLSL_SAMPLER_DIM_BUF
:
5580 case GLSL_SAMPLER_DIM_1D
:
5581 return array
? 2 : 1;
5582 case GLSL_SAMPLER_DIM_2D
:
5583 return array
? 3 : 2;
5584 case GLSL_SAMPLER_DIM_MS
:
5585 return array
? 4 : 3;
5586 case GLSL_SAMPLER_DIM_3D
:
5587 case GLSL_SAMPLER_DIM_CUBE
:
5589 case GLSL_SAMPLER_DIM_RECT
:
5590 case GLSL_SAMPLER_DIM_SUBPASS
:
5592 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5601 /* Adjust the sample index according to FMASK.
5603 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5604 * which is the identity mapping. Each nibble says which physical sample
5605 * should be fetched to get that sample.
5607 * For example, 0x11111100 means there are only 2 samples stored and
5608 * the second sample covers 3/4 of the pixel. When reading samples 0
5609 * and 1, return physical sample 0 (determined by the first two 0s
5610 * in FMASK), otherwise return physical sample 1.
5612 * The sample index should be adjusted as follows:
5613 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5615 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5617 Builder
bld(ctx
->program
, ctx
->block
);
5618 Temp fmask
= bld
.tmp(v1
);
5619 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5620 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5623 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5624 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5625 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5626 load
->operands
[0] = Operand(fmask_desc_ptr
);
5627 load
->operands
[1] = Operand(s4
); /* no sampler */
5628 load
->operands
[2] = Operand(coord
);
5629 load
->definitions
[0] = Definition(fmask
);
5636 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5637 ctx
->block
->instructions
.emplace_back(std::move(load
));
5639 Operand sample_index4
;
5640 if (sample_index
.isConstant()) {
5641 if (sample_index
.constantValue() < 16) {
5642 sample_index4
= Operand(sample_index
.constantValue() << 2);
5644 sample_index4
= Operand(0u);
5646 } else if (sample_index
.regClass() == s1
) {
5647 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5649 assert(sample_index
.regClass() == v1
);
5650 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5654 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5655 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5656 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5657 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5659 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5661 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5662 * resource descriptor is 0 (invalid),
5664 Temp compare
= bld
.tmp(bld
.lm
);
5665 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5666 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5668 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5670 /* Replace the MSAA sample index. */
5671 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5674 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5677 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5678 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5679 bool is_array
= glsl_sampler_type_is_array(type
);
5680 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5681 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5682 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5683 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5684 int count
= image_type_to_components_count(dim
, is_array
);
5685 std::vector
<Temp
> coords(count
);
5686 Builder
bld(ctx
->program
, ctx
->block
);
5690 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5691 /* get sample index */
5692 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5693 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5694 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5695 std::vector
<Temp
> fmask_load_address
;
5696 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5697 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5699 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5700 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5702 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5707 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5708 coords
.resize(coords
.size() + 1);
5709 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5711 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5713 for (int i
= 0; i
< count
; i
++)
5714 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5717 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5718 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5719 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5720 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5723 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5726 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5727 for (unsigned i
= 0; i
< coords
.size(); i
++)
5728 vec
->operands
[i
] = Operand(coords
[i
]);
5729 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5730 vec
->definitions
[0] = Definition(res
);
5731 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5736 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5738 Builder
bld(ctx
->program
, ctx
->block
);
5739 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5740 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5741 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5742 bool is_array
= glsl_sampler_type_is_array(type
);
5743 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5745 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5746 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5747 unsigned num_channels
= util_last_bit(mask
);
5748 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5749 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5752 switch (num_channels
) {
5754 opcode
= aco_opcode::buffer_load_format_x
;
5757 opcode
= aco_opcode::buffer_load_format_xy
;
5760 opcode
= aco_opcode::buffer_load_format_xyz
;
5763 opcode
= aco_opcode::buffer_load_format_xyzw
;
5766 unreachable(">4 channel buffer image load");
5768 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5769 load
->operands
[0] = Operand(rsrc
);
5770 load
->operands
[1] = Operand(vindex
);
5771 load
->operands
[2] = Operand((uint32_t) 0);
5773 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5776 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5777 load
->definitions
[0] = Definition(tmp
);
5779 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5780 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5781 load
->barrier
= barrier_image
;
5782 ctx
->block
->instructions
.emplace_back(std::move(load
));
5784 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5788 Temp coords
= get_image_coords(ctx
, instr
, type
);
5789 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5791 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5792 unsigned num_components
= util_bitcount(dmask
);
5794 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5797 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5799 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5800 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5802 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5803 load
->operands
[0] = Operand(resource
);
5804 load
->operands
[1] = Operand(s4
); /* no sampler */
5805 load
->operands
[2] = Operand(coords
);
5806 load
->definitions
[0] = Definition(tmp
);
5807 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5808 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5809 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5810 load
->dmask
= dmask
;
5812 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5813 load
->barrier
= barrier_image
;
5814 ctx
->block
->instructions
.emplace_back(std::move(load
));
5816 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5820 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5822 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5823 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5824 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5825 bool is_array
= glsl_sampler_type_is_array(type
);
5826 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5828 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5830 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5831 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5832 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5834 switch (data
.size()) {
5836 opcode
= aco_opcode::buffer_store_format_x
;
5839 opcode
= aco_opcode::buffer_store_format_xy
;
5842 opcode
= aco_opcode::buffer_store_format_xyz
;
5845 opcode
= aco_opcode::buffer_store_format_xyzw
;
5848 unreachable(">4 channel buffer image store");
5850 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5851 store
->operands
[0] = Operand(rsrc
);
5852 store
->operands
[1] = Operand(vindex
);
5853 store
->operands
[2] = Operand((uint32_t) 0);
5854 store
->operands
[3] = Operand(data
);
5855 store
->idxen
= true;
5858 store
->disable_wqm
= true;
5859 store
->barrier
= barrier_image
;
5860 ctx
->program
->needs_exact
= true;
5861 ctx
->block
->instructions
.emplace_back(std::move(store
));
5865 assert(data
.type() == RegType::vgpr
);
5866 Temp coords
= get_image_coords(ctx
, instr
, type
);
5867 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5869 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5870 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5872 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5873 store
->operands
[0] = Operand(resource
);
5874 store
->operands
[1] = Operand(data
);
5875 store
->operands
[2] = Operand(coords
);
5878 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5879 store
->dmask
= (1 << data
.size()) - 1;
5881 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5882 store
->disable_wqm
= true;
5883 store
->barrier
= barrier_image
;
5884 ctx
->program
->needs_exact
= true;
5885 ctx
->block
->instructions
.emplace_back(std::move(store
));
5889 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5891 /* return the previous value if dest is ever used */
5892 bool return_previous
= false;
5893 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5894 return_previous
= true;
5897 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5898 return_previous
= true;
5902 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5903 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5904 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5905 bool is_array
= glsl_sampler_type_is_array(type
);
5906 Builder
bld(ctx
->program
, ctx
->block
);
5908 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5909 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5911 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5912 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5914 aco_opcode buf_op
, image_op
;
5915 switch (instr
->intrinsic
) {
5916 case nir_intrinsic_image_deref_atomic_add
:
5917 buf_op
= aco_opcode::buffer_atomic_add
;
5918 image_op
= aco_opcode::image_atomic_add
;
5920 case nir_intrinsic_image_deref_atomic_umin
:
5921 buf_op
= aco_opcode::buffer_atomic_umin
;
5922 image_op
= aco_opcode::image_atomic_umin
;
5924 case nir_intrinsic_image_deref_atomic_imin
:
5925 buf_op
= aco_opcode::buffer_atomic_smin
;
5926 image_op
= aco_opcode::image_atomic_smin
;
5928 case nir_intrinsic_image_deref_atomic_umax
:
5929 buf_op
= aco_opcode::buffer_atomic_umax
;
5930 image_op
= aco_opcode::image_atomic_umax
;
5932 case nir_intrinsic_image_deref_atomic_imax
:
5933 buf_op
= aco_opcode::buffer_atomic_smax
;
5934 image_op
= aco_opcode::image_atomic_smax
;
5936 case nir_intrinsic_image_deref_atomic_and
:
5937 buf_op
= aco_opcode::buffer_atomic_and
;
5938 image_op
= aco_opcode::image_atomic_and
;
5940 case nir_intrinsic_image_deref_atomic_or
:
5941 buf_op
= aco_opcode::buffer_atomic_or
;
5942 image_op
= aco_opcode::image_atomic_or
;
5944 case nir_intrinsic_image_deref_atomic_xor
:
5945 buf_op
= aco_opcode::buffer_atomic_xor
;
5946 image_op
= aco_opcode::image_atomic_xor
;
5948 case nir_intrinsic_image_deref_atomic_exchange
:
5949 buf_op
= aco_opcode::buffer_atomic_swap
;
5950 image_op
= aco_opcode::image_atomic_swap
;
5952 case nir_intrinsic_image_deref_atomic_comp_swap
:
5953 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5954 image_op
= aco_opcode::image_atomic_cmpswap
;
5957 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5960 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5962 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5963 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5964 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5965 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5966 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5967 mubuf
->operands
[0] = Operand(resource
);
5968 mubuf
->operands
[1] = Operand(vindex
);
5969 mubuf
->operands
[2] = Operand((uint32_t)0);
5970 mubuf
->operands
[3] = Operand(data
);
5971 if (return_previous
)
5972 mubuf
->definitions
[0] = Definition(dst
);
5974 mubuf
->idxen
= true;
5975 mubuf
->glc
= return_previous
;
5976 mubuf
->dlc
= false; /* Not needed for atomics */
5977 mubuf
->disable_wqm
= true;
5978 mubuf
->barrier
= barrier_image
;
5979 ctx
->program
->needs_exact
= true;
5980 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5984 Temp coords
= get_image_coords(ctx
, instr
, type
);
5985 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5986 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5987 mimg
->operands
[0] = Operand(resource
);
5988 mimg
->operands
[1] = Operand(data
);
5989 mimg
->operands
[2] = Operand(coords
);
5990 if (return_previous
)
5991 mimg
->definitions
[0] = Definition(dst
);
5992 mimg
->glc
= return_previous
;
5993 mimg
->dlc
= false; /* Not needed for atomics */
5994 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5995 mimg
->dmask
= (1 << data
.size()) - 1;
5997 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5998 mimg
->disable_wqm
= true;
5999 mimg
->barrier
= barrier_image
;
6000 ctx
->program
->needs_exact
= true;
6001 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6005 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6007 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6008 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6009 Builder
bld(ctx
->program
, ctx
->block
);
6011 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6013 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6014 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6016 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6017 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6019 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6020 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6022 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6023 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6024 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6025 if (dst
.type() == RegType::vgpr
)
6026 bld
.copy(Definition(dst
), shr_dst
);
6028 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6030 emit_extract_vector(ctx
, desc
, 2, dst
);
6034 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6036 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6037 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6038 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6039 bool is_array
= glsl_sampler_type_is_array(type
);
6040 Builder
bld(ctx
->program
, ctx
->block
);
6042 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6043 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6044 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6048 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6051 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6053 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6055 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6056 mimg
->operands
[0] = Operand(resource
);
6057 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6058 mimg
->operands
[2] = Operand(lod
);
6059 uint8_t& dmask
= mimg
->dmask
;
6060 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6061 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6062 mimg
->da
= glsl_sampler_type_is_array(type
);
6063 mimg
->can_reorder
= true;
6064 Definition
& def
= mimg
->definitions
[0];
6065 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6067 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6068 glsl_sampler_type_is_array(type
)) {
6070 assert(instr
->dest
.ssa
.num_components
== 3);
6071 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6072 def
= Definition(tmp
);
6073 emit_split_vector(ctx
, tmp
, 3);
6075 /* divide 3rd value by 6 by multiplying with magic number */
6076 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6077 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6079 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6080 emit_extract_vector(ctx
, tmp
, 0, v1
),
6081 emit_extract_vector(ctx
, tmp
, 1, v1
),
6084 } else if (ctx
->options
->chip_class
== GFX9
&&
6085 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6086 glsl_sampler_type_is_array(type
)) {
6087 assert(instr
->dest
.ssa
.num_components
== 2);
6088 def
= Definition(dst
);
6091 def
= Definition(dst
);
6094 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6097 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6099 Builder
bld(ctx
->program
, ctx
->block
);
6100 unsigned num_components
= instr
->num_components
;
6102 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6103 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6104 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6106 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6107 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6108 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6109 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6112 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6114 Builder
bld(ctx
->program
, ctx
->block
);
6115 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6116 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6117 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6118 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6120 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6121 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6123 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6124 ctx
->options
->chip_class
>= GFX8
&&
6125 elem_size_bytes
>= 4;
6127 offset
= bld
.as_uniform(offset
);
6128 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6130 unsigned write_count
= 0;
6131 Temp write_datas
[32];
6132 unsigned offsets
[32];
6133 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6134 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6136 for (unsigned i
= 0; i
< write_count
; i
++) {
6137 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6138 if (smem
&& ctx
->stage
== fragment_fs
)
6139 op
= aco_opcode::p_fs_buffer_store_smem
;
6142 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6143 store
->operands
[0] = Operand(rsrc
);
6145 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6146 offset
, Operand(offsets
[i
]));
6147 store
->operands
[1] = Operand(off
);
6149 store
->operands
[1] = Operand(offset
);
6151 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6152 store
->operands
[1].setFixed(m0
);
6153 store
->operands
[2] = Operand(write_datas
[i
]);
6154 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6156 store
->disable_wqm
= true;
6157 store
->barrier
= barrier_buffer
;
6158 ctx
->block
->instructions
.emplace_back(std::move(store
));
6159 ctx
->program
->wb_smem_l1_on_end
= true;
6160 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6161 ctx
->block
->kind
|= block_kind_needs_lowering
;
6162 ctx
->program
->needs_exact
= true;
6165 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6166 store
->operands
[0] = Operand(rsrc
);
6167 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6168 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6169 store
->operands
[3] = Operand(write_datas
[i
]);
6170 store
->offset
= offsets
[i
];
6171 store
->offen
= (offset
.type() == RegType::vgpr
);
6172 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6174 store
->disable_wqm
= true;
6175 store
->barrier
= barrier_buffer
;
6176 ctx
->program
->needs_exact
= true;
6177 ctx
->block
->instructions
.emplace_back(std::move(store
));
6182 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6184 /* return the previous value if dest is ever used */
6185 bool return_previous
= false;
6186 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6187 return_previous
= true;
6190 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6191 return_previous
= true;
6195 Builder
bld(ctx
->program
, ctx
->block
);
6196 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6198 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6199 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6200 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6202 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6203 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6204 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6206 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6208 aco_opcode op32
, op64
;
6209 switch (instr
->intrinsic
) {
6210 case nir_intrinsic_ssbo_atomic_add
:
6211 op32
= aco_opcode::buffer_atomic_add
;
6212 op64
= aco_opcode::buffer_atomic_add_x2
;
6214 case nir_intrinsic_ssbo_atomic_imin
:
6215 op32
= aco_opcode::buffer_atomic_smin
;
6216 op64
= aco_opcode::buffer_atomic_smin_x2
;
6218 case nir_intrinsic_ssbo_atomic_umin
:
6219 op32
= aco_opcode::buffer_atomic_umin
;
6220 op64
= aco_opcode::buffer_atomic_umin_x2
;
6222 case nir_intrinsic_ssbo_atomic_imax
:
6223 op32
= aco_opcode::buffer_atomic_smax
;
6224 op64
= aco_opcode::buffer_atomic_smax_x2
;
6226 case nir_intrinsic_ssbo_atomic_umax
:
6227 op32
= aco_opcode::buffer_atomic_umax
;
6228 op64
= aco_opcode::buffer_atomic_umax_x2
;
6230 case nir_intrinsic_ssbo_atomic_and
:
6231 op32
= aco_opcode::buffer_atomic_and
;
6232 op64
= aco_opcode::buffer_atomic_and_x2
;
6234 case nir_intrinsic_ssbo_atomic_or
:
6235 op32
= aco_opcode::buffer_atomic_or
;
6236 op64
= aco_opcode::buffer_atomic_or_x2
;
6238 case nir_intrinsic_ssbo_atomic_xor
:
6239 op32
= aco_opcode::buffer_atomic_xor
;
6240 op64
= aco_opcode::buffer_atomic_xor_x2
;
6242 case nir_intrinsic_ssbo_atomic_exchange
:
6243 op32
= aco_opcode::buffer_atomic_swap
;
6244 op64
= aco_opcode::buffer_atomic_swap_x2
;
6246 case nir_intrinsic_ssbo_atomic_comp_swap
:
6247 op32
= aco_opcode::buffer_atomic_cmpswap
;
6248 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6251 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6253 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6254 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6255 mubuf
->operands
[0] = Operand(rsrc
);
6256 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6257 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6258 mubuf
->operands
[3] = Operand(data
);
6259 if (return_previous
)
6260 mubuf
->definitions
[0] = Definition(dst
);
6262 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6263 mubuf
->glc
= return_previous
;
6264 mubuf
->dlc
= false; /* Not needed for atomics */
6265 mubuf
->disable_wqm
= true;
6266 mubuf
->barrier
= barrier_buffer
;
6267 ctx
->program
->needs_exact
= true;
6268 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6271 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6273 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6274 Builder
bld(ctx
->program
, ctx
->block
);
6275 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6276 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6279 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6281 Builder
bld(ctx
->program
, ctx
->block
);
6282 unsigned num_components
= instr
->num_components
;
6283 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6285 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6286 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6287 num_components
, component_size
};
6288 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6289 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6290 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6291 info
.barrier
= barrier_buffer
;
6292 info
.can_reorder
= false;
6293 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6294 * it's safe to use SMEM */
6295 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6296 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6297 emit_global_load(ctx
, bld
, &info
);
6299 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6300 emit_smem_load(ctx
, bld
, &info
);
6304 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6306 Builder
bld(ctx
->program
, ctx
->block
);
6307 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6308 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6310 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6311 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6312 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6314 if (ctx
->options
->chip_class
>= GFX7
)
6315 addr
= as_vgpr(ctx
, addr
);
6317 unsigned write_count
= 0;
6318 Temp write_datas
[32];
6319 unsigned offsets
[32];
6320 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6321 16, &write_count
, write_datas
, offsets
);
6323 for (unsigned i
= 0; i
< write_count
; i
++) {
6324 if (ctx
->options
->chip_class
>= GFX7
) {
6325 unsigned offset
= offsets
[i
];
6326 Temp store_addr
= addr
;
6327 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6328 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6329 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6330 Temp carry
= bld
.tmp(bld
.lm
);
6331 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6333 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6334 Operand(offset
), addr0
);
6335 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6337 carry
).def(1).setHint(vcc
);
6339 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6344 bool global
= ctx
->options
->chip_class
>= GFX9
;
6346 switch (write_datas
[i
].bytes()) {
6348 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6351 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6354 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6357 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6360 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6363 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6366 unreachable("store_global not implemented for this size.");
6369 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6370 flat
->operands
[0] = Operand(store_addr
);
6371 flat
->operands
[1] = Operand(s1
);
6372 flat
->operands
[2] = Operand(write_datas
[i
]);
6375 flat
->offset
= offset
;
6376 flat
->disable_wqm
= true;
6377 flat
->barrier
= barrier_buffer
;
6378 ctx
->program
->needs_exact
= true;
6379 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6381 assert(ctx
->options
->chip_class
== GFX6
);
6383 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6385 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6387 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6388 mubuf
->operands
[0] = Operand(rsrc
);
6389 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6390 mubuf
->operands
[2] = Operand(0u);
6391 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6394 mubuf
->offset
= offsets
[i
];
6395 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6396 mubuf
->disable_wqm
= true;
6397 mubuf
->barrier
= barrier_buffer
;
6398 ctx
->program
->needs_exact
= true;
6399 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6404 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6406 /* return the previous value if dest is ever used */
6407 bool return_previous
= false;
6408 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6409 return_previous
= true;
6412 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6413 return_previous
= true;
6417 Builder
bld(ctx
->program
, ctx
->block
);
6418 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6419 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6421 if (ctx
->options
->chip_class
>= GFX7
)
6422 addr
= as_vgpr(ctx
, addr
);
6424 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6425 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6426 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6428 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6430 aco_opcode op32
, op64
;
6432 if (ctx
->options
->chip_class
>= GFX7
) {
6433 bool global
= ctx
->options
->chip_class
>= GFX9
;
6434 switch (instr
->intrinsic
) {
6435 case nir_intrinsic_global_atomic_add
:
6436 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6437 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6439 case nir_intrinsic_global_atomic_imin
:
6440 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6441 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6443 case nir_intrinsic_global_atomic_umin
:
6444 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6445 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6447 case nir_intrinsic_global_atomic_imax
:
6448 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6449 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6451 case nir_intrinsic_global_atomic_umax
:
6452 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6453 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6455 case nir_intrinsic_global_atomic_and
:
6456 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6457 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6459 case nir_intrinsic_global_atomic_or
:
6460 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6461 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6463 case nir_intrinsic_global_atomic_xor
:
6464 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6465 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6467 case nir_intrinsic_global_atomic_exchange
:
6468 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6469 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6471 case nir_intrinsic_global_atomic_comp_swap
:
6472 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6473 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6476 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6479 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6480 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6481 flat
->operands
[0] = Operand(addr
);
6482 flat
->operands
[1] = Operand(s1
);
6483 flat
->operands
[2] = Operand(data
);
6484 if (return_previous
)
6485 flat
->definitions
[0] = Definition(dst
);
6486 flat
->glc
= return_previous
;
6487 flat
->dlc
= false; /* Not needed for atomics */
6489 flat
->disable_wqm
= true;
6490 flat
->barrier
= barrier_buffer
;
6491 ctx
->program
->needs_exact
= true;
6492 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6494 assert(ctx
->options
->chip_class
== GFX6
);
6496 switch (instr
->intrinsic
) {
6497 case nir_intrinsic_global_atomic_add
:
6498 op32
= aco_opcode::buffer_atomic_add
;
6499 op64
= aco_opcode::buffer_atomic_add_x2
;
6501 case nir_intrinsic_global_atomic_imin
:
6502 op32
= aco_opcode::buffer_atomic_smin
;
6503 op64
= aco_opcode::buffer_atomic_smin_x2
;
6505 case nir_intrinsic_global_atomic_umin
:
6506 op32
= aco_opcode::buffer_atomic_umin
;
6507 op64
= aco_opcode::buffer_atomic_umin_x2
;
6509 case nir_intrinsic_global_atomic_imax
:
6510 op32
= aco_opcode::buffer_atomic_smax
;
6511 op64
= aco_opcode::buffer_atomic_smax_x2
;
6513 case nir_intrinsic_global_atomic_umax
:
6514 op32
= aco_opcode::buffer_atomic_umax
;
6515 op64
= aco_opcode::buffer_atomic_umax_x2
;
6517 case nir_intrinsic_global_atomic_and
:
6518 op32
= aco_opcode::buffer_atomic_and
;
6519 op64
= aco_opcode::buffer_atomic_and_x2
;
6521 case nir_intrinsic_global_atomic_or
:
6522 op32
= aco_opcode::buffer_atomic_or
;
6523 op64
= aco_opcode::buffer_atomic_or_x2
;
6525 case nir_intrinsic_global_atomic_xor
:
6526 op32
= aco_opcode::buffer_atomic_xor
;
6527 op64
= aco_opcode::buffer_atomic_xor_x2
;
6529 case nir_intrinsic_global_atomic_exchange
:
6530 op32
= aco_opcode::buffer_atomic_swap
;
6531 op64
= aco_opcode::buffer_atomic_swap_x2
;
6533 case nir_intrinsic_global_atomic_comp_swap
:
6534 op32
= aco_opcode::buffer_atomic_cmpswap
;
6535 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6538 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6541 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6543 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6545 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6546 mubuf
->operands
[0] = Operand(rsrc
);
6547 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6548 mubuf
->operands
[2] = Operand(0u);
6549 mubuf
->operands
[3] = Operand(data
);
6550 if (return_previous
)
6551 mubuf
->definitions
[0] = Definition(dst
);
6552 mubuf
->glc
= return_previous
;
6555 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6556 mubuf
->disable_wqm
= true;
6557 mubuf
->barrier
= barrier_buffer
;
6558 ctx
->program
->needs_exact
= true;
6559 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6563 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6564 Builder
bld(ctx
->program
, ctx
->block
);
6565 switch(instr
->intrinsic
) {
6566 case nir_intrinsic_group_memory_barrier
:
6567 case nir_intrinsic_memory_barrier
:
6568 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6570 case nir_intrinsic_memory_barrier_buffer
:
6571 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6573 case nir_intrinsic_memory_barrier_image
:
6574 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6576 case nir_intrinsic_memory_barrier_tcs_patch
:
6577 case nir_intrinsic_memory_barrier_shared
:
6578 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6581 unreachable("Unimplemented memory barrier intrinsic");
6586 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6588 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6589 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6590 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6591 Builder
bld(ctx
->program
, ctx
->block
);
6593 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6594 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6595 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6598 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6600 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6601 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6602 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6603 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6605 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6606 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6609 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6611 unsigned offset
= nir_intrinsic_base(instr
);
6612 Builder
bld(ctx
->program
, ctx
->block
);
6613 Operand m
= load_lds_size_m0(bld
);
6614 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6615 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6617 unsigned num_operands
= 3;
6618 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6619 switch(instr
->intrinsic
) {
6620 case nir_intrinsic_shared_atomic_add
:
6621 op32
= aco_opcode::ds_add_u32
;
6622 op64
= aco_opcode::ds_add_u64
;
6623 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6624 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6626 case nir_intrinsic_shared_atomic_imin
:
6627 op32
= aco_opcode::ds_min_i32
;
6628 op64
= aco_opcode::ds_min_i64
;
6629 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6630 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6632 case nir_intrinsic_shared_atomic_umin
:
6633 op32
= aco_opcode::ds_min_u32
;
6634 op64
= aco_opcode::ds_min_u64
;
6635 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6636 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6638 case nir_intrinsic_shared_atomic_imax
:
6639 op32
= aco_opcode::ds_max_i32
;
6640 op64
= aco_opcode::ds_max_i64
;
6641 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6642 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6644 case nir_intrinsic_shared_atomic_umax
:
6645 op32
= aco_opcode::ds_max_u32
;
6646 op64
= aco_opcode::ds_max_u64
;
6647 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6648 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6650 case nir_intrinsic_shared_atomic_and
:
6651 op32
= aco_opcode::ds_and_b32
;
6652 op64
= aco_opcode::ds_and_b64
;
6653 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6654 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6656 case nir_intrinsic_shared_atomic_or
:
6657 op32
= aco_opcode::ds_or_b32
;
6658 op64
= aco_opcode::ds_or_b64
;
6659 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6660 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6662 case nir_intrinsic_shared_atomic_xor
:
6663 op32
= aco_opcode::ds_xor_b32
;
6664 op64
= aco_opcode::ds_xor_b64
;
6665 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6666 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6668 case nir_intrinsic_shared_atomic_exchange
:
6669 op32
= aco_opcode::ds_write_b32
;
6670 op64
= aco_opcode::ds_write_b64
;
6671 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6672 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6674 case nir_intrinsic_shared_atomic_comp_swap
:
6675 op32
= aco_opcode::ds_cmpst_b32
;
6676 op64
= aco_opcode::ds_cmpst_b64
;
6677 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6678 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6682 unreachable("Unhandled shared atomic intrinsic");
6685 /* return the previous value if dest is ever used */
6686 bool return_previous
= false;
6687 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6688 return_previous
= true;
6691 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6692 return_previous
= true;
6697 if (data
.size() == 1) {
6698 assert(instr
->dest
.ssa
.bit_size
== 32);
6699 op
= return_previous
? op32_rtn
: op32
;
6701 assert(instr
->dest
.ssa
.bit_size
== 64);
6702 op
= return_previous
? op64_rtn
: op64
;
6705 if (offset
> 65535) {
6706 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6710 aco_ptr
<DS_instruction
> ds
;
6711 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6712 ds
->operands
[0] = Operand(address
);
6713 ds
->operands
[1] = Operand(data
);
6714 if (num_operands
== 4)
6715 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6716 ds
->operands
[num_operands
- 1] = m
;
6717 ds
->offset0
= offset
;
6718 if (return_previous
)
6719 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6720 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6723 Temp
get_scratch_resource(isel_context
*ctx
)
6725 Builder
bld(ctx
->program
, ctx
->block
);
6726 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6727 if (ctx
->stage
!= compute_cs
)
6728 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6730 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6731 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6733 if (ctx
->program
->chip_class
>= GFX10
) {
6734 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6735 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6736 S_008F0C_RESOURCE_LEVEL(1);
6737 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6738 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6739 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6742 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6743 if (ctx
->program
->chip_class
<= GFX8
)
6744 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6746 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6749 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6750 Builder
bld(ctx
->program
, ctx
->block
);
6751 Temp rsrc
= get_scratch_resource(ctx
);
6752 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6753 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6755 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6756 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6757 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6758 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6759 info
.swizzle_component_size
= 16;
6760 info
.can_reorder
= false;
6761 info
.soffset
= ctx
->program
->scratch_offset
;
6762 emit_mubuf_load(ctx
, bld
, &info
);
6765 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6766 Builder
bld(ctx
->program
, ctx
->block
);
6767 Temp rsrc
= get_scratch_resource(ctx
);
6768 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6769 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6771 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6772 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6774 unsigned write_count
= 0;
6775 Temp write_datas
[32];
6776 unsigned offsets
[32];
6777 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6778 16, &write_count
, write_datas
, offsets
);
6780 for (unsigned i
= 0; i
< write_count
; i
++) {
6781 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6782 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6786 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6787 uint8_t log2_ps_iter_samples
;
6788 if (ctx
->program
->info
->ps
.force_persample
) {
6789 log2_ps_iter_samples
=
6790 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6792 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6795 /* The bit pattern matches that used by fixed function fragment
6797 static const unsigned ps_iter_masks
[] = {
6798 0xffff, /* not used */
6804 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6806 Builder
bld(ctx
->program
, ctx
->block
);
6808 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6809 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6810 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6811 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6812 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6813 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6816 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6817 Builder
bld(ctx
->program
, ctx
->block
);
6819 unsigned stream
= nir_intrinsic_stream_id(instr
);
6820 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6821 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6822 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6825 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6827 unsigned num_components
=
6828 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6829 assert(num_components
);
6831 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6832 unsigned stream_offset
= 0;
6833 for (unsigned i
= 0; i
< stream
; i
++) {
6834 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6835 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6838 /* Limit on the stride field for <= GFX7. */
6839 assert(stride
< (1 << 14));
6841 Temp gsvs_dwords
[4];
6842 for (unsigned i
= 0; i
< 4; i
++)
6843 gsvs_dwords
[i
] = bld
.tmp(s1
);
6844 bld
.pseudo(aco_opcode::p_split_vector
,
6845 Definition(gsvs_dwords
[0]),
6846 Definition(gsvs_dwords
[1]),
6847 Definition(gsvs_dwords
[2]),
6848 Definition(gsvs_dwords
[3]),
6851 if (stream_offset
) {
6852 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6854 Temp carry
= bld
.tmp(s1
);
6855 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6856 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6859 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6860 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6862 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6863 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6865 unsigned offset
= 0;
6866 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6867 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6870 for (unsigned j
= 0; j
< 4; j
++) {
6871 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6874 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6875 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6876 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6877 if (const_offset
>= 4096u) {
6878 if (vaddr_offset
.isUndefined())
6879 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6881 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6882 const_offset
%= 4096u;
6885 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6886 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6887 mtbuf
->operands
[1] = vaddr_offset
;
6888 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6889 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6890 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6891 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6892 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6893 mtbuf
->offset
= const_offset
;
6896 mtbuf
->barrier
= barrier_gs_data
;
6897 mtbuf
->can_reorder
= true;
6898 bld
.insert(std::move(mtbuf
));
6901 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6904 /* outputs for the next vertex are undefined and keeping them around can
6905 * create invalid IR with control flow */
6906 ctx
->outputs
.mask
[i
] = 0;
6909 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6912 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6914 Builder
bld(ctx
->program
, ctx
->block
);
6916 if (cluster_size
== 1) {
6918 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6919 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6920 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6921 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6922 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6923 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6924 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6925 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6926 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6927 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6928 //subgroupAnd(val) -> (exec & ~val) == 0
6929 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6930 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6931 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6932 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6933 //subgroupOr(val) -> (val & exec) != 0
6934 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6935 return bool_to_vector_condition(ctx
, tmp
);
6936 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6937 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6938 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6939 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6940 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6941 return bool_to_vector_condition(ctx
, tmp
);
6943 //subgroupClustered{And,Or,Xor}(val, n) ->
6944 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6945 //cluster_offset = ~(n - 1) & lane_id
6946 //cluster_mask = ((1 << n) - 1)
6947 //subgroupClusteredAnd():
6948 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6949 //subgroupClusteredOr():
6950 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6951 //subgroupClusteredXor():
6952 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6953 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6954 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6957 if (op
== nir_op_iand
)
6958 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6960 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6962 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6964 if (ctx
->program
->chip_class
<= GFX7
)
6965 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6966 else if (ctx
->program
->wave_size
== 64)
6967 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6969 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6970 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6971 if (cluster_mask
!= 0xffffffff)
6972 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6974 Definition cmp_def
= Definition();
6975 if (op
== nir_op_iand
) {
6976 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6977 } else if (op
== nir_op_ior
) {
6978 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6979 } else if (op
== nir_op_ixor
) {
6980 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6981 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6982 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6984 cmp_def
.setHint(vcc
);
6985 return cmp_def
.getTemp();
6989 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6991 Builder
bld(ctx
->program
, ctx
->block
);
6993 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6994 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6995 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6997 if (op
== nir_op_iand
)
6998 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7000 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7002 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7003 Temp lo
= lohi
.def(0).getTemp();
7004 Temp hi
= lohi
.def(1).getTemp();
7005 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7007 Definition cmp_def
= Definition();
7008 if (op
== nir_op_iand
)
7009 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7010 else if (op
== nir_op_ior
)
7011 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7012 else if (op
== nir_op_ixor
)
7013 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7014 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7015 cmp_def
.setHint(vcc
);
7016 return cmp_def
.getTemp();
7019 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7021 Builder
bld(ctx
->program
, ctx
->block
);
7023 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7024 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7025 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7026 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7027 if (op
== nir_op_iand
)
7028 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7029 else if (op
== nir_op_ior
)
7030 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7031 else if (op
== nir_op_ixor
)
7032 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7038 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7040 Builder
bld(ctx
->program
, ctx
->block
);
7041 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7042 if (src
.regClass().type() == RegType::vgpr
) {
7043 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7044 } else if (src
.regClass() == s1
) {
7045 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7046 } else if (src
.regClass() == s2
) {
7047 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7049 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7050 nir_print_instr(&instr
->instr
, stderr
);
7051 fprintf(stderr
, "\n");
7055 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7057 Builder
bld(ctx
->program
, ctx
->block
);
7058 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7059 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7060 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7062 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7063 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7064 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7065 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7068 if (ctx
->program
->chip_class
>= GFX8
) {
7069 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7070 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7071 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7072 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7073 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7074 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7076 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7077 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7078 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7079 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7080 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7081 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7082 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7083 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7084 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7085 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7088 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7089 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7090 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7091 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7092 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7093 Temp wqm1
= bld
.tmp(v1
);
7094 emit_wqm(ctx
, tmp1
, wqm1
, true);
7095 Temp wqm2
= bld
.tmp(v1
);
7096 emit_wqm(ctx
, tmp2
, wqm2
, true);
7097 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7101 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7103 Builder
bld(ctx
->program
, ctx
->block
);
7104 switch(instr
->intrinsic
) {
7105 case nir_intrinsic_load_barycentric_sample
:
7106 case nir_intrinsic_load_barycentric_pixel
:
7107 case nir_intrinsic_load_barycentric_centroid
: {
7108 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7109 Temp bary
= Temp(0, s2
);
7111 case INTERP_MODE_SMOOTH
:
7112 case INTERP_MODE_NONE
:
7113 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7114 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7115 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7116 bary
= ctx
->persp_centroid
;
7117 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7118 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7120 case INTERP_MODE_NOPERSPECTIVE
:
7121 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7122 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7123 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7124 bary
= ctx
->linear_centroid
;
7125 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7126 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7131 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7132 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7133 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7134 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7135 Operand(p1
), Operand(p2
));
7136 emit_split_vector(ctx
, dst
, 2);
7139 case nir_intrinsic_load_barycentric_model
: {
7140 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7142 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7143 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7144 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7145 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7146 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7147 Operand(p1
), Operand(p2
), Operand(p3
));
7148 emit_split_vector(ctx
, dst
, 3);
7151 case nir_intrinsic_load_barycentric_at_sample
: {
7152 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7153 switch (ctx
->options
->key
.fs
.num_samples
) {
7154 case 2: sample_pos_offset
+= 1 << 3; break;
7155 case 4: sample_pos_offset
+= 3 << 3; break;
7156 case 8: sample_pos_offset
+= 7 << 3; break;
7160 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7161 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7162 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7163 if (addr
.type() == RegType::sgpr
) {
7166 sample_pos_offset
+= const_addr
->u32
<< 3;
7167 offset
= Operand(sample_pos_offset
);
7168 } else if (ctx
->options
->chip_class
>= GFX9
) {
7169 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7171 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7172 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7175 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7176 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7178 } else if (ctx
->options
->chip_class
>= GFX9
) {
7179 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7180 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7181 } else if (ctx
->options
->chip_class
>= GFX7
) {
7182 /* addr += private_segment_buffer + sample_pos_offset */
7183 Temp tmp0
= bld
.tmp(s1
);
7184 Temp tmp1
= bld
.tmp(s1
);
7185 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7186 Definition scc_tmp
= bld
.def(s1
, scc
);
7187 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7188 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7189 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7190 Temp pck0
= bld
.tmp(v1
);
7191 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7192 tmp1
= as_vgpr(ctx
, tmp1
);
7193 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7194 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7196 /* sample_pos = flat_load_dwordx2 addr */
7197 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7199 assert(ctx
->options
->chip_class
== GFX6
);
7201 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7202 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7203 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7205 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7206 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7208 sample_pos
= bld
.tmp(v2
);
7210 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7211 load
->definitions
[0] = Definition(sample_pos
);
7212 load
->operands
[0] = Operand(rsrc
);
7213 load
->operands
[1] = Operand(addr
);
7214 load
->operands
[2] = Operand(0u);
7215 load
->offset
= sample_pos_offset
;
7217 load
->addr64
= true;
7220 load
->disable_wqm
= false;
7221 load
->barrier
= barrier_none
;
7222 load
->can_reorder
= true;
7223 ctx
->block
->instructions
.emplace_back(std::move(load
));
7226 /* sample_pos -= 0.5 */
7227 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7228 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7229 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7230 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7231 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7233 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7236 case nir_intrinsic_load_barycentric_at_offset
: {
7237 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7238 RegClass rc
= RegClass(offset
.type(), 1);
7239 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7240 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7241 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7244 case nir_intrinsic_load_front_face
: {
7245 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7246 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7249 case nir_intrinsic_load_view_index
: {
7250 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7251 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7252 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7258 case nir_intrinsic_load_layer_id
: {
7259 unsigned idx
= nir_intrinsic_base(instr
);
7260 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7261 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7264 case nir_intrinsic_load_frag_coord
: {
7265 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7268 case nir_intrinsic_load_sample_pos
: {
7269 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7270 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7271 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7272 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7273 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7276 case nir_intrinsic_load_tess_coord
:
7277 visit_load_tess_coord(ctx
, instr
);
7279 case nir_intrinsic_load_interpolated_input
:
7280 visit_load_interpolated_input(ctx
, instr
);
7282 case nir_intrinsic_store_output
:
7283 visit_store_output(ctx
, instr
);
7285 case nir_intrinsic_load_input
:
7286 case nir_intrinsic_load_input_vertex
:
7287 visit_load_input(ctx
, instr
);
7289 case nir_intrinsic_load_output
:
7290 visit_load_output(ctx
, instr
);
7292 case nir_intrinsic_load_per_vertex_input
:
7293 visit_load_per_vertex_input(ctx
, instr
);
7295 case nir_intrinsic_load_per_vertex_output
:
7296 visit_load_per_vertex_output(ctx
, instr
);
7298 case nir_intrinsic_store_per_vertex_output
:
7299 visit_store_per_vertex_output(ctx
, instr
);
7301 case nir_intrinsic_load_ubo
:
7302 visit_load_ubo(ctx
, instr
);
7304 case nir_intrinsic_load_push_constant
:
7305 visit_load_push_constant(ctx
, instr
);
7307 case nir_intrinsic_load_constant
:
7308 visit_load_constant(ctx
, instr
);
7310 case nir_intrinsic_vulkan_resource_index
:
7311 visit_load_resource(ctx
, instr
);
7313 case nir_intrinsic_discard
:
7314 visit_discard(ctx
, instr
);
7316 case nir_intrinsic_discard_if
:
7317 visit_discard_if(ctx
, instr
);
7319 case nir_intrinsic_load_shared
:
7320 visit_load_shared(ctx
, instr
);
7322 case nir_intrinsic_store_shared
:
7323 visit_store_shared(ctx
, instr
);
7325 case nir_intrinsic_shared_atomic_add
:
7326 case nir_intrinsic_shared_atomic_imin
:
7327 case nir_intrinsic_shared_atomic_umin
:
7328 case nir_intrinsic_shared_atomic_imax
:
7329 case nir_intrinsic_shared_atomic_umax
:
7330 case nir_intrinsic_shared_atomic_and
:
7331 case nir_intrinsic_shared_atomic_or
:
7332 case nir_intrinsic_shared_atomic_xor
:
7333 case nir_intrinsic_shared_atomic_exchange
:
7334 case nir_intrinsic_shared_atomic_comp_swap
:
7335 visit_shared_atomic(ctx
, instr
);
7337 case nir_intrinsic_image_deref_load
:
7338 visit_image_load(ctx
, instr
);
7340 case nir_intrinsic_image_deref_store
:
7341 visit_image_store(ctx
, instr
);
7343 case nir_intrinsic_image_deref_atomic_add
:
7344 case nir_intrinsic_image_deref_atomic_umin
:
7345 case nir_intrinsic_image_deref_atomic_imin
:
7346 case nir_intrinsic_image_deref_atomic_umax
:
7347 case nir_intrinsic_image_deref_atomic_imax
:
7348 case nir_intrinsic_image_deref_atomic_and
:
7349 case nir_intrinsic_image_deref_atomic_or
:
7350 case nir_intrinsic_image_deref_atomic_xor
:
7351 case nir_intrinsic_image_deref_atomic_exchange
:
7352 case nir_intrinsic_image_deref_atomic_comp_swap
:
7353 visit_image_atomic(ctx
, instr
);
7355 case nir_intrinsic_image_deref_size
:
7356 visit_image_size(ctx
, instr
);
7358 case nir_intrinsic_load_ssbo
:
7359 visit_load_ssbo(ctx
, instr
);
7361 case nir_intrinsic_store_ssbo
:
7362 visit_store_ssbo(ctx
, instr
);
7364 case nir_intrinsic_load_global
:
7365 visit_load_global(ctx
, instr
);
7367 case nir_intrinsic_store_global
:
7368 visit_store_global(ctx
, instr
);
7370 case nir_intrinsic_global_atomic_add
:
7371 case nir_intrinsic_global_atomic_imin
:
7372 case nir_intrinsic_global_atomic_umin
:
7373 case nir_intrinsic_global_atomic_imax
:
7374 case nir_intrinsic_global_atomic_umax
:
7375 case nir_intrinsic_global_atomic_and
:
7376 case nir_intrinsic_global_atomic_or
:
7377 case nir_intrinsic_global_atomic_xor
:
7378 case nir_intrinsic_global_atomic_exchange
:
7379 case nir_intrinsic_global_atomic_comp_swap
:
7380 visit_global_atomic(ctx
, instr
);
7382 case nir_intrinsic_ssbo_atomic_add
:
7383 case nir_intrinsic_ssbo_atomic_imin
:
7384 case nir_intrinsic_ssbo_atomic_umin
:
7385 case nir_intrinsic_ssbo_atomic_imax
:
7386 case nir_intrinsic_ssbo_atomic_umax
:
7387 case nir_intrinsic_ssbo_atomic_and
:
7388 case nir_intrinsic_ssbo_atomic_or
:
7389 case nir_intrinsic_ssbo_atomic_xor
:
7390 case nir_intrinsic_ssbo_atomic_exchange
:
7391 case nir_intrinsic_ssbo_atomic_comp_swap
:
7392 visit_atomic_ssbo(ctx
, instr
);
7394 case nir_intrinsic_load_scratch
:
7395 visit_load_scratch(ctx
, instr
);
7397 case nir_intrinsic_store_scratch
:
7398 visit_store_scratch(ctx
, instr
);
7400 case nir_intrinsic_get_buffer_size
:
7401 visit_get_buffer_size(ctx
, instr
);
7403 case nir_intrinsic_control_barrier
: {
7404 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7405 /* GFX6 only (thanks to a hw bug workaround):
7406 * The real barrier instruction isn’t needed, because an entire patch
7407 * always fits into a single wave.
7412 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7413 bld
.sopp(aco_opcode::s_barrier
);
7417 case nir_intrinsic_memory_barrier_tcs_patch
:
7418 case nir_intrinsic_group_memory_barrier
:
7419 case nir_intrinsic_memory_barrier
:
7420 case nir_intrinsic_memory_barrier_buffer
:
7421 case nir_intrinsic_memory_barrier_image
:
7422 case nir_intrinsic_memory_barrier_shared
:
7423 emit_memory_barrier(ctx
, instr
);
7425 case nir_intrinsic_load_num_work_groups
: {
7426 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7427 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7428 emit_split_vector(ctx
, dst
, 3);
7431 case nir_intrinsic_load_local_invocation_id
: {
7432 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7433 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7434 emit_split_vector(ctx
, dst
, 3);
7437 case nir_intrinsic_load_work_group_id
: {
7438 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7439 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7441 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7442 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7443 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7444 emit_split_vector(ctx
, dst
, 3);
7447 case nir_intrinsic_load_local_invocation_index
: {
7448 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7450 /* The tg_size bits [6:11] contain the subgroup id,
7451 * we need this multiplied by the wave size, and then OR the thread id to it.
7453 if (ctx
->program
->wave_size
== 64) {
7454 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7455 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7456 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7457 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7459 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7460 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7461 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7462 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7466 case nir_intrinsic_load_subgroup_id
: {
7467 if (ctx
->stage
== compute_cs
) {
7468 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7469 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7471 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7475 case nir_intrinsic_load_subgroup_invocation
: {
7476 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7479 case nir_intrinsic_load_num_subgroups
: {
7480 if (ctx
->stage
== compute_cs
)
7481 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7482 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7484 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7487 case nir_intrinsic_ballot
: {
7488 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7489 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7490 Definition tmp
= bld
.def(dst
.regClass());
7491 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7492 if (instr
->src
[0].ssa
->bit_size
== 1) {
7493 assert(src
.regClass() == bld
.lm
);
7494 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7495 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7496 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7497 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7498 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7500 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7501 nir_print_instr(&instr
->instr
, stderr
);
7502 fprintf(stderr
, "\n");
7504 if (dst
.size() != bld
.lm
.size()) {
7505 /* Wave32 with ballot size set to 64 */
7506 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7508 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7511 case nir_intrinsic_shuffle
:
7512 case nir_intrinsic_read_invocation
: {
7513 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7514 if (!nir_src_is_divergent(instr
->src
[0])) {
7515 emit_uniform_subgroup(ctx
, instr
, src
);
7517 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7518 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7519 tid
= bld
.as_uniform(tid
);
7520 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7521 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7522 Temp tmp
= bld
.tmp(v1
);
7523 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7524 if (dst
.type() == RegType::vgpr
)
7525 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7527 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7528 } else if (src
.regClass() == v1
) {
7529 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7530 } else if (src
.regClass() == v2
) {
7531 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7532 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7533 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7534 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7535 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7536 emit_split_vector(ctx
, dst
, 2);
7537 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7538 assert(src
.regClass() == bld
.lm
);
7539 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7540 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7541 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7542 assert(src
.regClass() == bld
.lm
);
7544 if (ctx
->program
->chip_class
<= GFX7
)
7545 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7546 else if (ctx
->program
->wave_size
== 64)
7547 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7549 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7550 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7551 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7552 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7554 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7555 nir_print_instr(&instr
->instr
, stderr
);
7556 fprintf(stderr
, "\n");
7561 case nir_intrinsic_load_sample_id
: {
7562 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7563 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7566 case nir_intrinsic_load_sample_mask_in
: {
7567 visit_load_sample_mask_in(ctx
, instr
);
7570 case nir_intrinsic_read_first_invocation
: {
7571 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7572 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7573 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7575 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7577 } else if (src
.regClass() == v2
) {
7578 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7579 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7580 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7581 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7582 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7583 emit_split_vector(ctx
, dst
, 2);
7584 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7585 assert(src
.regClass() == bld
.lm
);
7586 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7587 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7588 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7589 } else if (src
.regClass() == s1
) {
7590 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7591 } else if (src
.regClass() == s2
) {
7592 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7594 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7595 nir_print_instr(&instr
->instr
, stderr
);
7596 fprintf(stderr
, "\n");
7600 case nir_intrinsic_vote_all
: {
7601 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7602 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7603 assert(src
.regClass() == bld
.lm
);
7604 assert(dst
.regClass() == bld
.lm
);
7606 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7607 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7608 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7611 case nir_intrinsic_vote_any
: {
7612 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7613 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7614 assert(src
.regClass() == bld
.lm
);
7615 assert(dst
.regClass() == bld
.lm
);
7617 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7618 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7621 case nir_intrinsic_reduce
:
7622 case nir_intrinsic_inclusive_scan
:
7623 case nir_intrinsic_exclusive_scan
: {
7624 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7625 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7626 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7627 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7628 nir_intrinsic_cluster_size(instr
) : 0;
7629 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7631 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7632 emit_uniform_subgroup(ctx
, instr
, src
);
7633 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7634 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7636 else if (op
== nir_op_iadd
)
7638 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7640 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7642 switch (instr
->intrinsic
) {
7643 case nir_intrinsic_reduce
:
7644 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7646 case nir_intrinsic_exclusive_scan
:
7647 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7649 case nir_intrinsic_inclusive_scan
:
7650 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7655 } else if (cluster_size
== 1) {
7656 bld
.copy(Definition(dst
), src
);
7658 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7660 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7664 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7665 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7680 unreachable("unknown reduction op");
7686 switch (instr
->intrinsic
) {
7687 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7688 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7689 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7691 unreachable("unknown reduce intrinsic");
7694 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7695 reduce
->operands
[0] = Operand(src
);
7696 // filled in by aco_reduce_assign.cpp, used internally as part of the
7698 assert(dst
.size() == 1 || dst
.size() == 2);
7699 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7700 reduce
->operands
[2] = Operand(v1
.as_linear());
7702 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7703 reduce
->definitions
[0] = Definition(tmp_dst
);
7704 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7705 reduce
->definitions
[2] = Definition();
7706 reduce
->definitions
[3] = Definition(scc
, s1
);
7707 reduce
->definitions
[4] = Definition();
7708 reduce
->reduce_op
= reduce_op
;
7709 reduce
->cluster_size
= cluster_size
;
7710 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7712 emit_wqm(ctx
, tmp_dst
, dst
);
7716 case nir_intrinsic_quad_broadcast
: {
7717 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7718 if (!nir_dest_is_divergent(instr
->dest
)) {
7719 emit_uniform_subgroup(ctx
, instr
, src
);
7721 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7722 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7723 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7725 if (instr
->dest
.ssa
.bit_size
== 1) {
7726 assert(src
.regClass() == bld
.lm
);
7727 assert(dst
.regClass() == bld
.lm
);
7728 uint32_t half_mask
= 0x11111111u
<< lane
;
7729 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7730 Temp tmp
= bld
.tmp(bld
.lm
);
7731 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7732 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7733 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7734 emit_wqm(ctx
, tmp
, dst
);
7735 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7736 Temp tmp
= bld
.tmp(v1
);
7737 if (ctx
->program
->chip_class
>= GFX8
)
7738 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7740 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7741 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7742 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7743 Temp tmp
= bld
.tmp(v1
);
7744 if (ctx
->program
->chip_class
>= GFX8
)
7745 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7747 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7749 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7750 if (ctx
->program
->chip_class
>= GFX8
)
7751 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7753 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7754 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7755 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7756 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7757 if (ctx
->program
->chip_class
>= GFX8
) {
7758 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7759 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7761 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7762 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7764 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7765 emit_split_vector(ctx
, dst
, 2);
7767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7768 nir_print_instr(&instr
->instr
, stderr
);
7769 fprintf(stderr
, "\n");
7774 case nir_intrinsic_quad_swap_horizontal
:
7775 case nir_intrinsic_quad_swap_vertical
:
7776 case nir_intrinsic_quad_swap_diagonal
:
7777 case nir_intrinsic_quad_swizzle_amd
: {
7778 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7779 if (!nir_dest_is_divergent(instr
->dest
)) {
7780 emit_uniform_subgroup(ctx
, instr
, src
);
7783 uint16_t dpp_ctrl
= 0;
7784 switch (instr
->intrinsic
) {
7785 case nir_intrinsic_quad_swap_horizontal
:
7786 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7788 case nir_intrinsic_quad_swap_vertical
:
7789 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7791 case nir_intrinsic_quad_swap_diagonal
:
7792 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7794 case nir_intrinsic_quad_swizzle_amd
:
7795 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7800 if (ctx
->program
->chip_class
< GFX8
)
7801 dpp_ctrl
|= (1 << 15);
7803 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7804 if (instr
->dest
.ssa
.bit_size
== 1) {
7805 assert(src
.regClass() == bld
.lm
);
7806 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7807 if (ctx
->program
->chip_class
>= GFX8
)
7808 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7810 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7811 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7812 emit_wqm(ctx
, tmp
, dst
);
7813 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7814 Temp tmp
= bld
.tmp(v1
);
7815 if (ctx
->program
->chip_class
>= GFX8
)
7816 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7818 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7819 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7820 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7821 Temp tmp
= bld
.tmp(v1
);
7822 if (ctx
->program
->chip_class
>= GFX8
)
7823 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7825 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7826 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7827 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7829 if (ctx
->program
->chip_class
>= GFX8
)
7830 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7832 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7833 emit_wqm(ctx
, tmp
, dst
);
7834 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7835 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7836 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7837 if (ctx
->program
->chip_class
>= GFX8
) {
7838 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7839 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7841 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7842 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7844 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7845 emit_split_vector(ctx
, dst
, 2);
7847 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7848 nir_print_instr(&instr
->instr
, stderr
);
7849 fprintf(stderr
, "\n");
7853 case nir_intrinsic_masked_swizzle_amd
: {
7854 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7855 if (!nir_dest_is_divergent(instr
->dest
)) {
7856 emit_uniform_subgroup(ctx
, instr
, src
);
7859 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7860 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7861 if (dst
.regClass() == v1
) {
7863 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7865 } else if (dst
.regClass() == v2
) {
7866 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7867 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7868 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7869 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7870 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7871 emit_split_vector(ctx
, dst
, 2);
7873 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7874 nir_print_instr(&instr
->instr
, stderr
);
7875 fprintf(stderr
, "\n");
7879 case nir_intrinsic_write_invocation_amd
: {
7880 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7881 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7882 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7883 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7884 if (dst
.regClass() == v1
) {
7885 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7886 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7887 } else if (dst
.regClass() == v2
) {
7888 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7889 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7892 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7893 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7894 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7895 emit_split_vector(ctx
, dst
, 2);
7897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7898 nir_print_instr(&instr
->instr
, stderr
);
7899 fprintf(stderr
, "\n");
7903 case nir_intrinsic_mbcnt_amd
: {
7904 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7905 RegClass rc
= RegClass(src
.type(), 1);
7906 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7907 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7908 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7909 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7910 emit_wqm(ctx
, wqm_tmp
, dst
);
7913 case nir_intrinsic_load_helper_invocation
: {
7914 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7915 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7916 ctx
->block
->kind
|= block_kind_needs_lowering
;
7917 ctx
->program
->needs_exact
= true;
7920 case nir_intrinsic_is_helper_invocation
: {
7921 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7922 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7923 ctx
->block
->kind
|= block_kind_needs_lowering
;
7924 ctx
->program
->needs_exact
= true;
7927 case nir_intrinsic_demote
:
7928 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7930 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7931 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7932 ctx
->block
->kind
|= block_kind_uses_demote
;
7933 ctx
->program
->needs_exact
= true;
7935 case nir_intrinsic_demote_if
: {
7936 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7937 assert(src
.regClass() == bld
.lm
);
7938 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7939 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7941 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7942 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7943 ctx
->block
->kind
|= block_kind_uses_demote
;
7944 ctx
->program
->needs_exact
= true;
7947 case nir_intrinsic_first_invocation
: {
7948 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7949 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7952 case nir_intrinsic_shader_clock
: {
7954 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7955 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7956 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7957 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7960 case nir_intrinsic_load_vertex_id_zero_base
: {
7961 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7962 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7965 case nir_intrinsic_load_first_vertex
: {
7966 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7967 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7970 case nir_intrinsic_load_base_instance
: {
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7975 case nir_intrinsic_load_instance_id
: {
7976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7977 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7980 case nir_intrinsic_load_draw_id
: {
7981 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7982 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7985 case nir_intrinsic_load_invocation_id
: {
7986 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7988 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7989 if (ctx
->options
->chip_class
>= GFX10
)
7990 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7992 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7993 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7994 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7995 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7997 unreachable("Unsupported stage for load_invocation_id");
8002 case nir_intrinsic_load_primitive_id
: {
8003 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8005 switch (ctx
->shader
->info
.stage
) {
8006 case MESA_SHADER_GEOMETRY
:
8007 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8009 case MESA_SHADER_TESS_CTRL
:
8010 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8012 case MESA_SHADER_TESS_EVAL
:
8013 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8016 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8021 case nir_intrinsic_load_patch_vertices_in
: {
8022 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8023 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8025 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8026 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8029 case nir_intrinsic_emit_vertex_with_counter
: {
8030 visit_emit_vertex_with_counter(ctx
, instr
);
8033 case nir_intrinsic_end_primitive_with_counter
: {
8034 unsigned stream
= nir_intrinsic_stream_id(instr
);
8035 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8038 case nir_intrinsic_set_vertex_count
: {
8039 /* unused, the HW keeps track of this for us */
8043 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8044 nir_print_instr(&instr
->instr
, stderr
);
8045 fprintf(stderr
, "\n");
8053 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8054 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8055 enum glsl_base_type
*stype
)
8057 nir_deref_instr
*texture_deref_instr
= NULL
;
8058 nir_deref_instr
*sampler_deref_instr
= NULL
;
8061 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8062 switch (instr
->src
[i
].src_type
) {
8063 case nir_tex_src_texture_deref
:
8064 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8066 case nir_tex_src_sampler_deref
:
8067 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8069 case nir_tex_src_plane
:
8070 plane
= nir_src_as_int(instr
->src
[i
].src
);
8077 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8079 if (!sampler_deref_instr
)
8080 sampler_deref_instr
= texture_deref_instr
;
8083 assert(instr
->op
!= nir_texop_txf_ms
&&
8084 instr
->op
!= nir_texop_samples_identical
);
8085 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8086 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8087 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8088 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8089 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8090 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8092 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8095 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8097 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8098 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8099 Builder
bld(ctx
->program
, ctx
->block
);
8101 /* to avoid unnecessary moves, we split and recombine sampler and image */
8102 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8103 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8104 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8105 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8106 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8107 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8108 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8109 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8111 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8112 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8113 img
[0], img
[1], img
[2], img
[3],
8114 img
[4], img
[5], img
[6], img
[7]);
8115 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8116 samp
[0], samp
[1], samp
[2], samp
[3]);
8119 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8120 instr
->op
== nir_texop_samples_identical
))
8121 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8124 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8125 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8127 Builder
bld(ctx
->program
, ctx
->block
);
8129 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8130 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8131 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8133 Operand
neg_one(0xbf800000u
);
8134 Operand
one(0x3f800000u
);
8135 Operand
two(0x40000000u
);
8136 Operand
four(0x40800000u
);
8138 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8139 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8140 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8142 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8143 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8144 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8145 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8148 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8149 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8150 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8152 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8155 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8156 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8157 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8160 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8161 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8163 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8164 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8167 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8169 Builder
bld(ctx
->program
, ctx
->block
);
8170 Temp ma
, tc
, sc
, id
;
8173 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8175 // see comment in ac_prepare_cube_coords()
8176 if (ctx
->options
->chip_class
<= GFX8
)
8177 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8180 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8182 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8183 vop3a
->operands
[0] = Operand(ma
);
8184 vop3a
->abs
[0] = true;
8185 Temp invma
= bld
.tmp(v1
);
8186 vop3a
->definitions
[0] = Definition(invma
);
8187 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8189 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8191 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8193 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8195 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8197 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8200 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8201 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8203 for (unsigned i
= 0; i
< 2; i
++) {
8204 // see comment in ac_prepare_cube_coords()
8206 Temp deriv_sc
, deriv_tc
;
8207 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8208 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8210 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8212 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8213 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8214 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8215 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8216 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8217 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8218 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8221 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8222 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8226 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8233 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8235 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8237 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8238 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8241 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8242 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8243 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8247 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8249 Builder
bld(ctx
->program
, ctx
->block
);
8250 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8251 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8252 has_clamped_lod
= false;
8253 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8254 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8255 clamped_lod
= Temp();
8256 std::vector
<Temp
> coords
;
8257 std::vector
<Temp
> derivs
;
8258 nir_const_value
*sample_index_cv
= NULL
;
8259 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8260 enum glsl_base_type stype
;
8261 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8263 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8264 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8265 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8266 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8268 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8269 switch (instr
->src
[i
].src_type
) {
8270 case nir_tex_src_coord
: {
8271 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8272 for (unsigned i
= 0; i
< coord
.size(); i
++)
8273 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8276 case nir_tex_src_bias
:
8277 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8280 case nir_tex_src_lod
: {
8281 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8283 if (val
&& val
->f32
<= 0.0) {
8286 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8291 case nir_tex_src_min_lod
:
8292 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8293 has_clamped_lod
= true;
8295 case nir_tex_src_comparator
:
8296 if (instr
->is_shadow
) {
8297 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8301 case nir_tex_src_offset
:
8302 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8303 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8306 case nir_tex_src_ddx
:
8307 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8310 case nir_tex_src_ddy
:
8311 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8314 case nir_tex_src_ms_index
:
8315 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8316 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8317 has_sample_index
= true;
8319 case nir_tex_src_texture_offset
:
8320 case nir_tex_src_sampler_offset
:
8326 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8327 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8329 if (instr
->op
== nir_texop_texture_samples
) {
8330 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8332 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8333 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8334 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8336 Operand default_sample
= Operand(1u);
8337 if (ctx
->options
->robust_buffer_access
) {
8338 /* Extract the second dword of the descriptor, if it's
8339 * all zero, then it's a null descriptor.
8341 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8342 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8343 default_sample
= Operand(is_non_null_descriptor
);
8346 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8347 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8348 samples
, default_sample
, bld
.scc(is_msaa
));
8352 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8353 aco_ptr
<Instruction
> tmp_instr
;
8354 Temp acc
, pack
= Temp();
8356 uint32_t pack_const
= 0;
8357 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8358 if (!const_offset
[i
])
8360 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8363 if (offset
.type() == RegType::sgpr
) {
8364 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8365 if (const_offset
[i
])
8368 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8369 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8372 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8375 if (pack
== Temp()) {
8378 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8382 if (pack_const
&& pack
!= Temp())
8383 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8385 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8386 if (const_offset
[i
])
8389 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8390 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8393 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8396 if (pack
== Temp()) {
8399 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8403 if (pack_const
&& pack
!= Temp())
8404 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8406 if (pack_const
&& pack
== Temp())
8407 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8408 else if (pack
== Temp())
8414 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8415 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8417 /* pack derivatives */
8418 if (has_ddx
|| has_ddy
) {
8419 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8420 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8421 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8422 derivs
= {ddx
, zero
, ddy
, zero
};
8424 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8425 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8426 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8427 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8432 if (instr
->coord_components
> 1 &&
8433 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8435 instr
->op
!= nir_texop_txf
)
8436 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8438 if (instr
->coord_components
> 2 &&
8439 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8440 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8441 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8442 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8444 instr
->op
!= nir_texop_txf
&&
8445 instr
->op
!= nir_texop_txf_ms
&&
8446 instr
->op
!= nir_texop_fragment_fetch
&&
8447 instr
->op
!= nir_texop_fragment_mask_fetch
)
8448 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8450 if (ctx
->options
->chip_class
== GFX9
&&
8451 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8452 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8453 assert(coords
.size() > 0 && coords
.size() < 3);
8455 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8456 Operand((uint32_t) 0) :
8457 Operand((uint32_t) 0x3f000000)));
8460 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8462 if (instr
->op
== nir_texop_samples_identical
)
8463 resource
= fmask_ptr
;
8465 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8466 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8467 instr
->op
!= nir_texop_txs
&&
8468 instr
->op
!= nir_texop_fragment_fetch
&&
8469 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8470 assert(has_sample_index
);
8471 Operand
op(sample_index
);
8472 if (sample_index_cv
)
8473 op
= Operand(sample_index_cv
->u32
);
8474 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8477 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8478 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8479 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8480 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8485 /* Build tex instruction */
8486 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8487 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8488 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8490 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8493 /* gather4 selects the component by dmask and always returns vec4 */
8494 if (instr
->op
== nir_texop_tg4
) {
8495 assert(instr
->dest
.ssa
.num_components
== 4);
8496 if (instr
->is_shadow
)
8499 dmask
= 1 << instr
->component
;
8500 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8501 tmp_dst
= bld
.tmp(v4
);
8502 } else if (instr
->op
== nir_texop_samples_identical
) {
8503 tmp_dst
= bld
.tmp(v1
);
8504 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8505 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8508 aco_ptr
<MIMG_instruction
> tex
;
8509 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8511 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8513 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8514 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8517 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8518 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8520 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8521 tex
->operands
[0] = Operand(resource
);
8522 tex
->operands
[1] = Operand(s4
); /* no sampler */
8523 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8524 if (ctx
->options
->chip_class
== GFX9
&&
8525 instr
->op
== nir_texop_txs
&&
8526 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8528 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8529 } else if (instr
->op
== nir_texop_query_levels
) {
8530 tex
->dmask
= 1 << 3;
8535 tex
->definitions
[0] = Definition(tmp_dst
);
8537 tex
->can_reorder
= true;
8538 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8541 /* divide 3rd value by 6 by multiplying with magic number */
8542 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8543 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8544 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8545 assert(instr
->dest
.ssa
.num_components
== 3);
8546 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8547 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8548 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8549 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8554 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8558 Temp tg4_compare_cube_wa64
= Temp();
8560 if (tg4_integer_workarounds
) {
8561 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8562 tex
->operands
[0] = Operand(resource
);
8563 tex
->operands
[1] = Operand(s4
); /* no sampler */
8564 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8568 Temp size
= bld
.tmp(v2
);
8569 tex
->definitions
[0] = Definition(size
);
8570 tex
->can_reorder
= true;
8571 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8572 emit_split_vector(ctx
, size
, size
.size());
8575 for (unsigned i
= 0; i
< 2; i
++) {
8576 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8577 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8578 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8579 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8582 Temp new_coords
[2] = {
8583 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8584 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8587 if (tg4_integer_cube_workaround
) {
8588 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8589 Temp desc
[resource
.size()];
8590 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8591 Format::PSEUDO
, 1, resource
.size())};
8592 split
->operands
[0] = Operand(resource
);
8593 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8594 desc
[i
] = bld
.tmp(s1
);
8595 split
->definitions
[i
] = Definition(desc
[i
]);
8597 ctx
->block
->instructions
.emplace_back(std::move(split
));
8599 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8600 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8601 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8604 if (stype
== GLSL_TYPE_UINT
) {
8605 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8606 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8607 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8608 bld
.scc(compare_cube_wa
));
8610 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8611 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8612 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8613 bld
.scc(compare_cube_wa
));
8615 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8616 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8618 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8620 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8621 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8622 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8624 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8625 Format::PSEUDO
, resource
.size(), 1)};
8626 for (unsigned i
= 0; i
< resource
.size(); i
++)
8627 vec
->operands
[i
] = Operand(desc
[i
]);
8628 resource
= bld
.tmp(resource
.regClass());
8629 vec
->definitions
[0] = Definition(resource
);
8630 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8632 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8633 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8634 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8635 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8637 coords
[0] = new_coords
[0];
8638 coords
[1] = new_coords
[1];
8641 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8642 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8644 assert(coords
.size() == 1);
8645 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8649 op
= aco_opcode::buffer_load_format_x
; break;
8651 op
= aco_opcode::buffer_load_format_xy
; break;
8653 op
= aco_opcode::buffer_load_format_xyz
; break;
8655 op
= aco_opcode::buffer_load_format_xyzw
; break;
8657 unreachable("Tex instruction loads more than 4 components.");
8660 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8661 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8664 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8666 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8667 mubuf
->operands
[0] = Operand(resource
);
8668 mubuf
->operands
[1] = Operand(coords
[0]);
8669 mubuf
->operands
[2] = Operand((uint32_t) 0);
8670 mubuf
->definitions
[0] = Definition(tmp_dst
);
8671 mubuf
->idxen
= true;
8672 mubuf
->can_reorder
= true;
8673 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8675 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8679 /* gather MIMG address components */
8680 std::vector
<Temp
> args
;
8682 args
.emplace_back(offset
);
8684 args
.emplace_back(bias
);
8686 args
.emplace_back(compare
);
8688 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8690 args
.insert(args
.end(), coords
.begin(), coords
.end());
8691 if (has_sample_index
)
8692 args
.emplace_back(sample_index
);
8694 args
.emplace_back(lod
);
8695 if (has_clamped_lod
)
8696 args
.emplace_back(clamped_lod
);
8698 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8699 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8700 vec
->definitions
[0] = Definition(arg
);
8701 for (unsigned i
= 0; i
< args
.size(); i
++)
8702 vec
->operands
[i
] = Operand(args
[i
]);
8703 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8706 if (instr
->op
== nir_texop_txf
||
8707 instr
->op
== nir_texop_txf_ms
||
8708 instr
->op
== nir_texop_samples_identical
||
8709 instr
->op
== nir_texop_fragment_fetch
||
8710 instr
->op
== nir_texop_fragment_mask_fetch
) {
8711 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8712 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8713 tex
->operands
[0] = Operand(resource
);
8714 tex
->operands
[1] = Operand(s4
); /* no sampler */
8715 tex
->operands
[2] = Operand(arg
);
8720 tex
->definitions
[0] = Definition(tmp_dst
);
8721 tex
->can_reorder
= true;
8722 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8724 if (instr
->op
== nir_texop_samples_identical
) {
8725 assert(dmask
== 1 && dst
.regClass() == v1
);
8726 assert(dst
.id() != tmp_dst
.id());
8728 Temp tmp
= bld
.tmp(bld
.lm
);
8729 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8730 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8733 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8738 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8739 aco_opcode opcode
= aco_opcode::image_sample
;
8740 if (has_offset
) { /* image_sample_*_o */
8741 if (has_clamped_lod
) {
8743 opcode
= aco_opcode::image_sample_c_cl_o
;
8745 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8747 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8749 opcode
= aco_opcode::image_sample_cl_o
;
8751 opcode
= aco_opcode::image_sample_d_cl_o
;
8753 opcode
= aco_opcode::image_sample_b_cl_o
;
8755 } else if (has_compare
) {
8756 opcode
= aco_opcode::image_sample_c_o
;
8758 opcode
= aco_opcode::image_sample_c_d_o
;
8760 opcode
= aco_opcode::image_sample_c_b_o
;
8762 opcode
= aco_opcode::image_sample_c_lz_o
;
8764 opcode
= aco_opcode::image_sample_c_l_o
;
8766 opcode
= aco_opcode::image_sample_o
;
8768 opcode
= aco_opcode::image_sample_d_o
;
8770 opcode
= aco_opcode::image_sample_b_o
;
8772 opcode
= aco_opcode::image_sample_lz_o
;
8774 opcode
= aco_opcode::image_sample_l_o
;
8776 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8778 opcode
= aco_opcode::image_sample_c_cl
;
8780 opcode
= aco_opcode::image_sample_c_d_cl
;
8782 opcode
= aco_opcode::image_sample_c_b_cl
;
8784 opcode
= aco_opcode::image_sample_cl
;
8786 opcode
= aco_opcode::image_sample_d_cl
;
8788 opcode
= aco_opcode::image_sample_b_cl
;
8790 } else { /* no offset */
8792 opcode
= aco_opcode::image_sample_c
;
8794 opcode
= aco_opcode::image_sample_c_d
;
8796 opcode
= aco_opcode::image_sample_c_b
;
8798 opcode
= aco_opcode::image_sample_c_lz
;
8800 opcode
= aco_opcode::image_sample_c_l
;
8802 opcode
= aco_opcode::image_sample
;
8804 opcode
= aco_opcode::image_sample_d
;
8806 opcode
= aco_opcode::image_sample_b
;
8808 opcode
= aco_opcode::image_sample_lz
;
8810 opcode
= aco_opcode::image_sample_l
;
8814 if (instr
->op
== nir_texop_tg4
) {
8815 if (has_offset
) { /* image_gather4_*_o */
8817 opcode
= aco_opcode::image_gather4_c_lz_o
;
8819 opcode
= aco_opcode::image_gather4_c_l_o
;
8821 opcode
= aco_opcode::image_gather4_c_b_o
;
8823 opcode
= aco_opcode::image_gather4_lz_o
;
8825 opcode
= aco_opcode::image_gather4_l_o
;
8827 opcode
= aco_opcode::image_gather4_b_o
;
8831 opcode
= aco_opcode::image_gather4_c_lz
;
8833 opcode
= aco_opcode::image_gather4_c_l
;
8835 opcode
= aco_opcode::image_gather4_c_b
;
8837 opcode
= aco_opcode::image_gather4_lz
;
8839 opcode
= aco_opcode::image_gather4_l
;
8841 opcode
= aco_opcode::image_gather4_b
;
8844 } else if (instr
->op
== nir_texop_lod
) {
8845 opcode
= aco_opcode::image_get_lod
;
8848 /* we don't need the bias, sample index, compare value or offset to be
8849 * computed in WQM but if the p_create_vector copies the coordinates, then it
8850 * needs to be in WQM */
8851 if (ctx
->stage
== fragment_fs
&&
8852 !has_derivs
&& !has_lod
&& !level_zero
&&
8853 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8854 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8855 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8857 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8858 tex
->operands
[0] = Operand(resource
);
8859 tex
->operands
[1] = Operand(sampler
);
8860 tex
->operands
[2] = Operand(arg
);
8864 tex
->definitions
[0] = Definition(tmp_dst
);
8865 tex
->can_reorder
= true;
8866 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8868 if (tg4_integer_cube_workaround
) {
8869 assert(tmp_dst
.id() != dst
.id());
8870 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8872 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8874 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8875 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8877 if (stype
== GLSL_TYPE_UINT
)
8878 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8880 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8881 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8883 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8884 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8885 val
[0], val
[1], val
[2], val
[3]);
8887 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8888 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8893 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8895 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8896 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8897 return Operand(tmp
.regClass());
8899 return Operand(tmp
);
8902 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8904 aco_ptr
<Pseudo_instruction
> phi
;
8905 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8906 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8908 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8909 logical
|= ctx
->block
->kind
& block_kind_merge
;
8910 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8912 /* we want a sorted list of sources, since the predecessor list is also sorted */
8913 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8914 nir_foreach_phi_src(src
, instr
)
8915 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8917 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8918 unsigned num_operands
= 0;
8919 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8920 unsigned num_defined
= 0;
8921 unsigned cur_pred_idx
= 0;
8922 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8923 if (cur_pred_idx
< preds
.size()) {
8924 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8925 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8926 unsigned skipped
= 0;
8927 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8929 if (cur_pred_idx
+ skipped
< preds
.size()) {
8930 for (unsigned i
= 0; i
< skipped
; i
++)
8931 operands
[num_operands
++] = Operand(dst
.regClass());
8932 cur_pred_idx
+= skipped
;
8937 /* Handle missing predecessors at the end. This shouldn't happen with loop
8938 * headers and we can't ignore these sources for loop header phis. */
8939 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8942 Operand op
= get_phi_operand(ctx
, src
.second
);
8943 operands
[num_operands
++] = op
;
8944 num_defined
+= !op
.isUndefined();
8946 /* handle block_kind_continue_or_break at loop exit blocks */
8947 while (cur_pred_idx
++ < preds
.size())
8948 operands
[num_operands
++] = Operand(dst
.regClass());
8950 /* If the loop ends with a break, still add a linear continue edge in case
8951 * that break is divergent or continue_or_break is used. We'll either remove
8952 * this operand later in visit_loop() if it's not necessary or replace the
8953 * undef with something correct. */
8954 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8955 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8956 nir_block
*last
= nir_loop_last_block(loop
);
8957 if (last
->successors
[0] != instr
->instr
.block
)
8958 operands
[num_operands
++] = Operand(RegClass());
8961 if (num_defined
== 0) {
8962 Builder
bld(ctx
->program
, ctx
->block
);
8963 if (dst
.regClass() == s1
) {
8964 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8965 } else if (dst
.regClass() == v1
) {
8966 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8968 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8969 for (unsigned i
= 0; i
< dst
.size(); i
++)
8970 vec
->operands
[i
] = Operand(0u);
8971 vec
->definitions
[0] = Definition(dst
);
8972 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8977 /* we can use a linear phi in some cases if one src is undef */
8978 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8979 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8981 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8982 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8983 assert(invert
->kind
& block_kind_invert
);
8985 unsigned then_block
= invert
->linear_preds
[0];
8987 Block
* insert_block
= NULL
;
8988 for (unsigned i
= 0; i
< num_operands
; i
++) {
8989 Operand op
= operands
[i
];
8990 if (op
.isUndefined())
8992 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8993 phi
->operands
[0] = op
;
8996 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8997 phi
->operands
[1] = Operand(dst
.regClass());
8998 phi
->definitions
[0] = Definition(dst
);
8999 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9003 /* try to scalarize vector phis */
9004 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9005 // TODO: scalarize linear phis on divergent ifs
9006 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9007 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9008 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9009 Operand src
= operands
[i
];
9010 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9011 can_scalarize
= false;
9013 if (can_scalarize
) {
9014 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9015 assert(dst
.size() % num_components
== 0);
9016 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9018 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9019 for (unsigned k
= 0; k
< num_components
; k
++) {
9020 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9021 for (unsigned i
= 0; i
< num_operands
; i
++) {
9022 Operand src
= operands
[i
];
9023 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9025 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9026 phi
->definitions
[0] = Definition(phi_dst
);
9027 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9028 new_vec
[k
] = phi_dst
;
9029 vec
->operands
[k
] = Operand(phi_dst
);
9031 vec
->definitions
[0] = Definition(dst
);
9032 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9033 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9038 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9039 for (unsigned i
= 0; i
< num_operands
; i
++)
9040 phi
->operands
[i
] = operands
[i
];
9041 phi
->definitions
[0] = Definition(dst
);
9042 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9046 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9048 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9050 assert(dst
.type() == RegType::sgpr
);
9052 if (dst
.size() == 1) {
9053 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9055 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9056 for (unsigned i
= 0; i
< dst
.size(); i
++)
9057 vec
->operands
[i
] = Operand(0u);
9058 vec
->definitions
[0] = Definition(dst
);
9059 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9063 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9065 Builder
bld(ctx
->program
, ctx
->block
);
9066 Block
*logical_target
;
9067 append_logical_end(ctx
->block
);
9068 unsigned idx
= ctx
->block
->index
;
9070 switch (instr
->type
) {
9071 case nir_jump_break
:
9072 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9073 add_logical_edge(idx
, logical_target
);
9074 ctx
->block
->kind
|= block_kind_break
;
9076 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9077 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9078 /* uniform break - directly jump out of the loop */
9079 ctx
->block
->kind
|= block_kind_uniform
;
9080 ctx
->cf_info
.has_branch
= true;
9081 bld
.branch(aco_opcode::p_branch
);
9082 add_linear_edge(idx
, logical_target
);
9085 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9086 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9088 case nir_jump_continue
:
9089 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9090 add_logical_edge(idx
, logical_target
);
9091 ctx
->block
->kind
|= block_kind_continue
;
9093 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9094 /* for potential uniform breaks after this continue,
9095 we must ensure that they are handled correctly */
9096 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9097 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9098 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9100 /* uniform continue - directly jump to the loop header */
9101 ctx
->block
->kind
|= block_kind_uniform
;
9102 ctx
->cf_info
.has_branch
= true;
9103 bld
.branch(aco_opcode::p_branch
);
9104 add_linear_edge(idx
, logical_target
);
9109 fprintf(stderr
, "Unknown NIR jump instr: ");
9110 nir_print_instr(&instr
->instr
, stderr
);
9111 fprintf(stderr
, "\n");
9115 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9116 ctx
->cf_info
.exec_potentially_empty_break
= true;
9117 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9120 /* remove critical edges from linear CFG */
9121 bld
.branch(aco_opcode::p_branch
);
9122 Block
* break_block
= ctx
->program
->create_and_insert_block();
9123 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9124 break_block
->kind
|= block_kind_uniform
;
9125 add_linear_edge(idx
, break_block
);
9126 /* the loop_header pointer might be invalidated by this point */
9127 if (instr
->type
== nir_jump_continue
)
9128 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9129 add_linear_edge(break_block
->index
, logical_target
);
9130 bld
.reset(break_block
);
9131 bld
.branch(aco_opcode::p_branch
);
9133 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9134 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9135 add_linear_edge(idx
, continue_block
);
9136 append_logical_start(continue_block
);
9137 ctx
->block
= continue_block
;
9141 void visit_block(isel_context
*ctx
, nir_block
*block
)
9143 nir_foreach_instr(instr
, block
) {
9144 switch (instr
->type
) {
9145 case nir_instr_type_alu
:
9146 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9148 case nir_instr_type_load_const
:
9149 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9151 case nir_instr_type_intrinsic
:
9152 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9154 case nir_instr_type_tex
:
9155 visit_tex(ctx
, nir_instr_as_tex(instr
));
9157 case nir_instr_type_phi
:
9158 visit_phi(ctx
, nir_instr_as_phi(instr
));
9160 case nir_instr_type_ssa_undef
:
9161 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9163 case nir_instr_type_deref
:
9165 case nir_instr_type_jump
:
9166 visit_jump(ctx
, nir_instr_as_jump(instr
));
9169 fprintf(stderr
, "Unknown NIR instr type: ");
9170 nir_print_instr(instr
, stderr
);
9171 fprintf(stderr
, "\n");
9176 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9177 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9182 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9183 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9185 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9186 RegClass rc
= vals
[0].regClass();
9188 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9190 unsigned next_pred
= 1;
9192 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9193 Block
& block
= ctx
->program
->blocks
[idx
];
9194 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9195 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9199 if (block
.kind
& block_kind_continue
) {
9200 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9205 bool all_same
= true;
9206 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9207 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9211 val
= vals
[block
.linear_preds
[0] - first
];
9213 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9214 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9215 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9216 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9217 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9218 phi
->definitions
[0] = Definition(val
.getTemp());
9219 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9221 vals
[idx
- first
] = val
;
9224 return vals
[last
- first
];
9227 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9229 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9230 append_logical_end(ctx
->block
);
9231 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9232 Builder
bld(ctx
->program
, ctx
->block
);
9233 bld
.branch(aco_opcode::p_branch
);
9234 unsigned loop_preheader_idx
= ctx
->block
->index
;
9236 Block loop_exit
= Block();
9237 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9238 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9240 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9241 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9242 loop_header
->kind
|= block_kind_loop_header
;
9243 add_edge(loop_preheader_idx
, loop_header
);
9244 ctx
->block
= loop_header
;
9246 /* emit loop body */
9247 unsigned loop_header_idx
= loop_header
->index
;
9248 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9249 append_logical_start(ctx
->block
);
9250 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9252 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9253 if (!ctx
->cf_info
.has_branch
) {
9254 append_logical_end(ctx
->block
);
9255 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9256 /* Discards can result in code running with an empty exec mask.
9257 * This would result in divergent breaks not ever being taken. As a
9258 * workaround, break the loop when the loop mask is empty instead of
9259 * always continuing. */
9260 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9261 unsigned block_idx
= ctx
->block
->index
;
9263 /* create helper blocks to avoid critical edges */
9264 Block
*break_block
= ctx
->program
->create_and_insert_block();
9265 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9266 break_block
->kind
= block_kind_uniform
;
9267 bld
.reset(break_block
);
9268 bld
.branch(aco_opcode::p_branch
);
9269 add_linear_edge(block_idx
, break_block
);
9270 add_linear_edge(break_block
->index
, &loop_exit
);
9272 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9273 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9274 continue_block
->kind
= block_kind_uniform
;
9275 bld
.reset(continue_block
);
9276 bld
.branch(aco_opcode::p_branch
);
9277 add_linear_edge(block_idx
, continue_block
);
9278 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9280 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9281 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9282 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9284 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9285 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9286 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9288 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9291 bld
.reset(ctx
->block
);
9292 bld
.branch(aco_opcode::p_branch
);
9295 /* Fixup phis in loop header from unreachable blocks.
9296 * has_branch/has_divergent_branch also indicates if the loop ends with a
9297 * break/continue instruction, but we don't emit those if unreachable=true */
9299 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9300 bool linear
= ctx
->cf_info
.has_branch
;
9301 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9302 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9303 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9304 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9305 /* the last operand should be the one that needs to be removed */
9306 instr
->operands
.pop_back();
9307 } else if (!is_phi(instr
)) {
9313 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9314 * and the previous one shouldn't both happen at once because a break in the
9315 * merge block would get CSE'd */
9316 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9317 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9318 Operand vals
[num_vals
];
9319 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9320 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9321 if (ctx
->cf_info
.has_branch
)
9322 instr
->operands
.pop_back();
9324 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9325 } else if (!is_phi(instr
)) {
9331 ctx
->cf_info
.has_branch
= false;
9333 // TODO: if the loop has not a single exit, we must add one °°
9334 /* emit loop successor block */
9335 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9336 append_logical_start(ctx
->block
);
9339 // TODO: check if it is beneficial to not branch on continues
9340 /* trim linear phis in loop header */
9341 for (auto&& instr
: loop_entry
->instructions
) {
9342 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9343 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9344 new_phi
->definitions
[0] = instr
->definitions
[0];
9345 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9346 new_phi
->operands
[i
] = instr
->operands
[i
];
9347 /* check that the remaining operands are all the same */
9348 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9349 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9350 instr
.swap(new_phi
);
9351 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9360 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9364 append_logical_end(ctx
->block
);
9365 ctx
->block
->kind
|= block_kind_branch
;
9367 /* branch to linear then block */
9368 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9369 aco_ptr
<Pseudo_branch_instruction
> branch
;
9370 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9371 branch
->operands
[0] = Operand(cond
);
9372 ctx
->block
->instructions
.push_back(std::move(branch
));
9374 ic
->BB_if_idx
= ctx
->block
->index
;
9375 ic
->BB_invert
= Block();
9376 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9377 /* Invert blocks are intentionally not marked as top level because they
9378 * are not part of the logical cfg. */
9379 ic
->BB_invert
.kind
|= block_kind_invert
;
9380 ic
->BB_endif
= Block();
9381 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9382 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9384 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9385 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9386 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9387 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9388 ctx
->cf_info
.parent_if
.is_divergent
= true;
9390 /* divergent branches use cbranch_execz */
9391 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9392 ctx
->cf_info
.exec_potentially_empty_break
= false;
9393 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9395 /** emit logical then block */
9396 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9397 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9398 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9399 ctx
->block
= BB_then_logical
;
9400 append_logical_start(BB_then_logical
);
9403 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9405 Block
*BB_then_logical
= ctx
->block
;
9406 append_logical_end(BB_then_logical
);
9407 /* branch from logical then block to invert block */
9408 aco_ptr
<Pseudo_branch_instruction
> branch
;
9409 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9410 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9411 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9412 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9413 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9414 BB_then_logical
->kind
|= block_kind_uniform
;
9415 assert(!ctx
->cf_info
.has_branch
);
9416 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9417 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9419 /** emit linear then block */
9420 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9421 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9422 BB_then_linear
->kind
|= block_kind_uniform
;
9423 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9424 /* branch from linear then block to invert block */
9425 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9426 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9427 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9429 /** emit invert merge block */
9430 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9431 ic
->invert_idx
= ctx
->block
->index
;
9433 /* branch to linear else block (skip else) */
9434 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9435 branch
->operands
[0] = Operand(ic
->cond
);
9436 ctx
->block
->instructions
.push_back(std::move(branch
));
9438 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9439 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9440 ic
->exec_potentially_empty_break_depth_old
=
9441 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9442 /* divergent branches use cbranch_execz */
9443 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9444 ctx
->cf_info
.exec_potentially_empty_break
= false;
9445 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9447 /** emit logical else block */
9448 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9449 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9450 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9451 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9452 ctx
->block
= BB_else_logical
;
9453 append_logical_start(BB_else_logical
);
9456 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9458 Block
*BB_else_logical
= ctx
->block
;
9459 append_logical_end(BB_else_logical
);
9461 /* branch from logical else block to endif block */
9462 aco_ptr
<Pseudo_branch_instruction
> branch
;
9463 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9464 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9465 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9466 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9467 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9468 BB_else_logical
->kind
|= block_kind_uniform
;
9470 assert(!ctx
->cf_info
.has_branch
);
9471 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9474 /** emit linear else block */
9475 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9476 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9477 BB_else_linear
->kind
|= block_kind_uniform
;
9478 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9480 /* branch from linear else block to endif block */
9481 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9482 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9483 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9486 /** emit endif merge block */
9487 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9488 append_logical_start(ctx
->block
);
9491 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9492 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9493 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9494 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9495 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9496 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9497 !ctx
->cf_info
.parent_if
.is_divergent
) {
9498 ctx
->cf_info
.exec_potentially_empty_break
= false;
9499 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9501 /* uniform control flow never has an empty exec-mask */
9502 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9503 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9504 ctx
->cf_info
.exec_potentially_empty_break
= false;
9505 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9509 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9511 assert(cond
.regClass() == s1
);
9513 append_logical_end(ctx
->block
);
9514 ctx
->block
->kind
|= block_kind_uniform
;
9516 aco_ptr
<Pseudo_branch_instruction
> branch
;
9517 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9518 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9519 branch
->operands
[0] = Operand(cond
);
9520 branch
->operands
[0].setFixed(scc
);
9521 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9523 ic
->BB_if_idx
= ctx
->block
->index
;
9524 ic
->BB_endif
= Block();
9525 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9526 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9528 ctx
->cf_info
.has_branch
= false;
9529 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9531 /** emit then block */
9532 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9533 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9534 add_edge(ic
->BB_if_idx
, BB_then
);
9535 append_logical_start(BB_then
);
9536 ctx
->block
= BB_then
;
9539 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9541 Block
*BB_then
= ctx
->block
;
9543 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9544 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9546 if (!ic
->uniform_has_then_branch
) {
9547 append_logical_end(BB_then
);
9548 /* branch from then block to endif block */
9549 aco_ptr
<Pseudo_branch_instruction
> branch
;
9550 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9551 BB_then
->instructions
.emplace_back(std::move(branch
));
9552 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9553 if (!ic
->then_branch_divergent
)
9554 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9555 BB_then
->kind
|= block_kind_uniform
;
9558 ctx
->cf_info
.has_branch
= false;
9559 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9561 /** emit else block */
9562 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9563 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9564 add_edge(ic
->BB_if_idx
, BB_else
);
9565 append_logical_start(BB_else
);
9566 ctx
->block
= BB_else
;
9569 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9571 Block
*BB_else
= ctx
->block
;
9573 if (!ctx
->cf_info
.has_branch
) {
9574 append_logical_end(BB_else
);
9575 /* branch from then block to endif block */
9576 aco_ptr
<Pseudo_branch_instruction
> branch
;
9577 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9578 BB_else
->instructions
.emplace_back(std::move(branch
));
9579 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9580 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9581 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9582 BB_else
->kind
|= block_kind_uniform
;
9585 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9586 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9588 /** emit endif merge block */
9589 if (!ctx
->cf_info
.has_branch
) {
9590 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9591 append_logical_start(ctx
->block
);
9595 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9597 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9598 Builder
bld(ctx
->program
, ctx
->block
);
9599 aco_ptr
<Pseudo_branch_instruction
> branch
;
9602 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9604 * Uniform conditionals are represented in the following way*) :
9606 * The linear and logical CFG:
9609 * BB_THEN (logical) BB_ELSE (logical)
9613 * *) Exceptions may be due to break and continue statements within loops
9614 * If a break/continue happens within uniform control flow, it branches
9615 * to the loop exit/entry block. Otherwise, it branches to the next
9619 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9620 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9621 cond
= bool_to_scalar_condition(ctx
, cond
);
9623 begin_uniform_if_then(ctx
, &ic
, cond
);
9624 visit_cf_list(ctx
, &if_stmt
->then_list
);
9626 begin_uniform_if_else(ctx
, &ic
);
9627 visit_cf_list(ctx
, &if_stmt
->else_list
);
9629 end_uniform_if(ctx
, &ic
);
9630 } else { /* non-uniform condition */
9632 * To maintain a logical and linear CFG without critical edges,
9633 * non-uniform conditionals are represented in the following way*) :
9638 * BB_THEN (logical) BB_THEN (linear)
9640 * BB_INVERT (linear)
9642 * BB_ELSE (logical) BB_ELSE (linear)
9649 * BB_THEN (logical) BB_ELSE (logical)
9653 * *) Exceptions may be due to break and continue statements within loops
9656 begin_divergent_if_then(ctx
, &ic
, cond
);
9657 visit_cf_list(ctx
, &if_stmt
->then_list
);
9659 begin_divergent_if_else(ctx
, &ic
);
9660 visit_cf_list(ctx
, &if_stmt
->else_list
);
9662 end_divergent_if(ctx
, &ic
);
9665 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9668 static bool visit_cf_list(isel_context
*ctx
,
9669 struct exec_list
*list
)
9671 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9672 switch (node
->type
) {
9673 case nir_cf_node_block
:
9674 visit_block(ctx
, nir_cf_node_as_block(node
));
9676 case nir_cf_node_if
:
9677 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9680 case nir_cf_node_loop
:
9681 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9684 unreachable("unimplemented cf list type");
9690 static void create_null_export(isel_context
*ctx
)
9692 /* Some shader stages always need to have exports.
9693 * So when there is none, we need to add a null export.
9696 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9697 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9698 Builder
bld(ctx
->program
, ctx
->block
);
9699 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9700 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9703 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9705 assert(ctx
->stage
== vertex_vs
||
9706 ctx
->stage
== tess_eval_vs
||
9707 ctx
->stage
== gs_copy_vs
||
9708 ctx
->stage
== ngg_vertex_gs
||
9709 ctx
->stage
== ngg_tess_eval_gs
);
9711 int offset
= (ctx
->stage
& sw_tes
)
9712 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9713 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9714 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9715 if (!is_pos
&& !mask
)
9717 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9719 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9720 exp
->enabled_mask
= mask
;
9721 for (unsigned i
= 0; i
< 4; ++i
) {
9722 if (mask
& (1 << i
))
9723 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9725 exp
->operands
[i
] = Operand(v1
);
9727 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9728 * Setting valid_mask=1 prevents it and has no other effect.
9730 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9732 exp
->compressed
= false;
9734 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9736 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9737 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9742 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9744 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9745 exp
->enabled_mask
= 0;
9746 for (unsigned i
= 0; i
< 4; ++i
)
9747 exp
->operands
[i
] = Operand(v1
);
9748 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9749 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9750 exp
->enabled_mask
|= 0x1;
9752 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9753 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9754 exp
->enabled_mask
|= 0x4;
9756 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9757 if (ctx
->options
->chip_class
< GFX9
) {
9758 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9759 exp
->enabled_mask
|= 0x8;
9761 Builder
bld(ctx
->program
, ctx
->block
);
9763 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9764 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9765 if (exp
->operands
[2].isTemp())
9766 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9768 exp
->operands
[2] = Operand(out
);
9769 exp
->enabled_mask
|= 0x4;
9772 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9774 exp
->compressed
= false;
9775 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9776 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9779 static void create_export_phis(isel_context
*ctx
)
9781 /* Used when exports are needed, but the output temps are defined in a preceding block.
9782 * This function will set up phis in order to access the outputs in the next block.
9785 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9786 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9787 ctx
->block
->instructions
.pop_back();
9789 Builder
bld(ctx
->program
, ctx
->block
);
9791 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9792 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9793 for (unsigned i
= 0; i
< 4; ++i
) {
9794 if (!(mask
& (1 << i
)))
9797 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9798 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9799 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9803 bld
.insert(std::move(logical_start
));
9806 static void create_vs_exports(isel_context
*ctx
)
9808 assert(ctx
->stage
== vertex_vs
||
9809 ctx
->stage
== tess_eval_vs
||
9810 ctx
->stage
== gs_copy_vs
||
9811 ctx
->stage
== ngg_vertex_gs
||
9812 ctx
->stage
== ngg_tess_eval_gs
);
9814 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9815 ? &ctx
->program
->info
->tes
.outinfo
9816 : &ctx
->program
->info
->vs
.outinfo
;
9818 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9819 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9820 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9823 if (ctx
->options
->key
.has_multiview_view_index
) {
9824 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9825 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9828 /* the order these position exports are created is important */
9830 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9831 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9832 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9833 exported_pos
= true;
9835 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9836 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9837 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9838 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9840 if (ctx
->export_clip_dists
) {
9841 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9842 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9843 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9844 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9847 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9848 if (i
< VARYING_SLOT_VAR0
&&
9849 i
!= VARYING_SLOT_LAYER
&&
9850 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9851 i
!= VARYING_SLOT_VIEWPORT
)
9854 export_vs_varying(ctx
, i
, false, NULL
);
9858 create_null_export(ctx
);
9861 static bool export_fs_mrt_z(isel_context
*ctx
)
9863 Builder
bld(ctx
->program
, ctx
->block
);
9864 unsigned enabled_channels
= 0;
9868 for (unsigned i
= 0; i
< 4; ++i
) {
9869 values
[i
] = Operand(v1
);
9872 /* Both stencil and sample mask only need 16-bits. */
9873 if (!ctx
->program
->info
->ps
.writes_z
&&
9874 (ctx
->program
->info
->ps
.writes_stencil
||
9875 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9876 compr
= true; /* COMPR flag */
9878 if (ctx
->program
->info
->ps
.writes_stencil
) {
9879 /* Stencil should be in X[23:16]. */
9880 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9881 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9882 enabled_channels
|= 0x3;
9885 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9886 /* SampleMask should be in Y[15:0]. */
9887 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9888 enabled_channels
|= 0xc;
9891 if (ctx
->program
->info
->ps
.writes_z
) {
9892 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9893 enabled_channels
|= 0x1;
9896 if (ctx
->program
->info
->ps
.writes_stencil
) {
9897 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9898 enabled_channels
|= 0x2;
9901 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9902 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9903 enabled_channels
|= 0x4;
9907 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9908 * writemask component.
9910 if (ctx
->options
->chip_class
== GFX6
&&
9911 ctx
->options
->family
!= CHIP_OLAND
&&
9912 ctx
->options
->family
!= CHIP_HAINAN
) {
9913 enabled_channels
|= 0x1;
9916 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9917 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9922 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9924 Builder
bld(ctx
->program
, ctx
->block
);
9925 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9928 for (unsigned i
= 0; i
< 4; ++i
) {
9929 if (write_mask
& (1 << i
)) {
9930 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9932 values
[i
] = Operand(v1
);
9936 unsigned target
, col_format
;
9937 unsigned enabled_channels
= 0;
9938 aco_opcode compr_op
= (aco_opcode
)0;
9940 slot
-= FRAG_RESULT_DATA0
;
9941 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9942 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9944 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9945 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9946 bool is_16bit
= values
[0].regClass() == v2b
;
9950 case V_028714_SPI_SHADER_ZERO
:
9951 enabled_channels
= 0; /* writemask */
9952 target
= V_008DFC_SQ_EXP_NULL
;
9955 case V_028714_SPI_SHADER_32_R
:
9956 enabled_channels
= 1;
9959 case V_028714_SPI_SHADER_32_GR
:
9960 enabled_channels
= 0x3;
9963 case V_028714_SPI_SHADER_32_AR
:
9964 if (ctx
->options
->chip_class
>= GFX10
) {
9965 /* Special case: on GFX10, the outputs are different for 32_AR */
9966 enabled_channels
= 0x3;
9967 values
[1] = values
[3];
9968 values
[3] = Operand(v1
);
9970 enabled_channels
= 0x9;
9974 case V_028714_SPI_SHADER_FP16_ABGR
:
9975 enabled_channels
= 0x5;
9976 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9978 if (ctx
->options
->chip_class
>= GFX9
) {
9979 /* Pack the FP16 values together instead of converting them to
9980 * FP32 and back to FP16.
9981 * TODO: use p_create_vector and let the compiler optimizes.
9983 compr_op
= aco_opcode::v_pack_b32_f16
;
9985 for (unsigned i
= 0; i
< 4; i
++) {
9986 if ((write_mask
>> i
) & 1)
9987 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9993 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9994 enabled_channels
= 0x5;
9995 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9996 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9998 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10002 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10003 enabled_channels
= 0x5;
10004 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10005 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10007 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10011 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10012 enabled_channels
= 0x5;
10013 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10014 if (is_int8
|| is_int10
) {
10016 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10017 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10019 for (unsigned i
= 0; i
< 4; i
++) {
10020 if ((write_mask
>> i
) & 1) {
10021 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10022 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10026 } else if (is_16bit
) {
10027 for (unsigned i
= 0; i
< 4; i
++) {
10028 if ((write_mask
>> i
) & 1) {
10029 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10030 values
[i
] = Operand(tmp
);
10037 case V_028714_SPI_SHADER_SINT16_ABGR
:
10038 enabled_channels
= 0x5;
10039 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10040 if (is_int8
|| is_int10
) {
10042 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10043 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10044 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10045 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10047 for (unsigned i
= 0; i
< 4; i
++) {
10048 if ((write_mask
>> i
) & 1) {
10049 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10050 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10052 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10053 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10057 } else if (is_16bit
) {
10058 for (unsigned i
= 0; i
< 4; i
++) {
10059 if ((write_mask
>> i
) & 1) {
10060 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10061 values
[i
] = Operand(tmp
);
10067 case V_028714_SPI_SHADER_32_ABGR
:
10068 enabled_channels
= 0xF;
10075 if (target
== V_008DFC_SQ_EXP_NULL
)
10078 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10079 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10081 (col_format
== V_028714_SPI_SHADER_32_R
||
10082 col_format
== V_028714_SPI_SHADER_32_GR
||
10083 col_format
== V_028714_SPI_SHADER_32_AR
||
10084 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10085 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10086 for (int i
= 0; i
< 4; i
++) {
10087 if (!(write_mask
& (1 << i
)))
10090 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10091 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10092 bld
.copy(bld
.def(v1
), Operand(3u)));
10093 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10094 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10098 if ((bool) compr_op
) {
10099 for (int i
= 0; i
< 2; i
++) {
10100 /* check if at least one of the values to be compressed is enabled */
10101 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10103 enabled_channels
|= enabled
<< (i
*2);
10104 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10105 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10106 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10108 values
[i
] = Operand(v1
);
10111 values
[2] = Operand(v1
);
10112 values
[3] = Operand(v1
);
10114 for (int i
= 0; i
< 4; i
++)
10115 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10118 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10119 enabled_channels
, target
, (bool) compr_op
);
10123 static void create_fs_exports(isel_context
*ctx
)
10125 bool exported
= false;
10127 /* Export depth, stencil and sample mask. */
10128 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10129 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10130 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10131 exported
|= export_fs_mrt_z(ctx
);
10133 /* Export all color render targets. */
10134 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10135 if (ctx
->outputs
.mask
[i
])
10136 exported
|= export_fs_mrt_color(ctx
, i
);
10139 create_null_export(ctx
);
10142 static void write_tcs_tess_factors(isel_context
*ctx
)
10144 unsigned outer_comps
;
10145 unsigned inner_comps
;
10147 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10164 Builder
bld(ctx
->program
, ctx
->block
);
10166 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10167 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10168 bld
.sopp(aco_opcode::s_barrier
);
10170 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10171 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10173 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10174 if_context ic_invocation_id_is_zero
;
10175 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10176 bld
.reset(ctx
->block
);
10178 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10180 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10181 unsigned stride
= inner_comps
+ outer_comps
;
10182 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10186 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10188 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10190 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10191 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10192 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10194 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10195 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10197 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10198 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10199 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10200 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10203 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10204 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10205 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10206 unsigned tf_const_offset
= 0;
10208 if (ctx
->program
->chip_class
<= GFX8
) {
10209 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10210 if_context ic_rel_patch_id_is_zero
;
10211 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10212 bld
.reset(ctx
->block
);
10214 /* Store the dynamic HS control word. */
10215 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10216 bld
.mubuf(aco_opcode::buffer_store_dword
,
10217 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10218 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10219 /* disable_wqm */ false, /* glc */ true);
10220 tf_const_offset
+= 4;
10222 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10223 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10224 bld
.reset(ctx
->block
);
10227 assert(stride
== 2 || stride
== 4 || stride
== 6);
10228 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10229 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10231 /* Store to offchip for TES to read - only if TES reads them */
10232 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10233 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10234 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10236 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10237 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10239 if (likely(inner_comps
)) {
10240 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10241 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10245 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10246 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10249 static void emit_stream_output(isel_context
*ctx
,
10250 Temp
const *so_buffers
,
10251 Temp
const *so_write_offset
,
10252 const struct radv_stream_output
*output
)
10254 unsigned num_comps
= util_bitcount(output
->component_mask
);
10255 unsigned writemask
= (1 << num_comps
) - 1;
10256 unsigned loc
= output
->location
;
10257 unsigned buf
= output
->buffer
;
10259 assert(num_comps
&& num_comps
<= 4);
10260 if (!num_comps
|| num_comps
> 4)
10263 unsigned start
= ffs(output
->component_mask
) - 1;
10266 bool all_undef
= true;
10267 assert(ctx
->stage
& hw_vs
);
10268 for (unsigned i
= 0; i
< num_comps
; i
++) {
10269 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10270 all_undef
= all_undef
&& !out
[i
].id();
10275 while (writemask
) {
10277 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10278 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10279 /* GFX6 doesn't support storing vec3, split it. */
10280 writemask
|= 1u << (start
+ 2);
10284 unsigned offset
= output
->offset
+ start
* 4;
10286 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10287 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10288 for (int i
= 0; i
< count
; ++i
)
10289 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10290 vec
->definitions
[0] = Definition(write_data
);
10291 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10296 opcode
= aco_opcode::buffer_store_dword
;
10299 opcode
= aco_opcode::buffer_store_dwordx2
;
10302 opcode
= aco_opcode::buffer_store_dwordx3
;
10305 opcode
= aco_opcode::buffer_store_dwordx4
;
10308 unreachable("Unsupported dword count.");
10311 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10312 store
->operands
[0] = Operand(so_buffers
[buf
]);
10313 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10314 store
->operands
[2] = Operand((uint32_t) 0);
10315 store
->operands
[3] = Operand(write_data
);
10316 if (offset
> 4095) {
10317 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10318 Builder
bld(ctx
->program
, ctx
->block
);
10319 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10321 store
->offset
= offset
;
10323 store
->offen
= true;
10325 store
->dlc
= false;
10327 store
->can_reorder
= true;
10328 ctx
->block
->instructions
.emplace_back(std::move(store
));
10332 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10334 Builder
bld(ctx
->program
, ctx
->block
);
10336 Temp so_buffers
[4];
10337 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10338 for (unsigned i
= 0; i
< 4; i
++) {
10339 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10343 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10344 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10347 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10348 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10350 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10352 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10355 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10357 bld
.reset(ctx
->block
);
10359 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10361 Temp so_write_offset
[4];
10363 for (unsigned i
= 0; i
< 4; i
++) {
10364 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10369 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10370 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10371 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10372 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10374 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10376 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10377 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10378 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10379 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10383 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10384 struct radv_stream_output
*output
=
10385 &ctx
->program
->info
->so
.outputs
[i
];
10386 if (stream
!= output
->stream
)
10389 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10392 begin_divergent_if_else(ctx
, &ic
);
10393 end_divergent_if(ctx
, &ic
);
10396 } /* end namespace */
10398 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10400 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10401 Builder
bld(ctx
->program
, ctx
->block
);
10402 constexpr unsigned hs_idx
= 1u;
10403 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10404 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10405 Operand((8u << 16) | (hs_idx
* 8u)));
10406 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10408 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10410 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10411 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10412 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10413 ls_has_nonzero_hs_threads
);
10414 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10415 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10416 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10417 ls_has_nonzero_hs_threads
);
10418 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10419 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10420 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10421 ls_has_nonzero_hs_threads
);
10423 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10424 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10425 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10428 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10430 /* Split all arguments except for the first (ring_offsets) and the last
10431 * (exec) so that the dead channels don't stay live throughout the program.
10433 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10434 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10435 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10436 startpgm
->definitions
[i
].regClass().size());
10441 void handle_bc_optimize(isel_context
*ctx
)
10443 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10444 Builder
bld(ctx
->program
, ctx
->block
);
10445 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10446 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10447 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10448 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10449 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10450 if (uses_center
&& uses_centroid
) {
10451 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10452 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10454 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10456 for (unsigned i
= 0; i
< 2; i
++) {
10457 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10458 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10459 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10460 persp_centroid
, persp_center
, sel
);
10462 ctx
->persp_centroid
= bld
.tmp(v2
);
10463 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10464 Operand(new_coord
[0]), Operand(new_coord
[1]));
10465 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10468 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10470 for (unsigned i
= 0; i
< 2; i
++) {
10471 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10472 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10473 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10474 linear_centroid
, linear_center
, sel
);
10476 ctx
->linear_centroid
= bld
.tmp(v2
);
10477 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10478 Operand(new_coord
[0]), Operand(new_coord
[1]));
10479 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10484 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10486 Program
*program
= ctx
->program
;
10488 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10490 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10491 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10492 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10493 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10494 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10496 program
->next_fp_mode
.must_flush_denorms32
=
10497 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10498 program
->next_fp_mode
.must_flush_denorms16_64
=
10499 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10500 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10502 program
->next_fp_mode
.care_about_round32
=
10503 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10505 program
->next_fp_mode
.care_about_round16_64
=
10506 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10507 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10509 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10510 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10511 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10512 program
->next_fp_mode
.denorm16_64
= 0;
10514 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10516 /* preserving fp32 denorms is expensive, so only do it if asked */
10517 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10518 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10520 program
->next_fp_mode
.denorm32
= 0;
10522 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10523 program
->next_fp_mode
.round32
= fp_round_tz
;
10525 program
->next_fp_mode
.round32
= fp_round_ne
;
10527 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10528 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10530 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10532 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10535 void cleanup_cfg(Program
*program
)
10537 /* create linear_succs/logical_succs */
10538 for (Block
& BB
: program
->blocks
) {
10539 for (unsigned idx
: BB
.linear_preds
)
10540 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10541 for (unsigned idx
: BB
.logical_preds
)
10542 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10546 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10548 Builder
bld(ctx
->program
, ctx
->block
);
10550 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10551 Temp count
= i
== 0
10552 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10553 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10554 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10556 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10559 if (ctx
->program
->wave_size
== 64) {
10560 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10561 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10562 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10564 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10565 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10571 bool ngg_early_prim_export(isel_context
*ctx
)
10573 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10577 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10579 Builder
bld(ctx
->program
, ctx
->block
);
10581 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10582 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10584 /* Get the id of the current wave within the threadgroup (workgroup) */
10585 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10586 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10588 /* Execute the following code only on the first wave (wave id 0),
10589 * use the SCC def to tell if the wave id is zero or not.
10591 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10593 begin_uniform_if_then(ctx
, &ic
, cond
);
10594 begin_uniform_if_else(ctx
, &ic
);
10595 bld
.reset(ctx
->block
);
10597 /* Number of vertices output by VS/TES */
10598 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10599 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10600 /* Number of primitives output by VS/TES */
10601 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10602 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10604 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10605 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10606 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10608 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10609 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10611 end_uniform_if(ctx
, &ic
);
10613 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10614 bld
.reset(ctx
->block
);
10615 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10618 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10620 Builder
bld(ctx
->program
, ctx
->block
);
10622 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10623 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10626 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10629 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10630 assert(vtxindex
[i
].id());
10633 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10637 /* The initial edge flag is always false in tess eval shaders. */
10638 if (ctx
->stage
== ngg_vertex_gs
) {
10639 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10640 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10644 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10649 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10651 Builder
bld(ctx
->program
, ctx
->block
);
10652 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10654 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10655 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10656 false /* compressed */, true/* done */, false /* valid mask */);
10659 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10661 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10662 * These must always come before VS exports.
10664 * It is recommended to do these as early as possible. They can be at the beginning when
10665 * there is no SW GS and the shader doesn't write edge flags.
10669 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10670 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10672 Builder
bld(ctx
->program
, ctx
->block
);
10673 constexpr unsigned max_vertices_per_primitive
= 3;
10674 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10676 if (ctx
->stage
== ngg_vertex_gs
) {
10677 /* TODO: optimize for points & lines */
10678 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10679 if (ctx
->shader
->info
.tess
.point_mode
)
10680 num_vertices_per_primitive
= 1;
10681 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10682 num_vertices_per_primitive
= 2;
10684 unreachable("Unsupported NGG shader stage");
10687 Temp vtxindex
[max_vertices_per_primitive
];
10688 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10689 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10690 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10691 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10692 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10693 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10694 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10695 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10697 /* Export primitive data to the index buffer. */
10698 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10700 /* Export primitive ID. */
10701 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10702 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10703 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10704 Temp provoking_vtx_index
= vtxindex
[0];
10705 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10707 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10710 begin_divergent_if_else(ctx
, &ic
);
10711 end_divergent_if(ctx
, &ic
);
10714 void ngg_emit_nogs_output(isel_context
*ctx
)
10716 /* Emits NGG GS output, for stages that don't have SW GS. */
10719 Builder
bld(ctx
->program
, ctx
->block
);
10720 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10722 /* NGG streamout is currently disabled by default. */
10723 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10725 if (late_prim_export
) {
10726 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10727 create_export_phis(ctx
);
10728 /* Do what we need to do in the GS threads. */
10729 ngg_emit_nogs_gsthreads(ctx
);
10731 /* What comes next should be executed on ES threads. */
10732 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10733 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10734 bld
.reset(ctx
->block
);
10737 /* Export VS outputs */
10738 ctx
->block
->kind
|= block_kind_export_end
;
10739 create_vs_exports(ctx
);
10741 /* Export primitive ID */
10742 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10745 if (ctx
->stage
== ngg_vertex_gs
) {
10746 /* Wait for GS threads to store primitive ID in LDS. */
10747 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10748 bld
.sopp(aco_opcode::s_barrier
);
10750 /* Calculate LDS address where the GS threads stored the primitive ID. */
10751 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10752 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10753 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10754 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10755 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10756 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10758 /* Load primitive ID from LDS. */
10759 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10760 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10761 /* TES: Just use the patch ID as the primitive ID. */
10762 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10764 unreachable("unsupported NGG shader stage.");
10767 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10768 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10770 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10773 if (late_prim_export
) {
10774 begin_divergent_if_else(ctx
, &ic
);
10775 end_divergent_if(ctx
, &ic
);
10776 bld
.reset(ctx
->block
);
10780 void select_program(Program
*program
,
10781 unsigned shader_count
,
10782 struct nir_shader
*const *shaders
,
10783 ac_shader_config
* config
,
10784 struct radv_shader_args
*args
)
10786 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10787 if_context ic_merged_wave_info
;
10788 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10790 for (unsigned i
= 0; i
< shader_count
; i
++) {
10791 nir_shader
*nir
= shaders
[i
];
10792 init_context(&ctx
, nir
);
10794 setup_fp_mode(&ctx
, nir
);
10797 /* needs to be after init_context() for FS */
10798 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10799 append_logical_start(ctx
.block
);
10801 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10802 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10804 split_arguments(&ctx
, startpgm
);
10808 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10810 if (ngg_early_prim_export(&ctx
))
10811 ngg_emit_nogs_gsthreads(&ctx
);
10814 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10815 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10816 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10817 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10818 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10819 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10820 ctx
.stage
== tess_eval_geometry_gs
));
10822 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10823 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10824 if (check_merged_wave_info
) {
10825 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10826 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10830 Builder
bld(ctx
.program
, ctx
.block
);
10832 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10833 bld
.sopp(aco_opcode::s_barrier
);
10835 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10836 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10838 } else if (ctx
.stage
== geometry_gs
)
10839 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10841 if (ctx
.stage
== fragment_fs
)
10842 handle_bc_optimize(&ctx
);
10844 visit_cf_list(&ctx
, &func
->body
);
10846 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10847 emit_streamout(&ctx
, 0);
10849 if (ctx
.stage
& hw_vs
) {
10850 create_vs_exports(&ctx
);
10851 ctx
.block
->kind
|= block_kind_export_end
;
10852 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10853 ngg_emit_nogs_output(&ctx
);
10854 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10855 Builder
bld(ctx
.program
, ctx
.block
);
10856 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10857 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10858 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10859 write_tcs_tess_factors(&ctx
);
10862 if (ctx
.stage
== fragment_fs
) {
10863 create_fs_exports(&ctx
);
10864 ctx
.block
->kind
|= block_kind_export_end
;
10867 if (endif_merged_wave_info
) {
10868 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10869 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10872 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10873 ngg_emit_nogs_output(&ctx
);
10875 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10876 /* Outputs of the previous stage are inputs to the next stage */
10877 ctx
.inputs
= ctx
.outputs
;
10878 ctx
.outputs
= shader_io_state();
10882 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10884 append_logical_end(ctx
.block
);
10885 ctx
.block
->kind
|= block_kind_uniform
;
10886 Builder
bld(ctx
.program
, ctx
.block
);
10887 if (ctx
.program
->wb_smem_l1_on_end
)
10888 bld
.smem(aco_opcode::s_dcache_wb
, false);
10889 bld
.sopp(aco_opcode::s_endpgm
);
10891 cleanup_cfg(program
);
10894 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10895 ac_shader_config
* config
,
10896 struct radv_shader_args
*args
)
10898 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10900 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10901 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10902 program
->next_fp_mode
.must_flush_denorms32
= false;
10903 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10904 program
->next_fp_mode
.care_about_round32
= false;
10905 program
->next_fp_mode
.care_about_round16_64
= false;
10906 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10907 program
->next_fp_mode
.denorm32
= 0;
10908 program
->next_fp_mode
.round32
= fp_round_ne
;
10909 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10910 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10912 add_startpgm(&ctx
);
10913 append_logical_start(ctx
.block
);
10915 Builder
bld(ctx
.program
, ctx
.block
);
10917 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10919 Operand
stream_id(0u);
10920 if (args
->shader_info
->so
.num_outputs
)
10921 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10922 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10924 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10926 std::stack
<Block
> endif_blocks
;
10928 for (unsigned stream
= 0; stream
< 4; stream
++) {
10929 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10932 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10933 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10936 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10938 unsigned BB_if_idx
= ctx
.block
->index
;
10939 Block BB_endif
= Block();
10940 if (!stream_id
.isConstant()) {
10942 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10943 append_logical_end(ctx
.block
);
10944 ctx
.block
->kind
|= block_kind_uniform
;
10945 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10947 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10949 ctx
.block
= ctx
.program
->create_and_insert_block();
10950 add_edge(BB_if_idx
, ctx
.block
);
10951 bld
.reset(ctx
.block
);
10952 append_logical_start(ctx
.block
);
10955 unsigned offset
= 0;
10956 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10957 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10960 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10961 unsigned length
= util_last_bit(output_usage_mask
);
10962 for (unsigned j
= 0; j
< length
; ++j
) {
10963 if (!(output_usage_mask
& (1 << j
)))
10966 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10967 Temp voffset
= vtx_offset
;
10968 if (const_offset
>= 4096u) {
10969 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10970 const_offset
%= 4096u;
10973 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10974 mubuf
->definitions
[0] = bld
.def(v1
);
10975 mubuf
->operands
[0] = Operand(gsvs_ring
);
10976 mubuf
->operands
[1] = Operand(voffset
);
10977 mubuf
->operands
[2] = Operand(0u);
10978 mubuf
->offen
= true;
10979 mubuf
->offset
= const_offset
;
10982 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10983 mubuf
->barrier
= barrier_none
;
10984 mubuf
->can_reorder
= true;
10986 ctx
.outputs
.mask
[i
] |= 1 << j
;
10987 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10989 bld
.insert(std::move(mubuf
));
10995 if (args
->shader_info
->so
.num_outputs
) {
10996 emit_streamout(&ctx
, stream
);
10997 bld
.reset(ctx
.block
);
11001 create_vs_exports(&ctx
);
11002 ctx
.block
->kind
|= block_kind_export_end
;
11005 if (!stream_id
.isConstant()) {
11006 append_logical_end(ctx
.block
);
11008 /* branch from then block to endif block */
11009 bld
.branch(aco_opcode::p_branch
);
11010 add_edge(ctx
.block
->index
, &BB_endif
);
11011 ctx
.block
->kind
|= block_kind_uniform
;
11013 /* emit else block */
11014 ctx
.block
= ctx
.program
->create_and_insert_block();
11015 add_edge(BB_if_idx
, ctx
.block
);
11016 bld
.reset(ctx
.block
);
11017 append_logical_start(ctx
.block
);
11019 endif_blocks
.push(std::move(BB_endif
));
11023 while (!endif_blocks
.empty()) {
11024 Block BB_endif
= std::move(endif_blocks
.top());
11025 endif_blocks
.pop();
11027 Block
*BB_else
= ctx
.block
;
11029 append_logical_end(BB_else
);
11030 /* branch from else block to endif block */
11031 bld
.branch(aco_opcode::p_branch
);
11032 add_edge(BB_else
->index
, &BB_endif
);
11033 BB_else
->kind
|= block_kind_uniform
;
11035 /** emit endif merge block */
11036 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11037 bld
.reset(ctx
.block
);
11038 append_logical_start(ctx
.block
);
11041 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11043 append_logical_end(ctx
.block
);
11044 ctx
.block
->kind
|= block_kind_uniform
;
11045 bld
.sopp(aco_opcode::s_endpgm
);
11047 cleanup_cfg(program
);