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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
308 if (num_components
> vec_src
.size()) {
309 if (vec_src
.type() == RegType::sgpr
) {
310 /* should still help get_alu_src() */
311 emit_split_vector(ctx
, vec_src
, vec_src
.size());
314 /* sub-dword split */
315 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
317 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
319 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
320 split
->operands
[0] = Operand(vec_src
);
321 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
322 for (unsigned i
= 0; i
< num_components
; i
++) {
323 elems
[i
] = {ctx
->program
->allocateId(), rc
};
324 split
->definitions
[i
] = Definition(elems
[i
]);
326 ctx
->block
->instructions
.emplace_back(std::move(split
));
327 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
330 /* This vector expansion uses a mask to determine which elements in the new vector
331 * come from the original vector. The other elements are undefined. */
332 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
334 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
339 Builder
bld(ctx
->program
, ctx
->block
);
340 if (num_components
== 1) {
341 if (dst
.type() == RegType::sgpr
)
342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
344 bld
.copy(Definition(dst
), vec_src
);
348 unsigned component_size
= dst
.size() / num_components
;
349 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
351 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
352 vec
->definitions
[0] = Definition(dst
);
354 for (unsigned i
= 0; i
< num_components
; i
++) {
355 if (mask
& (1 << i
)) {
356 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
357 if (dst
.type() == RegType::sgpr
)
358 src
= bld
.as_uniform(src
);
359 vec
->operands
[i
] = Operand(src
);
361 vec
->operands
[i
] = Operand(0u);
363 elems
[i
] = vec
->operands
[i
].getTemp();
365 ctx
->block
->instructions
.emplace_back(std::move(vec
));
366 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
369 /* adjust misaligned small bit size loads */
370 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
372 Builder
bld(ctx
->program
, ctx
->block
);
374 Temp select
= Temp();
375 if (offset
.isConstant()) {
376 assert(offset
.constantValue() && offset
.constantValue() < 4);
377 shift
= Operand(offset
.constantValue() * 8);
379 /* bit_offset = 8 * (offset & 0x3) */
380 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
381 select
= bld
.tmp(s1
);
382 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
385 if (vec
.size() == 1) {
386 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
387 } else if (vec
.size() == 2) {
388 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
389 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
391 emit_split_vector(ctx
, dst
, 2);
393 emit_extract_vector(ctx
, tmp
, 0, dst
);
394 } else if (vec
.size() == 4) {
395 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
396 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
397 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
398 if (select
!= Temp())
399 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
400 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
401 Temp mid
= bld
.tmp(s1
);
402 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
403 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
404 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
406 emit_split_vector(ctx
, dst
, 2);
410 /* this function trims subdword vectors:
411 * if dst is vgpr - split the src and create a shrunk version according to the mask.
412 * if dst is sgpr - split the src, but move the original to sgpr. */
413 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
415 assert(vec_src
.type() == RegType::vgpr
);
416 emit_split_vector(ctx
, vec_src
, num_components
);
418 Builder
bld(ctx
->program
, ctx
->block
);
419 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
420 unsigned component_size
= vec_src
.bytes() / num_components
;
421 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
424 for (unsigned i
= 0; i
< num_components
; i
++) {
426 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
429 if (dst
.type() == RegType::vgpr
) {
430 assert(dst
.bytes() == k
* component_size
);
431 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
432 for (unsigned i
= 0; i
< k
; i
++)
433 vec
->operands
[i
] = Operand(elems
[i
]);
434 vec
->definitions
[0] = Definition(dst
);
435 bld
.insert(std::move(vec
));
437 // TODO: alignbyte if mask doesn't start with 1?
439 assert(dst
.size() == vec_src
.size());
440 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
442 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
445 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
447 Builder
bld(ctx
->program
, ctx
->block
);
449 dst
= bld
.tmp(bld
.lm
);
451 assert(val
.regClass() == s1
);
452 assert(dst
.regClass() == bld
.lm
);
454 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
457 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
459 Builder
bld(ctx
->program
, ctx
->block
);
463 assert(val
.regClass() == bld
.lm
);
464 assert(dst
.regClass() == s1
);
466 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
467 Temp tmp
= bld
.tmp(s1
);
468 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
469 return emit_wqm(ctx
, tmp
, dst
);
472 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
474 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
475 return get_ssa_temp(ctx
, src
.src
.ssa
);
477 if (src
.src
.ssa
->num_components
== size
) {
478 bool identity_swizzle
= true;
479 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
480 if (src
.swizzle
[i
] != i
)
481 identity_swizzle
= false;
483 if (identity_swizzle
)
484 return get_ssa_temp(ctx
, src
.src
.ssa
);
487 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
488 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
489 assert(elem_size
> 0);
490 assert(vec
.bytes() % elem_size
== 0);
492 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
493 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
495 unsigned swizzle
= src
.swizzle
[0];
496 if (vec
.size() > 1) {
497 assert(src
.src
.ssa
->bit_size
== 16);
498 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
499 swizzle
= swizzle
& 1;
504 Temp dst
{ctx
->program
->allocateId(), s1
};
505 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
506 bfe
->operands
[0] = Operand(vec
);
507 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
508 bfe
->definitions
[0] = Definition(dst
);
509 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
510 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
514 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
516 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
519 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
520 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
521 for (unsigned i
= 0; i
< size
; ++i
) {
522 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
523 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
525 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
526 vec_instr
->definitions
[0] = Definition(dst
);
527 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
528 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
533 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
537 Builder
bld(ctx
->program
, ctx
->block
);
538 if (ptr
.type() == RegType::vgpr
)
539 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
540 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
541 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
544 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
546 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
547 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
548 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
549 sop2
->definitions
[0] = Definition(dst
);
551 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
552 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
555 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
556 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
558 Builder
bld(ctx
->program
, ctx
->block
);
559 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
560 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
561 if (src1
.type() == RegType::sgpr
) {
562 if (commutative
&& src0
.type() == RegType::vgpr
) {
567 src1
= as_vgpr(ctx
, src1
);
571 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
572 assert(dst
.size() == 1);
573 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
574 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
576 bld
.vop2(op
, Definition(dst
), src0
, src1
);
580 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
581 bool flush_denorms
= false)
583 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
584 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
585 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
587 /* ensure that the instruction has at most 1 sgpr operand
588 * The optimizer will inline constants for us */
589 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
590 src0
= as_vgpr(ctx
, src0
);
591 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
592 src1
= as_vgpr(ctx
, src1
);
593 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
594 src2
= as_vgpr(ctx
, src2
);
596 Builder
bld(ctx
->program
, ctx
->block
);
597 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
598 assert(dst
.size() == 1);
599 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
600 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
602 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
608 Builder
bld(ctx
->program
, ctx
->block
);
609 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
612 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
615 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
616 assert(src0
.size() == src1
.size());
618 aco_ptr
<Instruction
> vopc
;
619 if (src1
.type() == RegType::sgpr
) {
620 if (src0
.type() == RegType::vgpr
) {
621 /* to swap the operands, we might also have to change the opcode */
623 case aco_opcode::v_cmp_lt_f16
:
624 op
= aco_opcode::v_cmp_gt_f16
;
626 case aco_opcode::v_cmp_ge_f16
:
627 op
= aco_opcode::v_cmp_le_f16
;
629 case aco_opcode::v_cmp_lt_i16
:
630 op
= aco_opcode::v_cmp_gt_i16
;
632 case aco_opcode::v_cmp_ge_i16
:
633 op
= aco_opcode::v_cmp_le_i16
;
635 case aco_opcode::v_cmp_lt_u16
:
636 op
= aco_opcode::v_cmp_gt_u16
;
638 case aco_opcode::v_cmp_ge_u16
:
639 op
= aco_opcode::v_cmp_le_u16
;
641 case aco_opcode::v_cmp_lt_f32
:
642 op
= aco_opcode::v_cmp_gt_f32
;
644 case aco_opcode::v_cmp_ge_f32
:
645 op
= aco_opcode::v_cmp_le_f32
;
647 case aco_opcode::v_cmp_lt_i32
:
648 op
= aco_opcode::v_cmp_gt_i32
;
650 case aco_opcode::v_cmp_ge_i32
:
651 op
= aco_opcode::v_cmp_le_i32
;
653 case aco_opcode::v_cmp_lt_u32
:
654 op
= aco_opcode::v_cmp_gt_u32
;
656 case aco_opcode::v_cmp_ge_u32
:
657 op
= aco_opcode::v_cmp_le_u32
;
659 case aco_opcode::v_cmp_lt_f64
:
660 op
= aco_opcode::v_cmp_gt_f64
;
662 case aco_opcode::v_cmp_ge_f64
:
663 op
= aco_opcode::v_cmp_le_f64
;
665 case aco_opcode::v_cmp_lt_i64
:
666 op
= aco_opcode::v_cmp_gt_i64
;
668 case aco_opcode::v_cmp_ge_i64
:
669 op
= aco_opcode::v_cmp_le_i64
;
671 case aco_opcode::v_cmp_lt_u64
:
672 op
= aco_opcode::v_cmp_gt_u64
;
674 case aco_opcode::v_cmp_ge_u64
:
675 op
= aco_opcode::v_cmp_le_u64
;
677 default: /* eq and ne are commutative */
684 src1
= as_vgpr(ctx
, src1
);
688 Builder
bld(ctx
->program
, ctx
->block
);
689 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
692 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
694 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
695 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
696 Builder
bld(ctx
->program
, ctx
->block
);
698 assert(dst
.regClass() == bld
.lm
);
699 assert(src0
.type() == RegType::sgpr
);
700 assert(src1
.type() == RegType::sgpr
);
701 assert(src0
.regClass() == src1
.regClass());
703 /* Emit the SALU comparison instruction */
704 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
705 /* Turn the result into a per-lane bool */
706 bool_to_vector_condition(ctx
, cmp
, dst
);
709 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
710 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
712 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
713 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
714 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
715 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
717 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
718 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
719 aco_opcode op
= use_valu
? v_op
: s_op
;
720 assert(op
!= aco_opcode::num_opcodes
);
721 assert(dst
.regClass() == ctx
->program
->lane_mask
);
724 emit_vopc_instruction(ctx
, instr
, op
, dst
);
726 emit_sopc_instruction(ctx
, instr
, op
, dst
);
729 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
731 Builder
bld(ctx
->program
, ctx
->block
);
732 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
733 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
735 assert(dst
.regClass() == bld
.lm
);
736 assert(src0
.regClass() == bld
.lm
);
737 assert(src1
.regClass() == bld
.lm
);
739 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
742 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
744 Builder
bld(ctx
->program
, ctx
->block
);
745 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
746 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
747 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
749 assert(cond
.regClass() == bld
.lm
);
751 if (dst
.type() == RegType::vgpr
) {
752 aco_ptr
<Instruction
> bcsel
;
753 if (dst
.regClass() == v2b
) {
754 then
= as_vgpr(ctx
, then
);
755 els
= as_vgpr(ctx
, els
);
757 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
759 } else if (dst
.regClass() == v1
) {
760 then
= as_vgpr(ctx
, then
);
761 els
= as_vgpr(ctx
, els
);
763 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
764 } else if (dst
.regClass() == v2
) {
765 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
767 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
770 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
771 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
773 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
776 nir_print_instr(&instr
->instr
, stderr
);
777 fprintf(stderr
, "\n");
782 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
783 assert(dst
.regClass() == bld
.lm
);
784 assert(then
.regClass() == bld
.lm
);
785 assert(els
.regClass() == bld
.lm
);
788 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
789 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
790 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
791 assert(dst
.size() == then
.size());
792 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
793 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
795 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
796 nir_print_instr(&instr
->instr
, stderr
);
797 fprintf(stderr
, "\n");
802 /* divergent boolean bcsel
803 * this implements bcsel on bools: dst = s0 ? s1 : s2
804 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
805 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
807 if (cond
.id() != then
.id())
808 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
810 if (cond
.id() == els
.id())
811 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
813 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
814 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
817 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
818 aco_opcode op
, uint32_t undo
)
820 /* multiply by 16777216 to handle denormals */
821 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
822 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
823 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
824 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
825 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
827 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
829 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
832 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
834 if (ctx
->block
->fp_mode
.denorm32
== 0) {
835 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
839 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
842 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
844 if (ctx
->block
->fp_mode
.denorm32
== 0) {
845 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
849 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
852 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
854 if (ctx
->block
->fp_mode
.denorm32
== 0) {
855 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
859 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
862 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
864 if (ctx
->block
->fp_mode
.denorm32
== 0) {
865 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
869 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
872 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
874 if (ctx
->options
->chip_class
>= GFX7
)
875 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
877 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
878 /* TODO: create more efficient code! */
879 if (val
.type() == RegType::sgpr
)
880 val
= as_vgpr(ctx
, val
);
882 /* Split the input value. */
883 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
886 /* Extract the exponent and compute the unbiased value. */
887 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
889 /* Extract the fractional part. */
890 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
891 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
893 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
894 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
896 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
897 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
898 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
899 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
900 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
902 /* Get the sign bit. */
903 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
905 /* Decide the operation to apply depending on the unbiased exponent. */
906 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
907 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
908 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
909 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
910 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
911 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
913 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
916 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
918 if (ctx
->options
->chip_class
>= GFX7
)
919 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
921 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
922 Temp src0
= as_vgpr(ctx
, val
);
924 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
925 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
927 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
928 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
929 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
931 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
933 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
934 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
936 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
937 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
939 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
941 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
942 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
944 return add
->definitions
[0].getTemp();
947 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
949 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
950 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
952 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
955 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
956 return bld
.copy(Definition(dst
), src
);
957 else if (dst
.bytes() < src
.bytes())
958 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
962 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
965 } else if (src
.regClass() == s1
) {
967 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
969 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
971 assert(src_bits
!= 8 || src
.regClass() == v1b
);
972 assert(src_bits
!= 16 || src
.regClass() == v2b
);
973 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
974 sdwa
->operands
[0] = Operand(src
);
975 sdwa
->definitions
[0] = Definition(tmp
);
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
979 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
980 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
981 bld
.insert(std::move(sdwa
));
984 if (dst_bits
== 64) {
985 if (is_signed
&& dst
.regClass() == s2
) {
986 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
987 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
988 } else if (is_signed
&& dst
.regClass() == v2
) {
989 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
990 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
992 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
999 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1001 if (!instr
->dest
.dest
.is_ssa
) {
1002 fprintf(stderr
, "nir alu dst not in ssa: ");
1003 nir_print_instr(&instr
->instr
, stderr
);
1004 fprintf(stderr
, "\n");
1007 Builder
bld(ctx
->program
, ctx
->block
);
1008 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1013 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1014 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1015 for (unsigned i
= 0; i
< num
; ++i
)
1016 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1018 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1019 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1020 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1021 for (unsigned i
= 0; i
< num
; ++i
) {
1022 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1023 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1025 vec
->operands
[i
] = Operand
{elems
[i
]};
1027 vec
->definitions
[0] = Definition(dst
);
1028 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1029 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1031 // TODO: that is a bit suboptimal..
1032 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1033 for (unsigned i
= 0; i
< num
- 1; ++i
)
1034 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1035 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1036 for (unsigned i
= 0; i
< num
; ++i
) {
1037 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1038 if (bit
% 32 == 0) {
1039 elems
[bit
/ 32] = elems
[i
];
1041 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1042 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1043 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1046 if (dst
.size() == 1)
1047 bld
.copy(Definition(dst
), elems
[0]);
1049 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1054 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1055 aco_ptr
<Instruction
> mov
;
1056 if (dst
.type() == RegType::sgpr
) {
1057 if (src
.type() == RegType::vgpr
)
1058 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1059 else if (src
.regClass() == s1
)
1060 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1061 else if (src
.regClass() == s2
)
1062 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1064 unreachable("wrong src register class for nir_op_imov");
1065 } else if (dst
.regClass() == v1
) {
1066 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1067 } else if (dst
.regClass() == v2
) {
1068 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1070 nir_print_instr(&instr
->instr
, stderr
);
1071 unreachable("Should have been lowered to scalar.");
1076 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1077 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1078 assert(src
.regClass() == bld
.lm
);
1079 assert(dst
.regClass() == bld
.lm
);
1080 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1081 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1082 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1083 } else if (dst
.regClass() == v1
) {
1084 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1085 } else if (dst
.type() == RegType::sgpr
) {
1086 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1087 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1097 if (dst
.regClass() == v1
) {
1098 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1099 } else if (dst
.regClass() == s1
) {
1100 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1101 } else if (dst
.size() == 2) {
1102 Temp src0
= bld
.tmp(dst
.type(), 1);
1103 Temp src1
= bld
.tmp(dst
.type(), 1);
1104 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1106 if (dst
.regClass() == s2
) {
1107 Temp carry
= bld
.tmp(s1
);
1108 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1109 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1110 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1112 Temp lower
= bld
.tmp(v1
);
1113 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1114 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1115 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1118 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1119 nir_print_instr(&instr
->instr
, stderr
);
1120 fprintf(stderr
, "\n");
1125 if (dst
.regClass() == s1
) {
1126 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1127 } else if (dst
.regClass() == v1
) {
1128 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1129 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1131 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1132 nir_print_instr(&instr
->instr
, stderr
);
1133 fprintf(stderr
, "\n");
1137 case nir_op_isign
: {
1138 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1139 if (dst
.regClass() == s1
) {
1140 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1141 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1142 } else if (dst
.regClass() == s2
) {
1143 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1145 if (ctx
->program
->chip_class
>= GFX8
)
1146 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1148 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1149 /* SCC gets zero-extended to 64 bit */
1150 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1151 } else if (dst
.regClass() == v1
) {
1152 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1153 } else if (dst
.regClass() == v2
) {
1154 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1155 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1156 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1157 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1158 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1159 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (dst
.regClass() == v1
) {
1169 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1170 } else if (dst
.regClass() == s1
) {
1171 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1173 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1174 nir_print_instr(&instr
->instr
, stderr
);
1175 fprintf(stderr
, "\n");
1180 if (dst
.regClass() == v1
) {
1181 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1182 } else if (dst
.regClass() == s1
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1194 } else if (dst
.regClass() == s1
) {
1195 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1198 nir_print_instr(&instr
->instr
, stderr
);
1199 fprintf(stderr
, "\n");
1204 if (dst
.regClass() == v1
) {
1205 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1206 } else if (dst
.regClass() == s1
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1209 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1210 nir_print_instr(&instr
->instr
, stderr
);
1211 fprintf(stderr
, "\n");
1216 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1217 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1218 } else if (dst
.regClass() == v1
) {
1219 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1233 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1234 } else if (dst
.regClass() == v1
) {
1235 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1236 } else if (dst
.regClass() == s1
) {
1237 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1238 } else if (dst
.regClass() == s2
) {
1239 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1241 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1242 nir_print_instr(&instr
->instr
, stderr
);
1243 fprintf(stderr
, "\n");
1248 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1249 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1250 } else if (dst
.regClass() == v1
) {
1251 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1252 } else if (dst
.regClass() == s1
) {
1253 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1254 } else if (dst
.regClass() == s2
) {
1255 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1257 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1258 nir_print_instr(&instr
->instr
, stderr
);
1259 fprintf(stderr
, "\n");
1264 if (dst
.regClass() == v1
) {
1265 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1266 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1267 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1268 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1269 } else if (dst
.regClass() == v2
) {
1270 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1271 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1272 } else if (dst
.regClass() == s2
) {
1273 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1274 } else if (dst
.regClass() == s1
) {
1275 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1277 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1278 nir_print_instr(&instr
->instr
, stderr
);
1279 fprintf(stderr
, "\n");
1284 if (dst
.regClass() == v1
) {
1285 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1286 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1287 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1288 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1289 } else if (dst
.regClass() == v2
) {
1290 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1291 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1292 } else if (dst
.regClass() == s1
) {
1293 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1294 } else if (dst
.regClass() == s2
) {
1295 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1297 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1298 nir_print_instr(&instr
->instr
, stderr
);
1299 fprintf(stderr
, "\n");
1304 if (dst
.regClass() == v1
) {
1305 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1306 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1307 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1308 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1309 } else if (dst
.regClass() == v2
) {
1310 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1311 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1312 } else if (dst
.regClass() == s1
) {
1313 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1314 } else if (dst
.regClass() == s2
) {
1315 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1318 nir_print_instr(&instr
->instr
, stderr
);
1319 fprintf(stderr
, "\n");
1323 case nir_op_find_lsb
: {
1324 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1325 if (src
.regClass() == s1
) {
1326 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1327 } else if (src
.regClass() == v1
) {
1328 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1329 } else if (src
.regClass() == s2
) {
1330 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1332 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1333 nir_print_instr(&instr
->instr
, stderr
);
1334 fprintf(stderr
, "\n");
1338 case nir_op_ufind_msb
:
1339 case nir_op_ifind_msb
: {
1340 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1341 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1342 aco_opcode op
= src
.regClass() == s2
?
1343 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1344 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1345 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1347 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1348 Operand(src
.size() * 32u - 1u), msb_rev
);
1349 Temp msb
= sub
.def(0).getTemp();
1350 Temp carry
= sub
.def(1).getTemp();
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1353 } else if (src
.regClass() == v1
) {
1354 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1355 Temp msb_rev
= bld
.tmp(v1
);
1356 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1357 Temp msb
= bld
.tmp(v1
);
1358 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1359 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1361 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1362 nir_print_instr(&instr
->instr
, stderr
);
1363 fprintf(stderr
, "\n");
1367 case nir_op_bitfield_reverse
: {
1368 if (dst
.regClass() == s1
) {
1369 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1370 } else if (dst
.regClass() == v1
) {
1371 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1373 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1374 nir_print_instr(&instr
->instr
, stderr
);
1375 fprintf(stderr
, "\n");
1380 if (dst
.regClass() == s1
) {
1381 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1385 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1386 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1387 if (dst
.regClass() == v1
) {
1388 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1392 assert(src0
.size() == 2 && src1
.size() == 2);
1393 Temp src00
= bld
.tmp(src0
.type(), 1);
1394 Temp src01
= bld
.tmp(dst
.type(), 1);
1395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1396 Temp src10
= bld
.tmp(src1
.type(), 1);
1397 Temp src11
= bld
.tmp(dst
.type(), 1);
1398 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1400 if (dst
.regClass() == s2
) {
1401 Temp carry
= bld
.tmp(s1
);
1402 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1403 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1405 } else if (dst
.regClass() == v2
) {
1406 Temp dst0
= bld
.tmp(v1
);
1407 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1408 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1409 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1412 nir_print_instr(&instr
->instr
, stderr
);
1413 fprintf(stderr
, "\n");
1417 case nir_op_uadd_sat
: {
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == s1
) {
1421 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1422 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1424 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1425 } else if (dst
.regClass() == v1
) {
1426 if (ctx
->options
->chip_class
>= GFX9
) {
1427 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1428 add
->operands
[0] = Operand(src0
);
1429 add
->operands
[1] = Operand(src1
);
1430 add
->definitions
[0] = Definition(dst
);
1432 ctx
->block
->instructions
.emplace_back(std::move(add
));
1434 if (src1
.regClass() != v1
)
1435 std::swap(src0
, src1
);
1436 assert(src1
.regClass() == v1
);
1437 Temp tmp
= bld
.tmp(v1
);
1438 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1439 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_uadd_carry
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1455 if (dst
.regClass() == v1
) {
1456 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1457 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1461 Temp src00
= bld
.tmp(src0
.type(), 1);
1462 Temp src01
= bld
.tmp(dst
.type(), 1);
1463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1464 Temp src10
= bld
.tmp(src1
.type(), 1);
1465 Temp src11
= bld
.tmp(dst
.type(), 1);
1466 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1467 if (dst
.regClass() == s2
) {
1468 Temp carry
= bld
.tmp(s1
);
1469 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1470 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1471 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1472 } else if (dst
.regClass() == v2
) {
1473 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1474 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1475 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1476 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1478 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1479 nir_print_instr(&instr
->instr
, stderr
);
1480 fprintf(stderr
, "\n");
1485 if (dst
.regClass() == s1
) {
1486 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1490 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1491 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1492 if (dst
.regClass() == v1
) {
1493 bld
.vsub32(Definition(dst
), src0
, src1
);
1497 Temp src00
= bld
.tmp(src0
.type(), 1);
1498 Temp src01
= bld
.tmp(dst
.type(), 1);
1499 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1500 Temp src10
= bld
.tmp(src1
.type(), 1);
1501 Temp src11
= bld
.tmp(dst
.type(), 1);
1502 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1503 if (dst
.regClass() == s2
) {
1504 Temp carry
= bld
.tmp(s1
);
1505 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1506 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1507 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1508 } else if (dst
.regClass() == v2
) {
1509 Temp lower
= bld
.tmp(v1
);
1510 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1511 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1512 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1515 nir_print_instr(&instr
->instr
, stderr
);
1516 fprintf(stderr
, "\n");
1520 case nir_op_usub_borrow
: {
1521 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1522 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1523 if (dst
.regClass() == s1
) {
1524 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1526 } else if (dst
.regClass() == v1
) {
1527 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1528 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1532 Temp src00
= bld
.tmp(src0
.type(), 1);
1533 Temp src01
= bld
.tmp(dst
.type(), 1);
1534 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1535 Temp src10
= bld
.tmp(src1
.type(), 1);
1536 Temp src11
= bld
.tmp(dst
.type(), 1);
1537 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1538 if (dst
.regClass() == s2
) {
1539 Temp borrow
= bld
.tmp(s1
);
1540 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1541 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1543 } else if (dst
.regClass() == v2
) {
1544 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1545 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1546 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1547 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1549 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1550 nir_print_instr(&instr
->instr
, stderr
);
1551 fprintf(stderr
, "\n");
1556 if (dst
.regClass() == v1
) {
1557 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1558 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1559 } else if (dst
.regClass() == s1
) {
1560 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1563 nir_print_instr(&instr
->instr
, stderr
);
1564 fprintf(stderr
, "\n");
1568 case nir_op_umul_high
: {
1569 if (dst
.regClass() == v1
) {
1570 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1571 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1572 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1573 } else if (dst
.regClass() == s1
) {
1574 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1575 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1576 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1578 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1579 nir_print_instr(&instr
->instr
, stderr
);
1580 fprintf(stderr
, "\n");
1584 case nir_op_imul_high
: {
1585 if (dst
.regClass() == v1
) {
1586 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1587 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1588 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1589 } else if (dst
.regClass() == s1
) {
1590 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1591 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1592 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1594 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1595 nir_print_instr(&instr
->instr
, stderr
);
1596 fprintf(stderr
, "\n");
1601 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1602 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1603 if (dst
.regClass() == v2b
) {
1604 Temp tmp
= bld
.tmp(v1
);
1605 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1607 } else if (dst
.regClass() == v1
) {
1608 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1609 } else if (dst
.regClass() == v2
) {
1610 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1612 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1613 nir_print_instr(&instr
->instr
, stderr
);
1614 fprintf(stderr
, "\n");
1619 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1620 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1621 if (dst
.regClass() == v2b
) {
1622 Temp tmp
= bld
.tmp(v1
);
1623 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1624 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1625 } else if (dst
.regClass() == v1
) {
1626 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1627 } else if (dst
.regClass() == v2
) {
1628 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1630 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1631 nir_print_instr(&instr
->instr
, stderr
);
1632 fprintf(stderr
, "\n");
1637 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1638 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1639 if (dst
.regClass() == v2b
) {
1640 Temp tmp
= bld
.tmp(v1
);
1641 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1642 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1644 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1645 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1646 } else if (dst
.regClass() == v1
) {
1647 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1650 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1651 } else if (dst
.regClass() == v2
) {
1652 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1653 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1654 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1664 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1665 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1666 if (dst
.regClass() == v2b
) {
1667 // TODO: check fp_mode.must_flush_denorms16_64
1668 Temp tmp
= bld
.tmp(v1
);
1669 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1670 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1671 } else if (dst
.regClass() == v1
) {
1672 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1673 } else if (dst
.regClass() == v2
) {
1674 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1675 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1676 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1678 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1681 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1682 nir_print_instr(&instr
->instr
, stderr
);
1683 fprintf(stderr
, "\n");
1688 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1689 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1690 if (dst
.regClass() == v2b
) {
1691 // TODO: check fp_mode.must_flush_denorms16_64
1692 Temp tmp
= bld
.tmp(v1
);
1693 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1694 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1695 } else if (dst
.regClass() == v1
) {
1696 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1697 } else if (dst
.regClass() == v2
) {
1698 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1699 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1700 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1702 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1705 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1706 nir_print_instr(&instr
->instr
, stderr
);
1707 fprintf(stderr
, "\n");
1711 case nir_op_fmax3
: {
1712 if (dst
.regClass() == v2b
) {
1713 Temp tmp
= bld
.tmp(v1
);
1714 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1716 } else if (dst
.regClass() == v1
) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_fmin3
: {
1726 if (dst
.regClass() == v2b
) {
1727 Temp tmp
= bld
.tmp(v1
);
1728 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1729 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1730 } else if (dst
.regClass() == v1
) {
1731 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1733 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1734 nir_print_instr(&instr
->instr
, stderr
);
1735 fprintf(stderr
, "\n");
1739 case nir_op_fmed3
: {
1740 if (dst
.regClass() == v2b
) {
1741 Temp tmp
= bld
.tmp(v1
);
1742 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1743 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1744 } else if (dst
.regClass() == v1
) {
1745 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1748 nir_print_instr(&instr
->instr
, stderr
);
1749 fprintf(stderr
, "\n");
1753 case nir_op_umax3
: {
1754 if (dst
.size() == 1) {
1755 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1758 nir_print_instr(&instr
->instr
, stderr
);
1759 fprintf(stderr
, "\n");
1763 case nir_op_umin3
: {
1764 if (dst
.size() == 1) {
1765 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1768 nir_print_instr(&instr
->instr
, stderr
);
1769 fprintf(stderr
, "\n");
1773 case nir_op_umed3
: {
1774 if (dst
.size() == 1) {
1775 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1777 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1778 nir_print_instr(&instr
->instr
, stderr
);
1779 fprintf(stderr
, "\n");
1783 case nir_op_imax3
: {
1784 if (dst
.size() == 1) {
1785 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1793 case nir_op_imin3
: {
1794 if (dst
.size() == 1) {
1795 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1797 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1798 nir_print_instr(&instr
->instr
, stderr
);
1799 fprintf(stderr
, "\n");
1803 case nir_op_imed3
: {
1804 if (dst
.size() == 1) {
1805 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1807 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1808 nir_print_instr(&instr
->instr
, stderr
);
1809 fprintf(stderr
, "\n");
1813 case nir_op_cube_face_coord
: {
1814 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1815 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1816 emit_extract_vector(ctx
, in
, 1, v1
),
1817 emit_extract_vector(ctx
, in
, 2, v1
) };
1818 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1819 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1820 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1821 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1822 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1823 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1824 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1827 case nir_op_cube_face_index
: {
1828 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1829 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1830 emit_extract_vector(ctx
, in
, 1, v1
),
1831 emit_extract_vector(ctx
, in
, 2, v1
) };
1832 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1835 case nir_op_bcsel
: {
1836 emit_bcsel(ctx
, instr
, dst
);
1840 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1841 if (dst
.regClass() == v2b
) {
1842 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1844 } else if (dst
.regClass() == v1
) {
1845 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1846 } else if (dst
.regClass() == v2
) {
1847 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1849 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1850 nir_print_instr(&instr
->instr
, stderr
);
1851 fprintf(stderr
, "\n");
1856 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1857 if (dst
.regClass() == v2b
) {
1858 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1859 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1860 } else if (dst
.regClass() == v1
) {
1861 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1862 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1863 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1864 } else if (dst
.regClass() == v2
) {
1865 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1866 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1867 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1868 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1869 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1870 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1873 nir_print_instr(&instr
->instr
, stderr
);
1874 fprintf(stderr
, "\n");
1879 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1880 if (dst
.regClass() == v2b
) {
1881 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1883 } else if (dst
.regClass() == v1
) {
1884 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1885 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1886 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1887 } else if (dst
.regClass() == v2
) {
1888 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1889 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1890 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1892 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1893 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1895 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1896 nir_print_instr(&instr
->instr
, stderr
);
1897 fprintf(stderr
, "\n");
1902 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1903 if (dst
.regClass() == v2b
) {
1904 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1905 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1906 } else if (dst
.regClass() == v1
) {
1907 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1908 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1909 // TODO: confirm that this holds under any circumstances
1910 } else if (dst
.regClass() == v2
) {
1911 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1912 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1915 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1916 nir_print_instr(&instr
->instr
, stderr
);
1917 fprintf(stderr
, "\n");
1921 case nir_op_flog2
: {
1922 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1923 if (dst
.regClass() == v2b
) {
1924 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1925 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1926 } else if (dst
.regClass() == v1
) {
1927 emit_log2(ctx
, bld
, Definition(dst
), src
);
1929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1930 nir_print_instr(&instr
->instr
, stderr
);
1931 fprintf(stderr
, "\n");
1936 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1937 if (dst
.regClass() == v2b
) {
1938 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1939 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1940 } else if (dst
.regClass() == v1
) {
1941 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1942 } else if (dst
.regClass() == v2
) {
1943 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1945 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1946 nir_print_instr(&instr
->instr
, stderr
);
1947 fprintf(stderr
, "\n");
1951 case nir_op_fexp2
: {
1952 if (dst
.regClass() == v2b
) {
1953 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1954 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1956 } else if (dst
.regClass() == v1
) {
1957 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_fsqrt
: {
1966 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1972 } else if (dst
.regClass() == v2
) {
1973 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1975 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1976 nir_print_instr(&instr
->instr
, stderr
);
1977 fprintf(stderr
, "\n");
1981 case nir_op_ffract
: {
1982 if (dst
.regClass() == v2b
) {
1983 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1984 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1985 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1986 } else if (dst
.regClass() == v1
) {
1987 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1988 } else if (dst
.regClass() == v2
) {
1989 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1991 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1992 nir_print_instr(&instr
->instr
, stderr
);
1993 fprintf(stderr
, "\n");
1997 case nir_op_ffloor
: {
1998 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1999 if (dst
.regClass() == v2b
) {
2000 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
2001 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2002 } else if (dst
.regClass() == v1
) {
2003 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2004 } else if (dst
.regClass() == v2
) {
2005 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2007 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2008 nir_print_instr(&instr
->instr
, stderr
);
2009 fprintf(stderr
, "\n");
2013 case nir_op_fceil
: {
2014 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2015 if (dst
.regClass() == v2b
) {
2016 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
2017 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2018 } else if (dst
.regClass() == v1
) {
2019 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2020 } else if (dst
.regClass() == v2
) {
2021 if (ctx
->options
->chip_class
>= GFX7
) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2024 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2025 /* trunc = trunc(src0)
2026 * if (src0 > 0.0 && src0 != trunc)
2029 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2030 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2031 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2032 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2033 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2034 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2035 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2039 nir_print_instr(&instr
->instr
, stderr
);
2040 fprintf(stderr
, "\n");
2044 case nir_op_ftrunc
: {
2045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2046 if (dst
.regClass() == v2b
) {
2047 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2048 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2049 } else if (dst
.regClass() == v1
) {
2050 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2051 } else if (dst
.regClass() == v2
) {
2052 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2054 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2055 nir_print_instr(&instr
->instr
, stderr
);
2056 fprintf(stderr
, "\n");
2060 case nir_op_fround_even
: {
2061 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2062 if (dst
.regClass() == v2b
) {
2063 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2064 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2065 } else if (dst
.regClass() == v1
) {
2066 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2067 } else if (dst
.regClass() == v2
) {
2068 if (ctx
->options
->chip_class
>= GFX7
) {
2069 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2071 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2072 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2073 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2075 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2076 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2077 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2078 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2079 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2080 tmp
= sub
->definitions
[0].getTemp();
2082 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2083 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2084 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2085 Temp cond
= vop3
->definitions
[0].getTemp();
2087 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2088 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2089 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2090 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2092 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2095 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2096 nir_print_instr(&instr
->instr
, stderr
);
2097 fprintf(stderr
, "\n");
2103 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2104 aco_ptr
<Instruction
> norm
;
2105 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2106 if (dst
.regClass() == v2b
) {
2107 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2108 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2109 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2110 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2111 } else if (dst
.regClass() == v1
) {
2112 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2114 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2115 if (ctx
->options
->chip_class
< GFX9
)
2116 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2118 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2119 bld
.vop1(opcode
, Definition(dst
), tmp
);
2121 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2122 nir_print_instr(&instr
->instr
, stderr
);
2123 fprintf(stderr
, "\n");
2127 case nir_op_ldexp
: {
2128 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2129 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2130 if (dst
.regClass() == v2b
) {
2131 Temp tmp
= bld
.tmp(v1
);
2132 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2133 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2134 } else if (dst
.regClass() == v1
) {
2135 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2136 } else if (dst
.regClass() == v2
) {
2137 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2139 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2140 nir_print_instr(&instr
->instr
, stderr
);
2141 fprintf(stderr
, "\n");
2145 case nir_op_frexp_sig
: {
2146 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2147 if (dst
.regClass() == v2b
) {
2148 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2149 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2150 } else if (dst
.regClass() == v1
) {
2151 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2152 } else if (dst
.regClass() == v2
) {
2153 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2161 case nir_op_frexp_exp
: {
2162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2163 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2164 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2165 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2166 convert_int(bld
, tmp
, 8, 32, true, dst
);
2167 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2168 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2169 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2170 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2172 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2173 nir_print_instr(&instr
->instr
, stderr
);
2174 fprintf(stderr
, "\n");
2178 case nir_op_fsign
: {
2179 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2180 if (dst
.regClass() == v2b
) {
2181 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2182 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2183 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2184 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2185 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2186 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2187 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2188 } else if (dst
.regClass() == v1
) {
2189 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2190 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2191 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2193 } else if (dst
.regClass() == v2
) {
2194 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2195 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2196 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2198 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2199 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2200 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2202 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2204 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2205 nir_print_instr(&instr
->instr
, stderr
);
2206 fprintf(stderr
, "\n");
2211 case nir_op_f2f16_rtne
: {
2212 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2213 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2214 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2215 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2219 case nir_op_f2f16_rtz
: {
2220 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2221 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2222 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2223 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2224 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2227 case nir_op_f2f32
: {
2228 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2229 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2230 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2231 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2233 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2234 nir_print_instr(&instr
->instr
, stderr
);
2235 fprintf(stderr
, "\n");
2239 case nir_op_f2f64
: {
2240 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2241 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2242 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2243 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2246 case nir_op_i2f16
: {
2247 assert(dst
.regClass() == v2b
);
2248 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2249 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2250 src
= convert_int(bld
, src
, 8, 16, true);
2251 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
), src
);
2252 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2255 case nir_op_i2f32
: {
2256 assert(dst
.size() == 1);
2257 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2258 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2259 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2260 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2263 case nir_op_i2f64
: {
2264 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2265 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2266 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2267 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2268 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2269 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2270 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2271 RegClass rc
= RegClass(src
.type(), 1);
2272 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2273 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2274 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2275 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2276 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2277 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2280 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2281 nir_print_instr(&instr
->instr
, stderr
);
2282 fprintf(stderr
, "\n");
2286 case nir_op_u2f16
: {
2287 assert(dst
.regClass() == v2b
);
2288 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2289 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2290 src
= convert_int(bld
, src
, 8, 16, false);
2291 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
), src
);
2292 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2295 case nir_op_u2f32
: {
2296 assert(dst
.size() == 1);
2297 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2298 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2299 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2300 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2302 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2303 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2304 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2308 case nir_op_u2f64
: {
2309 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2310 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2311 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2312 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2313 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2314 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2315 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2316 RegClass rc
= RegClass(src
.type(), 1);
2317 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2318 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2319 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2320 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2321 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2322 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2324 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2325 nir_print_instr(&instr
->instr
, stderr
);
2326 fprintf(stderr
, "\n");
2331 case nir_op_f2i16
: {
2332 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2333 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2334 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2335 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2336 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2338 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2340 if (dst
.type() == RegType::vgpr
)
2341 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2343 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2347 case nir_op_f2u16
: {
2348 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2349 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2350 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2351 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2352 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2354 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2356 if (dst
.type() == RegType::vgpr
)
2357 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2359 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2362 case nir_op_f2i32
: {
2363 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2364 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2365 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2366 if (dst
.type() == RegType::vgpr
) {
2367 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2369 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2370 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2372 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2373 if (dst
.type() == RegType::vgpr
)
2374 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2376 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2377 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2379 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2380 if (dst
.type() == RegType::vgpr
)
2381 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2383 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2384 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2387 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2388 nir_print_instr(&instr
->instr
, stderr
);
2389 fprintf(stderr
, "\n");
2393 case nir_op_f2u32
: {
2394 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2395 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2396 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2397 if (dst
.type() == RegType::vgpr
) {
2398 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2400 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2401 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2403 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2404 if (dst
.type() == RegType::vgpr
)
2405 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2407 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2408 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2410 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2411 if (dst
.type() == RegType::vgpr
)
2412 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2414 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2415 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2418 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2419 nir_print_instr(&instr
->instr
, stderr
);
2420 fprintf(stderr
, "\n");
2424 case nir_op_f2i64
: {
2425 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2426 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2427 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2429 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2430 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2431 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2432 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2433 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2434 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2435 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2436 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2437 Temp new_exponent
= bld
.tmp(v1
);
2438 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2439 if (ctx
->program
->chip_class
>= GFX8
)
2440 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2442 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2443 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2444 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2445 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2446 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2447 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2448 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2449 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2450 Temp new_lower
= bld
.tmp(v1
);
2451 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2452 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2453 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2455 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2456 if (src
.type() == RegType::vgpr
)
2457 src
= bld
.as_uniform(src
);
2458 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2459 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2460 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2461 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2462 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2463 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2464 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2465 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2466 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2467 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2468 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2469 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2470 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2471 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2472 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2473 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2474 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2475 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2476 Temp borrow
= bld
.tmp(s1
);
2477 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2478 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2479 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2481 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2482 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2483 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2484 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2485 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2486 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2487 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2488 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2489 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2490 if (dst
.type() == RegType::sgpr
) {
2491 lower
= bld
.as_uniform(lower
);
2492 upper
= bld
.as_uniform(upper
);
2494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2497 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2498 nir_print_instr(&instr
->instr
, stderr
);
2499 fprintf(stderr
, "\n");
2503 case nir_op_f2u64
: {
2504 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2505 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2506 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2508 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2509 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2510 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2511 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2512 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2513 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2514 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2515 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2516 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2517 Temp new_exponent
= bld
.tmp(v1
);
2518 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2519 if (ctx
->program
->chip_class
>= GFX8
)
2520 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2522 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2523 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2524 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2525 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2526 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2527 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2528 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2529 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2531 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2532 if (src
.type() == RegType::vgpr
)
2533 src
= bld
.as_uniform(src
);
2534 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2535 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2536 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2537 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2538 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2539 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2540 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2541 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2542 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2543 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2544 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2545 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2546 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2547 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2548 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2549 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2550 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2551 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2553 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2554 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2555 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2556 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2557 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2558 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2559 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2560 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2561 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2562 if (dst
.type() == RegType::sgpr
) {
2563 lower
= bld
.as_uniform(lower
);
2564 upper
= bld
.as_uniform(upper
);
2566 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2569 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2570 nir_print_instr(&instr
->instr
, stderr
);
2571 fprintf(stderr
, "\n");
2575 case nir_op_b2f16
: {
2576 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2577 assert(src
.regClass() == bld
.lm
);
2579 if (dst
.regClass() == s1
) {
2580 src
= bool_to_scalar_condition(ctx
, src
);
2581 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2582 } else if (dst
.regClass() == v2b
) {
2583 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2584 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2585 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2587 unreachable("Wrong destination register class for nir_op_b2f16.");
2591 case nir_op_b2f32
: {
2592 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2593 assert(src
.regClass() == bld
.lm
);
2595 if (dst
.regClass() == s1
) {
2596 src
= bool_to_scalar_condition(ctx
, src
);
2597 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2598 } else if (dst
.regClass() == v1
) {
2599 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2601 unreachable("Wrong destination register class for nir_op_b2f32.");
2605 case nir_op_b2f64
: {
2606 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2607 assert(src
.regClass() == bld
.lm
);
2609 if (dst
.regClass() == s2
) {
2610 src
= bool_to_scalar_condition(ctx
, src
);
2611 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2612 } else if (dst
.regClass() == v2
) {
2613 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2614 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2615 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2617 unreachable("Wrong destination register class for nir_op_b2f64.");
2624 case nir_op_i2i64
: {
2625 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2626 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2632 case nir_op_u2u64
: {
2633 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2634 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2638 case nir_op_b2i32
: {
2639 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2640 assert(src
.regClass() == bld
.lm
);
2642 if (dst
.regClass() == s1
) {
2643 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2644 bool_to_scalar_condition(ctx
, src
, dst
);
2645 } else if (dst
.regClass() == v1
) {
2646 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2648 unreachable("Invalid register class for b2i32");
2654 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2655 assert(dst
.regClass() == bld
.lm
);
2657 if (src
.type() == RegType::vgpr
) {
2658 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2659 assert(dst
.regClass() == bld
.lm
);
2660 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2661 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2663 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2665 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2666 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2668 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2669 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2671 bool_to_vector_condition(ctx
, tmp
, dst
);
2675 case nir_op_pack_64_2x32_split
: {
2676 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2677 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2679 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2682 case nir_op_unpack_64_2x32_split_x
:
2683 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2685 case nir_op_unpack_64_2x32_split_y
:
2686 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2688 case nir_op_unpack_32_2x16_split_x
:
2689 if (dst
.type() == RegType::vgpr
) {
2690 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2692 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2695 case nir_op_unpack_32_2x16_split_y
:
2696 if (dst
.type() == RegType::vgpr
) {
2697 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2699 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2702 case nir_op_pack_32_2x16_split
: {
2703 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2704 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2705 if (dst
.regClass() == v1
) {
2706 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2707 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2708 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2710 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2711 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2712 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2716 case nir_op_pack_half_2x16
: {
2717 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2719 if (dst
.regClass() == v1
) {
2720 Temp src0
= bld
.tmp(v1
);
2721 Temp src1
= bld
.tmp(v1
);
2722 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2723 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2724 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2726 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2727 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2728 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2730 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2731 nir_print_instr(&instr
->instr
, stderr
);
2732 fprintf(stderr
, "\n");
2736 case nir_op_unpack_half_2x16_split_x
: {
2737 if (dst
.regClass() == v1
) {
2738 Builder
bld(ctx
->program
, ctx
->block
);
2739 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2742 nir_print_instr(&instr
->instr
, stderr
);
2743 fprintf(stderr
, "\n");
2747 case nir_op_unpack_half_2x16_split_y
: {
2748 if (dst
.regClass() == v1
) {
2749 Builder
bld(ctx
->program
, ctx
->block
);
2750 /* TODO: use SDWA here */
2751 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2752 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2754 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2755 nir_print_instr(&instr
->instr
, stderr
);
2756 fprintf(stderr
, "\n");
2760 case nir_op_fquantize2f16
: {
2761 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2762 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2765 if (ctx
->program
->chip_class
>= GFX8
) {
2766 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2767 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2768 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2770 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2771 * so compare the result and flush to 0 if it's smaller.
2773 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2774 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2775 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2776 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2777 cmp_res
= vop3
->definitions
[0].getTemp();
2780 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2781 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2782 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2784 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2789 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2790 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2792 if (dst
.regClass() == s1
) {
2793 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2794 } else if (dst
.regClass() == v1
) {
2795 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2797 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2798 nir_print_instr(&instr
->instr
, stderr
);
2799 fprintf(stderr
, "\n");
2803 case nir_op_bitfield_select
: {
2804 /* (mask & insert) | (~mask & base) */
2805 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2806 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2807 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2809 /* dst = (insert & bitmask) | (base & ~bitmask) */
2810 if (dst
.regClass() == s1
) {
2811 aco_ptr
<Instruction
> sop2
;
2812 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2813 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2815 if (const_insert
&& const_bitmask
) {
2816 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2818 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2819 lhs
= Operand(insert
);
2823 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2824 if (const_base
&& const_bitmask
) {
2825 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2827 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2828 rhs
= Operand(base
);
2831 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2833 } else if (dst
.regClass() == v1
) {
2834 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2835 base
= as_vgpr(ctx
, base
);
2836 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2837 insert
= as_vgpr(ctx
, insert
);
2839 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2843 nir_print_instr(&instr
->instr
, stderr
);
2844 fprintf(stderr
, "\n");
2850 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2851 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2852 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2854 if (dst
.type() == RegType::sgpr
) {
2856 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2857 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2858 if (const_offset
&& const_bits
) {
2859 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2860 extract
= Operand(const_extract
);
2864 width
= Operand(const_bits
->u32
<< 16);
2866 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2868 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2872 if (dst
.regClass() == s1
) {
2873 if (instr
->op
== nir_op_ubfe
)
2874 opcode
= aco_opcode::s_bfe_u32
;
2876 opcode
= aco_opcode::s_bfe_i32
;
2877 } else if (dst
.regClass() == s2
) {
2878 if (instr
->op
== nir_op_ubfe
)
2879 opcode
= aco_opcode::s_bfe_u64
;
2881 opcode
= aco_opcode::s_bfe_i64
;
2883 unreachable("Unsupported BFE bit size");
2886 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2890 if (dst
.regClass() == v1
) {
2891 if (instr
->op
== nir_op_ubfe
)
2892 opcode
= aco_opcode::v_bfe_u32
;
2894 opcode
= aco_opcode::v_bfe_i32
;
2896 unreachable("Unsupported BFE bit size");
2899 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2903 case nir_op_bit_count
: {
2904 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2905 if (src
.regClass() == s1
) {
2906 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2907 } else if (src
.regClass() == v1
) {
2908 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2909 } else if (src
.regClass() == v2
) {
2910 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2911 emit_extract_vector(ctx
, src
, 1, v1
),
2912 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2913 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2914 } else if (src
.regClass() == s2
) {
2915 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2917 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2918 nir_print_instr(&instr
->instr
, stderr
);
2919 fprintf(stderr
, "\n");
2924 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2928 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2932 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2936 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2940 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2948 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2949 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2951 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2952 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2956 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2957 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2959 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2960 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2964 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2968 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2973 case nir_op_fddx_fine
:
2974 case nir_op_fddy_fine
:
2975 case nir_op_fddx_coarse
:
2976 case nir_op_fddy_coarse
: {
2977 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2978 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2979 if (instr
->op
== nir_op_fddx_fine
) {
2980 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2981 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2982 } else if (instr
->op
== nir_op_fddy_fine
) {
2983 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2984 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2986 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2987 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2988 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2990 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2994 if (ctx
->program
->chip_class
>= GFX8
) {
2995 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2996 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2998 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2999 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3000 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3002 emit_wqm(ctx
, tmp
, dst
, true);
3006 fprintf(stderr
, "Unknown NIR ALU instr: ");
3007 nir_print_instr(&instr
->instr
, stderr
);
3008 fprintf(stderr
, "\n");
3012 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3014 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3016 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3017 // which get truncated the lsb if double and msb if int
3018 // for now, we only use s_mov_b64 with 64bit inline constants
3019 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3020 assert(dst
.type() == RegType::sgpr
);
3022 Builder
bld(ctx
->program
, ctx
->block
);
3024 if (instr
->def
.bit_size
== 1) {
3025 assert(dst
.regClass() == bld
.lm
);
3026 int val
= instr
->value
[0].b
? -1 : 0;
3027 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3028 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3029 } else if (instr
->def
.bit_size
== 8) {
3030 /* ensure that the value is correctly represented in the low byte of the register */
3031 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3032 } else if (instr
->def
.bit_size
== 16) {
3033 /* ensure that the value is correctly represented in the low half of the register */
3034 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3035 } else if (dst
.size() == 1) {
3036 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3038 assert(dst
.size() != 1);
3039 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3040 if (instr
->def
.bit_size
== 64)
3041 for (unsigned i
= 0; i
< dst
.size(); i
++)
3042 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3044 for (unsigned i
= 0; i
< dst
.size(); i
++)
3045 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3047 vec
->definitions
[0] = Definition(dst
);
3048 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3052 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3054 uint32_t new_mask
= 0;
3055 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3056 if (mask
& (1u << i
))
3057 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3061 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3063 Builder
bld(ctx
->program
, ctx
->block
);
3064 if (offset
.isTemp()) {
3065 Temp tmp
[3] = {vec
, vec
, vec
};
3067 if (vec
.size() == 3) {
3068 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3069 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3070 } else if (vec
.size() == 2) {
3071 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3072 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3074 for (unsigned i
= 0; i
< dst
.size(); i
++)
3075 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3078 if (dst
.size() == 2)
3079 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3081 offset
= Operand(0u);
3084 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3085 bld
.copy(Definition(dst
), vec
);
3087 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3090 struct LoadEmitInfo
{
3093 unsigned num_components
;
3094 unsigned component_size
;
3095 Temp resource
= Temp(0, s1
);
3096 unsigned component_stride
= 0;
3097 unsigned const_offset
= 0;
3098 unsigned align_mul
= 0;
3099 unsigned align_offset
= 0;
3102 unsigned swizzle_component_size
= 0;
3103 barrier_interaction barrier
= barrier_none
;
3104 bool can_reorder
= true;
3105 Temp soffset
= Temp(0, s1
);
3108 using LoadCallback
= Temp(*)(
3109 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3110 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3112 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3113 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3115 unsigned load_size
= info
->num_components
* info
->component_size
;
3116 unsigned component_size
= info
->component_size
;
3118 unsigned num_vals
= 0;
3119 Temp vals
[info
->dst
.bytes()];
3121 unsigned const_offset
= info
->const_offset
;
3123 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3124 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3126 unsigned bytes_read
= 0;
3127 while (bytes_read
< load_size
) {
3128 unsigned bytes_needed
= load_size
- bytes_read
;
3130 /* add buffer for unaligned loads */
3131 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3134 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3135 if (info
->component_stride
) {
3136 assert(supports_8bit_16bit_loads
&& "unimplemented");
3140 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3141 bytes_needed
= align(bytes_needed
, 4);
3148 if (info
->swizzle_component_size
)
3149 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3150 if (info
->component_stride
)
3151 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3153 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3155 /* reduce constant offset */
3156 Operand offset
= info
->offset
;
3157 unsigned reduced_const_offset
= const_offset
;
3158 bool remove_const_offset_completely
= need_to_align_offset
;
3159 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3160 unsigned to_add
= const_offset
;
3161 if (remove_const_offset_completely
) {
3162 reduced_const_offset
= 0;
3164 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3165 reduced_const_offset
%= max_const_offset_plus_one
;
3167 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3168 if (offset
.isConstant()) {
3169 offset
= Operand(offset
.constantValue() + to_add
);
3170 } else if (offset_tmp
.regClass() == s1
) {
3171 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3172 offset_tmp
, Operand(to_add
));
3173 } else if (offset_tmp
.regClass() == v1
) {
3174 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3176 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3177 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3178 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3180 if (offset_tmp
.regClass() == s2
) {
3181 Temp carry
= bld
.tmp(s1
);
3182 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3183 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3184 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3186 Temp new_lo
= bld
.tmp(v1
);
3187 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3188 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3189 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3194 /* align offset down if needed */
3195 Operand aligned_offset
= offset
;
3196 if (need_to_align_offset
) {
3197 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3198 if (offset
.isConstant()) {
3199 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3200 } else if (offset_tmp
.regClass() == s1
) {
3201 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3202 } else if (offset_tmp
.regClass() == s2
) {
3203 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3204 } else if (offset_tmp
.regClass() == v1
) {
3205 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3206 } else if (offset_tmp
.regClass() == v2
) {
3207 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3208 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3209 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3210 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3213 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3214 bld
.copy(bld
.def(s1
), aligned_offset
);
3216 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3217 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3218 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3220 /* shift result right if needed */
3222 Operand
align((uint32_t)byte_align
);
3223 if (byte_align
== -1) {
3224 if (offset
.isConstant())
3225 align
= Operand(offset
.constantValue() % 4u);
3226 else if (offset
.size() == 2)
3227 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3232 if (align
.isTemp() || align
.constantValue()) {
3233 assert(val
.bytes() >= load_size
&& "unimplemented");
3234 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3235 if (val
.type() == RegType::sgpr
)
3236 byte_align_scalar(ctx
, val
, align
, new_val
);
3238 byte_align_vector(ctx
, val
, align
, new_val
);
3243 /* add result to list and advance */
3244 if (info
->component_stride
) {
3245 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3246 const_offset
+= info
->component_stride
;
3247 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3249 const_offset
+= val
.bytes();
3250 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3252 bytes_read
+= val
.bytes();
3253 vals
[num_vals
++] = val
;
3256 /* the callback wrote directly to dst */
3257 if (vals
[0] == info
->dst
) {
3258 assert(num_vals
== 1);
3259 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3263 /* create array of components */
3264 unsigned components_split
= 0;
3265 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3266 bool has_vgprs
= false;
3267 for (unsigned i
= 0; i
< num_vals
;) {
3269 unsigned num_tmps
= 0;
3270 unsigned tmp_size
= 0;
3271 RegType reg_type
= RegType::sgpr
;
3272 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3273 if (vals
[i
].type() == RegType::vgpr
)
3274 reg_type
= RegType::vgpr
;
3275 tmp_size
+= vals
[i
].bytes();
3276 tmp
[num_tmps
++] = vals
[i
++];
3279 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3280 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3281 for (unsigned i
= 0; i
< num_vals
; i
++)
3282 vec
->operands
[i
] = Operand(tmp
[i
]);
3283 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3284 vec
->definitions
[0] = Definition(tmp
[0]);
3285 bld
.insert(std::move(vec
));
3288 if (tmp
[0].bytes() % component_size
) {
3290 assert(i
== num_vals
);
3291 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3292 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3295 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3297 unsigned start
= components_split
;
3299 if (tmp_size
== elem_rc
.bytes()) {
3300 allocated_vec
[components_split
++] = tmp
[0];
3302 assert(tmp_size
% elem_rc
.bytes() == 0);
3303 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3304 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3305 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3306 Temp component
= bld
.tmp(elem_rc
);
3307 allocated_vec
[components_split
++] = component
;
3308 split
->definitions
[i
] = Definition(component
);
3310 split
->operands
[0] = Operand(tmp
[0]);
3311 bld
.insert(std::move(split
));
3314 /* try to p_as_uniform early so we can create more optimizable code and
3315 * also update allocated_vec */
3316 for (unsigned j
= start
; j
< components_split
; j
++) {
3317 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3318 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3319 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3323 /* concatenate components and p_as_uniform() result if needed */
3324 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3325 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3327 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3329 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3330 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3331 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3332 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3334 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3335 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3336 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3337 vec
->definitions
[0] = Definition(tmp
);
3338 bld
.insert(std::move(vec
));
3339 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3341 vec
->definitions
[0] = Definition(info
->dst
);
3342 bld
.insert(std::move(vec
));
3346 Operand
load_lds_size_m0(Builder
& bld
)
3348 /* TODO: m0 does not need to be initialized on GFX9+ */
3349 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3352 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3353 Temp offset
, unsigned bytes_needed
,
3354 unsigned align
, unsigned const_offset
,
3357 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3359 Operand m
= load_lds_size_m0(bld
);
3361 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3362 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3367 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3368 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3370 op
= aco_opcode::ds_read_b128
;
3371 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3374 op
= aco_opcode::ds_read2_b64
;
3375 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3377 op
= aco_opcode::ds_read_b96
;
3378 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3380 op
= aco_opcode::ds_read_b64
;
3381 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3384 op
= aco_opcode::ds_read2_b32
;
3385 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3387 op
= aco_opcode::ds_read_b32
;
3388 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3390 op
= aco_opcode::ds_read_u16
;
3393 op
= aco_opcode::ds_read_u8
;
3396 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3397 if (const_offset
>= max_offset_plus_one
) {
3398 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3399 const_offset
%= max_offset_plus_one
;
3403 const_offset
/= (size
/ 2u);
3405 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3406 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3408 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3410 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3413 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3418 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3420 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3421 Temp offset
, unsigned bytes_needed
,
3422 unsigned align
, unsigned const_offset
,
3427 if (bytes_needed
<= 4) {
3429 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3430 } else if (bytes_needed
<= 8) {
3432 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3433 } else if (bytes_needed
<= 16) {
3435 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3436 } else if (bytes_needed
<= 32) {
3438 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3441 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3443 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3444 if (info
->resource
.id()) {
3445 load
->operands
[0] = Operand(info
->resource
);
3446 load
->operands
[1] = Operand(offset
);
3448 load
->operands
[0] = Operand(offset
);
3449 load
->operands
[1] = Operand(0u);
3451 RegClass
rc(RegType::sgpr
, size
);
3452 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3453 load
->definitions
[0] = Definition(val
);
3454 load
->glc
= info
->glc
;
3455 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3456 load
->barrier
= info
->barrier
;
3457 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3458 bld
.insert(std::move(load
));
3462 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3464 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3465 Temp offset
, unsigned bytes_needed
,
3466 unsigned align_
, unsigned const_offset
,
3469 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3470 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3472 if (info
->soffset
.id()) {
3473 if (soffset
.isTemp())
3474 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3475 soffset
= Operand(info
->soffset
);
3478 unsigned bytes_size
= 0;
3480 if (bytes_needed
== 1) {
3482 op
= aco_opcode::buffer_load_ubyte
;
3483 } else if (bytes_needed
== 2) {
3485 op
= aco_opcode::buffer_load_ushort
;
3486 } else if (bytes_needed
<= 4) {
3488 op
= aco_opcode::buffer_load_dword
;
3489 } else if (bytes_needed
<= 8) {
3491 op
= aco_opcode::buffer_load_dwordx2
;
3492 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3494 op
= aco_opcode::buffer_load_dwordx3
;
3497 op
= aco_opcode::buffer_load_dwordx4
;
3499 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3500 mubuf
->operands
[0] = Operand(info
->resource
);
3501 mubuf
->operands
[1] = vaddr
;
3502 mubuf
->operands
[2] = soffset
;
3503 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3504 mubuf
->glc
= info
->glc
;
3505 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3506 mubuf
->barrier
= info
->barrier
;
3507 mubuf
->can_reorder
= info
->can_reorder
;
3508 mubuf
->offset
= const_offset
;
3509 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3510 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3511 mubuf
->definitions
[0] = Definition(val
);
3512 bld
.insert(std::move(mubuf
));
3515 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3520 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3522 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3524 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3525 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3527 if (addr
.type() == RegType::vgpr
)
3528 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3529 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3532 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3533 Temp offset
, unsigned bytes_needed
,
3534 unsigned align_
, unsigned const_offset
,
3537 unsigned bytes_size
= 0;
3538 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3539 bool global
= bld
.program
->chip_class
>= GFX9
;
3541 if (bytes_needed
== 1) {
3543 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3544 } else if (bytes_needed
== 2) {
3546 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3547 } else if (bytes_needed
<= 4) {
3549 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3550 } else if (bytes_needed
<= 8) {
3552 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3553 } else if (bytes_needed
<= 12 && !mubuf
) {
3555 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3558 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3560 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3561 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3563 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3564 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3565 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3566 mubuf
->operands
[2] = Operand(0u);
3567 mubuf
->glc
= info
->glc
;
3570 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3571 mubuf
->disable_wqm
= false;
3572 mubuf
->barrier
= info
->barrier
;
3573 mubuf
->definitions
[0] = Definition(val
);
3574 bld
.insert(std::move(mubuf
));
3576 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3578 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3579 flat
->operands
[0] = Operand(offset
);
3580 flat
->operands
[1] = Operand(s1
);
3581 flat
->glc
= info
->glc
;
3582 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3583 flat
->barrier
= info
->barrier
;
3585 flat
->definitions
[0] = Definition(val
);
3586 bld
.insert(std::move(flat
));
3590 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3595 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3597 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3598 Temp address
, unsigned base_offset
, unsigned align
)
3600 assert(util_is_power_of_two_nonzero(align
));
3602 Builder
bld(ctx
->program
, ctx
->block
);
3604 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3605 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3606 info
.align_mul
= align
;
3607 info
.align_offset
= 0;
3608 info
.barrier
= barrier_shared
;
3609 info
.can_reorder
= false;
3610 info
.const_offset
= base_offset
;
3611 emit_lds_load(ctx
, bld
, &info
);
3616 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3621 Builder
bld(ctx
->program
, ctx
->block
);
3623 ASSERTED
bool is_subdword
= false;
3624 for (unsigned i
= 0; i
< count
; i
++)
3625 is_subdword
|= offsets
[i
] % 4;
3626 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3627 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3629 /* count == 1 fast path */
3631 if (dst_type
== RegType::sgpr
)
3632 dst
[0] = bld
.as_uniform(src
);
3634 dst
[0] = as_vgpr(ctx
, src
);
3638 for (unsigned i
= 0; i
< count
- 1; i
++)
3639 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3640 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3642 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3643 src
= as_vgpr(ctx
, src
);
3645 /* use allocated_vec if possible */
3646 auto it
= ctx
->allocated_vec
.find(src
.id());
3647 if (it
!= ctx
->allocated_vec
.end()) {
3648 unsigned total_size
= 0;
3649 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3650 total_size
+= it
->second
[i
].bytes();
3651 if (total_size
!= src
.bytes())
3654 unsigned elem_size
= it
->second
[0].bytes();
3656 for (unsigned i
= 0; i
< count
; i
++) {
3657 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3661 for (unsigned i
= 0; i
< count
; i
++) {
3662 unsigned start_idx
= offsets
[i
] / elem_size
;
3663 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3664 if (op_count
== 1) {
3665 if (dst_type
== RegType::sgpr
)
3666 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3668 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3672 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3673 for (unsigned j
= 0; j
< op_count
; j
++) {
3674 Temp tmp
= it
->second
[start_idx
+ j
];
3675 if (dst_type
== RegType::sgpr
)
3676 tmp
= bld
.as_uniform(tmp
);
3677 vec
->operands
[j
] = Operand(tmp
);
3679 vec
->definitions
[0] = Definition(dst
[i
]);
3680 bld
.insert(std::move(vec
));
3686 if (dst_type
== RegType::sgpr
)
3687 src
= bld
.as_uniform(src
);
3691 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3692 split
->operands
[0] = Operand(src
);
3693 for (unsigned i
= 0; i
< count
; i
++)
3694 split
->definitions
[i
] = Definition(dst
[i
]);
3695 bld
.insert(std::move(split
));
3698 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3699 int *start
, int *count
)
3701 unsigned start_elem
= ffs(todo_mask
) - 1;
3702 bool skip
= !(mask
& (1 << start_elem
));
3704 mask
= ~mask
& todo_mask
;
3708 u_bit_scan_consecutive_range(&mask
, start
, count
);
3713 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3715 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3718 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3719 Temp address
, unsigned base_offset
, unsigned align
)
3721 assert(util_is_power_of_two_nonzero(align
));
3722 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3724 Builder
bld(ctx
->program
, ctx
->block
);
3725 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3726 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3728 unsigned write_count
= 0;
3729 Temp write_datas
[32];
3730 unsigned offsets
[32];
3731 aco_opcode opcodes
[32];
3733 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3735 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3738 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3739 offsets
[write_count
] = offset
;
3740 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3742 advance_write_mask(&todo
, offset
, bytes
);
3746 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3747 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3748 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3749 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3751 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3752 aco_opcode op
= aco_opcode::num_opcodes
;
3753 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3754 op
= aco_opcode::ds_write_b128
;
3756 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3757 op
= aco_opcode::ds_write_b96
;
3759 } else if (bytes
>= 8 && aligned8
) {
3760 op
= aco_opcode::ds_write_b64
;
3762 } else if (bytes
>= 4 && aligned4
) {
3763 op
= aco_opcode::ds_write_b32
;
3765 } else if (bytes
>= 2 && aligned2
) {
3766 op
= aco_opcode::ds_write_b16
;
3768 } else if (bytes
>= 1) {
3769 op
= aco_opcode::ds_write_b8
;
3775 offsets
[write_count
] = offset
;
3776 opcodes
[write_count
] = op
;
3778 advance_write_mask(&todo
, offset
, bytes
);
3781 Operand m
= load_lds_size_m0(bld
);
3783 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3785 for (unsigned i
= 0; i
< write_count
; i
++) {
3786 aco_opcode op
= opcodes
[i
];
3787 if (op
== aco_opcode::num_opcodes
)
3790 Temp data
= write_datas
[i
];
3792 unsigned second
= write_count
;
3793 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3794 for (second
= i
+ 1; second
< write_count
; second
++) {
3795 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3796 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3797 opcodes
[second
] = aco_opcode::num_opcodes
;
3803 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3804 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3806 unsigned inline_offset
= base_offset
+ offsets
[i
];
3807 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3808 Temp address_offset
= address
;
3809 if (inline_offset
> max_offset
) {
3810 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3811 inline_offset
= offsets
[i
];
3813 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3816 Temp second_data
= write_datas
[second
];
3817 inline_offset
/= data
.bytes();
3818 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3820 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3825 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3827 unsigned align
= 16;
3829 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3835 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3840 return aco_opcode::buffer_store_byte
;
3843 return aco_opcode::buffer_store_short
;
3845 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3847 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3850 return aco_opcode::buffer_store_dwordx3
;
3852 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3854 unreachable("Unexpected store size");
3855 return aco_opcode::num_opcodes
;
3858 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3859 Temp data
, unsigned writemask
, int swizzle_element_size
,
3860 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3862 unsigned write_count_with_skips
= 0;
3865 /* determine how to split the data */
3866 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3869 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3870 offsets
[write_count_with_skips
] = offset
;
3871 if (skips
[write_count_with_skips
]) {
3872 advance_write_mask(&todo
, offset
, bytes
);
3873 write_count_with_skips
++;
3877 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3878 * larger than swizzle_element_size */
3879 bytes
= MIN2(bytes
, swizzle_element_size
);
3881 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3883 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3884 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3887 /* dword or larger stores have to be dword-aligned */
3888 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3889 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3890 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3891 if (bytes
>= 4 && !dword_aligned
)
3892 bytes
= MIN2(bytes
, 2);
3894 advance_write_mask(&todo
, offset
, bytes
);
3895 write_count_with_skips
++;
3898 /* actually split data */
3899 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3902 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3905 write_datas
[*write_count
] = write_datas
[i
];
3906 offsets
[*write_count
] = offsets
[i
];
3911 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3912 unsigned split_cnt
= 0u, Temp dst
= Temp())
3914 Builder
bld(ctx
->program
, ctx
->block
);
3915 unsigned dword_size
= elem_size_bytes
/ 4;
3918 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3920 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3921 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3922 instr
->definitions
[0] = Definition(dst
);
3924 for (unsigned i
= 0; i
< cnt
; ++i
) {
3926 assert(arr
[i
].size() == dword_size
);
3927 allocated_vec
[i
] = arr
[i
];
3928 instr
->operands
[i
] = Operand(arr
[i
]);
3930 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3931 allocated_vec
[i
] = zero
;
3932 instr
->operands
[i
] = Operand(zero
);
3936 bld
.insert(std::move(instr
));
3939 emit_split_vector(ctx
, dst
, split_cnt
);
3941 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3946 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3948 if (const_offset
>= 4096) {
3949 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3950 const_offset
%= 4096u;
3953 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3954 else if (unlikely(voffset
.regClass() == s1
))
3955 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3956 else if (likely(voffset
.regClass() == v1
))
3957 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3959 unreachable("Unsupported register class of voffset");
3962 return const_offset
;
3965 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3966 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3969 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3970 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3972 Builder
bld(ctx
->program
, ctx
->block
);
3973 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3974 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3976 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3977 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3978 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3979 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3980 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3982 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3985 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3986 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3987 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3989 Builder
bld(ctx
->program
, ctx
->block
);
3990 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3992 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3994 unsigned write_count
= 0;
3995 Temp write_datas
[32];
3996 unsigned offsets
[32];
3997 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3998 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4000 for (unsigned i
= 0; i
< write_count
; i
++) {
4001 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4002 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
4006 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4007 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4008 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4010 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
4011 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
4012 assert(!!stride
!= allow_combining
);
4014 Builder
bld(ctx
->program
, ctx
->block
);
4016 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4017 info
.component_stride
= allow_combining
? 0 : stride
;
4019 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4020 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4021 info
.align_offset
= 0;
4022 info
.soffset
= soffset
;
4023 info
.const_offset
= base_const_offset
;
4024 emit_mubuf_load(ctx
, bld
, &info
);
4027 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4029 Builder
bld(ctx
->program
, ctx
->block
);
4030 Temp offset
= base_offset
.first
;
4031 unsigned const_offset
= base_offset
.second
;
4033 if (!nir_src_is_const(*off_src
)) {
4034 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4037 /* Calculate indirect offset with stride */
4038 if (likely(indirect_offset_arg
.regClass() == v1
))
4039 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4040 else if (indirect_offset_arg
.regClass() == s1
)
4041 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4043 unreachable("Unsupported register class of indirect offset");
4045 /* Add to the supplied base offset */
4046 if (offset
.id() == 0)
4047 offset
= with_stride
;
4048 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4049 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4050 else if (offset
.size() == 1 && with_stride
.size() == 1)
4051 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4053 unreachable("Unsupported register class of indirect offset");
4055 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4056 const_offset
+= const_offset_arg
* stride
;
4059 return std::make_pair(offset
, const_offset
);
4062 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4064 Builder
bld(ctx
->program
, ctx
->block
);
4067 if (off1
.first
.id() && off2
.first
.id()) {
4068 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4069 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4070 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4071 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4073 unreachable("Unsupported register class of indirect offset");
4075 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4078 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4081 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4083 Builder
bld(ctx
->program
, ctx
->block
);
4084 unsigned const_offset
= offs
.second
* multiplier
;
4086 if (!offs
.first
.id())
4087 return std::make_pair(offs
.first
, const_offset
);
4089 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4090 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4091 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4093 return std::make_pair(offset
, const_offset
);
4096 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4098 Builder
bld(ctx
->program
, ctx
->block
);
4100 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4101 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4102 /* component is in bytes */
4103 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4105 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4106 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4107 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4110 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4112 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4115 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4117 Builder
bld(ctx
->program
, ctx
->block
);
4119 switch (ctx
->shader
->info
.stage
) {
4120 case MESA_SHADER_TESS_CTRL
:
4121 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4122 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4123 case MESA_SHADER_TESS_EVAL
:
4124 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4126 unreachable("Unsupported stage in get_tess_rel_patch_id");
4130 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4132 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4133 Builder
bld(ctx
->program
, ctx
->block
);
4135 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4136 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4138 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4140 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4141 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4143 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4144 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4145 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4147 return offset_mul(ctx
, offs
, 4u);
4150 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4152 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4153 Builder
bld(ctx
->program
, ctx
->block
);
4155 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4156 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
4157 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
4158 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
4159 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4160 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
4162 std::pair
<Temp
, unsigned> offs
= instr
4163 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4164 : std::make_pair(Temp(), 0u);
4166 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4167 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4172 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4173 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4175 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4176 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4178 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4179 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4185 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4187 Builder
bld(ctx
->program
, ctx
->block
);
4189 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4190 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4192 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4194 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4195 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4196 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4198 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4199 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4204 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4206 Builder
bld(ctx
->program
, ctx
->block
);
4208 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
4209 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
4210 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
4212 unsigned output_vertex_size
= num_tcs_outputs
* 16;
4213 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4214 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4215 unsigned attr_stride
= ctx
->tcs_num_patches
;
4217 std::pair
<Temp
, unsigned> offs
= instr
4218 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4219 : std::make_pair(Temp(), 0u);
4221 if (const_base_offset
)
4222 offs
.second
+= const_base_offset
* attr_stride
;
4224 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4225 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4226 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4231 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4236 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4237 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4239 if (!nir_src_is_const(*off_src
)) {
4245 off
+= nir_src_as_uint(*off_src
) * 16u;
4248 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
4249 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
4256 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4258 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4259 unsigned component
= nir_intrinsic_component(instr
);
4260 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4262 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4263 if (off_instr
->type
!= nir_instr_type_load_const
)
4266 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4267 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4269 if (instr
->src
[0].ssa
->bit_size
== 64)
4270 write_mask
= widen_mask(write_mask
, 2);
4272 for (unsigned i
= 0; i
< 8; ++i
) {
4273 if (write_mask
& (1 << i
)) {
4274 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4275 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
4283 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4285 /* Only TCS per-vertex inputs are supported by this function.
4286 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4288 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4291 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4292 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4293 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4294 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4295 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4296 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4301 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4302 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4303 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4308 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4310 Builder
bld(ctx
->program
, ctx
->block
);
4312 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4313 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4314 bool indirect_write
;
4315 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4316 if (temp_only_input
&& !indirect_write
)
4320 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4321 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4322 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4323 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4325 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4326 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4327 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4328 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4329 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4333 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4334 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4335 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4336 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4337 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4338 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4339 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4340 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4341 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4342 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4343 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4344 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4345 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4347 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
4348 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4349 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
4351 unreachable("Invalid LS or ES stage");
4354 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4355 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4356 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4360 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4365 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4366 return off
== ctx
->tcs_tess_lvl_out_loc
||
4367 off
== ctx
->tcs_tess_lvl_in_loc
;
4371 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4373 uint64_t mask
= per_vertex
4374 ? ctx
->program
->info
->tcs
.tes_inputs_read
4375 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4377 bool indirect_write
= false;
4378 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4379 return indirect_write
|| output_read_by_tes
;
4382 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4384 uint64_t mask
= per_vertex
4385 ? ctx
->shader
->info
.outputs_read
4386 : ctx
->shader
->info
.patch_outputs_read
;
4388 bool indirect_write
= false;
4389 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4390 return indirect_write
|| output_read
;
4393 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4395 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4396 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4398 Builder
bld(ctx
->program
, ctx
->block
);
4400 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4401 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4402 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4404 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4405 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4406 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4408 if (write_to_vmem
) {
4409 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4410 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4411 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4413 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4414 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4415 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4419 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4420 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4421 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4425 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4427 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4428 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4430 Builder
bld(ctx
->program
, ctx
->block
);
4432 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4433 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4434 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4435 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4437 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4440 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4442 if (ctx
->stage
== vertex_vs
||
4443 ctx
->stage
== tess_eval_vs
||
4444 ctx
->stage
== fragment_fs
||
4445 ctx
->stage
== ngg_vertex_gs
||
4446 ctx
->stage
== ngg_tess_eval_gs
||
4447 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4448 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4449 if (!stored_to_temps
) {
4450 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4451 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4452 fprintf(stderr
, "\n");
4455 } else if (ctx
->stage
== vertex_es
||
4456 ctx
->stage
== vertex_ls
||
4457 ctx
->stage
== tess_eval_es
||
4458 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4459 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4460 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4461 visit_store_ls_or_es_output(ctx
, instr
);
4462 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4463 visit_store_tcs_output(ctx
, instr
, false);
4465 unreachable("Shader stage not implemented");
4469 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4471 visit_load_tcs_output(ctx
, instr
, false);
4474 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4476 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4477 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4479 Builder
bld(ctx
->program
, ctx
->block
);
4480 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4481 if (ctx
->program
->has_16bank_lds
)
4482 interp_p1
.instr
->operands
[0].setLateKill(true);
4483 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4486 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4488 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4489 for (unsigned i
= 0; i
< num_components
; i
++)
4490 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4491 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4492 assert(num_components
== 4);
4493 Builder
bld(ctx
->program
, ctx
->block
);
4494 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4497 for (Operand
& op
: vec
->operands
)
4498 op
= op
.isUndefined() ? Operand(0u) : op
;
4500 vec
->definitions
[0] = Definition(dst
);
4501 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4502 emit_split_vector(ctx
, dst
, num_components
);
4506 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4508 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4509 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4510 unsigned idx
= nir_intrinsic_base(instr
);
4511 unsigned component
= nir_intrinsic_component(instr
);
4512 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4514 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4516 assert(offset
->u32
== 0);
4518 /* the lower 15bit of the prim_mask contain the offset into LDS
4519 * while the upper bits contain the number of prims */
4520 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4521 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4522 Builder
bld(ctx
->program
, ctx
->block
);
4523 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4524 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4525 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4526 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4527 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4530 if (instr
->dest
.ssa
.num_components
== 1) {
4531 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4533 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4534 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4536 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4537 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4538 vec
->operands
[i
] = Operand(tmp
);
4540 vec
->definitions
[0] = Definition(dst
);
4541 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4545 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4546 unsigned offset
, unsigned stride
, unsigned channels
)
4548 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4549 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4551 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4552 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4555 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4556 unsigned offset
, unsigned stride
, unsigned *channels
)
4558 if (!vtx_info
->chan_byte_size
) {
4559 *channels
= vtx_info
->num_channels
;
4560 return vtx_info
->chan_format
;
4563 unsigned num_channels
= *channels
;
4564 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4565 unsigned new_channels
= num_channels
+ 1;
4566 /* first, assume more loads is worse and try using a larger data format */
4567 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4569 /* don't make the attribute potentially out-of-bounds */
4570 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4574 if (new_channels
== 5) {
4575 /* then try decreasing load size (at the cost of more loads) */
4576 new_channels
= *channels
;
4577 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4581 if (new_channels
< *channels
)
4582 *channels
= new_channels
;
4583 num_channels
= new_channels
;
4586 switch (vtx_info
->chan_format
) {
4587 case V_008F0C_BUF_DATA_FORMAT_8
:
4588 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4589 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4590 case V_008F0C_BUF_DATA_FORMAT_16
:
4591 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4592 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4593 case V_008F0C_BUF_DATA_FORMAT_32
:
4594 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4595 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4597 unreachable("shouldn't reach here");
4598 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4601 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4602 * so we may need to fix it up. */
4603 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4605 Builder
bld(ctx
->program
, ctx
->block
);
4607 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4608 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4610 /* For the integer-like cases, do a natural sign extension.
4612 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4613 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4616 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4617 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4619 /* Convert back to the right type. */
4620 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4621 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4622 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4623 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4624 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4625 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4631 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4633 Builder
bld(ctx
->program
, ctx
->block
);
4634 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4635 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4637 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4638 if (off_instr
->type
!= nir_instr_type_load_const
) {
4639 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4640 nir_print_instr(off_instr
, stderr
);
4641 fprintf(stderr
, "\n");
4643 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4645 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4647 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4648 unsigned component
= nir_intrinsic_component(instr
);
4649 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4650 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4651 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4652 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4654 unsigned dfmt
= attrib_format
& 0xf;
4655 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4656 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4658 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4659 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4660 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4661 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4663 num_channels
= MAX2(num_channels
, 3);
4665 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4666 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4669 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4670 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4671 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4673 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4675 Temp divided
= bld
.tmp(v1
);
4676 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4677 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4679 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4682 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4685 index
= bld
.vadd32(bld
.def(v1
),
4686 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4687 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4690 Temp channels
[num_channels
];
4691 unsigned channel_start
= 0;
4692 bool direct_fetch
= false;
4694 /* skip unused channels at the start */
4695 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4696 channel_start
= ffs(mask
) - 1;
4697 for (unsigned i
= 0; i
< channel_start
; i
++)
4698 channels
[i
] = Temp(0, s1
);
4699 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4700 num_channels
= 3 - (ffs(mask
) - 1);
4704 while (channel_start
< num_channels
) {
4705 unsigned fetch_size
= num_channels
- channel_start
;
4706 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4707 bool expanded
= false;
4709 /* use MUBUF when possible to avoid possible alignment issues */
4710 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4711 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4712 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4713 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4714 vtx_info
->chan_byte_size
== 4;
4715 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4717 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4719 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4720 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4726 Temp fetch_index
= index
;
4727 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4728 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4729 fetch_offset
= fetch_offset
% attrib_stride
;
4732 Operand
soffset(0u);
4733 if (fetch_offset
>= 4096) {
4734 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4735 fetch_offset
%= 4096;
4739 switch (fetch_size
) {
4741 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4744 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4747 assert(ctx
->options
->chip_class
>= GFX7
||
4748 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4749 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4752 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4755 unreachable("Unimplemented load_input vector size");
4759 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4760 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4761 num_channels
<= 3)) {
4762 direct_fetch
= true;
4765 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4769 Instruction
*mubuf
= bld
.mubuf(opcode
,
4770 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4771 fetch_offset
, false, true).instr
;
4772 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4774 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4775 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4776 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4777 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4780 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4782 if (fetch_size
== 1) {
4783 channels
[channel_start
] = fetch_dst
;
4785 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4786 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4789 channel_start
+= fetch_size
;
4792 if (!direct_fetch
) {
4793 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4794 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4796 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4797 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4798 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4800 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4801 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4802 unsigned num_temp
= 0;
4803 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4804 unsigned idx
= i
+ component
;
4805 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4806 Temp channel
= channels
[swizzle
[idx
]];
4807 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4808 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4809 vec
->operands
[i
] = Operand(channel
);
4813 } else if (is_float
&& idx
== 3) {
4814 vec
->operands
[i
] = Operand(0x3f800000u
);
4815 } else if (!is_float
&& idx
== 3) {
4816 vec
->operands
[i
] = Operand(1u);
4818 vec
->operands
[i
] = Operand(0u);
4821 vec
->definitions
[0] = Definition(dst
);
4822 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4823 emit_split_vector(ctx
, dst
, dst
.size());
4825 if (num_temp
== dst
.size())
4826 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4828 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4829 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4830 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4831 if (off_instr
->type
!= nir_instr_type_load_const
||
4832 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4833 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4834 nir_print_instr(off_instr
, stderr
);
4835 fprintf(stderr
, "\n");
4838 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4839 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4841 assert(offset
->u32
== 0);
4843 /* the lower 15bit of the prim_mask contain the offset into LDS
4844 * while the upper bits contain the number of prims */
4845 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4846 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4847 Builder
bld(ctx
->program
, ctx
->block
);
4848 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4849 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4850 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4851 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4852 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4855 unsigned idx
= nir_intrinsic_base(instr
);
4856 unsigned component
= nir_intrinsic_component(instr
);
4857 unsigned vertex_id
= 2; /* P0 */
4859 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4860 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4861 switch (src0
->u32
) {
4863 vertex_id
= 2; /* P0 */
4866 vertex_id
= 0; /* P10 */
4869 vertex_id
= 1; /* P20 */
4872 unreachable("invalid vertex index");
4876 if (dst
.size() == 1) {
4877 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4879 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4880 for (unsigned i
= 0; i
< dst
.size(); i
++)
4881 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4882 vec
->definitions
[0] = Definition(dst
);
4883 bld
.insert(std::move(vec
));
4886 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4887 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4888 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4889 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4890 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4892 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4894 unreachable("Shader stage not implemented");
4898 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4900 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4902 Builder
bld(ctx
->program
, ctx
->block
);
4903 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4906 if (!nir_src_is_const(*vertex_src
)) {
4907 /* better code could be created, but this case probably doesn't happen
4908 * much in practice */
4909 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4910 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4913 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4914 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4916 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4918 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4921 if (vertex_offset
.id()) {
4922 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4923 Operand(i
), indirect_vertex
);
4924 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4926 vertex_offset
= elem
;
4930 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4931 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4933 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4934 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4935 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4936 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4937 Operand((vertex
% 2u) * 16u), Operand(16u));
4939 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4942 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4943 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4944 return offset_mul(ctx
, offs
, 4u);
4947 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4949 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4951 Builder
bld(ctx
->program
, ctx
->block
);
4952 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4953 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4955 if (ctx
->stage
== geometry_gs
) {
4956 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4957 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4958 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4959 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4960 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4961 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4962 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4964 unreachable("Unsupported GS stage.");
4968 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4970 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4972 Builder
bld(ctx
->program
, ctx
->block
);
4973 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4975 if (load_input_from_temps(ctx
, instr
, dst
))
4978 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4979 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4980 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4982 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4985 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4987 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4989 Builder
bld(ctx
->program
, ctx
->block
);
4991 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4992 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4993 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4995 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4996 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4998 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5001 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5003 switch (ctx
->shader
->info
.stage
) {
5004 case MESA_SHADER_GEOMETRY
:
5005 visit_load_gs_per_vertex_input(ctx
, instr
);
5007 case MESA_SHADER_TESS_CTRL
:
5008 visit_load_tcs_per_vertex_input(ctx
, instr
);
5010 case MESA_SHADER_TESS_EVAL
:
5011 visit_load_tes_per_vertex_input(ctx
, instr
);
5014 unreachable("Unimplemented shader stage");
5018 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5020 visit_load_tcs_output(ctx
, instr
, true);
5023 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5025 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5026 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5028 visit_store_tcs_output(ctx
, instr
, true);
5031 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5033 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5035 Builder
bld(ctx
->program
, ctx
->block
);
5036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5038 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5039 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5042 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5043 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5044 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5045 tes_w
= Operand(tmp
);
5048 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5049 emit_split_vector(ctx
, tess_coord
, 3);
5052 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5054 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5055 Builder
bld(ctx
->program
, ctx
->block
);
5056 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5057 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5058 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5061 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5065 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5067 Builder
bld(ctx
->program
, ctx
->block
);
5068 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5069 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
5070 index
= bld
.as_uniform(index
);
5071 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5072 unsigned binding
= nir_intrinsic_binding(instr
);
5075 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5076 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5077 unsigned offset
= layout
->binding
[binding
].offset
;
5079 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5080 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5081 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5082 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5083 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5086 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5087 stride
= layout
->binding
[binding
].size
;
5090 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5091 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5093 if (nir_const_index
) {
5094 const_index
= const_index
* stride
;
5095 } else if (index
.type() == RegType::vgpr
) {
5096 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5097 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5099 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5103 if (nir_const_index
) {
5104 const_index
= const_index
+ offset
;
5105 } else if (index
.type() == RegType::vgpr
) {
5106 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5108 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5112 if (nir_const_index
&& const_index
== 0) {
5114 } else if (index
.type() == RegType::vgpr
) {
5115 index
= bld
.vadd32(bld
.def(v1
),
5116 nir_const_index
? Operand(const_index
) : Operand(index
),
5119 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5120 nir_const_index
? Operand(const_index
) : Operand(index
),
5124 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5127 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5128 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5129 bool glc
=false, bool readonly
=true)
5131 Builder
bld(ctx
->program
, ctx
->block
);
5133 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5135 offset
= bld
.as_uniform(offset
);
5137 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5139 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5140 info
.can_reorder
= readonly
;
5141 info
.align_mul
= align_mul
;
5142 info
.align_offset
= align_offset
;
5144 emit_smem_load(ctx
, bld
, &info
);
5146 emit_mubuf_load(ctx
, bld
, &info
);
5149 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5151 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5152 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5154 Builder
bld(ctx
->program
, ctx
->block
);
5156 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5157 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5158 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5159 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5161 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5162 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5163 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5164 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5165 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5166 if (ctx
->options
->chip_class
>= GFX10
) {
5167 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5168 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5169 S_008F0C_RESOURCE_LEVEL(1);
5171 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5174 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5175 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5176 Operand(0xFFFFFFFFu
),
5177 Operand(desc_type
));
5178 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5179 rsrc
, upper_dwords
);
5181 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5182 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5184 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5185 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5186 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5189 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5191 Builder
bld(ctx
->program
, ctx
->block
);
5192 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5193 unsigned offset
= nir_intrinsic_base(instr
);
5194 unsigned count
= instr
->dest
.ssa
.num_components
;
5195 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5197 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5198 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5199 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5200 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5201 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5202 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5203 for (unsigned i
= 0; i
< count
; ++i
) {
5204 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5205 vec
->operands
[i
] = Operand
{elems
[i
]};
5207 vec
->definitions
[0] = Definition(dst
);
5208 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5209 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5214 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5215 if (offset
!= 0) // TODO check if index != 0 as well
5216 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5217 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5220 bool aligned
= true;
5222 if (instr
->dest
.ssa
.bit_size
== 8) {
5223 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5224 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5226 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5227 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5228 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5230 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5235 switch (vec
.size()) {
5237 op
= aco_opcode::s_load_dword
;
5240 op
= aco_opcode::s_load_dwordx2
;
5246 op
= aco_opcode::s_load_dwordx4
;
5252 op
= aco_opcode::s_load_dwordx8
;
5255 unreachable("unimplemented or forbidden load_push_constant.");
5258 bld
.smem(op
, Definition(vec
), ptr
, index
);
5261 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5262 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5267 emit_split_vector(ctx
, vec
, 4);
5268 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5269 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5270 emit_extract_vector(ctx
, vec
, 0, rc
),
5271 emit_extract_vector(ctx
, vec
, 1, rc
),
5272 emit_extract_vector(ctx
, vec
, 2, rc
));
5275 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5278 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5280 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5282 Builder
bld(ctx
->program
, ctx
->block
);
5284 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5285 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5286 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5287 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5288 if (ctx
->options
->chip_class
>= GFX10
) {
5289 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5290 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5291 S_008F0C_RESOURCE_LEVEL(1);
5293 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5294 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5297 unsigned base
= nir_intrinsic_base(instr
);
5298 unsigned range
= nir_intrinsic_range(instr
);
5300 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5301 if (base
&& offset
.type() == RegType::sgpr
)
5302 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5303 else if (base
&& offset
.type() == RegType::vgpr
)
5304 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5306 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5307 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5308 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5309 Operand(desc_type
));
5310 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5311 // TODO: get alignment information for subdword constants
5312 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5315 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5317 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5318 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5320 ctx
->program
->needs_exact
= true;
5322 // TODO: optimize uniform conditions
5323 Builder
bld(ctx
->program
, ctx
->block
);
5324 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5325 assert(src
.regClass() == bld
.lm
);
5326 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5327 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5328 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5332 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5334 Builder
bld(ctx
->program
, ctx
->block
);
5336 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5337 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5339 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5340 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5342 if (ctx
->block
->loop_nest_depth
&&
5343 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5344 /* we handle discards the same way as jump instructions */
5345 append_logical_end(ctx
->block
);
5347 /* in loops, discard behaves like break */
5348 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5349 ctx
->block
->kind
|= block_kind_discard
;
5352 /* uniform discard - loop ends here */
5353 assert(nir_instr_is_last(&instr
->instr
));
5354 ctx
->block
->kind
|= block_kind_uniform
;
5355 ctx
->cf_info
.has_branch
= true;
5356 bld
.branch(aco_opcode::p_branch
);
5357 add_linear_edge(ctx
->block
->index
, linear_target
);
5361 /* we add a break right behind the discard() instructions */
5362 ctx
->block
->kind
|= block_kind_break
;
5363 unsigned idx
= ctx
->block
->index
;
5365 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5366 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5368 /* remove critical edges from linear CFG */
5369 bld
.branch(aco_opcode::p_branch
);
5370 Block
* break_block
= ctx
->program
->create_and_insert_block();
5371 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5372 break_block
->kind
|= block_kind_uniform
;
5373 add_linear_edge(idx
, break_block
);
5374 add_linear_edge(break_block
->index
, linear_target
);
5375 bld
.reset(break_block
);
5376 bld
.branch(aco_opcode::p_branch
);
5378 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5379 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5380 add_linear_edge(idx
, continue_block
);
5381 append_logical_start(continue_block
);
5382 ctx
->block
= continue_block
;
5387 /* it can currently happen that NIR doesn't remove the unreachable code */
5388 if (!nir_instr_is_last(&instr
->instr
)) {
5389 ctx
->program
->needs_exact
= true;
5390 /* save exec somewhere temporarily so that it doesn't get
5391 * overwritten before the discard from outer exec masks */
5392 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5393 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5394 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5398 /* This condition is incorrect for uniformly branched discards in a loop
5399 * predicated by a divergent condition, but the above code catches that case
5400 * and the discard would end up turning into a discard_if.
5410 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5411 /* program just ends here */
5412 ctx
->block
->kind
|= block_kind_uniform
;
5413 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5414 0 /* enabled mask */, 9 /* dest */,
5415 false /* compressed */, true/* done */, true /* valid mask */);
5416 bld
.sopp(aco_opcode::s_endpgm
);
5417 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5419 ctx
->block
->kind
|= block_kind_discard
;
5420 /* branch and linear edge is added by visit_if() */
5424 enum aco_descriptor_type
{
5435 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5436 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5438 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5439 return dim
== ac_image_cube
||
5440 dim
== ac_image_1darray
||
5441 dim
== ac_image_2darray
||
5442 dim
== ac_image_2darraymsaa
;
5445 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5446 enum aco_descriptor_type desc_type
,
5447 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5449 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5450 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5451 if (it != ctx->tex_desc.end())
5454 Temp index
= Temp();
5455 bool index_set
= false;
5456 unsigned constant_index
= 0;
5457 unsigned descriptor_set
;
5458 unsigned base_index
;
5459 Builder
bld(ctx
->program
, ctx
->block
);
5462 assert(tex_instr
&& !image
);
5464 base_index
= tex_instr
->sampler_index
;
5466 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5467 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5471 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5472 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5474 constant_index
+= array_size
* const_value
->u32
;
5476 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5477 if (indirect
.type() == RegType::vgpr
)
5478 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5480 if (array_size
!= 1)
5481 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5487 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5491 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5493 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5494 base_index
= deref_instr
->var
->data
.binding
;
5497 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5498 list
= convert_pointer_to_64_bit(ctx
, list
);
5500 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5501 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5502 unsigned offset
= binding
->offset
;
5503 unsigned stride
= binding
->size
;
5507 assert(base_index
< layout
->binding_count
);
5509 switch (desc_type
) {
5510 case ACO_DESC_IMAGE
:
5512 opcode
= aco_opcode::s_load_dwordx8
;
5514 case ACO_DESC_FMASK
:
5516 opcode
= aco_opcode::s_load_dwordx8
;
5519 case ACO_DESC_SAMPLER
:
5521 opcode
= aco_opcode::s_load_dwordx4
;
5522 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5523 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5525 case ACO_DESC_BUFFER
:
5527 opcode
= aco_opcode::s_load_dwordx4
;
5529 case ACO_DESC_PLANE_0
:
5530 case ACO_DESC_PLANE_1
:
5532 opcode
= aco_opcode::s_load_dwordx8
;
5533 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5535 case ACO_DESC_PLANE_2
:
5537 opcode
= aco_opcode::s_load_dwordx4
;
5541 unreachable("invalid desc_type\n");
5544 offset
+= constant_index
* stride
;
5546 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5547 (!index_set
|| binding
->immutable_samplers_equal
)) {
5548 if (binding
->immutable_samplers_equal
)
5551 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5552 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5553 Operand(samplers
[constant_index
* 4 + 0]),
5554 Operand(samplers
[constant_index
* 4 + 1]),
5555 Operand(samplers
[constant_index
* 4 + 2]),
5556 Operand(samplers
[constant_index
* 4 + 3]));
5561 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5563 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5564 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5567 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5569 if (desc_type
== ACO_DESC_PLANE_2
) {
5571 for (unsigned i
= 0; i
< 8; i
++)
5572 components
[i
] = bld
.tmp(s1
);
5573 bld
.pseudo(aco_opcode::p_split_vector
,
5574 Definition(components
[0]),
5575 Definition(components
[1]),
5576 Definition(components
[2]),
5577 Definition(components
[3]),
5580 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5581 bld
.pseudo(aco_opcode::p_split_vector
,
5582 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5583 Definition(components
[4]),
5584 Definition(components
[5]),
5585 Definition(components
[6]),
5586 Definition(components
[7]),
5589 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5590 components
[0], components
[1], components
[2], components
[3],
5591 components
[4], components
[5], components
[6], components
[7]);
5597 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5600 case GLSL_SAMPLER_DIM_BUF
:
5602 case GLSL_SAMPLER_DIM_1D
:
5603 return array
? 2 : 1;
5604 case GLSL_SAMPLER_DIM_2D
:
5605 return array
? 3 : 2;
5606 case GLSL_SAMPLER_DIM_MS
:
5607 return array
? 4 : 3;
5608 case GLSL_SAMPLER_DIM_3D
:
5609 case GLSL_SAMPLER_DIM_CUBE
:
5611 case GLSL_SAMPLER_DIM_RECT
:
5612 case GLSL_SAMPLER_DIM_SUBPASS
:
5614 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5623 /* Adjust the sample index according to FMASK.
5625 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5626 * which is the identity mapping. Each nibble says which physical sample
5627 * should be fetched to get that sample.
5629 * For example, 0x11111100 means there are only 2 samples stored and
5630 * the second sample covers 3/4 of the pixel. When reading samples 0
5631 * and 1, return physical sample 0 (determined by the first two 0s
5632 * in FMASK), otherwise return physical sample 1.
5634 * The sample index should be adjusted as follows:
5635 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5637 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5639 Builder
bld(ctx
->program
, ctx
->block
);
5640 Temp fmask
= bld
.tmp(v1
);
5641 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5642 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5645 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5646 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5647 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5648 load
->operands
[0] = Operand(fmask_desc_ptr
);
5649 load
->operands
[1] = Operand(s4
); /* no sampler */
5650 load
->operands
[2] = Operand(coord
);
5651 load
->definitions
[0] = Definition(fmask
);
5658 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5659 ctx
->block
->instructions
.emplace_back(std::move(load
));
5661 Operand sample_index4
;
5662 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5663 sample_index4
= Operand(sample_index
.constantValue() << 2);
5664 } else if (sample_index
.regClass() == s1
) {
5665 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5667 assert(sample_index
.regClass() == v1
);
5668 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5672 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5673 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5674 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5675 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5677 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5679 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5680 * resource descriptor is 0 (invalid),
5682 Temp compare
= bld
.tmp(bld
.lm
);
5683 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5684 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5686 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5688 /* Replace the MSAA sample index. */
5689 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5692 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5695 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5696 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5697 bool is_array
= glsl_sampler_type_is_array(type
);
5698 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5699 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5700 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5701 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5702 int count
= image_type_to_components_count(dim
, is_array
);
5703 std::vector
<Temp
> coords(count
);
5704 Builder
bld(ctx
->program
, ctx
->block
);
5708 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5709 /* get sample index */
5710 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5711 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5712 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5713 std::vector
<Temp
> fmask_load_address
;
5714 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5715 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5717 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5718 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5720 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5725 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5726 coords
.resize(coords
.size() + 1);
5727 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5729 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5731 for (int i
= 0; i
< count
; i
++)
5732 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5735 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5736 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5737 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5738 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5741 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5744 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5745 for (unsigned i
= 0; i
< coords
.size(); i
++)
5746 vec
->operands
[i
] = Operand(coords
[i
]);
5747 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5748 vec
->definitions
[0] = Definition(res
);
5749 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5754 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5756 Builder
bld(ctx
->program
, ctx
->block
);
5757 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5758 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5759 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5760 bool is_array
= glsl_sampler_type_is_array(type
);
5761 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5763 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5764 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5765 unsigned num_channels
= util_last_bit(mask
);
5766 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5767 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5770 switch (num_channels
) {
5772 opcode
= aco_opcode::buffer_load_format_x
;
5775 opcode
= aco_opcode::buffer_load_format_xy
;
5778 opcode
= aco_opcode::buffer_load_format_xyz
;
5781 opcode
= aco_opcode::buffer_load_format_xyzw
;
5784 unreachable(">4 channel buffer image load");
5786 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5787 load
->operands
[0] = Operand(rsrc
);
5788 load
->operands
[1] = Operand(vindex
);
5789 load
->operands
[2] = Operand((uint32_t) 0);
5791 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5794 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5795 load
->definitions
[0] = Definition(tmp
);
5797 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5798 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5799 load
->barrier
= barrier_image
;
5800 ctx
->block
->instructions
.emplace_back(std::move(load
));
5802 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5806 Temp coords
= get_image_coords(ctx
, instr
, type
);
5807 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5809 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5810 unsigned num_components
= util_bitcount(dmask
);
5812 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5815 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5817 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5818 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5820 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5821 load
->operands
[0] = Operand(resource
);
5822 load
->operands
[1] = Operand(s4
); /* no sampler */
5823 load
->operands
[2] = Operand(coords
);
5824 load
->definitions
[0] = Definition(tmp
);
5825 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5826 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5827 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5828 load
->dmask
= dmask
;
5830 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5831 load
->barrier
= barrier_image
;
5832 ctx
->block
->instructions
.emplace_back(std::move(load
));
5834 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5838 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5840 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5841 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5842 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5843 bool is_array
= glsl_sampler_type_is_array(type
);
5844 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5846 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5848 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5849 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5850 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5852 switch (data
.size()) {
5854 opcode
= aco_opcode::buffer_store_format_x
;
5857 opcode
= aco_opcode::buffer_store_format_xy
;
5860 opcode
= aco_opcode::buffer_store_format_xyz
;
5863 opcode
= aco_opcode::buffer_store_format_xyzw
;
5866 unreachable(">4 channel buffer image store");
5868 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5869 store
->operands
[0] = Operand(rsrc
);
5870 store
->operands
[1] = Operand(vindex
);
5871 store
->operands
[2] = Operand((uint32_t) 0);
5872 store
->operands
[3] = Operand(data
);
5873 store
->idxen
= true;
5876 store
->disable_wqm
= true;
5877 store
->barrier
= barrier_image
;
5878 ctx
->program
->needs_exact
= true;
5879 ctx
->block
->instructions
.emplace_back(std::move(store
));
5883 assert(data
.type() == RegType::vgpr
);
5884 Temp coords
= get_image_coords(ctx
, instr
, type
);
5885 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5887 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5888 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5890 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5891 store
->operands
[0] = Operand(resource
);
5892 store
->operands
[1] = Operand(data
);
5893 store
->operands
[2] = Operand(coords
);
5896 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5897 store
->dmask
= (1 << data
.size()) - 1;
5899 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5900 store
->disable_wqm
= true;
5901 store
->barrier
= barrier_image
;
5902 ctx
->program
->needs_exact
= true;
5903 ctx
->block
->instructions
.emplace_back(std::move(store
));
5907 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5909 /* return the previous value if dest is ever used */
5910 bool return_previous
= false;
5911 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5912 return_previous
= true;
5915 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5916 return_previous
= true;
5920 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5921 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5922 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5923 bool is_array
= glsl_sampler_type_is_array(type
);
5924 Builder
bld(ctx
->program
, ctx
->block
);
5926 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5927 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5929 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5930 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5932 aco_opcode buf_op
, image_op
;
5933 switch (instr
->intrinsic
) {
5934 case nir_intrinsic_image_deref_atomic_add
:
5935 buf_op
= aco_opcode::buffer_atomic_add
;
5936 image_op
= aco_opcode::image_atomic_add
;
5938 case nir_intrinsic_image_deref_atomic_umin
:
5939 buf_op
= aco_opcode::buffer_atomic_umin
;
5940 image_op
= aco_opcode::image_atomic_umin
;
5942 case nir_intrinsic_image_deref_atomic_imin
:
5943 buf_op
= aco_opcode::buffer_atomic_smin
;
5944 image_op
= aco_opcode::image_atomic_smin
;
5946 case nir_intrinsic_image_deref_atomic_umax
:
5947 buf_op
= aco_opcode::buffer_atomic_umax
;
5948 image_op
= aco_opcode::image_atomic_umax
;
5950 case nir_intrinsic_image_deref_atomic_imax
:
5951 buf_op
= aco_opcode::buffer_atomic_smax
;
5952 image_op
= aco_opcode::image_atomic_smax
;
5954 case nir_intrinsic_image_deref_atomic_and
:
5955 buf_op
= aco_opcode::buffer_atomic_and
;
5956 image_op
= aco_opcode::image_atomic_and
;
5958 case nir_intrinsic_image_deref_atomic_or
:
5959 buf_op
= aco_opcode::buffer_atomic_or
;
5960 image_op
= aco_opcode::image_atomic_or
;
5962 case nir_intrinsic_image_deref_atomic_xor
:
5963 buf_op
= aco_opcode::buffer_atomic_xor
;
5964 image_op
= aco_opcode::image_atomic_xor
;
5966 case nir_intrinsic_image_deref_atomic_exchange
:
5967 buf_op
= aco_opcode::buffer_atomic_swap
;
5968 image_op
= aco_opcode::image_atomic_swap
;
5970 case nir_intrinsic_image_deref_atomic_comp_swap
:
5971 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5972 image_op
= aco_opcode::image_atomic_cmpswap
;
5975 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5978 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5980 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5981 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5982 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5983 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5984 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5985 mubuf
->operands
[0] = Operand(resource
);
5986 mubuf
->operands
[1] = Operand(vindex
);
5987 mubuf
->operands
[2] = Operand((uint32_t)0);
5988 mubuf
->operands
[3] = Operand(data
);
5989 if (return_previous
)
5990 mubuf
->definitions
[0] = Definition(dst
);
5992 mubuf
->idxen
= true;
5993 mubuf
->glc
= return_previous
;
5994 mubuf
->dlc
= false; /* Not needed for atomics */
5995 mubuf
->disable_wqm
= true;
5996 mubuf
->barrier
= barrier_image
;
5997 ctx
->program
->needs_exact
= true;
5998 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6002 Temp coords
= get_image_coords(ctx
, instr
, type
);
6003 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6004 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6005 mimg
->operands
[0] = Operand(resource
);
6006 mimg
->operands
[1] = Operand(data
);
6007 mimg
->operands
[2] = Operand(coords
);
6008 if (return_previous
)
6009 mimg
->definitions
[0] = Definition(dst
);
6010 mimg
->glc
= return_previous
;
6011 mimg
->dlc
= false; /* Not needed for atomics */
6012 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6013 mimg
->dmask
= (1 << data
.size()) - 1;
6015 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6016 mimg
->disable_wqm
= true;
6017 mimg
->barrier
= barrier_image
;
6018 ctx
->program
->needs_exact
= true;
6019 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6023 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6025 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6026 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6027 Builder
bld(ctx
->program
, ctx
->block
);
6029 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6031 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6032 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6034 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6035 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6037 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6038 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6040 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6041 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6042 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6043 if (dst
.type() == RegType::vgpr
)
6044 bld
.copy(Definition(dst
), shr_dst
);
6046 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6048 emit_extract_vector(ctx
, desc
, 2, dst
);
6052 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6054 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6055 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6056 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6057 bool is_array
= glsl_sampler_type_is_array(type
);
6058 Builder
bld(ctx
->program
, ctx
->block
);
6060 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6061 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6062 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6066 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6069 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6071 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6073 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6074 mimg
->operands
[0] = Operand(resource
);
6075 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6076 mimg
->operands
[2] = Operand(lod
);
6077 uint8_t& dmask
= mimg
->dmask
;
6078 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6079 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6080 mimg
->da
= glsl_sampler_type_is_array(type
);
6081 mimg
->can_reorder
= true;
6082 Definition
& def
= mimg
->definitions
[0];
6083 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6085 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6086 glsl_sampler_type_is_array(type
)) {
6088 assert(instr
->dest
.ssa
.num_components
== 3);
6089 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6090 def
= Definition(tmp
);
6091 emit_split_vector(ctx
, tmp
, 3);
6093 /* divide 3rd value by 6 by multiplying with magic number */
6094 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6095 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6097 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6098 emit_extract_vector(ctx
, tmp
, 0, v1
),
6099 emit_extract_vector(ctx
, tmp
, 1, v1
),
6102 } else if (ctx
->options
->chip_class
== GFX9
&&
6103 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6104 glsl_sampler_type_is_array(type
)) {
6105 assert(instr
->dest
.ssa
.num_components
== 2);
6106 def
= Definition(dst
);
6109 def
= Definition(dst
);
6112 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6115 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6117 Builder
bld(ctx
->program
, ctx
->block
);
6118 unsigned num_components
= instr
->num_components
;
6120 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6121 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6122 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6124 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6125 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6126 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6127 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6130 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6132 Builder
bld(ctx
->program
, ctx
->block
);
6133 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6134 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6135 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6136 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6138 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6139 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6141 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
6142 ctx
->options
->chip_class
>= GFX8
&&
6143 elem_size_bytes
>= 4;
6145 offset
= bld
.as_uniform(offset
);
6146 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6148 unsigned write_count
= 0;
6149 Temp write_datas
[32];
6150 unsigned offsets
[32];
6151 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6152 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6154 for (unsigned i
= 0; i
< write_count
; i
++) {
6155 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6156 if (smem
&& ctx
->stage
== fragment_fs
)
6157 op
= aco_opcode::p_fs_buffer_store_smem
;
6160 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6161 store
->operands
[0] = Operand(rsrc
);
6163 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6164 offset
, Operand(offsets
[i
]));
6165 store
->operands
[1] = Operand(off
);
6167 store
->operands
[1] = Operand(offset
);
6169 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6170 store
->operands
[1].setFixed(m0
);
6171 store
->operands
[2] = Operand(write_datas
[i
]);
6172 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6174 store
->disable_wqm
= true;
6175 store
->barrier
= barrier_buffer
;
6176 ctx
->block
->instructions
.emplace_back(std::move(store
));
6177 ctx
->program
->wb_smem_l1_on_end
= true;
6178 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6179 ctx
->block
->kind
|= block_kind_needs_lowering
;
6180 ctx
->program
->needs_exact
= true;
6183 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6184 store
->operands
[0] = Operand(rsrc
);
6185 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6186 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6187 store
->operands
[3] = Operand(write_datas
[i
]);
6188 store
->offset
= offsets
[i
];
6189 store
->offen
= (offset
.type() == RegType::vgpr
);
6190 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6192 store
->disable_wqm
= true;
6193 store
->barrier
= barrier_buffer
;
6194 ctx
->program
->needs_exact
= true;
6195 ctx
->block
->instructions
.emplace_back(std::move(store
));
6200 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6202 /* return the previous value if dest is ever used */
6203 bool return_previous
= false;
6204 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6205 return_previous
= true;
6208 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6209 return_previous
= true;
6213 Builder
bld(ctx
->program
, ctx
->block
);
6214 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6216 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6217 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6218 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6220 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6221 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6222 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6224 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6226 aco_opcode op32
, op64
;
6227 switch (instr
->intrinsic
) {
6228 case nir_intrinsic_ssbo_atomic_add
:
6229 op32
= aco_opcode::buffer_atomic_add
;
6230 op64
= aco_opcode::buffer_atomic_add_x2
;
6232 case nir_intrinsic_ssbo_atomic_imin
:
6233 op32
= aco_opcode::buffer_atomic_smin
;
6234 op64
= aco_opcode::buffer_atomic_smin_x2
;
6236 case nir_intrinsic_ssbo_atomic_umin
:
6237 op32
= aco_opcode::buffer_atomic_umin
;
6238 op64
= aco_opcode::buffer_atomic_umin_x2
;
6240 case nir_intrinsic_ssbo_atomic_imax
:
6241 op32
= aco_opcode::buffer_atomic_smax
;
6242 op64
= aco_opcode::buffer_atomic_smax_x2
;
6244 case nir_intrinsic_ssbo_atomic_umax
:
6245 op32
= aco_opcode::buffer_atomic_umax
;
6246 op64
= aco_opcode::buffer_atomic_umax_x2
;
6248 case nir_intrinsic_ssbo_atomic_and
:
6249 op32
= aco_opcode::buffer_atomic_and
;
6250 op64
= aco_opcode::buffer_atomic_and_x2
;
6252 case nir_intrinsic_ssbo_atomic_or
:
6253 op32
= aco_opcode::buffer_atomic_or
;
6254 op64
= aco_opcode::buffer_atomic_or_x2
;
6256 case nir_intrinsic_ssbo_atomic_xor
:
6257 op32
= aco_opcode::buffer_atomic_xor
;
6258 op64
= aco_opcode::buffer_atomic_xor_x2
;
6260 case nir_intrinsic_ssbo_atomic_exchange
:
6261 op32
= aco_opcode::buffer_atomic_swap
;
6262 op64
= aco_opcode::buffer_atomic_swap_x2
;
6264 case nir_intrinsic_ssbo_atomic_comp_swap
:
6265 op32
= aco_opcode::buffer_atomic_cmpswap
;
6266 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6269 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6271 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6272 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6273 mubuf
->operands
[0] = Operand(rsrc
);
6274 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6275 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6276 mubuf
->operands
[3] = Operand(data
);
6277 if (return_previous
)
6278 mubuf
->definitions
[0] = Definition(dst
);
6280 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6281 mubuf
->glc
= return_previous
;
6282 mubuf
->dlc
= false; /* Not needed for atomics */
6283 mubuf
->disable_wqm
= true;
6284 mubuf
->barrier
= barrier_buffer
;
6285 ctx
->program
->needs_exact
= true;
6286 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6289 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6291 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6292 Builder
bld(ctx
->program
, ctx
->block
);
6293 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6294 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6297 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6299 Builder
bld(ctx
->program
, ctx
->block
);
6300 unsigned num_components
= instr
->num_components
;
6301 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6303 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6304 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6305 num_components
, component_size
};
6306 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6307 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6308 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6309 info
.barrier
= barrier_buffer
;
6310 info
.can_reorder
= false;
6311 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6312 * it's safe to use SMEM */
6313 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6314 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6315 emit_global_load(ctx
, bld
, &info
);
6317 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6318 emit_smem_load(ctx
, bld
, &info
);
6322 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6324 Builder
bld(ctx
->program
, ctx
->block
);
6325 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6326 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6328 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6329 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6330 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6332 if (ctx
->options
->chip_class
>= GFX7
)
6333 addr
= as_vgpr(ctx
, addr
);
6335 unsigned write_count
= 0;
6336 Temp write_datas
[32];
6337 unsigned offsets
[32];
6338 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6339 16, &write_count
, write_datas
, offsets
);
6341 for (unsigned i
= 0; i
< write_count
; i
++) {
6342 if (ctx
->options
->chip_class
>= GFX7
) {
6343 unsigned offset
= offsets
[i
];
6344 Temp store_addr
= addr
;
6345 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6346 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6347 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6348 Temp carry
= bld
.tmp(bld
.lm
);
6349 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6351 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6352 Operand(offset
), addr0
);
6353 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6355 carry
).def(1).setHint(vcc
);
6357 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6362 bool global
= ctx
->options
->chip_class
>= GFX9
;
6364 switch (write_datas
[i
].bytes()) {
6366 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6369 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6372 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6375 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6378 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6381 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6384 unreachable("store_global not implemented for this size.");
6387 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6388 flat
->operands
[0] = Operand(store_addr
);
6389 flat
->operands
[1] = Operand(s1
);
6390 flat
->operands
[2] = Operand(write_datas
[i
]);
6393 flat
->offset
= offset
;
6394 flat
->disable_wqm
= true;
6395 flat
->barrier
= barrier_buffer
;
6396 ctx
->program
->needs_exact
= true;
6397 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6399 assert(ctx
->options
->chip_class
== GFX6
);
6401 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6403 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6405 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6406 mubuf
->operands
[0] = Operand(rsrc
);
6407 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6408 mubuf
->operands
[2] = Operand(0u);
6409 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6412 mubuf
->offset
= offsets
[i
];
6413 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6414 mubuf
->disable_wqm
= true;
6415 mubuf
->barrier
= barrier_buffer
;
6416 ctx
->program
->needs_exact
= true;
6417 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6422 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6424 /* return the previous value if dest is ever used */
6425 bool return_previous
= false;
6426 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6427 return_previous
= true;
6430 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6431 return_previous
= true;
6435 Builder
bld(ctx
->program
, ctx
->block
);
6436 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6437 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6439 if (ctx
->options
->chip_class
>= GFX7
)
6440 addr
= as_vgpr(ctx
, addr
);
6442 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6443 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6444 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6446 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6448 aco_opcode op32
, op64
;
6450 if (ctx
->options
->chip_class
>= GFX7
) {
6451 bool global
= ctx
->options
->chip_class
>= GFX9
;
6452 switch (instr
->intrinsic
) {
6453 case nir_intrinsic_global_atomic_add
:
6454 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6455 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6457 case nir_intrinsic_global_atomic_imin
:
6458 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6459 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6461 case nir_intrinsic_global_atomic_umin
:
6462 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6463 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6465 case nir_intrinsic_global_atomic_imax
:
6466 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6467 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6469 case nir_intrinsic_global_atomic_umax
:
6470 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6471 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6473 case nir_intrinsic_global_atomic_and
:
6474 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6475 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6477 case nir_intrinsic_global_atomic_or
:
6478 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6479 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6481 case nir_intrinsic_global_atomic_xor
:
6482 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6483 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6485 case nir_intrinsic_global_atomic_exchange
:
6486 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6487 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6489 case nir_intrinsic_global_atomic_comp_swap
:
6490 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6491 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6494 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6497 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6498 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6499 flat
->operands
[0] = Operand(addr
);
6500 flat
->operands
[1] = Operand(s1
);
6501 flat
->operands
[2] = Operand(data
);
6502 if (return_previous
)
6503 flat
->definitions
[0] = Definition(dst
);
6504 flat
->glc
= return_previous
;
6505 flat
->dlc
= false; /* Not needed for atomics */
6507 flat
->disable_wqm
= true;
6508 flat
->barrier
= barrier_buffer
;
6509 ctx
->program
->needs_exact
= true;
6510 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6512 assert(ctx
->options
->chip_class
== GFX6
);
6514 switch (instr
->intrinsic
) {
6515 case nir_intrinsic_global_atomic_add
:
6516 op32
= aco_opcode::buffer_atomic_add
;
6517 op64
= aco_opcode::buffer_atomic_add_x2
;
6519 case nir_intrinsic_global_atomic_imin
:
6520 op32
= aco_opcode::buffer_atomic_smin
;
6521 op64
= aco_opcode::buffer_atomic_smin_x2
;
6523 case nir_intrinsic_global_atomic_umin
:
6524 op32
= aco_opcode::buffer_atomic_umin
;
6525 op64
= aco_opcode::buffer_atomic_umin_x2
;
6527 case nir_intrinsic_global_atomic_imax
:
6528 op32
= aco_opcode::buffer_atomic_smax
;
6529 op64
= aco_opcode::buffer_atomic_smax_x2
;
6531 case nir_intrinsic_global_atomic_umax
:
6532 op32
= aco_opcode::buffer_atomic_umax
;
6533 op64
= aco_opcode::buffer_atomic_umax_x2
;
6535 case nir_intrinsic_global_atomic_and
:
6536 op32
= aco_opcode::buffer_atomic_and
;
6537 op64
= aco_opcode::buffer_atomic_and_x2
;
6539 case nir_intrinsic_global_atomic_or
:
6540 op32
= aco_opcode::buffer_atomic_or
;
6541 op64
= aco_opcode::buffer_atomic_or_x2
;
6543 case nir_intrinsic_global_atomic_xor
:
6544 op32
= aco_opcode::buffer_atomic_xor
;
6545 op64
= aco_opcode::buffer_atomic_xor_x2
;
6547 case nir_intrinsic_global_atomic_exchange
:
6548 op32
= aco_opcode::buffer_atomic_swap
;
6549 op64
= aco_opcode::buffer_atomic_swap_x2
;
6551 case nir_intrinsic_global_atomic_comp_swap
:
6552 op32
= aco_opcode::buffer_atomic_cmpswap
;
6553 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6556 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6559 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6561 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6563 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6564 mubuf
->operands
[0] = Operand(rsrc
);
6565 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6566 mubuf
->operands
[2] = Operand(0u);
6567 mubuf
->operands
[3] = Operand(data
);
6568 if (return_previous
)
6569 mubuf
->definitions
[0] = Definition(dst
);
6570 mubuf
->glc
= return_previous
;
6573 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6574 mubuf
->disable_wqm
= true;
6575 mubuf
->barrier
= barrier_buffer
;
6576 ctx
->program
->needs_exact
= true;
6577 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6581 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6582 Builder
bld(ctx
->program
, ctx
->block
);
6583 switch(instr
->intrinsic
) {
6584 case nir_intrinsic_group_memory_barrier
:
6585 case nir_intrinsic_memory_barrier
:
6586 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6588 case nir_intrinsic_memory_barrier_buffer
:
6589 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6591 case nir_intrinsic_memory_barrier_image
:
6592 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6594 case nir_intrinsic_memory_barrier_tcs_patch
:
6595 case nir_intrinsic_memory_barrier_shared
:
6596 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6599 unreachable("Unimplemented memory barrier intrinsic");
6604 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6606 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6607 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6608 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6609 Builder
bld(ctx
->program
, ctx
->block
);
6611 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6612 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6613 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6616 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6618 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6619 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6620 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6621 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6623 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6624 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6627 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6629 unsigned offset
= nir_intrinsic_base(instr
);
6630 Builder
bld(ctx
->program
, ctx
->block
);
6631 Operand m
= load_lds_size_m0(bld
);
6632 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6633 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6635 unsigned num_operands
= 3;
6636 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6637 switch(instr
->intrinsic
) {
6638 case nir_intrinsic_shared_atomic_add
:
6639 op32
= aco_opcode::ds_add_u32
;
6640 op64
= aco_opcode::ds_add_u64
;
6641 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6642 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6644 case nir_intrinsic_shared_atomic_imin
:
6645 op32
= aco_opcode::ds_min_i32
;
6646 op64
= aco_opcode::ds_min_i64
;
6647 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6648 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6650 case nir_intrinsic_shared_atomic_umin
:
6651 op32
= aco_opcode::ds_min_u32
;
6652 op64
= aco_opcode::ds_min_u64
;
6653 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6654 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6656 case nir_intrinsic_shared_atomic_imax
:
6657 op32
= aco_opcode::ds_max_i32
;
6658 op64
= aco_opcode::ds_max_i64
;
6659 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6660 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6662 case nir_intrinsic_shared_atomic_umax
:
6663 op32
= aco_opcode::ds_max_u32
;
6664 op64
= aco_opcode::ds_max_u64
;
6665 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6666 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6668 case nir_intrinsic_shared_atomic_and
:
6669 op32
= aco_opcode::ds_and_b32
;
6670 op64
= aco_opcode::ds_and_b64
;
6671 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6672 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6674 case nir_intrinsic_shared_atomic_or
:
6675 op32
= aco_opcode::ds_or_b32
;
6676 op64
= aco_opcode::ds_or_b64
;
6677 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6678 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6680 case nir_intrinsic_shared_atomic_xor
:
6681 op32
= aco_opcode::ds_xor_b32
;
6682 op64
= aco_opcode::ds_xor_b64
;
6683 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6684 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6686 case nir_intrinsic_shared_atomic_exchange
:
6687 op32
= aco_opcode::ds_write_b32
;
6688 op64
= aco_opcode::ds_write_b64
;
6689 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6690 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6692 case nir_intrinsic_shared_atomic_comp_swap
:
6693 op32
= aco_opcode::ds_cmpst_b32
;
6694 op64
= aco_opcode::ds_cmpst_b64
;
6695 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6696 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6700 unreachable("Unhandled shared atomic intrinsic");
6703 /* return the previous value if dest is ever used */
6704 bool return_previous
= false;
6705 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6706 return_previous
= true;
6709 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6710 return_previous
= true;
6715 if (data
.size() == 1) {
6716 assert(instr
->dest
.ssa
.bit_size
== 32);
6717 op
= return_previous
? op32_rtn
: op32
;
6719 assert(instr
->dest
.ssa
.bit_size
== 64);
6720 op
= return_previous
? op64_rtn
: op64
;
6723 if (offset
> 65535) {
6724 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6728 aco_ptr
<DS_instruction
> ds
;
6729 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6730 ds
->operands
[0] = Operand(address
);
6731 ds
->operands
[1] = Operand(data
);
6732 if (num_operands
== 4)
6733 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6734 ds
->operands
[num_operands
- 1] = m
;
6735 ds
->offset0
= offset
;
6736 if (return_previous
)
6737 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6738 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6741 Temp
get_scratch_resource(isel_context
*ctx
)
6743 Builder
bld(ctx
->program
, ctx
->block
);
6744 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6745 if (ctx
->stage
!= compute_cs
)
6746 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6748 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6749 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6751 if (ctx
->program
->chip_class
>= GFX10
) {
6752 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6753 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6754 S_008F0C_RESOURCE_LEVEL(1);
6755 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6756 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6757 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6760 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6761 if (ctx
->program
->chip_class
<= GFX8
)
6762 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6764 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6767 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6768 Builder
bld(ctx
->program
, ctx
->block
);
6769 Temp rsrc
= get_scratch_resource(ctx
);
6770 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6771 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6773 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6774 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6775 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6776 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6777 info
.swizzle_component_size
= 16;
6778 info
.can_reorder
= false;
6779 info
.soffset
= ctx
->program
->scratch_offset
;
6780 emit_mubuf_load(ctx
, bld
, &info
);
6783 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6784 Builder
bld(ctx
->program
, ctx
->block
);
6785 Temp rsrc
= get_scratch_resource(ctx
);
6786 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6787 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6789 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6790 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6792 unsigned write_count
= 0;
6793 Temp write_datas
[32];
6794 unsigned offsets
[32];
6795 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6796 16, &write_count
, write_datas
, offsets
);
6798 for (unsigned i
= 0; i
< write_count
; i
++) {
6799 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6800 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6804 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6805 uint8_t log2_ps_iter_samples
;
6806 if (ctx
->program
->info
->ps
.force_persample
) {
6807 log2_ps_iter_samples
=
6808 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6810 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6813 /* The bit pattern matches that used by fixed function fragment
6815 static const unsigned ps_iter_masks
[] = {
6816 0xffff, /* not used */
6822 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6824 Builder
bld(ctx
->program
, ctx
->block
);
6826 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6827 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6828 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6829 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6830 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6831 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6834 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6835 Builder
bld(ctx
->program
, ctx
->block
);
6837 unsigned stream
= nir_intrinsic_stream_id(instr
);
6838 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6839 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6840 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6843 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6845 unsigned num_components
=
6846 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6847 assert(num_components
);
6849 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6850 unsigned stream_offset
= 0;
6851 for (unsigned i
= 0; i
< stream
; i
++) {
6852 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6853 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6856 /* Limit on the stride field for <= GFX7. */
6857 assert(stride
< (1 << 14));
6859 Temp gsvs_dwords
[4];
6860 for (unsigned i
= 0; i
< 4; i
++)
6861 gsvs_dwords
[i
] = bld
.tmp(s1
);
6862 bld
.pseudo(aco_opcode::p_split_vector
,
6863 Definition(gsvs_dwords
[0]),
6864 Definition(gsvs_dwords
[1]),
6865 Definition(gsvs_dwords
[2]),
6866 Definition(gsvs_dwords
[3]),
6869 if (stream_offset
) {
6870 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6872 Temp carry
= bld
.tmp(s1
);
6873 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6874 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6877 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6878 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6880 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6881 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6883 unsigned offset
= 0;
6884 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6885 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6888 for (unsigned j
= 0; j
< 4; j
++) {
6889 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6892 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6893 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6894 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6895 if (const_offset
>= 4096u) {
6896 if (vaddr_offset
.isUndefined())
6897 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6899 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6900 const_offset
%= 4096u;
6903 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6904 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6905 mtbuf
->operands
[1] = vaddr_offset
;
6906 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6907 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6908 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6909 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6910 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6911 mtbuf
->offset
= const_offset
;
6914 mtbuf
->barrier
= barrier_gs_data
;
6915 mtbuf
->can_reorder
= true;
6916 bld
.insert(std::move(mtbuf
));
6919 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6922 /* outputs for the next vertex are undefined and keeping them around can
6923 * create invalid IR with control flow */
6924 ctx
->outputs
.mask
[i
] = 0;
6927 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6930 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6932 Builder
bld(ctx
->program
, ctx
->block
);
6934 if (cluster_size
== 1) {
6936 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6937 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6938 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6939 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6940 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6941 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6942 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6943 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6944 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6945 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6946 //subgroupAnd(val) -> (exec & ~val) == 0
6947 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6948 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6949 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6950 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6951 //subgroupOr(val) -> (val & exec) != 0
6952 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6953 return bool_to_vector_condition(ctx
, tmp
);
6954 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6955 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6956 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6957 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6958 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6959 return bool_to_vector_condition(ctx
, tmp
);
6961 //subgroupClustered{And,Or,Xor}(val, n) ->
6962 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6963 //cluster_offset = ~(n - 1) & lane_id
6964 //cluster_mask = ((1 << n) - 1)
6965 //subgroupClusteredAnd():
6966 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6967 //subgroupClusteredOr():
6968 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6969 //subgroupClusteredXor():
6970 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6971 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6972 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6975 if (op
== nir_op_iand
)
6976 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6978 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6980 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6982 if (ctx
->program
->chip_class
<= GFX7
)
6983 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6984 else if (ctx
->program
->wave_size
== 64)
6985 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6987 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6988 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6989 if (cluster_mask
!= 0xffffffff)
6990 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6992 Definition cmp_def
= Definition();
6993 if (op
== nir_op_iand
) {
6994 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6995 } else if (op
== nir_op_ior
) {
6996 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6997 } else if (op
== nir_op_ixor
) {
6998 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6999 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7000 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7002 cmp_def
.setHint(vcc
);
7003 return cmp_def
.getTemp();
7007 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7009 Builder
bld(ctx
->program
, ctx
->block
);
7011 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7012 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7013 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7015 if (op
== nir_op_iand
)
7016 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7018 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7020 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7021 Temp lo
= lohi
.def(0).getTemp();
7022 Temp hi
= lohi
.def(1).getTemp();
7023 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7025 Definition cmp_def
= Definition();
7026 if (op
== nir_op_iand
)
7027 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7028 else if (op
== nir_op_ior
)
7029 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7030 else if (op
== nir_op_ixor
)
7031 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7032 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7033 cmp_def
.setHint(vcc
);
7034 return cmp_def
.getTemp();
7037 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7039 Builder
bld(ctx
->program
, ctx
->block
);
7041 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7042 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7043 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7044 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7045 if (op
== nir_op_iand
)
7046 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7047 else if (op
== nir_op_ior
)
7048 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7049 else if (op
== nir_op_ixor
)
7050 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7056 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7058 Builder
bld(ctx
->program
, ctx
->block
);
7059 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7060 if (src
.regClass().type() == RegType::vgpr
) {
7061 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7062 } else if (src
.regClass() == s1
) {
7063 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7064 } else if (src
.regClass() == s2
) {
7065 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7068 nir_print_instr(&instr
->instr
, stderr
);
7069 fprintf(stderr
, "\n");
7073 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7075 Builder
bld(ctx
->program
, ctx
->block
);
7076 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7077 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7078 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7080 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7081 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7082 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7083 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7086 if (ctx
->program
->chip_class
>= GFX8
) {
7087 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7088 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7089 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7090 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7091 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7092 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7094 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7095 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7096 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7097 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7098 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7099 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7100 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7101 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7102 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7103 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7106 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7107 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7108 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7109 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7110 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7111 Temp wqm1
= bld
.tmp(v1
);
7112 emit_wqm(ctx
, tmp1
, wqm1
, true);
7113 Temp wqm2
= bld
.tmp(v1
);
7114 emit_wqm(ctx
, tmp2
, wqm2
, true);
7115 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7119 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7121 Builder
bld(ctx
->program
, ctx
->block
);
7122 switch(instr
->intrinsic
) {
7123 case nir_intrinsic_load_barycentric_sample
:
7124 case nir_intrinsic_load_barycentric_pixel
:
7125 case nir_intrinsic_load_barycentric_centroid
: {
7126 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7127 Temp bary
= Temp(0, s2
);
7129 case INTERP_MODE_SMOOTH
:
7130 case INTERP_MODE_NONE
:
7131 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7132 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7133 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7134 bary
= ctx
->persp_centroid
;
7135 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7136 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7138 case INTERP_MODE_NOPERSPECTIVE
:
7139 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7140 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7141 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7142 bary
= ctx
->linear_centroid
;
7143 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7144 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7150 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7151 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7153 Operand(p1
), Operand(p2
));
7154 emit_split_vector(ctx
, dst
, 2);
7157 case nir_intrinsic_load_barycentric_model
: {
7158 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7160 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7161 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7162 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7163 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7164 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7165 Operand(p1
), Operand(p2
), Operand(p3
));
7166 emit_split_vector(ctx
, dst
, 3);
7169 case nir_intrinsic_load_barycentric_at_sample
: {
7170 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7171 switch (ctx
->options
->key
.fs
.num_samples
) {
7172 case 2: sample_pos_offset
+= 1 << 3; break;
7173 case 4: sample_pos_offset
+= 3 << 3; break;
7174 case 8: sample_pos_offset
+= 7 << 3; break;
7178 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7179 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7180 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7181 if (addr
.type() == RegType::sgpr
) {
7184 sample_pos_offset
+= const_addr
->u32
<< 3;
7185 offset
= Operand(sample_pos_offset
);
7186 } else if (ctx
->options
->chip_class
>= GFX9
) {
7187 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7189 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7190 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7193 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7194 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7196 } else if (ctx
->options
->chip_class
>= GFX9
) {
7197 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7198 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7199 } else if (ctx
->options
->chip_class
>= GFX7
) {
7200 /* addr += private_segment_buffer + sample_pos_offset */
7201 Temp tmp0
= bld
.tmp(s1
);
7202 Temp tmp1
= bld
.tmp(s1
);
7203 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7204 Definition scc_tmp
= bld
.def(s1
, scc
);
7205 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7206 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7207 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7208 Temp pck0
= bld
.tmp(v1
);
7209 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7210 tmp1
= as_vgpr(ctx
, tmp1
);
7211 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7212 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7214 /* sample_pos = flat_load_dwordx2 addr */
7215 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7217 assert(ctx
->options
->chip_class
== GFX6
);
7219 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7220 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7221 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7223 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7224 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7226 sample_pos
= bld
.tmp(v2
);
7228 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7229 load
->definitions
[0] = Definition(sample_pos
);
7230 load
->operands
[0] = Operand(rsrc
);
7231 load
->operands
[1] = Operand(addr
);
7232 load
->operands
[2] = Operand(0u);
7233 load
->offset
= sample_pos_offset
;
7235 load
->addr64
= true;
7238 load
->disable_wqm
= false;
7239 load
->barrier
= barrier_none
;
7240 load
->can_reorder
= true;
7241 ctx
->block
->instructions
.emplace_back(std::move(load
));
7244 /* sample_pos -= 0.5 */
7245 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7246 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7247 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7248 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7249 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7251 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7254 case nir_intrinsic_load_barycentric_at_offset
: {
7255 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7256 RegClass rc
= RegClass(offset
.type(), 1);
7257 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7258 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7259 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7262 case nir_intrinsic_load_front_face
: {
7263 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7264 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7267 case nir_intrinsic_load_view_index
: {
7268 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7269 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7270 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7276 case nir_intrinsic_load_layer_id
: {
7277 unsigned idx
= nir_intrinsic_base(instr
);
7278 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7279 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7282 case nir_intrinsic_load_frag_coord
: {
7283 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7286 case nir_intrinsic_load_sample_pos
: {
7287 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7288 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7289 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7290 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7291 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7294 case nir_intrinsic_load_tess_coord
:
7295 visit_load_tess_coord(ctx
, instr
);
7297 case nir_intrinsic_load_interpolated_input
:
7298 visit_load_interpolated_input(ctx
, instr
);
7300 case nir_intrinsic_store_output
:
7301 visit_store_output(ctx
, instr
);
7303 case nir_intrinsic_load_input
:
7304 case nir_intrinsic_load_input_vertex
:
7305 visit_load_input(ctx
, instr
);
7307 case nir_intrinsic_load_output
:
7308 visit_load_output(ctx
, instr
);
7310 case nir_intrinsic_load_per_vertex_input
:
7311 visit_load_per_vertex_input(ctx
, instr
);
7313 case nir_intrinsic_load_per_vertex_output
:
7314 visit_load_per_vertex_output(ctx
, instr
);
7316 case nir_intrinsic_store_per_vertex_output
:
7317 visit_store_per_vertex_output(ctx
, instr
);
7319 case nir_intrinsic_load_ubo
:
7320 visit_load_ubo(ctx
, instr
);
7322 case nir_intrinsic_load_push_constant
:
7323 visit_load_push_constant(ctx
, instr
);
7325 case nir_intrinsic_load_constant
:
7326 visit_load_constant(ctx
, instr
);
7328 case nir_intrinsic_vulkan_resource_index
:
7329 visit_load_resource(ctx
, instr
);
7331 case nir_intrinsic_discard
:
7332 visit_discard(ctx
, instr
);
7334 case nir_intrinsic_discard_if
:
7335 visit_discard_if(ctx
, instr
);
7337 case nir_intrinsic_load_shared
:
7338 visit_load_shared(ctx
, instr
);
7340 case nir_intrinsic_store_shared
:
7341 visit_store_shared(ctx
, instr
);
7343 case nir_intrinsic_shared_atomic_add
:
7344 case nir_intrinsic_shared_atomic_imin
:
7345 case nir_intrinsic_shared_atomic_umin
:
7346 case nir_intrinsic_shared_atomic_imax
:
7347 case nir_intrinsic_shared_atomic_umax
:
7348 case nir_intrinsic_shared_atomic_and
:
7349 case nir_intrinsic_shared_atomic_or
:
7350 case nir_intrinsic_shared_atomic_xor
:
7351 case nir_intrinsic_shared_atomic_exchange
:
7352 case nir_intrinsic_shared_atomic_comp_swap
:
7353 visit_shared_atomic(ctx
, instr
);
7355 case nir_intrinsic_image_deref_load
:
7356 visit_image_load(ctx
, instr
);
7358 case nir_intrinsic_image_deref_store
:
7359 visit_image_store(ctx
, instr
);
7361 case nir_intrinsic_image_deref_atomic_add
:
7362 case nir_intrinsic_image_deref_atomic_umin
:
7363 case nir_intrinsic_image_deref_atomic_imin
:
7364 case nir_intrinsic_image_deref_atomic_umax
:
7365 case nir_intrinsic_image_deref_atomic_imax
:
7366 case nir_intrinsic_image_deref_atomic_and
:
7367 case nir_intrinsic_image_deref_atomic_or
:
7368 case nir_intrinsic_image_deref_atomic_xor
:
7369 case nir_intrinsic_image_deref_atomic_exchange
:
7370 case nir_intrinsic_image_deref_atomic_comp_swap
:
7371 visit_image_atomic(ctx
, instr
);
7373 case nir_intrinsic_image_deref_size
:
7374 visit_image_size(ctx
, instr
);
7376 case nir_intrinsic_load_ssbo
:
7377 visit_load_ssbo(ctx
, instr
);
7379 case nir_intrinsic_store_ssbo
:
7380 visit_store_ssbo(ctx
, instr
);
7382 case nir_intrinsic_load_global
:
7383 visit_load_global(ctx
, instr
);
7385 case nir_intrinsic_store_global
:
7386 visit_store_global(ctx
, instr
);
7388 case nir_intrinsic_global_atomic_add
:
7389 case nir_intrinsic_global_atomic_imin
:
7390 case nir_intrinsic_global_atomic_umin
:
7391 case nir_intrinsic_global_atomic_imax
:
7392 case nir_intrinsic_global_atomic_umax
:
7393 case nir_intrinsic_global_atomic_and
:
7394 case nir_intrinsic_global_atomic_or
:
7395 case nir_intrinsic_global_atomic_xor
:
7396 case nir_intrinsic_global_atomic_exchange
:
7397 case nir_intrinsic_global_atomic_comp_swap
:
7398 visit_global_atomic(ctx
, instr
);
7400 case nir_intrinsic_ssbo_atomic_add
:
7401 case nir_intrinsic_ssbo_atomic_imin
:
7402 case nir_intrinsic_ssbo_atomic_umin
:
7403 case nir_intrinsic_ssbo_atomic_imax
:
7404 case nir_intrinsic_ssbo_atomic_umax
:
7405 case nir_intrinsic_ssbo_atomic_and
:
7406 case nir_intrinsic_ssbo_atomic_or
:
7407 case nir_intrinsic_ssbo_atomic_xor
:
7408 case nir_intrinsic_ssbo_atomic_exchange
:
7409 case nir_intrinsic_ssbo_atomic_comp_swap
:
7410 visit_atomic_ssbo(ctx
, instr
);
7412 case nir_intrinsic_load_scratch
:
7413 visit_load_scratch(ctx
, instr
);
7415 case nir_intrinsic_store_scratch
:
7416 visit_store_scratch(ctx
, instr
);
7418 case nir_intrinsic_get_buffer_size
:
7419 visit_get_buffer_size(ctx
, instr
);
7421 case nir_intrinsic_control_barrier
: {
7422 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7423 /* GFX6 only (thanks to a hw bug workaround):
7424 * The real barrier instruction isn’t needed, because an entire patch
7425 * always fits into a single wave.
7430 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7431 bld
.sopp(aco_opcode::s_barrier
);
7435 case nir_intrinsic_memory_barrier_tcs_patch
:
7436 case nir_intrinsic_group_memory_barrier
:
7437 case nir_intrinsic_memory_barrier
:
7438 case nir_intrinsic_memory_barrier_buffer
:
7439 case nir_intrinsic_memory_barrier_image
:
7440 case nir_intrinsic_memory_barrier_shared
:
7441 emit_memory_barrier(ctx
, instr
);
7443 case nir_intrinsic_load_num_work_groups
: {
7444 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7445 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7446 emit_split_vector(ctx
, dst
, 3);
7449 case nir_intrinsic_load_local_invocation_id
: {
7450 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7451 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7452 emit_split_vector(ctx
, dst
, 3);
7455 case nir_intrinsic_load_work_group_id
: {
7456 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7457 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7458 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7459 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7460 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7461 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7462 emit_split_vector(ctx
, dst
, 3);
7465 case nir_intrinsic_load_local_invocation_index
: {
7466 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7468 /* The tg_size bits [6:11] contain the subgroup id,
7469 * we need this multiplied by the wave size, and then OR the thread id to it.
7471 if (ctx
->program
->wave_size
== 64) {
7472 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7473 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7474 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7475 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7477 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7478 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7479 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7480 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7484 case nir_intrinsic_load_subgroup_id
: {
7485 if (ctx
->stage
== compute_cs
) {
7486 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7487 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7489 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7493 case nir_intrinsic_load_subgroup_invocation
: {
7494 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7497 case nir_intrinsic_load_num_subgroups
: {
7498 if (ctx
->stage
== compute_cs
)
7499 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7500 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7502 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7505 case nir_intrinsic_ballot
: {
7506 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7507 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7508 Definition tmp
= bld
.def(dst
.regClass());
7509 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7510 if (instr
->src
[0].ssa
->bit_size
== 1) {
7511 assert(src
.regClass() == bld
.lm
);
7512 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7513 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7514 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7515 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7516 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7518 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7519 nir_print_instr(&instr
->instr
, stderr
);
7520 fprintf(stderr
, "\n");
7522 if (dst
.size() != bld
.lm
.size()) {
7523 /* Wave32 with ballot size set to 64 */
7524 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7526 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7529 case nir_intrinsic_shuffle
:
7530 case nir_intrinsic_read_invocation
: {
7531 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7532 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7533 emit_uniform_subgroup(ctx
, instr
, src
);
7535 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7536 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7537 tid
= bld
.as_uniform(tid
);
7538 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7539 if (src
.regClass() == v1
) {
7540 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7541 } else if (src
.regClass() == v2
) {
7542 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7543 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7544 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7545 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7546 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7547 emit_split_vector(ctx
, dst
, 2);
7548 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7549 assert(src
.regClass() == bld
.lm
);
7550 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7551 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7552 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7553 assert(src
.regClass() == bld
.lm
);
7555 if (ctx
->program
->chip_class
<= GFX7
)
7556 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7557 else if (ctx
->program
->wave_size
== 64)
7558 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7560 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7561 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7562 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7563 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7565 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7566 nir_print_instr(&instr
->instr
, stderr
);
7567 fprintf(stderr
, "\n");
7572 case nir_intrinsic_load_sample_id
: {
7573 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7574 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7577 case nir_intrinsic_load_sample_mask_in
: {
7578 visit_load_sample_mask_in(ctx
, instr
);
7581 case nir_intrinsic_read_first_invocation
: {
7582 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7583 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7584 if (src
.regClass() == v1
) {
7586 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7588 } else if (src
.regClass() == v2
) {
7589 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7590 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7591 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7592 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7594 emit_split_vector(ctx
, dst
, 2);
7595 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7596 assert(src
.regClass() == bld
.lm
);
7597 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7598 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7599 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7600 } else if (src
.regClass() == s1
) {
7601 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7602 } else if (src
.regClass() == s2
) {
7603 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7606 nir_print_instr(&instr
->instr
, stderr
);
7607 fprintf(stderr
, "\n");
7611 case nir_intrinsic_vote_all
: {
7612 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7613 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7614 assert(src
.regClass() == bld
.lm
);
7615 assert(dst
.regClass() == bld
.lm
);
7617 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7618 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7619 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7622 case nir_intrinsic_vote_any
: {
7623 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7624 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7625 assert(src
.regClass() == bld
.lm
);
7626 assert(dst
.regClass() == bld
.lm
);
7628 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7629 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7632 case nir_intrinsic_reduce
:
7633 case nir_intrinsic_inclusive_scan
:
7634 case nir_intrinsic_exclusive_scan
: {
7635 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7636 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7637 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7638 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7639 nir_intrinsic_cluster_size(instr
) : 0;
7640 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7642 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7643 emit_uniform_subgroup(ctx
, instr
, src
);
7644 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7645 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7647 else if (op
== nir_op_iadd
)
7649 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7651 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7653 switch (instr
->intrinsic
) {
7654 case nir_intrinsic_reduce
:
7655 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7657 case nir_intrinsic_exclusive_scan
:
7658 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7660 case nir_intrinsic_inclusive_scan
:
7661 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7666 } else if (cluster_size
== 1) {
7667 bld
.copy(Definition(dst
), src
);
7669 src
= as_vgpr(ctx
, src
);
7673 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7688 unreachable("unknown reduction op");
7693 switch (instr
->intrinsic
) {
7694 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7695 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7696 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7698 unreachable("unknown reduce intrinsic");
7701 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7702 reduce
->operands
[0] = Operand(src
);
7703 // filled in by aco_reduce_assign.cpp, used internally as part of the
7705 assert(dst
.size() == 1 || dst
.size() == 2);
7706 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7707 reduce
->operands
[2] = Operand(v1
.as_linear());
7709 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7710 reduce
->definitions
[0] = Definition(tmp_dst
);
7711 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7712 reduce
->definitions
[2] = Definition();
7713 reduce
->definitions
[3] = Definition(scc
, s1
);
7714 reduce
->definitions
[4] = Definition();
7715 reduce
->reduce_op
= reduce_op
;
7716 reduce
->cluster_size
= cluster_size
;
7717 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7719 emit_wqm(ctx
, tmp_dst
, dst
);
7723 case nir_intrinsic_quad_broadcast
: {
7724 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7725 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7726 emit_uniform_subgroup(ctx
, instr
, src
);
7728 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7729 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7730 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7732 if (instr
->dest
.ssa
.bit_size
== 1) {
7733 assert(src
.regClass() == bld
.lm
);
7734 assert(dst
.regClass() == bld
.lm
);
7735 uint32_t half_mask
= 0x11111111u
<< lane
;
7736 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7737 Temp tmp
= bld
.tmp(bld
.lm
);
7738 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7739 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7740 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7741 emit_wqm(ctx
, tmp
, dst
);
7742 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7743 if (ctx
->program
->chip_class
>= GFX8
)
7744 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7746 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7747 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7748 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7749 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7750 if (ctx
->program
->chip_class
>= GFX8
) {
7751 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7752 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7754 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7755 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7758 emit_split_vector(ctx
, dst
, 2);
7760 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7761 nir_print_instr(&instr
->instr
, stderr
);
7762 fprintf(stderr
, "\n");
7767 case nir_intrinsic_quad_swap_horizontal
:
7768 case nir_intrinsic_quad_swap_vertical
:
7769 case nir_intrinsic_quad_swap_diagonal
:
7770 case nir_intrinsic_quad_swizzle_amd
: {
7771 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7772 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7773 emit_uniform_subgroup(ctx
, instr
, src
);
7776 uint16_t dpp_ctrl
= 0;
7777 switch (instr
->intrinsic
) {
7778 case nir_intrinsic_quad_swap_horizontal
:
7779 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7781 case nir_intrinsic_quad_swap_vertical
:
7782 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7784 case nir_intrinsic_quad_swap_diagonal
:
7785 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7787 case nir_intrinsic_quad_swizzle_amd
:
7788 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7793 if (ctx
->program
->chip_class
< GFX8
)
7794 dpp_ctrl
|= (1 << 15);
7796 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7797 if (instr
->dest
.ssa
.bit_size
== 1) {
7798 assert(src
.regClass() == bld
.lm
);
7799 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7800 if (ctx
->program
->chip_class
>= GFX8
)
7801 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7803 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7804 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7805 emit_wqm(ctx
, tmp
, dst
);
7806 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7808 if (ctx
->program
->chip_class
>= GFX8
)
7809 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7811 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7812 emit_wqm(ctx
, tmp
, dst
);
7813 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7814 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7815 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7816 if (ctx
->program
->chip_class
>= GFX8
) {
7817 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7818 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7820 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7821 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7823 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7824 emit_split_vector(ctx
, dst
, 2);
7826 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7827 nir_print_instr(&instr
->instr
, stderr
);
7828 fprintf(stderr
, "\n");
7832 case nir_intrinsic_masked_swizzle_amd
: {
7833 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7834 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7835 emit_uniform_subgroup(ctx
, instr
, src
);
7838 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7839 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7840 if (dst
.regClass() == v1
) {
7842 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7844 } else if (dst
.regClass() == v2
) {
7845 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7846 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7847 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7848 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7849 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7850 emit_split_vector(ctx
, dst
, 2);
7852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7853 nir_print_instr(&instr
->instr
, stderr
);
7854 fprintf(stderr
, "\n");
7858 case nir_intrinsic_write_invocation_amd
: {
7859 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7860 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7861 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7862 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7863 if (dst
.regClass() == v1
) {
7864 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7865 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7866 } else if (dst
.regClass() == v2
) {
7867 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7868 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7869 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7870 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7871 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7872 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7873 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7874 emit_split_vector(ctx
, dst
, 2);
7876 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7877 nir_print_instr(&instr
->instr
, stderr
);
7878 fprintf(stderr
, "\n");
7882 case nir_intrinsic_mbcnt_amd
: {
7883 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7884 RegClass rc
= RegClass(src
.type(), 1);
7885 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7886 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7887 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7888 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7889 emit_wqm(ctx
, wqm_tmp
, dst
);
7892 case nir_intrinsic_load_helper_invocation
: {
7893 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7894 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7895 ctx
->block
->kind
|= block_kind_needs_lowering
;
7896 ctx
->program
->needs_exact
= true;
7899 case nir_intrinsic_is_helper_invocation
: {
7900 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7901 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7902 ctx
->block
->kind
|= block_kind_needs_lowering
;
7903 ctx
->program
->needs_exact
= true;
7906 case nir_intrinsic_demote
:
7907 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7909 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7910 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7911 ctx
->block
->kind
|= block_kind_uses_demote
;
7912 ctx
->program
->needs_exact
= true;
7914 case nir_intrinsic_demote_if
: {
7915 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7916 assert(src
.regClass() == bld
.lm
);
7917 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7918 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7920 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7921 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7922 ctx
->block
->kind
|= block_kind_uses_demote
;
7923 ctx
->program
->needs_exact
= true;
7926 case nir_intrinsic_first_invocation
: {
7927 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7928 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7931 case nir_intrinsic_shader_clock
:
7932 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7933 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7935 case nir_intrinsic_load_vertex_id_zero_base
: {
7936 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7937 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7940 case nir_intrinsic_load_first_vertex
: {
7941 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7942 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7945 case nir_intrinsic_load_base_instance
: {
7946 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7947 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7950 case nir_intrinsic_load_instance_id
: {
7951 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7952 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7955 case nir_intrinsic_load_draw_id
: {
7956 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7957 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7960 case nir_intrinsic_load_invocation_id
: {
7961 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7963 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7964 if (ctx
->options
->chip_class
>= GFX10
)
7965 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7967 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7968 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7969 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7970 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7972 unreachable("Unsupported stage for load_invocation_id");
7977 case nir_intrinsic_load_primitive_id
: {
7978 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7980 switch (ctx
->shader
->info
.stage
) {
7981 case MESA_SHADER_GEOMETRY
:
7982 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7984 case MESA_SHADER_TESS_CTRL
:
7985 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7987 case MESA_SHADER_TESS_EVAL
:
7988 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7991 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7996 case nir_intrinsic_load_patch_vertices_in
: {
7997 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7998 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8000 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8001 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8004 case nir_intrinsic_emit_vertex_with_counter
: {
8005 visit_emit_vertex_with_counter(ctx
, instr
);
8008 case nir_intrinsic_end_primitive_with_counter
: {
8009 unsigned stream
= nir_intrinsic_stream_id(instr
);
8010 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8013 case nir_intrinsic_set_vertex_count
: {
8014 /* unused, the HW keeps track of this for us */
8018 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8019 nir_print_instr(&instr
->instr
, stderr
);
8020 fprintf(stderr
, "\n");
8028 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8029 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8030 enum glsl_base_type
*stype
)
8032 nir_deref_instr
*texture_deref_instr
= NULL
;
8033 nir_deref_instr
*sampler_deref_instr
= NULL
;
8036 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8037 switch (instr
->src
[i
].src_type
) {
8038 case nir_tex_src_texture_deref
:
8039 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8041 case nir_tex_src_sampler_deref
:
8042 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8044 case nir_tex_src_plane
:
8045 plane
= nir_src_as_int(instr
->src
[i
].src
);
8052 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8054 if (!sampler_deref_instr
)
8055 sampler_deref_instr
= texture_deref_instr
;
8058 assert(instr
->op
!= nir_texop_txf_ms
&&
8059 instr
->op
!= nir_texop_samples_identical
);
8060 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8061 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8062 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8063 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8064 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8065 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8067 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8070 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8072 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8073 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8074 Builder
bld(ctx
->program
, ctx
->block
);
8076 /* to avoid unnecessary moves, we split and recombine sampler and image */
8077 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8078 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8079 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8080 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8081 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8082 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8083 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8084 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8086 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8087 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8088 img
[0], img
[1], img
[2], img
[3],
8089 img
[4], img
[5], img
[6], img
[7]);
8090 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8091 samp
[0], samp
[1], samp
[2], samp
[3]);
8094 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8095 instr
->op
== nir_texop_samples_identical
))
8096 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8099 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8100 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8102 Builder
bld(ctx
->program
, ctx
->block
);
8104 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8105 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8106 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8108 Operand
neg_one(0xbf800000u
);
8109 Operand
one(0x3f800000u
);
8110 Operand
two(0x40000000u
);
8111 Operand
four(0x40800000u
);
8113 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8114 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8115 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8117 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8118 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8119 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8120 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8123 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8124 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8125 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8127 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8130 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8131 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8132 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8135 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8136 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8138 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8139 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8142 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8144 Builder
bld(ctx
->program
, ctx
->block
);
8145 Temp ma
, tc
, sc
, id
;
8148 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8150 // see comment in ac_prepare_cube_coords()
8151 if (ctx
->options
->chip_class
<= GFX8
)
8152 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8155 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8157 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8158 vop3a
->operands
[0] = Operand(ma
);
8159 vop3a
->abs
[0] = true;
8160 Temp invma
= bld
.tmp(v1
);
8161 vop3a
->definitions
[0] = Definition(invma
);
8162 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8164 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8166 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8168 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8170 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8172 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8175 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8176 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8178 for (unsigned i
= 0; i
< 2; i
++) {
8179 // see comment in ac_prepare_cube_coords()
8181 Temp deriv_sc
, deriv_tc
;
8182 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8183 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8185 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8187 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8188 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8189 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8190 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8191 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8192 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8193 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8196 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8197 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8201 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8208 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8210 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8212 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8213 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8216 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8217 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8218 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8222 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8224 Builder
bld(ctx
->program
, ctx
->block
);
8225 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8226 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8227 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8228 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8229 std::vector
<Temp
> coords
;
8230 std::vector
<Temp
> derivs
;
8231 nir_const_value
*sample_index_cv
= NULL
;
8232 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8233 enum glsl_base_type stype
;
8234 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8236 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8237 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8238 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8239 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8241 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8242 switch (instr
->src
[i
].src_type
) {
8243 case nir_tex_src_coord
: {
8244 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8245 for (unsigned i
= 0; i
< coord
.size(); i
++)
8246 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8249 case nir_tex_src_bias
:
8250 if (instr
->op
== nir_texop_txb
) {
8251 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8255 case nir_tex_src_lod
: {
8256 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8258 if (val
&& val
->f32
<= 0.0) {
8261 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8266 case nir_tex_src_comparator
:
8267 if (instr
->is_shadow
) {
8268 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8272 case nir_tex_src_offset
:
8273 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8274 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8277 case nir_tex_src_ddx
:
8278 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8281 case nir_tex_src_ddy
:
8282 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8285 case nir_tex_src_ms_index
:
8286 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8287 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8288 has_sample_index
= true;
8290 case nir_tex_src_texture_offset
:
8291 case nir_tex_src_sampler_offset
:
8297 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8298 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8300 if (instr
->op
== nir_texop_texture_samples
) {
8301 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8303 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8304 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8305 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8306 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8308 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8309 samples
, Operand(1u), bld
.scc(is_msaa
));
8313 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8314 aco_ptr
<Instruction
> tmp_instr
;
8315 Temp acc
, pack
= Temp();
8317 uint32_t pack_const
= 0;
8318 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8319 if (!const_offset
[i
])
8321 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8324 if (offset
.type() == RegType::sgpr
) {
8325 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8326 if (const_offset
[i
])
8329 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8330 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8333 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8336 if (pack
== Temp()) {
8339 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8343 if (pack_const
&& pack
!= Temp())
8344 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8346 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8347 if (const_offset
[i
])
8350 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8351 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8354 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8357 if (pack
== Temp()) {
8360 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8364 if (pack_const
&& pack
!= Temp())
8365 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8367 if (pack_const
&& pack
== Temp())
8368 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8369 else if (pack
== Temp())
8375 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8376 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8378 /* pack derivatives */
8379 if (has_ddx
|| has_ddy
) {
8380 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8381 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8382 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8383 derivs
= {ddx
, zero
, ddy
, zero
};
8385 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8386 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8387 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8388 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8393 if (instr
->coord_components
> 1 &&
8394 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8396 instr
->op
!= nir_texop_txf
)
8397 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8399 if (instr
->coord_components
> 2 &&
8400 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8401 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8402 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8403 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8405 instr
->op
!= nir_texop_txf
&&
8406 instr
->op
!= nir_texop_txf_ms
&&
8407 instr
->op
!= nir_texop_fragment_fetch
&&
8408 instr
->op
!= nir_texop_fragment_mask_fetch
)
8409 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8411 if (ctx
->options
->chip_class
== GFX9
&&
8412 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8413 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8414 assert(coords
.size() > 0 && coords
.size() < 3);
8416 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8417 Operand((uint32_t) 0) :
8418 Operand((uint32_t) 0x3f000000)));
8421 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8423 if (instr
->op
== nir_texop_samples_identical
)
8424 resource
= fmask_ptr
;
8426 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8427 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8428 instr
->op
!= nir_texop_txs
&&
8429 instr
->op
!= nir_texop_fragment_fetch
&&
8430 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8431 assert(has_sample_index
);
8432 Operand
op(sample_index
);
8433 if (sample_index_cv
)
8434 op
= Operand(sample_index_cv
->u32
);
8435 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8438 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8439 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8440 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8441 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8446 /* Build tex instruction */
8447 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8448 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8449 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8451 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8454 /* gather4 selects the component by dmask and always returns vec4 */
8455 if (instr
->op
== nir_texop_tg4
) {
8456 assert(instr
->dest
.ssa
.num_components
== 4);
8457 if (instr
->is_shadow
)
8460 dmask
= 1 << instr
->component
;
8461 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8462 tmp_dst
= bld
.tmp(v4
);
8463 } else if (instr
->op
== nir_texop_samples_identical
) {
8464 tmp_dst
= bld
.tmp(v1
);
8465 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8466 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8469 aco_ptr
<MIMG_instruction
> tex
;
8470 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8472 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8474 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8475 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8478 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8479 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8481 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8482 tex
->operands
[0] = Operand(resource
);
8483 tex
->operands
[1] = Operand(s4
); /* no sampler */
8484 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8485 if (ctx
->options
->chip_class
== GFX9
&&
8486 instr
->op
== nir_texop_txs
&&
8487 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8489 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8490 } else if (instr
->op
== nir_texop_query_levels
) {
8491 tex
->dmask
= 1 << 3;
8496 tex
->definitions
[0] = Definition(tmp_dst
);
8498 tex
->can_reorder
= true;
8499 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8502 /* divide 3rd value by 6 by multiplying with magic number */
8503 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8504 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8505 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8506 assert(instr
->dest
.ssa
.num_components
== 3);
8507 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8508 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8509 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8510 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8515 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8519 Temp tg4_compare_cube_wa64
= Temp();
8521 if (tg4_integer_workarounds
) {
8522 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8523 tex
->operands
[0] = Operand(resource
);
8524 tex
->operands
[1] = Operand(s4
); /* no sampler */
8525 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8529 Temp size
= bld
.tmp(v2
);
8530 tex
->definitions
[0] = Definition(size
);
8531 tex
->can_reorder
= true;
8532 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8533 emit_split_vector(ctx
, size
, size
.size());
8536 for (unsigned i
= 0; i
< 2; i
++) {
8537 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8538 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8539 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8540 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8543 Temp new_coords
[2] = {
8544 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8545 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8548 if (tg4_integer_cube_workaround
) {
8549 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8550 Temp desc
[resource
.size()];
8551 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8552 Format::PSEUDO
, 1, resource
.size())};
8553 split
->operands
[0] = Operand(resource
);
8554 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8555 desc
[i
] = bld
.tmp(s1
);
8556 split
->definitions
[i
] = Definition(desc
[i
]);
8558 ctx
->block
->instructions
.emplace_back(std::move(split
));
8560 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8561 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8562 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8565 if (stype
== GLSL_TYPE_UINT
) {
8566 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8567 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8568 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8569 bld
.scc(compare_cube_wa
));
8571 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8572 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8573 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8574 bld
.scc(compare_cube_wa
));
8576 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8577 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8579 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8581 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8582 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8583 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8585 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8586 Format::PSEUDO
, resource
.size(), 1)};
8587 for (unsigned i
= 0; i
< resource
.size(); i
++)
8588 vec
->operands
[i
] = Operand(desc
[i
]);
8589 resource
= bld
.tmp(resource
.regClass());
8590 vec
->definitions
[0] = Definition(resource
);
8591 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8593 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8594 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8595 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8596 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8598 coords
[0] = new_coords
[0];
8599 coords
[1] = new_coords
[1];
8602 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8603 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8605 assert(coords
.size() == 1);
8606 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8610 op
= aco_opcode::buffer_load_format_x
; break;
8612 op
= aco_opcode::buffer_load_format_xy
; break;
8614 op
= aco_opcode::buffer_load_format_xyz
; break;
8616 op
= aco_opcode::buffer_load_format_xyzw
; break;
8618 unreachable("Tex instruction loads more than 4 components.");
8621 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8622 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8625 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8627 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8628 mubuf
->operands
[0] = Operand(resource
);
8629 mubuf
->operands
[1] = Operand(coords
[0]);
8630 mubuf
->operands
[2] = Operand((uint32_t) 0);
8631 mubuf
->definitions
[0] = Definition(tmp_dst
);
8632 mubuf
->idxen
= true;
8633 mubuf
->can_reorder
= true;
8634 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8636 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8640 /* gather MIMG address components */
8641 std::vector
<Temp
> args
;
8643 args
.emplace_back(offset
);
8645 args
.emplace_back(bias
);
8647 args
.emplace_back(compare
);
8649 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8651 args
.insert(args
.end(), coords
.begin(), coords
.end());
8652 if (has_sample_index
)
8653 args
.emplace_back(sample_index
);
8655 args
.emplace_back(lod
);
8657 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8658 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8659 vec
->definitions
[0] = Definition(arg
);
8660 for (unsigned i
= 0; i
< args
.size(); i
++)
8661 vec
->operands
[i
] = Operand(args
[i
]);
8662 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8665 if (instr
->op
== nir_texop_txf
||
8666 instr
->op
== nir_texop_txf_ms
||
8667 instr
->op
== nir_texop_samples_identical
||
8668 instr
->op
== nir_texop_fragment_fetch
||
8669 instr
->op
== nir_texop_fragment_mask_fetch
) {
8670 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8671 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8672 tex
->operands
[0] = Operand(resource
);
8673 tex
->operands
[1] = Operand(s4
); /* no sampler */
8674 tex
->operands
[2] = Operand(arg
);
8679 tex
->definitions
[0] = Definition(tmp_dst
);
8680 tex
->can_reorder
= true;
8681 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8683 if (instr
->op
== nir_texop_samples_identical
) {
8684 assert(dmask
== 1 && dst
.regClass() == v1
);
8685 assert(dst
.id() != tmp_dst
.id());
8687 Temp tmp
= bld
.tmp(bld
.lm
);
8688 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8689 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8692 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8697 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8698 aco_opcode opcode
= aco_opcode::image_sample
;
8699 if (has_offset
) { /* image_sample_*_o */
8701 opcode
= aco_opcode::image_sample_c_o
;
8703 opcode
= aco_opcode::image_sample_c_d_o
;
8705 opcode
= aco_opcode::image_sample_c_b_o
;
8707 opcode
= aco_opcode::image_sample_c_lz_o
;
8709 opcode
= aco_opcode::image_sample_c_l_o
;
8711 opcode
= aco_opcode::image_sample_o
;
8713 opcode
= aco_opcode::image_sample_d_o
;
8715 opcode
= aco_opcode::image_sample_b_o
;
8717 opcode
= aco_opcode::image_sample_lz_o
;
8719 opcode
= aco_opcode::image_sample_l_o
;
8721 } else { /* no offset */
8723 opcode
= aco_opcode::image_sample_c
;
8725 opcode
= aco_opcode::image_sample_c_d
;
8727 opcode
= aco_opcode::image_sample_c_b
;
8729 opcode
= aco_opcode::image_sample_c_lz
;
8731 opcode
= aco_opcode::image_sample_c_l
;
8733 opcode
= aco_opcode::image_sample
;
8735 opcode
= aco_opcode::image_sample_d
;
8737 opcode
= aco_opcode::image_sample_b
;
8739 opcode
= aco_opcode::image_sample_lz
;
8741 opcode
= aco_opcode::image_sample_l
;
8745 if (instr
->op
== nir_texop_tg4
) {
8747 opcode
= aco_opcode::image_gather4_lz_o
;
8749 opcode
= aco_opcode::image_gather4_c_lz_o
;
8751 opcode
= aco_opcode::image_gather4_lz
;
8753 opcode
= aco_opcode::image_gather4_c_lz
;
8755 } else if (instr
->op
== nir_texop_lod
) {
8756 opcode
= aco_opcode::image_get_lod
;
8759 /* we don't need the bias, sample index, compare value or offset to be
8760 * computed in WQM but if the p_create_vector copies the coordinates, then it
8761 * needs to be in WQM */
8762 if (ctx
->stage
== fragment_fs
&&
8763 !has_derivs
&& !has_lod
&& !level_zero
&&
8764 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8765 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8766 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8768 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8769 tex
->operands
[0] = Operand(resource
);
8770 tex
->operands
[1] = Operand(sampler
);
8771 tex
->operands
[2] = Operand(arg
);
8775 tex
->definitions
[0] = Definition(tmp_dst
);
8776 tex
->can_reorder
= true;
8777 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8779 if (tg4_integer_cube_workaround
) {
8780 assert(tmp_dst
.id() != dst
.id());
8781 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8783 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8785 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8786 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8788 if (stype
== GLSL_TYPE_UINT
)
8789 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8791 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8792 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8794 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8795 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8796 val
[0], val
[1], val
[2], val
[3]);
8798 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8799 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8804 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8806 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8807 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8808 return Operand(tmp
.regClass());
8810 return Operand(tmp
);
8813 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8815 aco_ptr
<Pseudo_instruction
> phi
;
8816 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8817 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8819 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8820 logical
|= ctx
->block
->kind
& block_kind_merge
;
8821 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8823 /* we want a sorted list of sources, since the predecessor list is also sorted */
8824 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8825 nir_foreach_phi_src(src
, instr
)
8826 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8828 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8829 unsigned num_operands
= 0;
8830 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8831 unsigned num_defined
= 0;
8832 unsigned cur_pred_idx
= 0;
8833 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8834 if (cur_pred_idx
< preds
.size()) {
8835 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8836 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8837 unsigned skipped
= 0;
8838 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8840 if (cur_pred_idx
+ skipped
< preds
.size()) {
8841 for (unsigned i
= 0; i
< skipped
; i
++)
8842 operands
[num_operands
++] = Operand(dst
.regClass());
8843 cur_pred_idx
+= skipped
;
8848 /* Handle missing predecessors at the end. This shouldn't happen with loop
8849 * headers and we can't ignore these sources for loop header phis. */
8850 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8853 Operand op
= get_phi_operand(ctx
, src
.second
);
8854 operands
[num_operands
++] = op
;
8855 num_defined
+= !op
.isUndefined();
8857 /* handle block_kind_continue_or_break at loop exit blocks */
8858 while (cur_pred_idx
++ < preds
.size())
8859 operands
[num_operands
++] = Operand(dst
.regClass());
8861 /* If the loop ends with a break, still add a linear continue edge in case
8862 * that break is divergent or continue_or_break is used. We'll either remove
8863 * this operand later in visit_loop() if it's not necessary or replace the
8864 * undef with something correct. */
8865 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8866 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8867 nir_block
*last
= nir_loop_last_block(loop
);
8868 if (last
->successors
[0] != instr
->instr
.block
)
8869 operands
[num_operands
++] = Operand(RegClass());
8872 if (num_defined
== 0) {
8873 Builder
bld(ctx
->program
, ctx
->block
);
8874 if (dst
.regClass() == s1
) {
8875 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8876 } else if (dst
.regClass() == v1
) {
8877 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8879 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8880 for (unsigned i
= 0; i
< dst
.size(); i
++)
8881 vec
->operands
[i
] = Operand(0u);
8882 vec
->definitions
[0] = Definition(dst
);
8883 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8888 /* we can use a linear phi in some cases if one src is undef */
8889 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8890 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8892 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8893 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8894 assert(invert
->kind
& block_kind_invert
);
8896 unsigned then_block
= invert
->linear_preds
[0];
8898 Block
* insert_block
= NULL
;
8899 for (unsigned i
= 0; i
< num_operands
; i
++) {
8900 Operand op
= operands
[i
];
8901 if (op
.isUndefined())
8903 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8904 phi
->operands
[0] = op
;
8907 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8908 phi
->operands
[1] = Operand(dst
.regClass());
8909 phi
->definitions
[0] = Definition(dst
);
8910 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8914 /* try to scalarize vector phis */
8915 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8916 // TODO: scalarize linear phis on divergent ifs
8917 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8918 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8919 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8920 Operand src
= operands
[i
];
8921 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8922 can_scalarize
= false;
8924 if (can_scalarize
) {
8925 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8926 assert(dst
.size() % num_components
== 0);
8927 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8929 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8930 for (unsigned k
= 0; k
< num_components
; k
++) {
8931 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8932 for (unsigned i
= 0; i
< num_operands
; i
++) {
8933 Operand src
= operands
[i
];
8934 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8936 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8937 phi
->definitions
[0] = Definition(phi_dst
);
8938 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8939 new_vec
[k
] = phi_dst
;
8940 vec
->operands
[k
] = Operand(phi_dst
);
8942 vec
->definitions
[0] = Definition(dst
);
8943 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8944 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8949 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8950 for (unsigned i
= 0; i
< num_operands
; i
++)
8951 phi
->operands
[i
] = operands
[i
];
8952 phi
->definitions
[0] = Definition(dst
);
8953 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8957 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8959 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8961 assert(dst
.type() == RegType::sgpr
);
8963 if (dst
.size() == 1) {
8964 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8966 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8967 for (unsigned i
= 0; i
< dst
.size(); i
++)
8968 vec
->operands
[i
] = Operand(0u);
8969 vec
->definitions
[0] = Definition(dst
);
8970 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8974 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8976 Builder
bld(ctx
->program
, ctx
->block
);
8977 Block
*logical_target
;
8978 append_logical_end(ctx
->block
);
8979 unsigned idx
= ctx
->block
->index
;
8981 switch (instr
->type
) {
8982 case nir_jump_break
:
8983 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8984 add_logical_edge(idx
, logical_target
);
8985 ctx
->block
->kind
|= block_kind_break
;
8987 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8988 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8989 /* uniform break - directly jump out of the loop */
8990 ctx
->block
->kind
|= block_kind_uniform
;
8991 ctx
->cf_info
.has_branch
= true;
8992 bld
.branch(aco_opcode::p_branch
);
8993 add_linear_edge(idx
, logical_target
);
8996 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8997 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8999 case nir_jump_continue
:
9000 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9001 add_logical_edge(idx
, logical_target
);
9002 ctx
->block
->kind
|= block_kind_continue
;
9004 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9005 /* for potential uniform breaks after this continue,
9006 we must ensure that they are handled correctly */
9007 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9008 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9009 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9011 /* uniform continue - directly jump to the loop header */
9012 ctx
->block
->kind
|= block_kind_uniform
;
9013 ctx
->cf_info
.has_branch
= true;
9014 bld
.branch(aco_opcode::p_branch
);
9015 add_linear_edge(idx
, logical_target
);
9020 fprintf(stderr
, "Unknown NIR jump instr: ");
9021 nir_print_instr(&instr
->instr
, stderr
);
9022 fprintf(stderr
, "\n");
9026 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9027 ctx
->cf_info
.exec_potentially_empty_break
= true;
9028 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9031 /* remove critical edges from linear CFG */
9032 bld
.branch(aco_opcode::p_branch
);
9033 Block
* break_block
= ctx
->program
->create_and_insert_block();
9034 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9035 break_block
->kind
|= block_kind_uniform
;
9036 add_linear_edge(idx
, break_block
);
9037 /* the loop_header pointer might be invalidated by this point */
9038 if (instr
->type
== nir_jump_continue
)
9039 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9040 add_linear_edge(break_block
->index
, logical_target
);
9041 bld
.reset(break_block
);
9042 bld
.branch(aco_opcode::p_branch
);
9044 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9045 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9046 add_linear_edge(idx
, continue_block
);
9047 append_logical_start(continue_block
);
9048 ctx
->block
= continue_block
;
9052 void visit_block(isel_context
*ctx
, nir_block
*block
)
9054 nir_foreach_instr(instr
, block
) {
9055 switch (instr
->type
) {
9056 case nir_instr_type_alu
:
9057 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9059 case nir_instr_type_load_const
:
9060 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9062 case nir_instr_type_intrinsic
:
9063 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9065 case nir_instr_type_tex
:
9066 visit_tex(ctx
, nir_instr_as_tex(instr
));
9068 case nir_instr_type_phi
:
9069 visit_phi(ctx
, nir_instr_as_phi(instr
));
9071 case nir_instr_type_ssa_undef
:
9072 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9074 case nir_instr_type_deref
:
9076 case nir_instr_type_jump
:
9077 visit_jump(ctx
, nir_instr_as_jump(instr
));
9080 fprintf(stderr
, "Unknown NIR instr type: ");
9081 nir_print_instr(instr
, stderr
);
9082 fprintf(stderr
, "\n");
9087 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9088 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9093 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9094 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9096 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9097 RegClass rc
= vals
[0].regClass();
9099 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9101 unsigned next_pred
= 1;
9103 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9104 Block
& block
= ctx
->program
->blocks
[idx
];
9105 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9106 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9110 if (block
.kind
& block_kind_continue
) {
9111 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9116 bool all_same
= true;
9117 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9118 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9122 val
= vals
[block
.linear_preds
[0] - first
];
9124 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9125 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9126 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9127 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9128 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9129 phi
->definitions
[0] = Definition(val
.getTemp());
9130 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9132 vals
[idx
- first
] = val
;
9135 return vals
[last
- first
];
9138 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9140 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9141 append_logical_end(ctx
->block
);
9142 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9143 Builder
bld(ctx
->program
, ctx
->block
);
9144 bld
.branch(aco_opcode::p_branch
);
9145 unsigned loop_preheader_idx
= ctx
->block
->index
;
9147 Block loop_exit
= Block();
9148 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9149 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9151 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9152 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9153 loop_header
->kind
|= block_kind_loop_header
;
9154 add_edge(loop_preheader_idx
, loop_header
);
9155 ctx
->block
= loop_header
;
9157 /* emit loop body */
9158 unsigned loop_header_idx
= loop_header
->index
;
9159 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9160 append_logical_start(ctx
->block
);
9161 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9163 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9164 if (!ctx
->cf_info
.has_branch
) {
9165 append_logical_end(ctx
->block
);
9166 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9167 /* Discards can result in code running with an empty exec mask.
9168 * This would result in divergent breaks not ever being taken. As a
9169 * workaround, break the loop when the loop mask is empty instead of
9170 * always continuing. */
9171 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9172 unsigned block_idx
= ctx
->block
->index
;
9174 /* create helper blocks to avoid critical edges */
9175 Block
*break_block
= ctx
->program
->create_and_insert_block();
9176 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9177 break_block
->kind
= block_kind_uniform
;
9178 bld
.reset(break_block
);
9179 bld
.branch(aco_opcode::p_branch
);
9180 add_linear_edge(block_idx
, break_block
);
9181 add_linear_edge(break_block
->index
, &loop_exit
);
9183 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9184 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9185 continue_block
->kind
= block_kind_uniform
;
9186 bld
.reset(continue_block
);
9187 bld
.branch(aco_opcode::p_branch
);
9188 add_linear_edge(block_idx
, continue_block
);
9189 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9191 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9192 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9193 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9195 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9196 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9197 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9199 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9202 bld
.reset(ctx
->block
);
9203 bld
.branch(aco_opcode::p_branch
);
9206 /* Fixup phis in loop header from unreachable blocks.
9207 * has_branch/has_divergent_branch also indicates if the loop ends with a
9208 * break/continue instruction, but we don't emit those if unreachable=true */
9210 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9211 bool linear
= ctx
->cf_info
.has_branch
;
9212 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9213 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9214 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9215 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9216 /* the last operand should be the one that needs to be removed */
9217 instr
->operands
.pop_back();
9218 } else if (!is_phi(instr
)) {
9224 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9225 * and the previous one shouldn't both happen at once because a break in the
9226 * merge block would get CSE'd */
9227 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9228 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9229 Operand vals
[num_vals
];
9230 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9231 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9232 if (ctx
->cf_info
.has_branch
)
9233 instr
->operands
.pop_back();
9235 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9236 } else if (!is_phi(instr
)) {
9242 ctx
->cf_info
.has_branch
= false;
9244 // TODO: if the loop has not a single exit, we must add one °°
9245 /* emit loop successor block */
9246 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9247 append_logical_start(ctx
->block
);
9250 // TODO: check if it is beneficial to not branch on continues
9251 /* trim linear phis in loop header */
9252 for (auto&& instr
: loop_entry
->instructions
) {
9253 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9254 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9255 new_phi
->definitions
[0] = instr
->definitions
[0];
9256 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9257 new_phi
->operands
[i
] = instr
->operands
[i
];
9258 /* check that the remaining operands are all the same */
9259 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9260 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9261 instr
.swap(new_phi
);
9262 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9271 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9275 append_logical_end(ctx
->block
);
9276 ctx
->block
->kind
|= block_kind_branch
;
9278 /* branch to linear then block */
9279 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9280 aco_ptr
<Pseudo_branch_instruction
> branch
;
9281 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9282 branch
->operands
[0] = Operand(cond
);
9283 ctx
->block
->instructions
.push_back(std::move(branch
));
9285 ic
->BB_if_idx
= ctx
->block
->index
;
9286 ic
->BB_invert
= Block();
9287 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9288 /* Invert blocks are intentionally not marked as top level because they
9289 * are not part of the logical cfg. */
9290 ic
->BB_invert
.kind
|= block_kind_invert
;
9291 ic
->BB_endif
= Block();
9292 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9293 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9295 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9296 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9297 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9298 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9299 ctx
->cf_info
.parent_if
.is_divergent
= true;
9301 /* divergent branches use cbranch_execz */
9302 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9303 ctx
->cf_info
.exec_potentially_empty_break
= false;
9304 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9306 /** emit logical then block */
9307 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9308 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9309 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9310 ctx
->block
= BB_then_logical
;
9311 append_logical_start(BB_then_logical
);
9314 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9316 Block
*BB_then_logical
= ctx
->block
;
9317 append_logical_end(BB_then_logical
);
9318 /* branch from logical then block to invert block */
9319 aco_ptr
<Pseudo_branch_instruction
> branch
;
9320 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9321 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9322 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9323 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9324 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9325 BB_then_logical
->kind
|= block_kind_uniform
;
9326 assert(!ctx
->cf_info
.has_branch
);
9327 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9328 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9330 /** emit linear then block */
9331 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9332 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9333 BB_then_linear
->kind
|= block_kind_uniform
;
9334 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9335 /* branch from linear then block to invert block */
9336 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9337 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9338 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9340 /** emit invert merge block */
9341 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9342 ic
->invert_idx
= ctx
->block
->index
;
9344 /* branch to linear else block (skip else) */
9345 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9346 branch
->operands
[0] = Operand(ic
->cond
);
9347 ctx
->block
->instructions
.push_back(std::move(branch
));
9349 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9350 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9351 ic
->exec_potentially_empty_break_depth_old
=
9352 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9353 /* divergent branches use cbranch_execz */
9354 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9355 ctx
->cf_info
.exec_potentially_empty_break
= false;
9356 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9358 /** emit logical else block */
9359 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9360 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9361 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9362 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9363 ctx
->block
= BB_else_logical
;
9364 append_logical_start(BB_else_logical
);
9367 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9369 Block
*BB_else_logical
= ctx
->block
;
9370 append_logical_end(BB_else_logical
);
9372 /* branch from logical else block to endif block */
9373 aco_ptr
<Pseudo_branch_instruction
> branch
;
9374 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9375 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9376 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9377 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9378 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9379 BB_else_logical
->kind
|= block_kind_uniform
;
9381 assert(!ctx
->cf_info
.has_branch
);
9382 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9385 /** emit linear else block */
9386 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9387 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9388 BB_else_linear
->kind
|= block_kind_uniform
;
9389 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9391 /* branch from linear else block to endif block */
9392 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9393 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9394 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9397 /** emit endif merge block */
9398 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9399 append_logical_start(ctx
->block
);
9402 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9403 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9404 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9405 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9406 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9407 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9408 !ctx
->cf_info
.parent_if
.is_divergent
) {
9409 ctx
->cf_info
.exec_potentially_empty_break
= false;
9410 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9412 /* uniform control flow never has an empty exec-mask */
9413 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9414 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9415 ctx
->cf_info
.exec_potentially_empty_break
= false;
9416 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9420 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9422 assert(cond
.regClass() == s1
);
9424 append_logical_end(ctx
->block
);
9425 ctx
->block
->kind
|= block_kind_uniform
;
9427 aco_ptr
<Pseudo_branch_instruction
> branch
;
9428 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9429 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9430 branch
->operands
[0] = Operand(cond
);
9431 branch
->operands
[0].setFixed(scc
);
9432 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9434 ic
->BB_if_idx
= ctx
->block
->index
;
9435 ic
->BB_endif
= Block();
9436 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9437 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9439 ctx
->cf_info
.has_branch
= false;
9440 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9442 /** emit then block */
9443 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9444 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9445 add_edge(ic
->BB_if_idx
, BB_then
);
9446 append_logical_start(BB_then
);
9447 ctx
->block
= BB_then
;
9450 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9452 Block
*BB_then
= ctx
->block
;
9454 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9455 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9457 if (!ic
->uniform_has_then_branch
) {
9458 append_logical_end(BB_then
);
9459 /* branch from then block to endif block */
9460 aco_ptr
<Pseudo_branch_instruction
> branch
;
9461 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9462 BB_then
->instructions
.emplace_back(std::move(branch
));
9463 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9464 if (!ic
->then_branch_divergent
)
9465 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9466 BB_then
->kind
|= block_kind_uniform
;
9469 ctx
->cf_info
.has_branch
= false;
9470 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9472 /** emit else block */
9473 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9474 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9475 add_edge(ic
->BB_if_idx
, BB_else
);
9476 append_logical_start(BB_else
);
9477 ctx
->block
= BB_else
;
9480 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9482 Block
*BB_else
= ctx
->block
;
9484 if (!ctx
->cf_info
.has_branch
) {
9485 append_logical_end(BB_else
);
9486 /* branch from then block to endif block */
9487 aco_ptr
<Pseudo_branch_instruction
> branch
;
9488 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9489 BB_else
->instructions
.emplace_back(std::move(branch
));
9490 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9491 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9492 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9493 BB_else
->kind
|= block_kind_uniform
;
9496 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9497 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9499 /** emit endif merge block */
9500 if (!ctx
->cf_info
.has_branch
) {
9501 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9502 append_logical_start(ctx
->block
);
9506 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9508 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9509 Builder
bld(ctx
->program
, ctx
->block
);
9510 aco_ptr
<Pseudo_branch_instruction
> branch
;
9513 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9515 * Uniform conditionals are represented in the following way*) :
9517 * The linear and logical CFG:
9520 * BB_THEN (logical) BB_ELSE (logical)
9524 * *) Exceptions may be due to break and continue statements within loops
9525 * If a break/continue happens within uniform control flow, it branches
9526 * to the loop exit/entry block. Otherwise, it branches to the next
9530 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9531 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9532 cond
= bool_to_scalar_condition(ctx
, cond
);
9534 begin_uniform_if_then(ctx
, &ic
, cond
);
9535 visit_cf_list(ctx
, &if_stmt
->then_list
);
9537 begin_uniform_if_else(ctx
, &ic
);
9538 visit_cf_list(ctx
, &if_stmt
->else_list
);
9540 end_uniform_if(ctx
, &ic
);
9542 return !ctx
->cf_info
.has_branch
;
9543 } else { /* non-uniform condition */
9545 * To maintain a logical and linear CFG without critical edges,
9546 * non-uniform conditionals are represented in the following way*) :
9551 * BB_THEN (logical) BB_THEN (linear)
9553 * BB_INVERT (linear)
9555 * BB_ELSE (logical) BB_ELSE (linear)
9562 * BB_THEN (logical) BB_ELSE (logical)
9566 * *) Exceptions may be due to break and continue statements within loops
9569 begin_divergent_if_then(ctx
, &ic
, cond
);
9570 visit_cf_list(ctx
, &if_stmt
->then_list
);
9572 begin_divergent_if_else(ctx
, &ic
);
9573 visit_cf_list(ctx
, &if_stmt
->else_list
);
9575 end_divergent_if(ctx
, &ic
);
9581 static bool visit_cf_list(isel_context
*ctx
,
9582 struct exec_list
*list
)
9584 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9585 switch (node
->type
) {
9586 case nir_cf_node_block
:
9587 visit_block(ctx
, nir_cf_node_as_block(node
));
9589 case nir_cf_node_if
:
9590 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9593 case nir_cf_node_loop
:
9594 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9597 unreachable("unimplemented cf list type");
9603 static void create_null_export(isel_context
*ctx
)
9605 /* Some shader stages always need to have exports.
9606 * So when there is none, we need to add a null export.
9609 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9610 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9611 Builder
bld(ctx
->program
, ctx
->block
);
9612 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9613 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9616 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9618 assert(ctx
->stage
== vertex_vs
||
9619 ctx
->stage
== tess_eval_vs
||
9620 ctx
->stage
== gs_copy_vs
||
9621 ctx
->stage
== ngg_vertex_gs
||
9622 ctx
->stage
== ngg_tess_eval_gs
);
9624 int offset
= (ctx
->stage
& sw_tes
)
9625 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9626 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9627 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9628 if (!is_pos
&& !mask
)
9630 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9632 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9633 exp
->enabled_mask
= mask
;
9634 for (unsigned i
= 0; i
< 4; ++i
) {
9635 if (mask
& (1 << i
))
9636 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9638 exp
->operands
[i
] = Operand(v1
);
9640 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9641 * Setting valid_mask=1 prevents it and has no other effect.
9643 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9645 exp
->compressed
= false;
9647 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9649 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9650 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9655 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9657 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9658 exp
->enabled_mask
= 0;
9659 for (unsigned i
= 0; i
< 4; ++i
)
9660 exp
->operands
[i
] = Operand(v1
);
9661 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9662 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9663 exp
->enabled_mask
|= 0x1;
9665 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9666 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9667 exp
->enabled_mask
|= 0x4;
9669 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9670 if (ctx
->options
->chip_class
< GFX9
) {
9671 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9672 exp
->enabled_mask
|= 0x8;
9674 Builder
bld(ctx
->program
, ctx
->block
);
9676 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9677 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9678 if (exp
->operands
[2].isTemp())
9679 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9681 exp
->operands
[2] = Operand(out
);
9682 exp
->enabled_mask
|= 0x4;
9685 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9687 exp
->compressed
= false;
9688 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9689 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9692 static void create_export_phis(isel_context
*ctx
)
9694 /* Used when exports are needed, but the output temps are defined in a preceding block.
9695 * This function will set up phis in order to access the outputs in the next block.
9698 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9699 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9700 ctx
->block
->instructions
.pop_back();
9702 Builder
bld(ctx
->program
, ctx
->block
);
9704 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9705 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9706 for (unsigned i
= 0; i
< 4; ++i
) {
9707 if (!(mask
& (1 << i
)))
9710 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9711 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9712 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9716 bld
.insert(std::move(logical_start
));
9719 static void create_vs_exports(isel_context
*ctx
)
9721 assert(ctx
->stage
== vertex_vs
||
9722 ctx
->stage
== tess_eval_vs
||
9723 ctx
->stage
== gs_copy_vs
||
9724 ctx
->stage
== ngg_vertex_gs
||
9725 ctx
->stage
== ngg_tess_eval_gs
);
9727 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9728 ? &ctx
->program
->info
->tes
.outinfo
9729 : &ctx
->program
->info
->vs
.outinfo
;
9731 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9732 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9733 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9736 if (ctx
->options
->key
.has_multiview_view_index
) {
9737 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9738 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9741 /* the order these position exports are created is important */
9743 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9744 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9745 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9746 exported_pos
= true;
9748 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9749 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9750 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9751 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9753 if (ctx
->export_clip_dists
) {
9754 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9755 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9756 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9757 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9760 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9761 if (i
< VARYING_SLOT_VAR0
&&
9762 i
!= VARYING_SLOT_LAYER
&&
9763 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9764 i
!= VARYING_SLOT_VIEWPORT
)
9767 export_vs_varying(ctx
, i
, false, NULL
);
9771 create_null_export(ctx
);
9774 static bool export_fs_mrt_z(isel_context
*ctx
)
9776 Builder
bld(ctx
->program
, ctx
->block
);
9777 unsigned enabled_channels
= 0;
9781 for (unsigned i
= 0; i
< 4; ++i
) {
9782 values
[i
] = Operand(v1
);
9785 /* Both stencil and sample mask only need 16-bits. */
9786 if (!ctx
->program
->info
->ps
.writes_z
&&
9787 (ctx
->program
->info
->ps
.writes_stencil
||
9788 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9789 compr
= true; /* COMPR flag */
9791 if (ctx
->program
->info
->ps
.writes_stencil
) {
9792 /* Stencil should be in X[23:16]. */
9793 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9794 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9795 enabled_channels
|= 0x3;
9798 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9799 /* SampleMask should be in Y[15:0]. */
9800 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9801 enabled_channels
|= 0xc;
9804 if (ctx
->program
->info
->ps
.writes_z
) {
9805 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9806 enabled_channels
|= 0x1;
9809 if (ctx
->program
->info
->ps
.writes_stencil
) {
9810 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9811 enabled_channels
|= 0x2;
9814 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9815 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9816 enabled_channels
|= 0x4;
9820 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9821 * writemask component.
9823 if (ctx
->options
->chip_class
== GFX6
&&
9824 ctx
->options
->family
!= CHIP_OLAND
&&
9825 ctx
->options
->family
!= CHIP_HAINAN
) {
9826 enabled_channels
|= 0x1;
9829 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9830 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9835 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9837 Builder
bld(ctx
->program
, ctx
->block
);
9838 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9841 for (unsigned i
= 0; i
< 4; ++i
) {
9842 if (write_mask
& (1 << i
)) {
9843 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9845 values
[i
] = Operand(v1
);
9849 unsigned target
, col_format
;
9850 unsigned enabled_channels
= 0;
9851 aco_opcode compr_op
= (aco_opcode
)0;
9853 slot
-= FRAG_RESULT_DATA0
;
9854 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9855 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9857 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9858 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9862 case V_028714_SPI_SHADER_ZERO
:
9863 enabled_channels
= 0; /* writemask */
9864 target
= V_008DFC_SQ_EXP_NULL
;
9867 case V_028714_SPI_SHADER_32_R
:
9868 enabled_channels
= 1;
9871 case V_028714_SPI_SHADER_32_GR
:
9872 enabled_channels
= 0x3;
9875 case V_028714_SPI_SHADER_32_AR
:
9876 if (ctx
->options
->chip_class
>= GFX10
) {
9877 /* Special case: on GFX10, the outputs are different for 32_AR */
9878 enabled_channels
= 0x3;
9879 values
[1] = values
[3];
9880 values
[3] = Operand(v1
);
9882 enabled_channels
= 0x9;
9886 case V_028714_SPI_SHADER_FP16_ABGR
:
9887 enabled_channels
= 0x5;
9888 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9891 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9892 enabled_channels
= 0x5;
9893 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9896 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9897 enabled_channels
= 0x5;
9898 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9901 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9902 enabled_channels
= 0x5;
9903 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9904 if (is_int8
|| is_int10
) {
9906 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9907 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9909 for (unsigned i
= 0; i
< 4; i
++) {
9910 if ((write_mask
>> i
) & 1) {
9911 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9912 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9920 case V_028714_SPI_SHADER_SINT16_ABGR
:
9921 enabled_channels
= 0x5;
9922 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9923 if (is_int8
|| is_int10
) {
9925 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9926 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9927 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9928 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9930 for (unsigned i
= 0; i
< 4; i
++) {
9931 if ((write_mask
>> i
) & 1) {
9932 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9933 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9935 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9936 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9943 case V_028714_SPI_SHADER_32_ABGR
:
9944 enabled_channels
= 0xF;
9951 if (target
== V_008DFC_SQ_EXP_NULL
)
9954 if ((bool) compr_op
) {
9955 for (int i
= 0; i
< 2; i
++) {
9956 /* check if at least one of the values to be compressed is enabled */
9957 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9959 enabled_channels
|= enabled
<< (i
*2);
9960 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9961 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9962 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9964 values
[i
] = Operand(v1
);
9967 values
[2] = Operand(v1
);
9968 values
[3] = Operand(v1
);
9970 for (int i
= 0; i
< 4; i
++)
9971 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9974 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9975 enabled_channels
, target
, (bool) compr_op
);
9979 static void create_fs_exports(isel_context
*ctx
)
9981 bool exported
= false;
9983 /* Export depth, stencil and sample mask. */
9984 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9985 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9986 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9987 exported
|= export_fs_mrt_z(ctx
);
9989 /* Export all color render targets. */
9990 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9991 if (ctx
->outputs
.mask
[i
])
9992 exported
|= export_fs_mrt_color(ctx
, i
);
9995 create_null_export(ctx
);
9998 static void write_tcs_tess_factors(isel_context
*ctx
)
10000 unsigned outer_comps
;
10001 unsigned inner_comps
;
10003 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10020 Builder
bld(ctx
->program
, ctx
->block
);
10022 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10023 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10024 bld
.sopp(aco_opcode::s_barrier
);
10026 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10027 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10029 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10030 if_context ic_invocation_id_is_zero
;
10031 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10032 bld
.reset(ctx
->block
);
10034 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10036 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10037 unsigned stride
= inner_comps
+ outer_comps
;
10038 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10042 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10044 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10046 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10047 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10048 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10050 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10051 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10053 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10054 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10055 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10056 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10059 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10060 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10061 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10062 unsigned tf_const_offset
= 0;
10064 if (ctx
->program
->chip_class
<= GFX8
) {
10065 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10066 if_context ic_rel_patch_id_is_zero
;
10067 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10068 bld
.reset(ctx
->block
);
10070 /* Store the dynamic HS control word. */
10071 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10072 bld
.mubuf(aco_opcode::buffer_store_dword
,
10073 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10074 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10075 /* disable_wqm */ false, /* glc */ true);
10076 tf_const_offset
+= 4;
10078 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10079 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10080 bld
.reset(ctx
->block
);
10083 assert(stride
== 2 || stride
== 4 || stride
== 6);
10084 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10085 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10087 /* Store to offchip for TES to read - only if TES reads them */
10088 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10089 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10090 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10092 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10093 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10095 if (likely(inner_comps
)) {
10096 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10097 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10101 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10102 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10105 static void emit_stream_output(isel_context
*ctx
,
10106 Temp
const *so_buffers
,
10107 Temp
const *so_write_offset
,
10108 const struct radv_stream_output
*output
)
10110 unsigned num_comps
= util_bitcount(output
->component_mask
);
10111 unsigned writemask
= (1 << num_comps
) - 1;
10112 unsigned loc
= output
->location
;
10113 unsigned buf
= output
->buffer
;
10115 assert(num_comps
&& num_comps
<= 4);
10116 if (!num_comps
|| num_comps
> 4)
10119 unsigned start
= ffs(output
->component_mask
) - 1;
10122 bool all_undef
= true;
10123 assert(ctx
->stage
& hw_vs
);
10124 for (unsigned i
= 0; i
< num_comps
; i
++) {
10125 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10126 all_undef
= all_undef
&& !out
[i
].id();
10131 while (writemask
) {
10133 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10134 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10135 /* GFX6 doesn't support storing vec3, split it. */
10136 writemask
|= 1u << (start
+ 2);
10140 unsigned offset
= output
->offset
+ start
* 4;
10142 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10143 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10144 for (int i
= 0; i
< count
; ++i
)
10145 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10146 vec
->definitions
[0] = Definition(write_data
);
10147 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10152 opcode
= aco_opcode::buffer_store_dword
;
10155 opcode
= aco_opcode::buffer_store_dwordx2
;
10158 opcode
= aco_opcode::buffer_store_dwordx3
;
10161 opcode
= aco_opcode::buffer_store_dwordx4
;
10164 unreachable("Unsupported dword count.");
10167 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10168 store
->operands
[0] = Operand(so_buffers
[buf
]);
10169 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10170 store
->operands
[2] = Operand((uint32_t) 0);
10171 store
->operands
[3] = Operand(write_data
);
10172 if (offset
> 4095) {
10173 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10174 Builder
bld(ctx
->program
, ctx
->block
);
10175 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10177 store
->offset
= offset
;
10179 store
->offen
= true;
10181 store
->dlc
= false;
10183 store
->can_reorder
= true;
10184 ctx
->block
->instructions
.emplace_back(std::move(store
));
10188 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10190 Builder
bld(ctx
->program
, ctx
->block
);
10192 Temp so_buffers
[4];
10193 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10194 for (unsigned i
= 0; i
< 4; i
++) {
10195 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10199 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10200 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10203 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10204 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10206 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10208 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10211 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10213 bld
.reset(ctx
->block
);
10215 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10217 Temp so_write_offset
[4];
10219 for (unsigned i
= 0; i
< 4; i
++) {
10220 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10225 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10226 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10227 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10228 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10230 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10232 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10233 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10234 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10235 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10239 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10240 struct radv_stream_output
*output
=
10241 &ctx
->program
->info
->so
.outputs
[i
];
10242 if (stream
!= output
->stream
)
10245 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10248 begin_divergent_if_else(ctx
, &ic
);
10249 end_divergent_if(ctx
, &ic
);
10252 } /* end namespace */
10254 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10256 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10257 Builder
bld(ctx
->program
, ctx
->block
);
10258 constexpr unsigned hs_idx
= 1u;
10259 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10260 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10261 Operand((8u << 16) | (hs_idx
* 8u)));
10262 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10264 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10266 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10267 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10268 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10269 ls_has_nonzero_hs_threads
);
10270 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10271 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10272 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10273 ls_has_nonzero_hs_threads
);
10274 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10275 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10276 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10277 ls_has_nonzero_hs_threads
);
10279 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10280 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10281 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10284 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10286 /* Split all arguments except for the first (ring_offsets) and the last
10287 * (exec) so that the dead channels don't stay live throughout the program.
10289 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10290 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10291 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10292 startpgm
->definitions
[i
].regClass().size());
10297 void handle_bc_optimize(isel_context
*ctx
)
10299 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10300 Builder
bld(ctx
->program
, ctx
->block
);
10301 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10302 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10303 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10304 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10305 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10306 if (uses_center
&& uses_centroid
) {
10307 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10308 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10310 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10312 for (unsigned i
= 0; i
< 2; i
++) {
10313 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10314 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10315 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10316 persp_centroid
, persp_center
, sel
);
10318 ctx
->persp_centroid
= bld
.tmp(v2
);
10319 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10320 Operand(new_coord
[0]), Operand(new_coord
[1]));
10321 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10324 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10326 for (unsigned i
= 0; i
< 2; i
++) {
10327 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10328 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10329 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10330 linear_centroid
, linear_center
, sel
);
10332 ctx
->linear_centroid
= bld
.tmp(v2
);
10333 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10334 Operand(new_coord
[0]), Operand(new_coord
[1]));
10335 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10340 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10342 Program
*program
= ctx
->program
;
10344 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10346 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10347 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10348 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10349 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10350 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10352 program
->next_fp_mode
.must_flush_denorms32
=
10353 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10354 program
->next_fp_mode
.must_flush_denorms16_64
=
10355 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10356 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10358 program
->next_fp_mode
.care_about_round32
=
10359 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10361 program
->next_fp_mode
.care_about_round16_64
=
10362 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10363 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10365 /* default to preserving fp16 and fp64 denorms, since it's free */
10366 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10367 program
->next_fp_mode
.denorm16_64
= 0;
10369 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10371 /* preserving fp32 denorms is expensive, so only do it if asked */
10372 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10373 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10375 program
->next_fp_mode
.denorm32
= 0;
10377 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10378 program
->next_fp_mode
.round32
= fp_round_tz
;
10380 program
->next_fp_mode
.round32
= fp_round_ne
;
10382 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10383 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10385 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10387 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10390 void cleanup_cfg(Program
*program
)
10392 /* create linear_succs/logical_succs */
10393 for (Block
& BB
: program
->blocks
) {
10394 for (unsigned idx
: BB
.linear_preds
)
10395 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10396 for (unsigned idx
: BB
.logical_preds
)
10397 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10401 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10403 Builder
bld(ctx
->program
, ctx
->block
);
10405 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10406 Temp count
= i
== 0
10407 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10408 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10409 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10411 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10414 if (ctx
->program
->wave_size
== 64) {
10415 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10416 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10417 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10419 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10420 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10426 bool ngg_early_prim_export(isel_context
*ctx
)
10428 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10432 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10434 Builder
bld(ctx
->program
, ctx
->block
);
10436 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10437 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10439 /* Get the id of the current wave within the threadgroup (workgroup) */
10440 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10441 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10443 /* Execute the following code only on the first wave (wave id 0),
10444 * use the SCC def to tell if the wave id is zero or not.
10446 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10448 begin_uniform_if_then(ctx
, &ic
, cond
);
10449 begin_uniform_if_else(ctx
, &ic
);
10450 bld
.reset(ctx
->block
);
10452 /* Number of vertices output by VS/TES */
10453 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10454 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10455 /* Number of primitives output by VS/TES */
10456 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10457 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10459 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10460 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10461 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10463 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10464 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10466 end_uniform_if(ctx
, &ic
);
10468 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10469 bld
.reset(ctx
->block
);
10470 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10473 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10475 Builder
bld(ctx
->program
, ctx
->block
);
10477 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10478 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10481 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10484 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10485 assert(vtxindex
[i
].id());
10488 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10492 /* The initial edge flag is always false in tess eval shaders. */
10493 if (ctx
->stage
== ngg_vertex_gs
) {
10494 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10495 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10499 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10504 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10506 Builder
bld(ctx
->program
, ctx
->block
);
10507 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10509 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10510 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10511 false /* compressed */, true/* done */, false /* valid mask */);
10514 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10516 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10517 * These must always come before VS exports.
10519 * It is recommended to do these as early as possible. They can be at the beginning when
10520 * there is no SW GS and the shader doesn't write edge flags.
10524 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10525 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10527 Builder
bld(ctx
->program
, ctx
->block
);
10528 constexpr unsigned max_vertices_per_primitive
= 3;
10529 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10531 if (ctx
->stage
== ngg_vertex_gs
) {
10532 /* TODO: optimize for points & lines */
10533 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10534 if (ctx
->shader
->info
.tess
.point_mode
)
10535 num_vertices_per_primitive
= 1;
10536 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10537 num_vertices_per_primitive
= 2;
10539 unreachable("Unsupported NGG shader stage");
10542 Temp vtxindex
[max_vertices_per_primitive
];
10543 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10544 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10545 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10546 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10547 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10548 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10549 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10550 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10552 /* Export primitive data to the index buffer. */
10553 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10555 /* Export primitive ID. */
10556 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10557 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10558 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10559 Temp provoking_vtx_index
= vtxindex
[0];
10560 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10562 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10565 begin_divergent_if_else(ctx
, &ic
);
10566 end_divergent_if(ctx
, &ic
);
10569 void ngg_emit_nogs_output(isel_context
*ctx
)
10571 /* Emits NGG GS output, for stages that don't have SW GS. */
10574 Builder
bld(ctx
->program
, ctx
->block
);
10575 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10577 /* NGG streamout is currently disabled by default. */
10578 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10580 if (late_prim_export
) {
10581 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10582 create_export_phis(ctx
);
10583 /* Do what we need to do in the GS threads. */
10584 ngg_emit_nogs_gsthreads(ctx
);
10586 /* What comes next should be executed on ES threads. */
10587 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10588 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10589 bld
.reset(ctx
->block
);
10592 /* Export VS outputs */
10593 ctx
->block
->kind
|= block_kind_export_end
;
10594 create_vs_exports(ctx
);
10596 /* Export primitive ID */
10597 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10600 if (ctx
->stage
== ngg_vertex_gs
) {
10601 /* Wait for GS threads to store primitive ID in LDS. */
10602 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10603 bld
.sopp(aco_opcode::s_barrier
);
10605 /* Calculate LDS address where the GS threads stored the primitive ID. */
10606 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10607 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10608 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10609 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10610 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10611 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10613 /* Load primitive ID from LDS. */
10614 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10615 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10616 /* TES: Just use the patch ID as the primitive ID. */
10617 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10619 unreachable("unsupported NGG shader stage.");
10622 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10623 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10625 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10628 if (late_prim_export
) {
10629 begin_divergent_if_else(ctx
, &ic
);
10630 end_divergent_if(ctx
, &ic
);
10631 bld
.reset(ctx
->block
);
10635 void select_program(Program
*program
,
10636 unsigned shader_count
,
10637 struct nir_shader
*const *shaders
,
10638 ac_shader_config
* config
,
10639 struct radv_shader_args
*args
)
10641 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10642 if_context ic_merged_wave_info
;
10643 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10645 for (unsigned i
= 0; i
< shader_count
; i
++) {
10646 nir_shader
*nir
= shaders
[i
];
10647 init_context(&ctx
, nir
);
10649 setup_fp_mode(&ctx
, nir
);
10652 /* needs to be after init_context() for FS */
10653 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10654 append_logical_start(ctx
.block
);
10656 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10657 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10659 split_arguments(&ctx
, startpgm
);
10663 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10665 if (ngg_early_prim_export(&ctx
))
10666 ngg_emit_nogs_gsthreads(&ctx
);
10669 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10670 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10671 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10672 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10673 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10674 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10675 ctx
.stage
== tess_eval_geometry_gs
));
10677 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10678 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10679 if (check_merged_wave_info
) {
10680 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10681 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10685 Builder
bld(ctx
.program
, ctx
.block
);
10687 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10688 bld
.sopp(aco_opcode::s_barrier
);
10690 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10691 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10693 } else if (ctx
.stage
== geometry_gs
)
10694 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10696 if (ctx
.stage
== fragment_fs
)
10697 handle_bc_optimize(&ctx
);
10699 visit_cf_list(&ctx
, &func
->body
);
10701 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10702 emit_streamout(&ctx
, 0);
10704 if (ctx
.stage
& hw_vs
) {
10705 create_vs_exports(&ctx
);
10706 ctx
.block
->kind
|= block_kind_export_end
;
10707 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10708 ngg_emit_nogs_output(&ctx
);
10709 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10710 Builder
bld(ctx
.program
, ctx
.block
);
10711 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10712 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10713 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10714 write_tcs_tess_factors(&ctx
);
10717 if (ctx
.stage
== fragment_fs
) {
10718 create_fs_exports(&ctx
);
10719 ctx
.block
->kind
|= block_kind_export_end
;
10722 if (endif_merged_wave_info
) {
10723 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10724 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10727 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10728 ngg_emit_nogs_output(&ctx
);
10730 ralloc_free(ctx
.divergent_vals
);
10732 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10733 /* Outputs of the previous stage are inputs to the next stage */
10734 ctx
.inputs
= ctx
.outputs
;
10735 ctx
.outputs
= shader_io_state();
10739 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10741 append_logical_end(ctx
.block
);
10742 ctx
.block
->kind
|= block_kind_uniform
;
10743 Builder
bld(ctx
.program
, ctx
.block
);
10744 if (ctx
.program
->wb_smem_l1_on_end
)
10745 bld
.smem(aco_opcode::s_dcache_wb
, false);
10746 bld
.sopp(aco_opcode::s_endpgm
);
10748 cleanup_cfg(program
);
10751 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10752 ac_shader_config
* config
,
10753 struct radv_shader_args
*args
)
10755 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10757 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10758 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10759 program
->next_fp_mode
.must_flush_denorms32
= false;
10760 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10761 program
->next_fp_mode
.care_about_round32
= false;
10762 program
->next_fp_mode
.care_about_round16_64
= false;
10763 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10764 program
->next_fp_mode
.denorm32
= 0;
10765 program
->next_fp_mode
.round32
= fp_round_ne
;
10766 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10767 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10769 add_startpgm(&ctx
);
10770 append_logical_start(ctx
.block
);
10772 Builder
bld(ctx
.program
, ctx
.block
);
10774 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10776 Operand
stream_id(0u);
10777 if (args
->shader_info
->so
.num_outputs
)
10778 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10779 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10781 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10783 std::stack
<Block
> endif_blocks
;
10785 for (unsigned stream
= 0; stream
< 4; stream
++) {
10786 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10789 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10790 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10793 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10795 unsigned BB_if_idx
= ctx
.block
->index
;
10796 Block BB_endif
= Block();
10797 if (!stream_id
.isConstant()) {
10799 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10800 append_logical_end(ctx
.block
);
10801 ctx
.block
->kind
|= block_kind_uniform
;
10802 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10804 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10806 ctx
.block
= ctx
.program
->create_and_insert_block();
10807 add_edge(BB_if_idx
, ctx
.block
);
10808 bld
.reset(ctx
.block
);
10809 append_logical_start(ctx
.block
);
10812 unsigned offset
= 0;
10813 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10814 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10817 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10818 unsigned length
= util_last_bit(output_usage_mask
);
10819 for (unsigned j
= 0; j
< length
; ++j
) {
10820 if (!(output_usage_mask
& (1 << j
)))
10823 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10824 Temp voffset
= vtx_offset
;
10825 if (const_offset
>= 4096u) {
10826 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10827 const_offset
%= 4096u;
10830 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10831 mubuf
->definitions
[0] = bld
.def(v1
);
10832 mubuf
->operands
[0] = Operand(gsvs_ring
);
10833 mubuf
->operands
[1] = Operand(voffset
);
10834 mubuf
->operands
[2] = Operand(0u);
10835 mubuf
->offen
= true;
10836 mubuf
->offset
= const_offset
;
10839 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10840 mubuf
->barrier
= barrier_none
;
10841 mubuf
->can_reorder
= true;
10843 ctx
.outputs
.mask
[i
] |= 1 << j
;
10844 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10846 bld
.insert(std::move(mubuf
));
10852 if (args
->shader_info
->so
.num_outputs
) {
10853 emit_streamout(&ctx
, stream
);
10854 bld
.reset(ctx
.block
);
10858 create_vs_exports(&ctx
);
10859 ctx
.block
->kind
|= block_kind_export_end
;
10862 if (!stream_id
.isConstant()) {
10863 append_logical_end(ctx
.block
);
10865 /* branch from then block to endif block */
10866 bld
.branch(aco_opcode::p_branch
);
10867 add_edge(ctx
.block
->index
, &BB_endif
);
10868 ctx
.block
->kind
|= block_kind_uniform
;
10870 /* emit else block */
10871 ctx
.block
= ctx
.program
->create_and_insert_block();
10872 add_edge(BB_if_idx
, ctx
.block
);
10873 bld
.reset(ctx
.block
);
10874 append_logical_start(ctx
.block
);
10876 endif_blocks
.push(std::move(BB_endif
));
10880 while (!endif_blocks
.empty()) {
10881 Block BB_endif
= std::move(endif_blocks
.top());
10882 endif_blocks
.pop();
10884 Block
*BB_else
= ctx
.block
;
10886 append_logical_end(BB_else
);
10887 /* branch from else block to endif block */
10888 bld
.branch(aco_opcode::p_branch
);
10889 add_edge(BB_else
->index
, &BB_endif
);
10890 BB_else
->kind
|= block_kind_uniform
;
10892 /** emit endif merge block */
10893 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10894 bld
.reset(ctx
.block
);
10895 append_logical_start(ctx
.block
);
10898 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10900 append_logical_end(ctx
.block
);
10901 ctx
.block
->kind
|= block_kind_uniform
;
10902 bld
.sopp(aco_opcode::s_endpgm
);
10904 cleanup_cfg(program
);