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12 * The above copyright notice and this permission notice (including the next
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 /* this function trims subdword vectors:
417 * if dst is vgpr - split the src and create a shrunk version according to the mask.
418 * if dst is sgpr - split the src, but move the original to sgpr. */
419 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
421 assert(vec_src
.type() == RegType::vgpr
);
422 emit_split_vector(ctx
, vec_src
, num_components
);
424 Builder
bld(ctx
->program
, ctx
->block
);
425 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
426 unsigned component_size
= vec_src
.bytes() / num_components
;
427 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
430 for (unsigned i
= 0; i
< num_components
; i
++) {
432 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
435 if (dst
.type() == RegType::vgpr
) {
436 assert(dst
.bytes() == k
* component_size
);
437 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
438 for (unsigned i
= 0; i
< k
; i
++)
439 vec
->operands
[i
] = Operand(elems
[i
]);
440 vec
->definitions
[0] = Definition(dst
);
441 bld
.insert(std::move(vec
));
443 // TODO: alignbyte if mask doesn't start with 1?
445 assert(dst
.size() == vec_src
.size());
446 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
448 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
451 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
453 Builder
bld(ctx
->program
, ctx
->block
);
455 dst
= bld
.tmp(bld
.lm
);
457 assert(val
.regClass() == s1
);
458 assert(dst
.regClass() == bld
.lm
);
460 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
463 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
465 Builder
bld(ctx
->program
, ctx
->block
);
469 assert(val
.regClass() == bld
.lm
);
470 assert(dst
.regClass() == s1
);
472 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
473 Temp tmp
= bld
.tmp(s1
);
474 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
475 return emit_wqm(ctx
, tmp
, dst
);
478 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
480 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
481 return get_ssa_temp(ctx
, src
.src
.ssa
);
483 if (src
.src
.ssa
->num_components
== size
) {
484 bool identity_swizzle
= true;
485 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
486 if (src
.swizzle
[i
] != i
)
487 identity_swizzle
= false;
489 if (identity_swizzle
)
490 return get_ssa_temp(ctx
, src
.src
.ssa
);
493 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
494 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
495 assert(elem_size
> 0);
496 assert(vec
.bytes() % elem_size
== 0);
498 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
499 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
501 unsigned swizzle
= src
.swizzle
[0];
502 if (vec
.size() > 1) {
503 assert(src
.src
.ssa
->bit_size
== 16);
504 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
505 swizzle
= swizzle
& 1;
510 Temp dst
{ctx
->program
->allocateId(), s1
};
511 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
512 bfe
->operands
[0] = Operand(vec
);
513 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
514 bfe
->definitions
[0] = Definition(dst
);
515 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
516 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
520 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
522 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
525 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
526 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
527 for (unsigned i
= 0; i
< size
; ++i
) {
528 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
529 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
531 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
532 vec_instr
->definitions
[0] = Definition(dst
);
533 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
534 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
539 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
543 Builder
bld(ctx
->program
, ctx
->block
);
544 if (ptr
.type() == RegType::vgpr
)
545 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
546 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
547 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
550 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
552 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
553 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
554 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
555 sop2
->definitions
[0] = Definition(dst
);
557 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
558 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
561 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
562 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
564 Builder
bld(ctx
->program
, ctx
->block
);
565 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
566 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
567 if (src1
.type() == RegType::sgpr
) {
568 if (commutative
&& src0
.type() == RegType::vgpr
) {
573 src1
= as_vgpr(ctx
, src1
);
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f16
:
630 op
= aco_opcode::v_cmp_gt_f16
;
632 case aco_opcode::v_cmp_ge_f16
:
633 op
= aco_opcode::v_cmp_le_f16
;
635 case aco_opcode::v_cmp_lt_i16
:
636 op
= aco_opcode::v_cmp_gt_i16
;
638 case aco_opcode::v_cmp_ge_i16
:
639 op
= aco_opcode::v_cmp_le_i16
;
641 case aco_opcode::v_cmp_lt_u16
:
642 op
= aco_opcode::v_cmp_gt_u16
;
644 case aco_opcode::v_cmp_ge_u16
:
645 op
= aco_opcode::v_cmp_le_u16
;
647 case aco_opcode::v_cmp_lt_f32
:
648 op
= aco_opcode::v_cmp_gt_f32
;
650 case aco_opcode::v_cmp_ge_f32
:
651 op
= aco_opcode::v_cmp_le_f32
;
653 case aco_opcode::v_cmp_lt_i32
:
654 op
= aco_opcode::v_cmp_gt_i32
;
656 case aco_opcode::v_cmp_ge_i32
:
657 op
= aco_opcode::v_cmp_le_i32
;
659 case aco_opcode::v_cmp_lt_u32
:
660 op
= aco_opcode::v_cmp_gt_u32
;
662 case aco_opcode::v_cmp_ge_u32
:
663 op
= aco_opcode::v_cmp_le_u32
;
665 case aco_opcode::v_cmp_lt_f64
:
666 op
= aco_opcode::v_cmp_gt_f64
;
668 case aco_opcode::v_cmp_ge_f64
:
669 op
= aco_opcode::v_cmp_le_f64
;
671 case aco_opcode::v_cmp_lt_i64
:
672 op
= aco_opcode::v_cmp_gt_i64
;
674 case aco_opcode::v_cmp_ge_i64
:
675 op
= aco_opcode::v_cmp_le_i64
;
677 case aco_opcode::v_cmp_lt_u64
:
678 op
= aco_opcode::v_cmp_gt_u64
;
680 case aco_opcode::v_cmp_ge_u64
:
681 op
= aco_opcode::v_cmp_le_u64
;
683 default: /* eq and ne are commutative */
690 src1
= as_vgpr(ctx
, src1
);
694 Builder
bld(ctx
->program
, ctx
->block
);
695 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
698 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
702 Builder
bld(ctx
->program
, ctx
->block
);
704 assert(dst
.regClass() == bld
.lm
);
705 assert(src0
.type() == RegType::sgpr
);
706 assert(src1
.type() == RegType::sgpr
);
707 assert(src0
.regClass() == src1
.regClass());
709 /* Emit the SALU comparison instruction */
710 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
711 /* Turn the result into a per-lane bool */
712 bool_to_vector_condition(ctx
, cmp
, dst
);
715 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
716 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
718 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
719 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
720 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
721 nir_dest_is_divergent(instr
->dest
.dest
) ||
722 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
723 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
724 aco_opcode op
= use_valu
? v_op
: s_op
;
725 assert(op
!= aco_opcode::num_opcodes
);
726 assert(dst
.regClass() == ctx
->program
->lane_mask
);
729 emit_vopc_instruction(ctx
, instr
, op
, dst
);
731 emit_sopc_instruction(ctx
, instr
, op
, dst
);
734 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
736 Builder
bld(ctx
->program
, ctx
->block
);
737 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
738 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
740 assert(dst
.regClass() == bld
.lm
);
741 assert(src0
.regClass() == bld
.lm
);
742 assert(src1
.regClass() == bld
.lm
);
744 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
747 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
749 Builder
bld(ctx
->program
, ctx
->block
);
750 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
751 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
752 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
754 assert(cond
.regClass() == bld
.lm
);
756 if (dst
.type() == RegType::vgpr
) {
757 aco_ptr
<Instruction
> bcsel
;
758 if (dst
.size() == 1) {
759 then
= as_vgpr(ctx
, then
);
760 els
= as_vgpr(ctx
, els
);
762 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
763 } else if (dst
.size() == 2) {
764 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
765 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
766 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
767 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
769 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
770 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
772 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
774 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
775 nir_print_instr(&instr
->instr
, stderr
);
776 fprintf(stderr
, "\n");
781 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
782 assert(dst
.regClass() == bld
.lm
);
783 assert(then
.regClass() == bld
.lm
);
784 assert(els
.regClass() == bld
.lm
);
787 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
788 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
789 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
790 assert(dst
.size() == then
.size());
791 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
792 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
794 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
795 nir_print_instr(&instr
->instr
, stderr
);
796 fprintf(stderr
, "\n");
801 /* divergent boolean bcsel
802 * this implements bcsel on bools: dst = s0 ? s1 : s2
803 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
804 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
806 if (cond
.id() != then
.id())
807 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
809 if (cond
.id() == els
.id())
810 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
812 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
813 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
816 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
817 aco_opcode op
, uint32_t undo
)
819 /* multiply by 16777216 to handle denormals */
820 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
821 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
822 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
823 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
824 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
826 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
828 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
831 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
833 if (ctx
->block
->fp_mode
.denorm32
== 0) {
834 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
838 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
841 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
843 if (ctx
->block
->fp_mode
.denorm32
== 0) {
844 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
848 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
851 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
853 if (ctx
->block
->fp_mode
.denorm32
== 0) {
854 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
858 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
861 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
863 if (ctx
->block
->fp_mode
.denorm32
== 0) {
864 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
868 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
871 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
873 if (ctx
->options
->chip_class
>= GFX7
)
874 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
876 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
877 /* TODO: create more efficient code! */
878 if (val
.type() == RegType::sgpr
)
879 val
= as_vgpr(ctx
, val
);
881 /* Split the input value. */
882 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
883 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
885 /* Extract the exponent and compute the unbiased value. */
886 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
887 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
889 /* Extract the fractional part. */
890 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
891 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
893 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
894 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
896 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
897 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
898 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
899 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
900 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
902 /* Get the sign bit. */
903 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
905 /* Decide the operation to apply depending on the unbiased exponent. */
906 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
907 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
908 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
909 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
910 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
911 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
913 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
916 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
918 if (ctx
->options
->chip_class
>= GFX7
)
919 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
921 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
922 Temp src0
= as_vgpr(ctx
, val
);
924 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
925 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
927 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
928 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
929 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
931 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
933 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
934 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
936 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
937 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
939 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
941 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
942 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
944 return add
->definitions
[0].getTemp();
947 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
949 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
950 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
952 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
955 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
956 return bld
.copy(Definition(dst
), src
);
957 else if (dst
.bytes() < src
.bytes())
958 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
962 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
965 } else if (src
.regClass() == s1
) {
967 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
969 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
970 } else if (ctx
->options
->chip_class
>= GFX8
) {
971 assert(src_bits
!= 8 || src
.regClass() == v1b
);
972 assert(src_bits
!= 16 || src
.regClass() == v2b
);
973 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
974 sdwa
->operands
[0] = Operand(src
);
975 sdwa
->definitions
[0] = Definition(tmp
);
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
979 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
980 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
981 bld
.insert(std::move(sdwa
));
983 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
984 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
985 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
988 if (dst_bits
== 64) {
989 if (is_signed
&& dst
.regClass() == s2
) {
990 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
991 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
992 } else if (is_signed
&& dst
.regClass() == v2
) {
993 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
994 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
996 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1003 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1005 if (!instr
->dest
.dest
.is_ssa
) {
1006 fprintf(stderr
, "nir alu dst not in ssa: ");
1007 nir_print_instr(&instr
->instr
, stderr
);
1008 fprintf(stderr
, "\n");
1011 Builder
bld(ctx
->program
, ctx
->block
);
1012 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1017 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1018 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1019 for (unsigned i
= 0; i
< num
; ++i
)
1020 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1022 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1023 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1024 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1025 for (unsigned i
= 0; i
< num
; ++i
) {
1026 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1027 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1029 vec
->operands
[i
] = Operand
{elems
[i
]};
1031 vec
->definitions
[0] = Definition(dst
);
1032 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1033 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1035 // TODO: that is a bit suboptimal..
1036 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1037 for (unsigned i
= 0; i
< num
- 1; ++i
)
1038 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1039 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1040 for (unsigned i
= 0; i
< num
; ++i
) {
1041 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1042 if (bit
% 32 == 0) {
1043 elems
[bit
/ 32] = elems
[i
];
1045 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1046 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1047 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1050 if (dst
.size() == 1)
1051 bld
.copy(Definition(dst
), elems
[0]);
1053 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1058 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1059 aco_ptr
<Instruction
> mov
;
1060 if (dst
.type() == RegType::sgpr
) {
1061 if (src
.type() == RegType::vgpr
)
1062 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1063 else if (src
.regClass() == s1
)
1064 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1065 else if (src
.regClass() == s2
)
1066 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1068 unreachable("wrong src register class for nir_op_imov");
1070 if (dst
.regClass() == v1
)
1071 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1072 else if (dst
.regClass() == v1b
||
1073 dst
.regClass() == v2b
||
1074 dst
.regClass() == v2
)
1075 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1077 unreachable("wrong src register class for nir_op_imov");
1082 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1083 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1084 assert(src
.regClass() == bld
.lm
);
1085 assert(dst
.regClass() == bld
.lm
);
1086 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1087 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1088 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1089 } else if (dst
.regClass() == v1
) {
1090 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1091 } else if (dst
.type() == RegType::sgpr
) {
1092 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1093 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1095 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1096 nir_print_instr(&instr
->instr
, stderr
);
1097 fprintf(stderr
, "\n");
1102 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1103 if (dst
.regClass() == v1
) {
1104 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1105 } else if (dst
.regClass() == s1
) {
1106 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1107 } else if (dst
.size() == 2) {
1108 Temp src0
= bld
.tmp(dst
.type(), 1);
1109 Temp src1
= bld
.tmp(dst
.type(), 1);
1110 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1112 if (dst
.regClass() == s2
) {
1113 Temp carry
= bld
.tmp(s1
);
1114 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1115 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1116 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1118 Temp lower
= bld
.tmp(v1
);
1119 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1120 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1121 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1125 nir_print_instr(&instr
->instr
, stderr
);
1126 fprintf(stderr
, "\n");
1131 if (dst
.regClass() == s1
) {
1132 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1133 } else if (dst
.regClass() == v1
) {
1134 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1135 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1143 case nir_op_isign
: {
1144 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1145 if (dst
.regClass() == s1
) {
1146 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1147 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1148 } else if (dst
.regClass() == s2
) {
1149 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1151 if (ctx
->program
->chip_class
>= GFX8
)
1152 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1154 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1155 /* SCC gets zero-extended to 64 bit */
1156 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1157 } else if (dst
.regClass() == v1
) {
1158 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1159 } else if (dst
.regClass() == v2
) {
1160 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1161 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1162 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1163 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1164 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1165 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1167 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1168 nir_print_instr(&instr
->instr
, stderr
);
1169 fprintf(stderr
, "\n");
1174 if (dst
.regClass() == v1
) {
1175 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1176 } else if (dst
.regClass() == s1
) {
1177 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1179 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1180 nir_print_instr(&instr
->instr
, stderr
);
1181 fprintf(stderr
, "\n");
1186 if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1191 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1192 nir_print_instr(&instr
->instr
, stderr
);
1193 fprintf(stderr
, "\n");
1198 if (dst
.regClass() == v1
) {
1199 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1200 } else if (dst
.regClass() == s1
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1203 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1204 nir_print_instr(&instr
->instr
, stderr
);
1205 fprintf(stderr
, "\n");
1210 if (dst
.regClass() == v1
) {
1211 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1212 } else if (dst
.regClass() == s1
) {
1213 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1215 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1216 nir_print_instr(&instr
->instr
, stderr
);
1217 fprintf(stderr
, "\n");
1222 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1223 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1224 } else if (dst
.regClass() == v1
) {
1225 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1228 } else if (dst
.regClass() == s2
) {
1229 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1231 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1232 nir_print_instr(&instr
->instr
, stderr
);
1233 fprintf(stderr
, "\n");
1238 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1239 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1240 } else if (dst
.regClass() == v1
) {
1241 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1242 } else if (dst
.regClass() == s1
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1244 } else if (dst
.regClass() == s2
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1247 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1248 nir_print_instr(&instr
->instr
, stderr
);
1249 fprintf(stderr
, "\n");
1254 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1255 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1256 } else if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1258 } else if (dst
.regClass() == s1
) {
1259 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1260 } else if (dst
.regClass() == s2
) {
1261 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1263 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1264 nir_print_instr(&instr
->instr
, stderr
);
1265 fprintf(stderr
, "\n");
1270 if (dst
.regClass() == v1
) {
1271 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1272 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1273 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1274 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1275 } else if (dst
.regClass() == v2
) {
1276 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1277 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1278 } else if (dst
.regClass() == s2
) {
1279 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1280 } else if (dst
.regClass() == s1
) {
1281 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1283 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1284 nir_print_instr(&instr
->instr
, stderr
);
1285 fprintf(stderr
, "\n");
1290 if (dst
.regClass() == v1
) {
1291 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1292 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1293 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1294 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1295 } else if (dst
.regClass() == v2
) {
1296 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1297 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1298 } else if (dst
.regClass() == s1
) {
1299 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1300 } else if (dst
.regClass() == s2
) {
1301 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1303 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1304 nir_print_instr(&instr
->instr
, stderr
);
1305 fprintf(stderr
, "\n");
1310 if (dst
.regClass() == v1
) {
1311 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1312 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1313 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1314 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1315 } else if (dst
.regClass() == v2
) {
1316 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1317 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1318 } else if (dst
.regClass() == s1
) {
1319 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1320 } else if (dst
.regClass() == s2
) {
1321 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1323 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1324 nir_print_instr(&instr
->instr
, stderr
);
1325 fprintf(stderr
, "\n");
1329 case nir_op_find_lsb
: {
1330 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1331 if (src
.regClass() == s1
) {
1332 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1333 } else if (src
.regClass() == v1
) {
1334 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1335 } else if (src
.regClass() == s2
) {
1336 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1338 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1339 nir_print_instr(&instr
->instr
, stderr
);
1340 fprintf(stderr
, "\n");
1344 case nir_op_ufind_msb
:
1345 case nir_op_ifind_msb
: {
1346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1347 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1348 aco_opcode op
= src
.regClass() == s2
?
1349 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1350 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1351 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1353 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1354 Operand(src
.size() * 32u - 1u), msb_rev
);
1355 Temp msb
= sub
.def(0).getTemp();
1356 Temp carry
= sub
.def(1).getTemp();
1358 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1359 } else if (src
.regClass() == v1
) {
1360 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1361 Temp msb_rev
= bld
.tmp(v1
);
1362 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1363 Temp msb
= bld
.tmp(v1
);
1364 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1365 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1367 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1368 nir_print_instr(&instr
->instr
, stderr
);
1369 fprintf(stderr
, "\n");
1373 case nir_op_bitfield_reverse
: {
1374 if (dst
.regClass() == s1
) {
1375 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1376 } else if (dst
.regClass() == v1
) {
1377 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1379 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1380 nir_print_instr(&instr
->instr
, stderr
);
1381 fprintf(stderr
, "\n");
1386 if (dst
.regClass() == s1
) {
1387 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1391 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1392 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1393 if (dst
.regClass() == v1
) {
1394 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1398 assert(src0
.size() == 2 && src1
.size() == 2);
1399 Temp src00
= bld
.tmp(src0
.type(), 1);
1400 Temp src01
= bld
.tmp(dst
.type(), 1);
1401 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1402 Temp src10
= bld
.tmp(src1
.type(), 1);
1403 Temp src11
= bld
.tmp(dst
.type(), 1);
1404 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1406 if (dst
.regClass() == s2
) {
1407 Temp carry
= bld
.tmp(s1
);
1408 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1409 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1410 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1411 } else if (dst
.regClass() == v2
) {
1412 Temp dst0
= bld
.tmp(v1
);
1413 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1414 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1415 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1417 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1418 nir_print_instr(&instr
->instr
, stderr
);
1419 fprintf(stderr
, "\n");
1423 case nir_op_uadd_sat
: {
1424 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1425 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1426 if (dst
.regClass() == s1
) {
1427 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1428 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1430 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1431 } else if (dst
.regClass() == v1
) {
1432 if (ctx
->options
->chip_class
>= GFX9
) {
1433 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1434 add
->operands
[0] = Operand(src0
);
1435 add
->operands
[1] = Operand(src1
);
1436 add
->definitions
[0] = Definition(dst
);
1438 ctx
->block
->instructions
.emplace_back(std::move(add
));
1440 if (src1
.regClass() != v1
)
1441 std::swap(src0
, src1
);
1442 assert(src1
.regClass() == v1
);
1443 Temp tmp
= bld
.tmp(v1
);
1444 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1445 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1448 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1449 nir_print_instr(&instr
->instr
, stderr
);
1450 fprintf(stderr
, "\n");
1454 case nir_op_uadd_carry
: {
1455 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1456 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1457 if (dst
.regClass() == s1
) {
1458 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1461 if (dst
.regClass() == v1
) {
1462 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1463 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1467 Temp src00
= bld
.tmp(src0
.type(), 1);
1468 Temp src01
= bld
.tmp(dst
.type(), 1);
1469 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1470 Temp src10
= bld
.tmp(src1
.type(), 1);
1471 Temp src11
= bld
.tmp(dst
.type(), 1);
1472 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1473 if (dst
.regClass() == s2
) {
1474 Temp carry
= bld
.tmp(s1
);
1475 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1476 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1477 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1478 } else if (dst
.regClass() == v2
) {
1479 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1480 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1481 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1482 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1484 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1485 nir_print_instr(&instr
->instr
, stderr
);
1486 fprintf(stderr
, "\n");
1491 if (dst
.regClass() == s1
) {
1492 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1496 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1497 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1498 if (dst
.regClass() == v1
) {
1499 bld
.vsub32(Definition(dst
), src0
, src1
);
1503 Temp src00
= bld
.tmp(src0
.type(), 1);
1504 Temp src01
= bld
.tmp(dst
.type(), 1);
1505 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1506 Temp src10
= bld
.tmp(src1
.type(), 1);
1507 Temp src11
= bld
.tmp(dst
.type(), 1);
1508 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1509 if (dst
.regClass() == s2
) {
1510 Temp carry
= bld
.tmp(s1
);
1511 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1512 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1513 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1514 } else if (dst
.regClass() == v2
) {
1515 Temp lower
= bld
.tmp(v1
);
1516 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1517 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1518 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1520 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1521 nir_print_instr(&instr
->instr
, stderr
);
1522 fprintf(stderr
, "\n");
1526 case nir_op_usub_borrow
: {
1527 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1528 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1529 if (dst
.regClass() == s1
) {
1530 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1532 } else if (dst
.regClass() == v1
) {
1533 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1534 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1538 Temp src00
= bld
.tmp(src0
.type(), 1);
1539 Temp src01
= bld
.tmp(dst
.type(), 1);
1540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1541 Temp src10
= bld
.tmp(src1
.type(), 1);
1542 Temp src11
= bld
.tmp(dst
.type(), 1);
1543 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1544 if (dst
.regClass() == s2
) {
1545 Temp borrow
= bld
.tmp(s1
);
1546 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1547 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1548 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1549 } else if (dst
.regClass() == v2
) {
1550 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1551 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1552 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1562 if (dst
.regClass() == v1
) {
1563 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1564 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1565 } else if (dst
.regClass() == s1
) {
1566 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1568 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1569 nir_print_instr(&instr
->instr
, stderr
);
1570 fprintf(stderr
, "\n");
1574 case nir_op_umul_high
: {
1575 if (dst
.regClass() == v1
) {
1576 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1577 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1578 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1579 } else if (dst
.regClass() == s1
) {
1580 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1581 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1582 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1584 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1585 nir_print_instr(&instr
->instr
, stderr
);
1586 fprintf(stderr
, "\n");
1590 case nir_op_imul_high
: {
1591 if (dst
.regClass() == v1
) {
1592 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1593 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1594 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1595 } else if (dst
.regClass() == s1
) {
1596 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1597 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1598 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1600 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1601 nir_print_instr(&instr
->instr
, stderr
);
1602 fprintf(stderr
, "\n");
1607 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1608 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1609 if (dst
.regClass() == v2b
) {
1610 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1611 } else if (dst
.regClass() == v1
) {
1612 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1613 } else if (dst
.regClass() == v2
) {
1614 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1616 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1617 nir_print_instr(&instr
->instr
, stderr
);
1618 fprintf(stderr
, "\n");
1623 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1624 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1625 if (dst
.regClass() == v2b
) {
1626 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1627 } else if (dst
.regClass() == v1
) {
1628 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1629 } else if (dst
.regClass() == v2
) {
1630 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1632 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1633 nir_print_instr(&instr
->instr
, stderr
);
1634 fprintf(stderr
, "\n");
1639 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1640 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1641 if (dst
.regClass() == v2b
) {
1642 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1643 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1645 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1646 } else if (dst
.regClass() == v1
) {
1647 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1650 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1651 } else if (dst
.regClass() == v2
) {
1652 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1653 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1654 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1664 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1665 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1666 if (dst
.regClass() == v2b
) {
1667 // TODO: check fp_mode.must_flush_denorms16_64
1668 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1669 } else if (dst
.regClass() == v1
) {
1670 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1671 } else if (dst
.regClass() == v2
) {
1672 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1673 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1674 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1676 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1686 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1687 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1688 if (dst
.regClass() == v2b
) {
1689 // TODO: check fp_mode.must_flush_denorms16_64
1690 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1691 } else if (dst
.regClass() == v1
) {
1692 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1693 } else if (dst
.regClass() == v2
) {
1694 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1695 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1696 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1698 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1701 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1702 nir_print_instr(&instr
->instr
, stderr
);
1703 fprintf(stderr
, "\n");
1707 case nir_op_fmax3
: {
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1713 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1714 nir_print_instr(&instr
->instr
, stderr
);
1715 fprintf(stderr
, "\n");
1719 case nir_op_fmin3
: {
1720 if (dst
.regClass() == v2b
) {
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1722 } else if (dst
.regClass() == v1
) {
1723 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1725 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1726 nir_print_instr(&instr
->instr
, stderr
);
1727 fprintf(stderr
, "\n");
1731 case nir_op_fmed3
: {
1732 if (dst
.regClass() == v2b
) {
1733 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1734 } else if (dst
.regClass() == v1
) {
1735 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1737 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1738 nir_print_instr(&instr
->instr
, stderr
);
1739 fprintf(stderr
, "\n");
1743 case nir_op_umax3
: {
1744 if (dst
.size() == 1) {
1745 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1748 nir_print_instr(&instr
->instr
, stderr
);
1749 fprintf(stderr
, "\n");
1753 case nir_op_umin3
: {
1754 if (dst
.size() == 1) {
1755 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1758 nir_print_instr(&instr
->instr
, stderr
);
1759 fprintf(stderr
, "\n");
1763 case nir_op_umed3
: {
1764 if (dst
.size() == 1) {
1765 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1768 nir_print_instr(&instr
->instr
, stderr
);
1769 fprintf(stderr
, "\n");
1773 case nir_op_imax3
: {
1774 if (dst
.size() == 1) {
1775 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1777 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1778 nir_print_instr(&instr
->instr
, stderr
);
1779 fprintf(stderr
, "\n");
1783 case nir_op_imin3
: {
1784 if (dst
.size() == 1) {
1785 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1793 case nir_op_imed3
: {
1794 if (dst
.size() == 1) {
1795 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1797 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1798 nir_print_instr(&instr
->instr
, stderr
);
1799 fprintf(stderr
, "\n");
1803 case nir_op_cube_face_coord
: {
1804 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1805 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1806 emit_extract_vector(ctx
, in
, 1, v1
),
1807 emit_extract_vector(ctx
, in
, 2, v1
) };
1808 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1809 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1810 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1811 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1812 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1813 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1814 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1817 case nir_op_cube_face_index
: {
1818 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1819 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1820 emit_extract_vector(ctx
, in
, 1, v1
),
1821 emit_extract_vector(ctx
, in
, 2, v1
) };
1822 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1825 case nir_op_bcsel
: {
1826 emit_bcsel(ctx
, instr
, dst
);
1830 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1831 if (dst
.regClass() == v2b
) {
1832 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1833 } else if (dst
.regClass() == v1
) {
1834 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1835 } else if (dst
.regClass() == v2
) {
1836 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1838 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1839 nir_print_instr(&instr
->instr
, stderr
);
1840 fprintf(stderr
, "\n");
1845 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1846 if (dst
.regClass() == v2b
) {
1847 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1848 } else if (dst
.regClass() == v1
) {
1849 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1850 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1851 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1852 } else if (dst
.regClass() == v2
) {
1853 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1854 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1855 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1856 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1857 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1858 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1860 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1861 nir_print_instr(&instr
->instr
, stderr
);
1862 fprintf(stderr
, "\n");
1867 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1868 if (dst
.regClass() == v2b
) {
1869 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1870 } else if (dst
.regClass() == v1
) {
1871 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1872 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1873 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1874 } else if (dst
.regClass() == v2
) {
1875 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1876 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1877 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1879 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1880 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1882 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1883 nir_print_instr(&instr
->instr
, stderr
);
1884 fprintf(stderr
, "\n");
1889 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1890 if (dst
.regClass() == v2b
) {
1891 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1892 } else if (dst
.regClass() == v1
) {
1893 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1894 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1895 // TODO: confirm that this holds under any circumstances
1896 } else if (dst
.regClass() == v2
) {
1897 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1898 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1901 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1902 nir_print_instr(&instr
->instr
, stderr
);
1903 fprintf(stderr
, "\n");
1907 case nir_op_flog2
: {
1908 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1909 if (dst
.regClass() == v2b
) {
1910 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1911 } else if (dst
.regClass() == v1
) {
1912 emit_log2(ctx
, bld
, Definition(dst
), src
);
1914 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1915 nir_print_instr(&instr
->instr
, stderr
);
1916 fprintf(stderr
, "\n");
1921 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1922 if (dst
.regClass() == v2b
) {
1923 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1924 } else if (dst
.regClass() == v1
) {
1925 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1926 } else if (dst
.regClass() == v2
) {
1927 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1930 nir_print_instr(&instr
->instr
, stderr
);
1931 fprintf(stderr
, "\n");
1935 case nir_op_fexp2
: {
1936 if (dst
.regClass() == v2b
) {
1937 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1941 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1942 nir_print_instr(&instr
->instr
, stderr
);
1943 fprintf(stderr
, "\n");
1947 case nir_op_fsqrt
: {
1948 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1949 if (dst
.regClass() == v2b
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1951 } else if (dst
.regClass() == v1
) {
1952 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1953 } else if (dst
.regClass() == v2
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1956 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1957 nir_print_instr(&instr
->instr
, stderr
);
1958 fprintf(stderr
, "\n");
1962 case nir_op_ffract
: {
1963 if (dst
.regClass() == v2b
) {
1964 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1965 } else if (dst
.regClass() == v1
) {
1966 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1967 } else if (dst
.regClass() == v2
) {
1968 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1970 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1971 nir_print_instr(&instr
->instr
, stderr
);
1972 fprintf(stderr
, "\n");
1976 case nir_op_ffloor
: {
1977 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1978 if (dst
.regClass() == v2b
) {
1979 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1980 } else if (dst
.regClass() == v1
) {
1981 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1982 } else if (dst
.regClass() == v2
) {
1983 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1985 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1986 nir_print_instr(&instr
->instr
, stderr
);
1987 fprintf(stderr
, "\n");
1991 case nir_op_fceil
: {
1992 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1993 if (dst
.regClass() == v2b
) {
1994 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1995 } else if (dst
.regClass() == v1
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1997 } else if (dst
.regClass() == v2
) {
1998 if (ctx
->options
->chip_class
>= GFX7
) {
1999 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2001 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2002 /* trunc = trunc(src0)
2003 * if (src0 > 0.0 && src0 != trunc)
2006 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2007 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2008 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2009 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2010 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2011 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2012 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2015 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2016 nir_print_instr(&instr
->instr
, stderr
);
2017 fprintf(stderr
, "\n");
2021 case nir_op_ftrunc
: {
2022 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2023 if (dst
.regClass() == v2b
) {
2024 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2025 } else if (dst
.regClass() == v1
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2027 } else if (dst
.regClass() == v2
) {
2028 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2030 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2031 nir_print_instr(&instr
->instr
, stderr
);
2032 fprintf(stderr
, "\n");
2036 case nir_op_fround_even
: {
2037 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2038 if (dst
.regClass() == v2b
) {
2039 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2040 } else if (dst
.regClass() == v1
) {
2041 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2042 } else if (dst
.regClass() == v2
) {
2043 if (ctx
->options
->chip_class
>= GFX7
) {
2044 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2046 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2047 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2048 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2050 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2051 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2052 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2053 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2054 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2055 tmp
= sub
->definitions
[0].getTemp();
2057 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2058 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2059 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2060 Temp cond
= vop3
->definitions
[0].getTemp();
2062 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2063 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2064 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2065 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2067 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2070 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2071 nir_print_instr(&instr
->instr
, stderr
);
2072 fprintf(stderr
, "\n");
2078 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2079 aco_ptr
<Instruction
> norm
;
2080 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2081 if (dst
.regClass() == v2b
) {
2082 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2083 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2084 bld
.vop1(opcode
, Definition(dst
), tmp
);
2085 } else if (dst
.regClass() == v1
) {
2086 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2088 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2089 if (ctx
->options
->chip_class
< GFX9
)
2090 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2092 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2093 bld
.vop1(opcode
, Definition(dst
), tmp
);
2095 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2096 nir_print_instr(&instr
->instr
, stderr
);
2097 fprintf(stderr
, "\n");
2101 case nir_op_ldexp
: {
2102 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2103 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2104 if (dst
.regClass() == v2b
) {
2105 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2106 } else if (dst
.regClass() == v1
) {
2107 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2108 } else if (dst
.regClass() == v2
) {
2109 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2112 nir_print_instr(&instr
->instr
, stderr
);
2113 fprintf(stderr
, "\n");
2117 case nir_op_frexp_sig
: {
2118 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2119 if (dst
.regClass() == v2b
) {
2120 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2121 } else if (dst
.regClass() == v1
) {
2122 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2123 } else if (dst
.regClass() == v2
) {
2124 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2126 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2127 nir_print_instr(&instr
->instr
, stderr
);
2128 fprintf(stderr
, "\n");
2132 case nir_op_frexp_exp
: {
2133 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2134 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2135 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2136 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2137 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2138 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2139 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2140 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2141 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2143 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2144 nir_print_instr(&instr
->instr
, stderr
);
2145 fprintf(stderr
, "\n");
2149 case nir_op_fsign
: {
2150 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2151 if (dst
.regClass() == v2b
) {
2152 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2153 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2154 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2155 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2156 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2157 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2158 } else if (dst
.regClass() == v1
) {
2159 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2160 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2161 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2162 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2163 } else if (dst
.regClass() == v2
) {
2164 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2165 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2166 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2168 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2169 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2170 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2172 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2174 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2175 nir_print_instr(&instr
->instr
, stderr
);
2176 fprintf(stderr
, "\n");
2181 case nir_op_f2f16_rtne
: {
2182 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2183 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2184 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2185 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2188 case nir_op_f2f16_rtz
: {
2189 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2190 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2191 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2192 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2195 case nir_op_f2f32
: {
2196 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2197 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2198 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2199 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2201 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2202 nir_print_instr(&instr
->instr
, stderr
);
2203 fprintf(stderr
, "\n");
2207 case nir_op_f2f64
: {
2208 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2209 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2210 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2211 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2214 case nir_op_i2f16
: {
2215 assert(dst
.regClass() == v2b
);
2216 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2217 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2218 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2219 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2222 case nir_op_i2f32
: {
2223 assert(dst
.size() == 1);
2224 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2225 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2226 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2227 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2230 case nir_op_i2f64
: {
2231 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2232 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2233 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2234 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2235 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2236 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2237 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2238 RegClass rc
= RegClass(src
.type(), 1);
2239 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2240 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2241 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2242 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2243 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2244 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2247 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2248 nir_print_instr(&instr
->instr
, stderr
);
2249 fprintf(stderr
, "\n");
2253 case nir_op_u2f16
: {
2254 assert(dst
.regClass() == v2b
);
2255 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2256 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2257 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2258 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2261 case nir_op_u2f32
: {
2262 assert(dst
.size() == 1);
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2265 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2266 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2268 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2269 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2270 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2274 case nir_op_u2f64
: {
2275 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2277 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2278 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2279 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2280 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 RegClass rc
= RegClass(src
.type(), 1);
2283 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2284 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2285 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2286 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2287 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2288 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2290 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2291 nir_print_instr(&instr
->instr
, stderr
);
2292 fprintf(stderr
, "\n");
2297 case nir_op_f2i16
: {
2298 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2299 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2300 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2301 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2302 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2304 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2306 if (dst
.type() == RegType::vgpr
)
2307 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2309 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2313 case nir_op_f2u16
: {
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2316 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2317 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2318 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2320 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2322 if (dst
.type() == RegType::vgpr
)
2323 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2325 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2328 case nir_op_f2i32
: {
2329 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2330 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2331 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2332 if (dst
.type() == RegType::vgpr
) {
2333 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2335 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2336 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2338 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2339 if (dst
.type() == RegType::vgpr
)
2340 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2343 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2345 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2346 if (dst
.type() == RegType::vgpr
)
2347 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2349 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2350 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2353 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2354 nir_print_instr(&instr
->instr
, stderr
);
2355 fprintf(stderr
, "\n");
2359 case nir_op_f2u32
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2362 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2363 if (dst
.type() == RegType::vgpr
) {
2364 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2366 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2367 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2369 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2370 if (dst
.type() == RegType::vgpr
)
2371 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2373 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2374 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2376 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2377 if (dst
.type() == RegType::vgpr
)
2378 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2380 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2381 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2384 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2385 nir_print_instr(&instr
->instr
, stderr
);
2386 fprintf(stderr
, "\n");
2390 case nir_op_f2i64
: {
2391 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2392 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2393 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2395 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2396 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2397 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2398 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2399 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2400 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2401 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2402 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2403 Temp new_exponent
= bld
.tmp(v1
);
2404 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2405 if (ctx
->program
->chip_class
>= GFX8
)
2406 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2408 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2409 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2410 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2411 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2412 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2413 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2414 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2415 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2416 Temp new_lower
= bld
.tmp(v1
);
2417 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2418 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2419 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2421 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2422 if (src
.type() == RegType::vgpr
)
2423 src
= bld
.as_uniform(src
);
2424 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2425 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2426 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2427 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2428 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2429 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2430 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2431 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2432 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2433 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2434 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2435 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2436 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2437 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2438 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2439 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2440 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2441 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2442 Temp borrow
= bld
.tmp(s1
);
2443 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2444 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2445 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2447 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2448 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2449 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2450 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2451 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2452 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2453 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2454 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2455 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2456 if (dst
.type() == RegType::sgpr
) {
2457 lower
= bld
.as_uniform(lower
);
2458 upper
= bld
.as_uniform(upper
);
2460 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2463 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2464 nir_print_instr(&instr
->instr
, stderr
);
2465 fprintf(stderr
, "\n");
2469 case nir_op_f2u64
: {
2470 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2471 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2472 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2474 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2475 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2476 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2477 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2478 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2479 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2480 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2481 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2482 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2483 Temp new_exponent
= bld
.tmp(v1
);
2484 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2485 if (ctx
->program
->chip_class
>= GFX8
)
2486 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2488 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2489 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2490 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2491 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2492 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2493 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2494 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2495 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2497 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2498 if (src
.type() == RegType::vgpr
)
2499 src
= bld
.as_uniform(src
);
2500 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2501 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2502 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2503 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2504 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2505 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2506 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2507 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2508 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2509 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2510 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2511 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2512 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2513 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2514 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2515 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2516 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2517 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2519 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2520 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2521 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2522 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2523 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2524 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2525 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2526 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2527 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2528 if (dst
.type() == RegType::sgpr
) {
2529 lower
= bld
.as_uniform(lower
);
2530 upper
= bld
.as_uniform(upper
);
2532 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2535 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2536 nir_print_instr(&instr
->instr
, stderr
);
2537 fprintf(stderr
, "\n");
2541 case nir_op_b2f16
: {
2542 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2543 assert(src
.regClass() == bld
.lm
);
2545 if (dst
.regClass() == s1
) {
2546 src
= bool_to_scalar_condition(ctx
, src
);
2547 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2548 } else if (dst
.regClass() == v2b
) {
2549 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2550 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2552 unreachable("Wrong destination register class for nir_op_b2f16.");
2556 case nir_op_b2f32
: {
2557 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2558 assert(src
.regClass() == bld
.lm
);
2560 if (dst
.regClass() == s1
) {
2561 src
= bool_to_scalar_condition(ctx
, src
);
2562 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2563 } else if (dst
.regClass() == v1
) {
2564 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2566 unreachable("Wrong destination register class for nir_op_b2f32.");
2570 case nir_op_b2f64
: {
2571 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2572 assert(src
.regClass() == bld
.lm
);
2574 if (dst
.regClass() == s2
) {
2575 src
= bool_to_scalar_condition(ctx
, src
);
2576 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2577 } else if (dst
.regClass() == v2
) {
2578 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2579 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2580 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2582 unreachable("Wrong destination register class for nir_op_b2f64.");
2589 case nir_op_i2i64
: {
2590 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2591 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2597 case nir_op_u2u64
: {
2598 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2599 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2603 case nir_op_b2i32
: {
2604 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2605 assert(src
.regClass() == bld
.lm
);
2607 if (dst
.regClass() == s1
) {
2608 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2609 bool_to_scalar_condition(ctx
, src
, dst
);
2610 } else if (dst
.regClass() == v1
) {
2611 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2613 unreachable("Invalid register class for b2i32");
2619 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2620 assert(dst
.regClass() == bld
.lm
);
2622 if (src
.type() == RegType::vgpr
) {
2623 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2624 assert(dst
.regClass() == bld
.lm
);
2625 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2626 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2628 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2630 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2631 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2633 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2634 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2636 bool_to_vector_condition(ctx
, tmp
, dst
);
2640 case nir_op_pack_64_2x32_split
: {
2641 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2642 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2644 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2647 case nir_op_unpack_64_2x32_split_x
:
2648 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2650 case nir_op_unpack_64_2x32_split_y
:
2651 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2653 case nir_op_unpack_32_2x16_split_x
:
2654 if (dst
.type() == RegType::vgpr
) {
2655 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2657 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2660 case nir_op_unpack_32_2x16_split_y
:
2661 if (dst
.type() == RegType::vgpr
) {
2662 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2664 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2667 case nir_op_pack_32_2x16_split
: {
2668 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2669 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2670 if (dst
.regClass() == v1
) {
2671 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2672 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2673 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2675 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2676 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2677 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2681 case nir_op_pack_half_2x16
: {
2682 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2684 if (dst
.regClass() == v1
) {
2685 Temp src0
= bld
.tmp(v1
);
2686 Temp src1
= bld
.tmp(v1
);
2687 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2688 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2689 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2691 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2692 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2693 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2695 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2696 nir_print_instr(&instr
->instr
, stderr
);
2697 fprintf(stderr
, "\n");
2701 case nir_op_unpack_half_2x16_split_x
: {
2702 if (dst
.regClass() == v1
) {
2703 Builder
bld(ctx
->program
, ctx
->block
);
2704 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2706 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2707 nir_print_instr(&instr
->instr
, stderr
);
2708 fprintf(stderr
, "\n");
2712 case nir_op_unpack_half_2x16_split_y
: {
2713 if (dst
.regClass() == v1
) {
2714 Builder
bld(ctx
->program
, ctx
->block
);
2715 /* TODO: use SDWA here */
2716 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2717 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2720 nir_print_instr(&instr
->instr
, stderr
);
2721 fprintf(stderr
, "\n");
2725 case nir_op_fquantize2f16
: {
2726 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2727 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2730 if (ctx
->program
->chip_class
>= GFX8
) {
2731 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2732 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2733 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2735 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2736 * so compare the result and flush to 0 if it's smaller.
2738 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2739 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2740 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2741 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2742 cmp_res
= vop3
->definitions
[0].getTemp();
2745 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2746 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2747 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2749 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2754 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2755 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2757 if (dst
.regClass() == s1
) {
2758 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2759 } else if (dst
.regClass() == v1
) {
2760 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2762 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2763 nir_print_instr(&instr
->instr
, stderr
);
2764 fprintf(stderr
, "\n");
2768 case nir_op_bitfield_select
: {
2769 /* (mask & insert) | (~mask & base) */
2770 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2771 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2772 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2774 /* dst = (insert & bitmask) | (base & ~bitmask) */
2775 if (dst
.regClass() == s1
) {
2776 aco_ptr
<Instruction
> sop2
;
2777 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2778 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2780 if (const_insert
&& const_bitmask
) {
2781 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2783 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2784 lhs
= Operand(insert
);
2788 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2789 if (const_base
&& const_bitmask
) {
2790 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2792 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2793 rhs
= Operand(base
);
2796 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2798 } else if (dst
.regClass() == v1
) {
2799 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2800 base
= as_vgpr(ctx
, base
);
2801 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2802 insert
= as_vgpr(ctx
, insert
);
2804 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2807 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2808 nir_print_instr(&instr
->instr
, stderr
);
2809 fprintf(stderr
, "\n");
2815 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2816 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2817 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2819 if (dst
.type() == RegType::sgpr
) {
2821 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2822 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2823 if (const_offset
&& const_bits
) {
2824 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2825 extract
= Operand(const_extract
);
2829 width
= Operand(const_bits
->u32
<< 16);
2831 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2833 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2837 if (dst
.regClass() == s1
) {
2838 if (instr
->op
== nir_op_ubfe
)
2839 opcode
= aco_opcode::s_bfe_u32
;
2841 opcode
= aco_opcode::s_bfe_i32
;
2842 } else if (dst
.regClass() == s2
) {
2843 if (instr
->op
== nir_op_ubfe
)
2844 opcode
= aco_opcode::s_bfe_u64
;
2846 opcode
= aco_opcode::s_bfe_i64
;
2848 unreachable("Unsupported BFE bit size");
2851 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2855 if (dst
.regClass() == v1
) {
2856 if (instr
->op
== nir_op_ubfe
)
2857 opcode
= aco_opcode::v_bfe_u32
;
2859 opcode
= aco_opcode::v_bfe_i32
;
2861 unreachable("Unsupported BFE bit size");
2864 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2868 case nir_op_bit_count
: {
2869 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2870 if (src
.regClass() == s1
) {
2871 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2872 } else if (src
.regClass() == v1
) {
2873 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2874 } else if (src
.regClass() == v2
) {
2875 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2876 emit_extract_vector(ctx
, src
, 1, v1
),
2877 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2878 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2879 } else if (src
.regClass() == s2
) {
2880 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2882 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2883 nir_print_instr(&instr
->instr
, stderr
);
2884 fprintf(stderr
, "\n");
2889 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2893 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2897 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2901 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2905 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2909 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2913 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2914 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2916 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2917 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2921 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2922 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2924 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2925 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2938 case nir_op_fddx_fine
:
2939 case nir_op_fddy_fine
:
2940 case nir_op_fddx_coarse
:
2941 case nir_op_fddy_coarse
: {
2942 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2943 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2944 if (instr
->op
== nir_op_fddx_fine
) {
2945 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2946 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2947 } else if (instr
->op
== nir_op_fddy_fine
) {
2948 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2949 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2951 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2952 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2953 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2955 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2959 if (ctx
->program
->chip_class
>= GFX8
) {
2960 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2961 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2963 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2964 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2965 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2967 emit_wqm(ctx
, tmp
, dst
, true);
2971 fprintf(stderr
, "Unknown NIR ALU instr: ");
2972 nir_print_instr(&instr
->instr
, stderr
);
2973 fprintf(stderr
, "\n");
2977 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2979 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2981 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2982 // which get truncated the lsb if double and msb if int
2983 // for now, we only use s_mov_b64 with 64bit inline constants
2984 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2985 assert(dst
.type() == RegType::sgpr
);
2987 Builder
bld(ctx
->program
, ctx
->block
);
2989 if (instr
->def
.bit_size
== 1) {
2990 assert(dst
.regClass() == bld
.lm
);
2991 int val
= instr
->value
[0].b
? -1 : 0;
2992 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2993 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2994 } else if (instr
->def
.bit_size
== 8) {
2995 /* ensure that the value is correctly represented in the low byte of the register */
2996 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2997 } else if (instr
->def
.bit_size
== 16) {
2998 /* ensure that the value is correctly represented in the low half of the register */
2999 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3000 } else if (dst
.size() == 1) {
3001 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3003 assert(dst
.size() != 1);
3004 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3005 if (instr
->def
.bit_size
== 64)
3006 for (unsigned i
= 0; i
< dst
.size(); i
++)
3007 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3009 for (unsigned i
= 0; i
< dst
.size(); i
++)
3010 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3012 vec
->definitions
[0] = Definition(dst
);
3013 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3017 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3019 uint32_t new_mask
= 0;
3020 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3021 if (mask
& (1u << i
))
3022 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3026 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3028 Builder
bld(ctx
->program
, ctx
->block
);
3029 if (offset
.isTemp()) {
3030 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
3032 if (vec
.size() == 4) {
3033 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
3034 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
3035 } else if (vec
.size() == 3) {
3036 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3037 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3038 } else if (vec
.size() == 2) {
3039 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3040 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3042 for (unsigned i
= 0; i
< dst
.size(); i
++)
3043 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3046 if (dst
.size() == 2)
3047 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3049 offset
= Operand(0u);
3052 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3053 bld
.copy(Definition(dst
), vec
);
3055 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3058 struct LoadEmitInfo
{
3061 unsigned num_components
;
3062 unsigned component_size
;
3063 Temp resource
= Temp(0, s1
);
3064 unsigned component_stride
= 0;
3065 unsigned const_offset
= 0;
3066 unsigned align_mul
= 0;
3067 unsigned align_offset
= 0;
3070 unsigned swizzle_component_size
= 0;
3071 barrier_interaction barrier
= barrier_none
;
3072 bool can_reorder
= true;
3073 Temp soffset
= Temp(0, s1
);
3076 using LoadCallback
= Temp(*)(
3077 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3078 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3080 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3081 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3083 unsigned load_size
= info
->num_components
* info
->component_size
;
3084 unsigned component_size
= info
->component_size
;
3086 unsigned num_vals
= 0;
3087 Temp vals
[info
->dst
.bytes()];
3089 unsigned const_offset
= info
->const_offset
;
3091 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3092 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3094 unsigned bytes_read
= 0;
3095 while (bytes_read
< load_size
) {
3096 unsigned bytes_needed
= load_size
- bytes_read
;
3098 /* add buffer for unaligned loads */
3099 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3102 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3103 if (info
->component_stride
) {
3104 assert(supports_8bit_16bit_loads
&& "unimplemented");
3108 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3109 bytes_needed
= align(bytes_needed
, 4);
3116 if (info
->swizzle_component_size
)
3117 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3118 if (info
->component_stride
)
3119 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3121 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3123 /* reduce constant offset */
3124 Operand offset
= info
->offset
;
3125 unsigned reduced_const_offset
= const_offset
;
3126 bool remove_const_offset_completely
= need_to_align_offset
;
3127 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3128 unsigned to_add
= const_offset
;
3129 if (remove_const_offset_completely
) {
3130 reduced_const_offset
= 0;
3132 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3133 reduced_const_offset
%= max_const_offset_plus_one
;
3135 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3136 if (offset
.isConstant()) {
3137 offset
= Operand(offset
.constantValue() + to_add
);
3138 } else if (offset_tmp
.regClass() == s1
) {
3139 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3140 offset_tmp
, Operand(to_add
));
3141 } else if (offset_tmp
.regClass() == v1
) {
3142 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3144 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3145 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3146 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3148 if (offset_tmp
.regClass() == s2
) {
3149 Temp carry
= bld
.tmp(s1
);
3150 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3151 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3152 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3154 Temp new_lo
= bld
.tmp(v1
);
3155 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3156 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3157 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3162 /* align offset down if needed */
3163 Operand aligned_offset
= offset
;
3164 if (need_to_align_offset
) {
3165 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3166 if (offset
.isConstant()) {
3167 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3168 } else if (offset_tmp
.regClass() == s1
) {
3169 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3170 } else if (offset_tmp
.regClass() == s2
) {
3171 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3172 } else if (offset_tmp
.regClass() == v1
) {
3173 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3174 } else if (offset_tmp
.regClass() == v2
) {
3175 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3176 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3177 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3178 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3181 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3182 bld
.copy(bld
.def(s1
), aligned_offset
);
3184 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3185 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3186 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3188 /* shift result right if needed */
3190 Operand
align((uint32_t)byte_align
);
3191 if (byte_align
== -1) {
3192 if (offset
.isConstant())
3193 align
= Operand(offset
.constantValue() % 4u);
3194 else if (offset
.size() == 2)
3195 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3200 if (align
.isTemp() || align
.constantValue()) {
3201 assert(val
.bytes() >= load_size
&& "unimplemented");
3202 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3203 if (val
.type() == RegType::sgpr
)
3204 byte_align_scalar(ctx
, val
, align
, new_val
);
3206 byte_align_vector(ctx
, val
, align
, new_val
);
3211 /* add result to list and advance */
3212 if (info
->component_stride
) {
3213 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3214 const_offset
+= info
->component_stride
;
3215 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3217 const_offset
+= val
.bytes();
3218 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3220 bytes_read
+= val
.bytes();
3221 vals
[num_vals
++] = val
;
3224 /* the callback wrote directly to dst */
3225 if (vals
[0] == info
->dst
) {
3226 assert(num_vals
== 1);
3227 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3231 /* create array of components */
3232 unsigned components_split
= 0;
3233 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3234 bool has_vgprs
= false;
3235 for (unsigned i
= 0; i
< num_vals
;) {
3237 unsigned num_tmps
= 0;
3238 unsigned tmp_size
= 0;
3239 RegType reg_type
= RegType::sgpr
;
3240 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3241 if (vals
[i
].type() == RegType::vgpr
)
3242 reg_type
= RegType::vgpr
;
3243 tmp_size
+= vals
[i
].bytes();
3244 tmp
[num_tmps
++] = vals
[i
++];
3247 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3248 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3249 for (unsigned i
= 0; i
< num_vals
; i
++)
3250 vec
->operands
[i
] = Operand(tmp
[i
]);
3251 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3252 vec
->definitions
[0] = Definition(tmp
[0]);
3253 bld
.insert(std::move(vec
));
3256 if (tmp
[0].bytes() % component_size
) {
3258 assert(i
== num_vals
);
3259 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3260 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3263 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3265 unsigned start
= components_split
;
3267 if (tmp_size
== elem_rc
.bytes()) {
3268 allocated_vec
[components_split
++] = tmp
[0];
3270 assert(tmp_size
% elem_rc
.bytes() == 0);
3271 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3272 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3273 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3274 Temp component
= bld
.tmp(elem_rc
);
3275 allocated_vec
[components_split
++] = component
;
3276 split
->definitions
[i
] = Definition(component
);
3278 split
->operands
[0] = Operand(tmp
[0]);
3279 bld
.insert(std::move(split
));
3282 /* try to p_as_uniform early so we can create more optimizable code and
3283 * also update allocated_vec */
3284 for (unsigned j
= start
; j
< components_split
; j
++) {
3285 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3286 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3287 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3291 /* concatenate components and p_as_uniform() result if needed */
3292 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3293 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3295 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3297 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3298 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3299 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3300 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3302 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3303 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3304 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3305 vec
->definitions
[0] = Definition(tmp
);
3306 bld
.insert(std::move(vec
));
3307 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3309 vec
->definitions
[0] = Definition(info
->dst
);
3310 bld
.insert(std::move(vec
));
3314 Operand
load_lds_size_m0(Builder
& bld
)
3316 /* TODO: m0 does not need to be initialized on GFX9+ */
3317 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3320 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3321 Temp offset
, unsigned bytes_needed
,
3322 unsigned align
, unsigned const_offset
,
3325 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3327 Operand m
= load_lds_size_m0(bld
);
3329 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3330 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3335 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3336 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3338 op
= aco_opcode::ds_read_b128
;
3339 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3342 op
= aco_opcode::ds_read2_b64
;
3343 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3345 op
= aco_opcode::ds_read_b96
;
3346 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3348 op
= aco_opcode::ds_read_b64
;
3349 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3352 op
= aco_opcode::ds_read2_b32
;
3353 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3355 op
= aco_opcode::ds_read_b32
;
3356 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3358 op
= aco_opcode::ds_read_u16
;
3361 op
= aco_opcode::ds_read_u8
;
3364 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3365 if (const_offset
>= max_offset_plus_one
) {
3366 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3367 const_offset
%= max_offset_plus_one
;
3371 const_offset
/= (size
/ 2u);
3373 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3374 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3376 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3378 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3381 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3386 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3388 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3389 Temp offset
, unsigned bytes_needed
,
3390 unsigned align
, unsigned const_offset
,
3395 if (bytes_needed
<= 4) {
3397 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3398 } else if (bytes_needed
<= 8) {
3400 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3401 } else if (bytes_needed
<= 16) {
3403 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3404 } else if (bytes_needed
<= 32) {
3406 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3409 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3411 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3412 if (info
->resource
.id()) {
3413 load
->operands
[0] = Operand(info
->resource
);
3414 load
->operands
[1] = Operand(offset
);
3416 load
->operands
[0] = Operand(offset
);
3417 load
->operands
[1] = Operand(0u);
3419 RegClass
rc(RegType::sgpr
, size
);
3420 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3421 load
->definitions
[0] = Definition(val
);
3422 load
->glc
= info
->glc
;
3423 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3424 load
->barrier
= info
->barrier
;
3425 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3426 bld
.insert(std::move(load
));
3430 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3432 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3433 Temp offset
, unsigned bytes_needed
,
3434 unsigned align_
, unsigned const_offset
,
3437 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3438 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3440 if (info
->soffset
.id()) {
3441 if (soffset
.isTemp())
3442 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3443 soffset
= Operand(info
->soffset
);
3446 unsigned bytes_size
= 0;
3448 if (bytes_needed
== 1) {
3450 op
= aco_opcode::buffer_load_ubyte
;
3451 } else if (bytes_needed
== 2) {
3453 op
= aco_opcode::buffer_load_ushort
;
3454 } else if (bytes_needed
<= 4) {
3456 op
= aco_opcode::buffer_load_dword
;
3457 } else if (bytes_needed
<= 8) {
3459 op
= aco_opcode::buffer_load_dwordx2
;
3460 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3462 op
= aco_opcode::buffer_load_dwordx3
;
3465 op
= aco_opcode::buffer_load_dwordx4
;
3467 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3468 mubuf
->operands
[0] = Operand(info
->resource
);
3469 mubuf
->operands
[1] = vaddr
;
3470 mubuf
->operands
[2] = soffset
;
3471 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3472 mubuf
->glc
= info
->glc
;
3473 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3474 mubuf
->barrier
= info
->barrier
;
3475 mubuf
->can_reorder
= info
->can_reorder
;
3476 mubuf
->offset
= const_offset
;
3477 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3478 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3479 mubuf
->definitions
[0] = Definition(val
);
3480 bld
.insert(std::move(mubuf
));
3483 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3488 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3490 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3492 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3493 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3495 if (addr
.type() == RegType::vgpr
)
3496 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3497 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3500 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3501 Temp offset
, unsigned bytes_needed
,
3502 unsigned align_
, unsigned const_offset
,
3505 unsigned bytes_size
= 0;
3506 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3507 bool global
= bld
.program
->chip_class
>= GFX9
;
3509 if (bytes_needed
== 1) {
3511 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3512 } else if (bytes_needed
== 2) {
3514 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3515 } else if (bytes_needed
<= 4) {
3517 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3518 } else if (bytes_needed
<= 8) {
3520 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3521 } else if (bytes_needed
<= 12 && !mubuf
) {
3523 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3526 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3528 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3529 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3531 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3532 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3533 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3534 mubuf
->operands
[2] = Operand(0u);
3535 mubuf
->glc
= info
->glc
;
3538 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3539 mubuf
->disable_wqm
= false;
3540 mubuf
->barrier
= info
->barrier
;
3541 mubuf
->definitions
[0] = Definition(val
);
3542 bld
.insert(std::move(mubuf
));
3544 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3546 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3547 flat
->operands
[0] = Operand(offset
);
3548 flat
->operands
[1] = Operand(s1
);
3549 flat
->glc
= info
->glc
;
3550 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3551 flat
->barrier
= info
->barrier
;
3553 flat
->definitions
[0] = Definition(val
);
3554 bld
.insert(std::move(flat
));
3558 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3563 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3565 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3566 Temp address
, unsigned base_offset
, unsigned align
)
3568 assert(util_is_power_of_two_nonzero(align
));
3570 Builder
bld(ctx
->program
, ctx
->block
);
3572 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3573 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3574 info
.align_mul
= align
;
3575 info
.align_offset
= 0;
3576 info
.barrier
= barrier_shared
;
3577 info
.can_reorder
= false;
3578 info
.const_offset
= base_offset
;
3579 emit_lds_load(ctx
, bld
, &info
);
3584 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3589 Builder
bld(ctx
->program
, ctx
->block
);
3591 ASSERTED
bool is_subdword
= false;
3592 for (unsigned i
= 0; i
< count
; i
++)
3593 is_subdword
|= offsets
[i
] % 4;
3594 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3595 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3597 /* count == 1 fast path */
3599 if (dst_type
== RegType::sgpr
)
3600 dst
[0] = bld
.as_uniform(src
);
3602 dst
[0] = as_vgpr(ctx
, src
);
3606 for (unsigned i
= 0; i
< count
- 1; i
++)
3607 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3608 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3610 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3611 src
= as_vgpr(ctx
, src
);
3613 /* use allocated_vec if possible */
3614 auto it
= ctx
->allocated_vec
.find(src
.id());
3615 if (it
!= ctx
->allocated_vec
.end()) {
3616 unsigned total_size
= 0;
3617 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3618 total_size
+= it
->second
[i
].bytes();
3619 if (total_size
!= src
.bytes())
3622 unsigned elem_size
= it
->second
[0].bytes();
3624 for (unsigned i
= 0; i
< count
; i
++) {
3625 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3629 for (unsigned i
= 0; i
< count
; i
++) {
3630 unsigned start_idx
= offsets
[i
] / elem_size
;
3631 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3632 if (op_count
== 1) {
3633 if (dst_type
== RegType::sgpr
)
3634 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3636 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3640 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3641 for (unsigned j
= 0; j
< op_count
; j
++) {
3642 Temp tmp
= it
->second
[start_idx
+ j
];
3643 if (dst_type
== RegType::sgpr
)
3644 tmp
= bld
.as_uniform(tmp
);
3645 vec
->operands
[j
] = Operand(tmp
);
3647 vec
->definitions
[0] = Definition(dst
[i
]);
3648 bld
.insert(std::move(vec
));
3654 if (dst_type
== RegType::sgpr
)
3655 src
= bld
.as_uniform(src
);
3659 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3660 split
->operands
[0] = Operand(src
);
3661 for (unsigned i
= 0; i
< count
; i
++)
3662 split
->definitions
[i
] = Definition(dst
[i
]);
3663 bld
.insert(std::move(split
));
3666 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3667 int *start
, int *count
)
3669 unsigned start_elem
= ffs(todo_mask
) - 1;
3670 bool skip
= !(mask
& (1 << start_elem
));
3672 mask
= ~mask
& todo_mask
;
3676 u_bit_scan_consecutive_range(&mask
, start
, count
);
3681 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3683 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3686 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3687 Temp address
, unsigned base_offset
, unsigned align
)
3689 assert(util_is_power_of_two_nonzero(align
));
3690 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3692 Builder
bld(ctx
->program
, ctx
->block
);
3693 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3694 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3696 unsigned write_count
= 0;
3697 Temp write_datas
[32];
3698 unsigned offsets
[32];
3699 aco_opcode opcodes
[32];
3701 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3703 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3706 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3707 offsets
[write_count
] = offset
;
3708 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3710 advance_write_mask(&todo
, offset
, bytes
);
3714 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3715 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3716 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3717 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3719 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3720 aco_opcode op
= aco_opcode::num_opcodes
;
3721 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3722 op
= aco_opcode::ds_write_b128
;
3724 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3725 op
= aco_opcode::ds_write_b96
;
3727 } else if (bytes
>= 8 && aligned8
) {
3728 op
= aco_opcode::ds_write_b64
;
3730 } else if (bytes
>= 4 && aligned4
) {
3731 op
= aco_opcode::ds_write_b32
;
3733 } else if (bytes
>= 2 && aligned2
) {
3734 op
= aco_opcode::ds_write_b16
;
3736 } else if (bytes
>= 1) {
3737 op
= aco_opcode::ds_write_b8
;
3743 offsets
[write_count
] = offset
;
3744 opcodes
[write_count
] = op
;
3746 advance_write_mask(&todo
, offset
, bytes
);
3749 Operand m
= load_lds_size_m0(bld
);
3751 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3753 for (unsigned i
= 0; i
< write_count
; i
++) {
3754 aco_opcode op
= opcodes
[i
];
3755 if (op
== aco_opcode::num_opcodes
)
3758 Temp data
= write_datas
[i
];
3760 unsigned second
= write_count
;
3761 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3762 for (second
= i
+ 1; second
< write_count
; second
++) {
3763 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3764 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3765 opcodes
[second
] = aco_opcode::num_opcodes
;
3771 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3772 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3774 unsigned inline_offset
= base_offset
+ offsets
[i
];
3775 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3776 Temp address_offset
= address
;
3777 if (inline_offset
> max_offset
) {
3778 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3779 inline_offset
= offsets
[i
];
3781 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3784 Temp second_data
= write_datas
[second
];
3785 inline_offset
/= data
.bytes();
3786 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3788 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3793 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3795 unsigned align
= 16;
3797 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3803 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3808 return aco_opcode::buffer_store_byte
;
3811 return aco_opcode::buffer_store_short
;
3813 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3815 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3818 return aco_opcode::buffer_store_dwordx3
;
3820 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3822 unreachable("Unexpected store size");
3823 return aco_opcode::num_opcodes
;
3826 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3827 Temp data
, unsigned writemask
, int swizzle_element_size
,
3828 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3830 unsigned write_count_with_skips
= 0;
3833 /* determine how to split the data */
3834 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3837 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3838 offsets
[write_count_with_skips
] = offset
;
3839 if (skips
[write_count_with_skips
]) {
3840 advance_write_mask(&todo
, offset
, bytes
);
3841 write_count_with_skips
++;
3845 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3846 * larger than swizzle_element_size */
3847 bytes
= MIN2(bytes
, swizzle_element_size
);
3849 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3851 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3852 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3855 /* dword or larger stores have to be dword-aligned */
3856 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3857 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3858 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3859 if (bytes
>= 4 && !dword_aligned
)
3860 bytes
= MIN2(bytes
, 2);
3862 advance_write_mask(&todo
, offset
, bytes
);
3863 write_count_with_skips
++;
3866 /* actually split data */
3867 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3870 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3873 write_datas
[*write_count
] = write_datas
[i
];
3874 offsets
[*write_count
] = offsets
[i
];
3879 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3880 unsigned split_cnt
= 0u, Temp dst
= Temp())
3882 Builder
bld(ctx
->program
, ctx
->block
);
3883 unsigned dword_size
= elem_size_bytes
/ 4;
3886 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3888 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3889 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3890 instr
->definitions
[0] = Definition(dst
);
3892 for (unsigned i
= 0; i
< cnt
; ++i
) {
3894 assert(arr
[i
].size() == dword_size
);
3895 allocated_vec
[i
] = arr
[i
];
3896 instr
->operands
[i
] = Operand(arr
[i
]);
3898 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3899 allocated_vec
[i
] = zero
;
3900 instr
->operands
[i
] = Operand(zero
);
3904 bld
.insert(std::move(instr
));
3907 emit_split_vector(ctx
, dst
, split_cnt
);
3909 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3914 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3916 if (const_offset
>= 4096) {
3917 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3918 const_offset
%= 4096u;
3921 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3922 else if (unlikely(voffset
.regClass() == s1
))
3923 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3924 else if (likely(voffset
.regClass() == v1
))
3925 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3927 unreachable("Unsupported register class of voffset");
3930 return const_offset
;
3933 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3934 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3937 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3938 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3940 Builder
bld(ctx
->program
, ctx
->block
);
3941 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3942 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3944 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3945 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3946 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3947 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3948 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3950 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3953 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3954 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3955 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3957 Builder
bld(ctx
->program
, ctx
->block
);
3958 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3960 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3962 unsigned write_count
= 0;
3963 Temp write_datas
[32];
3964 unsigned offsets
[32];
3965 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3966 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3968 for (unsigned i
= 0; i
< write_count
; i
++) {
3969 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3970 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3974 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3975 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3976 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3978 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3979 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3980 assert(!!stride
!= allow_combining
);
3982 Builder
bld(ctx
->program
, ctx
->block
);
3984 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3985 info
.component_stride
= allow_combining
? 0 : stride
;
3987 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3988 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3989 info
.align_offset
= 0;
3990 info
.soffset
= soffset
;
3991 info
.const_offset
= base_const_offset
;
3992 emit_mubuf_load(ctx
, bld
, &info
);
3995 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3997 Builder
bld(ctx
->program
, ctx
->block
);
3998 Temp offset
= base_offset
.first
;
3999 unsigned const_offset
= base_offset
.second
;
4001 if (!nir_src_is_const(*off_src
)) {
4002 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4005 /* Calculate indirect offset with stride */
4006 if (likely(indirect_offset_arg
.regClass() == v1
))
4007 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4008 else if (indirect_offset_arg
.regClass() == s1
)
4009 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4011 unreachable("Unsupported register class of indirect offset");
4013 /* Add to the supplied base offset */
4014 if (offset
.id() == 0)
4015 offset
= with_stride
;
4016 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4017 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4018 else if (offset
.size() == 1 && with_stride
.size() == 1)
4019 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4021 unreachable("Unsupported register class of indirect offset");
4023 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4024 const_offset
+= const_offset_arg
* stride
;
4027 return std::make_pair(offset
, const_offset
);
4030 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4032 Builder
bld(ctx
->program
, ctx
->block
);
4035 if (off1
.first
.id() && off2
.first
.id()) {
4036 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4037 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4038 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4039 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4041 unreachable("Unsupported register class of indirect offset");
4043 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4046 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4049 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4051 Builder
bld(ctx
->program
, ctx
->block
);
4052 unsigned const_offset
= offs
.second
* multiplier
;
4054 if (!offs
.first
.id())
4055 return std::make_pair(offs
.first
, const_offset
);
4057 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4058 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4059 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4061 return std::make_pair(offset
, const_offset
);
4064 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4066 Builder
bld(ctx
->program
, ctx
->block
);
4068 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4069 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4070 /* component is in bytes */
4071 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4073 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4074 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4075 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4078 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4080 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4083 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4085 Builder
bld(ctx
->program
, ctx
->block
);
4087 switch (ctx
->shader
->info
.stage
) {
4088 case MESA_SHADER_TESS_CTRL
:
4089 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4090 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4091 case MESA_SHADER_TESS_EVAL
:
4092 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4094 unreachable("Unsupported stage in get_tess_rel_patch_id");
4098 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4100 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4101 Builder
bld(ctx
->program
, ctx
->block
);
4103 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4104 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4106 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4108 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4109 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4111 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4112 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4113 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4115 return offset_mul(ctx
, offs
, 4u);
4118 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4120 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4121 Builder
bld(ctx
->program
, ctx
->block
);
4123 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4124 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4125 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4126 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4128 std::pair
<Temp
, unsigned> offs
= instr
4129 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4130 : std::make_pair(Temp(), 0u);
4132 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4133 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4138 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4139 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4141 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4142 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4144 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4145 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4151 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4153 Builder
bld(ctx
->program
, ctx
->block
);
4155 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4156 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4158 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4160 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4161 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4162 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4164 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4165 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4170 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4172 Builder
bld(ctx
->program
, ctx
->block
);
4174 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4175 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4176 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4177 unsigned attr_stride
= ctx
->tcs_num_patches
;
4179 std::pair
<Temp
, unsigned> offs
= instr
4180 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4181 : std::make_pair(Temp(), 0u);
4183 if (const_base_offset
)
4184 offs
.second
+= const_base_offset
* attr_stride
;
4186 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4187 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4188 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4193 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4195 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4200 unsigned drv_loc
= nir_intrinsic_base(instr
);
4201 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4203 if (!nir_src_is_const(*off_src
)) {
4209 uint64_t slot
= per_vertex
4210 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4211 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4212 return (((uint64_t) 1) << slot
) & mask
;
4215 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4217 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4218 unsigned component
= nir_intrinsic_component(instr
);
4219 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4221 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4222 if (off_instr
->type
!= nir_instr_type_load_const
)
4225 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4226 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4228 if (instr
->src
[0].ssa
->bit_size
== 64)
4229 write_mask
= widen_mask(write_mask
, 2);
4231 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4233 for (unsigned i
= 0; i
< 8; ++i
) {
4234 if (write_mask
& (1 << i
)) {
4235 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4236 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4244 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4246 /* Only TCS per-vertex inputs are supported by this function.
4247 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4249 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4252 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4253 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4254 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4255 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4256 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4257 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4262 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4263 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4264 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4269 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4271 Builder
bld(ctx
->program
, ctx
->block
);
4273 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4274 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4275 bool indirect_write
;
4276 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4277 if (temp_only_input
&& !indirect_write
)
4281 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4282 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4283 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4284 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4286 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4287 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4288 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4289 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4290 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4294 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4295 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4296 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4297 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4298 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4299 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4300 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4301 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4302 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4303 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4304 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4305 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4306 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4308 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4309 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4311 unreachable("Invalid LS or ES stage");
4314 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4315 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4316 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4320 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4325 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4326 return off
== ctx
->tcs_tess_lvl_out_loc
||
4327 off
== ctx
->tcs_tess_lvl_in_loc
;
4331 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4333 uint64_t mask
= per_vertex
4334 ? ctx
->program
->info
->tcs
.tes_inputs_read
4335 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4337 bool indirect_write
= false;
4338 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4339 return indirect_write
|| output_read_by_tes
;
4342 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4344 uint64_t mask
= per_vertex
4345 ? ctx
->shader
->info
.outputs_read
4346 : ctx
->shader
->info
.patch_outputs_read
;
4348 bool indirect_write
= false;
4349 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4350 return indirect_write
|| output_read
;
4353 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4355 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4356 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4358 Builder
bld(ctx
->program
, ctx
->block
);
4360 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4361 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4362 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4364 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4365 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4366 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4368 if (write_to_vmem
) {
4369 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4370 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4371 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4373 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4374 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4375 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4379 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4380 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4381 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4385 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4387 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4388 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4390 Builder
bld(ctx
->program
, ctx
->block
);
4392 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4393 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4394 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4395 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4397 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4400 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4402 if (ctx
->stage
== vertex_vs
||
4403 ctx
->stage
== tess_eval_vs
||
4404 ctx
->stage
== fragment_fs
||
4405 ctx
->stage
== ngg_vertex_gs
||
4406 ctx
->stage
== ngg_tess_eval_gs
||
4407 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4408 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4409 if (!stored_to_temps
) {
4410 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4411 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4412 fprintf(stderr
, "\n");
4415 } else if (ctx
->stage
== vertex_es
||
4416 ctx
->stage
== vertex_ls
||
4417 ctx
->stage
== tess_eval_es
||
4418 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4419 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4420 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4421 visit_store_ls_or_es_output(ctx
, instr
);
4422 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4423 visit_store_tcs_output(ctx
, instr
, false);
4425 unreachable("Shader stage not implemented");
4429 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4431 visit_load_tcs_output(ctx
, instr
, false);
4434 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4436 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4437 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4439 Builder
bld(ctx
->program
, ctx
->block
);
4441 if (dst
.regClass() == v2b
) {
4442 if (ctx
->program
->has_16bank_lds
) {
4443 assert(ctx
->options
->chip_class
<= GFX8
);
4444 Builder::Result interp_p1
=
4445 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4446 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4447 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4448 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4449 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4450 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4452 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4454 if (ctx
->options
->chip_class
== GFX8
)
4455 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4457 Builder::Result interp_p1
=
4458 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4459 coord1
, bld
.m0(prim_mask
), idx
, component
);
4460 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4461 interp_p1
, idx
, component
);
4464 Builder::Result interp_p1
=
4465 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4466 bld
.m0(prim_mask
), idx
, component
);
4468 if (ctx
->program
->has_16bank_lds
)
4469 interp_p1
.instr
->operands
[0].setLateKill(true);
4471 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4472 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4476 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4478 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4479 for (unsigned i
= 0; i
< num_components
; i
++)
4480 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4481 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4482 assert(num_components
== 4);
4483 Builder
bld(ctx
->program
, ctx
->block
);
4484 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4487 for (Operand
& op
: vec
->operands
)
4488 op
= op
.isUndefined() ? Operand(0u) : op
;
4490 vec
->definitions
[0] = Definition(dst
);
4491 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4492 emit_split_vector(ctx
, dst
, num_components
);
4496 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4498 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4499 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4500 unsigned idx
= nir_intrinsic_base(instr
);
4501 unsigned component
= nir_intrinsic_component(instr
);
4502 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4504 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4506 assert(offset
->u32
== 0);
4508 /* the lower 15bit of the prim_mask contain the offset into LDS
4509 * while the upper bits contain the number of prims */
4510 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4511 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4512 Builder
bld(ctx
->program
, ctx
->block
);
4513 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4514 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4515 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4516 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4517 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4520 if (instr
->dest
.ssa
.num_components
== 1) {
4521 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4523 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4524 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4526 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4527 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4528 vec
->operands
[i
] = Operand(tmp
);
4530 vec
->definitions
[0] = Definition(dst
);
4531 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4535 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4536 unsigned offset
, unsigned stride
, unsigned channels
)
4538 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4539 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4541 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4542 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4545 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4546 unsigned offset
, unsigned stride
, unsigned *channels
)
4548 if (!vtx_info
->chan_byte_size
) {
4549 *channels
= vtx_info
->num_channels
;
4550 return vtx_info
->chan_format
;
4553 unsigned num_channels
= *channels
;
4554 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4555 unsigned new_channels
= num_channels
+ 1;
4556 /* first, assume more loads is worse and try using a larger data format */
4557 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4559 /* don't make the attribute potentially out-of-bounds */
4560 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4564 if (new_channels
== 5) {
4565 /* then try decreasing load size (at the cost of more loads) */
4566 new_channels
= *channels
;
4567 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4571 if (new_channels
< *channels
)
4572 *channels
= new_channels
;
4573 num_channels
= new_channels
;
4576 switch (vtx_info
->chan_format
) {
4577 case V_008F0C_BUF_DATA_FORMAT_8
:
4578 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4579 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4580 case V_008F0C_BUF_DATA_FORMAT_16
:
4581 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4582 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4583 case V_008F0C_BUF_DATA_FORMAT_32
:
4584 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4585 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4587 unreachable("shouldn't reach here");
4588 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4591 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4592 * so we may need to fix it up. */
4593 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4595 Builder
bld(ctx
->program
, ctx
->block
);
4597 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4598 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4600 /* For the integer-like cases, do a natural sign extension.
4602 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4603 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4606 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4607 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4609 /* Convert back to the right type. */
4610 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4611 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4612 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4613 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4614 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4615 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4621 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4623 Builder
bld(ctx
->program
, ctx
->block
);
4624 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4625 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4627 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4628 if (off_instr
->type
!= nir_instr_type_load_const
) {
4629 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4630 nir_print_instr(off_instr
, stderr
);
4631 fprintf(stderr
, "\n");
4633 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4635 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4637 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4638 unsigned component
= nir_intrinsic_component(instr
);
4639 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4640 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4641 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4642 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4643 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4645 unsigned dfmt
= attrib_format
& 0xf;
4646 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4647 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4649 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4650 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4651 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4652 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4654 num_channels
= MAX2(num_channels
, 3);
4656 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4657 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4660 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4661 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4662 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4664 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4666 Temp divided
= bld
.tmp(v1
);
4667 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4668 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4670 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4673 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4676 index
= bld
.vadd32(bld
.def(v1
),
4677 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4678 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4681 Temp channels
[num_channels
];
4682 unsigned channel_start
= 0;
4683 bool direct_fetch
= false;
4685 /* skip unused channels at the start */
4686 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4687 channel_start
= ffs(mask
) - 1;
4688 for (unsigned i
= 0; i
< channel_start
; i
++)
4689 channels
[i
] = Temp(0, s1
);
4690 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4691 num_channels
= 3 - (ffs(mask
) - 1);
4695 while (channel_start
< num_channels
) {
4696 unsigned fetch_component
= num_channels
- channel_start
;
4697 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4698 bool expanded
= false;
4700 /* use MUBUF when possible to avoid possible alignment issues */
4701 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4702 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4703 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4704 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4705 vtx_info
->chan_byte_size
== 4;
4706 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4708 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4710 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4711 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4712 fetch_component
= 4;
4717 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4719 Temp fetch_index
= index
;
4720 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4721 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4722 fetch_offset
= fetch_offset
% attrib_stride
;
4725 Operand
soffset(0u);
4726 if (fetch_offset
>= 4096) {
4727 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4728 fetch_offset
%= 4096;
4732 switch (fetch_bytes
) {
4734 assert(!use_mubuf
&& bitsize
== 16);
4735 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4738 if (bitsize
== 16) {
4740 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4742 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4746 assert(!use_mubuf
&& bitsize
== 16);
4747 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4750 if (bitsize
== 16) {
4752 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4754 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4758 assert(ctx
->options
->chip_class
>= GFX7
||
4759 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4760 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4763 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4766 unreachable("Unimplemented load_input vector size");
4770 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4771 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4772 num_channels
<= 3)) {
4773 direct_fetch
= true;
4776 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4780 Instruction
*mubuf
= bld
.mubuf(opcode
,
4781 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4782 fetch_offset
, false, true).instr
;
4783 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4785 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4786 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4787 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4788 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4791 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4793 if (fetch_component
== 1) {
4794 channels
[channel_start
] = fetch_dst
;
4796 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4797 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4798 bitsize
== 16 ? v2b
: v1
);
4801 channel_start
+= fetch_component
;
4804 if (!direct_fetch
) {
4805 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4806 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4808 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4809 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4810 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4812 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4813 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4814 unsigned num_temp
= 0;
4815 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4816 unsigned idx
= i
+ component
;
4817 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4818 Temp channel
= channels
[swizzle
[idx
]];
4819 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4820 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4821 vec
->operands
[i
] = Operand(channel
);
4825 } else if (is_float
&& idx
== 3) {
4826 vec
->operands
[i
] = Operand(0x3f800000u
);
4827 } else if (!is_float
&& idx
== 3) {
4828 vec
->operands
[i
] = Operand(1u);
4830 vec
->operands
[i
] = Operand(0u);
4833 vec
->definitions
[0] = Definition(dst
);
4834 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4835 emit_split_vector(ctx
, dst
, dst
.size());
4837 if (num_temp
== dst
.size())
4838 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4840 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4841 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4842 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4843 if (off_instr
->type
!= nir_instr_type_load_const
||
4844 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4845 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4846 nir_print_instr(off_instr
, stderr
);
4847 fprintf(stderr
, "\n");
4850 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4851 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4853 assert(offset
->u32
== 0);
4855 /* the lower 15bit of the prim_mask contain the offset into LDS
4856 * while the upper bits contain the number of prims */
4857 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4858 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4859 Builder
bld(ctx
->program
, ctx
->block
);
4860 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4861 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4862 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4863 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4864 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4867 unsigned idx
= nir_intrinsic_base(instr
);
4868 unsigned component
= nir_intrinsic_component(instr
);
4869 unsigned vertex_id
= 2; /* P0 */
4871 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4872 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4873 switch (src0
->u32
) {
4875 vertex_id
= 2; /* P0 */
4878 vertex_id
= 0; /* P10 */
4881 vertex_id
= 1; /* P20 */
4884 unreachable("invalid vertex index");
4888 if (dst
.size() == 1) {
4889 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4891 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4892 for (unsigned i
= 0; i
< dst
.size(); i
++)
4893 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4894 vec
->definitions
[0] = Definition(dst
);
4895 bld
.insert(std::move(vec
));
4898 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4899 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4900 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4901 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4902 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4904 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4906 unreachable("Shader stage not implemented");
4910 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4912 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4914 Builder
bld(ctx
->program
, ctx
->block
);
4915 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4918 if (!nir_src_is_const(*vertex_src
)) {
4919 /* better code could be created, but this case probably doesn't happen
4920 * much in practice */
4921 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4922 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4925 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4926 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4928 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4930 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4933 if (vertex_offset
.id()) {
4934 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4935 Operand(i
), indirect_vertex
);
4936 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4938 vertex_offset
= elem
;
4942 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4943 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4945 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4946 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4947 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4948 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4949 Operand((vertex
% 2u) * 16u), Operand(16u));
4951 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4954 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4955 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4956 return offset_mul(ctx
, offs
, 4u);
4959 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4961 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4963 Builder
bld(ctx
->program
, ctx
->block
);
4964 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4965 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4967 if (ctx
->stage
== geometry_gs
) {
4968 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4969 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4970 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4971 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4972 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4973 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4974 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4976 unreachable("Unsupported GS stage.");
4980 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4982 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4984 Builder
bld(ctx
->program
, ctx
->block
);
4985 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4987 if (load_input_from_temps(ctx
, instr
, dst
))
4990 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4991 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4992 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4994 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4997 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4999 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5001 Builder
bld(ctx
->program
, ctx
->block
);
5003 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5004 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5005 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5007 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5008 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5010 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5013 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5015 switch (ctx
->shader
->info
.stage
) {
5016 case MESA_SHADER_GEOMETRY
:
5017 visit_load_gs_per_vertex_input(ctx
, instr
);
5019 case MESA_SHADER_TESS_CTRL
:
5020 visit_load_tcs_per_vertex_input(ctx
, instr
);
5022 case MESA_SHADER_TESS_EVAL
:
5023 visit_load_tes_per_vertex_input(ctx
, instr
);
5026 unreachable("Unimplemented shader stage");
5030 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5032 visit_load_tcs_output(ctx
, instr
, true);
5035 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5037 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5038 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5040 visit_store_tcs_output(ctx
, instr
, true);
5043 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5045 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5047 Builder
bld(ctx
->program
, ctx
->block
);
5048 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5050 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5051 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5054 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5055 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5056 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5057 tes_w
= Operand(tmp
);
5060 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5061 emit_split_vector(ctx
, tess_coord
, 3);
5064 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5066 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5067 Builder
bld(ctx
->program
, ctx
->block
);
5068 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5069 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5070 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5073 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5077 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5079 Builder
bld(ctx
->program
, ctx
->block
);
5080 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5081 if (!nir_dest_is_divergent(instr
->dest
))
5082 index
= bld
.as_uniform(index
);
5083 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5084 unsigned binding
= nir_intrinsic_binding(instr
);
5087 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5088 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5089 unsigned offset
= layout
->binding
[binding
].offset
;
5091 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5092 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5093 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5094 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5095 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5098 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5099 stride
= layout
->binding
[binding
].size
;
5102 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5103 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5105 if (nir_const_index
) {
5106 const_index
= const_index
* stride
;
5107 } else if (index
.type() == RegType::vgpr
) {
5108 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5109 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5111 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5115 if (nir_const_index
) {
5116 const_index
= const_index
+ offset
;
5117 } else if (index
.type() == RegType::vgpr
) {
5118 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5120 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5124 if (nir_const_index
&& const_index
== 0) {
5126 } else if (index
.type() == RegType::vgpr
) {
5127 index
= bld
.vadd32(bld
.def(v1
),
5128 nir_const_index
? Operand(const_index
) : Operand(index
),
5131 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5132 nir_const_index
? Operand(const_index
) : Operand(index
),
5136 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5139 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5140 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5141 bool glc
=false, bool readonly
=true)
5143 Builder
bld(ctx
->program
, ctx
->block
);
5145 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5147 offset
= bld
.as_uniform(offset
);
5149 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5151 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5152 info
.can_reorder
= readonly
;
5153 info
.align_mul
= align_mul
;
5154 info
.align_offset
= align_offset
;
5156 emit_smem_load(ctx
, bld
, &info
);
5158 emit_mubuf_load(ctx
, bld
, &info
);
5161 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5163 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5164 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5166 Builder
bld(ctx
->program
, ctx
->block
);
5168 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5169 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5170 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5171 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5173 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5174 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5175 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5176 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5177 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5178 if (ctx
->options
->chip_class
>= GFX10
) {
5179 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5180 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5181 S_008F0C_RESOURCE_LEVEL(1);
5183 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5184 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5186 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5187 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5188 Operand(0xFFFFFFFFu
),
5189 Operand(desc_type
));
5190 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5191 rsrc
, upper_dwords
);
5193 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5194 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5196 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5197 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5198 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5201 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5203 Builder
bld(ctx
->program
, ctx
->block
);
5204 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5205 unsigned offset
= nir_intrinsic_base(instr
);
5206 unsigned count
= instr
->dest
.ssa
.num_components
;
5207 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5209 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5210 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5211 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5212 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5213 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5214 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5215 for (unsigned i
= 0; i
< count
; ++i
) {
5216 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5217 vec
->operands
[i
] = Operand
{elems
[i
]};
5219 vec
->definitions
[0] = Definition(dst
);
5220 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5221 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5226 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5227 if (offset
!= 0) // TODO check if index != 0 as well
5228 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5229 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5232 bool aligned
= true;
5234 if (instr
->dest
.ssa
.bit_size
== 8) {
5235 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5236 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5238 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5239 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5240 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5242 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5247 switch (vec
.size()) {
5249 op
= aco_opcode::s_load_dword
;
5252 op
= aco_opcode::s_load_dwordx2
;
5258 op
= aco_opcode::s_load_dwordx4
;
5264 op
= aco_opcode::s_load_dwordx8
;
5267 unreachable("unimplemented or forbidden load_push_constant.");
5270 bld
.smem(op
, Definition(vec
), ptr
, index
);
5273 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5274 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5279 emit_split_vector(ctx
, vec
, 4);
5280 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5281 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5282 emit_extract_vector(ctx
, vec
, 0, rc
),
5283 emit_extract_vector(ctx
, vec
, 1, rc
),
5284 emit_extract_vector(ctx
, vec
, 2, rc
));
5287 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5290 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5292 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5294 Builder
bld(ctx
->program
, ctx
->block
);
5296 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5297 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5298 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5299 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5300 if (ctx
->options
->chip_class
>= GFX10
) {
5301 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5302 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5303 S_008F0C_RESOURCE_LEVEL(1);
5305 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5306 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5309 unsigned base
= nir_intrinsic_base(instr
);
5310 unsigned range
= nir_intrinsic_range(instr
);
5312 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5313 if (base
&& offset
.type() == RegType::sgpr
)
5314 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5315 else if (base
&& offset
.type() == RegType::vgpr
)
5316 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5318 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5319 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5320 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5321 Operand(desc_type
));
5322 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5323 // TODO: get alignment information for subdword constants
5324 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5327 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5329 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5330 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5332 ctx
->program
->needs_exact
= true;
5334 // TODO: optimize uniform conditions
5335 Builder
bld(ctx
->program
, ctx
->block
);
5336 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5337 assert(src
.regClass() == bld
.lm
);
5338 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5339 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5340 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5344 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5346 Builder
bld(ctx
->program
, ctx
->block
);
5348 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5349 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5351 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5352 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5354 if (ctx
->block
->loop_nest_depth
&&
5355 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5356 /* we handle discards the same way as jump instructions */
5357 append_logical_end(ctx
->block
);
5359 /* in loops, discard behaves like break */
5360 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5361 ctx
->block
->kind
|= block_kind_discard
;
5364 /* uniform discard - loop ends here */
5365 assert(nir_instr_is_last(&instr
->instr
));
5366 ctx
->block
->kind
|= block_kind_uniform
;
5367 ctx
->cf_info
.has_branch
= true;
5368 bld
.branch(aco_opcode::p_branch
);
5369 add_linear_edge(ctx
->block
->index
, linear_target
);
5373 /* we add a break right behind the discard() instructions */
5374 ctx
->block
->kind
|= block_kind_break
;
5375 unsigned idx
= ctx
->block
->index
;
5377 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5378 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5380 /* remove critical edges from linear CFG */
5381 bld
.branch(aco_opcode::p_branch
);
5382 Block
* break_block
= ctx
->program
->create_and_insert_block();
5383 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5384 break_block
->kind
|= block_kind_uniform
;
5385 add_linear_edge(idx
, break_block
);
5386 add_linear_edge(break_block
->index
, linear_target
);
5387 bld
.reset(break_block
);
5388 bld
.branch(aco_opcode::p_branch
);
5390 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5391 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5392 add_linear_edge(idx
, continue_block
);
5393 append_logical_start(continue_block
);
5394 ctx
->block
= continue_block
;
5399 /* it can currently happen that NIR doesn't remove the unreachable code */
5400 if (!nir_instr_is_last(&instr
->instr
)) {
5401 ctx
->program
->needs_exact
= true;
5402 /* save exec somewhere temporarily so that it doesn't get
5403 * overwritten before the discard from outer exec masks */
5404 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5405 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5406 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5410 /* This condition is incorrect for uniformly branched discards in a loop
5411 * predicated by a divergent condition, but the above code catches that case
5412 * and the discard would end up turning into a discard_if.
5422 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5423 /* program just ends here */
5424 ctx
->block
->kind
|= block_kind_uniform
;
5425 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5426 0 /* enabled mask */, 9 /* dest */,
5427 false /* compressed */, true/* done */, true /* valid mask */);
5428 bld
.sopp(aco_opcode::s_endpgm
);
5429 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5431 ctx
->block
->kind
|= block_kind_discard
;
5432 /* branch and linear edge is added by visit_if() */
5436 enum aco_descriptor_type
{
5447 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5448 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5450 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5451 return dim
== ac_image_cube
||
5452 dim
== ac_image_1darray
||
5453 dim
== ac_image_2darray
||
5454 dim
== ac_image_2darraymsaa
;
5457 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5458 enum aco_descriptor_type desc_type
,
5459 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5461 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5462 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5463 if (it != ctx->tex_desc.end())
5466 Temp index
= Temp();
5467 bool index_set
= false;
5468 unsigned constant_index
= 0;
5469 unsigned descriptor_set
;
5470 unsigned base_index
;
5471 Builder
bld(ctx
->program
, ctx
->block
);
5474 assert(tex_instr
&& !image
);
5476 base_index
= tex_instr
->sampler_index
;
5478 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5479 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5483 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5484 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5486 constant_index
+= array_size
* const_value
->u32
;
5488 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5489 if (indirect
.type() == RegType::vgpr
)
5490 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5492 if (array_size
!= 1)
5493 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5499 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5503 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5505 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5506 base_index
= deref_instr
->var
->data
.binding
;
5509 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5510 list
= convert_pointer_to_64_bit(ctx
, list
);
5512 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5513 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5514 unsigned offset
= binding
->offset
;
5515 unsigned stride
= binding
->size
;
5519 assert(base_index
< layout
->binding_count
);
5521 switch (desc_type
) {
5522 case ACO_DESC_IMAGE
:
5524 opcode
= aco_opcode::s_load_dwordx8
;
5526 case ACO_DESC_FMASK
:
5528 opcode
= aco_opcode::s_load_dwordx8
;
5531 case ACO_DESC_SAMPLER
:
5533 opcode
= aco_opcode::s_load_dwordx4
;
5534 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5535 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5537 case ACO_DESC_BUFFER
:
5539 opcode
= aco_opcode::s_load_dwordx4
;
5541 case ACO_DESC_PLANE_0
:
5542 case ACO_DESC_PLANE_1
:
5544 opcode
= aco_opcode::s_load_dwordx8
;
5545 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5547 case ACO_DESC_PLANE_2
:
5549 opcode
= aco_opcode::s_load_dwordx4
;
5553 unreachable("invalid desc_type\n");
5556 offset
+= constant_index
* stride
;
5558 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5559 (!index_set
|| binding
->immutable_samplers_equal
)) {
5560 if (binding
->immutable_samplers_equal
)
5563 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5564 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5565 Operand(samplers
[constant_index
* 4 + 0]),
5566 Operand(samplers
[constant_index
* 4 + 1]),
5567 Operand(samplers
[constant_index
* 4 + 2]),
5568 Operand(samplers
[constant_index
* 4 + 3]));
5573 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5575 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5576 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5579 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5581 if (desc_type
== ACO_DESC_PLANE_2
) {
5583 for (unsigned i
= 0; i
< 8; i
++)
5584 components
[i
] = bld
.tmp(s1
);
5585 bld
.pseudo(aco_opcode::p_split_vector
,
5586 Definition(components
[0]),
5587 Definition(components
[1]),
5588 Definition(components
[2]),
5589 Definition(components
[3]),
5592 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5593 bld
.pseudo(aco_opcode::p_split_vector
,
5594 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5595 Definition(components
[4]),
5596 Definition(components
[5]),
5597 Definition(components
[6]),
5598 Definition(components
[7]),
5601 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5602 components
[0], components
[1], components
[2], components
[3],
5603 components
[4], components
[5], components
[6], components
[7]);
5609 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5612 case GLSL_SAMPLER_DIM_BUF
:
5614 case GLSL_SAMPLER_DIM_1D
:
5615 return array
? 2 : 1;
5616 case GLSL_SAMPLER_DIM_2D
:
5617 return array
? 3 : 2;
5618 case GLSL_SAMPLER_DIM_MS
:
5619 return array
? 4 : 3;
5620 case GLSL_SAMPLER_DIM_3D
:
5621 case GLSL_SAMPLER_DIM_CUBE
:
5623 case GLSL_SAMPLER_DIM_RECT
:
5624 case GLSL_SAMPLER_DIM_SUBPASS
:
5626 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5635 /* Adjust the sample index according to FMASK.
5637 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5638 * which is the identity mapping. Each nibble says which physical sample
5639 * should be fetched to get that sample.
5641 * For example, 0x11111100 means there are only 2 samples stored and
5642 * the second sample covers 3/4 of the pixel. When reading samples 0
5643 * and 1, return physical sample 0 (determined by the first two 0s
5644 * in FMASK), otherwise return physical sample 1.
5646 * The sample index should be adjusted as follows:
5647 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5649 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5651 Builder
bld(ctx
->program
, ctx
->block
);
5652 Temp fmask
= bld
.tmp(v1
);
5653 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5654 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5657 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5658 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5659 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5660 load
->operands
[0] = Operand(fmask_desc_ptr
);
5661 load
->operands
[1] = Operand(s4
); /* no sampler */
5662 load
->operands
[2] = Operand(coord
);
5663 load
->definitions
[0] = Definition(fmask
);
5670 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5671 ctx
->block
->instructions
.emplace_back(std::move(load
));
5673 Operand sample_index4
;
5674 if (sample_index
.isConstant()) {
5675 if (sample_index
.constantValue() < 16) {
5676 sample_index4
= Operand(sample_index
.constantValue() << 2);
5678 sample_index4
= Operand(0u);
5680 } else if (sample_index
.regClass() == s1
) {
5681 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5683 assert(sample_index
.regClass() == v1
);
5684 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5688 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5689 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5690 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5691 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5693 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5695 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5696 * resource descriptor is 0 (invalid),
5698 Temp compare
= bld
.tmp(bld
.lm
);
5699 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5700 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5702 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5704 /* Replace the MSAA sample index. */
5705 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5708 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5711 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5712 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5713 bool is_array
= glsl_sampler_type_is_array(type
);
5714 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5715 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5716 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5717 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5718 int count
= image_type_to_components_count(dim
, is_array
);
5719 std::vector
<Temp
> coords(count
);
5720 Builder
bld(ctx
->program
, ctx
->block
);
5724 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5725 /* get sample index */
5726 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5727 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5728 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5729 std::vector
<Temp
> fmask_load_address
;
5730 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5731 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5733 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5734 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5736 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5741 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5742 coords
.resize(coords
.size() + 1);
5743 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5745 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5747 for (int i
= 0; i
< count
; i
++)
5748 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5751 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5752 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5753 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5754 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5757 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5760 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5761 for (unsigned i
= 0; i
< coords
.size(); i
++)
5762 vec
->operands
[i
] = Operand(coords
[i
]);
5763 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5764 vec
->definitions
[0] = Definition(res
);
5765 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5770 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5772 Builder
bld(ctx
->program
, ctx
->block
);
5773 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5774 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5775 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5776 bool is_array
= glsl_sampler_type_is_array(type
);
5777 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5779 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5780 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5781 unsigned num_channels
= util_last_bit(mask
);
5782 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5783 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5786 switch (num_channels
) {
5788 opcode
= aco_opcode::buffer_load_format_x
;
5791 opcode
= aco_opcode::buffer_load_format_xy
;
5794 opcode
= aco_opcode::buffer_load_format_xyz
;
5797 opcode
= aco_opcode::buffer_load_format_xyzw
;
5800 unreachable(">4 channel buffer image load");
5802 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5803 load
->operands
[0] = Operand(rsrc
);
5804 load
->operands
[1] = Operand(vindex
);
5805 load
->operands
[2] = Operand((uint32_t) 0);
5807 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5810 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5811 load
->definitions
[0] = Definition(tmp
);
5813 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5814 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5815 load
->barrier
= barrier_image
;
5816 ctx
->block
->instructions
.emplace_back(std::move(load
));
5818 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5822 Temp coords
= get_image_coords(ctx
, instr
, type
);
5823 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5825 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5826 unsigned num_components
= util_bitcount(dmask
);
5828 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5831 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5833 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5834 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5836 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5837 load
->operands
[0] = Operand(resource
);
5838 load
->operands
[1] = Operand(s4
); /* no sampler */
5839 load
->operands
[2] = Operand(coords
);
5840 load
->definitions
[0] = Definition(tmp
);
5841 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5842 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5843 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5844 load
->dmask
= dmask
;
5846 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5847 load
->barrier
= barrier_image
;
5848 ctx
->block
->instructions
.emplace_back(std::move(load
));
5850 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5854 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5856 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5857 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5858 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5859 bool is_array
= glsl_sampler_type_is_array(type
);
5860 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5862 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5864 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5865 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5866 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5868 switch (data
.size()) {
5870 opcode
= aco_opcode::buffer_store_format_x
;
5873 opcode
= aco_opcode::buffer_store_format_xy
;
5876 opcode
= aco_opcode::buffer_store_format_xyz
;
5879 opcode
= aco_opcode::buffer_store_format_xyzw
;
5882 unreachable(">4 channel buffer image store");
5884 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5885 store
->operands
[0] = Operand(rsrc
);
5886 store
->operands
[1] = Operand(vindex
);
5887 store
->operands
[2] = Operand((uint32_t) 0);
5888 store
->operands
[3] = Operand(data
);
5889 store
->idxen
= true;
5892 store
->disable_wqm
= true;
5893 store
->barrier
= barrier_image
;
5894 ctx
->program
->needs_exact
= true;
5895 ctx
->block
->instructions
.emplace_back(std::move(store
));
5899 assert(data
.type() == RegType::vgpr
);
5900 Temp coords
= get_image_coords(ctx
, instr
, type
);
5901 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5903 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5904 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5906 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5907 store
->operands
[0] = Operand(resource
);
5908 store
->operands
[1] = Operand(data
);
5909 store
->operands
[2] = Operand(coords
);
5912 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5913 store
->dmask
= (1 << data
.size()) - 1;
5915 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5916 store
->disable_wqm
= true;
5917 store
->barrier
= barrier_image
;
5918 ctx
->program
->needs_exact
= true;
5919 ctx
->block
->instructions
.emplace_back(std::move(store
));
5923 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5925 /* return the previous value if dest is ever used */
5926 bool return_previous
= false;
5927 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5928 return_previous
= true;
5931 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5932 return_previous
= true;
5936 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5937 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5938 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5939 bool is_array
= glsl_sampler_type_is_array(type
);
5940 Builder
bld(ctx
->program
, ctx
->block
);
5942 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5943 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5945 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5946 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5948 aco_opcode buf_op
, image_op
;
5949 switch (instr
->intrinsic
) {
5950 case nir_intrinsic_image_deref_atomic_add
:
5951 buf_op
= aco_opcode::buffer_atomic_add
;
5952 image_op
= aco_opcode::image_atomic_add
;
5954 case nir_intrinsic_image_deref_atomic_umin
:
5955 buf_op
= aco_opcode::buffer_atomic_umin
;
5956 image_op
= aco_opcode::image_atomic_umin
;
5958 case nir_intrinsic_image_deref_atomic_imin
:
5959 buf_op
= aco_opcode::buffer_atomic_smin
;
5960 image_op
= aco_opcode::image_atomic_smin
;
5962 case nir_intrinsic_image_deref_atomic_umax
:
5963 buf_op
= aco_opcode::buffer_atomic_umax
;
5964 image_op
= aco_opcode::image_atomic_umax
;
5966 case nir_intrinsic_image_deref_atomic_imax
:
5967 buf_op
= aco_opcode::buffer_atomic_smax
;
5968 image_op
= aco_opcode::image_atomic_smax
;
5970 case nir_intrinsic_image_deref_atomic_and
:
5971 buf_op
= aco_opcode::buffer_atomic_and
;
5972 image_op
= aco_opcode::image_atomic_and
;
5974 case nir_intrinsic_image_deref_atomic_or
:
5975 buf_op
= aco_opcode::buffer_atomic_or
;
5976 image_op
= aco_opcode::image_atomic_or
;
5978 case nir_intrinsic_image_deref_atomic_xor
:
5979 buf_op
= aco_opcode::buffer_atomic_xor
;
5980 image_op
= aco_opcode::image_atomic_xor
;
5982 case nir_intrinsic_image_deref_atomic_exchange
:
5983 buf_op
= aco_opcode::buffer_atomic_swap
;
5984 image_op
= aco_opcode::image_atomic_swap
;
5986 case nir_intrinsic_image_deref_atomic_comp_swap
:
5987 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5988 image_op
= aco_opcode::image_atomic_cmpswap
;
5991 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5994 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5996 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5997 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5998 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5999 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6000 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6001 mubuf
->operands
[0] = Operand(resource
);
6002 mubuf
->operands
[1] = Operand(vindex
);
6003 mubuf
->operands
[2] = Operand((uint32_t)0);
6004 mubuf
->operands
[3] = Operand(data
);
6005 if (return_previous
)
6006 mubuf
->definitions
[0] = Definition(dst
);
6008 mubuf
->idxen
= true;
6009 mubuf
->glc
= return_previous
;
6010 mubuf
->dlc
= false; /* Not needed for atomics */
6011 mubuf
->disable_wqm
= true;
6012 mubuf
->barrier
= barrier_image
;
6013 ctx
->program
->needs_exact
= true;
6014 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6018 Temp coords
= get_image_coords(ctx
, instr
, type
);
6019 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6020 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6021 mimg
->operands
[0] = Operand(resource
);
6022 mimg
->operands
[1] = Operand(data
);
6023 mimg
->operands
[2] = Operand(coords
);
6024 if (return_previous
)
6025 mimg
->definitions
[0] = Definition(dst
);
6026 mimg
->glc
= return_previous
;
6027 mimg
->dlc
= false; /* Not needed for atomics */
6028 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6029 mimg
->dmask
= (1 << data
.size()) - 1;
6031 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6032 mimg
->disable_wqm
= true;
6033 mimg
->barrier
= barrier_image
;
6034 ctx
->program
->needs_exact
= true;
6035 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6039 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6041 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6042 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6043 Builder
bld(ctx
->program
, ctx
->block
);
6045 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6047 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6048 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6050 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6051 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6053 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6054 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6056 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6057 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6058 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6059 if (dst
.type() == RegType::vgpr
)
6060 bld
.copy(Definition(dst
), shr_dst
);
6062 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6064 emit_extract_vector(ctx
, desc
, 2, dst
);
6068 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6070 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6071 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6072 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6073 bool is_array
= glsl_sampler_type_is_array(type
);
6074 Builder
bld(ctx
->program
, ctx
->block
);
6076 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6077 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6078 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6082 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6085 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6087 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6089 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6090 mimg
->operands
[0] = Operand(resource
);
6091 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6092 mimg
->operands
[2] = Operand(lod
);
6093 uint8_t& dmask
= mimg
->dmask
;
6094 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6095 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6096 mimg
->da
= glsl_sampler_type_is_array(type
);
6097 mimg
->can_reorder
= true;
6098 Definition
& def
= mimg
->definitions
[0];
6099 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6101 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6102 glsl_sampler_type_is_array(type
)) {
6104 assert(instr
->dest
.ssa
.num_components
== 3);
6105 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6106 def
= Definition(tmp
);
6107 emit_split_vector(ctx
, tmp
, 3);
6109 /* divide 3rd value by 6 by multiplying with magic number */
6110 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6111 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6113 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6114 emit_extract_vector(ctx
, tmp
, 0, v1
),
6115 emit_extract_vector(ctx
, tmp
, 1, v1
),
6118 } else if (ctx
->options
->chip_class
== GFX9
&&
6119 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6120 glsl_sampler_type_is_array(type
)) {
6121 assert(instr
->dest
.ssa
.num_components
== 2);
6122 def
= Definition(dst
);
6125 def
= Definition(dst
);
6128 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6131 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6133 Builder
bld(ctx
->program
, ctx
->block
);
6134 unsigned num_components
= instr
->num_components
;
6136 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6137 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6138 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6140 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6141 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6142 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6143 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6146 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6148 Builder
bld(ctx
->program
, ctx
->block
);
6149 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6150 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6151 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6152 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6154 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6155 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6157 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6158 ctx
->options
->chip_class
>= GFX8
&&
6159 elem_size_bytes
>= 4;
6161 offset
= bld
.as_uniform(offset
);
6162 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6164 unsigned write_count
= 0;
6165 Temp write_datas
[32];
6166 unsigned offsets
[32];
6167 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6168 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6170 for (unsigned i
= 0; i
< write_count
; i
++) {
6171 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6172 if (smem
&& ctx
->stage
== fragment_fs
)
6173 op
= aco_opcode::p_fs_buffer_store_smem
;
6176 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6177 store
->operands
[0] = Operand(rsrc
);
6179 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6180 offset
, Operand(offsets
[i
]));
6181 store
->operands
[1] = Operand(off
);
6183 store
->operands
[1] = Operand(offset
);
6185 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6186 store
->operands
[1].setFixed(m0
);
6187 store
->operands
[2] = Operand(write_datas
[i
]);
6188 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6190 store
->disable_wqm
= true;
6191 store
->barrier
= barrier_buffer
;
6192 ctx
->block
->instructions
.emplace_back(std::move(store
));
6193 ctx
->program
->wb_smem_l1_on_end
= true;
6194 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6195 ctx
->block
->kind
|= block_kind_needs_lowering
;
6196 ctx
->program
->needs_exact
= true;
6199 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6200 store
->operands
[0] = Operand(rsrc
);
6201 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6202 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6203 store
->operands
[3] = Operand(write_datas
[i
]);
6204 store
->offset
= offsets
[i
];
6205 store
->offen
= (offset
.type() == RegType::vgpr
);
6206 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6208 store
->disable_wqm
= true;
6209 store
->barrier
= barrier_buffer
;
6210 ctx
->program
->needs_exact
= true;
6211 ctx
->block
->instructions
.emplace_back(std::move(store
));
6216 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6218 /* return the previous value if dest is ever used */
6219 bool return_previous
= false;
6220 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6221 return_previous
= true;
6224 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6225 return_previous
= true;
6229 Builder
bld(ctx
->program
, ctx
->block
);
6230 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6232 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6233 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6234 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6236 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6237 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6238 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6240 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6242 aco_opcode op32
, op64
;
6243 switch (instr
->intrinsic
) {
6244 case nir_intrinsic_ssbo_atomic_add
:
6245 op32
= aco_opcode::buffer_atomic_add
;
6246 op64
= aco_opcode::buffer_atomic_add_x2
;
6248 case nir_intrinsic_ssbo_atomic_imin
:
6249 op32
= aco_opcode::buffer_atomic_smin
;
6250 op64
= aco_opcode::buffer_atomic_smin_x2
;
6252 case nir_intrinsic_ssbo_atomic_umin
:
6253 op32
= aco_opcode::buffer_atomic_umin
;
6254 op64
= aco_opcode::buffer_atomic_umin_x2
;
6256 case nir_intrinsic_ssbo_atomic_imax
:
6257 op32
= aco_opcode::buffer_atomic_smax
;
6258 op64
= aco_opcode::buffer_atomic_smax_x2
;
6260 case nir_intrinsic_ssbo_atomic_umax
:
6261 op32
= aco_opcode::buffer_atomic_umax
;
6262 op64
= aco_opcode::buffer_atomic_umax_x2
;
6264 case nir_intrinsic_ssbo_atomic_and
:
6265 op32
= aco_opcode::buffer_atomic_and
;
6266 op64
= aco_opcode::buffer_atomic_and_x2
;
6268 case nir_intrinsic_ssbo_atomic_or
:
6269 op32
= aco_opcode::buffer_atomic_or
;
6270 op64
= aco_opcode::buffer_atomic_or_x2
;
6272 case nir_intrinsic_ssbo_atomic_xor
:
6273 op32
= aco_opcode::buffer_atomic_xor
;
6274 op64
= aco_opcode::buffer_atomic_xor_x2
;
6276 case nir_intrinsic_ssbo_atomic_exchange
:
6277 op32
= aco_opcode::buffer_atomic_swap
;
6278 op64
= aco_opcode::buffer_atomic_swap_x2
;
6280 case nir_intrinsic_ssbo_atomic_comp_swap
:
6281 op32
= aco_opcode::buffer_atomic_cmpswap
;
6282 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6285 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6287 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6288 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6289 mubuf
->operands
[0] = Operand(rsrc
);
6290 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6291 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6292 mubuf
->operands
[3] = Operand(data
);
6293 if (return_previous
)
6294 mubuf
->definitions
[0] = Definition(dst
);
6296 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6297 mubuf
->glc
= return_previous
;
6298 mubuf
->dlc
= false; /* Not needed for atomics */
6299 mubuf
->disable_wqm
= true;
6300 mubuf
->barrier
= barrier_buffer
;
6301 ctx
->program
->needs_exact
= true;
6302 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6305 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6307 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6308 Builder
bld(ctx
->program
, ctx
->block
);
6309 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6310 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6313 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6315 Builder
bld(ctx
->program
, ctx
->block
);
6316 unsigned num_components
= instr
->num_components
;
6317 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6319 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6320 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6321 num_components
, component_size
};
6322 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6323 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6324 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6325 info
.barrier
= barrier_buffer
;
6326 info
.can_reorder
= false;
6327 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6328 * it's safe to use SMEM */
6329 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6330 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6331 emit_global_load(ctx
, bld
, &info
);
6333 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6334 emit_smem_load(ctx
, bld
, &info
);
6338 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6340 Builder
bld(ctx
->program
, ctx
->block
);
6341 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6342 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6344 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6345 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6346 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6348 if (ctx
->options
->chip_class
>= GFX7
)
6349 addr
= as_vgpr(ctx
, addr
);
6351 unsigned write_count
= 0;
6352 Temp write_datas
[32];
6353 unsigned offsets
[32];
6354 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6355 16, &write_count
, write_datas
, offsets
);
6357 for (unsigned i
= 0; i
< write_count
; i
++) {
6358 if (ctx
->options
->chip_class
>= GFX7
) {
6359 unsigned offset
= offsets
[i
];
6360 Temp store_addr
= addr
;
6361 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6362 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6363 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6364 Temp carry
= bld
.tmp(bld
.lm
);
6365 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6367 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6368 Operand(offset
), addr0
);
6369 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6371 carry
).def(1).setHint(vcc
);
6373 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6378 bool global
= ctx
->options
->chip_class
>= GFX9
;
6380 switch (write_datas
[i
].bytes()) {
6382 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6385 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6388 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6391 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6394 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6397 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6400 unreachable("store_global not implemented for this size.");
6403 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6404 flat
->operands
[0] = Operand(store_addr
);
6405 flat
->operands
[1] = Operand(s1
);
6406 flat
->operands
[2] = Operand(write_datas
[i
]);
6409 flat
->offset
= offset
;
6410 flat
->disable_wqm
= true;
6411 flat
->barrier
= barrier_buffer
;
6412 ctx
->program
->needs_exact
= true;
6413 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6415 assert(ctx
->options
->chip_class
== GFX6
);
6417 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6419 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6421 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6422 mubuf
->operands
[0] = Operand(rsrc
);
6423 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6424 mubuf
->operands
[2] = Operand(0u);
6425 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6428 mubuf
->offset
= offsets
[i
];
6429 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6430 mubuf
->disable_wqm
= true;
6431 mubuf
->barrier
= barrier_buffer
;
6432 ctx
->program
->needs_exact
= true;
6433 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6438 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6440 /* return the previous value if dest is ever used */
6441 bool return_previous
= false;
6442 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6443 return_previous
= true;
6446 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6447 return_previous
= true;
6451 Builder
bld(ctx
->program
, ctx
->block
);
6452 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6453 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6455 if (ctx
->options
->chip_class
>= GFX7
)
6456 addr
= as_vgpr(ctx
, addr
);
6458 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6459 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6460 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6462 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6464 aco_opcode op32
, op64
;
6466 if (ctx
->options
->chip_class
>= GFX7
) {
6467 bool global
= ctx
->options
->chip_class
>= GFX9
;
6468 switch (instr
->intrinsic
) {
6469 case nir_intrinsic_global_atomic_add
:
6470 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6471 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6473 case nir_intrinsic_global_atomic_imin
:
6474 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6475 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6477 case nir_intrinsic_global_atomic_umin
:
6478 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6479 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6481 case nir_intrinsic_global_atomic_imax
:
6482 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6483 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6485 case nir_intrinsic_global_atomic_umax
:
6486 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6487 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6489 case nir_intrinsic_global_atomic_and
:
6490 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6491 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6493 case nir_intrinsic_global_atomic_or
:
6494 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6495 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6497 case nir_intrinsic_global_atomic_xor
:
6498 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6499 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6501 case nir_intrinsic_global_atomic_exchange
:
6502 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6503 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6505 case nir_intrinsic_global_atomic_comp_swap
:
6506 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6507 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6510 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6513 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6514 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6515 flat
->operands
[0] = Operand(addr
);
6516 flat
->operands
[1] = Operand(s1
);
6517 flat
->operands
[2] = Operand(data
);
6518 if (return_previous
)
6519 flat
->definitions
[0] = Definition(dst
);
6520 flat
->glc
= return_previous
;
6521 flat
->dlc
= false; /* Not needed for atomics */
6523 flat
->disable_wqm
= true;
6524 flat
->barrier
= barrier_buffer
;
6525 ctx
->program
->needs_exact
= true;
6526 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6528 assert(ctx
->options
->chip_class
== GFX6
);
6530 switch (instr
->intrinsic
) {
6531 case nir_intrinsic_global_atomic_add
:
6532 op32
= aco_opcode::buffer_atomic_add
;
6533 op64
= aco_opcode::buffer_atomic_add_x2
;
6535 case nir_intrinsic_global_atomic_imin
:
6536 op32
= aco_opcode::buffer_atomic_smin
;
6537 op64
= aco_opcode::buffer_atomic_smin_x2
;
6539 case nir_intrinsic_global_atomic_umin
:
6540 op32
= aco_opcode::buffer_atomic_umin
;
6541 op64
= aco_opcode::buffer_atomic_umin_x2
;
6543 case nir_intrinsic_global_atomic_imax
:
6544 op32
= aco_opcode::buffer_atomic_smax
;
6545 op64
= aco_opcode::buffer_atomic_smax_x2
;
6547 case nir_intrinsic_global_atomic_umax
:
6548 op32
= aco_opcode::buffer_atomic_umax
;
6549 op64
= aco_opcode::buffer_atomic_umax_x2
;
6551 case nir_intrinsic_global_atomic_and
:
6552 op32
= aco_opcode::buffer_atomic_and
;
6553 op64
= aco_opcode::buffer_atomic_and_x2
;
6555 case nir_intrinsic_global_atomic_or
:
6556 op32
= aco_opcode::buffer_atomic_or
;
6557 op64
= aco_opcode::buffer_atomic_or_x2
;
6559 case nir_intrinsic_global_atomic_xor
:
6560 op32
= aco_opcode::buffer_atomic_xor
;
6561 op64
= aco_opcode::buffer_atomic_xor_x2
;
6563 case nir_intrinsic_global_atomic_exchange
:
6564 op32
= aco_opcode::buffer_atomic_swap
;
6565 op64
= aco_opcode::buffer_atomic_swap_x2
;
6567 case nir_intrinsic_global_atomic_comp_swap
:
6568 op32
= aco_opcode::buffer_atomic_cmpswap
;
6569 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6572 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6575 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6577 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6579 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6580 mubuf
->operands
[0] = Operand(rsrc
);
6581 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6582 mubuf
->operands
[2] = Operand(0u);
6583 mubuf
->operands
[3] = Operand(data
);
6584 if (return_previous
)
6585 mubuf
->definitions
[0] = Definition(dst
);
6586 mubuf
->glc
= return_previous
;
6589 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6590 mubuf
->disable_wqm
= true;
6591 mubuf
->barrier
= barrier_buffer
;
6592 ctx
->program
->needs_exact
= true;
6593 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6597 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6598 Builder
bld(ctx
->program
, ctx
->block
);
6599 switch(instr
->intrinsic
) {
6600 case nir_intrinsic_group_memory_barrier
:
6601 case nir_intrinsic_memory_barrier
:
6602 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6604 case nir_intrinsic_memory_barrier_buffer
:
6605 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6607 case nir_intrinsic_memory_barrier_image
:
6608 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6610 case nir_intrinsic_memory_barrier_tcs_patch
:
6611 case nir_intrinsic_memory_barrier_shared
:
6612 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6615 unreachable("Unimplemented memory barrier intrinsic");
6620 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6622 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6623 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6624 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6625 Builder
bld(ctx
->program
, ctx
->block
);
6627 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6628 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6629 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6632 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6634 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6635 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6636 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6637 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6639 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6640 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6643 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6645 unsigned offset
= nir_intrinsic_base(instr
);
6646 Builder
bld(ctx
->program
, ctx
->block
);
6647 Operand m
= load_lds_size_m0(bld
);
6648 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6649 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6651 unsigned num_operands
= 3;
6652 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6653 switch(instr
->intrinsic
) {
6654 case nir_intrinsic_shared_atomic_add
:
6655 op32
= aco_opcode::ds_add_u32
;
6656 op64
= aco_opcode::ds_add_u64
;
6657 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6658 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6660 case nir_intrinsic_shared_atomic_imin
:
6661 op32
= aco_opcode::ds_min_i32
;
6662 op64
= aco_opcode::ds_min_i64
;
6663 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6664 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6666 case nir_intrinsic_shared_atomic_umin
:
6667 op32
= aco_opcode::ds_min_u32
;
6668 op64
= aco_opcode::ds_min_u64
;
6669 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6670 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6672 case nir_intrinsic_shared_atomic_imax
:
6673 op32
= aco_opcode::ds_max_i32
;
6674 op64
= aco_opcode::ds_max_i64
;
6675 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6676 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6678 case nir_intrinsic_shared_atomic_umax
:
6679 op32
= aco_opcode::ds_max_u32
;
6680 op64
= aco_opcode::ds_max_u64
;
6681 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6682 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6684 case nir_intrinsic_shared_atomic_and
:
6685 op32
= aco_opcode::ds_and_b32
;
6686 op64
= aco_opcode::ds_and_b64
;
6687 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6688 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6690 case nir_intrinsic_shared_atomic_or
:
6691 op32
= aco_opcode::ds_or_b32
;
6692 op64
= aco_opcode::ds_or_b64
;
6693 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6694 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6696 case nir_intrinsic_shared_atomic_xor
:
6697 op32
= aco_opcode::ds_xor_b32
;
6698 op64
= aco_opcode::ds_xor_b64
;
6699 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6700 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6702 case nir_intrinsic_shared_atomic_exchange
:
6703 op32
= aco_opcode::ds_write_b32
;
6704 op64
= aco_opcode::ds_write_b64
;
6705 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6706 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6708 case nir_intrinsic_shared_atomic_comp_swap
:
6709 op32
= aco_opcode::ds_cmpst_b32
;
6710 op64
= aco_opcode::ds_cmpst_b64
;
6711 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6712 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6716 unreachable("Unhandled shared atomic intrinsic");
6719 /* return the previous value if dest is ever used */
6720 bool return_previous
= false;
6721 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6722 return_previous
= true;
6725 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6726 return_previous
= true;
6731 if (data
.size() == 1) {
6732 assert(instr
->dest
.ssa
.bit_size
== 32);
6733 op
= return_previous
? op32_rtn
: op32
;
6735 assert(instr
->dest
.ssa
.bit_size
== 64);
6736 op
= return_previous
? op64_rtn
: op64
;
6739 if (offset
> 65535) {
6740 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6744 aco_ptr
<DS_instruction
> ds
;
6745 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6746 ds
->operands
[0] = Operand(address
);
6747 ds
->operands
[1] = Operand(data
);
6748 if (num_operands
== 4)
6749 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6750 ds
->operands
[num_operands
- 1] = m
;
6751 ds
->offset0
= offset
;
6752 if (return_previous
)
6753 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6754 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6757 Temp
get_scratch_resource(isel_context
*ctx
)
6759 Builder
bld(ctx
->program
, ctx
->block
);
6760 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6761 if (ctx
->stage
!= compute_cs
)
6762 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6764 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6765 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6767 if (ctx
->program
->chip_class
>= GFX10
) {
6768 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6769 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6770 S_008F0C_RESOURCE_LEVEL(1);
6771 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6772 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6773 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6776 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6777 if (ctx
->program
->chip_class
<= GFX8
)
6778 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6780 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6783 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6784 Builder
bld(ctx
->program
, ctx
->block
);
6785 Temp rsrc
= get_scratch_resource(ctx
);
6786 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6787 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6789 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6790 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6791 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6792 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6793 info
.swizzle_component_size
= 16;
6794 info
.can_reorder
= false;
6795 info
.soffset
= ctx
->program
->scratch_offset
;
6796 emit_mubuf_load(ctx
, bld
, &info
);
6799 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6800 Builder
bld(ctx
->program
, ctx
->block
);
6801 Temp rsrc
= get_scratch_resource(ctx
);
6802 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6803 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6805 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6806 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6808 unsigned write_count
= 0;
6809 Temp write_datas
[32];
6810 unsigned offsets
[32];
6811 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6812 16, &write_count
, write_datas
, offsets
);
6814 for (unsigned i
= 0; i
< write_count
; i
++) {
6815 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6816 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6820 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6821 uint8_t log2_ps_iter_samples
;
6822 if (ctx
->program
->info
->ps
.force_persample
) {
6823 log2_ps_iter_samples
=
6824 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6826 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6829 /* The bit pattern matches that used by fixed function fragment
6831 static const unsigned ps_iter_masks
[] = {
6832 0xffff, /* not used */
6838 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6840 Builder
bld(ctx
->program
, ctx
->block
);
6842 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6843 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6844 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6845 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6846 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6847 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6850 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6851 Builder
bld(ctx
->program
, ctx
->block
);
6853 unsigned stream
= nir_intrinsic_stream_id(instr
);
6854 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6855 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6856 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6859 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6861 unsigned num_components
=
6862 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6863 assert(num_components
);
6865 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6866 unsigned stream_offset
= 0;
6867 for (unsigned i
= 0; i
< stream
; i
++) {
6868 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6869 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6872 /* Limit on the stride field for <= GFX7. */
6873 assert(stride
< (1 << 14));
6875 Temp gsvs_dwords
[4];
6876 for (unsigned i
= 0; i
< 4; i
++)
6877 gsvs_dwords
[i
] = bld
.tmp(s1
);
6878 bld
.pseudo(aco_opcode::p_split_vector
,
6879 Definition(gsvs_dwords
[0]),
6880 Definition(gsvs_dwords
[1]),
6881 Definition(gsvs_dwords
[2]),
6882 Definition(gsvs_dwords
[3]),
6885 if (stream_offset
) {
6886 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6888 Temp carry
= bld
.tmp(s1
);
6889 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6890 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6893 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6894 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6896 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6897 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6899 unsigned offset
= 0;
6900 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6901 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6904 for (unsigned j
= 0; j
< 4; j
++) {
6905 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6908 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6909 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6910 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6911 if (const_offset
>= 4096u) {
6912 if (vaddr_offset
.isUndefined())
6913 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6915 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6916 const_offset
%= 4096u;
6919 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6920 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6921 mtbuf
->operands
[1] = vaddr_offset
;
6922 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6923 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6924 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6925 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6926 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6927 mtbuf
->offset
= const_offset
;
6930 mtbuf
->barrier
= barrier_gs_data
;
6931 mtbuf
->can_reorder
= true;
6932 bld
.insert(std::move(mtbuf
));
6935 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6938 /* outputs for the next vertex are undefined and keeping them around can
6939 * create invalid IR with control flow */
6940 ctx
->outputs
.mask
[i
] = 0;
6943 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6946 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6948 Builder
bld(ctx
->program
, ctx
->block
);
6950 if (cluster_size
== 1) {
6952 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6953 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6954 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6955 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6956 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6957 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6958 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6959 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6960 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6961 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6962 //subgroupAnd(val) -> (exec & ~val) == 0
6963 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6964 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6965 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6966 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6967 //subgroupOr(val) -> (val & exec) != 0
6968 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6969 return bool_to_vector_condition(ctx
, tmp
);
6970 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6971 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6972 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6973 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6974 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6975 return bool_to_vector_condition(ctx
, tmp
);
6977 //subgroupClustered{And,Or,Xor}(val, n) ->
6978 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6979 //cluster_offset = ~(n - 1) & lane_id
6980 //cluster_mask = ((1 << n) - 1)
6981 //subgroupClusteredAnd():
6982 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6983 //subgroupClusteredOr():
6984 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6985 //subgroupClusteredXor():
6986 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6987 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6988 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6991 if (op
== nir_op_iand
)
6992 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6994 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6996 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6998 if (ctx
->program
->chip_class
<= GFX7
)
6999 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7000 else if (ctx
->program
->wave_size
== 64)
7001 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7003 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7004 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7005 if (cluster_mask
!= 0xffffffff)
7006 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7008 Definition cmp_def
= Definition();
7009 if (op
== nir_op_iand
) {
7010 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7011 } else if (op
== nir_op_ior
) {
7012 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7013 } else if (op
== nir_op_ixor
) {
7014 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7015 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7016 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7018 cmp_def
.setHint(vcc
);
7019 return cmp_def
.getTemp();
7023 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7025 Builder
bld(ctx
->program
, ctx
->block
);
7027 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7028 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7029 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7031 if (op
== nir_op_iand
)
7032 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7034 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7036 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7037 Temp lo
= lohi
.def(0).getTemp();
7038 Temp hi
= lohi
.def(1).getTemp();
7039 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7041 Definition cmp_def
= Definition();
7042 if (op
== nir_op_iand
)
7043 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7044 else if (op
== nir_op_ior
)
7045 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7046 else if (op
== nir_op_ixor
)
7047 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7048 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7049 cmp_def
.setHint(vcc
);
7050 return cmp_def
.getTemp();
7053 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7055 Builder
bld(ctx
->program
, ctx
->block
);
7057 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7058 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7059 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7060 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7061 if (op
== nir_op_iand
)
7062 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7063 else if (op
== nir_op_ior
)
7064 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7065 else if (op
== nir_op_ixor
)
7066 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7072 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7074 Builder
bld(ctx
->program
, ctx
->block
);
7075 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7076 if (src
.regClass().type() == RegType::vgpr
) {
7077 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7078 } else if (src
.regClass() == s1
) {
7079 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7080 } else if (src
.regClass() == s2
) {
7081 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7083 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7084 nir_print_instr(&instr
->instr
, stderr
);
7085 fprintf(stderr
, "\n");
7089 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7091 Builder
bld(ctx
->program
, ctx
->block
);
7092 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7093 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7094 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7096 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7097 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7098 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7099 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7102 if (ctx
->program
->chip_class
>= GFX8
) {
7103 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7104 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7105 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7106 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7107 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7108 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7110 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7111 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7112 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7113 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7114 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7115 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7116 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7117 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7118 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7119 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7122 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7123 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7124 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7125 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7126 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7127 Temp wqm1
= bld
.tmp(v1
);
7128 emit_wqm(ctx
, tmp1
, wqm1
, true);
7129 Temp wqm2
= bld
.tmp(v1
);
7130 emit_wqm(ctx
, tmp2
, wqm2
, true);
7131 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7135 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7137 Builder
bld(ctx
->program
, ctx
->block
);
7138 switch(instr
->intrinsic
) {
7139 case nir_intrinsic_load_barycentric_sample
:
7140 case nir_intrinsic_load_barycentric_pixel
:
7141 case nir_intrinsic_load_barycentric_centroid
: {
7142 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7143 Temp bary
= Temp(0, s2
);
7145 case INTERP_MODE_SMOOTH
:
7146 case INTERP_MODE_NONE
:
7147 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7148 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7149 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7150 bary
= ctx
->persp_centroid
;
7151 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7152 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7154 case INTERP_MODE_NOPERSPECTIVE
:
7155 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7156 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7157 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7158 bary
= ctx
->linear_centroid
;
7159 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7160 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7165 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7166 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7167 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7168 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7169 Operand(p1
), Operand(p2
));
7170 emit_split_vector(ctx
, dst
, 2);
7173 case nir_intrinsic_load_barycentric_model
: {
7174 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7176 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7177 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7178 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7179 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7180 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7181 Operand(p1
), Operand(p2
), Operand(p3
));
7182 emit_split_vector(ctx
, dst
, 3);
7185 case nir_intrinsic_load_barycentric_at_sample
: {
7186 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7187 switch (ctx
->options
->key
.fs
.num_samples
) {
7188 case 2: sample_pos_offset
+= 1 << 3; break;
7189 case 4: sample_pos_offset
+= 3 << 3; break;
7190 case 8: sample_pos_offset
+= 7 << 3; break;
7194 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7195 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7196 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7197 if (addr
.type() == RegType::sgpr
) {
7200 sample_pos_offset
+= const_addr
->u32
<< 3;
7201 offset
= Operand(sample_pos_offset
);
7202 } else if (ctx
->options
->chip_class
>= GFX9
) {
7203 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7205 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7206 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7209 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7210 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7212 } else if (ctx
->options
->chip_class
>= GFX9
) {
7213 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7214 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7215 } else if (ctx
->options
->chip_class
>= GFX7
) {
7216 /* addr += private_segment_buffer + sample_pos_offset */
7217 Temp tmp0
= bld
.tmp(s1
);
7218 Temp tmp1
= bld
.tmp(s1
);
7219 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7220 Definition scc_tmp
= bld
.def(s1
, scc
);
7221 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7222 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7223 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7224 Temp pck0
= bld
.tmp(v1
);
7225 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7226 tmp1
= as_vgpr(ctx
, tmp1
);
7227 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7228 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7230 /* sample_pos = flat_load_dwordx2 addr */
7231 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7233 assert(ctx
->options
->chip_class
== GFX6
);
7235 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7236 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7237 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7239 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7240 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7242 sample_pos
= bld
.tmp(v2
);
7244 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7245 load
->definitions
[0] = Definition(sample_pos
);
7246 load
->operands
[0] = Operand(rsrc
);
7247 load
->operands
[1] = Operand(addr
);
7248 load
->operands
[2] = Operand(0u);
7249 load
->offset
= sample_pos_offset
;
7251 load
->addr64
= true;
7254 load
->disable_wqm
= false;
7255 load
->barrier
= barrier_none
;
7256 load
->can_reorder
= true;
7257 ctx
->block
->instructions
.emplace_back(std::move(load
));
7260 /* sample_pos -= 0.5 */
7261 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7262 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7263 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7264 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7265 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7267 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7270 case nir_intrinsic_load_barycentric_at_offset
: {
7271 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7272 RegClass rc
= RegClass(offset
.type(), 1);
7273 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7274 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7275 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7278 case nir_intrinsic_load_front_face
: {
7279 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7280 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7283 case nir_intrinsic_load_view_index
: {
7284 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7285 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7286 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7292 case nir_intrinsic_load_layer_id
: {
7293 unsigned idx
= nir_intrinsic_base(instr
);
7294 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7295 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7298 case nir_intrinsic_load_frag_coord
: {
7299 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7302 case nir_intrinsic_load_sample_pos
: {
7303 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7304 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7305 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7306 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7307 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7310 case nir_intrinsic_load_tess_coord
:
7311 visit_load_tess_coord(ctx
, instr
);
7313 case nir_intrinsic_load_interpolated_input
:
7314 visit_load_interpolated_input(ctx
, instr
);
7316 case nir_intrinsic_store_output
:
7317 visit_store_output(ctx
, instr
);
7319 case nir_intrinsic_load_input
:
7320 case nir_intrinsic_load_input_vertex
:
7321 visit_load_input(ctx
, instr
);
7323 case nir_intrinsic_load_output
:
7324 visit_load_output(ctx
, instr
);
7326 case nir_intrinsic_load_per_vertex_input
:
7327 visit_load_per_vertex_input(ctx
, instr
);
7329 case nir_intrinsic_load_per_vertex_output
:
7330 visit_load_per_vertex_output(ctx
, instr
);
7332 case nir_intrinsic_store_per_vertex_output
:
7333 visit_store_per_vertex_output(ctx
, instr
);
7335 case nir_intrinsic_load_ubo
:
7336 visit_load_ubo(ctx
, instr
);
7338 case nir_intrinsic_load_push_constant
:
7339 visit_load_push_constant(ctx
, instr
);
7341 case nir_intrinsic_load_constant
:
7342 visit_load_constant(ctx
, instr
);
7344 case nir_intrinsic_vulkan_resource_index
:
7345 visit_load_resource(ctx
, instr
);
7347 case nir_intrinsic_discard
:
7348 visit_discard(ctx
, instr
);
7350 case nir_intrinsic_discard_if
:
7351 visit_discard_if(ctx
, instr
);
7353 case nir_intrinsic_load_shared
:
7354 visit_load_shared(ctx
, instr
);
7356 case nir_intrinsic_store_shared
:
7357 visit_store_shared(ctx
, instr
);
7359 case nir_intrinsic_shared_atomic_add
:
7360 case nir_intrinsic_shared_atomic_imin
:
7361 case nir_intrinsic_shared_atomic_umin
:
7362 case nir_intrinsic_shared_atomic_imax
:
7363 case nir_intrinsic_shared_atomic_umax
:
7364 case nir_intrinsic_shared_atomic_and
:
7365 case nir_intrinsic_shared_atomic_or
:
7366 case nir_intrinsic_shared_atomic_xor
:
7367 case nir_intrinsic_shared_atomic_exchange
:
7368 case nir_intrinsic_shared_atomic_comp_swap
:
7369 visit_shared_atomic(ctx
, instr
);
7371 case nir_intrinsic_image_deref_load
:
7372 visit_image_load(ctx
, instr
);
7374 case nir_intrinsic_image_deref_store
:
7375 visit_image_store(ctx
, instr
);
7377 case nir_intrinsic_image_deref_atomic_add
:
7378 case nir_intrinsic_image_deref_atomic_umin
:
7379 case nir_intrinsic_image_deref_atomic_imin
:
7380 case nir_intrinsic_image_deref_atomic_umax
:
7381 case nir_intrinsic_image_deref_atomic_imax
:
7382 case nir_intrinsic_image_deref_atomic_and
:
7383 case nir_intrinsic_image_deref_atomic_or
:
7384 case nir_intrinsic_image_deref_atomic_xor
:
7385 case nir_intrinsic_image_deref_atomic_exchange
:
7386 case nir_intrinsic_image_deref_atomic_comp_swap
:
7387 visit_image_atomic(ctx
, instr
);
7389 case nir_intrinsic_image_deref_size
:
7390 visit_image_size(ctx
, instr
);
7392 case nir_intrinsic_load_ssbo
:
7393 visit_load_ssbo(ctx
, instr
);
7395 case nir_intrinsic_store_ssbo
:
7396 visit_store_ssbo(ctx
, instr
);
7398 case nir_intrinsic_load_global
:
7399 visit_load_global(ctx
, instr
);
7401 case nir_intrinsic_store_global
:
7402 visit_store_global(ctx
, instr
);
7404 case nir_intrinsic_global_atomic_add
:
7405 case nir_intrinsic_global_atomic_imin
:
7406 case nir_intrinsic_global_atomic_umin
:
7407 case nir_intrinsic_global_atomic_imax
:
7408 case nir_intrinsic_global_atomic_umax
:
7409 case nir_intrinsic_global_atomic_and
:
7410 case nir_intrinsic_global_atomic_or
:
7411 case nir_intrinsic_global_atomic_xor
:
7412 case nir_intrinsic_global_atomic_exchange
:
7413 case nir_intrinsic_global_atomic_comp_swap
:
7414 visit_global_atomic(ctx
, instr
);
7416 case nir_intrinsic_ssbo_atomic_add
:
7417 case nir_intrinsic_ssbo_atomic_imin
:
7418 case nir_intrinsic_ssbo_atomic_umin
:
7419 case nir_intrinsic_ssbo_atomic_imax
:
7420 case nir_intrinsic_ssbo_atomic_umax
:
7421 case nir_intrinsic_ssbo_atomic_and
:
7422 case nir_intrinsic_ssbo_atomic_or
:
7423 case nir_intrinsic_ssbo_atomic_xor
:
7424 case nir_intrinsic_ssbo_atomic_exchange
:
7425 case nir_intrinsic_ssbo_atomic_comp_swap
:
7426 visit_atomic_ssbo(ctx
, instr
);
7428 case nir_intrinsic_load_scratch
:
7429 visit_load_scratch(ctx
, instr
);
7431 case nir_intrinsic_store_scratch
:
7432 visit_store_scratch(ctx
, instr
);
7434 case nir_intrinsic_get_buffer_size
:
7435 visit_get_buffer_size(ctx
, instr
);
7437 case nir_intrinsic_control_barrier
: {
7438 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7439 /* GFX6 only (thanks to a hw bug workaround):
7440 * The real barrier instruction isn’t needed, because an entire patch
7441 * always fits into a single wave.
7446 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7447 bld
.sopp(aco_opcode::s_barrier
);
7451 case nir_intrinsic_memory_barrier_tcs_patch
:
7452 case nir_intrinsic_group_memory_barrier
:
7453 case nir_intrinsic_memory_barrier
:
7454 case nir_intrinsic_memory_barrier_buffer
:
7455 case nir_intrinsic_memory_barrier_image
:
7456 case nir_intrinsic_memory_barrier_shared
:
7457 emit_memory_barrier(ctx
, instr
);
7459 case nir_intrinsic_load_num_work_groups
: {
7460 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7461 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7462 emit_split_vector(ctx
, dst
, 3);
7465 case nir_intrinsic_load_local_invocation_id
: {
7466 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7467 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7468 emit_split_vector(ctx
, dst
, 3);
7471 case nir_intrinsic_load_work_group_id
: {
7472 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7473 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7474 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7475 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7476 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7477 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7478 emit_split_vector(ctx
, dst
, 3);
7481 case nir_intrinsic_load_local_invocation_index
: {
7482 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7484 /* The tg_size bits [6:11] contain the subgroup id,
7485 * we need this multiplied by the wave size, and then OR the thread id to it.
7487 if (ctx
->program
->wave_size
== 64) {
7488 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7489 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7490 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7491 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7493 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7494 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7495 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7496 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7500 case nir_intrinsic_load_subgroup_id
: {
7501 if (ctx
->stage
== compute_cs
) {
7502 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7503 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7505 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7509 case nir_intrinsic_load_subgroup_invocation
: {
7510 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7513 case nir_intrinsic_load_num_subgroups
: {
7514 if (ctx
->stage
== compute_cs
)
7515 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7516 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7518 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7521 case nir_intrinsic_ballot
: {
7522 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7523 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7524 Definition tmp
= bld
.def(dst
.regClass());
7525 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7526 if (instr
->src
[0].ssa
->bit_size
== 1) {
7527 assert(src
.regClass() == bld
.lm
);
7528 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7529 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7530 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7531 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7532 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7534 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7535 nir_print_instr(&instr
->instr
, stderr
);
7536 fprintf(stderr
, "\n");
7538 if (dst
.size() != bld
.lm
.size()) {
7539 /* Wave32 with ballot size set to 64 */
7540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7542 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7545 case nir_intrinsic_shuffle
:
7546 case nir_intrinsic_read_invocation
: {
7547 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7548 if (!nir_src_is_divergent(instr
->src
[0])) {
7549 emit_uniform_subgroup(ctx
, instr
, src
);
7551 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7552 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7553 tid
= bld
.as_uniform(tid
);
7554 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7555 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7556 Temp tmp
= bld
.tmp(v1
);
7557 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7558 if (dst
.type() == RegType::vgpr
)
7559 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7561 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7562 } else if (src
.regClass() == v1
) {
7563 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7564 } else if (src
.regClass() == v2
) {
7565 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7566 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7567 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7568 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7569 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7570 emit_split_vector(ctx
, dst
, 2);
7571 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7572 assert(src
.regClass() == bld
.lm
);
7573 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7574 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7575 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7576 assert(src
.regClass() == bld
.lm
);
7578 if (ctx
->program
->chip_class
<= GFX7
)
7579 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7580 else if (ctx
->program
->wave_size
== 64)
7581 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7583 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7584 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7585 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7586 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7588 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7589 nir_print_instr(&instr
->instr
, stderr
);
7590 fprintf(stderr
, "\n");
7595 case nir_intrinsic_load_sample_id
: {
7596 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7597 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7600 case nir_intrinsic_load_sample_mask_in
: {
7601 visit_load_sample_mask_in(ctx
, instr
);
7604 case nir_intrinsic_read_first_invocation
: {
7605 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7606 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7607 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7609 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7611 } else if (src
.regClass() == v2
) {
7612 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7613 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7614 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7615 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7616 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7617 emit_split_vector(ctx
, dst
, 2);
7618 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7619 assert(src
.regClass() == bld
.lm
);
7620 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7621 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7622 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7623 } else if (src
.regClass() == s1
) {
7624 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7625 } else if (src
.regClass() == s2
) {
7626 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7628 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7629 nir_print_instr(&instr
->instr
, stderr
);
7630 fprintf(stderr
, "\n");
7634 case nir_intrinsic_vote_all
: {
7635 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7636 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7637 assert(src
.regClass() == bld
.lm
);
7638 assert(dst
.regClass() == bld
.lm
);
7640 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7641 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7642 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7645 case nir_intrinsic_vote_any
: {
7646 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7647 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7648 assert(src
.regClass() == bld
.lm
);
7649 assert(dst
.regClass() == bld
.lm
);
7651 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7652 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7655 case nir_intrinsic_reduce
:
7656 case nir_intrinsic_inclusive_scan
:
7657 case nir_intrinsic_exclusive_scan
: {
7658 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7659 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7660 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7661 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7662 nir_intrinsic_cluster_size(instr
) : 0;
7663 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7665 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7666 emit_uniform_subgroup(ctx
, instr
, src
);
7667 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7668 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7670 else if (op
== nir_op_iadd
)
7672 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7674 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7676 switch (instr
->intrinsic
) {
7677 case nir_intrinsic_reduce
:
7678 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7680 case nir_intrinsic_exclusive_scan
:
7681 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7683 case nir_intrinsic_inclusive_scan
:
7684 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7689 } else if (cluster_size
== 1) {
7690 bld
.copy(Definition(dst
), src
);
7692 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7694 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7698 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7699 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7714 unreachable("unknown reduction op");
7720 switch (instr
->intrinsic
) {
7721 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7722 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7723 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7725 unreachable("unknown reduce intrinsic");
7728 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7729 reduce
->operands
[0] = Operand(src
);
7730 // filled in by aco_reduce_assign.cpp, used internally as part of the
7732 assert(dst
.size() == 1 || dst
.size() == 2);
7733 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7734 reduce
->operands
[2] = Operand(v1
.as_linear());
7736 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7737 reduce
->definitions
[0] = Definition(tmp_dst
);
7738 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7739 reduce
->definitions
[2] = Definition();
7740 reduce
->definitions
[3] = Definition(scc
, s1
);
7741 reduce
->definitions
[4] = Definition();
7742 reduce
->reduce_op
= reduce_op
;
7743 reduce
->cluster_size
= cluster_size
;
7744 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7746 emit_wqm(ctx
, tmp_dst
, dst
);
7750 case nir_intrinsic_quad_broadcast
: {
7751 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7752 if (!nir_dest_is_divergent(instr
->dest
)) {
7753 emit_uniform_subgroup(ctx
, instr
, src
);
7755 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7756 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7757 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7759 if (instr
->dest
.ssa
.bit_size
== 1) {
7760 assert(src
.regClass() == bld
.lm
);
7761 assert(dst
.regClass() == bld
.lm
);
7762 uint32_t half_mask
= 0x11111111u
<< lane
;
7763 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7764 Temp tmp
= bld
.tmp(bld
.lm
);
7765 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7766 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7767 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7768 emit_wqm(ctx
, tmp
, dst
);
7769 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7770 Temp tmp
= bld
.tmp(v1
);
7771 if (ctx
->program
->chip_class
>= GFX8
)
7772 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7774 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7776 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7777 Temp tmp
= bld
.tmp(v1
);
7778 if (ctx
->program
->chip_class
>= GFX8
)
7779 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7781 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7782 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7783 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7784 if (ctx
->program
->chip_class
>= GFX8
)
7785 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7787 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7788 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7789 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7790 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7791 if (ctx
->program
->chip_class
>= GFX8
) {
7792 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7793 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7795 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7796 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7798 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7799 emit_split_vector(ctx
, dst
, 2);
7801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7802 nir_print_instr(&instr
->instr
, stderr
);
7803 fprintf(stderr
, "\n");
7808 case nir_intrinsic_quad_swap_horizontal
:
7809 case nir_intrinsic_quad_swap_vertical
:
7810 case nir_intrinsic_quad_swap_diagonal
:
7811 case nir_intrinsic_quad_swizzle_amd
: {
7812 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7813 if (!nir_dest_is_divergent(instr
->dest
)) {
7814 emit_uniform_subgroup(ctx
, instr
, src
);
7817 uint16_t dpp_ctrl
= 0;
7818 switch (instr
->intrinsic
) {
7819 case nir_intrinsic_quad_swap_horizontal
:
7820 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7822 case nir_intrinsic_quad_swap_vertical
:
7823 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7825 case nir_intrinsic_quad_swap_diagonal
:
7826 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7828 case nir_intrinsic_quad_swizzle_amd
:
7829 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7834 if (ctx
->program
->chip_class
< GFX8
)
7835 dpp_ctrl
|= (1 << 15);
7837 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7838 if (instr
->dest
.ssa
.bit_size
== 1) {
7839 assert(src
.regClass() == bld
.lm
);
7840 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7841 if (ctx
->program
->chip_class
>= GFX8
)
7842 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7844 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7845 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7846 emit_wqm(ctx
, tmp
, dst
);
7847 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7848 Temp tmp
= bld
.tmp(v1
);
7849 if (ctx
->program
->chip_class
>= GFX8
)
7850 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7852 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7853 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7854 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7855 Temp tmp
= bld
.tmp(v1
);
7856 if (ctx
->program
->chip_class
>= GFX8
)
7857 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7859 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7860 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7861 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7863 if (ctx
->program
->chip_class
>= GFX8
)
7864 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7866 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7867 emit_wqm(ctx
, tmp
, dst
);
7868 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7869 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7870 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7871 if (ctx
->program
->chip_class
>= GFX8
) {
7872 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7873 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7875 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7876 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7878 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7879 emit_split_vector(ctx
, dst
, 2);
7881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7882 nir_print_instr(&instr
->instr
, stderr
);
7883 fprintf(stderr
, "\n");
7887 case nir_intrinsic_masked_swizzle_amd
: {
7888 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7889 if (!nir_dest_is_divergent(instr
->dest
)) {
7890 emit_uniform_subgroup(ctx
, instr
, src
);
7893 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7894 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7895 if (dst
.regClass() == v1
) {
7897 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7899 } else if (dst
.regClass() == v2
) {
7900 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7901 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7902 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7903 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7904 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7905 emit_split_vector(ctx
, dst
, 2);
7907 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7908 nir_print_instr(&instr
->instr
, stderr
);
7909 fprintf(stderr
, "\n");
7913 case nir_intrinsic_write_invocation_amd
: {
7914 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7915 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7916 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7917 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7918 if (dst
.regClass() == v1
) {
7919 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7920 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7921 } else if (dst
.regClass() == v2
) {
7922 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7923 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7924 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7925 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7926 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7927 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7928 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7929 emit_split_vector(ctx
, dst
, 2);
7931 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7932 nir_print_instr(&instr
->instr
, stderr
);
7933 fprintf(stderr
, "\n");
7937 case nir_intrinsic_mbcnt_amd
: {
7938 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7939 RegClass rc
= RegClass(src
.type(), 1);
7940 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7941 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7942 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7943 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7944 emit_wqm(ctx
, wqm_tmp
, dst
);
7947 case nir_intrinsic_load_helper_invocation
: {
7948 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7949 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7950 ctx
->block
->kind
|= block_kind_needs_lowering
;
7951 ctx
->program
->needs_exact
= true;
7954 case nir_intrinsic_is_helper_invocation
: {
7955 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7956 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7957 ctx
->block
->kind
|= block_kind_needs_lowering
;
7958 ctx
->program
->needs_exact
= true;
7961 case nir_intrinsic_demote
:
7962 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7964 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7965 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7966 ctx
->block
->kind
|= block_kind_uses_demote
;
7967 ctx
->program
->needs_exact
= true;
7969 case nir_intrinsic_demote_if
: {
7970 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7971 assert(src
.regClass() == bld
.lm
);
7972 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7973 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7975 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7976 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7977 ctx
->block
->kind
|= block_kind_uses_demote
;
7978 ctx
->program
->needs_exact
= true;
7981 case nir_intrinsic_first_invocation
: {
7982 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7983 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7986 case nir_intrinsic_shader_clock
: {
7988 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7989 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7990 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7991 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7994 case nir_intrinsic_load_vertex_id_zero_base
: {
7995 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7996 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7999 case nir_intrinsic_load_first_vertex
: {
8000 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8001 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8004 case nir_intrinsic_load_base_instance
: {
8005 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8006 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8009 case nir_intrinsic_load_instance_id
: {
8010 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8011 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8014 case nir_intrinsic_load_draw_id
: {
8015 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8016 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8019 case nir_intrinsic_load_invocation_id
: {
8020 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8022 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8023 if (ctx
->options
->chip_class
>= GFX10
)
8024 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8026 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8027 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8028 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8029 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8031 unreachable("Unsupported stage for load_invocation_id");
8036 case nir_intrinsic_load_primitive_id
: {
8037 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8039 switch (ctx
->shader
->info
.stage
) {
8040 case MESA_SHADER_GEOMETRY
:
8041 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8043 case MESA_SHADER_TESS_CTRL
:
8044 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8046 case MESA_SHADER_TESS_EVAL
:
8047 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8050 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8055 case nir_intrinsic_load_patch_vertices_in
: {
8056 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8057 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8059 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8060 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8063 case nir_intrinsic_emit_vertex_with_counter
: {
8064 visit_emit_vertex_with_counter(ctx
, instr
);
8067 case nir_intrinsic_end_primitive_with_counter
: {
8068 unsigned stream
= nir_intrinsic_stream_id(instr
);
8069 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8072 case nir_intrinsic_set_vertex_count
: {
8073 /* unused, the HW keeps track of this for us */
8077 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8078 nir_print_instr(&instr
->instr
, stderr
);
8079 fprintf(stderr
, "\n");
8087 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8088 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8089 enum glsl_base_type
*stype
)
8091 nir_deref_instr
*texture_deref_instr
= NULL
;
8092 nir_deref_instr
*sampler_deref_instr
= NULL
;
8095 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8096 switch (instr
->src
[i
].src_type
) {
8097 case nir_tex_src_texture_deref
:
8098 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8100 case nir_tex_src_sampler_deref
:
8101 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8103 case nir_tex_src_plane
:
8104 plane
= nir_src_as_int(instr
->src
[i
].src
);
8111 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8113 if (!sampler_deref_instr
)
8114 sampler_deref_instr
= texture_deref_instr
;
8117 assert(instr
->op
!= nir_texop_txf_ms
&&
8118 instr
->op
!= nir_texop_samples_identical
);
8119 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8120 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8121 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8122 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8123 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8124 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8126 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8129 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8131 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8132 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8133 Builder
bld(ctx
->program
, ctx
->block
);
8135 /* to avoid unnecessary moves, we split and recombine sampler and image */
8136 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8137 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8138 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8139 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8140 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8141 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8143 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8145 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8146 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8147 img
[0], img
[1], img
[2], img
[3],
8148 img
[4], img
[5], img
[6], img
[7]);
8149 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8150 samp
[0], samp
[1], samp
[2], samp
[3]);
8153 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8154 instr
->op
== nir_texop_samples_identical
))
8155 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8158 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8159 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8161 Builder
bld(ctx
->program
, ctx
->block
);
8163 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8164 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8165 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8167 Operand
neg_one(0xbf800000u
);
8168 Operand
one(0x3f800000u
);
8169 Operand
two(0x40000000u
);
8170 Operand
four(0x40800000u
);
8172 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8173 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8174 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8176 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8177 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8178 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8179 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8182 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8183 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8184 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8186 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8189 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8190 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8191 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8194 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8195 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8197 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8198 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8201 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8203 Builder
bld(ctx
->program
, ctx
->block
);
8204 Temp ma
, tc
, sc
, id
;
8207 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8209 // see comment in ac_prepare_cube_coords()
8210 if (ctx
->options
->chip_class
<= GFX8
)
8211 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8214 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8216 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8217 vop3a
->operands
[0] = Operand(ma
);
8218 vop3a
->abs
[0] = true;
8219 Temp invma
= bld
.tmp(v1
);
8220 vop3a
->definitions
[0] = Definition(invma
);
8221 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8223 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8225 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8227 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8229 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8231 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8234 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8235 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8237 for (unsigned i
= 0; i
< 2; i
++) {
8238 // see comment in ac_prepare_cube_coords()
8240 Temp deriv_sc
, deriv_tc
;
8241 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8242 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8244 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8246 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8247 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8248 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8249 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8250 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8251 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8252 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8255 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8256 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8260 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8267 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8269 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8271 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8272 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8275 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8276 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8277 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8281 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8283 Builder
bld(ctx
->program
, ctx
->block
);
8284 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8285 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8286 has_clamped_lod
= false;
8287 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8288 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8289 clamped_lod
= Temp();
8290 std::vector
<Temp
> coords
;
8291 std::vector
<Temp
> derivs
;
8292 nir_const_value
*sample_index_cv
= NULL
;
8293 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8294 enum glsl_base_type stype
;
8295 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8297 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8298 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8299 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8300 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8302 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8303 switch (instr
->src
[i
].src_type
) {
8304 case nir_tex_src_coord
: {
8305 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8306 for (unsigned i
= 0; i
< coord
.size(); i
++)
8307 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8310 case nir_tex_src_bias
:
8311 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8314 case nir_tex_src_lod
: {
8315 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8317 if (val
&& val
->f32
<= 0.0) {
8320 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8325 case nir_tex_src_min_lod
:
8326 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8327 has_clamped_lod
= true;
8329 case nir_tex_src_comparator
:
8330 if (instr
->is_shadow
) {
8331 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8335 case nir_tex_src_offset
:
8336 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8337 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8340 case nir_tex_src_ddx
:
8341 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8344 case nir_tex_src_ddy
:
8345 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8348 case nir_tex_src_ms_index
:
8349 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8350 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8351 has_sample_index
= true;
8353 case nir_tex_src_texture_offset
:
8354 case nir_tex_src_sampler_offset
:
8360 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8361 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8363 if (instr
->op
== nir_texop_texture_samples
) {
8364 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8366 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8367 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8368 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8370 Operand default_sample
= Operand(1u);
8371 if (ctx
->options
->robust_buffer_access
) {
8372 /* Extract the second dword of the descriptor, if it's
8373 * all zero, then it's a null descriptor.
8375 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8376 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8377 default_sample
= Operand(is_non_null_descriptor
);
8380 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8381 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8382 samples
, default_sample
, bld
.scc(is_msaa
));
8386 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8387 aco_ptr
<Instruction
> tmp_instr
;
8388 Temp acc
, pack
= Temp();
8390 uint32_t pack_const
= 0;
8391 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8392 if (!const_offset
[i
])
8394 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8397 if (offset
.type() == RegType::sgpr
) {
8398 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8399 if (const_offset
[i
])
8402 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8403 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8406 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8409 if (pack
== Temp()) {
8412 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8416 if (pack_const
&& pack
!= Temp())
8417 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8419 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8420 if (const_offset
[i
])
8423 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8424 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8427 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8430 if (pack
== Temp()) {
8433 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8437 if (pack_const
&& pack
!= Temp())
8438 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8440 if (pack_const
&& pack
== Temp())
8441 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8442 else if (pack
== Temp())
8448 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8449 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8451 /* pack derivatives */
8452 if (has_ddx
|| has_ddy
) {
8453 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8454 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8455 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8456 derivs
= {ddx
, zero
, ddy
, zero
};
8458 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8459 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8460 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8461 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8466 if (instr
->coord_components
> 1 &&
8467 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8469 instr
->op
!= nir_texop_txf
)
8470 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8472 if (instr
->coord_components
> 2 &&
8473 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8474 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8475 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8476 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8478 instr
->op
!= nir_texop_txf
&&
8479 instr
->op
!= nir_texop_txf_ms
&&
8480 instr
->op
!= nir_texop_fragment_fetch
&&
8481 instr
->op
!= nir_texop_fragment_mask_fetch
)
8482 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8484 if (ctx
->options
->chip_class
== GFX9
&&
8485 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8486 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8487 assert(coords
.size() > 0 && coords
.size() < 3);
8489 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8490 Operand((uint32_t) 0) :
8491 Operand((uint32_t) 0x3f000000)));
8494 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8496 if (instr
->op
== nir_texop_samples_identical
)
8497 resource
= fmask_ptr
;
8499 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8500 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8501 instr
->op
!= nir_texop_txs
&&
8502 instr
->op
!= nir_texop_fragment_fetch
&&
8503 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8504 assert(has_sample_index
);
8505 Operand
op(sample_index
);
8506 if (sample_index_cv
)
8507 op
= Operand(sample_index_cv
->u32
);
8508 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8511 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8512 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8513 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8514 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8519 /* Build tex instruction */
8520 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8521 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8522 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8524 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8527 /* gather4 selects the component by dmask and always returns vec4 */
8528 if (instr
->op
== nir_texop_tg4
) {
8529 assert(instr
->dest
.ssa
.num_components
== 4);
8530 if (instr
->is_shadow
)
8533 dmask
= 1 << instr
->component
;
8534 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8535 tmp_dst
= bld
.tmp(v4
);
8536 } else if (instr
->op
== nir_texop_samples_identical
) {
8537 tmp_dst
= bld
.tmp(v1
);
8538 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8539 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8542 aco_ptr
<MIMG_instruction
> tex
;
8543 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8545 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8547 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8548 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8551 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8552 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8554 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8555 tex
->operands
[0] = Operand(resource
);
8556 tex
->operands
[1] = Operand(s4
); /* no sampler */
8557 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8558 if (ctx
->options
->chip_class
== GFX9
&&
8559 instr
->op
== nir_texop_txs
&&
8560 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8562 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8563 } else if (instr
->op
== nir_texop_query_levels
) {
8564 tex
->dmask
= 1 << 3;
8569 tex
->definitions
[0] = Definition(tmp_dst
);
8571 tex
->can_reorder
= true;
8572 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8575 /* divide 3rd value by 6 by multiplying with magic number */
8576 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8577 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8578 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8579 assert(instr
->dest
.ssa
.num_components
== 3);
8580 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8581 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8582 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8583 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8588 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8592 Temp tg4_compare_cube_wa64
= Temp();
8594 if (tg4_integer_workarounds
) {
8595 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8596 tex
->operands
[0] = Operand(resource
);
8597 tex
->operands
[1] = Operand(s4
); /* no sampler */
8598 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8602 Temp size
= bld
.tmp(v2
);
8603 tex
->definitions
[0] = Definition(size
);
8604 tex
->can_reorder
= true;
8605 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8606 emit_split_vector(ctx
, size
, size
.size());
8609 for (unsigned i
= 0; i
< 2; i
++) {
8610 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8611 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8612 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8613 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8616 Temp new_coords
[2] = {
8617 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8618 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8621 if (tg4_integer_cube_workaround
) {
8622 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8623 Temp desc
[resource
.size()];
8624 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8625 Format::PSEUDO
, 1, resource
.size())};
8626 split
->operands
[0] = Operand(resource
);
8627 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8628 desc
[i
] = bld
.tmp(s1
);
8629 split
->definitions
[i
] = Definition(desc
[i
]);
8631 ctx
->block
->instructions
.emplace_back(std::move(split
));
8633 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8634 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8635 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8638 if (stype
== GLSL_TYPE_UINT
) {
8639 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8640 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8641 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8642 bld
.scc(compare_cube_wa
));
8644 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8645 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8646 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8647 bld
.scc(compare_cube_wa
));
8649 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8650 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8652 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8654 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8655 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8656 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8658 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8659 Format::PSEUDO
, resource
.size(), 1)};
8660 for (unsigned i
= 0; i
< resource
.size(); i
++)
8661 vec
->operands
[i
] = Operand(desc
[i
]);
8662 resource
= bld
.tmp(resource
.regClass());
8663 vec
->definitions
[0] = Definition(resource
);
8664 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8666 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8667 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8668 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8669 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8671 coords
[0] = new_coords
[0];
8672 coords
[1] = new_coords
[1];
8675 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8676 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8678 assert(coords
.size() == 1);
8679 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8683 op
= aco_opcode::buffer_load_format_x
; break;
8685 op
= aco_opcode::buffer_load_format_xy
; break;
8687 op
= aco_opcode::buffer_load_format_xyz
; break;
8689 op
= aco_opcode::buffer_load_format_xyzw
; break;
8691 unreachable("Tex instruction loads more than 4 components.");
8694 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8695 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8698 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8700 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8701 mubuf
->operands
[0] = Operand(resource
);
8702 mubuf
->operands
[1] = Operand(coords
[0]);
8703 mubuf
->operands
[2] = Operand((uint32_t) 0);
8704 mubuf
->definitions
[0] = Definition(tmp_dst
);
8705 mubuf
->idxen
= true;
8706 mubuf
->can_reorder
= true;
8707 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8709 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8713 /* gather MIMG address components */
8714 std::vector
<Temp
> args
;
8716 args
.emplace_back(offset
);
8718 args
.emplace_back(bias
);
8720 args
.emplace_back(compare
);
8722 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8724 args
.insert(args
.end(), coords
.begin(), coords
.end());
8725 if (has_sample_index
)
8726 args
.emplace_back(sample_index
);
8728 args
.emplace_back(lod
);
8729 if (has_clamped_lod
)
8730 args
.emplace_back(clamped_lod
);
8732 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8733 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8734 vec
->definitions
[0] = Definition(arg
);
8735 for (unsigned i
= 0; i
< args
.size(); i
++)
8736 vec
->operands
[i
] = Operand(args
[i
]);
8737 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8740 if (instr
->op
== nir_texop_txf
||
8741 instr
->op
== nir_texop_txf_ms
||
8742 instr
->op
== nir_texop_samples_identical
||
8743 instr
->op
== nir_texop_fragment_fetch
||
8744 instr
->op
== nir_texop_fragment_mask_fetch
) {
8745 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8746 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8747 tex
->operands
[0] = Operand(resource
);
8748 tex
->operands
[1] = Operand(s4
); /* no sampler */
8749 tex
->operands
[2] = Operand(arg
);
8754 tex
->definitions
[0] = Definition(tmp_dst
);
8755 tex
->can_reorder
= true;
8756 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8758 if (instr
->op
== nir_texop_samples_identical
) {
8759 assert(dmask
== 1 && dst
.regClass() == v1
);
8760 assert(dst
.id() != tmp_dst
.id());
8762 Temp tmp
= bld
.tmp(bld
.lm
);
8763 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8764 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8767 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8772 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8773 aco_opcode opcode
= aco_opcode::image_sample
;
8774 if (has_offset
) { /* image_sample_*_o */
8775 if (has_clamped_lod
) {
8777 opcode
= aco_opcode::image_sample_c_cl_o
;
8779 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8781 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8783 opcode
= aco_opcode::image_sample_cl_o
;
8785 opcode
= aco_opcode::image_sample_d_cl_o
;
8787 opcode
= aco_opcode::image_sample_b_cl_o
;
8789 } else if (has_compare
) {
8790 opcode
= aco_opcode::image_sample_c_o
;
8792 opcode
= aco_opcode::image_sample_c_d_o
;
8794 opcode
= aco_opcode::image_sample_c_b_o
;
8796 opcode
= aco_opcode::image_sample_c_lz_o
;
8798 opcode
= aco_opcode::image_sample_c_l_o
;
8800 opcode
= aco_opcode::image_sample_o
;
8802 opcode
= aco_opcode::image_sample_d_o
;
8804 opcode
= aco_opcode::image_sample_b_o
;
8806 opcode
= aco_opcode::image_sample_lz_o
;
8808 opcode
= aco_opcode::image_sample_l_o
;
8810 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8812 opcode
= aco_opcode::image_sample_c_cl
;
8814 opcode
= aco_opcode::image_sample_c_d_cl
;
8816 opcode
= aco_opcode::image_sample_c_b_cl
;
8818 opcode
= aco_opcode::image_sample_cl
;
8820 opcode
= aco_opcode::image_sample_d_cl
;
8822 opcode
= aco_opcode::image_sample_b_cl
;
8824 } else { /* no offset */
8826 opcode
= aco_opcode::image_sample_c
;
8828 opcode
= aco_opcode::image_sample_c_d
;
8830 opcode
= aco_opcode::image_sample_c_b
;
8832 opcode
= aco_opcode::image_sample_c_lz
;
8834 opcode
= aco_opcode::image_sample_c_l
;
8836 opcode
= aco_opcode::image_sample
;
8838 opcode
= aco_opcode::image_sample_d
;
8840 opcode
= aco_opcode::image_sample_b
;
8842 opcode
= aco_opcode::image_sample_lz
;
8844 opcode
= aco_opcode::image_sample_l
;
8848 if (instr
->op
== nir_texop_tg4
) {
8849 if (has_offset
) { /* image_gather4_*_o */
8851 opcode
= aco_opcode::image_gather4_c_lz_o
;
8853 opcode
= aco_opcode::image_gather4_c_l_o
;
8855 opcode
= aco_opcode::image_gather4_c_b_o
;
8857 opcode
= aco_opcode::image_gather4_lz_o
;
8859 opcode
= aco_opcode::image_gather4_l_o
;
8861 opcode
= aco_opcode::image_gather4_b_o
;
8865 opcode
= aco_opcode::image_gather4_c_lz
;
8867 opcode
= aco_opcode::image_gather4_c_l
;
8869 opcode
= aco_opcode::image_gather4_c_b
;
8871 opcode
= aco_opcode::image_gather4_lz
;
8873 opcode
= aco_opcode::image_gather4_l
;
8875 opcode
= aco_opcode::image_gather4_b
;
8878 } else if (instr
->op
== nir_texop_lod
) {
8879 opcode
= aco_opcode::image_get_lod
;
8882 /* we don't need the bias, sample index, compare value or offset to be
8883 * computed in WQM but if the p_create_vector copies the coordinates, then it
8884 * needs to be in WQM */
8885 if (ctx
->stage
== fragment_fs
&&
8886 !has_derivs
&& !has_lod
&& !level_zero
&&
8887 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8888 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8889 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8891 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8892 tex
->operands
[0] = Operand(resource
);
8893 tex
->operands
[1] = Operand(sampler
);
8894 tex
->operands
[2] = Operand(arg
);
8898 tex
->definitions
[0] = Definition(tmp_dst
);
8899 tex
->can_reorder
= true;
8900 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8902 if (tg4_integer_cube_workaround
) {
8903 assert(tmp_dst
.id() != dst
.id());
8904 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8906 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8908 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8909 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8911 if (stype
== GLSL_TYPE_UINT
)
8912 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8914 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8915 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8917 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8918 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8919 val
[0], val
[1], val
[2], val
[3]);
8921 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8922 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8927 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8929 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8930 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8931 return Operand(tmp
.regClass());
8933 return Operand(tmp
);
8936 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8938 aco_ptr
<Pseudo_instruction
> phi
;
8939 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8940 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8942 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8943 logical
|= ctx
->block
->kind
& block_kind_merge
;
8944 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8946 /* we want a sorted list of sources, since the predecessor list is also sorted */
8947 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8948 nir_foreach_phi_src(src
, instr
)
8949 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8951 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8952 unsigned num_operands
= 0;
8953 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8954 unsigned num_defined
= 0;
8955 unsigned cur_pred_idx
= 0;
8956 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8957 if (cur_pred_idx
< preds
.size()) {
8958 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8959 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8960 unsigned skipped
= 0;
8961 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8963 if (cur_pred_idx
+ skipped
< preds
.size()) {
8964 for (unsigned i
= 0; i
< skipped
; i
++)
8965 operands
[num_operands
++] = Operand(dst
.regClass());
8966 cur_pred_idx
+= skipped
;
8971 /* Handle missing predecessors at the end. This shouldn't happen with loop
8972 * headers and we can't ignore these sources for loop header phis. */
8973 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8976 Operand op
= get_phi_operand(ctx
, src
.second
);
8977 operands
[num_operands
++] = op
;
8978 num_defined
+= !op
.isUndefined();
8980 /* handle block_kind_continue_or_break at loop exit blocks */
8981 while (cur_pred_idx
++ < preds
.size())
8982 operands
[num_operands
++] = Operand(dst
.regClass());
8984 /* If the loop ends with a break, still add a linear continue edge in case
8985 * that break is divergent or continue_or_break is used. We'll either remove
8986 * this operand later in visit_loop() if it's not necessary or replace the
8987 * undef with something correct. */
8988 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8989 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8990 nir_block
*last
= nir_loop_last_block(loop
);
8991 if (last
->successors
[0] != instr
->instr
.block
)
8992 operands
[num_operands
++] = Operand(RegClass());
8995 if (num_defined
== 0) {
8996 Builder
bld(ctx
->program
, ctx
->block
);
8997 if (dst
.regClass() == s1
) {
8998 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8999 } else if (dst
.regClass() == v1
) {
9000 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9002 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9003 for (unsigned i
= 0; i
< dst
.size(); i
++)
9004 vec
->operands
[i
] = Operand(0u);
9005 vec
->definitions
[0] = Definition(dst
);
9006 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9011 /* we can use a linear phi in some cases if one src is undef */
9012 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9013 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9015 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9016 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9017 assert(invert
->kind
& block_kind_invert
);
9019 unsigned then_block
= invert
->linear_preds
[0];
9021 Block
* insert_block
= NULL
;
9022 for (unsigned i
= 0; i
< num_operands
; i
++) {
9023 Operand op
= operands
[i
];
9024 if (op
.isUndefined())
9026 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9027 phi
->operands
[0] = op
;
9030 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9031 phi
->operands
[1] = Operand(dst
.regClass());
9032 phi
->definitions
[0] = Definition(dst
);
9033 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9037 /* try to scalarize vector phis */
9038 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9039 // TODO: scalarize linear phis on divergent ifs
9040 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9041 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9042 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9043 Operand src
= operands
[i
];
9044 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9045 can_scalarize
= false;
9047 if (can_scalarize
) {
9048 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9049 assert(dst
.size() % num_components
== 0);
9050 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9052 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9053 for (unsigned k
= 0; k
< num_components
; k
++) {
9054 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9055 for (unsigned i
= 0; i
< num_operands
; i
++) {
9056 Operand src
= operands
[i
];
9057 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9059 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9060 phi
->definitions
[0] = Definition(phi_dst
);
9061 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9062 new_vec
[k
] = phi_dst
;
9063 vec
->operands
[k
] = Operand(phi_dst
);
9065 vec
->definitions
[0] = Definition(dst
);
9066 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9067 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9072 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9073 for (unsigned i
= 0; i
< num_operands
; i
++)
9074 phi
->operands
[i
] = operands
[i
];
9075 phi
->definitions
[0] = Definition(dst
);
9076 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9080 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9082 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9084 assert(dst
.type() == RegType::sgpr
);
9086 if (dst
.size() == 1) {
9087 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9089 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9090 for (unsigned i
= 0; i
< dst
.size(); i
++)
9091 vec
->operands
[i
] = Operand(0u);
9092 vec
->definitions
[0] = Definition(dst
);
9093 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9097 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9099 Builder
bld(ctx
->program
, ctx
->block
);
9100 Block
*logical_target
;
9101 append_logical_end(ctx
->block
);
9102 unsigned idx
= ctx
->block
->index
;
9104 switch (instr
->type
) {
9105 case nir_jump_break
:
9106 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9107 add_logical_edge(idx
, logical_target
);
9108 ctx
->block
->kind
|= block_kind_break
;
9110 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9111 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9112 /* uniform break - directly jump out of the loop */
9113 ctx
->block
->kind
|= block_kind_uniform
;
9114 ctx
->cf_info
.has_branch
= true;
9115 bld
.branch(aco_opcode::p_branch
);
9116 add_linear_edge(idx
, logical_target
);
9119 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9120 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9122 case nir_jump_continue
:
9123 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9124 add_logical_edge(idx
, logical_target
);
9125 ctx
->block
->kind
|= block_kind_continue
;
9127 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9128 /* for potential uniform breaks after this continue,
9129 we must ensure that they are handled correctly */
9130 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9131 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9132 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9134 /* uniform continue - directly jump to the loop header */
9135 ctx
->block
->kind
|= block_kind_uniform
;
9136 ctx
->cf_info
.has_branch
= true;
9137 bld
.branch(aco_opcode::p_branch
);
9138 add_linear_edge(idx
, logical_target
);
9143 fprintf(stderr
, "Unknown NIR jump instr: ");
9144 nir_print_instr(&instr
->instr
, stderr
);
9145 fprintf(stderr
, "\n");
9149 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9150 ctx
->cf_info
.exec_potentially_empty_break
= true;
9151 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9154 /* remove critical edges from linear CFG */
9155 bld
.branch(aco_opcode::p_branch
);
9156 Block
* break_block
= ctx
->program
->create_and_insert_block();
9157 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9158 break_block
->kind
|= block_kind_uniform
;
9159 add_linear_edge(idx
, break_block
);
9160 /* the loop_header pointer might be invalidated by this point */
9161 if (instr
->type
== nir_jump_continue
)
9162 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9163 add_linear_edge(break_block
->index
, logical_target
);
9164 bld
.reset(break_block
);
9165 bld
.branch(aco_opcode::p_branch
);
9167 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9168 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9169 add_linear_edge(idx
, continue_block
);
9170 append_logical_start(continue_block
);
9171 ctx
->block
= continue_block
;
9175 void visit_block(isel_context
*ctx
, nir_block
*block
)
9177 nir_foreach_instr(instr
, block
) {
9178 switch (instr
->type
) {
9179 case nir_instr_type_alu
:
9180 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9182 case nir_instr_type_load_const
:
9183 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9185 case nir_instr_type_intrinsic
:
9186 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9188 case nir_instr_type_tex
:
9189 visit_tex(ctx
, nir_instr_as_tex(instr
));
9191 case nir_instr_type_phi
:
9192 visit_phi(ctx
, nir_instr_as_phi(instr
));
9194 case nir_instr_type_ssa_undef
:
9195 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9197 case nir_instr_type_deref
:
9199 case nir_instr_type_jump
:
9200 visit_jump(ctx
, nir_instr_as_jump(instr
));
9203 fprintf(stderr
, "Unknown NIR instr type: ");
9204 nir_print_instr(instr
, stderr
);
9205 fprintf(stderr
, "\n");
9210 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9211 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9216 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9217 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9219 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9220 RegClass rc
= vals
[0].regClass();
9222 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9224 unsigned next_pred
= 1;
9226 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9227 Block
& block
= ctx
->program
->blocks
[idx
];
9228 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9229 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9233 if (block
.kind
& block_kind_continue
) {
9234 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9239 bool all_same
= true;
9240 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9241 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9245 val
= vals
[block
.linear_preds
[0] - first
];
9247 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9248 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9249 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9250 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9251 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9252 phi
->definitions
[0] = Definition(val
.getTemp());
9253 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9255 vals
[idx
- first
] = val
;
9258 return vals
[last
- first
];
9261 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9263 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9264 append_logical_end(ctx
->block
);
9265 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9266 Builder
bld(ctx
->program
, ctx
->block
);
9267 bld
.branch(aco_opcode::p_branch
);
9268 unsigned loop_preheader_idx
= ctx
->block
->index
;
9270 Block loop_exit
= Block();
9271 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9272 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9274 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9275 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9276 loop_header
->kind
|= block_kind_loop_header
;
9277 add_edge(loop_preheader_idx
, loop_header
);
9278 ctx
->block
= loop_header
;
9280 /* emit loop body */
9281 unsigned loop_header_idx
= loop_header
->index
;
9282 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9283 append_logical_start(ctx
->block
);
9284 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9286 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9287 if (!ctx
->cf_info
.has_branch
) {
9288 append_logical_end(ctx
->block
);
9289 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9290 /* Discards can result in code running with an empty exec mask.
9291 * This would result in divergent breaks not ever being taken. As a
9292 * workaround, break the loop when the loop mask is empty instead of
9293 * always continuing. */
9294 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9295 unsigned block_idx
= ctx
->block
->index
;
9297 /* create helper blocks to avoid critical edges */
9298 Block
*break_block
= ctx
->program
->create_and_insert_block();
9299 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9300 break_block
->kind
= block_kind_uniform
;
9301 bld
.reset(break_block
);
9302 bld
.branch(aco_opcode::p_branch
);
9303 add_linear_edge(block_idx
, break_block
);
9304 add_linear_edge(break_block
->index
, &loop_exit
);
9306 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9307 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9308 continue_block
->kind
= block_kind_uniform
;
9309 bld
.reset(continue_block
);
9310 bld
.branch(aco_opcode::p_branch
);
9311 add_linear_edge(block_idx
, continue_block
);
9312 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9314 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9315 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9316 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9318 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9319 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9320 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9322 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9325 bld
.reset(ctx
->block
);
9326 bld
.branch(aco_opcode::p_branch
);
9329 /* Fixup phis in loop header from unreachable blocks.
9330 * has_branch/has_divergent_branch also indicates if the loop ends with a
9331 * break/continue instruction, but we don't emit those if unreachable=true */
9333 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9334 bool linear
= ctx
->cf_info
.has_branch
;
9335 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9336 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9337 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9338 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9339 /* the last operand should be the one that needs to be removed */
9340 instr
->operands
.pop_back();
9341 } else if (!is_phi(instr
)) {
9347 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9348 * and the previous one shouldn't both happen at once because a break in the
9349 * merge block would get CSE'd */
9350 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9351 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9352 Operand vals
[num_vals
];
9353 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9354 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9355 if (ctx
->cf_info
.has_branch
)
9356 instr
->operands
.pop_back();
9358 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9359 } else if (!is_phi(instr
)) {
9365 ctx
->cf_info
.has_branch
= false;
9367 // TODO: if the loop has not a single exit, we must add one °°
9368 /* emit loop successor block */
9369 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9370 append_logical_start(ctx
->block
);
9373 // TODO: check if it is beneficial to not branch on continues
9374 /* trim linear phis in loop header */
9375 for (auto&& instr
: loop_entry
->instructions
) {
9376 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9377 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9378 new_phi
->definitions
[0] = instr
->definitions
[0];
9379 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9380 new_phi
->operands
[i
] = instr
->operands
[i
];
9381 /* check that the remaining operands are all the same */
9382 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9383 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9384 instr
.swap(new_phi
);
9385 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9394 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9398 append_logical_end(ctx
->block
);
9399 ctx
->block
->kind
|= block_kind_branch
;
9401 /* branch to linear then block */
9402 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9403 aco_ptr
<Pseudo_branch_instruction
> branch
;
9404 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9405 branch
->operands
[0] = Operand(cond
);
9406 ctx
->block
->instructions
.push_back(std::move(branch
));
9408 ic
->BB_if_idx
= ctx
->block
->index
;
9409 ic
->BB_invert
= Block();
9410 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9411 /* Invert blocks are intentionally not marked as top level because they
9412 * are not part of the logical cfg. */
9413 ic
->BB_invert
.kind
|= block_kind_invert
;
9414 ic
->BB_endif
= Block();
9415 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9416 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9418 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9419 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9420 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9421 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9422 ctx
->cf_info
.parent_if
.is_divergent
= true;
9424 /* divergent branches use cbranch_execz */
9425 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9426 ctx
->cf_info
.exec_potentially_empty_break
= false;
9427 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9429 /** emit logical then block */
9430 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9431 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9432 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9433 ctx
->block
= BB_then_logical
;
9434 append_logical_start(BB_then_logical
);
9437 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9439 Block
*BB_then_logical
= ctx
->block
;
9440 append_logical_end(BB_then_logical
);
9441 /* branch from logical then block to invert block */
9442 aco_ptr
<Pseudo_branch_instruction
> branch
;
9443 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9444 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9445 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9446 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9447 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9448 BB_then_logical
->kind
|= block_kind_uniform
;
9449 assert(!ctx
->cf_info
.has_branch
);
9450 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9451 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9453 /** emit linear then block */
9454 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9455 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9456 BB_then_linear
->kind
|= block_kind_uniform
;
9457 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9458 /* branch from linear then block to invert block */
9459 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9460 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9461 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9463 /** emit invert merge block */
9464 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9465 ic
->invert_idx
= ctx
->block
->index
;
9467 /* branch to linear else block (skip else) */
9468 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9469 branch
->operands
[0] = Operand(ic
->cond
);
9470 ctx
->block
->instructions
.push_back(std::move(branch
));
9472 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9473 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9474 ic
->exec_potentially_empty_break_depth_old
=
9475 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9476 /* divergent branches use cbranch_execz */
9477 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9478 ctx
->cf_info
.exec_potentially_empty_break
= false;
9479 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9481 /** emit logical else block */
9482 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9483 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9484 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9485 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9486 ctx
->block
= BB_else_logical
;
9487 append_logical_start(BB_else_logical
);
9490 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9492 Block
*BB_else_logical
= ctx
->block
;
9493 append_logical_end(BB_else_logical
);
9495 /* branch from logical else block to endif block */
9496 aco_ptr
<Pseudo_branch_instruction
> branch
;
9497 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9498 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9499 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9500 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9501 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9502 BB_else_logical
->kind
|= block_kind_uniform
;
9504 assert(!ctx
->cf_info
.has_branch
);
9505 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9508 /** emit linear else block */
9509 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9510 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9511 BB_else_linear
->kind
|= block_kind_uniform
;
9512 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9514 /* branch from linear else block to endif block */
9515 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9516 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9517 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9520 /** emit endif merge block */
9521 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9522 append_logical_start(ctx
->block
);
9525 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9526 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9527 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9528 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9529 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9530 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9531 !ctx
->cf_info
.parent_if
.is_divergent
) {
9532 ctx
->cf_info
.exec_potentially_empty_break
= false;
9533 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9535 /* uniform control flow never has an empty exec-mask */
9536 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9537 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9538 ctx
->cf_info
.exec_potentially_empty_break
= false;
9539 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9543 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9545 assert(cond
.regClass() == s1
);
9547 append_logical_end(ctx
->block
);
9548 ctx
->block
->kind
|= block_kind_uniform
;
9550 aco_ptr
<Pseudo_branch_instruction
> branch
;
9551 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9552 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9553 branch
->operands
[0] = Operand(cond
);
9554 branch
->operands
[0].setFixed(scc
);
9555 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9557 ic
->BB_if_idx
= ctx
->block
->index
;
9558 ic
->BB_endif
= Block();
9559 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9560 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9562 ctx
->cf_info
.has_branch
= false;
9563 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9565 /** emit then block */
9566 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9567 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9568 add_edge(ic
->BB_if_idx
, BB_then
);
9569 append_logical_start(BB_then
);
9570 ctx
->block
= BB_then
;
9573 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9575 Block
*BB_then
= ctx
->block
;
9577 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9578 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9580 if (!ic
->uniform_has_then_branch
) {
9581 append_logical_end(BB_then
);
9582 /* branch from then block to endif block */
9583 aco_ptr
<Pseudo_branch_instruction
> branch
;
9584 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9585 BB_then
->instructions
.emplace_back(std::move(branch
));
9586 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9587 if (!ic
->then_branch_divergent
)
9588 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9589 BB_then
->kind
|= block_kind_uniform
;
9592 ctx
->cf_info
.has_branch
= false;
9593 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9595 /** emit else block */
9596 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9597 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9598 add_edge(ic
->BB_if_idx
, BB_else
);
9599 append_logical_start(BB_else
);
9600 ctx
->block
= BB_else
;
9603 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9605 Block
*BB_else
= ctx
->block
;
9607 if (!ctx
->cf_info
.has_branch
) {
9608 append_logical_end(BB_else
);
9609 /* branch from then block to endif block */
9610 aco_ptr
<Pseudo_branch_instruction
> branch
;
9611 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9612 BB_else
->instructions
.emplace_back(std::move(branch
));
9613 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9614 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9615 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9616 BB_else
->kind
|= block_kind_uniform
;
9619 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9620 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9622 /** emit endif merge block */
9623 if (!ctx
->cf_info
.has_branch
) {
9624 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9625 append_logical_start(ctx
->block
);
9629 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9631 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9632 Builder
bld(ctx
->program
, ctx
->block
);
9633 aco_ptr
<Pseudo_branch_instruction
> branch
;
9636 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9638 * Uniform conditionals are represented in the following way*) :
9640 * The linear and logical CFG:
9643 * BB_THEN (logical) BB_ELSE (logical)
9647 * *) Exceptions may be due to break and continue statements within loops
9648 * If a break/continue happens within uniform control flow, it branches
9649 * to the loop exit/entry block. Otherwise, it branches to the next
9653 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9654 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9655 cond
= bool_to_scalar_condition(ctx
, cond
);
9657 begin_uniform_if_then(ctx
, &ic
, cond
);
9658 visit_cf_list(ctx
, &if_stmt
->then_list
);
9660 begin_uniform_if_else(ctx
, &ic
);
9661 visit_cf_list(ctx
, &if_stmt
->else_list
);
9663 end_uniform_if(ctx
, &ic
);
9664 } else { /* non-uniform condition */
9666 * To maintain a logical and linear CFG without critical edges,
9667 * non-uniform conditionals are represented in the following way*) :
9672 * BB_THEN (logical) BB_THEN (linear)
9674 * BB_INVERT (linear)
9676 * BB_ELSE (logical) BB_ELSE (linear)
9683 * BB_THEN (logical) BB_ELSE (logical)
9687 * *) Exceptions may be due to break and continue statements within loops
9690 begin_divergent_if_then(ctx
, &ic
, cond
);
9691 visit_cf_list(ctx
, &if_stmt
->then_list
);
9693 begin_divergent_if_else(ctx
, &ic
);
9694 visit_cf_list(ctx
, &if_stmt
->else_list
);
9696 end_divergent_if(ctx
, &ic
);
9699 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9702 static bool visit_cf_list(isel_context
*ctx
,
9703 struct exec_list
*list
)
9705 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9706 switch (node
->type
) {
9707 case nir_cf_node_block
:
9708 visit_block(ctx
, nir_cf_node_as_block(node
));
9710 case nir_cf_node_if
:
9711 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9714 case nir_cf_node_loop
:
9715 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9718 unreachable("unimplemented cf list type");
9724 static void create_null_export(isel_context
*ctx
)
9726 /* Some shader stages always need to have exports.
9727 * So when there is none, we need to add a null export.
9730 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9731 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9732 Builder
bld(ctx
->program
, ctx
->block
);
9733 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9734 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9737 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9739 assert(ctx
->stage
== vertex_vs
||
9740 ctx
->stage
== tess_eval_vs
||
9741 ctx
->stage
== gs_copy_vs
||
9742 ctx
->stage
== ngg_vertex_gs
||
9743 ctx
->stage
== ngg_tess_eval_gs
);
9745 int offset
= (ctx
->stage
& sw_tes
)
9746 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9747 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9748 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9749 if (!is_pos
&& !mask
)
9751 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9753 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9754 exp
->enabled_mask
= mask
;
9755 for (unsigned i
= 0; i
< 4; ++i
) {
9756 if (mask
& (1 << i
))
9757 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9759 exp
->operands
[i
] = Operand(v1
);
9761 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9762 * Setting valid_mask=1 prevents it and has no other effect.
9764 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9766 exp
->compressed
= false;
9768 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9770 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9771 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9776 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9778 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9779 exp
->enabled_mask
= 0;
9780 for (unsigned i
= 0; i
< 4; ++i
)
9781 exp
->operands
[i
] = Operand(v1
);
9782 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9783 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9784 exp
->enabled_mask
|= 0x1;
9786 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9787 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9788 exp
->enabled_mask
|= 0x4;
9790 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9791 if (ctx
->options
->chip_class
< GFX9
) {
9792 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9793 exp
->enabled_mask
|= 0x8;
9795 Builder
bld(ctx
->program
, ctx
->block
);
9797 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9798 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9799 if (exp
->operands
[2].isTemp())
9800 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9802 exp
->operands
[2] = Operand(out
);
9803 exp
->enabled_mask
|= 0x4;
9806 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9808 exp
->compressed
= false;
9809 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9810 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9813 static void create_export_phis(isel_context
*ctx
)
9815 /* Used when exports are needed, but the output temps are defined in a preceding block.
9816 * This function will set up phis in order to access the outputs in the next block.
9819 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9820 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9821 ctx
->block
->instructions
.pop_back();
9823 Builder
bld(ctx
->program
, ctx
->block
);
9825 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9826 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9827 for (unsigned i
= 0; i
< 4; ++i
) {
9828 if (!(mask
& (1 << i
)))
9831 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9832 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9833 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9837 bld
.insert(std::move(logical_start
));
9840 static void create_vs_exports(isel_context
*ctx
)
9842 assert(ctx
->stage
== vertex_vs
||
9843 ctx
->stage
== tess_eval_vs
||
9844 ctx
->stage
== gs_copy_vs
||
9845 ctx
->stage
== ngg_vertex_gs
||
9846 ctx
->stage
== ngg_tess_eval_gs
);
9848 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9849 ? &ctx
->program
->info
->tes
.outinfo
9850 : &ctx
->program
->info
->vs
.outinfo
;
9852 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9853 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9854 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9857 if (ctx
->options
->key
.has_multiview_view_index
) {
9858 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9859 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9862 /* the order these position exports are created is important */
9864 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9865 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9866 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9867 exported_pos
= true;
9869 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9870 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9871 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9872 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9874 if (ctx
->export_clip_dists
) {
9875 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9876 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9877 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9878 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9881 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9882 if (i
< VARYING_SLOT_VAR0
&&
9883 i
!= VARYING_SLOT_LAYER
&&
9884 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9885 i
!= VARYING_SLOT_VIEWPORT
)
9888 export_vs_varying(ctx
, i
, false, NULL
);
9892 create_null_export(ctx
);
9895 static bool export_fs_mrt_z(isel_context
*ctx
)
9897 Builder
bld(ctx
->program
, ctx
->block
);
9898 unsigned enabled_channels
= 0;
9902 for (unsigned i
= 0; i
< 4; ++i
) {
9903 values
[i
] = Operand(v1
);
9906 /* Both stencil and sample mask only need 16-bits. */
9907 if (!ctx
->program
->info
->ps
.writes_z
&&
9908 (ctx
->program
->info
->ps
.writes_stencil
||
9909 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9910 compr
= true; /* COMPR flag */
9912 if (ctx
->program
->info
->ps
.writes_stencil
) {
9913 /* Stencil should be in X[23:16]. */
9914 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9915 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9916 enabled_channels
|= 0x3;
9919 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9920 /* SampleMask should be in Y[15:0]. */
9921 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9922 enabled_channels
|= 0xc;
9925 if (ctx
->program
->info
->ps
.writes_z
) {
9926 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9927 enabled_channels
|= 0x1;
9930 if (ctx
->program
->info
->ps
.writes_stencil
) {
9931 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9932 enabled_channels
|= 0x2;
9935 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9936 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9937 enabled_channels
|= 0x4;
9941 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9942 * writemask component.
9944 if (ctx
->options
->chip_class
== GFX6
&&
9945 ctx
->options
->family
!= CHIP_OLAND
&&
9946 ctx
->options
->family
!= CHIP_HAINAN
) {
9947 enabled_channels
|= 0x1;
9950 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9951 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9956 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9958 Builder
bld(ctx
->program
, ctx
->block
);
9959 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9962 for (unsigned i
= 0; i
< 4; ++i
) {
9963 if (write_mask
& (1 << i
)) {
9964 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9966 values
[i
] = Operand(v1
);
9970 unsigned target
, col_format
;
9971 unsigned enabled_channels
= 0;
9972 aco_opcode compr_op
= (aco_opcode
)0;
9974 slot
-= FRAG_RESULT_DATA0
;
9975 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9976 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9978 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9979 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9980 bool is_16bit
= values
[0].regClass() == v2b
;
9984 case V_028714_SPI_SHADER_ZERO
:
9985 enabled_channels
= 0; /* writemask */
9986 target
= V_008DFC_SQ_EXP_NULL
;
9989 case V_028714_SPI_SHADER_32_R
:
9990 enabled_channels
= 1;
9993 case V_028714_SPI_SHADER_32_GR
:
9994 enabled_channels
= 0x3;
9997 case V_028714_SPI_SHADER_32_AR
:
9998 if (ctx
->options
->chip_class
>= GFX10
) {
9999 /* Special case: on GFX10, the outputs are different for 32_AR */
10000 enabled_channels
= 0x3;
10001 values
[1] = values
[3];
10002 values
[3] = Operand(v1
);
10004 enabled_channels
= 0x9;
10008 case V_028714_SPI_SHADER_FP16_ABGR
:
10009 enabled_channels
= 0x5;
10010 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10012 if (ctx
->options
->chip_class
>= GFX9
) {
10013 /* Pack the FP16 values together instead of converting them to
10014 * FP32 and back to FP16.
10015 * TODO: use p_create_vector and let the compiler optimizes.
10017 compr_op
= aco_opcode::v_pack_b32_f16
;
10019 for (unsigned i
= 0; i
< 4; i
++) {
10020 if ((write_mask
>> i
) & 1)
10021 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10027 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10028 enabled_channels
= 0x5;
10029 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10030 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10032 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10036 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10037 enabled_channels
= 0x5;
10038 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10039 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10041 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10045 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10046 enabled_channels
= 0x5;
10047 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10048 if (is_int8
|| is_int10
) {
10050 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10051 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10053 for (unsigned i
= 0; i
< 4; i
++) {
10054 if ((write_mask
>> i
) & 1) {
10055 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10056 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10060 } else if (is_16bit
) {
10061 for (unsigned i
= 0; i
< 4; i
++) {
10062 if ((write_mask
>> i
) & 1) {
10063 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10064 values
[i
] = Operand(tmp
);
10071 case V_028714_SPI_SHADER_SINT16_ABGR
:
10072 enabled_channels
= 0x5;
10073 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10074 if (is_int8
|| is_int10
) {
10076 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10077 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10078 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10079 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10081 for (unsigned i
= 0; i
< 4; i
++) {
10082 if ((write_mask
>> i
) & 1) {
10083 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10084 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10086 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10087 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10091 } else if (is_16bit
) {
10092 for (unsigned i
= 0; i
< 4; i
++) {
10093 if ((write_mask
>> i
) & 1) {
10094 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10095 values
[i
] = Operand(tmp
);
10101 case V_028714_SPI_SHADER_32_ABGR
:
10102 enabled_channels
= 0xF;
10109 if (target
== V_008DFC_SQ_EXP_NULL
)
10112 if ((bool) compr_op
) {
10113 for (int i
= 0; i
< 2; i
++) {
10114 /* check if at least one of the values to be compressed is enabled */
10115 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10117 enabled_channels
|= enabled
<< (i
*2);
10118 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10119 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10120 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10122 values
[i
] = Operand(v1
);
10125 values
[2] = Operand(v1
);
10126 values
[3] = Operand(v1
);
10128 for (int i
= 0; i
< 4; i
++)
10129 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10132 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10133 enabled_channels
, target
, (bool) compr_op
);
10137 static void create_fs_exports(isel_context
*ctx
)
10139 bool exported
= false;
10141 /* Export depth, stencil and sample mask. */
10142 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10143 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10144 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10145 exported
|= export_fs_mrt_z(ctx
);
10147 /* Export all color render targets. */
10148 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10149 if (ctx
->outputs
.mask
[i
])
10150 exported
|= export_fs_mrt_color(ctx
, i
);
10153 create_null_export(ctx
);
10156 static void write_tcs_tess_factors(isel_context
*ctx
)
10158 unsigned outer_comps
;
10159 unsigned inner_comps
;
10161 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10178 Builder
bld(ctx
->program
, ctx
->block
);
10180 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10181 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10182 bld
.sopp(aco_opcode::s_barrier
);
10184 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10185 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10187 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10188 if_context ic_invocation_id_is_zero
;
10189 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10190 bld
.reset(ctx
->block
);
10192 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10194 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10195 unsigned stride
= inner_comps
+ outer_comps
;
10196 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10200 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10202 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10204 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10205 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10206 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10208 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10209 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10211 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10212 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10213 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10214 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10217 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10218 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10219 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10220 unsigned tf_const_offset
= 0;
10222 if (ctx
->program
->chip_class
<= GFX8
) {
10223 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10224 if_context ic_rel_patch_id_is_zero
;
10225 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10226 bld
.reset(ctx
->block
);
10228 /* Store the dynamic HS control word. */
10229 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10230 bld
.mubuf(aco_opcode::buffer_store_dword
,
10231 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10232 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10233 /* disable_wqm */ false, /* glc */ true);
10234 tf_const_offset
+= 4;
10236 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10237 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10238 bld
.reset(ctx
->block
);
10241 assert(stride
== 2 || stride
== 4 || stride
== 6);
10242 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10243 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10245 /* Store to offchip for TES to read - only if TES reads them */
10246 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10247 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10248 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10250 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10251 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10253 if (likely(inner_comps
)) {
10254 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10255 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10259 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10260 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10263 static void emit_stream_output(isel_context
*ctx
,
10264 Temp
const *so_buffers
,
10265 Temp
const *so_write_offset
,
10266 const struct radv_stream_output
*output
)
10268 unsigned num_comps
= util_bitcount(output
->component_mask
);
10269 unsigned writemask
= (1 << num_comps
) - 1;
10270 unsigned loc
= output
->location
;
10271 unsigned buf
= output
->buffer
;
10273 assert(num_comps
&& num_comps
<= 4);
10274 if (!num_comps
|| num_comps
> 4)
10277 unsigned start
= ffs(output
->component_mask
) - 1;
10280 bool all_undef
= true;
10281 assert(ctx
->stage
& hw_vs
);
10282 for (unsigned i
= 0; i
< num_comps
; i
++) {
10283 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10284 all_undef
= all_undef
&& !out
[i
].id();
10289 while (writemask
) {
10291 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10292 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10293 /* GFX6 doesn't support storing vec3, split it. */
10294 writemask
|= 1u << (start
+ 2);
10298 unsigned offset
= output
->offset
+ start
* 4;
10300 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10301 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10302 for (int i
= 0; i
< count
; ++i
)
10303 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10304 vec
->definitions
[0] = Definition(write_data
);
10305 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10310 opcode
= aco_opcode::buffer_store_dword
;
10313 opcode
= aco_opcode::buffer_store_dwordx2
;
10316 opcode
= aco_opcode::buffer_store_dwordx3
;
10319 opcode
= aco_opcode::buffer_store_dwordx4
;
10322 unreachable("Unsupported dword count.");
10325 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10326 store
->operands
[0] = Operand(so_buffers
[buf
]);
10327 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10328 store
->operands
[2] = Operand((uint32_t) 0);
10329 store
->operands
[3] = Operand(write_data
);
10330 if (offset
> 4095) {
10331 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10332 Builder
bld(ctx
->program
, ctx
->block
);
10333 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10335 store
->offset
= offset
;
10337 store
->offen
= true;
10339 store
->dlc
= false;
10341 store
->can_reorder
= true;
10342 ctx
->block
->instructions
.emplace_back(std::move(store
));
10346 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10348 Builder
bld(ctx
->program
, ctx
->block
);
10350 Temp so_buffers
[4];
10351 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10352 for (unsigned i
= 0; i
< 4; i
++) {
10353 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10357 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10358 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10361 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10362 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10364 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10366 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10369 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10371 bld
.reset(ctx
->block
);
10373 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10375 Temp so_write_offset
[4];
10377 for (unsigned i
= 0; i
< 4; i
++) {
10378 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10383 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10384 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10385 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10386 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10388 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10390 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10391 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10392 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10393 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10397 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10398 struct radv_stream_output
*output
=
10399 &ctx
->program
->info
->so
.outputs
[i
];
10400 if (stream
!= output
->stream
)
10403 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10406 begin_divergent_if_else(ctx
, &ic
);
10407 end_divergent_if(ctx
, &ic
);
10410 } /* end namespace */
10412 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10414 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10415 Builder
bld(ctx
->program
, ctx
->block
);
10416 constexpr unsigned hs_idx
= 1u;
10417 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10418 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10419 Operand((8u << 16) | (hs_idx
* 8u)));
10420 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10422 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10424 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10425 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10426 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10427 ls_has_nonzero_hs_threads
);
10428 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10429 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10430 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10431 ls_has_nonzero_hs_threads
);
10432 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10433 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10434 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10435 ls_has_nonzero_hs_threads
);
10437 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10438 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10439 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10442 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10444 /* Split all arguments except for the first (ring_offsets) and the last
10445 * (exec) so that the dead channels don't stay live throughout the program.
10447 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10448 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10449 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10450 startpgm
->definitions
[i
].regClass().size());
10455 void handle_bc_optimize(isel_context
*ctx
)
10457 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10458 Builder
bld(ctx
->program
, ctx
->block
);
10459 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10460 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10461 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10462 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10463 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10464 if (uses_center
&& uses_centroid
) {
10465 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10466 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10468 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10470 for (unsigned i
= 0; i
< 2; i
++) {
10471 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10472 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10473 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10474 persp_centroid
, persp_center
, sel
);
10476 ctx
->persp_centroid
= bld
.tmp(v2
);
10477 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10478 Operand(new_coord
[0]), Operand(new_coord
[1]));
10479 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10482 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10484 for (unsigned i
= 0; i
< 2; i
++) {
10485 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10486 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10487 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10488 linear_centroid
, linear_center
, sel
);
10490 ctx
->linear_centroid
= bld
.tmp(v2
);
10491 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10492 Operand(new_coord
[0]), Operand(new_coord
[1]));
10493 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10498 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10500 Program
*program
= ctx
->program
;
10502 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10504 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10505 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10506 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10507 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10508 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10510 program
->next_fp_mode
.must_flush_denorms32
=
10511 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10512 program
->next_fp_mode
.must_flush_denorms16_64
=
10513 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10514 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10516 program
->next_fp_mode
.care_about_round32
=
10517 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10519 program
->next_fp_mode
.care_about_round16_64
=
10520 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10521 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10523 /* default to preserving fp16 and fp64 denorms, since it's free */
10524 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10525 program
->next_fp_mode
.denorm16_64
= 0;
10527 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10529 /* preserving fp32 denorms is expensive, so only do it if asked */
10530 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10531 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10533 program
->next_fp_mode
.denorm32
= 0;
10535 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10536 program
->next_fp_mode
.round32
= fp_round_tz
;
10538 program
->next_fp_mode
.round32
= fp_round_ne
;
10540 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10541 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10543 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10545 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10548 void cleanup_cfg(Program
*program
)
10550 /* create linear_succs/logical_succs */
10551 for (Block
& BB
: program
->blocks
) {
10552 for (unsigned idx
: BB
.linear_preds
)
10553 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10554 for (unsigned idx
: BB
.logical_preds
)
10555 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10559 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10561 Builder
bld(ctx
->program
, ctx
->block
);
10563 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10564 Temp count
= i
== 0
10565 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10566 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10567 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10569 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10572 if (ctx
->program
->wave_size
== 64) {
10573 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10574 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10575 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10577 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10578 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10584 bool ngg_early_prim_export(isel_context
*ctx
)
10586 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10590 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10592 Builder
bld(ctx
->program
, ctx
->block
);
10594 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10595 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10597 /* Get the id of the current wave within the threadgroup (workgroup) */
10598 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10599 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10601 /* Execute the following code only on the first wave (wave id 0),
10602 * use the SCC def to tell if the wave id is zero or not.
10604 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10606 begin_uniform_if_then(ctx
, &ic
, cond
);
10607 begin_uniform_if_else(ctx
, &ic
);
10608 bld
.reset(ctx
->block
);
10610 /* Number of vertices output by VS/TES */
10611 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10612 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10613 /* Number of primitives output by VS/TES */
10614 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10615 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10617 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10618 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10619 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10621 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10622 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10624 end_uniform_if(ctx
, &ic
);
10626 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10627 bld
.reset(ctx
->block
);
10628 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10631 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10633 Builder
bld(ctx
->program
, ctx
->block
);
10635 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10636 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10639 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10642 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10643 assert(vtxindex
[i
].id());
10646 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10650 /* The initial edge flag is always false in tess eval shaders. */
10651 if (ctx
->stage
== ngg_vertex_gs
) {
10652 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10653 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10657 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10662 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10664 Builder
bld(ctx
->program
, ctx
->block
);
10665 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10667 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10668 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10669 false /* compressed */, true/* done */, false /* valid mask */);
10672 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10674 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10675 * These must always come before VS exports.
10677 * It is recommended to do these as early as possible. They can be at the beginning when
10678 * there is no SW GS and the shader doesn't write edge flags.
10682 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10683 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10685 Builder
bld(ctx
->program
, ctx
->block
);
10686 constexpr unsigned max_vertices_per_primitive
= 3;
10687 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10689 if (ctx
->stage
== ngg_vertex_gs
) {
10690 /* TODO: optimize for points & lines */
10691 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10692 if (ctx
->shader
->info
.tess
.point_mode
)
10693 num_vertices_per_primitive
= 1;
10694 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10695 num_vertices_per_primitive
= 2;
10697 unreachable("Unsupported NGG shader stage");
10700 Temp vtxindex
[max_vertices_per_primitive
];
10701 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10702 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10703 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10704 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10705 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10706 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10707 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10708 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10710 /* Export primitive data to the index buffer. */
10711 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10713 /* Export primitive ID. */
10714 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10715 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10716 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10717 Temp provoking_vtx_index
= vtxindex
[0];
10718 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10720 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10723 begin_divergent_if_else(ctx
, &ic
);
10724 end_divergent_if(ctx
, &ic
);
10727 void ngg_emit_nogs_output(isel_context
*ctx
)
10729 /* Emits NGG GS output, for stages that don't have SW GS. */
10732 Builder
bld(ctx
->program
, ctx
->block
);
10733 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10735 /* NGG streamout is currently disabled by default. */
10736 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10738 if (late_prim_export
) {
10739 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10740 create_export_phis(ctx
);
10741 /* Do what we need to do in the GS threads. */
10742 ngg_emit_nogs_gsthreads(ctx
);
10744 /* What comes next should be executed on ES threads. */
10745 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10746 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10747 bld
.reset(ctx
->block
);
10750 /* Export VS outputs */
10751 ctx
->block
->kind
|= block_kind_export_end
;
10752 create_vs_exports(ctx
);
10754 /* Export primitive ID */
10755 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10758 if (ctx
->stage
== ngg_vertex_gs
) {
10759 /* Wait for GS threads to store primitive ID in LDS. */
10760 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10761 bld
.sopp(aco_opcode::s_barrier
);
10763 /* Calculate LDS address where the GS threads stored the primitive ID. */
10764 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10765 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10766 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10767 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10768 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10769 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10771 /* Load primitive ID from LDS. */
10772 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10773 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10774 /* TES: Just use the patch ID as the primitive ID. */
10775 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10777 unreachable("unsupported NGG shader stage.");
10780 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10781 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10783 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10786 if (late_prim_export
) {
10787 begin_divergent_if_else(ctx
, &ic
);
10788 end_divergent_if(ctx
, &ic
);
10789 bld
.reset(ctx
->block
);
10793 void select_program(Program
*program
,
10794 unsigned shader_count
,
10795 struct nir_shader
*const *shaders
,
10796 ac_shader_config
* config
,
10797 struct radv_shader_args
*args
)
10799 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10800 if_context ic_merged_wave_info
;
10801 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10803 for (unsigned i
= 0; i
< shader_count
; i
++) {
10804 nir_shader
*nir
= shaders
[i
];
10805 init_context(&ctx
, nir
);
10807 setup_fp_mode(&ctx
, nir
);
10810 /* needs to be after init_context() for FS */
10811 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10812 append_logical_start(ctx
.block
);
10814 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10815 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10817 split_arguments(&ctx
, startpgm
);
10821 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10823 if (ngg_early_prim_export(&ctx
))
10824 ngg_emit_nogs_gsthreads(&ctx
);
10827 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10828 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10829 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10830 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10831 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10832 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10833 ctx
.stage
== tess_eval_geometry_gs
));
10835 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10836 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10837 if (check_merged_wave_info
) {
10838 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10839 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10843 Builder
bld(ctx
.program
, ctx
.block
);
10845 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10846 bld
.sopp(aco_opcode::s_barrier
);
10848 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10849 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10851 } else if (ctx
.stage
== geometry_gs
)
10852 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10854 if (ctx
.stage
== fragment_fs
)
10855 handle_bc_optimize(&ctx
);
10857 visit_cf_list(&ctx
, &func
->body
);
10859 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10860 emit_streamout(&ctx
, 0);
10862 if (ctx
.stage
& hw_vs
) {
10863 create_vs_exports(&ctx
);
10864 ctx
.block
->kind
|= block_kind_export_end
;
10865 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10866 ngg_emit_nogs_output(&ctx
);
10867 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10868 Builder
bld(ctx
.program
, ctx
.block
);
10869 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10870 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10871 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10872 write_tcs_tess_factors(&ctx
);
10875 if (ctx
.stage
== fragment_fs
) {
10876 create_fs_exports(&ctx
);
10877 ctx
.block
->kind
|= block_kind_export_end
;
10880 if (endif_merged_wave_info
) {
10881 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10882 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10885 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10886 ngg_emit_nogs_output(&ctx
);
10888 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10889 /* Outputs of the previous stage are inputs to the next stage */
10890 ctx
.inputs
= ctx
.outputs
;
10891 ctx
.outputs
= shader_io_state();
10895 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10897 append_logical_end(ctx
.block
);
10898 ctx
.block
->kind
|= block_kind_uniform
;
10899 Builder
bld(ctx
.program
, ctx
.block
);
10900 if (ctx
.program
->wb_smem_l1_on_end
)
10901 bld
.smem(aco_opcode::s_dcache_wb
, false);
10902 bld
.sopp(aco_opcode::s_endpgm
);
10904 cleanup_cfg(program
);
10907 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10908 ac_shader_config
* config
,
10909 struct radv_shader_args
*args
)
10911 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10913 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10914 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10915 program
->next_fp_mode
.must_flush_denorms32
= false;
10916 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10917 program
->next_fp_mode
.care_about_round32
= false;
10918 program
->next_fp_mode
.care_about_round16_64
= false;
10919 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10920 program
->next_fp_mode
.denorm32
= 0;
10921 program
->next_fp_mode
.round32
= fp_round_ne
;
10922 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10923 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10925 add_startpgm(&ctx
);
10926 append_logical_start(ctx
.block
);
10928 Builder
bld(ctx
.program
, ctx
.block
);
10930 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10932 Operand
stream_id(0u);
10933 if (args
->shader_info
->so
.num_outputs
)
10934 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10935 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10937 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10939 std::stack
<Block
> endif_blocks
;
10941 for (unsigned stream
= 0; stream
< 4; stream
++) {
10942 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10945 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10946 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10949 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10951 unsigned BB_if_idx
= ctx
.block
->index
;
10952 Block BB_endif
= Block();
10953 if (!stream_id
.isConstant()) {
10955 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10956 append_logical_end(ctx
.block
);
10957 ctx
.block
->kind
|= block_kind_uniform
;
10958 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10960 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10962 ctx
.block
= ctx
.program
->create_and_insert_block();
10963 add_edge(BB_if_idx
, ctx
.block
);
10964 bld
.reset(ctx
.block
);
10965 append_logical_start(ctx
.block
);
10968 unsigned offset
= 0;
10969 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10970 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10973 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10974 unsigned length
= util_last_bit(output_usage_mask
);
10975 for (unsigned j
= 0; j
< length
; ++j
) {
10976 if (!(output_usage_mask
& (1 << j
)))
10979 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10980 Temp voffset
= vtx_offset
;
10981 if (const_offset
>= 4096u) {
10982 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10983 const_offset
%= 4096u;
10986 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10987 mubuf
->definitions
[0] = bld
.def(v1
);
10988 mubuf
->operands
[0] = Operand(gsvs_ring
);
10989 mubuf
->operands
[1] = Operand(voffset
);
10990 mubuf
->operands
[2] = Operand(0u);
10991 mubuf
->offen
= true;
10992 mubuf
->offset
= const_offset
;
10995 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10996 mubuf
->barrier
= barrier_none
;
10997 mubuf
->can_reorder
= true;
10999 ctx
.outputs
.mask
[i
] |= 1 << j
;
11000 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11002 bld
.insert(std::move(mubuf
));
11008 if (args
->shader_info
->so
.num_outputs
) {
11009 emit_streamout(&ctx
, stream
);
11010 bld
.reset(ctx
.block
);
11014 create_vs_exports(&ctx
);
11015 ctx
.block
->kind
|= block_kind_export_end
;
11018 if (!stream_id
.isConstant()) {
11019 append_logical_end(ctx
.block
);
11021 /* branch from then block to endif block */
11022 bld
.branch(aco_opcode::p_branch
);
11023 add_edge(ctx
.block
->index
, &BB_endif
);
11024 ctx
.block
->kind
|= block_kind_uniform
;
11026 /* emit else block */
11027 ctx
.block
= ctx
.program
->create_and_insert_block();
11028 add_edge(BB_if_idx
, ctx
.block
);
11029 bld
.reset(ctx
.block
);
11030 append_logical_start(ctx
.block
);
11032 endif_blocks
.push(std::move(BB_endif
));
11036 while (!endif_blocks
.empty()) {
11037 Block BB_endif
= std::move(endif_blocks
.top());
11038 endif_blocks
.pop();
11040 Block
*BB_else
= ctx
.block
;
11042 append_logical_end(BB_else
);
11043 /* branch from else block to endif block */
11044 bld
.branch(aco_opcode::p_branch
);
11045 add_edge(BB_else
->index
, &BB_endif
);
11046 BB_else
->kind
|= block_kind_uniform
;
11048 /** emit endif merge block */
11049 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11050 bld
.reset(ctx
.block
);
11051 append_logical_start(ctx
.block
);
11054 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11056 append_logical_end(ctx
.block
);
11057 ctx
.block
->kind
|= block_kind_uniform
;
11058 bld
.sopp(aco_opcode::s_endpgm
);
11060 cleanup_cfg(program
);