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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
139 } else if (ctx
->program
->chip_class
<= GFX7
) {
140 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
143 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
148 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
150 Builder
bld(ctx
->program
, ctx
->block
);
153 dst
= bld
.tmp(src
.regClass());
155 assert(src
.size() == dst
.size());
157 if (ctx
->stage
!= fragment_fs
) {
161 bld
.copy(Definition(dst
), src
);
165 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
166 ctx
->program
->needs_wqm
|= program_needs_wqm
;
170 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
172 if (index
.regClass() == s1
)
173 return bld
.readlane(bld
.def(s1
), data
, index
);
175 if (ctx
->options
->chip_class
<= GFX7
) {
176 /* GFX6-7: there is no bpermute instruction */
177 Operand
index_op(index
);
178 Operand
input_data(data
);
179 index_op
.setLateKill(true);
180 input_data
.setLateKill(true);
182 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
183 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
184 /* GFX10 wave64 mode: emulate full-wave bpermute */
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
192 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
193 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
194 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
195 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
196 Operand
input_data(data
);
198 index_x4
.setLateKill(true);
199 input_data
.setLateKill(true);
200 same_half
.setLateKill(true);
202 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
204 /* GFX8-9 or GFX10 wave32: bpermute works normally */
205 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
206 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
210 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
212 if (ctx
->options
->chip_class
>= GFX8
) {
213 unsigned and_mask
= mask
& 0x1f;
214 unsigned or_mask
= (mask
>> 5) & 0x1f;
215 unsigned xor_mask
= (mask
>> 10) & 0x1f;
217 uint16_t dpp_ctrl
= 0xffff;
219 // TODO: we could use DPP8 for some swizzles
220 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
221 unsigned res
[4] = {0, 1, 2, 3};
222 for (unsigned i
= 0; i
< 4; i
++)
223 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
224 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
225 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
226 dpp_ctrl
= dpp_row_rr(8);
227 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
228 dpp_ctrl
= dpp_row_mirror
;
229 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
230 dpp_ctrl
= dpp_row_half_mirror
;
233 if (dpp_ctrl
!= 0xffff)
234 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
237 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
240 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
242 if (val
.type() == RegType::sgpr
) {
243 Builder
bld(ctx
->program
, ctx
->block
);
244 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
246 assert(val
.type() == RegType::vgpr
);
250 //assumes a != 0xffffffff
251 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
254 Builder
bld(ctx
->program
, ctx
->block
);
256 if (util_is_power_of_two_or_zero(b
)) {
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
261 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
263 assert(info
.multiplier
<= 0xffffffff);
265 bool pre_shift
= info
.pre_shift
!= 0;
266 bool increment
= info
.increment
!= 0;
267 bool multiply
= true;
268 bool post_shift
= info
.post_shift
!= 0;
270 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
271 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
275 Temp pre_shift_dst
= a
;
277 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
278 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
281 Temp increment_dst
= pre_shift_dst
;
283 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
284 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
287 Temp multiply_dst
= increment_dst
;
289 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
290 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
291 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
299 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
301 Builder
bld(ctx
->program
, ctx
->block
);
302 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
306 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
308 /* no need to extract the whole vector */
309 if (src
.regClass() == dst_rc
) {
314 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
315 Builder
bld(ctx
->program
, ctx
->block
);
316 auto it
= ctx
->allocated_vec
.find(src
.id());
317 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
318 if (it
->second
[idx
].regClass() == dst_rc
) {
319 return it
->second
[idx
];
321 assert(!dst_rc
.is_subdword());
322 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
323 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
327 if (dst_rc
.is_subdword())
328 src
= as_vgpr(ctx
, src
);
330 if (src
.bytes() == dst_rc
.bytes()) {
332 return bld
.copy(bld
.def(dst_rc
), src
);
334 Temp dst
= bld
.tmp(dst_rc
);
335 emit_extract_vector(ctx
, src
, idx
, dst
);
340 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
342 if (num_components
== 1)
344 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
347 if (num_components
> vec_src
.size()) {
348 if (vec_src
.type() == RegType::sgpr
) {
349 /* should still help get_alu_src() */
350 emit_split_vector(ctx
, vec_src
, vec_src
.size());
353 /* sub-dword split */
354 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
356 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
358 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
359 split
->operands
[0] = Operand(vec_src
);
360 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
361 for (unsigned i
= 0; i
< num_components
; i
++) {
362 elems
[i
] = {ctx
->program
->allocateId(), rc
};
363 split
->definitions
[i
] = Definition(elems
[i
]);
365 ctx
->block
->instructions
.emplace_back(std::move(split
));
366 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
369 /* This vector expansion uses a mask to determine which elements in the new vector
370 * come from the original vector. The other elements are undefined. */
371 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
373 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
378 Builder
bld(ctx
->program
, ctx
->block
);
379 if (num_components
== 1) {
380 if (dst
.type() == RegType::sgpr
)
381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
383 bld
.copy(Definition(dst
), vec_src
);
387 unsigned component_size
= dst
.size() / num_components
;
388 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
390 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
391 vec
->definitions
[0] = Definition(dst
);
393 for (unsigned i
= 0; i
< num_components
; i
++) {
394 if (mask
& (1 << i
)) {
395 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
396 if (dst
.type() == RegType::sgpr
)
397 src
= bld
.as_uniform(src
);
398 vec
->operands
[i
] = Operand(src
);
400 vec
->operands
[i
] = Operand(0u);
402 elems
[i
] = vec
->operands
[i
].getTemp();
404 ctx
->block
->instructions
.emplace_back(std::move(vec
));
405 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
408 /* adjust misaligned small bit size loads */
409 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
411 Builder
bld(ctx
->program
, ctx
->block
);
413 Temp select
= Temp();
414 if (offset
.isConstant()) {
415 assert(offset
.constantValue() && offset
.constantValue() < 4);
416 shift
= Operand(offset
.constantValue() * 8);
418 /* bit_offset = 8 * (offset & 0x3) */
419 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
420 select
= bld
.tmp(s1
);
421 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
424 if (vec
.size() == 1) {
425 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
426 } else if (vec
.size() == 2) {
427 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
428 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
430 emit_split_vector(ctx
, dst
, 2);
432 emit_extract_vector(ctx
, tmp
, 0, dst
);
433 } else if (vec
.size() == 4) {
434 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
435 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
436 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
437 if (select
!= Temp())
438 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
439 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
440 Temp mid
= bld
.tmp(s1
);
441 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
442 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
443 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
444 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
445 emit_split_vector(ctx
, dst
, 2);
449 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
451 Builder
bld(ctx
->program
, ctx
->block
);
452 if (offset
.isTemp()) {
453 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
455 if (vec
.size() == 4) {
456 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
458 } else if (vec
.size() == 3) {
459 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
461 } else if (vec
.size() == 2) {
462 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
465 for (unsigned i
= 0; i
< dst
.size(); i
++)
466 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
470 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
472 offset
= Operand(0u);
475 unsigned num_components
= vec
.bytes() / component_size
;
476 if (vec
.regClass() == dst
.regClass()) {
477 assert(offset
.constantValue() == 0);
478 bld
.copy(Definition(dst
), vec
);
479 emit_split_vector(ctx
, dst
, num_components
);
483 emit_split_vector(ctx
, vec
, num_components
);
484 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
485 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
487 assert(offset
.constantValue() % component_size
== 0);
488 unsigned skip
= offset
.constantValue() / component_size
;
489 for (unsigned i
= skip
; i
< num_components
; i
++)
490 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
492 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
493 if (dst
.type() == RegType::vgpr
) {
494 num_components
= dst
.bytes() / component_size
;
495 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
496 for (unsigned i
= 0; i
< num_components
; i
++)
497 create_vec
->operands
[i
] = Operand(elems
[i
]);
498 create_vec
->definitions
[0] = Definition(dst
);
499 bld
.insert(std::move(create_vec
));
501 /* if dst is sgpr - split the src, but move the original to sgpr. */
503 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
504 byte_align_scalar(ctx
, vec
, offset
, dst
);
506 assert(dst
.size() == vec
.size());
507 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
510 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
513 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
515 Builder
bld(ctx
->program
, ctx
->block
);
517 dst
= bld
.tmp(bld
.lm
);
519 assert(val
.regClass() == s1
);
520 assert(dst
.regClass() == bld
.lm
);
522 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
525 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
527 Builder
bld(ctx
->program
, ctx
->block
);
531 assert(val
.regClass() == bld
.lm
);
532 assert(dst
.regClass() == s1
);
534 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
535 Temp tmp
= bld
.tmp(s1
);
536 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
537 return emit_wqm(ctx
, tmp
, dst
);
540 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
542 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
543 return get_ssa_temp(ctx
, src
.src
.ssa
);
545 if (src
.src
.ssa
->num_components
== size
) {
546 bool identity_swizzle
= true;
547 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
548 if (src
.swizzle
[i
] != i
)
549 identity_swizzle
= false;
551 if (identity_swizzle
)
552 return get_ssa_temp(ctx
, src
.src
.ssa
);
555 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
556 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
557 assert(elem_size
> 0);
558 assert(vec
.bytes() % elem_size
== 0);
560 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
561 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
563 unsigned swizzle
= src
.swizzle
[0];
564 if (vec
.size() > 1) {
565 assert(src
.src
.ssa
->bit_size
== 16);
566 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
567 swizzle
= swizzle
& 1;
572 Temp dst
{ctx
->program
->allocateId(), s1
};
573 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
574 bfe
->operands
[0] = Operand(vec
);
575 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
576 bfe
->definitions
[0] = Definition(dst
);
577 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
578 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
582 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
584 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
587 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
588 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
589 for (unsigned i
= 0; i
< size
; ++i
) {
590 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
591 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
593 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
594 vec_instr
->definitions
[0] = Definition(dst
);
595 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
596 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
601 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
605 Builder
bld(ctx
->program
, ctx
->block
);
606 if (ptr
.type() == RegType::vgpr
)
607 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
608 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
609 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
612 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
614 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
615 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
616 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
617 sop2
->definitions
[0] = Definition(dst
);
618 if (instr
->no_unsigned_wrap
)
619 sop2
->definitions
[0].setNUW(true);
621 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
622 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
625 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
626 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
628 Builder
bld(ctx
->program
, ctx
->block
);
629 bld
.is_precise
= instr
->exact
;
631 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
632 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
633 if (src1
.type() == RegType::sgpr
) {
634 if (commutative
&& src0
.type() == RegType::vgpr
) {
639 src1
= as_vgpr(ctx
, src1
);
643 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
644 assert(dst
.size() == 1);
645 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
646 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
648 bld
.vop2(op
, Definition(dst
), src0
, src1
);
652 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
653 aco_opcode op
, Temp dst
)
655 Builder
bld(ctx
->program
, ctx
->block
);
656 bld
.is_precise
= instr
->exact
;
658 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
659 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
661 if (src1
.type() == RegType::sgpr
) {
662 assert(src0
.type() == RegType::vgpr
);
663 std::swap(src0
, src1
);
666 Temp src00
= bld
.tmp(src0
.type(), 1);
667 Temp src01
= bld
.tmp(src0
.type(), 1);
668 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
669 Temp src10
= bld
.tmp(v1
);
670 Temp src11
= bld
.tmp(v1
);
671 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
672 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
673 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
674 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
677 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
678 bool flush_denorms
= false)
680 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
681 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
682 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
684 /* ensure that the instruction has at most 1 sgpr operand
685 * The optimizer will inline constants for us */
686 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
687 src0
= as_vgpr(ctx
, src0
);
688 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
689 src1
= as_vgpr(ctx
, src1
);
690 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
691 src2
= as_vgpr(ctx
, src2
);
693 Builder
bld(ctx
->program
, ctx
->block
);
694 bld
.is_precise
= instr
->exact
;
695 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
696 assert(dst
.size() == 1);
697 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
698 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
700 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
704 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
706 Builder
bld(ctx
->program
, ctx
->block
);
707 bld
.is_precise
= instr
->exact
;
708 if (dst
.type() == RegType::sgpr
)
709 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
710 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
712 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
715 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
717 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
718 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
719 assert(src0
.size() == src1
.size());
721 aco_ptr
<Instruction
> vopc
;
722 if (src1
.type() == RegType::sgpr
) {
723 if (src0
.type() == RegType::vgpr
) {
724 /* to swap the operands, we might also have to change the opcode */
726 case aco_opcode::v_cmp_lt_f16
:
727 op
= aco_opcode::v_cmp_gt_f16
;
729 case aco_opcode::v_cmp_ge_f16
:
730 op
= aco_opcode::v_cmp_le_f16
;
732 case aco_opcode::v_cmp_lt_i16
:
733 op
= aco_opcode::v_cmp_gt_i16
;
735 case aco_opcode::v_cmp_ge_i16
:
736 op
= aco_opcode::v_cmp_le_i16
;
738 case aco_opcode::v_cmp_lt_u16
:
739 op
= aco_opcode::v_cmp_gt_u16
;
741 case aco_opcode::v_cmp_ge_u16
:
742 op
= aco_opcode::v_cmp_le_u16
;
744 case aco_opcode::v_cmp_lt_f32
:
745 op
= aco_opcode::v_cmp_gt_f32
;
747 case aco_opcode::v_cmp_ge_f32
:
748 op
= aco_opcode::v_cmp_le_f32
;
750 case aco_opcode::v_cmp_lt_i32
:
751 op
= aco_opcode::v_cmp_gt_i32
;
753 case aco_opcode::v_cmp_ge_i32
:
754 op
= aco_opcode::v_cmp_le_i32
;
756 case aco_opcode::v_cmp_lt_u32
:
757 op
= aco_opcode::v_cmp_gt_u32
;
759 case aco_opcode::v_cmp_ge_u32
:
760 op
= aco_opcode::v_cmp_le_u32
;
762 case aco_opcode::v_cmp_lt_f64
:
763 op
= aco_opcode::v_cmp_gt_f64
;
765 case aco_opcode::v_cmp_ge_f64
:
766 op
= aco_opcode::v_cmp_le_f64
;
768 case aco_opcode::v_cmp_lt_i64
:
769 op
= aco_opcode::v_cmp_gt_i64
;
771 case aco_opcode::v_cmp_ge_i64
:
772 op
= aco_opcode::v_cmp_le_i64
;
774 case aco_opcode::v_cmp_lt_u64
:
775 op
= aco_opcode::v_cmp_gt_u64
;
777 case aco_opcode::v_cmp_ge_u64
:
778 op
= aco_opcode::v_cmp_le_u64
;
780 default: /* eq and ne are commutative */
787 src1
= as_vgpr(ctx
, src1
);
791 Builder
bld(ctx
->program
, ctx
->block
);
792 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
795 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
797 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
798 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
799 Builder
bld(ctx
->program
, ctx
->block
);
801 assert(dst
.regClass() == bld
.lm
);
802 assert(src0
.type() == RegType::sgpr
);
803 assert(src1
.type() == RegType::sgpr
);
804 assert(src0
.regClass() == src1
.regClass());
806 /* Emit the SALU comparison instruction */
807 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
808 /* Turn the result into a per-lane bool */
809 bool_to_vector_condition(ctx
, cmp
, dst
);
812 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
813 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
815 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
816 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
817 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
818 nir_dest_is_divergent(instr
->dest
.dest
) ||
819 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
820 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
821 aco_opcode op
= use_valu
? v_op
: s_op
;
822 assert(op
!= aco_opcode::num_opcodes
);
823 assert(dst
.regClass() == ctx
->program
->lane_mask
);
826 emit_vopc_instruction(ctx
, instr
, op
, dst
);
828 emit_sopc_instruction(ctx
, instr
, op
, dst
);
831 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
833 Builder
bld(ctx
->program
, ctx
->block
);
834 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
835 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
837 assert(dst
.regClass() == bld
.lm
);
838 assert(src0
.regClass() == bld
.lm
);
839 assert(src1
.regClass() == bld
.lm
);
841 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
844 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
846 Builder
bld(ctx
->program
, ctx
->block
);
847 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
848 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
849 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
851 assert(cond
.regClass() == bld
.lm
);
853 if (dst
.type() == RegType::vgpr
) {
854 aco_ptr
<Instruction
> bcsel
;
855 if (dst
.size() == 1) {
856 then
= as_vgpr(ctx
, then
);
857 els
= as_vgpr(ctx
, els
);
859 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
860 } else if (dst
.size() == 2) {
861 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
863 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
864 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
866 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
867 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
872 nir_print_instr(&instr
->instr
, stderr
);
873 fprintf(stderr
, "\n");
878 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
879 assert(dst
.regClass() == bld
.lm
);
880 assert(then
.regClass() == bld
.lm
);
881 assert(els
.regClass() == bld
.lm
);
884 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
885 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
886 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
887 assert(dst
.size() == then
.size());
888 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
889 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
891 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
892 nir_print_instr(&instr
->instr
, stderr
);
893 fprintf(stderr
, "\n");
898 /* divergent boolean bcsel
899 * this implements bcsel on bools: dst = s0 ? s1 : s2
900 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
901 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
903 if (cond
.id() != then
.id())
904 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
906 if (cond
.id() == els
.id())
907 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
909 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
910 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
913 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
914 aco_opcode op
, uint32_t undo
)
916 /* multiply by 16777216 to handle denormals */
917 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
918 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
919 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
920 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
921 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
923 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
925 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
928 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
930 if (ctx
->block
->fp_mode
.denorm32
== 0) {
931 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
935 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
938 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
940 if (ctx
->block
->fp_mode
.denorm32
== 0) {
941 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
945 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
948 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
950 if (ctx
->block
->fp_mode
.denorm32
== 0) {
951 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
955 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
958 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
960 if (ctx
->block
->fp_mode
.denorm32
== 0) {
961 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
965 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
968 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
970 if (ctx
->options
->chip_class
>= GFX7
)
971 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
973 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
974 /* TODO: create more efficient code! */
975 if (val
.type() == RegType::sgpr
)
976 val
= as_vgpr(ctx
, val
);
978 /* Split the input value. */
979 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
980 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
982 /* Extract the exponent and compute the unbiased value. */
983 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
984 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
986 /* Extract the fractional part. */
987 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
988 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
990 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
991 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
993 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
994 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
995 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
996 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
997 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
999 /* Get the sign bit. */
1000 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1002 /* Decide the operation to apply depending on the unbiased exponent. */
1003 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1004 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1005 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1006 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1007 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1008 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1010 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1013 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1015 if (ctx
->options
->chip_class
>= GFX7
)
1016 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1018 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1019 * lowered at NIR level for precision reasons). */
1020 Temp src0
= as_vgpr(ctx
, val
);
1022 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1023 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1025 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1026 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1027 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1029 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1030 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1031 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1032 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1034 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1035 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1037 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1039 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1040 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1042 return add
->definitions
[0].getTemp();
1045 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1047 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1048 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1050 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1053 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1054 return bld
.copy(Definition(dst
), src
);
1055 else if (dst
.bytes() < src
.bytes())
1056 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1060 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1063 } else if (src
.regClass() == s1
) {
1065 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1067 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1068 } else if (ctx
->options
->chip_class
>= GFX8
) {
1069 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1070 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1071 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1072 sdwa
->operands
[0] = Operand(src
);
1073 sdwa
->definitions
[0] = Definition(tmp
);
1075 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1077 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1078 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1079 bld
.insert(std::move(sdwa
));
1081 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1082 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1083 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1086 if (dst_bits
== 64) {
1087 if (is_signed
&& dst
.regClass() == s2
) {
1088 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1089 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1090 } else if (is_signed
&& dst
.regClass() == v2
) {
1091 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1092 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1094 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1101 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1103 if (!instr
->dest
.dest
.is_ssa
) {
1104 fprintf(stderr
, "nir alu dst not in ssa: ");
1105 nir_print_instr(&instr
->instr
, stderr
);
1106 fprintf(stderr
, "\n");
1109 Builder
bld(ctx
->program
, ctx
->block
);
1110 bld
.is_precise
= instr
->exact
;
1111 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1116 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1117 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1118 for (unsigned i
= 0; i
< num
; ++i
)
1119 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1121 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1122 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1123 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1124 for (unsigned i
= 0; i
< num
; ++i
) {
1125 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1126 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1128 vec
->operands
[i
] = Operand
{elems
[i
]};
1130 vec
->definitions
[0] = Definition(dst
);
1131 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1132 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1134 // TODO: that is a bit suboptimal..
1135 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1136 for (unsigned i
= 0; i
< num
- 1; ++i
)
1137 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1138 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1139 for (unsigned i
= 0; i
< num
; ++i
) {
1140 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1141 if (bit
% 32 == 0) {
1142 elems
[bit
/ 32] = elems
[i
];
1144 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1145 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1146 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1149 if (dst
.size() == 1)
1150 bld
.copy(Definition(dst
), elems
[0]);
1152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1157 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1158 aco_ptr
<Instruction
> mov
;
1159 if (dst
.type() == RegType::sgpr
) {
1160 if (src
.type() == RegType::vgpr
)
1161 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1162 else if (src
.regClass() == s1
)
1163 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1164 else if (src
.regClass() == s2
)
1165 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1167 unreachable("wrong src register class for nir_op_imov");
1169 if (dst
.regClass() == v1
)
1170 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1171 else if (dst
.regClass() == v1b
||
1172 dst
.regClass() == v2b
||
1173 dst
.regClass() == v2
)
1174 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1176 unreachable("wrong src register class for nir_op_imov");
1181 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1182 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1183 assert(src
.regClass() == bld
.lm
);
1184 assert(dst
.regClass() == bld
.lm
);
1185 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1186 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1187 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1188 } else if (dst
.regClass() == v1
) {
1189 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1190 } else if (dst
.regClass() == v2
) {
1191 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1192 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1193 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1194 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1196 } else if (dst
.type() == RegType::sgpr
) {
1197 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1198 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1200 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1201 nir_print_instr(&instr
->instr
, stderr
);
1202 fprintf(stderr
, "\n");
1207 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1208 if (dst
.regClass() == v1
) {
1209 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1210 } else if (dst
.regClass() == s1
) {
1211 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1212 } else if (dst
.size() == 2) {
1213 Temp src0
= bld
.tmp(dst
.type(), 1);
1214 Temp src1
= bld
.tmp(dst
.type(), 1);
1215 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1217 if (dst
.regClass() == s2
) {
1218 Temp carry
= bld
.tmp(s1
);
1219 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1220 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1221 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1223 Temp lower
= bld
.tmp(v1
);
1224 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1225 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == s1
) {
1237 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1238 } else if (dst
.regClass() == v1
) {
1239 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1240 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1242 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1243 nir_print_instr(&instr
->instr
, stderr
);
1244 fprintf(stderr
, "\n");
1248 case nir_op_isign
: {
1249 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1250 if (dst
.regClass() == s1
) {
1251 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1252 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1253 } else if (dst
.regClass() == s2
) {
1254 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1256 if (ctx
->program
->chip_class
>= GFX8
)
1257 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1259 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1260 /* SCC gets zero-extended to 64 bit */
1261 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1262 } else if (dst
.regClass() == v1
) {
1263 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1264 } else if (dst
.regClass() == v2
) {
1265 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1266 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1267 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1268 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1269 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1270 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1272 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1273 nir_print_instr(&instr
->instr
, stderr
);
1274 fprintf(stderr
, "\n");
1279 if (dst
.regClass() == v1
) {
1280 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1281 } else if (dst
.regClass() == s1
) {
1282 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1291 if (dst
.regClass() == v1
) {
1292 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1293 } else if (dst
.regClass() == s1
) {
1294 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1296 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1297 nir_print_instr(&instr
->instr
, stderr
);
1298 fprintf(stderr
, "\n");
1303 if (dst
.regClass() == v1
) {
1304 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1305 } else if (dst
.regClass() == s1
) {
1306 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1308 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1309 nir_print_instr(&instr
->instr
, stderr
);
1310 fprintf(stderr
, "\n");
1315 if (dst
.regClass() == v1
) {
1316 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1317 } else if (dst
.regClass() == s1
) {
1318 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1320 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1321 nir_print_instr(&instr
->instr
, stderr
);
1322 fprintf(stderr
, "\n");
1327 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1328 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1329 } else if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1331 } else if (dst
.regClass() == v2
) {
1332 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1333 } else if (dst
.regClass() == s1
) {
1334 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1335 } else if (dst
.regClass() == s2
) {
1336 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1338 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1339 nir_print_instr(&instr
->instr
, stderr
);
1340 fprintf(stderr
, "\n");
1345 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1346 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1347 } else if (dst
.regClass() == v1
) {
1348 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1349 } else if (dst
.regClass() == v2
) {
1350 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1351 } else if (dst
.regClass() == s1
) {
1352 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1353 } else if (dst
.regClass() == s2
) {
1354 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1356 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1357 nir_print_instr(&instr
->instr
, stderr
);
1358 fprintf(stderr
, "\n");
1363 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1364 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1365 } else if (dst
.regClass() == v1
) {
1366 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1367 } else if (dst
.regClass() == v2
) {
1368 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1369 } else if (dst
.regClass() == s1
) {
1370 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1371 } else if (dst
.regClass() == s2
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1374 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1375 nir_print_instr(&instr
->instr
, stderr
);
1376 fprintf(stderr
, "\n");
1381 if (dst
.regClass() == v1
) {
1382 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1383 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1384 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1385 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1386 } else if (dst
.regClass() == v2
) {
1387 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1388 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1391 } else if (dst
.regClass() == s1
) {
1392 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1401 if (dst
.regClass() == v1
) {
1402 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1403 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1404 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1405 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1406 } else if (dst
.regClass() == v2
) {
1407 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1408 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1409 } else if (dst
.regClass() == s1
) {
1410 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1411 } else if (dst
.regClass() == s2
) {
1412 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1414 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1415 nir_print_instr(&instr
->instr
, stderr
);
1416 fprintf(stderr
, "\n");
1421 if (dst
.regClass() == v1
) {
1422 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1423 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1424 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1425 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1426 } else if (dst
.regClass() == v2
) {
1427 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1428 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1429 } else if (dst
.regClass() == s1
) {
1430 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1431 } else if (dst
.regClass() == s2
) {
1432 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1434 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1435 nir_print_instr(&instr
->instr
, stderr
);
1436 fprintf(stderr
, "\n");
1440 case nir_op_find_lsb
: {
1441 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1442 if (src
.regClass() == s1
) {
1443 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1444 } else if (src
.regClass() == v1
) {
1445 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1446 } else if (src
.regClass() == s2
) {
1447 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1449 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1450 nir_print_instr(&instr
->instr
, stderr
);
1451 fprintf(stderr
, "\n");
1455 case nir_op_ufind_msb
:
1456 case nir_op_ifind_msb
: {
1457 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1458 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1459 aco_opcode op
= src
.regClass() == s2
?
1460 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1461 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1462 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1464 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1465 Operand(src
.size() * 32u - 1u), msb_rev
);
1466 Temp msb
= sub
.def(0).getTemp();
1467 Temp carry
= sub
.def(1).getTemp();
1469 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1470 } else if (src
.regClass() == v1
) {
1471 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1472 Temp msb_rev
= bld
.tmp(v1
);
1473 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1474 Temp msb
= bld
.tmp(v1
);
1475 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1476 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1478 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1479 nir_print_instr(&instr
->instr
, stderr
);
1480 fprintf(stderr
, "\n");
1484 case nir_op_bitfield_reverse
: {
1485 if (dst
.regClass() == s1
) {
1486 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1487 } else if (dst
.regClass() == v1
) {
1488 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1497 if (dst
.regClass() == s1
) {
1498 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1502 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1503 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1504 if (dst
.regClass() == v1
) {
1505 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1509 assert(src0
.size() == 2 && src1
.size() == 2);
1510 Temp src00
= bld
.tmp(src0
.type(), 1);
1511 Temp src01
= bld
.tmp(dst
.type(), 1);
1512 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1513 Temp src10
= bld
.tmp(src1
.type(), 1);
1514 Temp src11
= bld
.tmp(dst
.type(), 1);
1515 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1517 if (dst
.regClass() == s2
) {
1518 Temp carry
= bld
.tmp(s1
);
1519 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1520 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1521 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1522 } else if (dst
.regClass() == v2
) {
1523 Temp dst0
= bld
.tmp(v1
);
1524 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1525 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1526 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1528 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1529 nir_print_instr(&instr
->instr
, stderr
);
1530 fprintf(stderr
, "\n");
1534 case nir_op_uadd_sat
: {
1535 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1536 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1537 if (dst
.regClass() == s1
) {
1538 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1539 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1541 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1542 } else if (dst
.regClass() == v1
) {
1543 if (ctx
->options
->chip_class
>= GFX9
) {
1544 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1545 add
->operands
[0] = Operand(src0
);
1546 add
->operands
[1] = Operand(src1
);
1547 add
->definitions
[0] = Definition(dst
);
1549 ctx
->block
->instructions
.emplace_back(std::move(add
));
1551 if (src1
.regClass() != v1
)
1552 std::swap(src0
, src1
);
1553 assert(src1
.regClass() == v1
);
1554 Temp tmp
= bld
.tmp(v1
);
1555 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1556 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1560 nir_print_instr(&instr
->instr
, stderr
);
1561 fprintf(stderr
, "\n");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1596 nir_print_instr(&instr
->instr
, stderr
);
1597 fprintf(stderr
, "\n");
1602 if (dst
.regClass() == s1
) {
1603 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1607 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1608 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1609 if (dst
.regClass() == v1
) {
1610 bld
.vsub32(Definition(dst
), src0
, src1
);
1614 Temp src00
= bld
.tmp(src0
.type(), 1);
1615 Temp src01
= bld
.tmp(dst
.type(), 1);
1616 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1617 Temp src10
= bld
.tmp(src1
.type(), 1);
1618 Temp src11
= bld
.tmp(dst
.type(), 1);
1619 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1620 if (dst
.regClass() == s2
) {
1621 Temp carry
= bld
.tmp(s1
);
1622 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1623 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1625 } else if (dst
.regClass() == v2
) {
1626 Temp lower
= bld
.tmp(v1
);
1627 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1628 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1629 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_usub_borrow
: {
1638 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1639 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1640 if (dst
.regClass() == s1
) {
1641 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1643 } else if (dst
.regClass() == v1
) {
1644 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1645 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1649 Temp src00
= bld
.tmp(src0
.type(), 1);
1650 Temp src01
= bld
.tmp(dst
.type(), 1);
1651 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1652 Temp src10
= bld
.tmp(src1
.type(), 1);
1653 Temp src11
= bld
.tmp(dst
.type(), 1);
1654 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1655 if (dst
.regClass() == s2
) {
1656 Temp borrow
= bld
.tmp(s1
);
1657 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1658 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1659 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1660 } else if (dst
.regClass() == v2
) {
1661 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1662 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1663 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1664 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1666 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1667 nir_print_instr(&instr
->instr
, stderr
);
1668 fprintf(stderr
, "\n");
1673 if (dst
.regClass() == v1
) {
1674 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1675 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1676 } else if (dst
.regClass() == s1
) {
1677 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1685 case nir_op_umul_high
: {
1686 if (dst
.regClass() == v1
) {
1687 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1688 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1689 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1690 } else if (dst
.regClass() == s1
) {
1691 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1692 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1693 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1695 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1696 nir_print_instr(&instr
->instr
, stderr
);
1697 fprintf(stderr
, "\n");
1701 case nir_op_imul_high
: {
1702 if (dst
.regClass() == v1
) {
1703 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1704 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1705 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1706 } else if (dst
.regClass() == s1
) {
1707 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1708 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1709 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1711 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1712 nir_print_instr(&instr
->instr
, stderr
);
1713 fprintf(stderr
, "\n");
1718 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1719 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1720 if (dst
.regClass() == v2b
) {
1721 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1722 } else if (dst
.regClass() == v1
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1724 } else if (dst
.regClass() == v2
) {
1725 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1727 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1728 nir_print_instr(&instr
->instr
, stderr
);
1729 fprintf(stderr
, "\n");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1736 if (dst
.regClass() == v2b
) {
1737 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1738 } else if (dst
.regClass() == v1
) {
1739 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1740 } else if (dst
.regClass() == v2
) {
1741 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1743 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1744 nir_print_instr(&instr
->instr
, stderr
);
1745 fprintf(stderr
, "\n");
1750 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1751 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1752 if (dst
.regClass() == v2b
) {
1753 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1754 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1756 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1757 } else if (dst
.regClass() == v1
) {
1758 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1759 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1762 } else if (dst
.regClass() == v2
) {
1763 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1764 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1765 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1769 nir_print_instr(&instr
->instr
, stderr
);
1770 fprintf(stderr
, "\n");
1775 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1776 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1777 if (dst
.regClass() == v2b
) {
1778 // TODO: check fp_mode.must_flush_denorms16_64
1779 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1780 } else if (dst
.regClass() == v1
) {
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1782 } else if (dst
.regClass() == v2
) {
1783 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1784 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1785 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1787 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1791 nir_print_instr(&instr
->instr
, stderr
);
1792 fprintf(stderr
, "\n");
1797 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1798 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1799 if (dst
.regClass() == v2b
) {
1800 // TODO: check fp_mode.must_flush_denorms16_64
1801 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1802 } else if (dst
.regClass() == v1
) {
1803 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1804 } else if (dst
.regClass() == v2
) {
1805 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1806 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1807 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1809 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1812 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1813 nir_print_instr(&instr
->instr
, stderr
);
1814 fprintf(stderr
, "\n");
1818 case nir_op_fmax3
: {
1819 if (dst
.regClass() == v2b
) {
1820 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1821 } else if (dst
.regClass() == v1
) {
1822 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1830 case nir_op_fmin3
: {
1831 if (dst
.regClass() == v2b
) {
1832 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1833 } else if (dst
.regClass() == v1
) {
1834 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1836 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1837 nir_print_instr(&instr
->instr
, stderr
);
1838 fprintf(stderr
, "\n");
1842 case nir_op_fmed3
: {
1843 if (dst
.regClass() == v2b
) {
1844 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1845 } else if (dst
.regClass() == v1
) {
1846 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1848 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1849 nir_print_instr(&instr
->instr
, stderr
);
1850 fprintf(stderr
, "\n");
1854 case nir_op_umax3
: {
1855 if (dst
.size() == 1) {
1856 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1858 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1859 nir_print_instr(&instr
->instr
, stderr
);
1860 fprintf(stderr
, "\n");
1864 case nir_op_umin3
: {
1865 if (dst
.size() == 1) {
1866 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1868 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1869 nir_print_instr(&instr
->instr
, stderr
);
1870 fprintf(stderr
, "\n");
1874 case nir_op_umed3
: {
1875 if (dst
.size() == 1) {
1876 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1878 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1879 nir_print_instr(&instr
->instr
, stderr
);
1880 fprintf(stderr
, "\n");
1884 case nir_op_imax3
: {
1885 if (dst
.size() == 1) {
1886 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1894 case nir_op_imin3
: {
1895 if (dst
.size() == 1) {
1896 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1898 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1899 nir_print_instr(&instr
->instr
, stderr
);
1900 fprintf(stderr
, "\n");
1904 case nir_op_imed3
: {
1905 if (dst
.size() == 1) {
1906 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_cube_face_coord
: {
1915 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1916 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1917 emit_extract_vector(ctx
, in
, 1, v1
),
1918 emit_extract_vector(ctx
, in
, 2, v1
) };
1919 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1920 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1921 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1922 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1923 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1924 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1925 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1928 case nir_op_cube_face_index
: {
1929 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1930 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1931 emit_extract_vector(ctx
, in
, 1, v1
),
1932 emit_extract_vector(ctx
, in
, 2, v1
) };
1933 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1936 case nir_op_bcsel
: {
1937 emit_bcsel(ctx
, instr
, dst
);
1941 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1942 if (dst
.regClass() == v2b
) {
1943 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1944 } else if (dst
.regClass() == v1
) {
1945 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1946 } else if (dst
.regClass() == v2
) {
1947 /* Lowered at NIR level for precision reasons. */
1948 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1950 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1951 nir_print_instr(&instr
->instr
, stderr
);
1952 fprintf(stderr
, "\n");
1957 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1958 if (dst
.regClass() == v2b
) {
1959 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1960 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1961 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1962 } else if (dst
.regClass() == v1
) {
1963 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1964 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1965 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1966 } else if (dst
.regClass() == v2
) {
1967 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1968 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1969 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1970 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1971 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1972 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1974 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1975 nir_print_instr(&instr
->instr
, stderr
);
1976 fprintf(stderr
, "\n");
1981 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1982 if (dst
.regClass() == v2b
) {
1983 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1984 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1985 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1986 } else if (dst
.regClass() == v1
) {
1987 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1988 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1989 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1990 } else if (dst
.regClass() == v2
) {
1991 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1992 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1993 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1995 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1996 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1998 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1999 nir_print_instr(&instr
->instr
, stderr
);
2000 fprintf(stderr
, "\n");
2005 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2006 if (dst
.regClass() == v2b
) {
2007 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
2008 } else if (dst
.regClass() == v1
) {
2009 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2010 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
2011 // TODO: confirm that this holds under any circumstances
2012 } else if (dst
.regClass() == v2
) {
2013 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
2014 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
2017 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2018 nir_print_instr(&instr
->instr
, stderr
);
2019 fprintf(stderr
, "\n");
2023 case nir_op_flog2
: {
2024 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2025 if (dst
.regClass() == v2b
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
2027 } else if (dst
.regClass() == v1
) {
2028 emit_log2(ctx
, bld
, Definition(dst
), src
);
2030 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2031 nir_print_instr(&instr
->instr
, stderr
);
2032 fprintf(stderr
, "\n");
2037 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2038 if (dst
.regClass() == v2b
) {
2039 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2040 } else if (dst
.regClass() == v1
) {
2041 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2042 } else if (dst
.regClass() == v2
) {
2043 /* Lowered at NIR level for precision reasons. */
2044 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2046 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2047 nir_print_instr(&instr
->instr
, stderr
);
2048 fprintf(stderr
, "\n");
2052 case nir_op_fexp2
: {
2053 if (dst
.regClass() == v2b
) {
2054 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2055 } else if (dst
.regClass() == v1
) {
2056 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2058 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2059 nir_print_instr(&instr
->instr
, stderr
);
2060 fprintf(stderr
, "\n");
2064 case nir_op_fsqrt
: {
2065 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2066 if (dst
.regClass() == v2b
) {
2067 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2068 } else if (dst
.regClass() == v1
) {
2069 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2070 } else if (dst
.regClass() == v2
) {
2071 /* Lowered at NIR level for precision reasons. */
2072 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2074 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2075 nir_print_instr(&instr
->instr
, stderr
);
2076 fprintf(stderr
, "\n");
2080 case nir_op_ffract
: {
2081 if (dst
.regClass() == v2b
) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2083 } else if (dst
.regClass() == v1
) {
2084 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2085 } else if (dst
.regClass() == v2
) {
2086 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2088 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2089 nir_print_instr(&instr
->instr
, stderr
);
2090 fprintf(stderr
, "\n");
2094 case nir_op_ffloor
: {
2095 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2096 if (dst
.regClass() == v2b
) {
2097 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2098 } else if (dst
.regClass() == v1
) {
2099 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2100 } else if (dst
.regClass() == v2
) {
2101 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2103 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2104 nir_print_instr(&instr
->instr
, stderr
);
2105 fprintf(stderr
, "\n");
2109 case nir_op_fceil
: {
2110 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2111 if (dst
.regClass() == v2b
) {
2112 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2113 } else if (dst
.regClass() == v1
) {
2114 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2115 } else if (dst
.regClass() == v2
) {
2116 if (ctx
->options
->chip_class
>= GFX7
) {
2117 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2119 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2120 /* trunc = trunc(src0)
2121 * if (src0 > 0.0 && src0 != trunc)
2124 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2125 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2126 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2127 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2128 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2129 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2130 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2133 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2134 nir_print_instr(&instr
->instr
, stderr
);
2135 fprintf(stderr
, "\n");
2139 case nir_op_ftrunc
: {
2140 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2141 if (dst
.regClass() == v2b
) {
2142 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2143 } else if (dst
.regClass() == v1
) {
2144 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2145 } else if (dst
.regClass() == v2
) {
2146 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_fround_even
: {
2155 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (dst
.regClass() == v2b
) {
2157 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2158 } else if (dst
.regClass() == v1
) {
2159 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2160 } else if (dst
.regClass() == v2
) {
2161 if (ctx
->options
->chip_class
>= GFX7
) {
2162 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2164 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2165 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2166 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2168 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2169 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2170 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2171 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2172 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2173 tmp
= sub
->definitions
[0].getTemp();
2175 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2176 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2177 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2178 Temp cond
= vop3
->definitions
[0].getTemp();
2180 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2181 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2182 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2183 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2185 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2188 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2189 nir_print_instr(&instr
->instr
, stderr
);
2190 fprintf(stderr
, "\n");
2196 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2197 aco_ptr
<Instruction
> norm
;
2198 if (dst
.regClass() == v2b
) {
2199 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2200 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2201 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2202 bld
.vop1(opcode
, Definition(dst
), tmp
);
2203 } else if (dst
.regClass() == v1
) {
2204 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2205 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2207 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2208 if (ctx
->options
->chip_class
< GFX9
)
2209 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2211 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2212 bld
.vop1(opcode
, Definition(dst
), tmp
);
2214 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2215 nir_print_instr(&instr
->instr
, stderr
);
2216 fprintf(stderr
, "\n");
2220 case nir_op_ldexp
: {
2221 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2222 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2223 if (dst
.regClass() == v2b
) {
2224 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2225 } else if (dst
.regClass() == v1
) {
2226 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2227 } else if (dst
.regClass() == v2
) {
2228 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2230 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2231 nir_print_instr(&instr
->instr
, stderr
);
2232 fprintf(stderr
, "\n");
2236 case nir_op_frexp_sig
: {
2237 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2238 if (dst
.regClass() == v2b
) {
2239 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2240 } else if (dst
.regClass() == v1
) {
2241 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2242 } else if (dst
.regClass() == v2
) {
2243 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2246 nir_print_instr(&instr
->instr
, stderr
);
2247 fprintf(stderr
, "\n");
2251 case nir_op_frexp_exp
: {
2252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2253 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2254 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2255 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2256 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2257 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2258 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2259 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2260 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2262 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2263 nir_print_instr(&instr
->instr
, stderr
);
2264 fprintf(stderr
, "\n");
2268 case nir_op_fsign
: {
2269 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2270 if (dst
.regClass() == v2b
) {
2271 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2272 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2273 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2274 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2275 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2276 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2277 } else if (dst
.regClass() == v1
) {
2278 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2279 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2280 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2281 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2282 } else if (dst
.regClass() == v2
) {
2283 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2284 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2285 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2287 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2288 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2289 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2291 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2293 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2294 nir_print_instr(&instr
->instr
, stderr
);
2295 fprintf(stderr
, "\n");
2300 case nir_op_f2f16_rtne
: {
2301 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2302 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2303 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2304 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2305 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2306 * keep value numbering and the scheduler simpler.
2308 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2310 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2313 case nir_op_f2f16_rtz
: {
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2316 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2317 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2320 case nir_op_f2f32
: {
2321 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2322 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2323 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2324 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2326 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2327 nir_print_instr(&instr
->instr
, stderr
);
2328 fprintf(stderr
, "\n");
2332 case nir_op_f2f64
: {
2333 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2334 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2335 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2336 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2339 case nir_op_i2f16
: {
2340 assert(dst
.regClass() == v2b
);
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2343 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2344 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2345 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2346 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2349 case nir_op_i2f32
: {
2350 assert(dst
.size() == 1);
2351 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2352 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2353 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2354 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2357 case nir_op_i2f64
: {
2358 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2359 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2360 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2361 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2362 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2363 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2364 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2365 RegClass rc
= RegClass(src
.type(), 1);
2366 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2367 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2368 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2369 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2370 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2371 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2374 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2375 nir_print_instr(&instr
->instr
, stderr
);
2376 fprintf(stderr
, "\n");
2380 case nir_op_u2f16
: {
2381 assert(dst
.regClass() == v2b
);
2382 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2383 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2384 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2385 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2386 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2387 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2390 case nir_op_u2f32
: {
2391 assert(dst
.size() == 1);
2392 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2393 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2394 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2396 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2397 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2398 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2402 case nir_op_u2f64
: {
2403 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2404 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2405 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2406 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2407 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2408 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2409 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2410 RegClass rc
= RegClass(src
.type(), 1);
2411 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2412 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2413 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2414 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2415 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2416 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2418 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2419 nir_print_instr(&instr
->instr
, stderr
);
2420 fprintf(stderr
, "\n");
2425 case nir_op_f2i16
: {
2426 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2427 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2428 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2429 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2431 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2435 case nir_op_f2u16
: {
2436 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2437 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2438 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2439 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2441 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2444 case nir_op_f2i32
: {
2445 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2446 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2447 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2448 if (dst
.type() == RegType::vgpr
) {
2449 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2451 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2452 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2454 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2456 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2457 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2459 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2460 nir_print_instr(&instr
->instr
, stderr
);
2461 fprintf(stderr
, "\n");
2465 case nir_op_f2u32
: {
2466 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2467 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2468 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2469 if (dst
.type() == RegType::vgpr
) {
2470 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2472 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2473 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2475 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2476 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2477 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2478 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2480 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2481 nir_print_instr(&instr
->instr
, stderr
);
2482 fprintf(stderr
, "\n");
2486 case nir_op_f2i64
: {
2487 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2488 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2489 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2491 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2492 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2493 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2494 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2495 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2496 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2497 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2498 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2499 Temp new_exponent
= bld
.tmp(v1
);
2500 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2501 if (ctx
->program
->chip_class
>= GFX8
)
2502 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2504 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2505 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2506 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2507 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2508 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2509 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2510 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2511 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2512 Temp new_lower
= bld
.tmp(v1
);
2513 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2514 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2515 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2517 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2518 if (src
.type() == RegType::vgpr
)
2519 src
= bld
.as_uniform(src
);
2520 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2521 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2522 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2523 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2524 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2525 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2526 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2527 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2528 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2529 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2530 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2531 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2532 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2533 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2534 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2535 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2536 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2537 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2538 Temp borrow
= bld
.tmp(s1
);
2539 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2540 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2543 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2544 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2545 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2546 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2547 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2548 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2549 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2550 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2551 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2552 if (dst
.type() == RegType::sgpr
) {
2553 lower
= bld
.as_uniform(lower
);
2554 upper
= bld
.as_uniform(upper
);
2556 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2560 nir_print_instr(&instr
->instr
, stderr
);
2561 fprintf(stderr
, "\n");
2565 case nir_op_f2u64
: {
2566 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2567 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2568 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2570 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2571 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2572 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2573 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2574 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2575 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2576 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2577 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2578 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2579 Temp new_exponent
= bld
.tmp(v1
);
2580 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2581 if (ctx
->program
->chip_class
>= GFX8
)
2582 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2584 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2585 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2586 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2587 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2588 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2589 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2590 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2591 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2593 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2594 if (src
.type() == RegType::vgpr
)
2595 src
= bld
.as_uniform(src
);
2596 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2597 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2598 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2599 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2600 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2601 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2602 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2603 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2604 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2605 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2606 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2607 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2608 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2609 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2610 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2611 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2612 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2613 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2615 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2616 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2617 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2618 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2619 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2620 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2621 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2622 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2623 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2624 if (dst
.type() == RegType::sgpr
) {
2625 lower
= bld
.as_uniform(lower
);
2626 upper
= bld
.as_uniform(upper
);
2628 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2632 nir_print_instr(&instr
->instr
, stderr
);
2633 fprintf(stderr
, "\n");
2637 case nir_op_b2f16
: {
2638 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2639 assert(src
.regClass() == bld
.lm
);
2641 if (dst
.regClass() == s1
) {
2642 src
= bool_to_scalar_condition(ctx
, src
);
2643 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2644 } else if (dst
.regClass() == v2b
) {
2645 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2646 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2648 unreachable("Wrong destination register class for nir_op_b2f16.");
2652 case nir_op_b2f32
: {
2653 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2654 assert(src
.regClass() == bld
.lm
);
2656 if (dst
.regClass() == s1
) {
2657 src
= bool_to_scalar_condition(ctx
, src
);
2658 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2659 } else if (dst
.regClass() == v1
) {
2660 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2662 unreachable("Wrong destination register class for nir_op_b2f32.");
2666 case nir_op_b2f64
: {
2667 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2668 assert(src
.regClass() == bld
.lm
);
2670 if (dst
.regClass() == s2
) {
2671 src
= bool_to_scalar_condition(ctx
, src
);
2672 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2673 } else if (dst
.regClass() == v2
) {
2674 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2675 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2676 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2678 unreachable("Wrong destination register class for nir_op_b2f64.");
2685 case nir_op_i2i64
: {
2686 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2687 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2693 case nir_op_u2u64
: {
2694 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2695 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2702 case nir_op_b2i64
: {
2703 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2704 assert(src
.regClass() == bld
.lm
);
2706 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2707 if (tmp
.regClass() == s1
) {
2708 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2709 bool_to_scalar_condition(ctx
, src
, tmp
);
2710 } else if (tmp
.type() == RegType::vgpr
) {
2711 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2713 unreachable("Invalid register class for b2i32");
2717 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2722 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2723 assert(dst
.regClass() == bld
.lm
);
2725 if (src
.type() == RegType::vgpr
) {
2726 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2727 assert(dst
.regClass() == bld
.lm
);
2728 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2729 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2731 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2733 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2734 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2736 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2737 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2739 bool_to_vector_condition(ctx
, tmp
, dst
);
2743 case nir_op_pack_64_2x32_split
: {
2744 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2745 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2747 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2750 case nir_op_unpack_64_2x32_split_x
:
2751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2753 case nir_op_unpack_64_2x32_split_y
:
2754 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2756 case nir_op_unpack_32_2x16_split_x
:
2757 if (dst
.type() == RegType::vgpr
) {
2758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2760 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2763 case nir_op_unpack_32_2x16_split_y
:
2764 if (dst
.type() == RegType::vgpr
) {
2765 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2767 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2770 case nir_op_pack_32_2x16_split
: {
2771 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2772 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2773 if (dst
.regClass() == v1
) {
2774 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2775 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2778 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2779 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2780 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2784 case nir_op_pack_half_2x16
: {
2785 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2787 if (dst
.regClass() == v1
) {
2788 Temp src0
= bld
.tmp(v1
);
2789 Temp src1
= bld
.tmp(v1
);
2790 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2791 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2792 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2794 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2795 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2796 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2798 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2799 nir_print_instr(&instr
->instr
, stderr
);
2800 fprintf(stderr
, "\n");
2804 case nir_op_unpack_half_2x16_split_x
: {
2805 if (dst
.regClass() == v1
) {
2806 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2808 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2809 nir_print_instr(&instr
->instr
, stderr
);
2810 fprintf(stderr
, "\n");
2814 case nir_op_unpack_half_2x16_split_y
: {
2815 if (dst
.regClass() == v1
) {
2816 /* TODO: use SDWA here */
2817 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2818 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2820 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2821 nir_print_instr(&instr
->instr
, stderr
);
2822 fprintf(stderr
, "\n");
2826 case nir_op_fquantize2f16
: {
2827 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2828 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2831 if (ctx
->program
->chip_class
>= GFX8
) {
2832 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2833 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2834 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2836 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2837 * so compare the result and flush to 0 if it's smaller.
2839 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2840 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2841 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2842 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2843 cmp_res
= vop3
->definitions
[0].getTemp();
2846 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2847 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2848 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2850 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2855 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2856 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2858 if (dst
.regClass() == s1
) {
2859 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2860 } else if (dst
.regClass() == v1
) {
2861 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2863 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2864 nir_print_instr(&instr
->instr
, stderr
);
2865 fprintf(stderr
, "\n");
2869 case nir_op_bitfield_select
: {
2870 /* (mask & insert) | (~mask & base) */
2871 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2872 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2873 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2875 /* dst = (insert & bitmask) | (base & ~bitmask) */
2876 if (dst
.regClass() == s1
) {
2877 aco_ptr
<Instruction
> sop2
;
2878 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2879 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2881 if (const_insert
&& const_bitmask
) {
2882 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2884 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2885 lhs
= Operand(insert
);
2889 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2890 if (const_base
&& const_bitmask
) {
2891 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2893 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2894 rhs
= Operand(base
);
2897 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2899 } else if (dst
.regClass() == v1
) {
2900 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2901 base
= as_vgpr(ctx
, base
);
2902 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2903 insert
= as_vgpr(ctx
, insert
);
2905 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2909 nir_print_instr(&instr
->instr
, stderr
);
2910 fprintf(stderr
, "\n");
2916 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2917 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2918 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2920 if (dst
.type() == RegType::sgpr
) {
2922 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2923 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2924 if (const_offset
&& const_bits
) {
2925 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2926 extract
= Operand(const_extract
);
2930 width
= Operand(const_bits
->u32
<< 16);
2932 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2934 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2938 if (dst
.regClass() == s1
) {
2939 if (instr
->op
== nir_op_ubfe
)
2940 opcode
= aco_opcode::s_bfe_u32
;
2942 opcode
= aco_opcode::s_bfe_i32
;
2943 } else if (dst
.regClass() == s2
) {
2944 if (instr
->op
== nir_op_ubfe
)
2945 opcode
= aco_opcode::s_bfe_u64
;
2947 opcode
= aco_opcode::s_bfe_i64
;
2949 unreachable("Unsupported BFE bit size");
2952 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2956 if (dst
.regClass() == v1
) {
2957 if (instr
->op
== nir_op_ubfe
)
2958 opcode
= aco_opcode::v_bfe_u32
;
2960 opcode
= aco_opcode::v_bfe_i32
;
2962 unreachable("Unsupported BFE bit size");
2965 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2969 case nir_op_bit_count
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 if (src
.regClass() == s1
) {
2972 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2973 } else if (src
.regClass() == v1
) {
2974 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2975 } else if (src
.regClass() == v2
) {
2976 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2977 emit_extract_vector(ctx
, src
, 1, v1
),
2978 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2979 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2980 } else if (src
.regClass() == s2
) {
2981 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2983 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2984 nir_print_instr(&instr
->instr
, stderr
);
2985 fprintf(stderr
, "\n");
2990 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2994 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2998 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
3002 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3006 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3010 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3014 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3015 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3017 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3018 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3022 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3023 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3025 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3026 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3030 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3034 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3039 case nir_op_fddx_fine
:
3040 case nir_op_fddy_fine
:
3041 case nir_op_fddx_coarse
:
3042 case nir_op_fddy_coarse
: {
3043 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3044 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3045 if (instr
->op
== nir_op_fddx_fine
) {
3046 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3047 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3048 } else if (instr
->op
== nir_op_fddy_fine
) {
3049 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3050 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3052 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3053 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3054 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3056 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3060 if (ctx
->program
->chip_class
>= GFX8
) {
3061 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3062 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3064 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3065 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3066 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3068 emit_wqm(ctx
, tmp
, dst
, true);
3072 fprintf(stderr
, "Unknown NIR ALU instr: ");
3073 nir_print_instr(&instr
->instr
, stderr
);
3074 fprintf(stderr
, "\n");
3078 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3080 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3082 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3083 // which get truncated the lsb if double and msb if int
3084 // for now, we only use s_mov_b64 with 64bit inline constants
3085 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3086 assert(dst
.type() == RegType::sgpr
);
3088 Builder
bld(ctx
->program
, ctx
->block
);
3090 if (instr
->def
.bit_size
== 1) {
3091 assert(dst
.regClass() == bld
.lm
);
3092 int val
= instr
->value
[0].b
? -1 : 0;
3093 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3094 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3095 } else if (instr
->def
.bit_size
== 8) {
3096 /* ensure that the value is correctly represented in the low byte of the register */
3097 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3098 } else if (instr
->def
.bit_size
== 16) {
3099 /* ensure that the value is correctly represented in the low half of the register */
3100 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3101 } else if (dst
.size() == 1) {
3102 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3104 assert(dst
.size() != 1);
3105 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3106 if (instr
->def
.bit_size
== 64)
3107 for (unsigned i
= 0; i
< dst
.size(); i
++)
3108 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3110 for (unsigned i
= 0; i
< dst
.size(); i
++)
3111 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3113 vec
->definitions
[0] = Definition(dst
);
3114 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3118 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3120 uint32_t new_mask
= 0;
3121 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3122 if (mask
& (1u << i
))
3123 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3127 struct LoadEmitInfo
{
3130 unsigned num_components
;
3131 unsigned component_size
;
3132 Temp resource
= Temp(0, s1
);
3133 unsigned component_stride
= 0;
3134 unsigned const_offset
= 0;
3135 unsigned align_mul
= 0;
3136 unsigned align_offset
= 0;
3139 unsigned swizzle_component_size
= 0;
3140 barrier_interaction barrier
= barrier_none
;
3141 bool can_reorder
= true;
3142 Temp soffset
= Temp(0, s1
);
3145 using LoadCallback
= Temp(*)(
3146 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3147 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3149 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3150 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3152 unsigned load_size
= info
->num_components
* info
->component_size
;
3153 unsigned component_size
= info
->component_size
;
3155 unsigned num_vals
= 0;
3156 Temp vals
[info
->dst
.bytes()];
3158 unsigned const_offset
= info
->const_offset
;
3160 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3161 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3163 unsigned bytes_read
= 0;
3164 while (bytes_read
< load_size
) {
3165 unsigned bytes_needed
= load_size
- bytes_read
;
3167 /* add buffer for unaligned loads */
3168 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3171 if ((bytes_needed
> 2 ||
3172 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3173 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3174 if (info
->component_stride
) {
3175 assert(supports_8bit_16bit_loads
&& "unimplemented");
3179 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3180 bytes_needed
= align(bytes_needed
, 4);
3187 if (info
->swizzle_component_size
)
3188 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3189 if (info
->component_stride
)
3190 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3192 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3194 /* reduce constant offset */
3195 Operand offset
= info
->offset
;
3196 unsigned reduced_const_offset
= const_offset
;
3197 bool remove_const_offset_completely
= need_to_align_offset
;
3198 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3199 unsigned to_add
= const_offset
;
3200 if (remove_const_offset_completely
) {
3201 reduced_const_offset
= 0;
3203 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3204 reduced_const_offset
%= max_const_offset_plus_one
;
3206 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3207 if (offset
.isConstant()) {
3208 offset
= Operand(offset
.constantValue() + to_add
);
3209 } else if (offset_tmp
.regClass() == s1
) {
3210 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3211 offset_tmp
, Operand(to_add
));
3212 } else if (offset_tmp
.regClass() == v1
) {
3213 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3215 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3216 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3217 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3219 if (offset_tmp
.regClass() == s2
) {
3220 Temp carry
= bld
.tmp(s1
);
3221 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3222 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3223 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3225 Temp new_lo
= bld
.tmp(v1
);
3226 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3227 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3228 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3233 /* align offset down if needed */
3234 Operand aligned_offset
= offset
;
3235 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3236 if (need_to_align_offset
) {
3238 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3239 if (offset
.isConstant()) {
3240 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3241 } else if (offset_tmp
.regClass() == s1
) {
3242 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3243 } else if (offset_tmp
.regClass() == s2
) {
3244 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3245 } else if (offset_tmp
.regClass() == v1
) {
3246 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3247 } else if (offset_tmp
.regClass() == v2
) {
3248 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3249 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3250 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3251 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3254 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3255 bld
.copy(bld
.def(s1
), aligned_offset
);
3257 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3258 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3260 /* the callback wrote directly to dst */
3261 if (val
== info
->dst
) {
3262 assert(num_vals
== 0);
3263 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3267 /* shift result right if needed */
3268 if (info
->component_size
< 4 && byte_align_loads
) {
3269 Operand
align((uint32_t)byte_align
);
3270 if (byte_align
== -1) {
3271 if (offset
.isConstant())
3272 align
= Operand(offset
.constantValue() % 4u);
3273 else if (offset
.size() == 2)
3274 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3279 assert(val
.bytes() >= load_size
&& "unimplemented");
3280 if (val
.type() == RegType::sgpr
)
3281 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3283 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3287 /* add result to list and advance */
3288 if (info
->component_stride
) {
3289 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3290 const_offset
+= info
->component_stride
;
3291 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3293 const_offset
+= val
.bytes();
3294 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3296 bytes_read
+= val
.bytes();
3297 vals
[num_vals
++] = val
;
3300 /* create array of components */
3301 unsigned components_split
= 0;
3302 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3303 bool has_vgprs
= false;
3304 for (unsigned i
= 0; i
< num_vals
;) {
3306 unsigned num_tmps
= 0;
3307 unsigned tmp_size
= 0;
3308 RegType reg_type
= RegType::sgpr
;
3309 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3310 if (vals
[i
].type() == RegType::vgpr
)
3311 reg_type
= RegType::vgpr
;
3312 tmp_size
+= vals
[i
].bytes();
3313 tmp
[num_tmps
++] = vals
[i
++];
3316 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3317 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3318 for (unsigned i
= 0; i
< num_tmps
; i
++)
3319 vec
->operands
[i
] = Operand(tmp
[i
]);
3320 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3321 vec
->definitions
[0] = Definition(tmp
[0]);
3322 bld
.insert(std::move(vec
));
3325 if (tmp
[0].bytes() % component_size
) {
3327 assert(i
== num_vals
);
3328 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3329 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3332 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3334 unsigned start
= components_split
;
3336 if (tmp_size
== elem_rc
.bytes()) {
3337 allocated_vec
[components_split
++] = tmp
[0];
3339 assert(tmp_size
% elem_rc
.bytes() == 0);
3340 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3341 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3342 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3343 Temp component
= bld
.tmp(elem_rc
);
3344 allocated_vec
[components_split
++] = component
;
3345 split
->definitions
[i
] = Definition(component
);
3347 split
->operands
[0] = Operand(tmp
[0]);
3348 bld
.insert(std::move(split
));
3351 /* try to p_as_uniform early so we can create more optimizable code and
3352 * also update allocated_vec */
3353 for (unsigned j
= start
; j
< components_split
; j
++) {
3354 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3355 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3356 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3360 /* concatenate components and p_as_uniform() result if needed */
3361 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3362 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3364 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3366 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3367 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3368 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3369 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3371 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3372 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3373 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3374 vec
->definitions
[0] = Definition(tmp
);
3375 bld
.insert(std::move(vec
));
3376 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3378 vec
->definitions
[0] = Definition(info
->dst
);
3379 bld
.insert(std::move(vec
));
3383 Operand
load_lds_size_m0(Builder
& bld
)
3385 /* TODO: m0 does not need to be initialized on GFX9+ */
3386 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3389 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3390 Temp offset
, unsigned bytes_needed
,
3391 unsigned align
, unsigned const_offset
,
3394 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3396 Operand m
= load_lds_size_m0(bld
);
3398 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3399 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3404 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3405 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3407 op
= aco_opcode::ds_read_b128
;
3408 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3411 op
= aco_opcode::ds_read2_b64
;
3412 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3414 op
= aco_opcode::ds_read_b96
;
3415 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3417 op
= aco_opcode::ds_read_b64
;
3418 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3421 op
= aco_opcode::ds_read2_b32
;
3422 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3424 op
= aco_opcode::ds_read_b32
;
3425 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3427 op
= aco_opcode::ds_read_u16
;
3430 op
= aco_opcode::ds_read_u8
;
3433 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3434 if (const_offset
>= max_offset_plus_one
) {
3435 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3436 const_offset
%= max_offset_plus_one
;
3440 const_offset
/= (size
/ 2u);
3442 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3443 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3445 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3447 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3450 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3455 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3457 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3458 Temp offset
, unsigned bytes_needed
,
3459 unsigned align
, unsigned const_offset
,
3464 if (bytes_needed
<= 4) {
3466 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3467 } else if (bytes_needed
<= 8) {
3469 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3470 } else if (bytes_needed
<= 16) {
3472 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3473 } else if (bytes_needed
<= 32) {
3475 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3478 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3480 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3481 if (info
->resource
.id()) {
3482 load
->operands
[0] = Operand(info
->resource
);
3483 load
->operands
[1] = Operand(offset
);
3485 load
->operands
[0] = Operand(offset
);
3486 load
->operands
[1] = Operand(0u);
3488 RegClass
rc(RegType::sgpr
, size
);
3489 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3490 load
->definitions
[0] = Definition(val
);
3491 load
->glc
= info
->glc
;
3492 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3493 load
->barrier
= info
->barrier
;
3494 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3495 bld
.insert(std::move(load
));
3499 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3501 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3502 Temp offset
, unsigned bytes_needed
,
3503 unsigned align_
, unsigned const_offset
,
3506 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3507 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3509 if (info
->soffset
.id()) {
3510 if (soffset
.isTemp())
3511 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3512 soffset
= Operand(info
->soffset
);
3515 unsigned bytes_size
= 0;
3517 if (bytes_needed
== 1 || align_
% 2) {
3519 op
= aco_opcode::buffer_load_ubyte
;
3520 } else if (bytes_needed
== 2 || align_
% 4) {
3522 op
= aco_opcode::buffer_load_ushort
;
3523 } else if (bytes_needed
<= 4) {
3525 op
= aco_opcode::buffer_load_dword
;
3526 } else if (bytes_needed
<= 8) {
3528 op
= aco_opcode::buffer_load_dwordx2
;
3529 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3531 op
= aco_opcode::buffer_load_dwordx3
;
3534 op
= aco_opcode::buffer_load_dwordx4
;
3536 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3537 mubuf
->operands
[0] = Operand(info
->resource
);
3538 mubuf
->operands
[1] = vaddr
;
3539 mubuf
->operands
[2] = soffset
;
3540 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3541 mubuf
->glc
= info
->glc
;
3542 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3543 mubuf
->barrier
= info
->barrier
;
3544 mubuf
->can_reorder
= info
->can_reorder
;
3545 mubuf
->offset
= const_offset
;
3546 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3547 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3548 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3549 mubuf
->definitions
[0] = Definition(val
);
3550 bld
.insert(std::move(mubuf
));
3555 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3556 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3558 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3560 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3561 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3563 if (addr
.type() == RegType::vgpr
)
3564 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3565 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3568 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3569 Temp offset
, unsigned bytes_needed
,
3570 unsigned align_
, unsigned const_offset
,
3573 unsigned bytes_size
= 0;
3574 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3575 bool global
= bld
.program
->chip_class
>= GFX9
;
3577 if (bytes_needed
== 1) {
3579 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3580 } else if (bytes_needed
== 2) {
3582 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3583 } else if (bytes_needed
<= 4) {
3585 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3586 } else if (bytes_needed
<= 8) {
3588 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3589 } else if (bytes_needed
<= 12 && !mubuf
) {
3591 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3594 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3596 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3597 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3599 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3600 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3601 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3602 mubuf
->operands
[2] = Operand(0u);
3603 mubuf
->glc
= info
->glc
;
3606 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3607 mubuf
->disable_wqm
= false;
3608 mubuf
->barrier
= info
->barrier
;
3609 mubuf
->definitions
[0] = Definition(val
);
3610 bld
.insert(std::move(mubuf
));
3612 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3614 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3615 flat
->operands
[0] = Operand(offset
);
3616 flat
->operands
[1] = Operand(s1
);
3617 flat
->glc
= info
->glc
;
3618 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3619 flat
->barrier
= info
->barrier
;
3621 flat
->definitions
[0] = Definition(val
);
3622 bld
.insert(std::move(flat
));
3628 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3630 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3631 Temp address
, unsigned base_offset
, unsigned align
)
3633 assert(util_is_power_of_two_nonzero(align
));
3635 Builder
bld(ctx
->program
, ctx
->block
);
3637 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3638 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3639 info
.align_mul
= align
;
3640 info
.align_offset
= 0;
3641 info
.barrier
= barrier_shared
;
3642 info
.can_reorder
= false;
3643 info
.const_offset
= base_offset
;
3644 emit_lds_load(ctx
, bld
, &info
);
3649 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3654 Builder
bld(ctx
->program
, ctx
->block
);
3656 ASSERTED
bool is_subdword
= false;
3657 for (unsigned i
= 0; i
< count
; i
++)
3658 is_subdword
|= offsets
[i
] % 4;
3659 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3660 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3662 /* count == 1 fast path */
3664 if (dst_type
== RegType::sgpr
)
3665 dst
[0] = bld
.as_uniform(src
);
3667 dst
[0] = as_vgpr(ctx
, src
);
3671 for (unsigned i
= 0; i
< count
- 1; i
++)
3672 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3673 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3675 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3676 src
= as_vgpr(ctx
, src
);
3678 /* use allocated_vec if possible */
3679 auto it
= ctx
->allocated_vec
.find(src
.id());
3680 if (it
!= ctx
->allocated_vec
.end()) {
3681 if (!it
->second
[0].id())
3683 unsigned elem_size
= it
->second
[0].bytes();
3684 assert(src
.bytes() % elem_size
== 0);
3686 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3687 if (!it
->second
[i
].id())
3691 for (unsigned i
= 0; i
< count
; i
++) {
3692 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3696 for (unsigned i
= 0; i
< count
; i
++) {
3697 unsigned start_idx
= offsets
[i
] / elem_size
;
3698 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3699 if (op_count
== 1) {
3700 if (dst_type
== RegType::sgpr
)
3701 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3703 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3707 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3708 for (unsigned j
= 0; j
< op_count
; j
++) {
3709 Temp tmp
= it
->second
[start_idx
+ j
];
3710 if (dst_type
== RegType::sgpr
)
3711 tmp
= bld
.as_uniform(tmp
);
3712 vec
->operands
[j
] = Operand(tmp
);
3714 vec
->definitions
[0] = Definition(dst
[i
]);
3715 bld
.insert(std::move(vec
));
3723 if (dst_type
== RegType::sgpr
)
3724 src
= bld
.as_uniform(src
);
3727 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3728 split
->operands
[0] = Operand(src
);
3729 for (unsigned i
= 0; i
< count
; i
++)
3730 split
->definitions
[i
] = Definition(dst
[i
]);
3731 bld
.insert(std::move(split
));
3734 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3735 int *start
, int *count
)
3737 unsigned start_elem
= ffs(todo_mask
) - 1;
3738 bool skip
= !(mask
& (1 << start_elem
));
3740 mask
= ~mask
& todo_mask
;
3744 u_bit_scan_consecutive_range(&mask
, start
, count
);
3749 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3751 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3754 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3755 Temp address
, unsigned base_offset
, unsigned align
)
3757 assert(util_is_power_of_two_nonzero(align
));
3758 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3760 Builder
bld(ctx
->program
, ctx
->block
);
3761 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3762 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3764 unsigned write_count
= 0;
3765 Temp write_datas
[32];
3766 unsigned offsets
[32];
3767 aco_opcode opcodes
[32];
3769 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3771 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3774 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3775 offsets
[write_count
] = offset
;
3776 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3778 advance_write_mask(&todo
, offset
, bytes
);
3782 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3783 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3784 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3785 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3787 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3788 aco_opcode op
= aco_opcode::num_opcodes
;
3789 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3790 op
= aco_opcode::ds_write_b128
;
3792 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3793 op
= aco_opcode::ds_write_b96
;
3795 } else if (bytes
>= 8 && aligned8
) {
3796 op
= aco_opcode::ds_write_b64
;
3798 } else if (bytes
>= 4 && aligned4
) {
3799 op
= aco_opcode::ds_write_b32
;
3801 } else if (bytes
>= 2 && aligned2
) {
3802 op
= aco_opcode::ds_write_b16
;
3804 } else if (bytes
>= 1) {
3805 op
= aco_opcode::ds_write_b8
;
3811 offsets
[write_count
] = offset
;
3812 opcodes
[write_count
] = op
;
3814 advance_write_mask(&todo
, offset
, bytes
);
3817 Operand m
= load_lds_size_m0(bld
);
3819 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3821 for (unsigned i
= 0; i
< write_count
; i
++) {
3822 aco_opcode op
= opcodes
[i
];
3823 if (op
== aco_opcode::num_opcodes
)
3826 Temp data
= write_datas
[i
];
3828 unsigned second
= write_count
;
3829 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3830 for (second
= i
+ 1; second
< write_count
; second
++) {
3831 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3832 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3833 opcodes
[second
] = aco_opcode::num_opcodes
;
3839 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3840 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3842 unsigned inline_offset
= base_offset
+ offsets
[i
];
3843 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3844 Temp address_offset
= address
;
3845 if (inline_offset
> max_offset
) {
3846 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3847 inline_offset
= offsets
[i
];
3849 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3852 Temp second_data
= write_datas
[second
];
3853 inline_offset
/= data
.bytes();
3854 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3856 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3861 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3863 unsigned align
= 16;
3865 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3871 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3876 return aco_opcode::buffer_store_byte
;
3879 return aco_opcode::buffer_store_short
;
3881 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3883 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3886 return aco_opcode::buffer_store_dwordx3
;
3888 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3890 unreachable("Unexpected store size");
3891 return aco_opcode::num_opcodes
;
3894 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3895 Temp data
, unsigned writemask
, int swizzle_element_size
,
3896 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3898 unsigned write_count_with_skips
= 0;
3901 /* determine how to split the data */
3902 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3905 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3906 offsets
[write_count_with_skips
] = offset
;
3907 if (skips
[write_count_with_skips
]) {
3908 advance_write_mask(&todo
, offset
, bytes
);
3909 write_count_with_skips
++;
3913 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3914 * larger than swizzle_element_size */
3915 bytes
= MIN2(bytes
, swizzle_element_size
);
3917 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3919 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3920 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3923 /* dword or larger stores have to be dword-aligned */
3924 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3925 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3926 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3928 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3930 advance_write_mask(&todo
, offset
, bytes
);
3931 write_count_with_skips
++;
3934 /* actually split data */
3935 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3938 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3941 write_datas
[*write_count
] = write_datas
[i
];
3942 offsets
[*write_count
] = offsets
[i
];
3947 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3948 unsigned split_cnt
= 0u, Temp dst
= Temp())
3950 Builder
bld(ctx
->program
, ctx
->block
);
3951 unsigned dword_size
= elem_size_bytes
/ 4;
3954 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3956 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3957 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3958 instr
->definitions
[0] = Definition(dst
);
3960 for (unsigned i
= 0; i
< cnt
; ++i
) {
3962 assert(arr
[i
].size() == dword_size
);
3963 allocated_vec
[i
] = arr
[i
];
3964 instr
->operands
[i
] = Operand(arr
[i
]);
3966 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3967 allocated_vec
[i
] = zero
;
3968 instr
->operands
[i
] = Operand(zero
);
3972 bld
.insert(std::move(instr
));
3975 emit_split_vector(ctx
, dst
, split_cnt
);
3977 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3982 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3984 if (const_offset
>= 4096) {
3985 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3986 const_offset
%= 4096u;
3989 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3990 else if (unlikely(voffset
.regClass() == s1
))
3991 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3992 else if (likely(voffset
.regClass() == v1
))
3993 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3995 unreachable("Unsupported register class of voffset");
3998 return const_offset
;
4001 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
4002 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false,
4003 bool swizzled
= false)
4006 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
4007 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
4009 Builder
bld(ctx
->program
, ctx
->block
);
4010 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
4011 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
4013 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
4014 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
4015 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
4016 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
4017 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
4018 /* dlc*/ false, /* slc */ slc
);
4020 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
4023 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
4024 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
4025 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
4027 Builder
bld(ctx
->program
, ctx
->block
);
4028 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4030 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
4032 unsigned write_count
= 0;
4033 Temp write_datas
[32];
4034 unsigned offsets
[32];
4035 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
4036 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4038 for (unsigned i
= 0; i
< write_count
; i
++) {
4039 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4040 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
, !allow_combining
);
4044 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4045 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4046 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4048 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4049 assert((num_components
* elem_size_bytes
) == dst
.bytes());
4050 assert(!!stride
!= allow_combining
);
4052 Builder
bld(ctx
->program
, ctx
->block
);
4054 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4055 info
.component_stride
= allow_combining
? 0 : stride
;
4057 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4058 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4059 info
.align_offset
= 0;
4060 info
.soffset
= soffset
;
4061 info
.const_offset
= base_const_offset
;
4062 emit_mubuf_load(ctx
, bld
, &info
);
4065 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4067 Builder
bld(ctx
->program
, ctx
->block
);
4068 Temp offset
= base_offset
.first
;
4069 unsigned const_offset
= base_offset
.second
;
4071 if (!nir_src_is_const(*off_src
)) {
4072 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4075 /* Calculate indirect offset with stride */
4076 if (likely(indirect_offset_arg
.regClass() == v1
))
4077 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4078 else if (indirect_offset_arg
.regClass() == s1
)
4079 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4081 unreachable("Unsupported register class of indirect offset");
4083 /* Add to the supplied base offset */
4084 if (offset
.id() == 0)
4085 offset
= with_stride
;
4086 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4087 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4088 else if (offset
.size() == 1 && with_stride
.size() == 1)
4089 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4091 unreachable("Unsupported register class of indirect offset");
4093 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4094 const_offset
+= const_offset_arg
* stride
;
4097 return std::make_pair(offset
, const_offset
);
4100 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4102 Builder
bld(ctx
->program
, ctx
->block
);
4105 if (off1
.first
.id() && off2
.first
.id()) {
4106 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4107 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4108 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4109 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4111 unreachable("Unsupported register class of indirect offset");
4113 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4116 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4119 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4121 Builder
bld(ctx
->program
, ctx
->block
);
4122 unsigned const_offset
= offs
.second
* multiplier
;
4124 if (!offs
.first
.id())
4125 return std::make_pair(offs
.first
, const_offset
);
4127 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4128 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4129 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4131 return std::make_pair(offset
, const_offset
);
4134 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4136 Builder
bld(ctx
->program
, ctx
->block
);
4138 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4139 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4140 /* component is in bytes */
4141 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4143 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4144 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4145 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4148 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4150 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4153 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4155 Builder
bld(ctx
->program
, ctx
->block
);
4157 switch (ctx
->shader
->info
.stage
) {
4158 case MESA_SHADER_TESS_CTRL
:
4159 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4160 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4161 case MESA_SHADER_TESS_EVAL
:
4162 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4164 unreachable("Unsupported stage in get_tess_rel_patch_id");
4168 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4170 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4171 Builder
bld(ctx
->program
, ctx
->block
);
4173 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4174 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4176 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4178 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4179 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4181 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4182 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4183 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4185 return offset_mul(ctx
, offs
, 4u);
4188 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4190 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4191 Builder
bld(ctx
->program
, ctx
->block
);
4193 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4194 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4195 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4196 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4198 std::pair
<Temp
, unsigned> offs
= instr
4199 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4200 : std::make_pair(Temp(), 0u);
4202 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4203 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4208 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4209 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4211 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4212 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4214 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4215 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4221 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4223 Builder
bld(ctx
->program
, ctx
->block
);
4225 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4226 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4228 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4230 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4231 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4232 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4234 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4235 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4240 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4242 Builder
bld(ctx
->program
, ctx
->block
);
4244 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4245 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4246 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4247 unsigned attr_stride
= ctx
->tcs_num_patches
;
4249 std::pair
<Temp
, unsigned> offs
= instr
4250 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4251 : std::make_pair(Temp(), 0u);
4253 if (const_base_offset
)
4254 offs
.second
+= const_base_offset
* attr_stride
;
4256 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4257 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4258 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4263 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4265 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4270 unsigned drv_loc
= nir_intrinsic_base(instr
);
4271 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4273 if (!nir_src_is_const(*off_src
)) {
4279 uint64_t slot
= per_vertex
4280 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4281 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4282 return (((uint64_t) 1) << slot
) & mask
;
4285 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4287 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4288 unsigned component
= nir_intrinsic_component(instr
);
4289 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4291 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4292 if (off_instr
->type
!= nir_instr_type_load_const
)
4295 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4296 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4298 if (instr
->src
[0].ssa
->bit_size
== 64)
4299 write_mask
= widen_mask(write_mask
, 2);
4301 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4303 for (unsigned i
= 0; i
< 8; ++i
) {
4304 if (write_mask
& (1 << i
)) {
4305 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4306 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4314 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4316 /* Only TCS per-vertex inputs are supported by this function.
4317 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4319 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4322 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4323 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4324 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4325 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4326 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4327 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4332 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4333 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4334 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4339 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4341 Builder
bld(ctx
->program
, ctx
->block
);
4343 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4344 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4345 bool indirect_write
;
4346 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4347 if (temp_only_input
&& !indirect_write
)
4351 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4352 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4353 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4354 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4356 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4357 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4358 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4359 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4360 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4364 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4365 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4366 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4367 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4368 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4369 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4370 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4371 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4372 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4373 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4374 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4375 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4376 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4378 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4379 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4381 unreachable("Invalid LS or ES stage");
4384 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4385 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4386 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4390 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4395 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4396 return off
== ctx
->tcs_tess_lvl_out_loc
||
4397 off
== ctx
->tcs_tess_lvl_in_loc
;
4401 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4403 uint64_t mask
= per_vertex
4404 ? ctx
->program
->info
->tcs
.tes_inputs_read
4405 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4407 bool indirect_write
= false;
4408 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4409 return indirect_write
|| output_read_by_tes
;
4412 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4414 uint64_t mask
= per_vertex
4415 ? ctx
->shader
->info
.outputs_read
4416 : ctx
->shader
->info
.patch_outputs_read
;
4418 bool indirect_write
= false;
4419 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4420 return indirect_write
|| output_read
;
4423 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4425 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4426 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4428 Builder
bld(ctx
->program
, ctx
->block
);
4430 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4431 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4432 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4434 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4435 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4436 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4438 if (write_to_vmem
) {
4439 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4440 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4441 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4443 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4444 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4445 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4449 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4450 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4451 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4455 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4457 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4458 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4460 Builder
bld(ctx
->program
, ctx
->block
);
4462 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4463 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4464 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4465 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4467 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4470 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4472 if (ctx
->stage
== vertex_vs
||
4473 ctx
->stage
== tess_eval_vs
||
4474 ctx
->stage
== fragment_fs
||
4475 ctx
->stage
== ngg_vertex_gs
||
4476 ctx
->stage
== ngg_tess_eval_gs
||
4477 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4478 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4479 if (!stored_to_temps
) {
4480 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4481 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4482 fprintf(stderr
, "\n");
4485 } else if (ctx
->stage
== vertex_es
||
4486 ctx
->stage
== vertex_ls
||
4487 ctx
->stage
== tess_eval_es
||
4488 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4489 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4490 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4491 visit_store_ls_or_es_output(ctx
, instr
);
4492 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4493 visit_store_tcs_output(ctx
, instr
, false);
4495 unreachable("Shader stage not implemented");
4499 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4501 visit_load_tcs_output(ctx
, instr
, false);
4504 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4506 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4507 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4509 Builder
bld(ctx
->program
, ctx
->block
);
4511 if (dst
.regClass() == v2b
) {
4512 if (ctx
->program
->has_16bank_lds
) {
4513 assert(ctx
->options
->chip_class
<= GFX8
);
4514 Builder::Result interp_p1
=
4515 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4516 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4517 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4518 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4519 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4520 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4522 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4524 if (ctx
->options
->chip_class
== GFX8
)
4525 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4527 Builder::Result interp_p1
=
4528 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4529 coord1
, bld
.m0(prim_mask
), idx
, component
);
4530 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4531 interp_p1
, idx
, component
);
4534 Builder::Result interp_p1
=
4535 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4536 bld
.m0(prim_mask
), idx
, component
);
4538 if (ctx
->program
->has_16bank_lds
)
4539 interp_p1
.instr
->operands
[0].setLateKill(true);
4541 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4542 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4546 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4548 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4549 for (unsigned i
= 0; i
< num_components
; i
++)
4550 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4551 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4552 assert(num_components
== 4);
4553 Builder
bld(ctx
->program
, ctx
->block
);
4554 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4557 for (Operand
& op
: vec
->operands
)
4558 op
= op
.isUndefined() ? Operand(0u) : op
;
4560 vec
->definitions
[0] = Definition(dst
);
4561 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4562 emit_split_vector(ctx
, dst
, num_components
);
4566 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4568 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4569 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4570 unsigned idx
= nir_intrinsic_base(instr
);
4571 unsigned component
= nir_intrinsic_component(instr
);
4572 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4574 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4576 assert(offset
->u32
== 0);
4578 /* the lower 15bit of the prim_mask contain the offset into LDS
4579 * while the upper bits contain the number of prims */
4580 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4581 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4582 Builder
bld(ctx
->program
, ctx
->block
);
4583 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4584 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4585 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4586 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4587 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4590 if (instr
->dest
.ssa
.num_components
== 1) {
4591 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4593 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4594 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4596 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4597 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4598 vec
->operands
[i
] = Operand(tmp
);
4600 vec
->definitions
[0] = Definition(dst
);
4601 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4605 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4606 unsigned offset
, unsigned stride
, unsigned channels
)
4608 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4609 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4611 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4612 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4615 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4616 unsigned offset
, unsigned stride
, unsigned *channels
)
4618 if (!vtx_info
->chan_byte_size
) {
4619 *channels
= vtx_info
->num_channels
;
4620 return vtx_info
->chan_format
;
4623 unsigned num_channels
= *channels
;
4624 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4625 unsigned new_channels
= num_channels
+ 1;
4626 /* first, assume more loads is worse and try using a larger data format */
4627 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4629 /* don't make the attribute potentially out-of-bounds */
4630 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4634 if (new_channels
== 5) {
4635 /* then try decreasing load size (at the cost of more loads) */
4636 new_channels
= *channels
;
4637 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4641 if (new_channels
< *channels
)
4642 *channels
= new_channels
;
4643 num_channels
= new_channels
;
4646 switch (vtx_info
->chan_format
) {
4647 case V_008F0C_BUF_DATA_FORMAT_8
:
4648 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4649 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4650 case V_008F0C_BUF_DATA_FORMAT_16
:
4651 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4652 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4653 case V_008F0C_BUF_DATA_FORMAT_32
:
4654 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4655 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4657 unreachable("shouldn't reach here");
4658 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4661 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4662 * so we may need to fix it up. */
4663 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4665 Builder
bld(ctx
->program
, ctx
->block
);
4667 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4668 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4670 /* For the integer-like cases, do a natural sign extension.
4672 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4673 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4676 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4677 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4679 /* Convert back to the right type. */
4680 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4681 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4682 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4683 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4684 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4685 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4691 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4693 Builder
bld(ctx
->program
, ctx
->block
);
4694 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4695 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4697 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4698 if (off_instr
->type
!= nir_instr_type_load_const
) {
4699 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4700 nir_print_instr(off_instr
, stderr
);
4701 fprintf(stderr
, "\n");
4703 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4705 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4707 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4708 unsigned component
= nir_intrinsic_component(instr
);
4709 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4710 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4711 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4712 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4713 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4715 unsigned dfmt
= attrib_format
& 0xf;
4716 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4717 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4719 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4720 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4721 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4722 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4724 num_channels
= MAX2(num_channels
, 3);
4726 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4727 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4730 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4731 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4732 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4734 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4736 Temp divided
= bld
.tmp(v1
);
4737 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4738 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4740 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4743 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4746 index
= bld
.vadd32(bld
.def(v1
),
4747 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4748 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4751 Temp channels
[num_channels
];
4752 unsigned channel_start
= 0;
4753 bool direct_fetch
= false;
4755 /* skip unused channels at the start */
4756 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4757 channel_start
= ffs(mask
) - 1;
4758 for (unsigned i
= 0; i
< channel_start
; i
++)
4759 channels
[i
] = Temp(0, s1
);
4760 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4761 num_channels
= 3 - (ffs(mask
) - 1);
4765 while (channel_start
< num_channels
) {
4766 unsigned fetch_component
= num_channels
- channel_start
;
4767 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4768 bool expanded
= false;
4770 /* use MUBUF when possible to avoid possible alignment issues */
4771 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4772 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4773 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4774 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4775 vtx_info
->chan_byte_size
== 4;
4776 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4778 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4780 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4781 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4782 fetch_component
= 4;
4787 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4789 Temp fetch_index
= index
;
4790 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4791 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4792 fetch_offset
= fetch_offset
% attrib_stride
;
4795 Operand
soffset(0u);
4796 if (fetch_offset
>= 4096) {
4797 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4798 fetch_offset
%= 4096;
4802 switch (fetch_bytes
) {
4804 assert(!use_mubuf
&& bitsize
== 16);
4805 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4808 if (bitsize
== 16) {
4810 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4812 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4816 assert(!use_mubuf
&& bitsize
== 16);
4817 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4820 if (bitsize
== 16) {
4822 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4824 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4828 assert(ctx
->options
->chip_class
>= GFX7
||
4829 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4830 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4833 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4836 unreachable("Unimplemented load_input vector size");
4840 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4841 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4842 num_channels
<= 3)) {
4843 direct_fetch
= true;
4846 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4850 Instruction
*mubuf
= bld
.mubuf(opcode
,
4851 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4852 fetch_offset
, false, false, true).instr
;
4853 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4855 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4856 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4857 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4858 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4861 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4863 if (fetch_component
== 1) {
4864 channels
[channel_start
] = fetch_dst
;
4866 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4867 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4868 bitsize
== 16 ? v2b
: v1
);
4871 channel_start
+= fetch_component
;
4874 if (!direct_fetch
) {
4875 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4876 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4878 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4879 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4880 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4882 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4883 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4884 unsigned num_temp
= 0;
4885 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4886 unsigned idx
= i
+ component
;
4887 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4888 Temp channel
= channels
[swizzle
[idx
]];
4889 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4890 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4891 vec
->operands
[i
] = Operand(channel
);
4895 } else if (is_float
&& idx
== 3) {
4896 vec
->operands
[i
] = Operand(0x3f800000u
);
4897 } else if (!is_float
&& idx
== 3) {
4898 vec
->operands
[i
] = Operand(1u);
4900 vec
->operands
[i
] = Operand(0u);
4903 vec
->definitions
[0] = Definition(dst
);
4904 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4905 emit_split_vector(ctx
, dst
, dst
.size());
4907 if (num_temp
== dst
.size())
4908 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4910 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4911 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4912 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4913 if (off_instr
->type
!= nir_instr_type_load_const
||
4914 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4915 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4916 nir_print_instr(off_instr
, stderr
);
4917 fprintf(stderr
, "\n");
4920 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4921 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4923 assert(offset
->u32
== 0);
4925 /* the lower 15bit of the prim_mask contain the offset into LDS
4926 * while the upper bits contain the number of prims */
4927 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4928 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4929 Builder
bld(ctx
->program
, ctx
->block
);
4930 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4931 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4932 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4933 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4934 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4937 unsigned idx
= nir_intrinsic_base(instr
);
4938 unsigned component
= nir_intrinsic_component(instr
);
4939 unsigned vertex_id
= 2; /* P0 */
4941 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4942 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4943 switch (src0
->u32
) {
4945 vertex_id
= 2; /* P0 */
4948 vertex_id
= 0; /* P10 */
4951 vertex_id
= 1; /* P20 */
4954 unreachable("invalid vertex index");
4958 if (dst
.size() == 1) {
4959 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4961 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4962 for (unsigned i
= 0; i
< dst
.size(); i
++)
4963 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4964 vec
->definitions
[0] = Definition(dst
);
4965 bld
.insert(std::move(vec
));
4968 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4969 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4970 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4971 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4972 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4974 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4976 unreachable("Shader stage not implemented");
4980 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4982 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4984 Builder
bld(ctx
->program
, ctx
->block
);
4985 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4988 if (!nir_src_is_const(*vertex_src
)) {
4989 /* better code could be created, but this case probably doesn't happen
4990 * much in practice */
4991 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4992 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4995 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4996 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4998 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
5000 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
5003 if (vertex_offset
.id()) {
5004 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
5005 Operand(i
), indirect_vertex
);
5006 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
5008 vertex_offset
= elem
;
5012 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5013 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
5015 unsigned vertex
= nir_src_as_uint(*vertex_src
);
5016 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5017 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5018 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
5019 Operand((vertex
% 2u) * 16u), Operand(16u));
5021 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
5024 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
5025 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
5026 return offset_mul(ctx
, offs
, 4u);
5029 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5031 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5033 Builder
bld(ctx
->program
, ctx
->block
);
5034 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5035 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5037 if (ctx
->stage
== geometry_gs
) {
5038 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
5039 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
5040 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
5041 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5042 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
5043 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5044 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5046 unreachable("Unsupported GS stage.");
5050 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5052 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5054 Builder
bld(ctx
->program
, ctx
->block
);
5055 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5057 if (load_input_from_temps(ctx
, instr
, dst
))
5060 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5061 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5062 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5064 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5067 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5069 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5071 Builder
bld(ctx
->program
, ctx
->block
);
5073 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5074 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5075 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5077 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5078 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5080 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5083 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5085 switch (ctx
->shader
->info
.stage
) {
5086 case MESA_SHADER_GEOMETRY
:
5087 visit_load_gs_per_vertex_input(ctx
, instr
);
5089 case MESA_SHADER_TESS_CTRL
:
5090 visit_load_tcs_per_vertex_input(ctx
, instr
);
5092 case MESA_SHADER_TESS_EVAL
:
5093 visit_load_tes_per_vertex_input(ctx
, instr
);
5096 unreachable("Unimplemented shader stage");
5100 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5102 visit_load_tcs_output(ctx
, instr
, true);
5105 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5107 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5108 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5110 visit_store_tcs_output(ctx
, instr
, true);
5113 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5115 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5117 Builder
bld(ctx
->program
, ctx
->block
);
5118 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5120 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5121 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5124 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5125 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5126 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5127 tes_w
= Operand(tmp
);
5130 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5131 emit_split_vector(ctx
, tess_coord
, 3);
5134 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5136 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5137 Builder
bld(ctx
->program
, ctx
->block
);
5138 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5139 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5140 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5143 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5147 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5149 Builder
bld(ctx
->program
, ctx
->block
);
5150 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5151 if (!nir_dest_is_divergent(instr
->dest
))
5152 index
= bld
.as_uniform(index
);
5153 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5154 unsigned binding
= nir_intrinsic_binding(instr
);
5157 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5158 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5159 unsigned offset
= layout
->binding
[binding
].offset
;
5161 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5162 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5163 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5164 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5165 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5168 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5169 stride
= layout
->binding
[binding
].size
;
5172 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5173 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5175 if (nir_const_index
) {
5176 const_index
= const_index
* stride
;
5177 } else if (index
.type() == RegType::vgpr
) {
5178 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5179 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5181 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5185 if (nir_const_index
) {
5186 const_index
= const_index
+ offset
;
5187 } else if (index
.type() == RegType::vgpr
) {
5188 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5190 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5194 if (nir_const_index
&& const_index
== 0) {
5196 } else if (index
.type() == RegType::vgpr
) {
5197 index
= bld
.vadd32(bld
.def(v1
),
5198 nir_const_index
? Operand(const_index
) : Operand(index
),
5201 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5202 nir_const_index
? Operand(const_index
) : Operand(index
),
5206 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5209 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5210 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5211 bool glc
=false, bool readonly
=true, bool allow_smem
=true)
5213 Builder
bld(ctx
->program
, ctx
->block
);
5215 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5217 offset
= bld
.as_uniform(offset
);
5219 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5221 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5222 info
.can_reorder
= readonly
;
5223 info
.align_mul
= align_mul
;
5224 info
.align_offset
= align_offset
;
5226 emit_smem_load(ctx
, bld
, &info
);
5228 emit_mubuf_load(ctx
, bld
, &info
);
5231 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5233 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5234 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5236 Builder
bld(ctx
->program
, ctx
->block
);
5238 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5239 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5240 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5241 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5243 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5244 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5245 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5246 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5247 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5248 if (ctx
->options
->chip_class
>= GFX10
) {
5249 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5250 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5251 S_008F0C_RESOURCE_LEVEL(1);
5253 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5254 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5256 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5257 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5258 Operand(0xFFFFFFFFu
),
5259 Operand(desc_type
));
5260 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5261 rsrc
, upper_dwords
);
5263 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5264 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5266 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5267 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5268 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5271 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5273 Builder
bld(ctx
->program
, ctx
->block
);
5274 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5275 unsigned offset
= nir_intrinsic_base(instr
);
5276 unsigned count
= instr
->dest
.ssa
.num_components
;
5277 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5279 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5280 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5281 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5282 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5283 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5284 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5285 for (unsigned i
= 0; i
< count
; ++i
) {
5286 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5287 vec
->operands
[i
] = Operand
{elems
[i
]};
5289 vec
->definitions
[0] = Definition(dst
);
5290 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5291 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5296 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5297 if (offset
!= 0) // TODO check if index != 0 as well
5298 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5299 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5302 bool aligned
= true;
5304 if (instr
->dest
.ssa
.bit_size
== 8) {
5305 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5306 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5308 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5309 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5310 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5312 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5317 switch (vec
.size()) {
5319 op
= aco_opcode::s_load_dword
;
5322 op
= aco_opcode::s_load_dwordx2
;
5328 op
= aco_opcode::s_load_dwordx4
;
5334 op
= aco_opcode::s_load_dwordx8
;
5337 unreachable("unimplemented or forbidden load_push_constant.");
5340 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5343 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5344 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5349 emit_split_vector(ctx
, vec
, 4);
5350 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5351 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5352 emit_extract_vector(ctx
, vec
, 0, rc
),
5353 emit_extract_vector(ctx
, vec
, 1, rc
),
5354 emit_extract_vector(ctx
, vec
, 2, rc
));
5357 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5360 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5362 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5364 Builder
bld(ctx
->program
, ctx
->block
);
5366 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5367 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5368 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5369 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5370 if (ctx
->options
->chip_class
>= GFX10
) {
5371 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5372 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5373 S_008F0C_RESOURCE_LEVEL(1);
5375 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5376 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5379 unsigned base
= nir_intrinsic_base(instr
);
5380 unsigned range
= nir_intrinsic_range(instr
);
5382 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5383 if (base
&& offset
.type() == RegType::sgpr
)
5384 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5385 else if (base
&& offset
.type() == RegType::vgpr
)
5386 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5388 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5389 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5390 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5391 Operand(desc_type
));
5392 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5393 // TODO: get alignment information for subdword constants
5394 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5397 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5399 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5400 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5402 ctx
->program
->needs_exact
= true;
5404 // TODO: optimize uniform conditions
5405 Builder
bld(ctx
->program
, ctx
->block
);
5406 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5407 assert(src
.regClass() == bld
.lm
);
5408 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5409 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5410 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5414 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5416 Builder
bld(ctx
->program
, ctx
->block
);
5418 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5419 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5421 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5422 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5424 if (ctx
->block
->loop_nest_depth
&&
5425 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5426 /* we handle discards the same way as jump instructions */
5427 append_logical_end(ctx
->block
);
5429 /* in loops, discard behaves like break */
5430 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5431 ctx
->block
->kind
|= block_kind_discard
;
5434 /* uniform discard - loop ends here */
5435 assert(nir_instr_is_last(&instr
->instr
));
5436 ctx
->block
->kind
|= block_kind_uniform
;
5437 ctx
->cf_info
.has_branch
= true;
5438 bld
.branch(aco_opcode::p_branch
);
5439 add_linear_edge(ctx
->block
->index
, linear_target
);
5443 /* we add a break right behind the discard() instructions */
5444 ctx
->block
->kind
|= block_kind_break
;
5445 unsigned idx
= ctx
->block
->index
;
5447 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5448 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5450 /* remove critical edges from linear CFG */
5451 bld
.branch(aco_opcode::p_branch
);
5452 Block
* break_block
= ctx
->program
->create_and_insert_block();
5453 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5454 break_block
->kind
|= block_kind_uniform
;
5455 add_linear_edge(idx
, break_block
);
5456 add_linear_edge(break_block
->index
, linear_target
);
5457 bld
.reset(break_block
);
5458 bld
.branch(aco_opcode::p_branch
);
5460 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5461 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5462 add_linear_edge(idx
, continue_block
);
5463 append_logical_start(continue_block
);
5464 ctx
->block
= continue_block
;
5469 /* it can currently happen that NIR doesn't remove the unreachable code */
5470 if (!nir_instr_is_last(&instr
->instr
)) {
5471 ctx
->program
->needs_exact
= true;
5472 /* save exec somewhere temporarily so that it doesn't get
5473 * overwritten before the discard from outer exec masks */
5474 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5475 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5476 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5480 /* This condition is incorrect for uniformly branched discards in a loop
5481 * predicated by a divergent condition, but the above code catches that case
5482 * and the discard would end up turning into a discard_if.
5492 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5493 /* program just ends here */
5494 ctx
->block
->kind
|= block_kind_uniform
;
5495 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5496 0 /* enabled mask */, 9 /* dest */,
5497 false /* compressed */, true/* done */, true /* valid mask */);
5498 bld
.sopp(aco_opcode::s_endpgm
);
5499 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5501 ctx
->block
->kind
|= block_kind_discard
;
5502 /* branch and linear edge is added by visit_if() */
5506 enum aco_descriptor_type
{
5517 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5518 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5520 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5521 return dim
== ac_image_cube
||
5522 dim
== ac_image_1darray
||
5523 dim
== ac_image_2darray
||
5524 dim
== ac_image_2darraymsaa
;
5527 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5528 enum aco_descriptor_type desc_type
,
5529 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5531 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5532 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5533 if (it != ctx->tex_desc.end())
5536 Temp index
= Temp();
5537 bool index_set
= false;
5538 unsigned constant_index
= 0;
5539 unsigned descriptor_set
;
5540 unsigned base_index
;
5541 Builder
bld(ctx
->program
, ctx
->block
);
5544 assert(tex_instr
&& !image
);
5546 base_index
= tex_instr
->sampler_index
;
5548 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5549 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5553 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5554 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5556 constant_index
+= array_size
* const_value
->u32
;
5558 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5559 if (indirect
.type() == RegType::vgpr
)
5560 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5562 if (array_size
!= 1)
5563 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5569 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5573 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5575 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5576 base_index
= deref_instr
->var
->data
.binding
;
5579 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5580 list
= convert_pointer_to_64_bit(ctx
, list
);
5582 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5583 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5584 unsigned offset
= binding
->offset
;
5585 unsigned stride
= binding
->size
;
5589 assert(base_index
< layout
->binding_count
);
5591 switch (desc_type
) {
5592 case ACO_DESC_IMAGE
:
5594 opcode
= aco_opcode::s_load_dwordx8
;
5596 case ACO_DESC_FMASK
:
5598 opcode
= aco_opcode::s_load_dwordx8
;
5601 case ACO_DESC_SAMPLER
:
5603 opcode
= aco_opcode::s_load_dwordx4
;
5604 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5605 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5607 case ACO_DESC_BUFFER
:
5609 opcode
= aco_opcode::s_load_dwordx4
;
5611 case ACO_DESC_PLANE_0
:
5612 case ACO_DESC_PLANE_1
:
5614 opcode
= aco_opcode::s_load_dwordx8
;
5615 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5617 case ACO_DESC_PLANE_2
:
5619 opcode
= aco_opcode::s_load_dwordx4
;
5623 unreachable("invalid desc_type\n");
5626 offset
+= constant_index
* stride
;
5628 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5629 (!index_set
|| binding
->immutable_samplers_equal
)) {
5630 if (binding
->immutable_samplers_equal
)
5633 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5634 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5635 Operand(samplers
[constant_index
* 4 + 0]),
5636 Operand(samplers
[constant_index
* 4 + 1]),
5637 Operand(samplers
[constant_index
* 4 + 2]),
5638 Operand(samplers
[constant_index
* 4 + 3]));
5643 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5645 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5646 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5649 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5651 if (desc_type
== ACO_DESC_PLANE_2
) {
5653 for (unsigned i
= 0; i
< 8; i
++)
5654 components
[i
] = bld
.tmp(s1
);
5655 bld
.pseudo(aco_opcode::p_split_vector
,
5656 Definition(components
[0]),
5657 Definition(components
[1]),
5658 Definition(components
[2]),
5659 Definition(components
[3]),
5662 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5663 bld
.pseudo(aco_opcode::p_split_vector
,
5664 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5665 Definition(components
[4]),
5666 Definition(components
[5]),
5667 Definition(components
[6]),
5668 Definition(components
[7]),
5671 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5672 components
[0], components
[1], components
[2], components
[3],
5673 components
[4], components
[5], components
[6], components
[7]);
5679 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5682 case GLSL_SAMPLER_DIM_BUF
:
5684 case GLSL_SAMPLER_DIM_1D
:
5685 return array
? 2 : 1;
5686 case GLSL_SAMPLER_DIM_2D
:
5687 return array
? 3 : 2;
5688 case GLSL_SAMPLER_DIM_MS
:
5689 return array
? 4 : 3;
5690 case GLSL_SAMPLER_DIM_3D
:
5691 case GLSL_SAMPLER_DIM_CUBE
:
5693 case GLSL_SAMPLER_DIM_RECT
:
5694 case GLSL_SAMPLER_DIM_SUBPASS
:
5696 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5705 /* Adjust the sample index according to FMASK.
5707 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5708 * which is the identity mapping. Each nibble says which physical sample
5709 * should be fetched to get that sample.
5711 * For example, 0x11111100 means there are only 2 samples stored and
5712 * the second sample covers 3/4 of the pixel. When reading samples 0
5713 * and 1, return physical sample 0 (determined by the first two 0s
5714 * in FMASK), otherwise return physical sample 1.
5716 * The sample index should be adjusted as follows:
5717 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5719 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5721 Builder
bld(ctx
->program
, ctx
->block
);
5722 Temp fmask
= bld
.tmp(v1
);
5723 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5724 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5727 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5728 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5729 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5730 load
->operands
[0] = Operand(fmask_desc_ptr
);
5731 load
->operands
[1] = Operand(s4
); /* no sampler */
5732 load
->operands
[2] = Operand(coord
);
5733 load
->definitions
[0] = Definition(fmask
);
5740 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5741 ctx
->block
->instructions
.emplace_back(std::move(load
));
5743 Operand sample_index4
;
5744 if (sample_index
.isConstant()) {
5745 if (sample_index
.constantValue() < 16) {
5746 sample_index4
= Operand(sample_index
.constantValue() << 2);
5748 sample_index4
= Operand(0u);
5750 } else if (sample_index
.regClass() == s1
) {
5751 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5753 assert(sample_index
.regClass() == v1
);
5754 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5758 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5759 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5760 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5761 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5763 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5765 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5766 * resource descriptor is 0 (invalid),
5768 Temp compare
= bld
.tmp(bld
.lm
);
5769 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5770 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5772 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5774 /* Replace the MSAA sample index. */
5775 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5778 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5781 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5782 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5783 bool is_array
= glsl_sampler_type_is_array(type
);
5784 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5785 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5786 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5787 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5788 int count
= image_type_to_components_count(dim
, is_array
);
5789 std::vector
<Temp
> coords(count
);
5790 Builder
bld(ctx
->program
, ctx
->block
);
5794 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5795 /* get sample index */
5796 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5797 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5798 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5799 std::vector
<Temp
> fmask_load_address
;
5800 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5801 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5803 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5804 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5806 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5811 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5812 coords
.resize(coords
.size() + 1);
5813 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5815 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5817 for (int i
= 0; i
< count
; i
++)
5818 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5821 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5822 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5823 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5824 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5827 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5830 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5831 for (unsigned i
= 0; i
< coords
.size(); i
++)
5832 vec
->operands
[i
] = Operand(coords
[i
]);
5833 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5834 vec
->definitions
[0] = Definition(res
);
5835 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5840 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5842 Builder
bld(ctx
->program
, ctx
->block
);
5843 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5844 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5845 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5846 bool is_array
= glsl_sampler_type_is_array(type
);
5847 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5849 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5850 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5851 unsigned num_channels
= util_last_bit(mask
);
5852 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5853 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5856 switch (num_channels
) {
5858 opcode
= aco_opcode::buffer_load_format_x
;
5861 opcode
= aco_opcode::buffer_load_format_xy
;
5864 opcode
= aco_opcode::buffer_load_format_xyz
;
5867 opcode
= aco_opcode::buffer_load_format_xyzw
;
5870 unreachable(">4 channel buffer image load");
5872 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5873 load
->operands
[0] = Operand(rsrc
);
5874 load
->operands
[1] = Operand(vindex
);
5875 load
->operands
[2] = Operand((uint32_t) 0);
5877 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5880 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5881 load
->definitions
[0] = Definition(tmp
);
5883 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5884 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5885 load
->barrier
= barrier_image
;
5886 ctx
->block
->instructions
.emplace_back(std::move(load
));
5888 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5892 Temp coords
= get_image_coords(ctx
, instr
, type
);
5893 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5895 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5896 unsigned num_components
= util_bitcount(dmask
);
5898 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5901 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5903 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5904 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5906 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5907 load
->operands
[0] = Operand(resource
);
5908 load
->operands
[1] = Operand(s4
); /* no sampler */
5909 load
->operands
[2] = Operand(coords
);
5910 load
->definitions
[0] = Definition(tmp
);
5911 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5912 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5913 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5914 load
->dmask
= dmask
;
5916 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5917 load
->barrier
= barrier_image
;
5918 ctx
->block
->instructions
.emplace_back(std::move(load
));
5920 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5924 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5926 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5927 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5928 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5929 bool is_array
= glsl_sampler_type_is_array(type
);
5930 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5932 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5934 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5935 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5936 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5938 switch (data
.size()) {
5940 opcode
= aco_opcode::buffer_store_format_x
;
5943 opcode
= aco_opcode::buffer_store_format_xy
;
5946 opcode
= aco_opcode::buffer_store_format_xyz
;
5949 opcode
= aco_opcode::buffer_store_format_xyzw
;
5952 unreachable(">4 channel buffer image store");
5954 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5955 store
->operands
[0] = Operand(rsrc
);
5956 store
->operands
[1] = Operand(vindex
);
5957 store
->operands
[2] = Operand((uint32_t) 0);
5958 store
->operands
[3] = Operand(data
);
5959 store
->idxen
= true;
5962 store
->disable_wqm
= true;
5963 store
->barrier
= barrier_image
;
5964 ctx
->program
->needs_exact
= true;
5965 ctx
->block
->instructions
.emplace_back(std::move(store
));
5969 assert(data
.type() == RegType::vgpr
);
5970 Temp coords
= get_image_coords(ctx
, instr
, type
);
5971 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5973 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5974 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5976 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5977 store
->operands
[0] = Operand(resource
);
5978 store
->operands
[1] = Operand(data
);
5979 store
->operands
[2] = Operand(coords
);
5982 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5983 store
->dmask
= (1 << data
.size()) - 1;
5985 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5986 store
->disable_wqm
= true;
5987 store
->barrier
= barrier_image
;
5988 ctx
->program
->needs_exact
= true;
5989 ctx
->block
->instructions
.emplace_back(std::move(store
));
5993 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5995 /* return the previous value if dest is ever used */
5996 bool return_previous
= false;
5997 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5998 return_previous
= true;
6001 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6002 return_previous
= true;
6006 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6007 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6008 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6009 bool is_array
= glsl_sampler_type_is_array(type
);
6010 Builder
bld(ctx
->program
, ctx
->block
);
6012 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
6013 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
6015 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
6016 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
6018 aco_opcode buf_op
, image_op
;
6019 switch (instr
->intrinsic
) {
6020 case nir_intrinsic_image_deref_atomic_add
:
6021 buf_op
= aco_opcode::buffer_atomic_add
;
6022 image_op
= aco_opcode::image_atomic_add
;
6024 case nir_intrinsic_image_deref_atomic_umin
:
6025 buf_op
= aco_opcode::buffer_atomic_umin
;
6026 image_op
= aco_opcode::image_atomic_umin
;
6028 case nir_intrinsic_image_deref_atomic_imin
:
6029 buf_op
= aco_opcode::buffer_atomic_smin
;
6030 image_op
= aco_opcode::image_atomic_smin
;
6032 case nir_intrinsic_image_deref_atomic_umax
:
6033 buf_op
= aco_opcode::buffer_atomic_umax
;
6034 image_op
= aco_opcode::image_atomic_umax
;
6036 case nir_intrinsic_image_deref_atomic_imax
:
6037 buf_op
= aco_opcode::buffer_atomic_smax
;
6038 image_op
= aco_opcode::image_atomic_smax
;
6040 case nir_intrinsic_image_deref_atomic_and
:
6041 buf_op
= aco_opcode::buffer_atomic_and
;
6042 image_op
= aco_opcode::image_atomic_and
;
6044 case nir_intrinsic_image_deref_atomic_or
:
6045 buf_op
= aco_opcode::buffer_atomic_or
;
6046 image_op
= aco_opcode::image_atomic_or
;
6048 case nir_intrinsic_image_deref_atomic_xor
:
6049 buf_op
= aco_opcode::buffer_atomic_xor
;
6050 image_op
= aco_opcode::image_atomic_xor
;
6052 case nir_intrinsic_image_deref_atomic_exchange
:
6053 buf_op
= aco_opcode::buffer_atomic_swap
;
6054 image_op
= aco_opcode::image_atomic_swap
;
6056 case nir_intrinsic_image_deref_atomic_comp_swap
:
6057 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
6058 image_op
= aco_opcode::image_atomic_cmpswap
;
6061 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6064 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6066 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6067 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6068 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6069 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6070 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6071 mubuf
->operands
[0] = Operand(resource
);
6072 mubuf
->operands
[1] = Operand(vindex
);
6073 mubuf
->operands
[2] = Operand((uint32_t)0);
6074 mubuf
->operands
[3] = Operand(data
);
6075 if (return_previous
)
6076 mubuf
->definitions
[0] = Definition(dst
);
6078 mubuf
->idxen
= true;
6079 mubuf
->glc
= return_previous
;
6080 mubuf
->dlc
= false; /* Not needed for atomics */
6081 mubuf
->disable_wqm
= true;
6082 mubuf
->barrier
= barrier_image
;
6083 ctx
->program
->needs_exact
= true;
6084 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6088 Temp coords
= get_image_coords(ctx
, instr
, type
);
6089 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6090 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6091 mimg
->operands
[0] = Operand(resource
);
6092 mimg
->operands
[1] = Operand(data
);
6093 mimg
->operands
[2] = Operand(coords
);
6094 if (return_previous
)
6095 mimg
->definitions
[0] = Definition(dst
);
6096 mimg
->glc
= return_previous
;
6097 mimg
->dlc
= false; /* Not needed for atomics */
6098 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6099 mimg
->dmask
= (1 << data
.size()) - 1;
6101 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6102 mimg
->disable_wqm
= true;
6103 mimg
->barrier
= barrier_image
;
6104 ctx
->program
->needs_exact
= true;
6105 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6109 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6111 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6112 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6113 Builder
bld(ctx
->program
, ctx
->block
);
6115 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6117 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6118 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6120 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6121 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6123 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6124 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6126 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6127 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6128 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6129 if (dst
.type() == RegType::vgpr
)
6130 bld
.copy(Definition(dst
), shr_dst
);
6132 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6134 emit_extract_vector(ctx
, desc
, 2, dst
);
6138 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6140 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6141 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6142 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6143 bool is_array
= glsl_sampler_type_is_array(type
);
6144 Builder
bld(ctx
->program
, ctx
->block
);
6146 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6147 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6148 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6152 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6155 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6157 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6159 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6160 mimg
->operands
[0] = Operand(resource
);
6161 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6162 mimg
->operands
[2] = Operand(lod
);
6163 uint8_t& dmask
= mimg
->dmask
;
6164 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6165 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6166 mimg
->da
= glsl_sampler_type_is_array(type
);
6167 mimg
->can_reorder
= true;
6168 Definition
& def
= mimg
->definitions
[0];
6169 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6171 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6172 glsl_sampler_type_is_array(type
)) {
6174 assert(instr
->dest
.ssa
.num_components
== 3);
6175 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6176 def
= Definition(tmp
);
6177 emit_split_vector(ctx
, tmp
, 3);
6179 /* divide 3rd value by 6 by multiplying with magic number */
6180 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6181 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6183 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6184 emit_extract_vector(ctx
, tmp
, 0, v1
),
6185 emit_extract_vector(ctx
, tmp
, 1, v1
),
6188 } else if (ctx
->options
->chip_class
== GFX9
&&
6189 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6190 glsl_sampler_type_is_array(type
)) {
6191 assert(instr
->dest
.ssa
.num_components
== 2);
6192 def
= Definition(dst
);
6195 def
= Definition(dst
);
6198 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6201 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6203 Builder
bld(ctx
->program
, ctx
->block
);
6204 unsigned num_components
= instr
->num_components
;
6206 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6207 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6208 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6210 unsigned access
= nir_intrinsic_access(instr
);
6211 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6212 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6214 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6215 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6216 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6218 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6219 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6221 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6222 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false, allow_smem
);
6225 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6227 Builder
bld(ctx
->program
, ctx
->block
);
6228 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6229 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6230 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6231 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6233 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6234 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6236 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6237 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6238 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6239 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6241 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6243 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6244 ctx
->options
->chip_class
>= GFX8
&&
6245 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6248 offset
= bld
.as_uniform(offset
);
6249 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6251 unsigned write_count
= 0;
6252 Temp write_datas
[32];
6253 unsigned offsets
[32];
6254 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6255 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6257 for (unsigned i
= 0; i
< write_count
; i
++) {
6258 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6259 if (smem
&& ctx
->stage
== fragment_fs
)
6260 op
= aco_opcode::p_fs_buffer_store_smem
;
6263 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6264 store
->operands
[0] = Operand(rsrc
);
6266 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6267 offset
, Operand(offsets
[i
]));
6268 store
->operands
[1] = Operand(off
);
6270 store
->operands
[1] = Operand(offset
);
6272 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6273 store
->operands
[1].setFixed(m0
);
6274 store
->operands
[2] = Operand(write_datas
[i
]);
6277 store
->disable_wqm
= true;
6278 store
->barrier
= barrier_buffer
;
6279 ctx
->block
->instructions
.emplace_back(std::move(store
));
6280 ctx
->program
->wb_smem_l1_on_end
= true;
6281 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6282 ctx
->block
->kind
|= block_kind_needs_lowering
;
6283 ctx
->program
->needs_exact
= true;
6286 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6287 store
->operands
[0] = Operand(rsrc
);
6288 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6289 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6290 store
->operands
[3] = Operand(write_datas
[i
]);
6291 store
->offset
= offsets
[i
];
6292 store
->offen
= (offset
.type() == RegType::vgpr
);
6295 store
->disable_wqm
= true;
6296 store
->barrier
= barrier_buffer
;
6297 ctx
->program
->needs_exact
= true;
6298 ctx
->block
->instructions
.emplace_back(std::move(store
));
6303 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6305 /* return the previous value if dest is ever used */
6306 bool return_previous
= false;
6307 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6308 return_previous
= true;
6311 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6312 return_previous
= true;
6316 Builder
bld(ctx
->program
, ctx
->block
);
6317 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6319 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6320 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6321 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6323 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6324 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6325 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6327 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6329 aco_opcode op32
, op64
;
6330 switch (instr
->intrinsic
) {
6331 case nir_intrinsic_ssbo_atomic_add
:
6332 op32
= aco_opcode::buffer_atomic_add
;
6333 op64
= aco_opcode::buffer_atomic_add_x2
;
6335 case nir_intrinsic_ssbo_atomic_imin
:
6336 op32
= aco_opcode::buffer_atomic_smin
;
6337 op64
= aco_opcode::buffer_atomic_smin_x2
;
6339 case nir_intrinsic_ssbo_atomic_umin
:
6340 op32
= aco_opcode::buffer_atomic_umin
;
6341 op64
= aco_opcode::buffer_atomic_umin_x2
;
6343 case nir_intrinsic_ssbo_atomic_imax
:
6344 op32
= aco_opcode::buffer_atomic_smax
;
6345 op64
= aco_opcode::buffer_atomic_smax_x2
;
6347 case nir_intrinsic_ssbo_atomic_umax
:
6348 op32
= aco_opcode::buffer_atomic_umax
;
6349 op64
= aco_opcode::buffer_atomic_umax_x2
;
6351 case nir_intrinsic_ssbo_atomic_and
:
6352 op32
= aco_opcode::buffer_atomic_and
;
6353 op64
= aco_opcode::buffer_atomic_and_x2
;
6355 case nir_intrinsic_ssbo_atomic_or
:
6356 op32
= aco_opcode::buffer_atomic_or
;
6357 op64
= aco_opcode::buffer_atomic_or_x2
;
6359 case nir_intrinsic_ssbo_atomic_xor
:
6360 op32
= aco_opcode::buffer_atomic_xor
;
6361 op64
= aco_opcode::buffer_atomic_xor_x2
;
6363 case nir_intrinsic_ssbo_atomic_exchange
:
6364 op32
= aco_opcode::buffer_atomic_swap
;
6365 op64
= aco_opcode::buffer_atomic_swap_x2
;
6367 case nir_intrinsic_ssbo_atomic_comp_swap
:
6368 op32
= aco_opcode::buffer_atomic_cmpswap
;
6369 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6372 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6374 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6375 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6376 mubuf
->operands
[0] = Operand(rsrc
);
6377 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6378 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6379 mubuf
->operands
[3] = Operand(data
);
6380 if (return_previous
)
6381 mubuf
->definitions
[0] = Definition(dst
);
6383 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6384 mubuf
->glc
= return_previous
;
6385 mubuf
->dlc
= false; /* Not needed for atomics */
6386 mubuf
->disable_wqm
= true;
6387 mubuf
->barrier
= barrier_buffer
;
6388 ctx
->program
->needs_exact
= true;
6389 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6392 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6394 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6395 Builder
bld(ctx
->program
, ctx
->block
);
6396 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6397 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6400 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6402 Builder
bld(ctx
->program
, ctx
->block
);
6403 unsigned num_components
= instr
->num_components
;
6404 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6406 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6407 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6408 num_components
, component_size
};
6409 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6410 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6411 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6412 info
.barrier
= barrier_buffer
;
6413 info
.can_reorder
= false;
6414 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6415 * it's safe to use SMEM */
6416 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6417 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6418 emit_global_load(ctx
, bld
, &info
);
6420 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6421 emit_smem_load(ctx
, bld
, &info
);
6425 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6427 Builder
bld(ctx
->program
, ctx
->block
);
6428 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6429 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6431 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6432 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6433 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6435 if (ctx
->options
->chip_class
>= GFX7
)
6436 addr
= as_vgpr(ctx
, addr
);
6438 unsigned write_count
= 0;
6439 Temp write_datas
[32];
6440 unsigned offsets
[32];
6441 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6442 16, &write_count
, write_datas
, offsets
);
6444 for (unsigned i
= 0; i
< write_count
; i
++) {
6445 if (ctx
->options
->chip_class
>= GFX7
) {
6446 unsigned offset
= offsets
[i
];
6447 Temp store_addr
= addr
;
6448 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6449 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6450 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6451 Temp carry
= bld
.tmp(bld
.lm
);
6452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6454 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6455 Operand(offset
), addr0
);
6456 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6458 carry
).def(1).setHint(vcc
);
6460 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6465 bool global
= ctx
->options
->chip_class
>= GFX9
;
6467 switch (write_datas
[i
].bytes()) {
6469 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6472 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6475 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6478 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6481 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6484 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6487 unreachable("store_global not implemented for this size.");
6490 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6491 flat
->operands
[0] = Operand(store_addr
);
6492 flat
->operands
[1] = Operand(s1
);
6493 flat
->operands
[2] = Operand(write_datas
[i
]);
6496 flat
->offset
= offset
;
6497 flat
->disable_wqm
= true;
6498 flat
->barrier
= barrier_buffer
;
6499 ctx
->program
->needs_exact
= true;
6500 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6502 assert(ctx
->options
->chip_class
== GFX6
);
6504 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6506 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6508 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6509 mubuf
->operands
[0] = Operand(rsrc
);
6510 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6511 mubuf
->operands
[2] = Operand(0u);
6512 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6515 mubuf
->offset
= offsets
[i
];
6516 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6517 mubuf
->disable_wqm
= true;
6518 mubuf
->barrier
= barrier_buffer
;
6519 ctx
->program
->needs_exact
= true;
6520 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6525 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6527 /* return the previous value if dest is ever used */
6528 bool return_previous
= false;
6529 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6530 return_previous
= true;
6533 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6534 return_previous
= true;
6538 Builder
bld(ctx
->program
, ctx
->block
);
6539 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6540 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6542 if (ctx
->options
->chip_class
>= GFX7
)
6543 addr
= as_vgpr(ctx
, addr
);
6545 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6546 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6547 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6549 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6551 aco_opcode op32
, op64
;
6553 if (ctx
->options
->chip_class
>= GFX7
) {
6554 bool global
= ctx
->options
->chip_class
>= GFX9
;
6555 switch (instr
->intrinsic
) {
6556 case nir_intrinsic_global_atomic_add
:
6557 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6558 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6560 case nir_intrinsic_global_atomic_imin
:
6561 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6562 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6564 case nir_intrinsic_global_atomic_umin
:
6565 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6566 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6568 case nir_intrinsic_global_atomic_imax
:
6569 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6570 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6572 case nir_intrinsic_global_atomic_umax
:
6573 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6574 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6576 case nir_intrinsic_global_atomic_and
:
6577 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6578 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6580 case nir_intrinsic_global_atomic_or
:
6581 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6582 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6584 case nir_intrinsic_global_atomic_xor
:
6585 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6586 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6588 case nir_intrinsic_global_atomic_exchange
:
6589 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6590 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6592 case nir_intrinsic_global_atomic_comp_swap
:
6593 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6594 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6597 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6600 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6601 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6602 flat
->operands
[0] = Operand(addr
);
6603 flat
->operands
[1] = Operand(s1
);
6604 flat
->operands
[2] = Operand(data
);
6605 if (return_previous
)
6606 flat
->definitions
[0] = Definition(dst
);
6607 flat
->glc
= return_previous
;
6608 flat
->dlc
= false; /* Not needed for atomics */
6610 flat
->disable_wqm
= true;
6611 flat
->barrier
= barrier_buffer
;
6612 ctx
->program
->needs_exact
= true;
6613 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6615 assert(ctx
->options
->chip_class
== GFX6
);
6617 switch (instr
->intrinsic
) {
6618 case nir_intrinsic_global_atomic_add
:
6619 op32
= aco_opcode::buffer_atomic_add
;
6620 op64
= aco_opcode::buffer_atomic_add_x2
;
6622 case nir_intrinsic_global_atomic_imin
:
6623 op32
= aco_opcode::buffer_atomic_smin
;
6624 op64
= aco_opcode::buffer_atomic_smin_x2
;
6626 case nir_intrinsic_global_atomic_umin
:
6627 op32
= aco_opcode::buffer_atomic_umin
;
6628 op64
= aco_opcode::buffer_atomic_umin_x2
;
6630 case nir_intrinsic_global_atomic_imax
:
6631 op32
= aco_opcode::buffer_atomic_smax
;
6632 op64
= aco_opcode::buffer_atomic_smax_x2
;
6634 case nir_intrinsic_global_atomic_umax
:
6635 op32
= aco_opcode::buffer_atomic_umax
;
6636 op64
= aco_opcode::buffer_atomic_umax_x2
;
6638 case nir_intrinsic_global_atomic_and
:
6639 op32
= aco_opcode::buffer_atomic_and
;
6640 op64
= aco_opcode::buffer_atomic_and_x2
;
6642 case nir_intrinsic_global_atomic_or
:
6643 op32
= aco_opcode::buffer_atomic_or
;
6644 op64
= aco_opcode::buffer_atomic_or_x2
;
6646 case nir_intrinsic_global_atomic_xor
:
6647 op32
= aco_opcode::buffer_atomic_xor
;
6648 op64
= aco_opcode::buffer_atomic_xor_x2
;
6650 case nir_intrinsic_global_atomic_exchange
:
6651 op32
= aco_opcode::buffer_atomic_swap
;
6652 op64
= aco_opcode::buffer_atomic_swap_x2
;
6654 case nir_intrinsic_global_atomic_comp_swap
:
6655 op32
= aco_opcode::buffer_atomic_cmpswap
;
6656 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6659 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6662 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6664 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6666 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6667 mubuf
->operands
[0] = Operand(rsrc
);
6668 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6669 mubuf
->operands
[2] = Operand(0u);
6670 mubuf
->operands
[3] = Operand(data
);
6671 if (return_previous
)
6672 mubuf
->definitions
[0] = Definition(dst
);
6673 mubuf
->glc
= return_previous
;
6676 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6677 mubuf
->disable_wqm
= true;
6678 mubuf
->barrier
= barrier_buffer
;
6679 ctx
->program
->needs_exact
= true;
6680 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6684 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6685 Builder
bld(ctx
->program
, ctx
->block
);
6686 switch(instr
->intrinsic
) {
6687 case nir_intrinsic_group_memory_barrier
:
6688 case nir_intrinsic_memory_barrier
:
6689 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6691 case nir_intrinsic_memory_barrier_buffer
:
6692 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6694 case nir_intrinsic_memory_barrier_image
:
6695 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6697 case nir_intrinsic_memory_barrier_tcs_patch
:
6698 case nir_intrinsic_memory_barrier_shared
:
6699 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6702 unreachable("Unimplemented memory barrier intrinsic");
6707 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6709 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6710 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6711 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6712 Builder
bld(ctx
->program
, ctx
->block
);
6714 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6715 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6716 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6719 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6721 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6722 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6723 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6724 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6726 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6727 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6730 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6732 unsigned offset
= nir_intrinsic_base(instr
);
6733 Builder
bld(ctx
->program
, ctx
->block
);
6734 Operand m
= load_lds_size_m0(bld
);
6735 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6736 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6738 unsigned num_operands
= 3;
6739 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6740 switch(instr
->intrinsic
) {
6741 case nir_intrinsic_shared_atomic_add
:
6742 op32
= aco_opcode::ds_add_u32
;
6743 op64
= aco_opcode::ds_add_u64
;
6744 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6745 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6747 case nir_intrinsic_shared_atomic_imin
:
6748 op32
= aco_opcode::ds_min_i32
;
6749 op64
= aco_opcode::ds_min_i64
;
6750 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6751 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6753 case nir_intrinsic_shared_atomic_umin
:
6754 op32
= aco_opcode::ds_min_u32
;
6755 op64
= aco_opcode::ds_min_u64
;
6756 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6757 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6759 case nir_intrinsic_shared_atomic_imax
:
6760 op32
= aco_opcode::ds_max_i32
;
6761 op64
= aco_opcode::ds_max_i64
;
6762 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6763 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6765 case nir_intrinsic_shared_atomic_umax
:
6766 op32
= aco_opcode::ds_max_u32
;
6767 op64
= aco_opcode::ds_max_u64
;
6768 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6769 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6771 case nir_intrinsic_shared_atomic_and
:
6772 op32
= aco_opcode::ds_and_b32
;
6773 op64
= aco_opcode::ds_and_b64
;
6774 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6775 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6777 case nir_intrinsic_shared_atomic_or
:
6778 op32
= aco_opcode::ds_or_b32
;
6779 op64
= aco_opcode::ds_or_b64
;
6780 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6781 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6783 case nir_intrinsic_shared_atomic_xor
:
6784 op32
= aco_opcode::ds_xor_b32
;
6785 op64
= aco_opcode::ds_xor_b64
;
6786 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6787 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6789 case nir_intrinsic_shared_atomic_exchange
:
6790 op32
= aco_opcode::ds_write_b32
;
6791 op64
= aco_opcode::ds_write_b64
;
6792 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6793 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6795 case nir_intrinsic_shared_atomic_comp_swap
:
6796 op32
= aco_opcode::ds_cmpst_b32
;
6797 op64
= aco_opcode::ds_cmpst_b64
;
6798 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6799 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6802 case nir_intrinsic_shared_atomic_fadd
:
6803 op32
= aco_opcode::ds_add_f32
;
6804 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6805 op64
= aco_opcode::num_opcodes
;
6806 op64_rtn
= aco_opcode::num_opcodes
;
6809 unreachable("Unhandled shared atomic intrinsic");
6812 /* return the previous value if dest is ever used */
6813 bool return_previous
= false;
6814 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6815 return_previous
= true;
6818 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6819 return_previous
= true;
6824 if (data
.size() == 1) {
6825 assert(instr
->dest
.ssa
.bit_size
== 32);
6826 op
= return_previous
? op32_rtn
: op32
;
6828 assert(instr
->dest
.ssa
.bit_size
== 64);
6829 op
= return_previous
? op64_rtn
: op64
;
6832 if (offset
> 65535) {
6833 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6837 aco_ptr
<DS_instruction
> ds
;
6838 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6839 ds
->operands
[0] = Operand(address
);
6840 ds
->operands
[1] = Operand(data
);
6841 if (num_operands
== 4)
6842 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6843 ds
->operands
[num_operands
- 1] = m
;
6844 ds
->offset0
= offset
;
6845 if (return_previous
)
6846 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6847 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6850 Temp
get_scratch_resource(isel_context
*ctx
)
6852 Builder
bld(ctx
->program
, ctx
->block
);
6853 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6854 if (ctx
->stage
!= compute_cs
)
6855 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6857 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6858 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6860 if (ctx
->program
->chip_class
>= GFX10
) {
6861 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6862 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6863 S_008F0C_RESOURCE_LEVEL(1);
6864 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6865 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6866 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6869 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6870 if (ctx
->program
->chip_class
<= GFX8
)
6871 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6873 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6876 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6877 Builder
bld(ctx
->program
, ctx
->block
);
6878 Temp rsrc
= get_scratch_resource(ctx
);
6879 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6880 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6882 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6883 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6884 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6885 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6886 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6887 info
.can_reorder
= false;
6888 info
.soffset
= ctx
->program
->scratch_offset
;
6889 emit_scratch_load(ctx
, bld
, &info
);
6892 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6893 Builder
bld(ctx
->program
, ctx
->block
);
6894 Temp rsrc
= get_scratch_resource(ctx
);
6895 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6896 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6898 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6899 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6901 unsigned write_count
= 0;
6902 Temp write_datas
[32];
6903 unsigned offsets
[32];
6904 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6905 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6906 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6908 for (unsigned i
= 0; i
< write_count
; i
++) {
6909 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6910 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6914 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6915 uint8_t log2_ps_iter_samples
;
6916 if (ctx
->program
->info
->ps
.force_persample
) {
6917 log2_ps_iter_samples
=
6918 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6920 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6923 /* The bit pattern matches that used by fixed function fragment
6925 static const unsigned ps_iter_masks
[] = {
6926 0xffff, /* not used */
6932 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6934 Builder
bld(ctx
->program
, ctx
->block
);
6936 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6937 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6938 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6939 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6940 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6941 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6944 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6945 Builder
bld(ctx
->program
, ctx
->block
);
6947 unsigned stream
= nir_intrinsic_stream_id(instr
);
6948 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6949 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6950 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6953 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6955 unsigned num_components
=
6956 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6957 assert(num_components
);
6959 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6960 unsigned stream_offset
= 0;
6961 for (unsigned i
= 0; i
< stream
; i
++) {
6962 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6963 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6966 /* Limit on the stride field for <= GFX7. */
6967 assert(stride
< (1 << 14));
6969 Temp gsvs_dwords
[4];
6970 for (unsigned i
= 0; i
< 4; i
++)
6971 gsvs_dwords
[i
] = bld
.tmp(s1
);
6972 bld
.pseudo(aco_opcode::p_split_vector
,
6973 Definition(gsvs_dwords
[0]),
6974 Definition(gsvs_dwords
[1]),
6975 Definition(gsvs_dwords
[2]),
6976 Definition(gsvs_dwords
[3]),
6979 if (stream_offset
) {
6980 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6982 Temp carry
= bld
.tmp(s1
);
6983 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6984 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6987 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6988 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6990 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6991 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6993 unsigned offset
= 0;
6994 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6995 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6998 for (unsigned j
= 0; j
< 4; j
++) {
6999 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7002 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7003 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7004 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7005 if (const_offset
>= 4096u) {
7006 if (vaddr_offset
.isUndefined())
7007 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7009 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7010 const_offset
%= 4096u;
7013 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7014 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7015 mtbuf
->operands
[1] = vaddr_offset
;
7016 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7017 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7018 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7019 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7020 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7021 mtbuf
->offset
= const_offset
;
7024 mtbuf
->barrier
= barrier_gs_data
;
7025 mtbuf
->can_reorder
= true;
7026 bld
.insert(std::move(mtbuf
));
7029 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7032 /* outputs for the next vertex are undefined and keeping them around can
7033 * create invalid IR with control flow */
7034 ctx
->outputs
.mask
[i
] = 0;
7037 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7040 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7042 Builder
bld(ctx
->program
, ctx
->block
);
7044 if (cluster_size
== 1) {
7046 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7047 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7048 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7049 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7050 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7051 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7052 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7053 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7054 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7055 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7056 //subgroupAnd(val) -> (exec & ~val) == 0
7057 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7058 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7059 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7060 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7061 //subgroupOr(val) -> (val & exec) != 0
7062 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7063 return bool_to_vector_condition(ctx
, tmp
);
7064 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7065 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7066 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7067 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7068 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7069 return bool_to_vector_condition(ctx
, tmp
);
7071 //subgroupClustered{And,Or,Xor}(val, n) ->
7072 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7073 //cluster_offset = ~(n - 1) & lane_id
7074 //cluster_mask = ((1 << n) - 1)
7075 //subgroupClusteredAnd():
7076 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7077 //subgroupClusteredOr():
7078 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7079 //subgroupClusteredXor():
7080 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7081 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7082 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7085 if (op
== nir_op_iand
)
7086 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7088 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7090 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7092 if (ctx
->program
->chip_class
<= GFX7
)
7093 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7094 else if (ctx
->program
->wave_size
== 64)
7095 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7097 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7098 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7099 if (cluster_mask
!= 0xffffffff)
7100 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7102 Definition cmp_def
= Definition();
7103 if (op
== nir_op_iand
) {
7104 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7105 } else if (op
== nir_op_ior
) {
7106 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7107 } else if (op
== nir_op_ixor
) {
7108 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7109 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7110 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7112 cmp_def
.setHint(vcc
);
7113 return cmp_def
.getTemp();
7117 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7119 Builder
bld(ctx
->program
, ctx
->block
);
7121 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7122 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7123 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7125 if (op
== nir_op_iand
)
7126 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7128 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7130 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7131 Temp lo
= lohi
.def(0).getTemp();
7132 Temp hi
= lohi
.def(1).getTemp();
7133 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7135 Definition cmp_def
= Definition();
7136 if (op
== nir_op_iand
)
7137 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7138 else if (op
== nir_op_ior
)
7139 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7140 else if (op
== nir_op_ixor
)
7141 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7142 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7143 cmp_def
.setHint(vcc
);
7144 return cmp_def
.getTemp();
7147 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7149 Builder
bld(ctx
->program
, ctx
->block
);
7151 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7152 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7153 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7154 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7155 if (op
== nir_op_iand
)
7156 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7157 else if (op
== nir_op_ior
)
7158 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7159 else if (op
== nir_op_ixor
)
7160 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7166 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7168 Builder
bld(ctx
->program
, ctx
->block
);
7169 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7170 if (src
.regClass().type() == RegType::vgpr
) {
7171 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7172 } else if (src
.regClass() == s1
) {
7173 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7174 } else if (src
.regClass() == s2
) {
7175 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7177 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7178 nir_print_instr(&instr
->instr
, stderr
);
7179 fprintf(stderr
, "\n");
7183 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7185 Builder
bld(ctx
->program
, ctx
->block
);
7186 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7187 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7188 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7190 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7191 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7192 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7193 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7196 if (ctx
->program
->chip_class
>= GFX8
) {
7197 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7198 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7199 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7200 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7201 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7202 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7204 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7205 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7206 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7207 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7208 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7209 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7210 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7211 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7212 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7213 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7216 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7217 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7218 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7219 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7220 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7221 Temp wqm1
= bld
.tmp(v1
);
7222 emit_wqm(ctx
, tmp1
, wqm1
, true);
7223 Temp wqm2
= bld
.tmp(v1
);
7224 emit_wqm(ctx
, tmp2
, wqm2
, true);
7225 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7229 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7231 Builder
bld(ctx
->program
, ctx
->block
);
7232 switch(instr
->intrinsic
) {
7233 case nir_intrinsic_load_barycentric_sample
:
7234 case nir_intrinsic_load_barycentric_pixel
:
7235 case nir_intrinsic_load_barycentric_centroid
: {
7236 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7237 Temp bary
= Temp(0, s2
);
7239 case INTERP_MODE_SMOOTH
:
7240 case INTERP_MODE_NONE
:
7241 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7242 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7243 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7244 bary
= ctx
->persp_centroid
;
7245 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7246 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7248 case INTERP_MODE_NOPERSPECTIVE
:
7249 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7250 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7251 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7252 bary
= ctx
->linear_centroid
;
7253 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7254 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7259 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7260 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7261 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7263 Operand(p1
), Operand(p2
));
7264 emit_split_vector(ctx
, dst
, 2);
7267 case nir_intrinsic_load_barycentric_model
: {
7268 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7270 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7271 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7272 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7273 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7274 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7275 Operand(p1
), Operand(p2
), Operand(p3
));
7276 emit_split_vector(ctx
, dst
, 3);
7279 case nir_intrinsic_load_barycentric_at_sample
: {
7280 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7281 switch (ctx
->options
->key
.fs
.num_samples
) {
7282 case 2: sample_pos_offset
+= 1 << 3; break;
7283 case 4: sample_pos_offset
+= 3 << 3; break;
7284 case 8: sample_pos_offset
+= 7 << 3; break;
7288 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7289 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7290 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7291 //TODO: bounds checking?
7292 if (addr
.type() == RegType::sgpr
) {
7295 sample_pos_offset
+= const_addr
->u32
<< 3;
7296 offset
= Operand(sample_pos_offset
);
7297 } else if (ctx
->options
->chip_class
>= GFX9
) {
7298 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7300 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7301 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7304 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7305 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7307 } else if (ctx
->options
->chip_class
>= GFX9
) {
7308 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7309 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7310 } else if (ctx
->options
->chip_class
>= GFX7
) {
7311 /* addr += private_segment_buffer + sample_pos_offset */
7312 Temp tmp0
= bld
.tmp(s1
);
7313 Temp tmp1
= bld
.tmp(s1
);
7314 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7315 Definition scc_tmp
= bld
.def(s1
, scc
);
7316 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7317 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7318 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7319 Temp pck0
= bld
.tmp(v1
);
7320 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7321 tmp1
= as_vgpr(ctx
, tmp1
);
7322 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7323 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7325 /* sample_pos = flat_load_dwordx2 addr */
7326 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7328 assert(ctx
->options
->chip_class
== GFX6
);
7330 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7331 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7332 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7334 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7335 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7337 sample_pos
= bld
.tmp(v2
);
7339 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7340 load
->definitions
[0] = Definition(sample_pos
);
7341 load
->operands
[0] = Operand(rsrc
);
7342 load
->operands
[1] = Operand(addr
);
7343 load
->operands
[2] = Operand(0u);
7344 load
->offset
= sample_pos_offset
;
7346 load
->addr64
= true;
7349 load
->disable_wqm
= false;
7350 load
->barrier
= barrier_none
;
7351 load
->can_reorder
= true;
7352 ctx
->block
->instructions
.emplace_back(std::move(load
));
7355 /* sample_pos -= 0.5 */
7356 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7357 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7358 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7359 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7360 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7362 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7365 case nir_intrinsic_load_barycentric_at_offset
: {
7366 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7367 RegClass rc
= RegClass(offset
.type(), 1);
7368 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7369 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7370 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7373 case nir_intrinsic_load_front_face
: {
7374 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7375 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7378 case nir_intrinsic_load_view_index
: {
7379 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7380 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7381 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7387 case nir_intrinsic_load_layer_id
: {
7388 unsigned idx
= nir_intrinsic_base(instr
);
7389 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7390 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7393 case nir_intrinsic_load_frag_coord
: {
7394 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7397 case nir_intrinsic_load_sample_pos
: {
7398 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7399 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7400 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7401 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7402 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7405 case nir_intrinsic_load_tess_coord
:
7406 visit_load_tess_coord(ctx
, instr
);
7408 case nir_intrinsic_load_interpolated_input
:
7409 visit_load_interpolated_input(ctx
, instr
);
7411 case nir_intrinsic_store_output
:
7412 visit_store_output(ctx
, instr
);
7414 case nir_intrinsic_load_input
:
7415 case nir_intrinsic_load_input_vertex
:
7416 visit_load_input(ctx
, instr
);
7418 case nir_intrinsic_load_output
:
7419 visit_load_output(ctx
, instr
);
7421 case nir_intrinsic_load_per_vertex_input
:
7422 visit_load_per_vertex_input(ctx
, instr
);
7424 case nir_intrinsic_load_per_vertex_output
:
7425 visit_load_per_vertex_output(ctx
, instr
);
7427 case nir_intrinsic_store_per_vertex_output
:
7428 visit_store_per_vertex_output(ctx
, instr
);
7430 case nir_intrinsic_load_ubo
:
7431 visit_load_ubo(ctx
, instr
);
7433 case nir_intrinsic_load_push_constant
:
7434 visit_load_push_constant(ctx
, instr
);
7436 case nir_intrinsic_load_constant
:
7437 visit_load_constant(ctx
, instr
);
7439 case nir_intrinsic_vulkan_resource_index
:
7440 visit_load_resource(ctx
, instr
);
7442 case nir_intrinsic_discard
:
7443 visit_discard(ctx
, instr
);
7445 case nir_intrinsic_discard_if
:
7446 visit_discard_if(ctx
, instr
);
7448 case nir_intrinsic_load_shared
:
7449 visit_load_shared(ctx
, instr
);
7451 case nir_intrinsic_store_shared
:
7452 visit_store_shared(ctx
, instr
);
7454 case nir_intrinsic_shared_atomic_add
:
7455 case nir_intrinsic_shared_atomic_imin
:
7456 case nir_intrinsic_shared_atomic_umin
:
7457 case nir_intrinsic_shared_atomic_imax
:
7458 case nir_intrinsic_shared_atomic_umax
:
7459 case nir_intrinsic_shared_atomic_and
:
7460 case nir_intrinsic_shared_atomic_or
:
7461 case nir_intrinsic_shared_atomic_xor
:
7462 case nir_intrinsic_shared_atomic_exchange
:
7463 case nir_intrinsic_shared_atomic_comp_swap
:
7464 case nir_intrinsic_shared_atomic_fadd
:
7465 visit_shared_atomic(ctx
, instr
);
7467 case nir_intrinsic_image_deref_load
:
7468 visit_image_load(ctx
, instr
);
7470 case nir_intrinsic_image_deref_store
:
7471 visit_image_store(ctx
, instr
);
7473 case nir_intrinsic_image_deref_atomic_add
:
7474 case nir_intrinsic_image_deref_atomic_umin
:
7475 case nir_intrinsic_image_deref_atomic_imin
:
7476 case nir_intrinsic_image_deref_atomic_umax
:
7477 case nir_intrinsic_image_deref_atomic_imax
:
7478 case nir_intrinsic_image_deref_atomic_and
:
7479 case nir_intrinsic_image_deref_atomic_or
:
7480 case nir_intrinsic_image_deref_atomic_xor
:
7481 case nir_intrinsic_image_deref_atomic_exchange
:
7482 case nir_intrinsic_image_deref_atomic_comp_swap
:
7483 visit_image_atomic(ctx
, instr
);
7485 case nir_intrinsic_image_deref_size
:
7486 visit_image_size(ctx
, instr
);
7488 case nir_intrinsic_load_ssbo
:
7489 visit_load_ssbo(ctx
, instr
);
7491 case nir_intrinsic_store_ssbo
:
7492 visit_store_ssbo(ctx
, instr
);
7494 case nir_intrinsic_load_global
:
7495 visit_load_global(ctx
, instr
);
7497 case nir_intrinsic_store_global
:
7498 visit_store_global(ctx
, instr
);
7500 case nir_intrinsic_global_atomic_add
:
7501 case nir_intrinsic_global_atomic_imin
:
7502 case nir_intrinsic_global_atomic_umin
:
7503 case nir_intrinsic_global_atomic_imax
:
7504 case nir_intrinsic_global_atomic_umax
:
7505 case nir_intrinsic_global_atomic_and
:
7506 case nir_intrinsic_global_atomic_or
:
7507 case nir_intrinsic_global_atomic_xor
:
7508 case nir_intrinsic_global_atomic_exchange
:
7509 case nir_intrinsic_global_atomic_comp_swap
:
7510 visit_global_atomic(ctx
, instr
);
7512 case nir_intrinsic_ssbo_atomic_add
:
7513 case nir_intrinsic_ssbo_atomic_imin
:
7514 case nir_intrinsic_ssbo_atomic_umin
:
7515 case nir_intrinsic_ssbo_atomic_imax
:
7516 case nir_intrinsic_ssbo_atomic_umax
:
7517 case nir_intrinsic_ssbo_atomic_and
:
7518 case nir_intrinsic_ssbo_atomic_or
:
7519 case nir_intrinsic_ssbo_atomic_xor
:
7520 case nir_intrinsic_ssbo_atomic_exchange
:
7521 case nir_intrinsic_ssbo_atomic_comp_swap
:
7522 visit_atomic_ssbo(ctx
, instr
);
7524 case nir_intrinsic_load_scratch
:
7525 visit_load_scratch(ctx
, instr
);
7527 case nir_intrinsic_store_scratch
:
7528 visit_store_scratch(ctx
, instr
);
7530 case nir_intrinsic_get_buffer_size
:
7531 visit_get_buffer_size(ctx
, instr
);
7533 case nir_intrinsic_control_barrier
: {
7534 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7535 /* GFX6 only (thanks to a hw bug workaround):
7536 * The real barrier instruction isn’t needed, because an entire patch
7537 * always fits into a single wave.
7542 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7543 bld
.sopp(aco_opcode::s_barrier
);
7547 case nir_intrinsic_memory_barrier_tcs_patch
:
7548 case nir_intrinsic_group_memory_barrier
:
7549 case nir_intrinsic_memory_barrier
:
7550 case nir_intrinsic_memory_barrier_buffer
:
7551 case nir_intrinsic_memory_barrier_image
:
7552 case nir_intrinsic_memory_barrier_shared
:
7553 emit_memory_barrier(ctx
, instr
);
7555 case nir_intrinsic_load_num_work_groups
: {
7556 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7557 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7558 emit_split_vector(ctx
, dst
, 3);
7561 case nir_intrinsic_load_local_invocation_id
: {
7562 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7563 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7564 emit_split_vector(ctx
, dst
, 3);
7567 case nir_intrinsic_load_work_group_id
: {
7568 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7569 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7570 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7571 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7572 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7573 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7574 emit_split_vector(ctx
, dst
, 3);
7577 case nir_intrinsic_load_local_invocation_index
: {
7578 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7580 /* The tg_size bits [6:11] contain the subgroup id,
7581 * we need this multiplied by the wave size, and then OR the thread id to it.
7583 if (ctx
->program
->wave_size
== 64) {
7584 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7585 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7586 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7587 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7589 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7590 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7591 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7592 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7596 case nir_intrinsic_load_subgroup_id
: {
7597 if (ctx
->stage
== compute_cs
) {
7598 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7599 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7601 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7605 case nir_intrinsic_load_subgroup_invocation
: {
7606 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7609 case nir_intrinsic_load_num_subgroups
: {
7610 if (ctx
->stage
== compute_cs
)
7611 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7612 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7614 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7617 case nir_intrinsic_ballot
: {
7618 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7619 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7620 Definition tmp
= bld
.def(dst
.regClass());
7621 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7622 if (instr
->src
[0].ssa
->bit_size
== 1) {
7623 assert(src
.regClass() == bld
.lm
);
7624 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7625 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7626 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7627 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7628 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7630 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7631 nir_print_instr(&instr
->instr
, stderr
);
7632 fprintf(stderr
, "\n");
7634 if (dst
.size() != bld
.lm
.size()) {
7635 /* Wave32 with ballot size set to 64 */
7636 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7638 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7641 case nir_intrinsic_shuffle
:
7642 case nir_intrinsic_read_invocation
: {
7643 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7644 if (!nir_src_is_divergent(instr
->src
[0])) {
7645 emit_uniform_subgroup(ctx
, instr
, src
);
7647 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7648 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7649 tid
= bld
.as_uniform(tid
);
7650 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7651 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7652 Temp tmp
= bld
.tmp(v1
);
7653 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7654 if (dst
.type() == RegType::vgpr
)
7655 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7657 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7658 } else if (src
.regClass() == v1
) {
7659 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7660 } else if (src
.regClass() == v2
) {
7661 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7662 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7663 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7664 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7665 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7666 emit_split_vector(ctx
, dst
, 2);
7667 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7668 assert(src
.regClass() == bld
.lm
);
7669 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7670 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7671 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7672 assert(src
.regClass() == bld
.lm
);
7674 if (ctx
->program
->chip_class
<= GFX7
)
7675 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7676 else if (ctx
->program
->wave_size
== 64)
7677 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7679 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7680 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7681 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7682 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7684 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7685 nir_print_instr(&instr
->instr
, stderr
);
7686 fprintf(stderr
, "\n");
7691 case nir_intrinsic_load_sample_id
: {
7692 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7693 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7696 case nir_intrinsic_load_sample_mask_in
: {
7697 visit_load_sample_mask_in(ctx
, instr
);
7700 case nir_intrinsic_read_first_invocation
: {
7701 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7702 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7703 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7705 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7707 } else if (src
.regClass() == v2
) {
7708 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7709 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7710 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7711 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7712 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7713 emit_split_vector(ctx
, dst
, 2);
7714 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7715 assert(src
.regClass() == bld
.lm
);
7716 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7717 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7718 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7719 } else if (src
.regClass() == s1
) {
7720 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7721 } else if (src
.regClass() == s2
) {
7722 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7724 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7725 nir_print_instr(&instr
->instr
, stderr
);
7726 fprintf(stderr
, "\n");
7730 case nir_intrinsic_vote_all
: {
7731 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7732 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7733 assert(src
.regClass() == bld
.lm
);
7734 assert(dst
.regClass() == bld
.lm
);
7736 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7737 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7738 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7741 case nir_intrinsic_vote_any
: {
7742 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7743 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7744 assert(src
.regClass() == bld
.lm
);
7745 assert(dst
.regClass() == bld
.lm
);
7747 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7748 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7751 case nir_intrinsic_reduce
:
7752 case nir_intrinsic_inclusive_scan
:
7753 case nir_intrinsic_exclusive_scan
: {
7754 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7755 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7756 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7757 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7758 nir_intrinsic_cluster_size(instr
) : 0;
7759 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7761 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7762 emit_uniform_subgroup(ctx
, instr
, src
);
7763 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7764 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7766 else if (op
== nir_op_iadd
)
7768 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7770 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7772 switch (instr
->intrinsic
) {
7773 case nir_intrinsic_reduce
:
7774 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7776 case nir_intrinsic_exclusive_scan
:
7777 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7779 case nir_intrinsic_inclusive_scan
:
7780 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7785 } else if (cluster_size
== 1) {
7786 bld
.copy(Definition(dst
), src
);
7788 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7790 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7794 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7795 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7810 unreachable("unknown reduction op");
7816 switch (instr
->intrinsic
) {
7817 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7818 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7819 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7821 unreachable("unknown reduce intrinsic");
7824 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7825 reduce
->operands
[0] = Operand(src
);
7826 // filled in by aco_reduce_assign.cpp, used internally as part of the
7828 assert(dst
.size() == 1 || dst
.size() == 2);
7829 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7830 reduce
->operands
[2] = Operand(v1
.as_linear());
7832 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7833 reduce
->definitions
[0] = Definition(tmp_dst
);
7834 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7835 reduce
->definitions
[2] = Definition();
7836 reduce
->definitions
[3] = Definition(scc
, s1
);
7837 reduce
->definitions
[4] = Definition();
7838 reduce
->reduce_op
= reduce_op
;
7839 reduce
->cluster_size
= cluster_size
;
7840 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7842 emit_wqm(ctx
, tmp_dst
, dst
);
7846 case nir_intrinsic_quad_broadcast
: {
7847 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7848 if (!nir_dest_is_divergent(instr
->dest
)) {
7849 emit_uniform_subgroup(ctx
, instr
, src
);
7851 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7852 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7853 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7855 if (instr
->dest
.ssa
.bit_size
== 1) {
7856 assert(src
.regClass() == bld
.lm
);
7857 assert(dst
.regClass() == bld
.lm
);
7858 uint32_t half_mask
= 0x11111111u
<< lane
;
7859 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7860 Temp tmp
= bld
.tmp(bld
.lm
);
7861 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7862 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7863 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7864 emit_wqm(ctx
, tmp
, dst
);
7865 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7866 Temp tmp
= bld
.tmp(v1
);
7867 if (ctx
->program
->chip_class
>= GFX8
)
7868 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7870 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7871 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7872 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7873 Temp tmp
= bld
.tmp(v1
);
7874 if (ctx
->program
->chip_class
>= GFX8
)
7875 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7877 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7879 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7880 if (ctx
->program
->chip_class
>= GFX8
)
7881 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7883 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7884 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7885 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7886 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7887 if (ctx
->program
->chip_class
>= GFX8
) {
7888 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7889 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7891 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7892 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7894 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7895 emit_split_vector(ctx
, dst
, 2);
7897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7898 nir_print_instr(&instr
->instr
, stderr
);
7899 fprintf(stderr
, "\n");
7904 case nir_intrinsic_quad_swap_horizontal
:
7905 case nir_intrinsic_quad_swap_vertical
:
7906 case nir_intrinsic_quad_swap_diagonal
:
7907 case nir_intrinsic_quad_swizzle_amd
: {
7908 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7909 if (!nir_dest_is_divergent(instr
->dest
)) {
7910 emit_uniform_subgroup(ctx
, instr
, src
);
7913 uint16_t dpp_ctrl
= 0;
7914 switch (instr
->intrinsic
) {
7915 case nir_intrinsic_quad_swap_horizontal
:
7916 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7918 case nir_intrinsic_quad_swap_vertical
:
7919 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7921 case nir_intrinsic_quad_swap_diagonal
:
7922 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7924 case nir_intrinsic_quad_swizzle_amd
:
7925 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7930 if (ctx
->program
->chip_class
< GFX8
)
7931 dpp_ctrl
|= (1 << 15);
7933 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7934 if (instr
->dest
.ssa
.bit_size
== 1) {
7935 assert(src
.regClass() == bld
.lm
);
7936 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7937 if (ctx
->program
->chip_class
>= GFX8
)
7938 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7940 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7941 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7942 emit_wqm(ctx
, tmp
, dst
);
7943 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7944 Temp tmp
= bld
.tmp(v1
);
7945 if (ctx
->program
->chip_class
>= GFX8
)
7946 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7948 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7949 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7950 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7951 Temp tmp
= bld
.tmp(v1
);
7952 if (ctx
->program
->chip_class
>= GFX8
)
7953 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7955 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7956 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7957 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7959 if (ctx
->program
->chip_class
>= GFX8
)
7960 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7962 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7963 emit_wqm(ctx
, tmp
, dst
);
7964 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7965 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7966 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7967 if (ctx
->program
->chip_class
>= GFX8
) {
7968 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7969 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7971 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7972 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7974 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7975 emit_split_vector(ctx
, dst
, 2);
7977 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7978 nir_print_instr(&instr
->instr
, stderr
);
7979 fprintf(stderr
, "\n");
7983 case nir_intrinsic_masked_swizzle_amd
: {
7984 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7985 if (!nir_dest_is_divergent(instr
->dest
)) {
7986 emit_uniform_subgroup(ctx
, instr
, src
);
7989 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7990 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7991 if (instr
->dest
.ssa
.bit_size
== 1) {
7992 assert(src
.regClass() == bld
.lm
);
7993 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7994 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7995 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7996 emit_wqm(ctx
, tmp
, dst
);
7997 } else if (dst
.regClass() == v1b
) {
7998 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7999 emit_extract_vector(ctx
, tmp
, 0, dst
);
8000 } else if (dst
.regClass() == v2b
) {
8001 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8002 emit_extract_vector(ctx
, tmp
, 0, dst
);
8003 } else if (dst
.regClass() == v1
) {
8004 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
8005 } else if (dst
.regClass() == v2
) {
8006 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8007 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8008 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
8009 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
8010 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8011 emit_split_vector(ctx
, dst
, 2);
8013 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8014 nir_print_instr(&instr
->instr
, stderr
);
8015 fprintf(stderr
, "\n");
8019 case nir_intrinsic_write_invocation_amd
: {
8020 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8021 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8022 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8023 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8024 if (dst
.regClass() == v1
) {
8025 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8026 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8027 } else if (dst
.regClass() == v2
) {
8028 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8029 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8030 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8031 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8032 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8033 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8034 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8035 emit_split_vector(ctx
, dst
, 2);
8037 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8038 nir_print_instr(&instr
->instr
, stderr
);
8039 fprintf(stderr
, "\n");
8043 case nir_intrinsic_mbcnt_amd
: {
8044 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8045 RegClass rc
= RegClass(src
.type(), 1);
8046 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8047 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8048 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8049 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8050 emit_wqm(ctx
, wqm_tmp
, dst
);
8053 case nir_intrinsic_load_helper_invocation
: {
8054 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8055 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8056 ctx
->block
->kind
|= block_kind_needs_lowering
;
8057 ctx
->program
->needs_exact
= true;
8060 case nir_intrinsic_is_helper_invocation
: {
8061 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8062 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8063 ctx
->block
->kind
|= block_kind_needs_lowering
;
8064 ctx
->program
->needs_exact
= true;
8067 case nir_intrinsic_demote
:
8068 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8070 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8071 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8072 ctx
->block
->kind
|= block_kind_uses_demote
;
8073 ctx
->program
->needs_exact
= true;
8075 case nir_intrinsic_demote_if
: {
8076 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8077 assert(src
.regClass() == bld
.lm
);
8078 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8079 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8081 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8082 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8083 ctx
->block
->kind
|= block_kind_uses_demote
;
8084 ctx
->program
->needs_exact
= true;
8087 case nir_intrinsic_first_invocation
: {
8088 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8089 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8092 case nir_intrinsic_shader_clock
: {
8094 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8095 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8096 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8097 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8100 case nir_intrinsic_load_vertex_id_zero_base
: {
8101 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8102 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8105 case nir_intrinsic_load_first_vertex
: {
8106 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8107 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8110 case nir_intrinsic_load_base_instance
: {
8111 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8112 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8115 case nir_intrinsic_load_instance_id
: {
8116 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8117 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8120 case nir_intrinsic_load_draw_id
: {
8121 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8122 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8125 case nir_intrinsic_load_invocation_id
: {
8126 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8128 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8129 if (ctx
->options
->chip_class
>= GFX10
)
8130 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8132 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8133 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8134 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8135 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8137 unreachable("Unsupported stage for load_invocation_id");
8142 case nir_intrinsic_load_primitive_id
: {
8143 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8145 switch (ctx
->shader
->info
.stage
) {
8146 case MESA_SHADER_GEOMETRY
:
8147 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8149 case MESA_SHADER_TESS_CTRL
:
8150 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8152 case MESA_SHADER_TESS_EVAL
:
8153 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8156 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8161 case nir_intrinsic_load_patch_vertices_in
: {
8162 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8163 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8165 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8166 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8169 case nir_intrinsic_emit_vertex_with_counter
: {
8170 visit_emit_vertex_with_counter(ctx
, instr
);
8173 case nir_intrinsic_end_primitive_with_counter
: {
8174 unsigned stream
= nir_intrinsic_stream_id(instr
);
8175 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8178 case nir_intrinsic_set_vertex_count
: {
8179 /* unused, the HW keeps track of this for us */
8183 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8184 nir_print_instr(&instr
->instr
, stderr
);
8185 fprintf(stderr
, "\n");
8193 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8194 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8195 enum glsl_base_type
*stype
)
8197 nir_deref_instr
*texture_deref_instr
= NULL
;
8198 nir_deref_instr
*sampler_deref_instr
= NULL
;
8201 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8202 switch (instr
->src
[i
].src_type
) {
8203 case nir_tex_src_texture_deref
:
8204 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8206 case nir_tex_src_sampler_deref
:
8207 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8209 case nir_tex_src_plane
:
8210 plane
= nir_src_as_int(instr
->src
[i
].src
);
8217 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8219 if (!sampler_deref_instr
)
8220 sampler_deref_instr
= texture_deref_instr
;
8223 assert(instr
->op
!= nir_texop_txf_ms
&&
8224 instr
->op
!= nir_texop_samples_identical
);
8225 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8226 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8227 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8228 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8229 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8230 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8232 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8235 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8237 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8238 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8239 Builder
bld(ctx
->program
, ctx
->block
);
8241 /* to avoid unnecessary moves, we split and recombine sampler and image */
8242 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8243 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8244 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8245 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8246 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8247 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8248 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8249 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8251 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8252 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8253 img
[0], img
[1], img
[2], img
[3],
8254 img
[4], img
[5], img
[6], img
[7]);
8255 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8256 samp
[0], samp
[1], samp
[2], samp
[3]);
8259 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8260 instr
->op
== nir_texop_samples_identical
))
8261 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8264 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8265 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8267 Builder
bld(ctx
->program
, ctx
->block
);
8269 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8270 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8271 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8273 Operand
neg_one(0xbf800000u
);
8274 Operand
one(0x3f800000u
);
8275 Operand
two(0x40000000u
);
8276 Operand
four(0x40800000u
);
8278 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8279 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8280 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8282 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8283 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8284 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8285 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8288 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8289 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8290 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8292 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8295 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8296 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8297 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8300 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8301 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8303 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8304 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8307 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8309 Builder
bld(ctx
->program
, ctx
->block
);
8310 Temp ma
, tc
, sc
, id
;
8313 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8315 // see comment in ac_prepare_cube_coords()
8316 if (ctx
->options
->chip_class
<= GFX8
)
8317 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8320 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8322 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8323 vop3a
->operands
[0] = Operand(ma
);
8324 vop3a
->abs
[0] = true;
8325 Temp invma
= bld
.tmp(v1
);
8326 vop3a
->definitions
[0] = Definition(invma
);
8327 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8329 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8331 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8333 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8335 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8337 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8340 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8341 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8343 for (unsigned i
= 0; i
< 2; i
++) {
8344 // see comment in ac_prepare_cube_coords()
8346 Temp deriv_sc
, deriv_tc
;
8347 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8348 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8350 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8352 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8353 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8354 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8355 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8356 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8357 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8358 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8361 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8362 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8366 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8373 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8375 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8377 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8378 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8381 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8382 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8383 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8387 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8389 Builder
bld(ctx
->program
, ctx
->block
);
8390 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8391 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8392 has_clamped_lod
= false;
8393 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8394 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8395 clamped_lod
= Temp();
8396 std::vector
<Temp
> coords
;
8397 std::vector
<Temp
> derivs
;
8398 nir_const_value
*sample_index_cv
= NULL
;
8399 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8400 enum glsl_base_type stype
;
8401 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8403 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8404 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8405 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8406 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8408 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8409 switch (instr
->src
[i
].src_type
) {
8410 case nir_tex_src_coord
: {
8411 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8412 for (unsigned i
= 0; i
< coord
.size(); i
++)
8413 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8416 case nir_tex_src_bias
:
8417 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8420 case nir_tex_src_lod
: {
8421 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8423 if (val
&& val
->f32
<= 0.0) {
8426 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8431 case nir_tex_src_min_lod
:
8432 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8433 has_clamped_lod
= true;
8435 case nir_tex_src_comparator
:
8436 if (instr
->is_shadow
) {
8437 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8441 case nir_tex_src_offset
:
8442 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8443 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8446 case nir_tex_src_ddx
:
8447 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8450 case nir_tex_src_ddy
:
8451 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8454 case nir_tex_src_ms_index
:
8455 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8456 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8457 has_sample_index
= true;
8459 case nir_tex_src_texture_offset
:
8460 case nir_tex_src_sampler_offset
:
8466 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8467 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8469 if (instr
->op
== nir_texop_texture_samples
) {
8470 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8472 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8473 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8474 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8476 Operand default_sample
= Operand(1u);
8477 if (ctx
->options
->robust_buffer_access
) {
8478 /* Extract the second dword of the descriptor, if it's
8479 * all zero, then it's a null descriptor.
8481 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8482 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8483 default_sample
= Operand(is_non_null_descriptor
);
8486 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8487 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8488 samples
, default_sample
, bld
.scc(is_msaa
));
8492 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8493 aco_ptr
<Instruction
> tmp_instr
;
8494 Temp acc
, pack
= Temp();
8496 uint32_t pack_const
= 0;
8497 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8498 if (!const_offset
[i
])
8500 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8503 if (offset
.type() == RegType::sgpr
) {
8504 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8505 if (const_offset
[i
])
8508 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8509 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8512 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8515 if (pack
== Temp()) {
8518 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8522 if (pack_const
&& pack
!= Temp())
8523 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8525 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8526 if (const_offset
[i
])
8529 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8530 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8533 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8536 if (pack
== Temp()) {
8539 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8543 if (pack_const
&& pack
!= Temp())
8544 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8546 if (pack_const
&& pack
== Temp())
8547 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8548 else if (pack
== Temp())
8554 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8555 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8557 /* pack derivatives */
8558 if (has_ddx
|| has_ddy
) {
8559 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8560 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8561 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8562 derivs
= {ddx
, zero
, ddy
, zero
};
8564 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8565 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8566 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8567 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8572 if (instr
->coord_components
> 1 &&
8573 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8575 instr
->op
!= nir_texop_txf
)
8576 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8578 if (instr
->coord_components
> 2 &&
8579 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8580 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8581 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8582 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8584 instr
->op
!= nir_texop_txf
&&
8585 instr
->op
!= nir_texop_txf_ms
&&
8586 instr
->op
!= nir_texop_fragment_fetch
&&
8587 instr
->op
!= nir_texop_fragment_mask_fetch
)
8588 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8590 if (ctx
->options
->chip_class
== GFX9
&&
8591 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8592 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8593 assert(coords
.size() > 0 && coords
.size() < 3);
8595 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8596 Operand((uint32_t) 0) :
8597 Operand((uint32_t) 0x3f000000)));
8600 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8602 if (instr
->op
== nir_texop_samples_identical
)
8603 resource
= fmask_ptr
;
8605 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8606 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8607 instr
->op
!= nir_texop_txs
&&
8608 instr
->op
!= nir_texop_fragment_fetch
&&
8609 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8610 assert(has_sample_index
);
8611 Operand
op(sample_index
);
8612 if (sample_index_cv
)
8613 op
= Operand(sample_index_cv
->u32
);
8614 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8617 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8618 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8619 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8620 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8625 /* Build tex instruction */
8626 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8627 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8628 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8630 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8633 /* gather4 selects the component by dmask and always returns vec4 */
8634 if (instr
->op
== nir_texop_tg4
) {
8635 assert(instr
->dest
.ssa
.num_components
== 4);
8636 if (instr
->is_shadow
)
8639 dmask
= 1 << instr
->component
;
8640 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8641 tmp_dst
= bld
.tmp(v4
);
8642 } else if (instr
->op
== nir_texop_samples_identical
) {
8643 tmp_dst
= bld
.tmp(v1
);
8644 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8645 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8648 aco_ptr
<MIMG_instruction
> tex
;
8649 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8651 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8653 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8654 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8657 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8658 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8660 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8661 tex
->operands
[0] = Operand(resource
);
8662 tex
->operands
[1] = Operand(s4
); /* no sampler */
8663 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8664 if (ctx
->options
->chip_class
== GFX9
&&
8665 instr
->op
== nir_texop_txs
&&
8666 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8668 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8669 } else if (instr
->op
== nir_texop_query_levels
) {
8670 tex
->dmask
= 1 << 3;
8675 tex
->definitions
[0] = Definition(tmp_dst
);
8677 tex
->can_reorder
= true;
8678 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8681 /* divide 3rd value by 6 by multiplying with magic number */
8682 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8683 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8684 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8685 assert(instr
->dest
.ssa
.num_components
== 3);
8686 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8687 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8688 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8689 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8694 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8698 Temp tg4_compare_cube_wa64
= Temp();
8700 if (tg4_integer_workarounds
) {
8701 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8702 tex
->operands
[0] = Operand(resource
);
8703 tex
->operands
[1] = Operand(s4
); /* no sampler */
8704 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8708 Temp size
= bld
.tmp(v2
);
8709 tex
->definitions
[0] = Definition(size
);
8710 tex
->can_reorder
= true;
8711 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8712 emit_split_vector(ctx
, size
, size
.size());
8715 for (unsigned i
= 0; i
< 2; i
++) {
8716 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8717 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8718 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8719 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8722 Temp new_coords
[2] = {
8723 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8724 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8727 if (tg4_integer_cube_workaround
) {
8728 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8729 Temp desc
[resource
.size()];
8730 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8731 Format::PSEUDO
, 1, resource
.size())};
8732 split
->operands
[0] = Operand(resource
);
8733 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8734 desc
[i
] = bld
.tmp(s1
);
8735 split
->definitions
[i
] = Definition(desc
[i
]);
8737 ctx
->block
->instructions
.emplace_back(std::move(split
));
8739 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8740 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8741 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8744 if (stype
== GLSL_TYPE_UINT
) {
8745 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8746 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8747 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8748 bld
.scc(compare_cube_wa
));
8750 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8751 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8752 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8753 bld
.scc(compare_cube_wa
));
8755 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8756 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8758 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8760 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8761 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8762 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8764 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8765 Format::PSEUDO
, resource
.size(), 1)};
8766 for (unsigned i
= 0; i
< resource
.size(); i
++)
8767 vec
->operands
[i
] = Operand(desc
[i
]);
8768 resource
= bld
.tmp(resource
.regClass());
8769 vec
->definitions
[0] = Definition(resource
);
8770 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8772 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8773 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8774 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8775 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8777 coords
[0] = new_coords
[0];
8778 coords
[1] = new_coords
[1];
8781 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8782 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8784 assert(coords
.size() == 1);
8785 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8789 op
= aco_opcode::buffer_load_format_x
; break;
8791 op
= aco_opcode::buffer_load_format_xy
; break;
8793 op
= aco_opcode::buffer_load_format_xyz
; break;
8795 op
= aco_opcode::buffer_load_format_xyzw
; break;
8797 unreachable("Tex instruction loads more than 4 components.");
8800 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8801 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8804 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8806 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8807 mubuf
->operands
[0] = Operand(resource
);
8808 mubuf
->operands
[1] = Operand(coords
[0]);
8809 mubuf
->operands
[2] = Operand((uint32_t) 0);
8810 mubuf
->definitions
[0] = Definition(tmp_dst
);
8811 mubuf
->idxen
= true;
8812 mubuf
->can_reorder
= true;
8813 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8815 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8819 /* gather MIMG address components */
8820 std::vector
<Temp
> args
;
8822 args
.emplace_back(offset
);
8824 args
.emplace_back(bias
);
8826 args
.emplace_back(compare
);
8828 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8830 args
.insert(args
.end(), coords
.begin(), coords
.end());
8831 if (has_sample_index
)
8832 args
.emplace_back(sample_index
);
8834 args
.emplace_back(lod
);
8835 if (has_clamped_lod
)
8836 args
.emplace_back(clamped_lod
);
8838 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8839 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8840 vec
->definitions
[0] = Definition(arg
);
8841 for (unsigned i
= 0; i
< args
.size(); i
++)
8842 vec
->operands
[i
] = Operand(args
[i
]);
8843 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8846 if (instr
->op
== nir_texop_txf
||
8847 instr
->op
== nir_texop_txf_ms
||
8848 instr
->op
== nir_texop_samples_identical
||
8849 instr
->op
== nir_texop_fragment_fetch
||
8850 instr
->op
== nir_texop_fragment_mask_fetch
) {
8851 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8852 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8853 tex
->operands
[0] = Operand(resource
);
8854 tex
->operands
[1] = Operand(s4
); /* no sampler */
8855 tex
->operands
[2] = Operand(arg
);
8860 tex
->definitions
[0] = Definition(tmp_dst
);
8861 tex
->can_reorder
= true;
8862 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8864 if (instr
->op
== nir_texop_samples_identical
) {
8865 assert(dmask
== 1 && dst
.regClass() == v1
);
8866 assert(dst
.id() != tmp_dst
.id());
8868 Temp tmp
= bld
.tmp(bld
.lm
);
8869 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8870 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8873 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8878 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8879 aco_opcode opcode
= aco_opcode::image_sample
;
8880 if (has_offset
) { /* image_sample_*_o */
8881 if (has_clamped_lod
) {
8883 opcode
= aco_opcode::image_sample_c_cl_o
;
8885 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8887 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8889 opcode
= aco_opcode::image_sample_cl_o
;
8891 opcode
= aco_opcode::image_sample_d_cl_o
;
8893 opcode
= aco_opcode::image_sample_b_cl_o
;
8895 } else if (has_compare
) {
8896 opcode
= aco_opcode::image_sample_c_o
;
8898 opcode
= aco_opcode::image_sample_c_d_o
;
8900 opcode
= aco_opcode::image_sample_c_b_o
;
8902 opcode
= aco_opcode::image_sample_c_lz_o
;
8904 opcode
= aco_opcode::image_sample_c_l_o
;
8906 opcode
= aco_opcode::image_sample_o
;
8908 opcode
= aco_opcode::image_sample_d_o
;
8910 opcode
= aco_opcode::image_sample_b_o
;
8912 opcode
= aco_opcode::image_sample_lz_o
;
8914 opcode
= aco_opcode::image_sample_l_o
;
8916 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8918 opcode
= aco_opcode::image_sample_c_cl
;
8920 opcode
= aco_opcode::image_sample_c_d_cl
;
8922 opcode
= aco_opcode::image_sample_c_b_cl
;
8924 opcode
= aco_opcode::image_sample_cl
;
8926 opcode
= aco_opcode::image_sample_d_cl
;
8928 opcode
= aco_opcode::image_sample_b_cl
;
8930 } else { /* no offset */
8932 opcode
= aco_opcode::image_sample_c
;
8934 opcode
= aco_opcode::image_sample_c_d
;
8936 opcode
= aco_opcode::image_sample_c_b
;
8938 opcode
= aco_opcode::image_sample_c_lz
;
8940 opcode
= aco_opcode::image_sample_c_l
;
8942 opcode
= aco_opcode::image_sample
;
8944 opcode
= aco_opcode::image_sample_d
;
8946 opcode
= aco_opcode::image_sample_b
;
8948 opcode
= aco_opcode::image_sample_lz
;
8950 opcode
= aco_opcode::image_sample_l
;
8954 if (instr
->op
== nir_texop_tg4
) {
8955 if (has_offset
) { /* image_gather4_*_o */
8957 opcode
= aco_opcode::image_gather4_c_lz_o
;
8959 opcode
= aco_opcode::image_gather4_c_l_o
;
8961 opcode
= aco_opcode::image_gather4_c_b_o
;
8963 opcode
= aco_opcode::image_gather4_lz_o
;
8965 opcode
= aco_opcode::image_gather4_l_o
;
8967 opcode
= aco_opcode::image_gather4_b_o
;
8971 opcode
= aco_opcode::image_gather4_c_lz
;
8973 opcode
= aco_opcode::image_gather4_c_l
;
8975 opcode
= aco_opcode::image_gather4_c_b
;
8977 opcode
= aco_opcode::image_gather4_lz
;
8979 opcode
= aco_opcode::image_gather4_l
;
8981 opcode
= aco_opcode::image_gather4_b
;
8984 } else if (instr
->op
== nir_texop_lod
) {
8985 opcode
= aco_opcode::image_get_lod
;
8988 /* we don't need the bias, sample index, compare value or offset to be
8989 * computed in WQM but if the p_create_vector copies the coordinates, then it
8990 * needs to be in WQM */
8991 if (ctx
->stage
== fragment_fs
&&
8992 !has_derivs
&& !has_lod
&& !level_zero
&&
8993 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8994 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8995 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8997 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8998 tex
->operands
[0] = Operand(resource
);
8999 tex
->operands
[1] = Operand(sampler
);
9000 tex
->operands
[2] = Operand(arg
);
9004 tex
->definitions
[0] = Definition(tmp_dst
);
9005 tex
->can_reorder
= true;
9006 ctx
->block
->instructions
.emplace_back(std::move(tex
));
9008 if (tg4_integer_cube_workaround
) {
9009 assert(tmp_dst
.id() != dst
.id());
9010 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
9012 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
9014 for (unsigned i
= 0; i
< dst
.size(); i
++) {
9015 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
9017 if (stype
== GLSL_TYPE_UINT
)
9018 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
9020 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
9021 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
9023 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
9024 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
9025 val
[0], val
[1], val
[2], val
[3]);
9027 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
9028 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
9033 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
9035 Temp tmp
= get_ssa_temp(ctx
, ssa
);
9036 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
9038 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
9039 if (ctx
->program
->wave_size
== 64)
9040 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
9042 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
9044 return Operand(tmp
);
9048 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9050 aco_ptr
<Pseudo_instruction
> phi
;
9051 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9052 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9054 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
9055 logical
|= ctx
->block
->kind
& block_kind_merge
;
9056 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9058 /* we want a sorted list of sources, since the predecessor list is also sorted */
9059 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9060 nir_foreach_phi_src(src
, instr
)
9061 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9063 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9064 unsigned num_operands
= 0;
9065 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9066 unsigned num_defined
= 0;
9067 unsigned cur_pred_idx
= 0;
9068 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9069 if (cur_pred_idx
< preds
.size()) {
9070 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9071 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9072 unsigned skipped
= 0;
9073 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9075 if (cur_pred_idx
+ skipped
< preds
.size()) {
9076 for (unsigned i
= 0; i
< skipped
; i
++)
9077 operands
[num_operands
++] = Operand(dst
.regClass());
9078 cur_pred_idx
+= skipped
;
9083 /* Handle missing predecessors at the end. This shouldn't happen with loop
9084 * headers and we can't ignore these sources for loop header phis. */
9085 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9088 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9089 operands
[num_operands
++] = op
;
9090 num_defined
+= !op
.isUndefined();
9092 /* handle block_kind_continue_or_break at loop exit blocks */
9093 while (cur_pred_idx
++ < preds
.size())
9094 operands
[num_operands
++] = Operand(dst
.regClass());
9096 /* If the loop ends with a break, still add a linear continue edge in case
9097 * that break is divergent or continue_or_break is used. We'll either remove
9098 * this operand later in visit_loop() if it's not necessary or replace the
9099 * undef with something correct. */
9100 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9101 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9102 nir_block
*last
= nir_loop_last_block(loop
);
9103 if (last
->successors
[0] != instr
->instr
.block
)
9104 operands
[num_operands
++] = Operand(RegClass());
9107 if (num_defined
== 0) {
9108 Builder
bld(ctx
->program
, ctx
->block
);
9109 if (dst
.regClass() == s1
) {
9110 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9111 } else if (dst
.regClass() == v1
) {
9112 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9114 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9115 for (unsigned i
= 0; i
< dst
.size(); i
++)
9116 vec
->operands
[i
] = Operand(0u);
9117 vec
->definitions
[0] = Definition(dst
);
9118 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9123 /* we can use a linear phi in some cases if one src is undef */
9124 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9125 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9127 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9128 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9129 assert(invert
->kind
& block_kind_invert
);
9131 unsigned then_block
= invert
->linear_preds
[0];
9133 Block
* insert_block
= NULL
;
9134 for (unsigned i
= 0; i
< num_operands
; i
++) {
9135 Operand op
= operands
[i
];
9136 if (op
.isUndefined())
9138 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9139 phi
->operands
[0] = op
;
9142 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9143 phi
->operands
[1] = Operand(dst
.regClass());
9144 phi
->definitions
[0] = Definition(dst
);
9145 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9149 /* try to scalarize vector phis */
9150 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9151 // TODO: scalarize linear phis on divergent ifs
9152 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9153 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9154 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9155 Operand src
= operands
[i
];
9156 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9157 can_scalarize
= false;
9159 if (can_scalarize
) {
9160 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9161 assert(dst
.size() % num_components
== 0);
9162 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9164 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9165 for (unsigned k
= 0; k
< num_components
; k
++) {
9166 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9167 for (unsigned i
= 0; i
< num_operands
; i
++) {
9168 Operand src
= operands
[i
];
9169 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9171 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9172 phi
->definitions
[0] = Definition(phi_dst
);
9173 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9174 new_vec
[k
] = phi_dst
;
9175 vec
->operands
[k
] = Operand(phi_dst
);
9177 vec
->definitions
[0] = Definition(dst
);
9178 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9179 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9184 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9185 for (unsigned i
= 0; i
< num_operands
; i
++)
9186 phi
->operands
[i
] = operands
[i
];
9187 phi
->definitions
[0] = Definition(dst
);
9188 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9192 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9194 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9196 assert(dst
.type() == RegType::sgpr
);
9198 if (dst
.size() == 1) {
9199 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9201 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9202 for (unsigned i
= 0; i
< dst
.size(); i
++)
9203 vec
->operands
[i
] = Operand(0u);
9204 vec
->definitions
[0] = Definition(dst
);
9205 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9209 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9211 Builder
bld(ctx
->program
, ctx
->block
);
9212 Block
*logical_target
;
9213 append_logical_end(ctx
->block
);
9214 unsigned idx
= ctx
->block
->index
;
9216 switch (instr
->type
) {
9217 case nir_jump_break
:
9218 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9219 add_logical_edge(idx
, logical_target
);
9220 ctx
->block
->kind
|= block_kind_break
;
9222 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9223 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9224 /* uniform break - directly jump out of the loop */
9225 ctx
->block
->kind
|= block_kind_uniform
;
9226 ctx
->cf_info
.has_branch
= true;
9227 bld
.branch(aco_opcode::p_branch
);
9228 add_linear_edge(idx
, logical_target
);
9231 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9232 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9234 case nir_jump_continue
:
9235 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9236 add_logical_edge(idx
, logical_target
);
9237 ctx
->block
->kind
|= block_kind_continue
;
9239 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9240 /* for potential uniform breaks after this continue,
9241 we must ensure that they are handled correctly */
9242 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9243 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9244 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9246 /* uniform continue - directly jump to the loop header */
9247 ctx
->block
->kind
|= block_kind_uniform
;
9248 ctx
->cf_info
.has_branch
= true;
9249 bld
.branch(aco_opcode::p_branch
);
9250 add_linear_edge(idx
, logical_target
);
9255 fprintf(stderr
, "Unknown NIR jump instr: ");
9256 nir_print_instr(&instr
->instr
, stderr
);
9257 fprintf(stderr
, "\n");
9261 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9262 ctx
->cf_info
.exec_potentially_empty_break
= true;
9263 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9266 /* remove critical edges from linear CFG */
9267 bld
.branch(aco_opcode::p_branch
);
9268 Block
* break_block
= ctx
->program
->create_and_insert_block();
9269 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9270 break_block
->kind
|= block_kind_uniform
;
9271 add_linear_edge(idx
, break_block
);
9272 /* the loop_header pointer might be invalidated by this point */
9273 if (instr
->type
== nir_jump_continue
)
9274 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9275 add_linear_edge(break_block
->index
, logical_target
);
9276 bld
.reset(break_block
);
9277 bld
.branch(aco_opcode::p_branch
);
9279 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9280 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9281 add_linear_edge(idx
, continue_block
);
9282 append_logical_start(continue_block
);
9283 ctx
->block
= continue_block
;
9287 void visit_block(isel_context
*ctx
, nir_block
*block
)
9289 nir_foreach_instr(instr
, block
) {
9290 switch (instr
->type
) {
9291 case nir_instr_type_alu
:
9292 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9294 case nir_instr_type_load_const
:
9295 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9297 case nir_instr_type_intrinsic
:
9298 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9300 case nir_instr_type_tex
:
9301 visit_tex(ctx
, nir_instr_as_tex(instr
));
9303 case nir_instr_type_phi
:
9304 visit_phi(ctx
, nir_instr_as_phi(instr
));
9306 case nir_instr_type_ssa_undef
:
9307 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9309 case nir_instr_type_deref
:
9311 case nir_instr_type_jump
:
9312 visit_jump(ctx
, nir_instr_as_jump(instr
));
9315 fprintf(stderr
, "Unknown NIR instr type: ");
9316 nir_print_instr(instr
, stderr
);
9317 fprintf(stderr
, "\n");
9322 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9323 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9328 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9329 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9331 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9332 RegClass rc
= vals
[0].regClass();
9334 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9336 unsigned next_pred
= 1;
9338 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9339 Block
& block
= ctx
->program
->blocks
[idx
];
9340 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9341 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9345 if (block
.kind
& block_kind_continue
) {
9346 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9351 bool all_same
= true;
9352 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9353 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9357 val
= vals
[block
.linear_preds
[0] - first
];
9359 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9360 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9361 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9362 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9363 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9364 phi
->definitions
[0] = Definition(val
.getTemp());
9365 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9367 vals
[idx
- first
] = val
;
9370 return vals
[last
- first
];
9373 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9375 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9376 append_logical_end(ctx
->block
);
9377 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9378 Builder
bld(ctx
->program
, ctx
->block
);
9379 bld
.branch(aco_opcode::p_branch
);
9380 unsigned loop_preheader_idx
= ctx
->block
->index
;
9382 Block loop_exit
= Block();
9383 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9384 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9386 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9387 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9388 loop_header
->kind
|= block_kind_loop_header
;
9389 add_edge(loop_preheader_idx
, loop_header
);
9390 ctx
->block
= loop_header
;
9392 /* emit loop body */
9393 unsigned loop_header_idx
= loop_header
->index
;
9394 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9395 append_logical_start(ctx
->block
);
9396 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9398 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9399 if (!ctx
->cf_info
.has_branch
) {
9400 append_logical_end(ctx
->block
);
9401 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9402 /* Discards can result in code running with an empty exec mask.
9403 * This would result in divergent breaks not ever being taken. As a
9404 * workaround, break the loop when the loop mask is empty instead of
9405 * always continuing. */
9406 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9407 unsigned block_idx
= ctx
->block
->index
;
9409 /* create helper blocks to avoid critical edges */
9410 Block
*break_block
= ctx
->program
->create_and_insert_block();
9411 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9412 break_block
->kind
= block_kind_uniform
;
9413 bld
.reset(break_block
);
9414 bld
.branch(aco_opcode::p_branch
);
9415 add_linear_edge(block_idx
, break_block
);
9416 add_linear_edge(break_block
->index
, &loop_exit
);
9418 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9419 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9420 continue_block
->kind
= block_kind_uniform
;
9421 bld
.reset(continue_block
);
9422 bld
.branch(aco_opcode::p_branch
);
9423 add_linear_edge(block_idx
, continue_block
);
9424 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9426 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9427 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9428 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9430 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9431 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9432 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9434 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9437 bld
.reset(ctx
->block
);
9438 bld
.branch(aco_opcode::p_branch
);
9441 /* Fixup phis in loop header from unreachable blocks.
9442 * has_branch/has_divergent_branch also indicates if the loop ends with a
9443 * break/continue instruction, but we don't emit those if unreachable=true */
9445 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9446 bool linear
= ctx
->cf_info
.has_branch
;
9447 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9448 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9449 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9450 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9451 /* the last operand should be the one that needs to be removed */
9452 instr
->operands
.pop_back();
9453 } else if (!is_phi(instr
)) {
9459 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9460 * and the previous one shouldn't both happen at once because a break in the
9461 * merge block would get CSE'd */
9462 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9463 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9464 Operand vals
[num_vals
];
9465 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9466 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9467 if (ctx
->cf_info
.has_branch
)
9468 instr
->operands
.pop_back();
9470 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9471 } else if (!is_phi(instr
)) {
9477 ctx
->cf_info
.has_branch
= false;
9479 // TODO: if the loop has not a single exit, we must add one °°
9480 /* emit loop successor block */
9481 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9482 append_logical_start(ctx
->block
);
9485 // TODO: check if it is beneficial to not branch on continues
9486 /* trim linear phis in loop header */
9487 for (auto&& instr
: loop_entry
->instructions
) {
9488 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9489 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9490 new_phi
->definitions
[0] = instr
->definitions
[0];
9491 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9492 new_phi
->operands
[i
] = instr
->operands
[i
];
9493 /* check that the remaining operands are all the same */
9494 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9495 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9496 instr
.swap(new_phi
);
9497 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9506 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9510 append_logical_end(ctx
->block
);
9511 ctx
->block
->kind
|= block_kind_branch
;
9513 /* branch to linear then block */
9514 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9515 aco_ptr
<Pseudo_branch_instruction
> branch
;
9516 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9517 branch
->operands
[0] = Operand(cond
);
9518 ctx
->block
->instructions
.push_back(std::move(branch
));
9520 ic
->BB_if_idx
= ctx
->block
->index
;
9521 ic
->BB_invert
= Block();
9522 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9523 /* Invert blocks are intentionally not marked as top level because they
9524 * are not part of the logical cfg. */
9525 ic
->BB_invert
.kind
|= block_kind_invert
;
9526 ic
->BB_endif
= Block();
9527 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9528 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9530 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9531 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9532 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9533 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9534 ctx
->cf_info
.parent_if
.is_divergent
= true;
9536 /* divergent branches use cbranch_execz */
9537 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9538 ctx
->cf_info
.exec_potentially_empty_break
= false;
9539 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9541 /** emit logical then block */
9542 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9543 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9544 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9545 ctx
->block
= BB_then_logical
;
9546 append_logical_start(BB_then_logical
);
9549 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9551 Block
*BB_then_logical
= ctx
->block
;
9552 append_logical_end(BB_then_logical
);
9553 /* branch from logical then block to invert block */
9554 aco_ptr
<Pseudo_branch_instruction
> branch
;
9555 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9556 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9557 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9558 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9559 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9560 BB_then_logical
->kind
|= block_kind_uniform
;
9561 assert(!ctx
->cf_info
.has_branch
);
9562 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9563 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9565 /** emit linear then block */
9566 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9567 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9568 BB_then_linear
->kind
|= block_kind_uniform
;
9569 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9570 /* branch from linear then block to invert block */
9571 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9572 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9573 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9575 /** emit invert merge block */
9576 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9577 ic
->invert_idx
= ctx
->block
->index
;
9579 /* branch to linear else block (skip else) */
9580 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9581 branch
->operands
[0] = Operand(ic
->cond
);
9582 ctx
->block
->instructions
.push_back(std::move(branch
));
9584 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9585 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9586 ic
->exec_potentially_empty_break_depth_old
=
9587 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9588 /* divergent branches use cbranch_execz */
9589 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9590 ctx
->cf_info
.exec_potentially_empty_break
= false;
9591 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9593 /** emit logical else block */
9594 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9595 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9596 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9597 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9598 ctx
->block
= BB_else_logical
;
9599 append_logical_start(BB_else_logical
);
9602 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9604 Block
*BB_else_logical
= ctx
->block
;
9605 append_logical_end(BB_else_logical
);
9607 /* branch from logical else block to endif block */
9608 aco_ptr
<Pseudo_branch_instruction
> branch
;
9609 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9610 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9611 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9612 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9613 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9614 BB_else_logical
->kind
|= block_kind_uniform
;
9616 assert(!ctx
->cf_info
.has_branch
);
9617 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9620 /** emit linear else block */
9621 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9622 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9623 BB_else_linear
->kind
|= block_kind_uniform
;
9624 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9626 /* branch from linear else block to endif block */
9627 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9628 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9629 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9632 /** emit endif merge block */
9633 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9634 append_logical_start(ctx
->block
);
9637 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9638 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9639 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9640 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9641 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9642 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9643 !ctx
->cf_info
.parent_if
.is_divergent
) {
9644 ctx
->cf_info
.exec_potentially_empty_break
= false;
9645 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9647 /* uniform control flow never has an empty exec-mask */
9648 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9649 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9650 ctx
->cf_info
.exec_potentially_empty_break
= false;
9651 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9655 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9657 assert(cond
.regClass() == s1
);
9659 append_logical_end(ctx
->block
);
9660 ctx
->block
->kind
|= block_kind_uniform
;
9662 aco_ptr
<Pseudo_branch_instruction
> branch
;
9663 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9664 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9665 branch
->operands
[0] = Operand(cond
);
9666 branch
->operands
[0].setFixed(scc
);
9667 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9669 ic
->BB_if_idx
= ctx
->block
->index
;
9670 ic
->BB_endif
= Block();
9671 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9672 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9674 ctx
->cf_info
.has_branch
= false;
9675 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9677 /** emit then block */
9678 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9679 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9680 add_edge(ic
->BB_if_idx
, BB_then
);
9681 append_logical_start(BB_then
);
9682 ctx
->block
= BB_then
;
9685 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9687 Block
*BB_then
= ctx
->block
;
9689 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9690 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9692 if (!ic
->uniform_has_then_branch
) {
9693 append_logical_end(BB_then
);
9694 /* branch from then block to endif block */
9695 aco_ptr
<Pseudo_branch_instruction
> branch
;
9696 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9697 BB_then
->instructions
.emplace_back(std::move(branch
));
9698 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9699 if (!ic
->then_branch_divergent
)
9700 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9701 BB_then
->kind
|= block_kind_uniform
;
9704 ctx
->cf_info
.has_branch
= false;
9705 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9707 /** emit else block */
9708 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9709 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9710 add_edge(ic
->BB_if_idx
, BB_else
);
9711 append_logical_start(BB_else
);
9712 ctx
->block
= BB_else
;
9715 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9717 Block
*BB_else
= ctx
->block
;
9719 if (!ctx
->cf_info
.has_branch
) {
9720 append_logical_end(BB_else
);
9721 /* branch from then block to endif block */
9722 aco_ptr
<Pseudo_branch_instruction
> branch
;
9723 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9724 BB_else
->instructions
.emplace_back(std::move(branch
));
9725 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9726 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9727 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9728 BB_else
->kind
|= block_kind_uniform
;
9731 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9732 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9734 /** emit endif merge block */
9735 if (!ctx
->cf_info
.has_branch
) {
9736 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9737 append_logical_start(ctx
->block
);
9741 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9743 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9744 Builder
bld(ctx
->program
, ctx
->block
);
9745 aco_ptr
<Pseudo_branch_instruction
> branch
;
9748 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9750 * Uniform conditionals are represented in the following way*) :
9752 * The linear and logical CFG:
9755 * BB_THEN (logical) BB_ELSE (logical)
9759 * *) Exceptions may be due to break and continue statements within loops
9760 * If a break/continue happens within uniform control flow, it branches
9761 * to the loop exit/entry block. Otherwise, it branches to the next
9765 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9766 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9767 cond
= bool_to_scalar_condition(ctx
, cond
);
9769 begin_uniform_if_then(ctx
, &ic
, cond
);
9770 visit_cf_list(ctx
, &if_stmt
->then_list
);
9772 begin_uniform_if_else(ctx
, &ic
);
9773 visit_cf_list(ctx
, &if_stmt
->else_list
);
9775 end_uniform_if(ctx
, &ic
);
9776 } else { /* non-uniform condition */
9778 * To maintain a logical and linear CFG without critical edges,
9779 * non-uniform conditionals are represented in the following way*) :
9784 * BB_THEN (logical) BB_THEN (linear)
9786 * BB_INVERT (linear)
9788 * BB_ELSE (logical) BB_ELSE (linear)
9795 * BB_THEN (logical) BB_ELSE (logical)
9799 * *) Exceptions may be due to break and continue statements within loops
9802 begin_divergent_if_then(ctx
, &ic
, cond
);
9803 visit_cf_list(ctx
, &if_stmt
->then_list
);
9805 begin_divergent_if_else(ctx
, &ic
);
9806 visit_cf_list(ctx
, &if_stmt
->else_list
);
9808 end_divergent_if(ctx
, &ic
);
9811 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9814 static bool visit_cf_list(isel_context
*ctx
,
9815 struct exec_list
*list
)
9817 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9818 switch (node
->type
) {
9819 case nir_cf_node_block
:
9820 visit_block(ctx
, nir_cf_node_as_block(node
));
9822 case nir_cf_node_if
:
9823 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9826 case nir_cf_node_loop
:
9827 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9830 unreachable("unimplemented cf list type");
9836 static void create_null_export(isel_context
*ctx
)
9838 /* Some shader stages always need to have exports.
9839 * So when there is none, we need to add a null export.
9842 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9843 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9844 Builder
bld(ctx
->program
, ctx
->block
);
9845 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9846 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9849 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9851 assert(ctx
->stage
== vertex_vs
||
9852 ctx
->stage
== tess_eval_vs
||
9853 ctx
->stage
== gs_copy_vs
||
9854 ctx
->stage
== ngg_vertex_gs
||
9855 ctx
->stage
== ngg_tess_eval_gs
);
9857 int offset
= (ctx
->stage
& sw_tes
)
9858 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9859 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9860 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9861 if (!is_pos
&& !mask
)
9863 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9865 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9866 exp
->enabled_mask
= mask
;
9867 for (unsigned i
= 0; i
< 4; ++i
) {
9868 if (mask
& (1 << i
))
9869 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9871 exp
->operands
[i
] = Operand(v1
);
9873 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9874 * Setting valid_mask=1 prevents it and has no other effect.
9876 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9878 exp
->compressed
= false;
9880 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9882 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9883 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9888 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9890 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9891 exp
->enabled_mask
= 0;
9892 for (unsigned i
= 0; i
< 4; ++i
)
9893 exp
->operands
[i
] = Operand(v1
);
9894 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9895 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9896 exp
->enabled_mask
|= 0x1;
9898 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9899 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9900 exp
->enabled_mask
|= 0x4;
9902 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9903 if (ctx
->options
->chip_class
< GFX9
) {
9904 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9905 exp
->enabled_mask
|= 0x8;
9907 Builder
bld(ctx
->program
, ctx
->block
);
9909 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9910 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9911 if (exp
->operands
[2].isTemp())
9912 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9914 exp
->operands
[2] = Operand(out
);
9915 exp
->enabled_mask
|= 0x4;
9918 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9920 exp
->compressed
= false;
9921 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9922 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9925 static void create_export_phis(isel_context
*ctx
)
9927 /* Used when exports are needed, but the output temps are defined in a preceding block.
9928 * This function will set up phis in order to access the outputs in the next block.
9931 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9932 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9933 ctx
->block
->instructions
.pop_back();
9935 Builder
bld(ctx
->program
, ctx
->block
);
9937 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9938 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9939 for (unsigned i
= 0; i
< 4; ++i
) {
9940 if (!(mask
& (1 << i
)))
9943 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9944 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9945 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9949 bld
.insert(std::move(logical_start
));
9952 static void create_vs_exports(isel_context
*ctx
)
9954 assert(ctx
->stage
== vertex_vs
||
9955 ctx
->stage
== tess_eval_vs
||
9956 ctx
->stage
== gs_copy_vs
||
9957 ctx
->stage
== ngg_vertex_gs
||
9958 ctx
->stage
== ngg_tess_eval_gs
);
9960 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9961 ? &ctx
->program
->info
->tes
.outinfo
9962 : &ctx
->program
->info
->vs
.outinfo
;
9964 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9965 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9966 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9969 if (ctx
->options
->key
.has_multiview_view_index
) {
9970 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9971 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9974 /* the order these position exports are created is important */
9976 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9977 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9978 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9979 exported_pos
= true;
9981 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9982 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9983 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9984 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9986 if (ctx
->export_clip_dists
) {
9987 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9988 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9989 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9990 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9993 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9994 if (i
< VARYING_SLOT_VAR0
&&
9995 i
!= VARYING_SLOT_LAYER
&&
9996 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9997 i
!= VARYING_SLOT_VIEWPORT
)
10000 export_vs_varying(ctx
, i
, false, NULL
);
10004 create_null_export(ctx
);
10007 static bool export_fs_mrt_z(isel_context
*ctx
)
10009 Builder
bld(ctx
->program
, ctx
->block
);
10010 unsigned enabled_channels
= 0;
10011 bool compr
= false;
10014 for (unsigned i
= 0; i
< 4; ++i
) {
10015 values
[i
] = Operand(v1
);
10018 /* Both stencil and sample mask only need 16-bits. */
10019 if (!ctx
->program
->info
->ps
.writes_z
&&
10020 (ctx
->program
->info
->ps
.writes_stencil
||
10021 ctx
->program
->info
->ps
.writes_sample_mask
)) {
10022 compr
= true; /* COMPR flag */
10024 if (ctx
->program
->info
->ps
.writes_stencil
) {
10025 /* Stencil should be in X[23:16]. */
10026 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10027 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
10028 enabled_channels
|= 0x3;
10031 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10032 /* SampleMask should be in Y[15:0]. */
10033 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10034 enabled_channels
|= 0xc;
10037 if (ctx
->program
->info
->ps
.writes_z
) {
10038 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
10039 enabled_channels
|= 0x1;
10042 if (ctx
->program
->info
->ps
.writes_stencil
) {
10043 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10044 enabled_channels
|= 0x2;
10047 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10048 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10049 enabled_channels
|= 0x4;
10053 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10054 * writemask component.
10056 if (ctx
->options
->chip_class
== GFX6
&&
10057 ctx
->options
->family
!= CHIP_OLAND
&&
10058 ctx
->options
->family
!= CHIP_HAINAN
) {
10059 enabled_channels
|= 0x1;
10062 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10063 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10068 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10070 Builder
bld(ctx
->program
, ctx
->block
);
10071 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10074 for (unsigned i
= 0; i
< 4; ++i
) {
10075 if (write_mask
& (1 << i
)) {
10076 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10078 values
[i
] = Operand(v1
);
10082 unsigned target
, col_format
;
10083 unsigned enabled_channels
= 0;
10084 aco_opcode compr_op
= (aco_opcode
)0;
10086 slot
-= FRAG_RESULT_DATA0
;
10087 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10088 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10090 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10091 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10092 bool is_16bit
= values
[0].regClass() == v2b
;
10094 switch (col_format
)
10096 case V_028714_SPI_SHADER_ZERO
:
10097 enabled_channels
= 0; /* writemask */
10098 target
= V_008DFC_SQ_EXP_NULL
;
10101 case V_028714_SPI_SHADER_32_R
:
10102 enabled_channels
= 1;
10105 case V_028714_SPI_SHADER_32_GR
:
10106 enabled_channels
= 0x3;
10109 case V_028714_SPI_SHADER_32_AR
:
10110 if (ctx
->options
->chip_class
>= GFX10
) {
10111 /* Special case: on GFX10, the outputs are different for 32_AR */
10112 enabled_channels
= 0x3;
10113 values
[1] = values
[3];
10114 values
[3] = Operand(v1
);
10116 enabled_channels
= 0x9;
10120 case V_028714_SPI_SHADER_FP16_ABGR
:
10121 enabled_channels
= 0x5;
10122 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10124 if (ctx
->options
->chip_class
>= GFX9
) {
10125 /* Pack the FP16 values together instead of converting them to
10126 * FP32 and back to FP16.
10127 * TODO: use p_create_vector and let the compiler optimizes.
10129 compr_op
= aco_opcode::v_pack_b32_f16
;
10131 for (unsigned i
= 0; i
< 4; i
++) {
10132 if ((write_mask
>> i
) & 1)
10133 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10139 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10140 enabled_channels
= 0x5;
10141 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10142 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10144 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10148 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10149 enabled_channels
= 0x5;
10150 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10151 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10153 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10157 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10158 enabled_channels
= 0x5;
10159 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10160 if (is_int8
|| is_int10
) {
10162 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10163 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10165 for (unsigned i
= 0; i
< 4; i
++) {
10166 if ((write_mask
>> i
) & 1) {
10167 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10168 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10172 } else if (is_16bit
) {
10173 for (unsigned i
= 0; i
< 4; i
++) {
10174 if ((write_mask
>> i
) & 1) {
10175 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10176 values
[i
] = Operand(tmp
);
10183 case V_028714_SPI_SHADER_SINT16_ABGR
:
10184 enabled_channels
= 0x5;
10185 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10186 if (is_int8
|| is_int10
) {
10188 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10189 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10190 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10191 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10193 for (unsigned i
= 0; i
< 4; i
++) {
10194 if ((write_mask
>> i
) & 1) {
10195 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10196 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10198 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10199 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10203 } else if (is_16bit
) {
10204 for (unsigned i
= 0; i
< 4; i
++) {
10205 if ((write_mask
>> i
) & 1) {
10206 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10207 values
[i
] = Operand(tmp
);
10213 case V_028714_SPI_SHADER_32_ABGR
:
10214 enabled_channels
= 0xF;
10221 if (target
== V_008DFC_SQ_EXP_NULL
)
10224 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10225 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10227 (col_format
== V_028714_SPI_SHADER_32_R
||
10228 col_format
== V_028714_SPI_SHADER_32_GR
||
10229 col_format
== V_028714_SPI_SHADER_32_AR
||
10230 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10231 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10232 for (int i
= 0; i
< 4; i
++) {
10233 if (!(write_mask
& (1 << i
)))
10236 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10237 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10238 bld
.copy(bld
.def(v1
), Operand(3u)));
10239 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10240 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10244 if ((bool) compr_op
) {
10245 for (int i
= 0; i
< 2; i
++) {
10246 /* check if at least one of the values to be compressed is enabled */
10247 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10249 enabled_channels
|= enabled
<< (i
*2);
10250 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10251 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10252 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10254 values
[i
] = Operand(v1
);
10257 values
[2] = Operand(v1
);
10258 values
[3] = Operand(v1
);
10260 for (int i
= 0; i
< 4; i
++)
10261 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10264 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10265 enabled_channels
, target
, (bool) compr_op
);
10269 static void create_fs_exports(isel_context
*ctx
)
10271 bool exported
= false;
10273 /* Export depth, stencil and sample mask. */
10274 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10275 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10276 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10277 exported
|= export_fs_mrt_z(ctx
);
10279 /* Export all color render targets. */
10280 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10281 if (ctx
->outputs
.mask
[i
])
10282 exported
|= export_fs_mrt_color(ctx
, i
);
10285 create_null_export(ctx
);
10288 static void write_tcs_tess_factors(isel_context
*ctx
)
10290 unsigned outer_comps
;
10291 unsigned inner_comps
;
10293 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10310 Builder
bld(ctx
->program
, ctx
->block
);
10312 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10313 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10314 bld
.sopp(aco_opcode::s_barrier
);
10316 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10317 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10319 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10320 if_context ic_invocation_id_is_zero
;
10321 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10322 bld
.reset(ctx
->block
);
10324 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10326 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10327 unsigned stride
= inner_comps
+ outer_comps
;
10328 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10332 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10334 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10336 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10337 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10338 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10340 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10341 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10343 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10344 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10345 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10346 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10349 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10350 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10351 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10352 unsigned tf_const_offset
= 0;
10354 if (ctx
->program
->chip_class
<= GFX8
) {
10355 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10356 if_context ic_rel_patch_id_is_zero
;
10357 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10358 bld
.reset(ctx
->block
);
10360 /* Store the dynamic HS control word. */
10361 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10362 bld
.mubuf(aco_opcode::buffer_store_dword
,
10363 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10364 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10365 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10366 tf_const_offset
+= 4;
10368 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10369 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10370 bld
.reset(ctx
->block
);
10373 assert(stride
== 2 || stride
== 4 || stride
== 6);
10374 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10375 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10377 /* Store to offchip for TES to read - only if TES reads them */
10378 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10379 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10380 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10382 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10383 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10385 if (likely(inner_comps
)) {
10386 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10387 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10391 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10392 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10395 static void emit_stream_output(isel_context
*ctx
,
10396 Temp
const *so_buffers
,
10397 Temp
const *so_write_offset
,
10398 const struct radv_stream_output
*output
)
10400 unsigned num_comps
= util_bitcount(output
->component_mask
);
10401 unsigned writemask
= (1 << num_comps
) - 1;
10402 unsigned loc
= output
->location
;
10403 unsigned buf
= output
->buffer
;
10405 assert(num_comps
&& num_comps
<= 4);
10406 if (!num_comps
|| num_comps
> 4)
10409 unsigned start
= ffs(output
->component_mask
) - 1;
10412 bool all_undef
= true;
10413 assert(ctx
->stage
& hw_vs
);
10414 for (unsigned i
= 0; i
< num_comps
; i
++) {
10415 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10416 all_undef
= all_undef
&& !out
[i
].id();
10421 while (writemask
) {
10423 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10424 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10425 /* GFX6 doesn't support storing vec3, split it. */
10426 writemask
|= 1u << (start
+ 2);
10430 unsigned offset
= output
->offset
+ start
* 4;
10432 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10433 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10434 for (int i
= 0; i
< count
; ++i
)
10435 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10436 vec
->definitions
[0] = Definition(write_data
);
10437 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10442 opcode
= aco_opcode::buffer_store_dword
;
10445 opcode
= aco_opcode::buffer_store_dwordx2
;
10448 opcode
= aco_opcode::buffer_store_dwordx3
;
10451 opcode
= aco_opcode::buffer_store_dwordx4
;
10454 unreachable("Unsupported dword count.");
10457 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10458 store
->operands
[0] = Operand(so_buffers
[buf
]);
10459 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10460 store
->operands
[2] = Operand((uint32_t) 0);
10461 store
->operands
[3] = Operand(write_data
);
10462 if (offset
> 4095) {
10463 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10464 Builder
bld(ctx
->program
, ctx
->block
);
10465 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10467 store
->offset
= offset
;
10469 store
->offen
= true;
10471 store
->dlc
= false;
10473 store
->can_reorder
= true;
10474 ctx
->block
->instructions
.emplace_back(std::move(store
));
10478 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10480 Builder
bld(ctx
->program
, ctx
->block
);
10482 Temp so_buffers
[4];
10483 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10484 for (unsigned i
= 0; i
< 4; i
++) {
10485 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10489 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10490 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10493 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10494 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10496 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10498 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10501 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10503 bld
.reset(ctx
->block
);
10505 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10507 Temp so_write_offset
[4];
10509 for (unsigned i
= 0; i
< 4; i
++) {
10510 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10515 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10516 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10517 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10518 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10520 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10522 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10523 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10524 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10525 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10529 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10530 struct radv_stream_output
*output
=
10531 &ctx
->program
->info
->so
.outputs
[i
];
10532 if (stream
!= output
->stream
)
10535 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10538 begin_divergent_if_else(ctx
, &ic
);
10539 end_divergent_if(ctx
, &ic
);
10542 } /* end namespace */
10544 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10546 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10547 Builder
bld(ctx
->program
, ctx
->block
);
10548 constexpr unsigned hs_idx
= 1u;
10549 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10550 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10551 Operand((8u << 16) | (hs_idx
* 8u)));
10552 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10554 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10556 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10557 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10558 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10559 ls_has_nonzero_hs_threads
);
10560 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10561 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10562 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10563 ls_has_nonzero_hs_threads
);
10564 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10565 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10566 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10567 ls_has_nonzero_hs_threads
);
10569 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10570 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10571 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10574 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10576 /* Split all arguments except for the first (ring_offsets) and the last
10577 * (exec) so that the dead channels don't stay live throughout the program.
10579 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10580 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10581 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10582 startpgm
->definitions
[i
].regClass().size());
10587 void handle_bc_optimize(isel_context
*ctx
)
10589 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10590 Builder
bld(ctx
->program
, ctx
->block
);
10591 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10592 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10593 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10594 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10595 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10596 if (uses_center
&& uses_centroid
) {
10597 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10598 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10600 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10602 for (unsigned i
= 0; i
< 2; i
++) {
10603 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10604 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10605 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10606 persp_centroid
, persp_center
, sel
);
10608 ctx
->persp_centroid
= bld
.tmp(v2
);
10609 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10610 Operand(new_coord
[0]), Operand(new_coord
[1]));
10611 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10614 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10616 for (unsigned i
= 0; i
< 2; i
++) {
10617 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10618 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10619 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10620 linear_centroid
, linear_center
, sel
);
10622 ctx
->linear_centroid
= bld
.tmp(v2
);
10623 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10624 Operand(new_coord
[0]), Operand(new_coord
[1]));
10625 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10630 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10632 Program
*program
= ctx
->program
;
10634 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10636 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10637 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10638 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10639 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10640 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10642 program
->next_fp_mode
.must_flush_denorms32
=
10643 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10644 program
->next_fp_mode
.must_flush_denorms16_64
=
10645 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10646 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10648 program
->next_fp_mode
.care_about_round32
=
10649 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10651 program
->next_fp_mode
.care_about_round16_64
=
10652 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10653 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10655 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10656 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10657 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10658 program
->next_fp_mode
.denorm16_64
= 0;
10660 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10662 /* preserving fp32 denorms is expensive, so only do it if asked */
10663 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10664 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10666 program
->next_fp_mode
.denorm32
= 0;
10668 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10669 program
->next_fp_mode
.round32
= fp_round_tz
;
10671 program
->next_fp_mode
.round32
= fp_round_ne
;
10673 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10674 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10676 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10678 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10681 void cleanup_cfg(Program
*program
)
10683 /* create linear_succs/logical_succs */
10684 for (Block
& BB
: program
->blocks
) {
10685 for (unsigned idx
: BB
.linear_preds
)
10686 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10687 for (unsigned idx
: BB
.logical_preds
)
10688 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10692 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10694 Builder
bld(ctx
->program
, ctx
->block
);
10696 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10697 Temp count
= i
== 0
10698 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10699 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10700 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10702 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10705 if (ctx
->program
->wave_size
== 64) {
10706 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10707 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10708 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10710 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10711 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10717 bool ngg_early_prim_export(isel_context
*ctx
)
10719 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10723 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10725 Builder
bld(ctx
->program
, ctx
->block
);
10727 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10728 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10730 /* Get the id of the current wave within the threadgroup (workgroup) */
10731 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10732 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10734 /* Execute the following code only on the first wave (wave id 0),
10735 * use the SCC def to tell if the wave id is zero or not.
10737 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10739 begin_uniform_if_then(ctx
, &ic
, cond
);
10740 begin_uniform_if_else(ctx
, &ic
);
10741 bld
.reset(ctx
->block
);
10743 /* Number of vertices output by VS/TES */
10744 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10745 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10746 /* Number of primitives output by VS/TES */
10747 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10748 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10750 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10751 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10752 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10754 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10755 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10757 end_uniform_if(ctx
, &ic
);
10759 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10760 bld
.reset(ctx
->block
);
10761 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10764 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10766 Builder
bld(ctx
->program
, ctx
->block
);
10768 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10769 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10772 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10775 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10776 assert(vtxindex
[i
].id());
10779 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10783 /* The initial edge flag is always false in tess eval shaders. */
10784 if (ctx
->stage
== ngg_vertex_gs
) {
10785 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10786 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10790 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10795 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10797 Builder
bld(ctx
->program
, ctx
->block
);
10798 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10800 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10801 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10802 false /* compressed */, true/* done */, false /* valid mask */);
10805 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10807 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10808 * These must always come before VS exports.
10810 * It is recommended to do these as early as possible. They can be at the beginning when
10811 * there is no SW GS and the shader doesn't write edge flags.
10815 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10816 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10818 Builder
bld(ctx
->program
, ctx
->block
);
10819 constexpr unsigned max_vertices_per_primitive
= 3;
10820 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10822 if (ctx
->stage
== ngg_vertex_gs
) {
10823 /* TODO: optimize for points & lines */
10824 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10825 if (ctx
->shader
->info
.tess
.point_mode
)
10826 num_vertices_per_primitive
= 1;
10827 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10828 num_vertices_per_primitive
= 2;
10830 unreachable("Unsupported NGG shader stage");
10833 Temp vtxindex
[max_vertices_per_primitive
];
10834 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10835 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10836 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10837 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10838 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10839 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10840 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10841 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10843 /* Export primitive data to the index buffer. */
10844 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10846 /* Export primitive ID. */
10847 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10848 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10849 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10850 Temp provoking_vtx_index
= vtxindex
[0];
10851 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10853 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10856 begin_divergent_if_else(ctx
, &ic
);
10857 end_divergent_if(ctx
, &ic
);
10860 void ngg_emit_nogs_output(isel_context
*ctx
)
10862 /* Emits NGG GS output, for stages that don't have SW GS. */
10865 Builder
bld(ctx
->program
, ctx
->block
);
10866 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10868 /* NGG streamout is currently disabled by default. */
10869 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10871 if (late_prim_export
) {
10872 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10873 create_export_phis(ctx
);
10874 /* Do what we need to do in the GS threads. */
10875 ngg_emit_nogs_gsthreads(ctx
);
10877 /* What comes next should be executed on ES threads. */
10878 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10879 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10880 bld
.reset(ctx
->block
);
10883 /* Export VS outputs */
10884 ctx
->block
->kind
|= block_kind_export_end
;
10885 create_vs_exports(ctx
);
10887 /* Export primitive ID */
10888 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10891 if (ctx
->stage
== ngg_vertex_gs
) {
10892 /* Wait for GS threads to store primitive ID in LDS. */
10893 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10894 bld
.sopp(aco_opcode::s_barrier
);
10896 /* Calculate LDS address where the GS threads stored the primitive ID. */
10897 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10898 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10899 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10900 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10901 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10902 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10904 /* Load primitive ID from LDS. */
10905 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10906 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10907 /* TES: Just use the patch ID as the primitive ID. */
10908 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10910 unreachable("unsupported NGG shader stage.");
10913 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10914 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10916 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10919 if (late_prim_export
) {
10920 begin_divergent_if_else(ctx
, &ic
);
10921 end_divergent_if(ctx
, &ic
);
10922 bld
.reset(ctx
->block
);
10926 void select_program(Program
*program
,
10927 unsigned shader_count
,
10928 struct nir_shader
*const *shaders
,
10929 ac_shader_config
* config
,
10930 struct radv_shader_args
*args
)
10932 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10933 if_context ic_merged_wave_info
;
10934 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10936 for (unsigned i
= 0; i
< shader_count
; i
++) {
10937 nir_shader
*nir
= shaders
[i
];
10938 init_context(&ctx
, nir
);
10940 setup_fp_mode(&ctx
, nir
);
10943 /* needs to be after init_context() for FS */
10944 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10945 append_logical_start(ctx
.block
);
10947 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10948 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10950 split_arguments(&ctx
, startpgm
);
10954 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10956 if (ngg_early_prim_export(&ctx
))
10957 ngg_emit_nogs_gsthreads(&ctx
);
10960 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10961 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10962 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10963 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10964 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10965 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10966 ctx
.stage
== tess_eval_geometry_gs
));
10968 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10969 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10970 if (check_merged_wave_info
) {
10971 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10972 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10976 Builder
bld(ctx
.program
, ctx
.block
);
10978 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10979 bld
.sopp(aco_opcode::s_barrier
);
10981 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10982 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10984 } else if (ctx
.stage
== geometry_gs
)
10985 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10987 if (ctx
.stage
== fragment_fs
)
10988 handle_bc_optimize(&ctx
);
10990 visit_cf_list(&ctx
, &func
->body
);
10992 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10993 emit_streamout(&ctx
, 0);
10995 if (ctx
.stage
& hw_vs
) {
10996 create_vs_exports(&ctx
);
10997 ctx
.block
->kind
|= block_kind_export_end
;
10998 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10999 ngg_emit_nogs_output(&ctx
);
11000 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
11001 Builder
bld(ctx
.program
, ctx
.block
);
11002 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
11003 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
11004 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
11005 write_tcs_tess_factors(&ctx
);
11008 if (ctx
.stage
== fragment_fs
) {
11009 create_fs_exports(&ctx
);
11010 ctx
.block
->kind
|= block_kind_export_end
;
11013 if (endif_merged_wave_info
) {
11014 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
11015 end_divergent_if(&ctx
, &ic_merged_wave_info
);
11018 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
11019 ngg_emit_nogs_output(&ctx
);
11021 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
11022 /* Outputs of the previous stage are inputs to the next stage */
11023 ctx
.inputs
= ctx
.outputs
;
11024 ctx
.outputs
= shader_io_state();
11028 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11030 append_logical_end(ctx
.block
);
11031 ctx
.block
->kind
|= block_kind_uniform
;
11032 Builder
bld(ctx
.program
, ctx
.block
);
11033 if (ctx
.program
->wb_smem_l1_on_end
)
11034 bld
.smem(aco_opcode::s_dcache_wb
, false);
11035 bld
.sopp(aco_opcode::s_endpgm
);
11037 cleanup_cfg(program
);
11040 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
11041 ac_shader_config
* config
,
11042 struct radv_shader_args
*args
)
11044 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
11046 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11048 add_startpgm(&ctx
);
11049 append_logical_start(ctx
.block
);
11051 Builder
bld(ctx
.program
, ctx
.block
);
11053 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11055 Operand
stream_id(0u);
11056 if (args
->shader_info
->so
.num_outputs
)
11057 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11058 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11060 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11062 std::stack
<Block
> endif_blocks
;
11064 for (unsigned stream
= 0; stream
< 4; stream
++) {
11065 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11068 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11069 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11072 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11074 unsigned BB_if_idx
= ctx
.block
->index
;
11075 Block BB_endif
= Block();
11076 if (!stream_id
.isConstant()) {
11078 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11079 append_logical_end(ctx
.block
);
11080 ctx
.block
->kind
|= block_kind_uniform
;
11081 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11083 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11085 ctx
.block
= ctx
.program
->create_and_insert_block();
11086 add_edge(BB_if_idx
, ctx
.block
);
11087 bld
.reset(ctx
.block
);
11088 append_logical_start(ctx
.block
);
11091 unsigned offset
= 0;
11092 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11093 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11096 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11097 unsigned length
= util_last_bit(output_usage_mask
);
11098 for (unsigned j
= 0; j
< length
; ++j
) {
11099 if (!(output_usage_mask
& (1 << j
)))
11102 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11103 Temp voffset
= vtx_offset
;
11104 if (const_offset
>= 4096u) {
11105 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11106 const_offset
%= 4096u;
11109 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11110 mubuf
->definitions
[0] = bld
.def(v1
);
11111 mubuf
->operands
[0] = Operand(gsvs_ring
);
11112 mubuf
->operands
[1] = Operand(voffset
);
11113 mubuf
->operands
[2] = Operand(0u);
11114 mubuf
->offen
= true;
11115 mubuf
->offset
= const_offset
;
11118 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11119 mubuf
->barrier
= barrier_none
;
11120 mubuf
->can_reorder
= true;
11122 ctx
.outputs
.mask
[i
] |= 1 << j
;
11123 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11125 bld
.insert(std::move(mubuf
));
11131 if (args
->shader_info
->so
.num_outputs
) {
11132 emit_streamout(&ctx
, stream
);
11133 bld
.reset(ctx
.block
);
11137 create_vs_exports(&ctx
);
11138 ctx
.block
->kind
|= block_kind_export_end
;
11141 if (!stream_id
.isConstant()) {
11142 append_logical_end(ctx
.block
);
11144 /* branch from then block to endif block */
11145 bld
.branch(aco_opcode::p_branch
);
11146 add_edge(ctx
.block
->index
, &BB_endif
);
11147 ctx
.block
->kind
|= block_kind_uniform
;
11149 /* emit else block */
11150 ctx
.block
= ctx
.program
->create_and_insert_block();
11151 add_edge(BB_if_idx
, ctx
.block
);
11152 bld
.reset(ctx
.block
);
11153 append_logical_start(ctx
.block
);
11155 endif_blocks
.push(std::move(BB_endif
));
11159 while (!endif_blocks
.empty()) {
11160 Block BB_endif
= std::move(endif_blocks
.top());
11161 endif_blocks
.pop();
11163 Block
*BB_else
= ctx
.block
;
11165 append_logical_end(BB_else
);
11166 /* branch from else block to endif block */
11167 bld
.branch(aco_opcode::p_branch
);
11168 add_edge(BB_else
->index
, &BB_endif
);
11169 BB_else
->kind
|= block_kind_uniform
;
11171 /** emit endif merge block */
11172 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11173 bld
.reset(ctx
.block
);
11174 append_logical_start(ctx
.block
);
11177 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11179 append_logical_end(ctx
.block
);
11180 ctx
.block
->kind
|= block_kind_uniform
;
11181 bld
.sopp(aco_opcode::s_endpgm
);
11183 cleanup_cfg(program
);