2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 #define isel_err(...) _isel_err(ctx, __FILE__, __LINE__, __VA_ARGS__)
43 static void _isel_err(isel_context
*ctx
, const char *file
, unsigned line
,
44 const nir_instr
*instr
, const char *msg
)
48 FILE *memf
= open_memstream(&out
, &outsize
);
50 fprintf(memf
, "%s: ", msg
);
51 nir_print_instr(instr
, memf
);
54 _aco_err(ctx
->program
, file
, line
, out
);
58 class loop_info_RAII
{
60 unsigned header_idx_old
;
62 bool divergent_cont_old
;
63 bool divergent_branch_old
;
64 bool divergent_if_old
;
67 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
69 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
70 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
71 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
72 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
75 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
76 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
77 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
78 ctx
->cf_info
.parent_if
.is_divergent
= false;
79 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
84 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
85 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
86 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
87 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
88 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
89 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
90 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
91 ctx
->cf_info
.exec_potentially_empty_discard
= false;
99 bool exec_potentially_empty_discard_old
;
100 bool exec_potentially_empty_break_old
;
101 uint16_t exec_potentially_empty_break_depth_old
;
105 bool uniform_has_then_branch
;
106 bool then_branch_divergent
;
111 static bool visit_cf_list(struct isel_context
*ctx
,
112 struct exec_list
*list
);
114 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
116 succ
->logical_preds
.emplace_back(pred_idx
);
120 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
122 succ
->linear_preds
.emplace_back(pred_idx
);
125 static void add_edge(unsigned pred_idx
, Block
*succ
)
127 add_logical_edge(pred_idx
, succ
);
128 add_linear_edge(pred_idx
, succ
);
131 static void append_logical_start(Block
*b
)
133 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
136 static void append_logical_end(Block
*b
)
138 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
141 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
143 assert(ctx
->allocated
[def
->index
].id());
144 return ctx
->allocated
[def
->index
];
147 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
148 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
150 Builder
bld(ctx
->program
, ctx
->block
);
151 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
152 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
154 if (ctx
->program
->wave_size
== 32) {
156 } else if (ctx
->program
->chip_class
<= GFX7
) {
157 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
160 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
165 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
167 Builder
bld(ctx
->program
, ctx
->block
);
170 dst
= bld
.tmp(src
.regClass());
172 assert(src
.size() == dst
.size());
174 if (ctx
->stage
!= fragment_fs
) {
178 bld
.copy(Definition(dst
), src
);
182 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
183 ctx
->program
->needs_wqm
|= program_needs_wqm
;
187 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
189 if (index
.regClass() == s1
)
190 return bld
.readlane(bld
.def(s1
), data
, index
);
192 if (ctx
->options
->chip_class
<= GFX7
) {
193 /* GFX6-7: there is no bpermute instruction */
194 Operand
index_op(index
);
195 Operand
input_data(data
);
196 index_op
.setLateKill(true);
197 input_data
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
200 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
201 /* GFX10 wave64 mode: emulate full-wave bpermute */
202 if (!ctx
->has_gfx10_wave64_bpermute
) {
203 ctx
->has_gfx10_wave64_bpermute
= true;
204 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
205 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
208 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
209 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
210 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
211 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
212 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
213 Operand
input_data(data
);
215 index_x4
.setLateKill(true);
216 input_data
.setLateKill(true);
217 same_half
.setLateKill(true);
219 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
221 /* GFX8-9 or GFX10 wave32: bpermute works normally */
222 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
223 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
227 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
229 if (ctx
->options
->chip_class
>= GFX8
) {
230 unsigned and_mask
= mask
& 0x1f;
231 unsigned or_mask
= (mask
>> 5) & 0x1f;
232 unsigned xor_mask
= (mask
>> 10) & 0x1f;
234 uint16_t dpp_ctrl
= 0xffff;
236 // TODO: we could use DPP8 for some swizzles
237 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
238 unsigned res
[4] = {0, 1, 2, 3};
239 for (unsigned i
= 0; i
< 4; i
++)
240 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
241 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
242 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
243 dpp_ctrl
= dpp_row_rr(8);
244 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
245 dpp_ctrl
= dpp_row_mirror
;
246 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
247 dpp_ctrl
= dpp_row_half_mirror
;
250 if (dpp_ctrl
!= 0xffff)
251 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
254 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
257 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
259 if (val
.type() == RegType::sgpr
) {
260 Builder
bld(ctx
->program
, ctx
->block
);
261 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
263 assert(val
.type() == RegType::vgpr
);
267 //assumes a != 0xffffffff
268 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
271 Builder
bld(ctx
->program
, ctx
->block
);
273 if (util_is_power_of_two_or_zero(b
)) {
274 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
278 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
280 assert(info
.multiplier
<= 0xffffffff);
282 bool pre_shift
= info
.pre_shift
!= 0;
283 bool increment
= info
.increment
!= 0;
284 bool multiply
= true;
285 bool post_shift
= info
.post_shift
!= 0;
287 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
288 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
292 Temp pre_shift_dst
= a
;
294 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
298 Temp increment_dst
= pre_shift_dst
;
300 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
301 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
304 Temp multiply_dst
= increment_dst
;
306 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
307 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
308 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
312 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
316 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
318 Builder
bld(ctx
->program
, ctx
->block
);
319 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
323 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
325 /* no need to extract the whole vector */
326 if (src
.regClass() == dst_rc
) {
331 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
332 Builder
bld(ctx
->program
, ctx
->block
);
333 auto it
= ctx
->allocated_vec
.find(src
.id());
334 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
335 if (it
->second
[idx
].regClass() == dst_rc
) {
336 return it
->second
[idx
];
338 assert(!dst_rc
.is_subdword());
339 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
340 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
344 if (dst_rc
.is_subdword())
345 src
= as_vgpr(ctx
, src
);
347 if (src
.bytes() == dst_rc
.bytes()) {
349 return bld
.copy(bld
.def(dst_rc
), src
);
351 Temp dst
= bld
.tmp(dst_rc
);
352 emit_extract_vector(ctx
, src
, idx
, dst
);
357 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
359 if (num_components
== 1)
361 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
364 if (num_components
> vec_src
.size()) {
365 if (vec_src
.type() == RegType::sgpr
) {
366 /* should still help get_alu_src() */
367 emit_split_vector(ctx
, vec_src
, vec_src
.size());
370 /* sub-dword split */
371 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
373 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
375 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
376 split
->operands
[0] = Operand(vec_src
);
377 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
378 for (unsigned i
= 0; i
< num_components
; i
++) {
379 elems
[i
] = {ctx
->program
->allocateId(), rc
};
380 split
->definitions
[i
] = Definition(elems
[i
]);
382 ctx
->block
->instructions
.emplace_back(std::move(split
));
383 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
386 /* This vector expansion uses a mask to determine which elements in the new vector
387 * come from the original vector. The other elements are undefined. */
388 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
390 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
395 Builder
bld(ctx
->program
, ctx
->block
);
396 if (num_components
== 1) {
397 if (dst
.type() == RegType::sgpr
)
398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
400 bld
.copy(Definition(dst
), vec_src
);
404 unsigned component_size
= dst
.size() / num_components
;
405 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
407 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
408 vec
->definitions
[0] = Definition(dst
);
410 for (unsigned i
= 0; i
< num_components
; i
++) {
411 if (mask
& (1 << i
)) {
412 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
413 if (dst
.type() == RegType::sgpr
)
414 src
= bld
.as_uniform(src
);
415 vec
->operands
[i
] = Operand(src
);
417 vec
->operands
[i
] = Operand(0u);
419 elems
[i
] = vec
->operands
[i
].getTemp();
421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
422 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
425 /* adjust misaligned small bit size loads */
426 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
428 Builder
bld(ctx
->program
, ctx
->block
);
430 Temp select
= Temp();
431 if (offset
.isConstant()) {
432 assert(offset
.constantValue() && offset
.constantValue() < 4);
433 shift
= Operand(offset
.constantValue() * 8);
435 /* bit_offset = 8 * (offset & 0x3) */
436 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
437 select
= bld
.tmp(s1
);
438 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
441 if (vec
.size() == 1) {
442 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
443 } else if (vec
.size() == 2) {
444 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
445 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
447 emit_split_vector(ctx
, dst
, 2);
449 emit_extract_vector(ctx
, tmp
, 0, dst
);
450 } else if (vec
.size() == 3 || vec
.size() == 4) {
451 Temp lo
= bld
.tmp(s2
), hi
;
452 if (vec
.size() == 3) {
453 /* this can happen if we use VMEM for a uniform load */
455 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
458 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
459 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
461 if (select
!= Temp())
462 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
463 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
464 Temp mid
= bld
.tmp(s1
);
465 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
466 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
467 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
468 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
469 emit_split_vector(ctx
, dst
, 2);
473 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
475 Builder
bld(ctx
->program
, ctx
->block
);
476 if (offset
.isTemp()) {
477 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
479 if (vec
.size() == 4) {
480 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
481 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
482 } else if (vec
.size() == 3) {
483 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
484 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
485 } else if (vec
.size() == 2) {
486 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
487 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
489 for (unsigned i
= 0; i
< dst
.size(); i
++)
490 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
494 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
496 offset
= Operand(0u);
499 unsigned num_components
= vec
.bytes() / component_size
;
500 if (vec
.regClass() == dst
.regClass()) {
501 assert(offset
.constantValue() == 0);
502 bld
.copy(Definition(dst
), vec
);
503 emit_split_vector(ctx
, dst
, num_components
);
507 emit_split_vector(ctx
, vec
, num_components
);
508 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
509 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
511 assert(offset
.constantValue() % component_size
== 0);
512 unsigned skip
= offset
.constantValue() / component_size
;
513 for (unsigned i
= skip
; i
< num_components
; i
++)
514 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
516 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
517 if (dst
.type() == RegType::vgpr
) {
518 num_components
= dst
.bytes() / component_size
;
519 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
520 for (unsigned i
= 0; i
< num_components
; i
++)
521 create_vec
->operands
[i
] = Operand(elems
[i
]);
522 create_vec
->definitions
[0] = Definition(dst
);
523 bld
.insert(std::move(create_vec
));
525 /* if dst is sgpr - split the src, but move the original to sgpr. */
527 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
528 byte_align_scalar(ctx
, vec
, offset
, dst
);
530 assert(dst
.size() == vec
.size());
531 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
534 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
537 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
539 Builder
bld(ctx
->program
, ctx
->block
);
541 dst
= bld
.tmp(bld
.lm
);
543 assert(val
.regClass() == s1
);
544 assert(dst
.regClass() == bld
.lm
);
546 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
549 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
551 Builder
bld(ctx
->program
, ctx
->block
);
555 assert(val
.regClass() == bld
.lm
);
556 assert(dst
.regClass() == s1
);
558 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
559 Temp tmp
= bld
.tmp(s1
);
560 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
561 return emit_wqm(ctx
, tmp
, dst
);
564 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
567 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
568 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
570 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
573 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
574 return bld
.copy(Definition(dst
), src
);
575 else if (dst
.bytes() < src
.bytes())
576 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
580 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
583 } else if (src
.regClass() == s1
) {
585 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
587 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
588 } else if (ctx
->options
->chip_class
>= GFX8
) {
589 assert(src_bits
!= 8 || src
.regClass() == v1b
);
590 assert(src_bits
!= 16 || src
.regClass() == v2b
);
591 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
592 sdwa
->operands
[0] = Operand(src
);
593 sdwa
->definitions
[0] = Definition(tmp
);
595 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
597 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
598 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
599 bld
.insert(std::move(sdwa
));
601 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
602 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
603 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
606 if (dst_bits
== 64) {
607 if (is_signed
&& dst
.regClass() == s2
) {
608 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
609 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
610 } else if (is_signed
&& dst
.regClass() == v2
) {
611 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
612 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
614 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
621 enum sgpr_extract_mode
{
627 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
629 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
630 unsigned src_size
= src
->src
.ssa
->bit_size
;
631 unsigned swizzle
= src
->swizzle
[0];
633 if (vec
.size() > 1) {
634 assert(src_size
== 16);
635 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
636 swizzle
= swizzle
& 1;
639 Builder
bld(ctx
->program
, ctx
->block
);
640 unsigned offset
= src_size
* swizzle
;
641 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
643 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
644 bld
.copy(Definition(tmp
), vec
);
645 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
646 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
647 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
648 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
649 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
650 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
652 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
653 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
656 if (dst
.regClass() == s2
)
657 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
662 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
664 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
665 return get_ssa_temp(ctx
, src
.src
.ssa
);
667 if (src
.src
.ssa
->num_components
== size
) {
668 bool identity_swizzle
= true;
669 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
670 if (src
.swizzle
[i
] != i
)
671 identity_swizzle
= false;
673 if (identity_swizzle
)
674 return get_ssa_temp(ctx
, src
.src
.ssa
);
677 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
678 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
679 assert(elem_size
> 0);
680 assert(vec
.bytes() % elem_size
== 0);
682 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
683 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
685 return extract_8_16_bit_sgpr_element(
686 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
689 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
691 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
694 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
695 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
696 for (unsigned i
= 0; i
< size
; ++i
) {
697 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
698 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
700 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
701 vec_instr
->definitions
[0] = Definition(dst
);
702 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
703 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
708 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
712 Builder
bld(ctx
->program
, ctx
->block
);
713 if (ptr
.type() == RegType::vgpr
)
714 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
715 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
716 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
719 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
721 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
722 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
723 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
724 sop2
->definitions
[0] = Definition(dst
);
725 if (instr
->no_unsigned_wrap
)
726 sop2
->definitions
[0].setNUW(true);
728 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
729 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
732 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
733 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
735 Builder
bld(ctx
->program
, ctx
->block
);
736 bld
.is_precise
= instr
->exact
;
738 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
739 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
740 if (src1
.type() == RegType::sgpr
) {
741 if (commutative
&& src0
.type() == RegType::vgpr
) {
746 src1
= as_vgpr(ctx
, src1
);
750 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
751 assert(dst
.size() == 1);
752 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
753 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
755 bld
.vop2(op
, Definition(dst
), src0
, src1
);
759 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
760 aco_opcode op
, Temp dst
)
762 Builder
bld(ctx
->program
, ctx
->block
);
763 bld
.is_precise
= instr
->exact
;
765 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
766 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
768 if (src1
.type() == RegType::sgpr
) {
769 assert(src0
.type() == RegType::vgpr
);
770 std::swap(src0
, src1
);
773 Temp src00
= bld
.tmp(src0
.type(), 1);
774 Temp src01
= bld
.tmp(src0
.type(), 1);
775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
776 Temp src10
= bld
.tmp(v1
);
777 Temp src11
= bld
.tmp(v1
);
778 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
779 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
780 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
781 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
784 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
785 bool flush_denorms
= false)
787 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
788 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
789 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
791 /* ensure that the instruction has at most 1 sgpr operand
792 * The optimizer will inline constants for us */
793 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
794 src0
= as_vgpr(ctx
, src0
);
795 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
796 src1
= as_vgpr(ctx
, src1
);
797 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
798 src2
= as_vgpr(ctx
, src2
);
800 Builder
bld(ctx
->program
, ctx
->block
);
801 bld
.is_precise
= instr
->exact
;
802 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
803 assert(dst
.size() == 1);
804 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
805 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
807 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
811 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
813 Builder
bld(ctx
->program
, ctx
->block
);
814 bld
.is_precise
= instr
->exact
;
815 if (dst
.type() == RegType::sgpr
)
816 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
817 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
819 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
822 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
824 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
825 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
826 assert(src0
.size() == src1
.size());
828 aco_ptr
<Instruction
> vopc
;
829 if (src1
.type() == RegType::sgpr
) {
830 if (src0
.type() == RegType::vgpr
) {
831 /* to swap the operands, we might also have to change the opcode */
833 case aco_opcode::v_cmp_lt_f16
:
834 op
= aco_opcode::v_cmp_gt_f16
;
836 case aco_opcode::v_cmp_ge_f16
:
837 op
= aco_opcode::v_cmp_le_f16
;
839 case aco_opcode::v_cmp_lt_i16
:
840 op
= aco_opcode::v_cmp_gt_i16
;
842 case aco_opcode::v_cmp_ge_i16
:
843 op
= aco_opcode::v_cmp_le_i16
;
845 case aco_opcode::v_cmp_lt_u16
:
846 op
= aco_opcode::v_cmp_gt_u16
;
848 case aco_opcode::v_cmp_ge_u16
:
849 op
= aco_opcode::v_cmp_le_u16
;
851 case aco_opcode::v_cmp_lt_f32
:
852 op
= aco_opcode::v_cmp_gt_f32
;
854 case aco_opcode::v_cmp_ge_f32
:
855 op
= aco_opcode::v_cmp_le_f32
;
857 case aco_opcode::v_cmp_lt_i32
:
858 op
= aco_opcode::v_cmp_gt_i32
;
860 case aco_opcode::v_cmp_ge_i32
:
861 op
= aco_opcode::v_cmp_le_i32
;
863 case aco_opcode::v_cmp_lt_u32
:
864 op
= aco_opcode::v_cmp_gt_u32
;
866 case aco_opcode::v_cmp_ge_u32
:
867 op
= aco_opcode::v_cmp_le_u32
;
869 case aco_opcode::v_cmp_lt_f64
:
870 op
= aco_opcode::v_cmp_gt_f64
;
872 case aco_opcode::v_cmp_ge_f64
:
873 op
= aco_opcode::v_cmp_le_f64
;
875 case aco_opcode::v_cmp_lt_i64
:
876 op
= aco_opcode::v_cmp_gt_i64
;
878 case aco_opcode::v_cmp_ge_i64
:
879 op
= aco_opcode::v_cmp_le_i64
;
881 case aco_opcode::v_cmp_lt_u64
:
882 op
= aco_opcode::v_cmp_gt_u64
;
884 case aco_opcode::v_cmp_ge_u64
:
885 op
= aco_opcode::v_cmp_le_u64
;
887 default: /* eq and ne are commutative */
894 src1
= as_vgpr(ctx
, src1
);
898 Builder
bld(ctx
->program
, ctx
->block
);
899 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
902 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
904 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
905 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
906 Builder
bld(ctx
->program
, ctx
->block
);
908 assert(dst
.regClass() == bld
.lm
);
909 assert(src0
.type() == RegType::sgpr
);
910 assert(src1
.type() == RegType::sgpr
);
911 assert(src0
.regClass() == src1
.regClass());
913 /* Emit the SALU comparison instruction */
914 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
915 /* Turn the result into a per-lane bool */
916 bool_to_vector_condition(ctx
, cmp
, dst
);
919 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
920 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
922 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
923 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
924 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
925 nir_dest_is_divergent(instr
->dest
.dest
) ||
926 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
927 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
928 aco_opcode op
= use_valu
? v_op
: s_op
;
929 assert(op
!= aco_opcode::num_opcodes
);
930 assert(dst
.regClass() == ctx
->program
->lane_mask
);
933 emit_vopc_instruction(ctx
, instr
, op
, dst
);
935 emit_sopc_instruction(ctx
, instr
, op
, dst
);
938 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
940 Builder
bld(ctx
->program
, ctx
->block
);
941 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
942 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
944 assert(dst
.regClass() == bld
.lm
);
945 assert(src0
.regClass() == bld
.lm
);
946 assert(src1
.regClass() == bld
.lm
);
948 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
951 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
953 Builder
bld(ctx
->program
, ctx
->block
);
954 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
955 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
956 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
958 assert(cond
.regClass() == bld
.lm
);
960 if (dst
.type() == RegType::vgpr
) {
961 aco_ptr
<Instruction
> bcsel
;
962 if (dst
.size() == 1) {
963 then
= as_vgpr(ctx
, then
);
964 els
= as_vgpr(ctx
, els
);
966 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
967 } else if (dst
.size() == 2) {
968 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
970 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
971 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
973 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
974 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
976 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
978 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
983 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
984 assert(dst
.regClass() == bld
.lm
);
985 assert(then
.regClass() == bld
.lm
);
986 assert(els
.regClass() == bld
.lm
);
989 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
990 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
991 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
992 assert(dst
.size() == then
.size());
993 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
994 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
996 isel_err(&instr
->instr
, "Unimplemented uniform bcsel bit size");
1001 /* divergent boolean bcsel
1002 * this implements bcsel on bools: dst = s0 ? s1 : s2
1003 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
1004 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
1006 if (cond
.id() != then
.id())
1007 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
1009 if (cond
.id() == els
.id())
1010 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
1012 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
1013 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
1016 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
1017 aco_opcode op
, uint32_t undo
)
1019 /* multiply by 16777216 to handle denormals */
1020 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1021 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1022 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1023 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1024 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1026 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1028 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1031 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1033 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1034 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1038 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1041 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1043 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1044 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1048 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1051 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1053 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1054 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1058 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1061 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1063 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1064 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1068 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1071 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1073 if (ctx
->options
->chip_class
>= GFX7
)
1074 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1076 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1077 /* TODO: create more efficient code! */
1078 if (val
.type() == RegType::sgpr
)
1079 val
= as_vgpr(ctx
, val
);
1081 /* Split the input value. */
1082 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1083 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1085 /* Extract the exponent and compute the unbiased value. */
1086 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1087 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1089 /* Extract the fractional part. */
1090 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1091 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1093 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1094 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1096 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1097 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1098 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1099 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1100 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1102 /* Get the sign bit. */
1103 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1105 /* Decide the operation to apply depending on the unbiased exponent. */
1106 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1107 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1108 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1109 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1110 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1111 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1113 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1116 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1118 if (ctx
->options
->chip_class
>= GFX7
)
1119 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1121 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1122 * lowered at NIR level for precision reasons). */
1123 Temp src0
= as_vgpr(ctx
, val
);
1125 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1126 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1128 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1129 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1130 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1132 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1133 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1134 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1135 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1137 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1138 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1140 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1142 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1143 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1145 return add
->definitions
[0].getTemp();
1148 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1150 if (!instr
->dest
.dest
.is_ssa
) {
1151 isel_err(&instr
->instr
, "nir alu dst not in ssa");
1154 Builder
bld(ctx
->program
, ctx
->block
);
1155 bld
.is_precise
= instr
->exact
;
1156 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1161 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1162 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1163 for (unsigned i
= 0; i
< num
; ++i
)
1164 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1166 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1167 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1168 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1169 for (unsigned i
= 0; i
< num
; ++i
) {
1170 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1171 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1173 vec
->operands
[i
] = Operand
{elems
[i
]};
1175 vec
->definitions
[0] = Definition(dst
);
1176 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1177 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1179 // TODO: that is a bit suboptimal..
1180 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1181 for (unsigned i
= 0; i
< num
- 1; ++i
)
1182 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1183 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1184 for (unsigned i
= 0; i
< num
; ++i
) {
1185 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1186 if (bit
% 32 == 0) {
1187 elems
[bit
/ 32] = elems
[i
];
1189 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1190 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1191 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1194 if (dst
.size() == 1)
1195 bld
.copy(Definition(dst
), elems
[0]);
1197 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1202 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1203 aco_ptr
<Instruction
> mov
;
1204 if (dst
.type() == RegType::sgpr
) {
1205 if (src
.type() == RegType::vgpr
)
1206 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1207 else if (src
.regClass() == s1
)
1208 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1209 else if (src
.regClass() == s2
)
1210 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1212 unreachable("wrong src register class for nir_op_imov");
1214 if (dst
.regClass() == v1
)
1215 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1216 else if (dst
.regClass() == v1b
||
1217 dst
.regClass() == v2b
||
1218 dst
.regClass() == v2
)
1219 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1221 unreachable("wrong src register class for nir_op_imov");
1226 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1227 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1228 assert(src
.regClass() == bld
.lm
);
1229 assert(dst
.regClass() == bld
.lm
);
1230 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1231 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1232 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1233 } else if (dst
.regClass() == v1
) {
1234 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1235 } else if (dst
.regClass() == v2
) {
1236 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1237 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1238 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1239 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1240 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1241 } else if (dst
.type() == RegType::sgpr
) {
1242 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1243 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1245 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1250 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1251 if (dst
.regClass() == v1
) {
1252 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1253 } else if (dst
.regClass() == s1
) {
1254 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1255 } else if (dst
.size() == 2) {
1256 Temp src0
= bld
.tmp(dst
.type(), 1);
1257 Temp src1
= bld
.tmp(dst
.type(), 1);
1258 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1260 if (dst
.regClass() == s2
) {
1261 Temp carry
= bld
.tmp(s1
);
1262 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1263 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1264 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1266 Temp lower
= bld
.tmp(v1
);
1267 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1268 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1269 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1272 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1277 if (dst
.regClass() == s1
) {
1278 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1279 } else if (dst
.regClass() == v1
) {
1280 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1281 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1283 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1287 case nir_op_isign
: {
1288 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1289 if (dst
.regClass() == s1
) {
1290 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1291 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1292 } else if (dst
.regClass() == s2
) {
1293 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1295 if (ctx
->program
->chip_class
>= GFX8
)
1296 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1298 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1299 /* SCC gets zero-extended to 64 bit */
1300 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1301 } else if (dst
.regClass() == v1
) {
1302 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1303 } else if (dst
.regClass() == v2
) {
1304 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1305 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1306 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1307 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1308 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1309 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1311 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1316 if (dst
.regClass() == v1
) {
1317 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1318 } else if (dst
.regClass() == s1
) {
1319 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1321 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1326 if (dst
.regClass() == v1
) {
1327 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1328 } else if (dst
.regClass() == s1
) {
1329 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1331 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1336 if (dst
.regClass() == v1
) {
1337 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1338 } else if (dst
.regClass() == s1
) {
1339 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1341 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1346 if (dst
.regClass() == v1
) {
1347 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1348 } else if (dst
.regClass() == s1
) {
1349 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1351 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1356 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1357 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1358 } else if (dst
.regClass() == v1
) {
1359 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1360 } else if (dst
.regClass() == v2
) {
1361 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1362 } else if (dst
.regClass() == s1
) {
1363 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1364 } else if (dst
.regClass() == s2
) {
1365 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1367 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1372 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1373 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1374 } else if (dst
.regClass() == v1
) {
1375 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1376 } else if (dst
.regClass() == v2
) {
1377 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1378 } else if (dst
.regClass() == s1
) {
1379 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1380 } else if (dst
.regClass() == s2
) {
1381 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1383 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1388 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1389 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1390 } else if (dst
.regClass() == v1
) {
1391 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1392 } else if (dst
.regClass() == v2
) {
1393 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1394 } else if (dst
.regClass() == s1
) {
1395 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1396 } else if (dst
.regClass() == s2
) {
1397 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1399 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1404 if (dst
.regClass() == v1
) {
1405 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1406 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1407 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1408 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1409 } else if (dst
.regClass() == v2
) {
1410 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1411 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1412 } else if (dst
.regClass() == s2
) {
1413 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1414 } else if (dst
.regClass() == s1
) {
1415 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1417 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1422 if (dst
.regClass() == v1
) {
1423 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1424 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1425 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1426 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1427 } else if (dst
.regClass() == v2
) {
1428 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1429 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1430 } else if (dst
.regClass() == s1
) {
1431 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1432 } else if (dst
.regClass() == s2
) {
1433 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1435 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1440 if (dst
.regClass() == v1
) {
1441 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1442 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1443 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1444 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1445 } else if (dst
.regClass() == v2
) {
1446 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1447 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1448 } else if (dst
.regClass() == s1
) {
1449 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1450 } else if (dst
.regClass() == s2
) {
1451 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1453 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1457 case nir_op_find_lsb
: {
1458 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1459 if (src
.regClass() == s1
) {
1460 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1461 } else if (src
.regClass() == v1
) {
1462 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1463 } else if (src
.regClass() == s2
) {
1464 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1466 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1470 case nir_op_ufind_msb
:
1471 case nir_op_ifind_msb
: {
1472 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1473 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1474 aco_opcode op
= src
.regClass() == s2
?
1475 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1476 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1477 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1479 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1480 Operand(src
.size() * 32u - 1u), msb_rev
);
1481 Temp msb
= sub
.def(0).getTemp();
1482 Temp carry
= sub
.def(1).getTemp();
1484 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1485 } else if (src
.regClass() == v1
) {
1486 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1487 Temp msb_rev
= bld
.tmp(v1
);
1488 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1489 Temp msb
= bld
.tmp(v1
);
1490 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1491 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1493 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1497 case nir_op_bitfield_reverse
: {
1498 if (dst
.regClass() == s1
) {
1499 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1500 } else if (dst
.regClass() == v1
) {
1501 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1503 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1508 if (dst
.regClass() == s1
) {
1509 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1513 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1514 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1515 if (dst
.regClass() == v1
) {
1516 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1520 assert(src0
.size() == 2 && src1
.size() == 2);
1521 Temp src00
= bld
.tmp(src0
.type(), 1);
1522 Temp src01
= bld
.tmp(dst
.type(), 1);
1523 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1524 Temp src10
= bld
.tmp(src1
.type(), 1);
1525 Temp src11
= bld
.tmp(dst
.type(), 1);
1526 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1528 if (dst
.regClass() == s2
) {
1529 Temp carry
= bld
.tmp(s1
);
1530 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1531 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1532 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1533 } else if (dst
.regClass() == v2
) {
1534 Temp dst0
= bld
.tmp(v1
);
1535 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1536 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1537 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1539 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1543 case nir_op_uadd_sat
: {
1544 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1545 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1546 if (dst
.regClass() == s1
) {
1547 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1548 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1550 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1551 } else if (dst
.regClass() == v1
) {
1552 if (ctx
->options
->chip_class
>= GFX9
) {
1553 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1554 add
->operands
[0] = Operand(src0
);
1555 add
->operands
[1] = Operand(src1
);
1556 add
->definitions
[0] = Definition(dst
);
1558 ctx
->block
->instructions
.emplace_back(std::move(add
));
1560 if (src1
.regClass() != v1
)
1561 std::swap(src0
, src1
);
1562 assert(src1
.regClass() == v1
);
1563 Temp tmp
= bld
.tmp(v1
);
1564 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1565 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1568 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1572 case nir_op_uadd_carry
: {
1573 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1574 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1575 if (dst
.regClass() == s1
) {
1576 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1579 if (dst
.regClass() == v1
) {
1580 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1581 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1585 Temp src00
= bld
.tmp(src0
.type(), 1);
1586 Temp src01
= bld
.tmp(dst
.type(), 1);
1587 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1588 Temp src10
= bld
.tmp(src1
.type(), 1);
1589 Temp src11
= bld
.tmp(dst
.type(), 1);
1590 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1591 if (dst
.regClass() == s2
) {
1592 Temp carry
= bld
.tmp(s1
);
1593 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1594 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1595 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1596 } else if (dst
.regClass() == v2
) {
1597 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1598 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1599 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1602 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1607 if (dst
.regClass() == s1
) {
1608 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1613 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1614 if (dst
.regClass() == v1
) {
1615 bld
.vsub32(Definition(dst
), src0
, src1
);
1619 Temp src00
= bld
.tmp(src0
.type(), 1);
1620 Temp src01
= bld
.tmp(dst
.type(), 1);
1621 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1622 Temp src10
= bld
.tmp(src1
.type(), 1);
1623 Temp src11
= bld
.tmp(dst
.type(), 1);
1624 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1625 if (dst
.regClass() == s2
) {
1626 Temp carry
= bld
.tmp(s1
);
1627 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1628 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1629 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1630 } else if (dst
.regClass() == v2
) {
1631 Temp lower
= bld
.tmp(v1
);
1632 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1633 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1634 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1636 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1640 case nir_op_usub_borrow
: {
1641 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1642 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1643 if (dst
.regClass() == s1
) {
1644 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1646 } else if (dst
.regClass() == v1
) {
1647 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1648 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1652 Temp src00
= bld
.tmp(src0
.type(), 1);
1653 Temp src01
= bld
.tmp(dst
.type(), 1);
1654 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1655 Temp src10
= bld
.tmp(src1
.type(), 1);
1656 Temp src11
= bld
.tmp(dst
.type(), 1);
1657 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1658 if (dst
.regClass() == s2
) {
1659 Temp borrow
= bld
.tmp(s1
);
1660 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1661 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1662 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1663 } else if (dst
.regClass() == v2
) {
1664 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1665 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1666 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1667 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1669 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1674 if (dst
.regClass() == v1
) {
1675 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1676 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1677 } else if (dst
.regClass() == s1
) {
1678 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1680 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1684 case nir_op_umul_high
: {
1685 if (dst
.regClass() == v1
) {
1686 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1687 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1688 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1689 } else if (dst
.regClass() == s1
) {
1690 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1691 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1692 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1694 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1698 case nir_op_imul_high
: {
1699 if (dst
.regClass() == v1
) {
1700 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1701 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1702 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1703 } else if (dst
.regClass() == s1
) {
1704 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1705 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1706 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1708 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1713 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1714 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1715 if (dst
.regClass() == v2b
) {
1716 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1717 } else if (dst
.regClass() == v1
) {
1718 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1719 } else if (dst
.regClass() == v2
) {
1720 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1722 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1727 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1728 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1729 if (dst
.regClass() == v2b
) {
1730 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1731 } else if (dst
.regClass() == v1
) {
1732 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1733 } else if (dst
.regClass() == v2
) {
1734 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1736 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1741 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1742 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1743 if (dst
.regClass() == v2b
) {
1744 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1747 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1748 } else if (dst
.regClass() == v1
) {
1749 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1750 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1752 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1753 } else if (dst
.regClass() == v2
) {
1754 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1755 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1756 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1759 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1764 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1765 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1766 if (dst
.regClass() == v2b
) {
1767 // TODO: check fp_mode.must_flush_denorms16_64
1768 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1769 } else if (dst
.regClass() == v1
) {
1770 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1771 } else if (dst
.regClass() == v2
) {
1772 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1773 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1774 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1776 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1779 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1784 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1785 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1786 if (dst
.regClass() == v2b
) {
1787 // TODO: check fp_mode.must_flush_denorms16_64
1788 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1789 } else if (dst
.regClass() == v1
) {
1790 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1791 } else if (dst
.regClass() == v2
) {
1792 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1793 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1794 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1796 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1799 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1803 case nir_op_cube_face_coord
: {
1804 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1805 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1806 emit_extract_vector(ctx
, in
, 1, v1
),
1807 emit_extract_vector(ctx
, in
, 2, v1
) };
1808 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1809 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1810 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1811 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1812 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1813 Operand(0x3f000000u
/*0.5*/),
1814 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
));
1815 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1816 Operand(0x3f000000u
/*0.5*/),
1817 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
));
1818 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1821 case nir_op_cube_face_index
: {
1822 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1823 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1824 emit_extract_vector(ctx
, in
, 1, v1
),
1825 emit_extract_vector(ctx
, in
, 2, v1
) };
1826 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1829 case nir_op_bcsel
: {
1830 emit_bcsel(ctx
, instr
, dst
);
1834 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1835 if (dst
.regClass() == v2b
) {
1836 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1837 } else if (dst
.regClass() == v1
) {
1838 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1839 } else if (dst
.regClass() == v2
) {
1840 /* Lowered at NIR level for precision reasons. */
1841 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1843 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1848 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1849 if (dst
.regClass() == v2b
) {
1850 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1851 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1852 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1853 } else if (dst
.regClass() == v1
) {
1854 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1855 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1856 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1857 } else if (dst
.regClass() == v2
) {
1858 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1859 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1860 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1862 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1863 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1865 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1870 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1871 if (dst
.regClass() == v2b
) {
1872 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1873 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1874 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1875 } else if (dst
.regClass() == v1
) {
1876 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1877 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1878 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1879 } else if (dst
.regClass() == v2
) {
1880 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1881 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1882 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1883 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1884 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1885 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1887 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1892 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1893 if (dst
.regClass() == v2b
) {
1894 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1895 } else if (dst
.regClass() == v1
) {
1896 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1897 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1898 // TODO: confirm that this holds under any circumstances
1899 } else if (dst
.regClass() == v2
) {
1900 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1901 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1904 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1908 case nir_op_flog2
: {
1909 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1910 if (dst
.regClass() == v2b
) {
1911 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1912 } else if (dst
.regClass() == v1
) {
1913 emit_log2(ctx
, bld
, Definition(dst
), src
);
1915 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1920 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1921 if (dst
.regClass() == v2b
) {
1922 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1923 } else if (dst
.regClass() == v1
) {
1924 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1925 } else if (dst
.regClass() == v2
) {
1926 /* Lowered at NIR level for precision reasons. */
1927 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1929 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1933 case nir_op_fexp2
: {
1934 if (dst
.regClass() == v2b
) {
1935 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1936 } else if (dst
.regClass() == v1
) {
1937 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1939 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1943 case nir_op_fsqrt
: {
1944 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1945 if (dst
.regClass() == v2b
) {
1946 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1947 } else if (dst
.regClass() == v1
) {
1948 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1949 } else if (dst
.regClass() == v2
) {
1950 /* Lowered at NIR level for precision reasons. */
1951 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1953 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1957 case nir_op_ffract
: {
1958 if (dst
.regClass() == v2b
) {
1959 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1960 } else if (dst
.regClass() == v1
) {
1961 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1962 } else if (dst
.regClass() == v2
) {
1963 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1965 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1969 case nir_op_ffloor
: {
1970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1971 if (dst
.regClass() == v2b
) {
1972 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1973 } else if (dst
.regClass() == v1
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1975 } else if (dst
.regClass() == v2
) {
1976 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1978 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1982 case nir_op_fceil
: {
1983 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1984 if (dst
.regClass() == v2b
) {
1985 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1986 } else if (dst
.regClass() == v1
) {
1987 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1988 } else if (dst
.regClass() == v2
) {
1989 if (ctx
->options
->chip_class
>= GFX7
) {
1990 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1992 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1993 /* trunc = trunc(src0)
1994 * if (src0 > 0.0 && src0 != trunc)
1997 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1998 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1999 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2000 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2001 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2002 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2003 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2006 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2010 case nir_op_ftrunc
: {
2011 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2012 if (dst
.regClass() == v2b
) {
2013 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2014 } else if (dst
.regClass() == v1
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2016 } else if (dst
.regClass() == v2
) {
2017 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2019 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2023 case nir_op_fround_even
: {
2024 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2025 if (dst
.regClass() == v2b
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2027 } else if (dst
.regClass() == v1
) {
2028 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2029 } else if (dst
.regClass() == v2
) {
2030 if (ctx
->options
->chip_class
>= GFX7
) {
2031 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2033 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2034 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2035 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2037 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2038 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2039 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2040 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2041 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2042 tmp
= sub
->definitions
[0].getTemp();
2044 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2045 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2046 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2047 Temp cond
= vop3
->definitions
[0].getTemp();
2049 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2050 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2051 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2052 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2054 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2057 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2063 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2064 aco_ptr
<Instruction
> norm
;
2065 if (dst
.regClass() == v2b
) {
2066 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2067 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2068 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2069 bld
.vop1(opcode
, Definition(dst
), tmp
);
2070 } else if (dst
.regClass() == v1
) {
2071 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2072 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2074 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2075 if (ctx
->options
->chip_class
< GFX9
)
2076 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2078 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2079 bld
.vop1(opcode
, Definition(dst
), tmp
);
2081 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2085 case nir_op_ldexp
: {
2086 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2087 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2088 if (dst
.regClass() == v2b
) {
2089 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2090 } else if (dst
.regClass() == v1
) {
2091 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2092 } else if (dst
.regClass() == v2
) {
2093 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2095 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2099 case nir_op_frexp_sig
: {
2100 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2101 if (dst
.regClass() == v2b
) {
2102 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2103 } else if (dst
.regClass() == v1
) {
2104 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2105 } else if (dst
.regClass() == v2
) {
2106 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2108 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2112 case nir_op_frexp_exp
: {
2113 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2114 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2115 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2116 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2117 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2118 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2119 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2120 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2121 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2123 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2127 case nir_op_fsign
: {
2128 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2129 if (dst
.regClass() == v2b
) {
2130 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2131 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2132 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2133 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2134 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2135 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2136 } else if (dst
.regClass() == v1
) {
2137 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2138 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2139 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2140 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2141 } else if (dst
.regClass() == v2
) {
2142 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2143 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2144 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2146 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2147 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2148 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2150 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2152 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2157 case nir_op_f2f16_rtne
: {
2158 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2159 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2160 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2161 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2162 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2163 * keep value numbering and the scheduler simpler.
2165 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2167 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2170 case nir_op_f2f16_rtz
: {
2171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2172 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2173 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2174 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2177 case nir_op_f2f32
: {
2178 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2179 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2180 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2181 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2183 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2187 case nir_op_f2f64
: {
2188 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2189 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2190 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2191 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2194 case nir_op_i2f16
: {
2195 assert(dst
.regClass() == v2b
);
2196 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2197 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2198 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2199 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2200 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2201 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2204 case nir_op_i2f32
: {
2205 assert(dst
.size() == 1);
2206 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2207 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2208 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2209 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2212 case nir_op_i2f64
: {
2213 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2214 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2215 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2216 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2217 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2218 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2220 RegClass rc
= RegClass(src
.type(), 1);
2221 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2222 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2223 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2224 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2225 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2226 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2229 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2233 case nir_op_u2f16
: {
2234 assert(dst
.regClass() == v2b
);
2235 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2236 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2237 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2238 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2239 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2240 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2243 case nir_op_u2f32
: {
2244 assert(dst
.size() == 1);
2245 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2246 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2247 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2249 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2250 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2251 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2255 case nir_op_u2f64
: {
2256 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2257 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2258 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2259 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2260 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2261 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2262 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2263 RegClass rc
= RegClass(src
.type(), 1);
2264 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2265 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2266 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2267 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2268 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2269 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2271 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2276 case nir_op_f2i16
: {
2277 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2278 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2279 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2280 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2282 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2286 case nir_op_f2u16
: {
2287 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2288 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2289 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2290 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2292 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2295 case nir_op_f2i32
: {
2296 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2297 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2298 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2299 if (dst
.type() == RegType::vgpr
) {
2300 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2302 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2303 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2305 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2306 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2310 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2314 case nir_op_f2u32
: {
2315 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2316 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2317 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2318 if (dst
.type() == RegType::vgpr
) {
2319 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2321 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2322 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2324 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2325 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2326 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2327 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2329 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2333 case nir_op_f2i64
: {
2334 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2335 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2336 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2338 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2339 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2340 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2341 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2342 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2343 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2344 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2345 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2346 Temp new_exponent
= bld
.tmp(v1
);
2347 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2348 if (ctx
->program
->chip_class
>= GFX8
)
2349 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2351 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2352 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2353 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2354 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2355 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2356 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2357 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2358 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2359 Temp new_lower
= bld
.tmp(v1
);
2360 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2361 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2362 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2364 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2365 if (src
.type() == RegType::vgpr
)
2366 src
= bld
.as_uniform(src
);
2367 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2368 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2369 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2370 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2371 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2372 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2373 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2374 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2375 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2376 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2377 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2378 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2379 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2380 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2381 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2382 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2383 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2384 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2385 Temp borrow
= bld
.tmp(s1
);
2386 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2387 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2388 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2390 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2391 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2392 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2393 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2394 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2395 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2396 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2397 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2398 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2399 if (dst
.type() == RegType::sgpr
) {
2400 lower
= bld
.as_uniform(lower
);
2401 upper
= bld
.as_uniform(upper
);
2403 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2406 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2410 case nir_op_f2u64
: {
2411 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2412 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2413 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2415 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2416 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2417 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2418 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2419 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2420 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2421 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2422 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2423 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2424 Temp new_exponent
= bld
.tmp(v1
);
2425 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2426 if (ctx
->program
->chip_class
>= GFX8
)
2427 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2429 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2430 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2431 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2432 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2433 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2434 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2435 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2436 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2438 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2439 if (src
.type() == RegType::vgpr
)
2440 src
= bld
.as_uniform(src
);
2441 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2442 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2443 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2444 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2445 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2446 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2447 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2448 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2449 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2450 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2451 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2452 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2453 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2454 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2455 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2456 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2457 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2458 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2460 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2461 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2462 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2463 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2464 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2465 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2466 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2467 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2468 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2469 if (dst
.type() == RegType::sgpr
) {
2470 lower
= bld
.as_uniform(lower
);
2471 upper
= bld
.as_uniform(upper
);
2473 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2476 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2480 case nir_op_b2f16
: {
2481 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2482 assert(src
.regClass() == bld
.lm
);
2484 if (dst
.regClass() == s1
) {
2485 src
= bool_to_scalar_condition(ctx
, src
);
2486 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2487 } else if (dst
.regClass() == v2b
) {
2488 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2489 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2491 unreachable("Wrong destination register class for nir_op_b2f16.");
2495 case nir_op_b2f32
: {
2496 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2497 assert(src
.regClass() == bld
.lm
);
2499 if (dst
.regClass() == s1
) {
2500 src
= bool_to_scalar_condition(ctx
, src
);
2501 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2502 } else if (dst
.regClass() == v1
) {
2503 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2505 unreachable("Wrong destination register class for nir_op_b2f32.");
2509 case nir_op_b2f64
: {
2510 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2511 assert(src
.regClass() == bld
.lm
);
2513 if (dst
.regClass() == s2
) {
2514 src
= bool_to_scalar_condition(ctx
, src
);
2515 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2516 } else if (dst
.regClass() == v2
) {
2517 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2518 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2519 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2521 unreachable("Wrong destination register class for nir_op_b2f64.");
2528 case nir_op_i2i64
: {
2529 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2530 /* no need to do the extract in get_alu_src() */
2531 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2532 sgpr_extract_sext
: sgpr_extract_undef
;
2533 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2535 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2536 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2543 case nir_op_u2u64
: {
2544 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2545 /* no need to do the extract in get_alu_src() */
2546 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2547 sgpr_extract_zext
: sgpr_extract_undef
;
2548 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2550 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2551 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2559 case nir_op_b2i64
: {
2560 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2561 assert(src
.regClass() == bld
.lm
);
2563 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2564 if (tmp
.regClass() == s1
) {
2565 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2566 bool_to_scalar_condition(ctx
, src
, tmp
);
2567 } else if (tmp
.type() == RegType::vgpr
) {
2568 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2570 unreachable("Invalid register class for b2i32");
2574 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2579 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2580 assert(dst
.regClass() == bld
.lm
);
2582 if (src
.type() == RegType::vgpr
) {
2583 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2584 assert(dst
.regClass() == bld
.lm
);
2585 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2586 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2588 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2590 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2591 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2593 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2594 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2596 bool_to_vector_condition(ctx
, tmp
, dst
);
2600 case nir_op_pack_64_2x32_split
: {
2601 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2602 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2604 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2607 case nir_op_unpack_64_2x32_split_x
:
2608 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2610 case nir_op_unpack_64_2x32_split_y
:
2611 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2613 case nir_op_unpack_32_2x16_split_x
:
2614 if (dst
.type() == RegType::vgpr
) {
2615 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2617 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2620 case nir_op_unpack_32_2x16_split_y
:
2621 if (dst
.type() == RegType::vgpr
) {
2622 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2624 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2627 case nir_op_pack_32_2x16_split
: {
2628 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2629 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2630 if (dst
.regClass() == v1
) {
2631 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2632 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2633 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2635 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2636 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2637 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2641 case nir_op_pack_half_2x16
: {
2642 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2644 if (dst
.regClass() == v1
) {
2645 Temp src0
= bld
.tmp(v1
);
2646 Temp src1
= bld
.tmp(v1
);
2647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2648 if (0 && (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)) {
2649 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2651 src0
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src0
);
2652 src1
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src1
);
2653 if (ctx
->program
->chip_class
>= GFX10
) {
2654 /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
2655 bld
.vop3(aco_opcode::v_pack_b32_f16
, Definition(dst
), src0
, src1
);
2657 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
), src0
, src1
);
2661 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2665 case nir_op_unpack_half_2x16_split_x
: {
2666 if (dst
.regClass() == v1
) {
2667 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2669 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2673 case nir_op_unpack_half_2x16_split_y
: {
2674 if (dst
.regClass() == v1
) {
2675 /* TODO: use SDWA here */
2676 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2677 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2679 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2683 case nir_op_fquantize2f16
: {
2684 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2685 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2688 if (ctx
->program
->chip_class
>= GFX8
) {
2689 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2690 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2691 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2693 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2694 * so compare the result and flush to 0 if it's smaller.
2696 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2697 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2698 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2699 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2700 cmp_res
= vop3
->definitions
[0].getTemp();
2703 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2704 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2705 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2707 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2712 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2713 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2715 if (dst
.regClass() == s1
) {
2716 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2717 } else if (dst
.regClass() == v1
) {
2718 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2720 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2724 case nir_op_bitfield_select
: {
2725 /* (mask & insert) | (~mask & base) */
2726 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2727 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2728 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2730 /* dst = (insert & bitmask) | (base & ~bitmask) */
2731 if (dst
.regClass() == s1
) {
2732 aco_ptr
<Instruction
> sop2
;
2733 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2734 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2736 if (const_insert
&& const_bitmask
) {
2737 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2739 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2740 lhs
= Operand(insert
);
2744 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2745 if (const_base
&& const_bitmask
) {
2746 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2748 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2749 rhs
= Operand(base
);
2752 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2754 } else if (dst
.regClass() == v1
) {
2755 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2756 base
= as_vgpr(ctx
, base
);
2757 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2758 insert
= as_vgpr(ctx
, insert
);
2760 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2763 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2769 if (dst
.bytes() != 4)
2770 unreachable("Unsupported BFE bit size");
2772 if (dst
.type() == RegType::sgpr
) {
2773 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2775 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2776 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2777 if (const_offset
&& const_bits
) {
2778 uint32_t extract
= (const_bits
->u32
<< 16) | (const_offset
->u32
& 0x1f);
2779 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
2780 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, Operand(extract
));
2784 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2785 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2786 if (instr
->op
== nir_op_ubfe
) {
2787 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b32
, bld
.def(s1
), bits
, offset
);
2788 Temp masked
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, mask
);
2789 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), masked
, offset
);
2791 Operand bits_op
= const_bits
? Operand(const_bits
->u32
<< 16) :
2792 bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2793 Operand offset_op
= const_offset
? Operand(const_offset
->u32
& 0x1fu
) :
2794 bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(0x1fu
));
2796 Temp extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits_op
, offset_op
);
2797 bld
.sop2(aco_opcode::s_bfe_i32
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2801 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::v_bfe_u32
: aco_opcode::v_bfe_i32
;
2802 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2806 case nir_op_bit_count
: {
2807 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2808 if (src
.regClass() == s1
) {
2809 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2810 } else if (src
.regClass() == v1
) {
2811 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2812 } else if (src
.regClass() == v2
) {
2813 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2814 emit_extract_vector(ctx
, src
, 1, v1
),
2815 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2816 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2817 } else if (src
.regClass() == s2
) {
2818 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2820 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2825 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2829 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2833 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2837 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2841 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2845 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2849 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2850 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2852 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2853 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2857 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2858 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2860 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2861 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2865 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2869 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2874 case nir_op_fddx_fine
:
2875 case nir_op_fddy_fine
:
2876 case nir_op_fddx_coarse
:
2877 case nir_op_fddy_coarse
: {
2878 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2879 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2880 if (instr
->op
== nir_op_fddx_fine
) {
2881 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2882 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2883 } else if (instr
->op
== nir_op_fddy_fine
) {
2884 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2885 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2887 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2888 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2889 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2891 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2895 if (ctx
->program
->chip_class
>= GFX8
) {
2896 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2897 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2899 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2900 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2901 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2903 emit_wqm(ctx
, tmp
, dst
, true);
2907 isel_err(&instr
->instr
, "Unknown NIR ALU instr");
2911 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2913 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2915 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2916 // which get truncated the lsb if double and msb if int
2917 // for now, we only use s_mov_b64 with 64bit inline constants
2918 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2919 assert(dst
.type() == RegType::sgpr
);
2921 Builder
bld(ctx
->program
, ctx
->block
);
2923 if (instr
->def
.bit_size
== 1) {
2924 assert(dst
.regClass() == bld
.lm
);
2925 int val
= instr
->value
[0].b
? -1 : 0;
2926 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2927 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2928 } else if (instr
->def
.bit_size
== 8) {
2929 /* ensure that the value is correctly represented in the low byte of the register */
2930 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2931 } else if (instr
->def
.bit_size
== 16) {
2932 /* ensure that the value is correctly represented in the low half of the register */
2933 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2934 } else if (dst
.size() == 1) {
2935 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2937 assert(dst
.size() != 1);
2938 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2939 if (instr
->def
.bit_size
== 64)
2940 for (unsigned i
= 0; i
< dst
.size(); i
++)
2941 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2943 for (unsigned i
= 0; i
< dst
.size(); i
++)
2944 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2946 vec
->definitions
[0] = Definition(dst
);
2947 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2951 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2953 uint32_t new_mask
= 0;
2954 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2955 if (mask
& (1u << i
))
2956 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2960 struct LoadEmitInfo
{
2963 unsigned num_components
;
2964 unsigned component_size
;
2965 Temp resource
= Temp(0, s1
);
2966 unsigned component_stride
= 0;
2967 unsigned const_offset
= 0;
2968 unsigned align_mul
= 0;
2969 unsigned align_offset
= 0;
2972 unsigned swizzle_component_size
= 0;
2973 memory_sync_info sync
;
2974 Temp soffset
= Temp(0, s1
);
2977 using LoadCallback
= Temp(*)(
2978 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
2979 unsigned align
, unsigned const_offset
, Temp dst_hint
);
2981 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
2982 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
2984 unsigned load_size
= info
->num_components
* info
->component_size
;
2985 unsigned component_size
= info
->component_size
;
2987 unsigned num_vals
= 0;
2988 Temp vals
[info
->dst
.bytes()];
2990 unsigned const_offset
= info
->const_offset
;
2992 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
2993 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
2995 unsigned bytes_read
= 0;
2996 while (bytes_read
< load_size
) {
2997 unsigned bytes_needed
= load_size
- bytes_read
;
2999 /* add buffer for unaligned loads */
3000 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3003 if ((bytes_needed
> 2 ||
3004 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3005 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3006 if (info
->component_stride
) {
3007 assert(supports_8bit_16bit_loads
&& "unimplemented");
3011 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3012 bytes_needed
= align(bytes_needed
, 4);
3019 if (info
->swizzle_component_size
)
3020 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3021 if (info
->component_stride
)
3022 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3024 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3026 /* reduce constant offset */
3027 Operand offset
= info
->offset
;
3028 unsigned reduced_const_offset
= const_offset
;
3029 bool remove_const_offset_completely
= need_to_align_offset
;
3030 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3031 unsigned to_add
= const_offset
;
3032 if (remove_const_offset_completely
) {
3033 reduced_const_offset
= 0;
3035 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3036 reduced_const_offset
%= max_const_offset_plus_one
;
3038 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3039 if (offset
.isConstant()) {
3040 offset
= Operand(offset
.constantValue() + to_add
);
3041 } else if (offset_tmp
.regClass() == s1
) {
3042 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3043 offset_tmp
, Operand(to_add
));
3044 } else if (offset_tmp
.regClass() == v1
) {
3045 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3047 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3048 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3049 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3051 if (offset_tmp
.regClass() == s2
) {
3052 Temp carry
= bld
.tmp(s1
);
3053 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3054 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3055 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3057 Temp new_lo
= bld
.tmp(v1
);
3058 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3059 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3060 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3065 /* align offset down if needed */
3066 Operand aligned_offset
= offset
;
3067 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3068 if (need_to_align_offset
) {
3070 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3071 if (offset
.isConstant()) {
3072 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3073 } else if (offset_tmp
.regClass() == s1
) {
3074 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3075 } else if (offset_tmp
.regClass() == s2
) {
3076 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3077 } else if (offset_tmp
.regClass() == v1
) {
3078 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3079 } else if (offset_tmp
.regClass() == v2
) {
3080 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3081 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3082 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3083 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3086 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3087 bld
.copy(bld
.def(s1
), aligned_offset
);
3089 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3090 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3092 /* the callback wrote directly to dst */
3093 if (val
== info
->dst
) {
3094 assert(num_vals
== 0);
3095 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3099 /* shift result right if needed */
3100 if (info
->component_size
< 4 && byte_align_loads
) {
3101 Operand
align((uint32_t)byte_align
);
3102 if (byte_align
== -1) {
3103 if (offset
.isConstant())
3104 align
= Operand(offset
.constantValue() % 4u);
3105 else if (offset
.size() == 2)
3106 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3111 assert(val
.bytes() >= load_size
&& "unimplemented");
3112 if (val
.type() == RegType::sgpr
)
3113 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3115 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3119 /* add result to list and advance */
3120 if (info
->component_stride
) {
3121 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3122 const_offset
+= info
->component_stride
;
3123 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3125 const_offset
+= val
.bytes();
3126 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3128 bytes_read
+= val
.bytes();
3129 vals
[num_vals
++] = val
;
3132 /* create array of components */
3133 unsigned components_split
= 0;
3134 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3135 bool has_vgprs
= false;
3136 for (unsigned i
= 0; i
< num_vals
;) {
3138 unsigned num_tmps
= 0;
3139 unsigned tmp_size
= 0;
3140 RegType reg_type
= RegType::sgpr
;
3141 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3142 if (vals
[i
].type() == RegType::vgpr
)
3143 reg_type
= RegType::vgpr
;
3144 tmp_size
+= vals
[i
].bytes();
3145 tmp
[num_tmps
++] = vals
[i
++];
3148 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3149 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3150 for (unsigned i
= 0; i
< num_tmps
; i
++)
3151 vec
->operands
[i
] = Operand(tmp
[i
]);
3152 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3153 vec
->definitions
[0] = Definition(tmp
[0]);
3154 bld
.insert(std::move(vec
));
3157 if (tmp
[0].bytes() % component_size
) {
3159 assert(i
== num_vals
);
3160 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3161 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3164 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3166 unsigned start
= components_split
;
3168 if (tmp_size
== elem_rc
.bytes()) {
3169 allocated_vec
[components_split
++] = tmp
[0];
3171 assert(tmp_size
% elem_rc
.bytes() == 0);
3172 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3173 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3174 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3175 Temp component
= bld
.tmp(elem_rc
);
3176 allocated_vec
[components_split
++] = component
;
3177 split
->definitions
[i
] = Definition(component
);
3179 split
->operands
[0] = Operand(tmp
[0]);
3180 bld
.insert(std::move(split
));
3183 /* try to p_as_uniform early so we can create more optimizable code and
3184 * also update allocated_vec */
3185 for (unsigned j
= start
; j
< components_split
; j
++) {
3186 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3187 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3188 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3192 /* concatenate components and p_as_uniform() result if needed */
3193 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3194 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3196 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3198 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3199 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3200 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3201 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3203 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3204 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3205 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3206 vec
->definitions
[0] = Definition(tmp
);
3207 bld
.insert(std::move(vec
));
3208 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3210 vec
->definitions
[0] = Definition(info
->dst
);
3211 bld
.insert(std::move(vec
));
3215 Operand
load_lds_size_m0(Builder
& bld
)
3217 /* TODO: m0 does not need to be initialized on GFX9+ */
3218 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3221 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3222 Temp offset
, unsigned bytes_needed
,
3223 unsigned align
, unsigned const_offset
,
3226 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3228 Operand m
= load_lds_size_m0(bld
);
3230 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3231 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3236 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3237 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3239 op
= aco_opcode::ds_read_b128
;
3240 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3243 op
= aco_opcode::ds_read2_b64
;
3244 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3246 op
= aco_opcode::ds_read_b96
;
3247 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3249 op
= aco_opcode::ds_read_b64
;
3250 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3253 op
= aco_opcode::ds_read2_b32
;
3254 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3256 op
= aco_opcode::ds_read_b32
;
3257 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3259 op
= aco_opcode::ds_read_u16
;
3262 op
= aco_opcode::ds_read_u8
;
3265 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3266 if (const_offset
>= max_offset_plus_one
) {
3267 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3268 const_offset
%= max_offset_plus_one
;
3272 const_offset
/= (size
/ 2u);
3274 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3275 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3278 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3280 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3281 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3284 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3289 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3291 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3292 Temp offset
, unsigned bytes_needed
,
3293 unsigned align
, unsigned const_offset
,
3298 if (bytes_needed
<= 4) {
3300 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3301 } else if (bytes_needed
<= 8) {
3303 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3304 } else if (bytes_needed
<= 16) {
3306 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3307 } else if (bytes_needed
<= 32) {
3309 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3312 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3314 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3315 if (info
->resource
.id()) {
3316 load
->operands
[0] = Operand(info
->resource
);
3317 load
->operands
[1] = Operand(offset
);
3319 load
->operands
[0] = Operand(offset
);
3320 load
->operands
[1] = Operand(0u);
3322 RegClass
rc(RegType::sgpr
, size
);
3323 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3324 load
->definitions
[0] = Definition(val
);
3325 load
->glc
= info
->glc
;
3326 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3327 load
->sync
= info
->sync
;
3328 bld
.insert(std::move(load
));
3332 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3334 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3335 Temp offset
, unsigned bytes_needed
,
3336 unsigned align_
, unsigned const_offset
,
3339 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3340 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3342 if (info
->soffset
.id()) {
3343 if (soffset
.isTemp())
3344 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3345 soffset
= Operand(info
->soffset
);
3348 unsigned bytes_size
= 0;
3350 if (bytes_needed
== 1 || align_
% 2) {
3352 op
= aco_opcode::buffer_load_ubyte
;
3353 } else if (bytes_needed
== 2 || align_
% 4) {
3355 op
= aco_opcode::buffer_load_ushort
;
3356 } else if (bytes_needed
<= 4) {
3358 op
= aco_opcode::buffer_load_dword
;
3359 } else if (bytes_needed
<= 8) {
3361 op
= aco_opcode::buffer_load_dwordx2
;
3362 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3364 op
= aco_opcode::buffer_load_dwordx3
;
3367 op
= aco_opcode::buffer_load_dwordx4
;
3369 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3370 mubuf
->operands
[0] = Operand(info
->resource
);
3371 mubuf
->operands
[1] = vaddr
;
3372 mubuf
->operands
[2] = soffset
;
3373 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3374 mubuf
->glc
= info
->glc
;
3375 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3376 mubuf
->sync
= info
->sync
;
3377 mubuf
->offset
= const_offset
;
3378 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3379 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3380 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3381 mubuf
->definitions
[0] = Definition(val
);
3382 bld
.insert(std::move(mubuf
));
3387 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3388 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3390 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3392 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3393 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3395 if (addr
.type() == RegType::vgpr
)
3396 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3397 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3400 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3401 Temp offset
, unsigned bytes_needed
,
3402 unsigned align_
, unsigned const_offset
,
3405 unsigned bytes_size
= 0;
3406 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3407 bool global
= bld
.program
->chip_class
>= GFX9
;
3409 if (bytes_needed
== 1) {
3411 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3412 } else if (bytes_needed
== 2) {
3414 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3415 } else if (bytes_needed
<= 4) {
3417 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3418 } else if (bytes_needed
<= 8) {
3420 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3421 } else if (bytes_needed
<= 12 && !mubuf
) {
3423 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3426 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3428 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3429 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3431 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3432 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3433 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3434 mubuf
->operands
[2] = Operand(0u);
3435 mubuf
->glc
= info
->glc
;
3438 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3439 mubuf
->disable_wqm
= false;
3440 mubuf
->sync
= info
->sync
;
3441 mubuf
->definitions
[0] = Definition(val
);
3442 bld
.insert(std::move(mubuf
));
3444 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3446 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3447 flat
->operands
[0] = Operand(offset
);
3448 flat
->operands
[1] = Operand(s1
);
3449 flat
->glc
= info
->glc
;
3450 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3451 flat
->sync
= info
->sync
;
3453 flat
->definitions
[0] = Definition(val
);
3454 bld
.insert(std::move(flat
));
3460 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3462 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3463 Temp address
, unsigned base_offset
, unsigned align
)
3465 assert(util_is_power_of_two_nonzero(align
));
3467 Builder
bld(ctx
->program
, ctx
->block
);
3469 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3470 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3471 info
.align_mul
= align
;
3472 info
.align_offset
= 0;
3473 info
.sync
= memory_sync_info(storage_shared
);
3474 info
.const_offset
= base_offset
;
3475 emit_lds_load(ctx
, bld
, &info
);
3480 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3485 Builder
bld(ctx
->program
, ctx
->block
);
3487 ASSERTED
bool is_subdword
= false;
3488 for (unsigned i
= 0; i
< count
; i
++)
3489 is_subdword
|= offsets
[i
] % 4;
3490 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3491 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3493 /* count == 1 fast path */
3495 if (dst_type
== RegType::sgpr
)
3496 dst
[0] = bld
.as_uniform(src
);
3498 dst
[0] = as_vgpr(ctx
, src
);
3502 for (unsigned i
= 0; i
< count
- 1; i
++)
3503 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3504 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3506 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3507 src
= as_vgpr(ctx
, src
);
3509 /* use allocated_vec if possible */
3510 auto it
= ctx
->allocated_vec
.find(src
.id());
3511 if (it
!= ctx
->allocated_vec
.end()) {
3512 if (!it
->second
[0].id())
3514 unsigned elem_size
= it
->second
[0].bytes();
3515 assert(src
.bytes() % elem_size
== 0);
3517 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3518 if (!it
->second
[i
].id())
3522 for (unsigned i
= 0; i
< count
; i
++) {
3523 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3527 for (unsigned i
= 0; i
< count
; i
++) {
3528 unsigned start_idx
= offsets
[i
] / elem_size
;
3529 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3530 if (op_count
== 1) {
3531 if (dst_type
== RegType::sgpr
)
3532 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3534 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3538 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3539 for (unsigned j
= 0; j
< op_count
; j
++) {
3540 Temp tmp
= it
->second
[start_idx
+ j
];
3541 if (dst_type
== RegType::sgpr
)
3542 tmp
= bld
.as_uniform(tmp
);
3543 vec
->operands
[j
] = Operand(tmp
);
3545 vec
->definitions
[0] = Definition(dst
[i
]);
3546 bld
.insert(std::move(vec
));
3554 if (dst_type
== RegType::sgpr
)
3555 src
= bld
.as_uniform(src
);
3558 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3559 split
->operands
[0] = Operand(src
);
3560 for (unsigned i
= 0; i
< count
; i
++)
3561 split
->definitions
[i
] = Definition(dst
[i
]);
3562 bld
.insert(std::move(split
));
3565 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3566 int *start
, int *count
)
3568 unsigned start_elem
= ffs(todo_mask
) - 1;
3569 bool skip
= !(mask
& (1 << start_elem
));
3571 mask
= ~mask
& todo_mask
;
3575 u_bit_scan_consecutive_range(&mask
, start
, count
);
3580 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3582 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3585 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3586 Temp address
, unsigned base_offset
, unsigned align
)
3588 assert(util_is_power_of_two_nonzero(align
));
3589 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3591 Builder
bld(ctx
->program
, ctx
->block
);
3592 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3593 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3595 unsigned write_count
= 0;
3596 Temp write_datas
[32];
3597 unsigned offsets
[32];
3598 aco_opcode opcodes
[32];
3600 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3602 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3605 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3606 offsets
[write_count
] = offset
;
3607 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3609 advance_write_mask(&todo
, offset
, bytes
);
3613 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3614 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3615 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3616 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3618 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3619 aco_opcode op
= aco_opcode::num_opcodes
;
3620 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3621 op
= aco_opcode::ds_write_b128
;
3623 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3624 op
= aco_opcode::ds_write_b96
;
3626 } else if (bytes
>= 8 && aligned8
) {
3627 op
= aco_opcode::ds_write_b64
;
3629 } else if (bytes
>= 4 && aligned4
) {
3630 op
= aco_opcode::ds_write_b32
;
3632 } else if (bytes
>= 2 && aligned2
) {
3633 op
= aco_opcode::ds_write_b16
;
3635 } else if (bytes
>= 1) {
3636 op
= aco_opcode::ds_write_b8
;
3642 offsets
[write_count
] = offset
;
3643 opcodes
[write_count
] = op
;
3645 advance_write_mask(&todo
, offset
, bytes
);
3648 Operand m
= load_lds_size_m0(bld
);
3650 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3652 for (unsigned i
= 0; i
< write_count
; i
++) {
3653 aco_opcode op
= opcodes
[i
];
3654 if (op
== aco_opcode::num_opcodes
)
3657 Temp data
= write_datas
[i
];
3659 unsigned second
= write_count
;
3660 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3661 for (second
= i
+ 1; second
< write_count
; second
++) {
3662 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3663 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3664 opcodes
[second
] = aco_opcode::num_opcodes
;
3670 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3671 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3673 unsigned inline_offset
= base_offset
+ offsets
[i
];
3674 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3675 Temp address_offset
= address
;
3676 if (inline_offset
> max_offset
) {
3677 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3678 inline_offset
= offsets
[i
];
3680 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3684 Temp second_data
= write_datas
[second
];
3685 inline_offset
/= data
.bytes();
3686 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3688 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3690 static_cast<DS_instruction
*>(instr
)->sync
=
3691 memory_sync_info(storage_shared
);
3695 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3697 unsigned align
= 16;
3699 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3705 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3710 return aco_opcode::buffer_store_byte
;
3713 return aco_opcode::buffer_store_short
;
3715 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3717 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3720 return aco_opcode::buffer_store_dwordx3
;
3722 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3724 unreachable("Unexpected store size");
3725 return aco_opcode::num_opcodes
;
3728 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3729 Temp data
, unsigned writemask
, int swizzle_element_size
,
3730 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3732 unsigned write_count_with_skips
= 0;
3735 /* determine how to split the data */
3736 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3739 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3740 offsets
[write_count_with_skips
] = offset
;
3741 if (skips
[write_count_with_skips
]) {
3742 advance_write_mask(&todo
, offset
, bytes
);
3743 write_count_with_skips
++;
3747 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3748 * larger than swizzle_element_size */
3749 bytes
= MIN2(bytes
, swizzle_element_size
);
3751 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3753 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3754 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3757 /* dword or larger stores have to be dword-aligned */
3758 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3759 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3760 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3762 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3764 advance_write_mask(&todo
, offset
, bytes
);
3765 write_count_with_skips
++;
3768 /* actually split data */
3769 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3772 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3775 write_datas
[*write_count
] = write_datas
[i
];
3776 offsets
[*write_count
] = offsets
[i
];
3781 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3782 unsigned split_cnt
= 0u, Temp dst
= Temp())
3784 Builder
bld(ctx
->program
, ctx
->block
);
3785 unsigned dword_size
= elem_size_bytes
/ 4;
3788 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3790 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3791 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3792 instr
->definitions
[0] = Definition(dst
);
3794 for (unsigned i
= 0; i
< cnt
; ++i
) {
3796 assert(arr
[i
].size() == dword_size
);
3797 allocated_vec
[i
] = arr
[i
];
3798 instr
->operands
[i
] = Operand(arr
[i
]);
3800 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3801 allocated_vec
[i
] = zero
;
3802 instr
->operands
[i
] = Operand(zero
);
3806 bld
.insert(std::move(instr
));
3809 emit_split_vector(ctx
, dst
, split_cnt
);
3811 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3816 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3818 if (const_offset
>= 4096) {
3819 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3820 const_offset
%= 4096u;
3823 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3824 else if (unlikely(voffset
.regClass() == s1
))
3825 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3826 else if (likely(voffset
.regClass() == v1
))
3827 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3829 unreachable("Unsupported register class of voffset");
3832 return const_offset
;
3835 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3836 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
3837 bool slc
= false, bool swizzled
= false)
3840 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3841 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3843 Builder
bld(ctx
->program
, ctx
->block
);
3844 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3845 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3847 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3848 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3849 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3850 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
3851 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
3852 /* dlc*/ false, /* slc */ slc
);
3854 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
3857 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3858 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3859 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
3861 Builder
bld(ctx
->program
, ctx
->block
);
3862 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3864 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3866 unsigned write_count
= 0;
3867 Temp write_datas
[32];
3868 unsigned offsets
[32];
3869 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3870 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3872 for (unsigned i
= 0; i
< write_count
; i
++) {
3873 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3874 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
3878 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3879 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3880 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3882 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3883 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3884 assert(!!stride
!= allow_combining
);
3886 Builder
bld(ctx
->program
, ctx
->block
);
3888 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3889 info
.component_stride
= allow_combining
? 0 : stride
;
3891 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3892 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3893 info
.align_offset
= 0;
3894 info
.soffset
= soffset
;
3895 info
.const_offset
= base_const_offset
;
3896 emit_mubuf_load(ctx
, bld
, &info
);
3899 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3901 Builder
bld(ctx
->program
, ctx
->block
);
3902 Temp offset
= base_offset
.first
;
3903 unsigned const_offset
= base_offset
.second
;
3905 if (!nir_src_is_const(*off_src
)) {
3906 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3909 /* Calculate indirect offset with stride */
3910 if (likely(indirect_offset_arg
.regClass() == v1
))
3911 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3912 else if (indirect_offset_arg
.regClass() == s1
)
3913 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3915 unreachable("Unsupported register class of indirect offset");
3917 /* Add to the supplied base offset */
3918 if (offset
.id() == 0)
3919 offset
= with_stride
;
3920 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3921 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3922 else if (offset
.size() == 1 && with_stride
.size() == 1)
3923 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3925 unreachable("Unsupported register class of indirect offset");
3927 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3928 const_offset
+= const_offset_arg
* stride
;
3931 return std::make_pair(offset
, const_offset
);
3934 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3936 Builder
bld(ctx
->program
, ctx
->block
);
3939 if (off1
.first
.id() && off2
.first
.id()) {
3940 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3941 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3942 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3943 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3945 unreachable("Unsupported register class of indirect offset");
3947 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3950 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3953 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3955 Builder
bld(ctx
->program
, ctx
->block
);
3956 unsigned const_offset
= offs
.second
* multiplier
;
3958 if (!offs
.first
.id())
3959 return std::make_pair(offs
.first
, const_offset
);
3961 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3962 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3963 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
3965 return std::make_pair(offset
, const_offset
);
3968 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3970 Builder
bld(ctx
->program
, ctx
->block
);
3972 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3973 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3974 /* component is in bytes */
3975 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3977 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3978 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3979 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3982 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3984 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3987 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3989 Builder
bld(ctx
->program
, ctx
->block
);
3991 switch (ctx
->shader
->info
.stage
) {
3992 case MESA_SHADER_TESS_CTRL
:
3993 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3994 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3995 case MESA_SHADER_TESS_EVAL
:
3996 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3998 unreachable("Unsupported stage in get_tess_rel_patch_id");
4002 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4004 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4005 Builder
bld(ctx
->program
, ctx
->block
);
4007 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4008 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4010 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4012 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4013 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4015 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4016 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4017 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4019 return offset_mul(ctx
, offs
, 4u);
4022 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4024 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4025 Builder
bld(ctx
->program
, ctx
->block
);
4027 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4028 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4029 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4030 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4032 std::pair
<Temp
, unsigned> offs
= instr
4033 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4034 : std::make_pair(Temp(), 0u);
4036 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4037 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4042 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4043 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4045 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4046 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4048 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4049 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4055 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4057 Builder
bld(ctx
->program
, ctx
->block
);
4059 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4060 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4062 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4064 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4065 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4066 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4068 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4069 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4074 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4076 Builder
bld(ctx
->program
, ctx
->block
);
4078 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4079 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4080 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4081 unsigned attr_stride
= ctx
->tcs_num_patches
;
4083 std::pair
<Temp
, unsigned> offs
= instr
4084 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4085 : std::make_pair(Temp(), 0u);
4087 if (const_base_offset
)
4088 offs
.second
+= const_base_offset
* attr_stride
;
4090 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4091 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4092 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4097 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4099 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4104 unsigned drv_loc
= nir_intrinsic_base(instr
);
4105 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4107 if (!nir_src_is_const(*off_src
)) {
4113 uint64_t slot
= per_vertex
4114 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4115 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4116 return (((uint64_t) 1) << slot
) & mask
;
4119 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4121 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4122 unsigned component
= nir_intrinsic_component(instr
);
4123 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4125 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4126 if (off_instr
->type
!= nir_instr_type_load_const
)
4129 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4130 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4132 if (instr
->src
[0].ssa
->bit_size
== 64)
4133 write_mask
= widen_mask(write_mask
, 2);
4135 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4137 for (unsigned i
= 0; i
< 8; ++i
) {
4138 if (write_mask
& (1 << i
)) {
4139 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4140 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4148 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4150 /* Only TCS per-vertex inputs are supported by this function.
4151 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4153 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4156 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4157 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4158 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4159 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4160 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4161 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4166 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4167 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4168 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4173 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4175 Builder
bld(ctx
->program
, ctx
->block
);
4177 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4178 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4179 bool indirect_write
;
4180 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4181 if (temp_only_input
&& !indirect_write
)
4185 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4186 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4187 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4188 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4190 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4191 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4192 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4193 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4194 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4198 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4199 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4200 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4201 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4202 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4203 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4204 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4205 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4206 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4207 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4208 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4209 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4210 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4212 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4213 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4215 unreachable("Invalid LS or ES stage");
4218 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4219 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4220 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4224 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4229 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4230 return off
== ctx
->tcs_tess_lvl_out_loc
||
4231 off
== ctx
->tcs_tess_lvl_in_loc
;
4235 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4237 uint64_t mask
= per_vertex
4238 ? ctx
->program
->info
->tcs
.tes_inputs_read
4239 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4241 bool indirect_write
= false;
4242 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4243 return indirect_write
|| output_read_by_tes
;
4246 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4248 uint64_t mask
= per_vertex
4249 ? ctx
->shader
->info
.outputs_read
4250 : ctx
->shader
->info
.patch_outputs_read
;
4252 bool indirect_write
= false;
4253 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4254 return indirect_write
|| output_read
;
4257 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4259 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4260 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4262 Builder
bld(ctx
->program
, ctx
->block
);
4264 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4265 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4266 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4268 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4269 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4270 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4272 if (write_to_vmem
) {
4273 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4274 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4275 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4277 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4278 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4279 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4283 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4284 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4285 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4289 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4291 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4292 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4294 Builder
bld(ctx
->program
, ctx
->block
);
4296 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4297 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4298 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4299 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4301 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4304 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4306 if (ctx
->stage
== vertex_vs
||
4307 ctx
->stage
== tess_eval_vs
||
4308 ctx
->stage
== fragment_fs
||
4309 ctx
->stage
== ngg_vertex_gs
||
4310 ctx
->stage
== ngg_tess_eval_gs
||
4311 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4312 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4313 if (!stored_to_temps
) {
4314 isel_err(instr
->src
[1].ssa
->parent_instr
, "Unimplemented output offset instruction");
4317 } else if (ctx
->stage
== vertex_es
||
4318 ctx
->stage
== vertex_ls
||
4319 ctx
->stage
== tess_eval_es
||
4320 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4321 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4322 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4323 visit_store_ls_or_es_output(ctx
, instr
);
4324 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4325 visit_store_tcs_output(ctx
, instr
, false);
4327 unreachable("Shader stage not implemented");
4331 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4333 visit_load_tcs_output(ctx
, instr
, false);
4336 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4338 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4339 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4341 Builder
bld(ctx
->program
, ctx
->block
);
4343 if (dst
.regClass() == v2b
) {
4344 if (ctx
->program
->has_16bank_lds
) {
4345 assert(ctx
->options
->chip_class
<= GFX8
);
4346 Builder::Result interp_p1
=
4347 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4348 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4349 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4350 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4351 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4352 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4354 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4356 if (ctx
->options
->chip_class
== GFX8
)
4357 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4359 Builder::Result interp_p1
=
4360 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4361 coord1
, bld
.m0(prim_mask
), idx
, component
);
4362 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4363 interp_p1
, idx
, component
);
4366 Builder::Result interp_p1
=
4367 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4368 bld
.m0(prim_mask
), idx
, component
);
4370 if (ctx
->program
->has_16bank_lds
)
4371 interp_p1
.instr
->operands
[0].setLateKill(true);
4373 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4374 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4378 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4380 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4381 for (unsigned i
= 0; i
< num_components
; i
++)
4382 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4383 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4384 assert(num_components
== 4);
4385 Builder
bld(ctx
->program
, ctx
->block
);
4386 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4389 for (Operand
& op
: vec
->operands
)
4390 op
= op
.isUndefined() ? Operand(0u) : op
;
4392 vec
->definitions
[0] = Definition(dst
);
4393 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4394 emit_split_vector(ctx
, dst
, num_components
);
4398 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4400 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4401 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4402 unsigned idx
= nir_intrinsic_base(instr
);
4403 unsigned component
= nir_intrinsic_component(instr
);
4404 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4406 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4408 assert(offset
->u32
== 0);
4410 /* the lower 15bit of the prim_mask contain the offset into LDS
4411 * while the upper bits contain the number of prims */
4412 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4413 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4414 Builder
bld(ctx
->program
, ctx
->block
);
4415 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4416 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4417 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4418 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4419 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4422 if (instr
->dest
.ssa
.num_components
== 1) {
4423 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4425 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4426 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4428 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4429 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4430 vec
->operands
[i
] = Operand(tmp
);
4432 vec
->definitions
[0] = Definition(dst
);
4433 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4437 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4438 unsigned offset
, unsigned stride
, unsigned channels
)
4440 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4441 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4443 return (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->chip_class
<= GFX9
) ||
4444 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4447 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4448 unsigned offset
, unsigned stride
, unsigned *channels
)
4450 if (!vtx_info
->chan_byte_size
) {
4451 *channels
= vtx_info
->num_channels
;
4452 return vtx_info
->chan_format
;
4455 unsigned num_channels
= *channels
;
4456 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4457 unsigned new_channels
= num_channels
+ 1;
4458 /* first, assume more loads is worse and try using a larger data format */
4459 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4461 /* don't make the attribute potentially out-of-bounds */
4462 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4466 if (new_channels
== 5) {
4467 /* then try decreasing load size (at the cost of more loads) */
4468 new_channels
= *channels
;
4469 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4473 if (new_channels
< *channels
)
4474 *channels
= new_channels
;
4475 num_channels
= new_channels
;
4478 switch (vtx_info
->chan_format
) {
4479 case V_008F0C_BUF_DATA_FORMAT_8
:
4480 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4481 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4482 case V_008F0C_BUF_DATA_FORMAT_16
:
4483 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4484 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4485 case V_008F0C_BUF_DATA_FORMAT_32
:
4486 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4487 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4489 unreachable("shouldn't reach here");
4490 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4493 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4494 * so we may need to fix it up. */
4495 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4497 Builder
bld(ctx
->program
, ctx
->block
);
4499 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4500 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4502 /* For the integer-like cases, do a natural sign extension.
4504 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4505 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4508 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4509 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4511 /* Convert back to the right type. */
4512 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4513 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4514 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4515 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4516 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4517 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4523 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4525 Builder
bld(ctx
->program
, ctx
->block
);
4526 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4527 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4529 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4530 if (off_instr
->type
!= nir_instr_type_load_const
) {
4531 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4533 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4535 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4537 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4538 unsigned component
= nir_intrinsic_component(instr
);
4539 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4540 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4541 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4542 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4543 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4545 unsigned dfmt
= attrib_format
& 0xf;
4546 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4547 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4549 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4550 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4551 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4552 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4554 num_channels
= MAX2(num_channels
, 3);
4556 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4557 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4560 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4561 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4562 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4564 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4566 Temp divided
= bld
.tmp(v1
);
4567 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4568 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4570 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4573 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4576 index
= bld
.vadd32(bld
.def(v1
),
4577 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4578 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4581 Temp channels
[num_channels
];
4582 unsigned channel_start
= 0;
4583 bool direct_fetch
= false;
4585 /* skip unused channels at the start */
4586 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4587 channel_start
= ffs(mask
) - 1;
4588 for (unsigned i
= 0; i
< channel_start
; i
++)
4589 channels
[i
] = Temp(0, s1
);
4590 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4591 num_channels
= 3 - (ffs(mask
) - 1);
4595 while (channel_start
< num_channels
) {
4596 unsigned fetch_component
= num_channels
- channel_start
;
4597 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4598 bool expanded
= false;
4600 /* use MUBUF when possible to avoid possible alignment issues */
4601 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4602 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4603 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4604 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4605 vtx_info
->chan_byte_size
== 4;
4606 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4608 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4610 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4611 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4612 fetch_component
= 4;
4617 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4619 Temp fetch_index
= index
;
4620 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4621 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4622 fetch_offset
= fetch_offset
% attrib_stride
;
4625 Operand
soffset(0u);
4626 if (fetch_offset
>= 4096) {
4627 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4628 fetch_offset
%= 4096;
4632 switch (fetch_bytes
) {
4634 assert(!use_mubuf
&& bitsize
== 16);
4635 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4638 if (bitsize
== 16) {
4640 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4642 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4646 assert(!use_mubuf
&& bitsize
== 16);
4647 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4650 if (bitsize
== 16) {
4652 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4654 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4658 assert(ctx
->options
->chip_class
>= GFX7
||
4659 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4660 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4663 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4666 unreachable("Unimplemented load_input vector size");
4670 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4671 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4672 num_channels
<= 3)) {
4673 direct_fetch
= true;
4676 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4681 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4682 fetch_offset
, false, false, true).instr
;
4685 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4686 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4689 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4691 if (fetch_component
== 1) {
4692 channels
[channel_start
] = fetch_dst
;
4694 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4695 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4696 bitsize
== 16 ? v2b
: v1
);
4699 channel_start
+= fetch_component
;
4702 if (!direct_fetch
) {
4703 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4704 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4706 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4707 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4708 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4710 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4711 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4712 unsigned num_temp
= 0;
4713 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4714 unsigned idx
= i
+ component
;
4715 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4716 Temp channel
= channels
[swizzle
[idx
]];
4717 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4718 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4719 vec
->operands
[i
] = Operand(channel
);
4723 } else if (is_float
&& idx
== 3) {
4724 vec
->operands
[i
] = Operand(0x3f800000u
);
4725 } else if (!is_float
&& idx
== 3) {
4726 vec
->operands
[i
] = Operand(1u);
4728 vec
->operands
[i
] = Operand(0u);
4731 vec
->definitions
[0] = Definition(dst
);
4732 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4733 emit_split_vector(ctx
, dst
, dst
.size());
4735 if (num_temp
== dst
.size())
4736 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4738 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4739 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4740 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4741 if (off_instr
->type
!= nir_instr_type_load_const
||
4742 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4743 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4746 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4747 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4749 assert(offset
->u32
== 0);
4751 /* the lower 15bit of the prim_mask contain the offset into LDS
4752 * while the upper bits contain the number of prims */
4753 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4754 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4755 Builder
bld(ctx
->program
, ctx
->block
);
4756 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4757 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4758 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4759 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4760 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4763 unsigned idx
= nir_intrinsic_base(instr
);
4764 unsigned component
= nir_intrinsic_component(instr
);
4765 unsigned vertex_id
= 2; /* P0 */
4767 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4768 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4769 switch (src0
->u32
) {
4771 vertex_id
= 2; /* P0 */
4774 vertex_id
= 0; /* P10 */
4777 vertex_id
= 1; /* P20 */
4780 unreachable("invalid vertex index");
4784 if (dst
.size() == 1) {
4785 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4787 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4788 for (unsigned i
= 0; i
< dst
.size(); i
++)
4789 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4790 vec
->definitions
[0] = Definition(dst
);
4791 bld
.insert(std::move(vec
));
4794 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4795 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4796 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4797 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4798 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4800 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4802 unreachable("Shader stage not implemented");
4806 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4808 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4810 Builder
bld(ctx
->program
, ctx
->block
);
4811 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4814 if (!nir_src_is_const(*vertex_src
)) {
4815 /* better code could be created, but this case probably doesn't happen
4816 * much in practice */
4817 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4818 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4821 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4822 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4824 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4826 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4829 if (vertex_offset
.id()) {
4830 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4831 Operand(i
), indirect_vertex
);
4832 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4834 vertex_offset
= elem
;
4838 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4839 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4841 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4842 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4843 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4844 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4845 Operand((vertex
% 2u) * 16u), Operand(16u));
4847 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4850 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4851 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4852 return offset_mul(ctx
, offs
, 4u);
4855 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4857 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4859 Builder
bld(ctx
->program
, ctx
->block
);
4860 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4861 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4863 if (ctx
->stage
== geometry_gs
) {
4864 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4865 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4866 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4867 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4868 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4869 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4870 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4872 unreachable("Unsupported GS stage.");
4876 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4878 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4880 Builder
bld(ctx
->program
, ctx
->block
);
4881 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4883 if (load_input_from_temps(ctx
, instr
, dst
))
4886 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4887 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4888 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4890 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4893 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4895 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4897 Builder
bld(ctx
->program
, ctx
->block
);
4899 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4900 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4901 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4903 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4904 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4906 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4909 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4911 switch (ctx
->shader
->info
.stage
) {
4912 case MESA_SHADER_GEOMETRY
:
4913 visit_load_gs_per_vertex_input(ctx
, instr
);
4915 case MESA_SHADER_TESS_CTRL
:
4916 visit_load_tcs_per_vertex_input(ctx
, instr
);
4918 case MESA_SHADER_TESS_EVAL
:
4919 visit_load_tes_per_vertex_input(ctx
, instr
);
4922 unreachable("Unimplemented shader stage");
4926 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4928 visit_load_tcs_output(ctx
, instr
, true);
4931 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4933 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4934 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4936 visit_store_tcs_output(ctx
, instr
, true);
4939 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4941 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4943 Builder
bld(ctx
->program
, ctx
->block
);
4944 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4946 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4947 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4950 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4951 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4952 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4953 tes_w
= Operand(tmp
);
4956 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4957 emit_split_vector(ctx
, tess_coord
, 3);
4960 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4962 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4963 Builder
bld(ctx
->program
, ctx
->block
);
4964 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4965 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4966 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4969 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4973 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4975 Builder
bld(ctx
->program
, ctx
->block
);
4976 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4977 if (!nir_dest_is_divergent(instr
->dest
))
4978 index
= bld
.as_uniform(index
);
4979 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4980 unsigned binding
= nir_intrinsic_binding(instr
);
4983 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4984 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4985 unsigned offset
= layout
->binding
[binding
].offset
;
4987 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4988 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4989 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4990 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4991 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4994 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4995 stride
= layout
->binding
[binding
].size
;
4998 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4999 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5001 if (nir_const_index
) {
5002 const_index
= const_index
* stride
;
5003 } else if (index
.type() == RegType::vgpr
) {
5004 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5005 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5007 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5011 if (nir_const_index
) {
5012 const_index
= const_index
+ offset
;
5013 } else if (index
.type() == RegType::vgpr
) {
5014 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5016 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5020 if (nir_const_index
&& const_index
== 0) {
5022 } else if (index
.type() == RegType::vgpr
) {
5023 index
= bld
.vadd32(bld
.def(v1
),
5024 nir_const_index
? Operand(const_index
) : Operand(index
),
5027 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5028 nir_const_index
? Operand(const_index
) : Operand(index
),
5032 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5035 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5036 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5037 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5039 Builder
bld(ctx
->program
, ctx
->block
);
5041 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5043 offset
= bld
.as_uniform(offset
);
5045 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5048 info
.align_mul
= align_mul
;
5049 info
.align_offset
= align_offset
;
5051 emit_smem_load(ctx
, bld
, &info
);
5053 emit_mubuf_load(ctx
, bld
, &info
);
5056 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5058 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5059 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5061 Builder
bld(ctx
->program
, ctx
->block
);
5063 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5064 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5065 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5066 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5068 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5069 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5070 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5071 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5072 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5073 if (ctx
->options
->chip_class
>= GFX10
) {
5074 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5075 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5076 S_008F0C_RESOURCE_LEVEL(1);
5078 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5079 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5081 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5082 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5083 Operand(0xFFFFFFFFu
),
5084 Operand(desc_type
));
5085 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5086 rsrc
, upper_dwords
);
5088 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5089 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5091 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5092 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5093 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5096 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5098 Builder
bld(ctx
->program
, ctx
->block
);
5099 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5100 unsigned offset
= nir_intrinsic_base(instr
);
5101 unsigned count
= instr
->dest
.ssa
.num_components
;
5102 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5104 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5105 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5106 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5107 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5108 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5109 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5110 for (unsigned i
= 0; i
< count
; ++i
) {
5111 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5112 vec
->operands
[i
] = Operand
{elems
[i
]};
5114 vec
->definitions
[0] = Definition(dst
);
5115 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5116 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5121 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5122 if (offset
!= 0) // TODO check if index != 0 as well
5123 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5124 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5127 bool aligned
= true;
5129 if (instr
->dest
.ssa
.bit_size
== 8) {
5130 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5131 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5133 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5134 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5135 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5137 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5142 switch (vec
.size()) {
5144 op
= aco_opcode::s_load_dword
;
5147 op
= aco_opcode::s_load_dwordx2
;
5153 op
= aco_opcode::s_load_dwordx4
;
5159 op
= aco_opcode::s_load_dwordx8
;
5162 unreachable("unimplemented or forbidden load_push_constant.");
5165 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5168 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5169 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5174 emit_split_vector(ctx
, vec
, 4);
5175 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5176 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5177 emit_extract_vector(ctx
, vec
, 0, rc
),
5178 emit_extract_vector(ctx
, vec
, 1, rc
),
5179 emit_extract_vector(ctx
, vec
, 2, rc
));
5182 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5185 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5187 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5189 Builder
bld(ctx
->program
, ctx
->block
);
5191 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5192 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5193 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5194 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5195 if (ctx
->options
->chip_class
>= GFX10
) {
5196 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5197 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5198 S_008F0C_RESOURCE_LEVEL(1);
5200 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5201 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5204 unsigned base
= nir_intrinsic_base(instr
);
5205 unsigned range
= nir_intrinsic_range(instr
);
5207 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5208 if (base
&& offset
.type() == RegType::sgpr
)
5209 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5210 else if (base
&& offset
.type() == RegType::vgpr
)
5211 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5213 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5214 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5215 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5216 Operand(desc_type
));
5217 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5218 // TODO: get alignment information for subdword constants
5219 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5222 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5224 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5225 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5227 ctx
->program
->needs_exact
= true;
5229 // TODO: optimize uniform conditions
5230 Builder
bld(ctx
->program
, ctx
->block
);
5231 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5232 assert(src
.regClass() == bld
.lm
);
5233 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5234 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5235 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5239 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5241 Builder
bld(ctx
->program
, ctx
->block
);
5243 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5244 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5246 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5247 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5249 if (ctx
->block
->loop_nest_depth
&&
5250 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5251 /* we handle discards the same way as jump instructions */
5252 append_logical_end(ctx
->block
);
5254 /* in loops, discard behaves like break */
5255 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5256 ctx
->block
->kind
|= block_kind_discard
;
5259 /* uniform discard - loop ends here */
5260 assert(nir_instr_is_last(&instr
->instr
));
5261 ctx
->block
->kind
|= block_kind_uniform
;
5262 ctx
->cf_info
.has_branch
= true;
5263 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5264 add_linear_edge(ctx
->block
->index
, linear_target
);
5268 /* we add a break right behind the discard() instructions */
5269 ctx
->block
->kind
|= block_kind_break
;
5270 unsigned idx
= ctx
->block
->index
;
5272 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5273 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5275 /* remove critical edges from linear CFG */
5276 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5277 Block
* break_block
= ctx
->program
->create_and_insert_block();
5278 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5279 break_block
->kind
|= block_kind_uniform
;
5280 add_linear_edge(idx
, break_block
);
5281 add_linear_edge(break_block
->index
, linear_target
);
5282 bld
.reset(break_block
);
5283 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5285 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5286 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5287 add_linear_edge(idx
, continue_block
);
5288 append_logical_start(continue_block
);
5289 ctx
->block
= continue_block
;
5294 /* it can currently happen that NIR doesn't remove the unreachable code */
5295 if (!nir_instr_is_last(&instr
->instr
)) {
5296 ctx
->program
->needs_exact
= true;
5297 /* save exec somewhere temporarily so that it doesn't get
5298 * overwritten before the discard from outer exec masks */
5299 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5300 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5301 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5305 /* This condition is incorrect for uniformly branched discards in a loop
5306 * predicated by a divergent condition, but the above code catches that case
5307 * and the discard would end up turning into a discard_if.
5317 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5318 /* program just ends here */
5319 ctx
->block
->kind
|= block_kind_uniform
;
5320 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5321 0 /* enabled mask */, 9 /* dest */,
5322 false /* compressed */, true/* done */, true /* valid mask */);
5323 bld
.sopp(aco_opcode::s_endpgm
);
5324 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5326 ctx
->block
->kind
|= block_kind_discard
;
5327 /* branch and linear edge is added by visit_if() */
5331 enum aco_descriptor_type
{
5342 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5343 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5345 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5346 return dim
== ac_image_cube
||
5347 dim
== ac_image_1darray
||
5348 dim
== ac_image_2darray
||
5349 dim
== ac_image_2darraymsaa
;
5352 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5353 enum aco_descriptor_type desc_type
,
5354 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5356 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5357 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5358 if (it != ctx->tex_desc.end())
5361 Temp index
= Temp();
5362 bool index_set
= false;
5363 unsigned constant_index
= 0;
5364 unsigned descriptor_set
;
5365 unsigned base_index
;
5366 Builder
bld(ctx
->program
, ctx
->block
);
5369 assert(tex_instr
&& !image
);
5371 base_index
= tex_instr
->sampler_index
;
5373 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5374 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5378 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5379 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5381 constant_index
+= array_size
* const_value
->u32
;
5383 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5384 if (indirect
.type() == RegType::vgpr
)
5385 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5387 if (array_size
!= 1)
5388 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5394 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5398 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5400 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5401 base_index
= deref_instr
->var
->data
.binding
;
5404 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5405 list
= convert_pointer_to_64_bit(ctx
, list
);
5407 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5408 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5409 unsigned offset
= binding
->offset
;
5410 unsigned stride
= binding
->size
;
5414 assert(base_index
< layout
->binding_count
);
5416 switch (desc_type
) {
5417 case ACO_DESC_IMAGE
:
5419 opcode
= aco_opcode::s_load_dwordx8
;
5421 case ACO_DESC_FMASK
:
5423 opcode
= aco_opcode::s_load_dwordx8
;
5426 case ACO_DESC_SAMPLER
:
5428 opcode
= aco_opcode::s_load_dwordx4
;
5429 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5430 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5432 case ACO_DESC_BUFFER
:
5434 opcode
= aco_opcode::s_load_dwordx4
;
5436 case ACO_DESC_PLANE_0
:
5437 case ACO_DESC_PLANE_1
:
5439 opcode
= aco_opcode::s_load_dwordx8
;
5440 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5442 case ACO_DESC_PLANE_2
:
5444 opcode
= aco_opcode::s_load_dwordx4
;
5448 unreachable("invalid desc_type\n");
5451 offset
+= constant_index
* stride
;
5453 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5454 (!index_set
|| binding
->immutable_samplers_equal
)) {
5455 if (binding
->immutable_samplers_equal
)
5458 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5459 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5460 Operand(samplers
[constant_index
* 4 + 0]),
5461 Operand(samplers
[constant_index
* 4 + 1]),
5462 Operand(samplers
[constant_index
* 4 + 2]),
5463 Operand(samplers
[constant_index
* 4 + 3]));
5468 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5470 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5471 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5474 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5476 if (desc_type
== ACO_DESC_PLANE_2
) {
5478 for (unsigned i
= 0; i
< 8; i
++)
5479 components
[i
] = bld
.tmp(s1
);
5480 bld
.pseudo(aco_opcode::p_split_vector
,
5481 Definition(components
[0]),
5482 Definition(components
[1]),
5483 Definition(components
[2]),
5484 Definition(components
[3]),
5487 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5488 bld
.pseudo(aco_opcode::p_split_vector
,
5489 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5490 Definition(components
[4]),
5491 Definition(components
[5]),
5492 Definition(components
[6]),
5493 Definition(components
[7]),
5496 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5497 components
[0], components
[1], components
[2], components
[3],
5498 components
[4], components
[5], components
[6], components
[7]);
5504 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5507 case GLSL_SAMPLER_DIM_BUF
:
5509 case GLSL_SAMPLER_DIM_1D
:
5510 return array
? 2 : 1;
5511 case GLSL_SAMPLER_DIM_2D
:
5512 return array
? 3 : 2;
5513 case GLSL_SAMPLER_DIM_MS
:
5514 return array
? 4 : 3;
5515 case GLSL_SAMPLER_DIM_3D
:
5516 case GLSL_SAMPLER_DIM_CUBE
:
5518 case GLSL_SAMPLER_DIM_RECT
:
5519 case GLSL_SAMPLER_DIM_SUBPASS
:
5521 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5530 /* Adjust the sample index according to FMASK.
5532 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5533 * which is the identity mapping. Each nibble says which physical sample
5534 * should be fetched to get that sample.
5536 * For example, 0x11111100 means there are only 2 samples stored and
5537 * the second sample covers 3/4 of the pixel. When reading samples 0
5538 * and 1, return physical sample 0 (determined by the first two 0s
5539 * in FMASK), otherwise return physical sample 1.
5541 * The sample index should be adjusted as follows:
5542 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5544 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5546 Builder
bld(ctx
->program
, ctx
->block
);
5547 Temp fmask
= bld
.tmp(v1
);
5548 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5549 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5552 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5553 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5554 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5555 load
->operands
[0] = Operand(fmask_desc_ptr
);
5556 load
->operands
[1] = Operand(s4
); /* no sampler */
5557 load
->operands
[2] = Operand(coord
);
5558 load
->definitions
[0] = Definition(fmask
);
5565 ctx
->block
->instructions
.emplace_back(std::move(load
));
5567 Operand sample_index4
;
5568 if (sample_index
.isConstant()) {
5569 if (sample_index
.constantValue() < 16) {
5570 sample_index4
= Operand(sample_index
.constantValue() << 2);
5572 sample_index4
= Operand(0u);
5574 } else if (sample_index
.regClass() == s1
) {
5575 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5577 assert(sample_index
.regClass() == v1
);
5578 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5582 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5583 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5584 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5585 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5587 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5589 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5590 * resource descriptor is 0 (invalid),
5592 Temp compare
= bld
.tmp(bld
.lm
);
5593 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5594 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5596 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5598 /* Replace the MSAA sample index. */
5599 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5602 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5605 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5606 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5607 bool is_array
= glsl_sampler_type_is_array(type
);
5608 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5609 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5610 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5611 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5612 int count
= image_type_to_components_count(dim
, is_array
);
5613 std::vector
<Temp
> coords(count
);
5614 Builder
bld(ctx
->program
, ctx
->block
);
5618 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5619 /* get sample index */
5620 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5621 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5622 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5623 std::vector
<Temp
> fmask_load_address
;
5624 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5625 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5627 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5628 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5630 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5635 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5636 coords
.resize(coords
.size() + 1);
5637 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5639 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5641 for (int i
= 0; i
< count
; i
++)
5642 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5645 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5646 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5647 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5648 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5651 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5654 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5655 for (unsigned i
= 0; i
< coords
.size(); i
++)
5656 vec
->operands
[i
] = Operand(coords
[i
]);
5657 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5658 vec
->definitions
[0] = Definition(res
);
5659 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5664 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5666 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5667 if (semantics
& semantic_atomicrmw
)
5668 return memory_sync_info(storage
, semantics
);
5670 unsigned access
= nir_intrinsic_access(instr
);
5672 if (access
& ACCESS_VOLATILE
)
5673 semantics
|= semantic_volatile
;
5674 if (access
& ACCESS_CAN_REORDER
)
5675 semantics
|= semantic_can_reorder
| semantic_private
;
5677 return memory_sync_info(storage
, semantics
);
5680 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5682 Builder
bld(ctx
->program
, ctx
->block
);
5683 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5684 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5685 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5686 bool is_array
= glsl_sampler_type_is_array(type
);
5687 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5689 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5690 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5692 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5693 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5694 unsigned num_channels
= util_last_bit(mask
);
5695 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5696 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5699 switch (num_channels
) {
5701 opcode
= aco_opcode::buffer_load_format_x
;
5704 opcode
= aco_opcode::buffer_load_format_xy
;
5707 opcode
= aco_opcode::buffer_load_format_xyz
;
5710 opcode
= aco_opcode::buffer_load_format_xyzw
;
5713 unreachable(">4 channel buffer image load");
5715 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5716 load
->operands
[0] = Operand(rsrc
);
5717 load
->operands
[1] = Operand(vindex
);
5718 load
->operands
[2] = Operand((uint32_t) 0);
5720 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5723 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5724 load
->definitions
[0] = Definition(tmp
);
5726 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5727 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5729 ctx
->block
->instructions
.emplace_back(std::move(load
));
5731 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5735 Temp coords
= get_image_coords(ctx
, instr
, type
);
5736 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5738 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5739 unsigned num_components
= util_bitcount(dmask
);
5741 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5744 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5746 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5747 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5749 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5750 load
->operands
[0] = Operand(resource
);
5751 load
->operands
[1] = Operand(s4
); /* no sampler */
5752 load
->operands
[2] = Operand(coords
);
5753 load
->definitions
[0] = Definition(tmp
);
5754 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5755 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5756 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5757 load
->dmask
= dmask
;
5759 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5761 ctx
->block
->instructions
.emplace_back(std::move(load
));
5763 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5767 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5769 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5770 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5771 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5772 bool is_array
= glsl_sampler_type_is_array(type
);
5773 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5775 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5776 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5777 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5779 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5780 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5781 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5783 switch (data
.size()) {
5785 opcode
= aco_opcode::buffer_store_format_x
;
5788 opcode
= aco_opcode::buffer_store_format_xy
;
5791 opcode
= aco_opcode::buffer_store_format_xyz
;
5794 opcode
= aco_opcode::buffer_store_format_xyzw
;
5797 unreachable(">4 channel buffer image store");
5799 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5800 store
->operands
[0] = Operand(rsrc
);
5801 store
->operands
[1] = Operand(vindex
);
5802 store
->operands
[2] = Operand((uint32_t) 0);
5803 store
->operands
[3] = Operand(data
);
5804 store
->idxen
= true;
5807 store
->disable_wqm
= true;
5809 ctx
->program
->needs_exact
= true;
5810 ctx
->block
->instructions
.emplace_back(std::move(store
));
5814 assert(data
.type() == RegType::vgpr
);
5815 Temp coords
= get_image_coords(ctx
, instr
, type
);
5816 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5818 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5819 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5821 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5822 store
->operands
[0] = Operand(resource
);
5823 store
->operands
[1] = Operand(data
);
5824 store
->operands
[2] = Operand(coords
);
5827 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5828 store
->dmask
= (1 << data
.size()) - 1;
5830 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5831 store
->disable_wqm
= true;
5833 ctx
->program
->needs_exact
= true;
5834 ctx
->block
->instructions
.emplace_back(std::move(store
));
5838 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5840 /* return the previous value if dest is ever used */
5841 bool return_previous
= false;
5842 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5843 return_previous
= true;
5846 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5847 return_previous
= true;
5851 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5852 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5853 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5854 bool is_array
= glsl_sampler_type_is_array(type
);
5855 Builder
bld(ctx
->program
, ctx
->block
);
5857 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5858 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5860 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5861 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5863 aco_opcode buf_op
, image_op
;
5864 switch (instr
->intrinsic
) {
5865 case nir_intrinsic_image_deref_atomic_add
:
5866 buf_op
= aco_opcode::buffer_atomic_add
;
5867 image_op
= aco_opcode::image_atomic_add
;
5869 case nir_intrinsic_image_deref_atomic_umin
:
5870 buf_op
= aco_opcode::buffer_atomic_umin
;
5871 image_op
= aco_opcode::image_atomic_umin
;
5873 case nir_intrinsic_image_deref_atomic_imin
:
5874 buf_op
= aco_opcode::buffer_atomic_smin
;
5875 image_op
= aco_opcode::image_atomic_smin
;
5877 case nir_intrinsic_image_deref_atomic_umax
:
5878 buf_op
= aco_opcode::buffer_atomic_umax
;
5879 image_op
= aco_opcode::image_atomic_umax
;
5881 case nir_intrinsic_image_deref_atomic_imax
:
5882 buf_op
= aco_opcode::buffer_atomic_smax
;
5883 image_op
= aco_opcode::image_atomic_smax
;
5885 case nir_intrinsic_image_deref_atomic_and
:
5886 buf_op
= aco_opcode::buffer_atomic_and
;
5887 image_op
= aco_opcode::image_atomic_and
;
5889 case nir_intrinsic_image_deref_atomic_or
:
5890 buf_op
= aco_opcode::buffer_atomic_or
;
5891 image_op
= aco_opcode::image_atomic_or
;
5893 case nir_intrinsic_image_deref_atomic_xor
:
5894 buf_op
= aco_opcode::buffer_atomic_xor
;
5895 image_op
= aco_opcode::image_atomic_xor
;
5897 case nir_intrinsic_image_deref_atomic_exchange
:
5898 buf_op
= aco_opcode::buffer_atomic_swap
;
5899 image_op
= aco_opcode::image_atomic_swap
;
5901 case nir_intrinsic_image_deref_atomic_comp_swap
:
5902 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5903 image_op
= aco_opcode::image_atomic_cmpswap
;
5906 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5909 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5910 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
5912 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5913 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5914 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5915 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5916 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5917 mubuf
->operands
[0] = Operand(resource
);
5918 mubuf
->operands
[1] = Operand(vindex
);
5919 mubuf
->operands
[2] = Operand((uint32_t)0);
5920 mubuf
->operands
[3] = Operand(data
);
5921 if (return_previous
)
5922 mubuf
->definitions
[0] = Definition(dst
);
5924 mubuf
->idxen
= true;
5925 mubuf
->glc
= return_previous
;
5926 mubuf
->dlc
= false; /* Not needed for atomics */
5927 mubuf
->disable_wqm
= true;
5929 ctx
->program
->needs_exact
= true;
5930 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5934 Temp coords
= get_image_coords(ctx
, instr
, type
);
5935 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5936 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5937 mimg
->operands
[0] = Operand(resource
);
5938 mimg
->operands
[1] = Operand(data
);
5939 mimg
->operands
[2] = Operand(coords
);
5940 if (return_previous
)
5941 mimg
->definitions
[0] = Definition(dst
);
5942 mimg
->glc
= return_previous
;
5943 mimg
->dlc
= false; /* Not needed for atomics */
5944 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5945 mimg
->dmask
= (1 << data
.size()) - 1;
5947 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5948 mimg
->disable_wqm
= true;
5950 ctx
->program
->needs_exact
= true;
5951 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5955 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5957 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5958 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5959 Builder
bld(ctx
->program
, ctx
->block
);
5961 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5963 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5964 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5966 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5967 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5969 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5970 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5972 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5973 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5974 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5975 if (dst
.type() == RegType::vgpr
)
5976 bld
.copy(Definition(dst
), shr_dst
);
5978 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5980 emit_extract_vector(ctx
, desc
, 2, dst
);
5984 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5986 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5987 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5988 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5989 bool is_array
= glsl_sampler_type_is_array(type
);
5990 Builder
bld(ctx
->program
, ctx
->block
);
5992 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5993 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5994 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5998 assert(nir_src_as_uint(instr
->src
[1]) == 0);
5999 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6002 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6004 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6006 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6007 mimg
->operands
[0] = Operand(resource
);
6008 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6009 mimg
->operands
[2] = Operand(lod
);
6010 uint8_t& dmask
= mimg
->dmask
;
6011 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6012 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6013 mimg
->da
= glsl_sampler_type_is_array(type
);
6014 Definition
& def
= mimg
->definitions
[0];
6015 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6017 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6018 glsl_sampler_type_is_array(type
)) {
6020 assert(instr
->dest
.ssa
.num_components
== 3);
6021 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6022 def
= Definition(tmp
);
6023 emit_split_vector(ctx
, tmp
, 3);
6025 /* divide 3rd value by 6 by multiplying with magic number */
6026 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6027 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6029 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6030 emit_extract_vector(ctx
, tmp
, 0, v1
),
6031 emit_extract_vector(ctx
, tmp
, 1, v1
),
6034 } else if (ctx
->options
->chip_class
== GFX9
&&
6035 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6036 glsl_sampler_type_is_array(type
)) {
6037 assert(instr
->dest
.ssa
.num_components
== 2);
6038 def
= Definition(dst
);
6041 def
= Definition(dst
);
6044 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6047 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6049 Builder
bld(ctx
->program
, ctx
->block
);
6050 unsigned num_components
= instr
->num_components
;
6052 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6053 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6054 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6056 unsigned access
= nir_intrinsic_access(instr
);
6057 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6058 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6060 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6061 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6062 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6064 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6065 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6067 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6068 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6069 get_memory_sync_info(instr
, storage_buffer
, 0));
6072 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6074 Builder
bld(ctx
->program
, ctx
->block
);
6075 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6076 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6077 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6078 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6080 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6081 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6083 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6084 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6085 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6086 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6087 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6089 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6091 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6092 ctx
->options
->chip_class
>= GFX8
&&
6093 ctx
->options
->chip_class
< GFX10_3
&&
6094 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6097 offset
= bld
.as_uniform(offset
);
6098 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6100 unsigned write_count
= 0;
6101 Temp write_datas
[32];
6102 unsigned offsets
[32];
6103 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6104 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6106 for (unsigned i
= 0; i
< write_count
; i
++) {
6107 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6108 if (smem
&& ctx
->stage
== fragment_fs
)
6109 op
= aco_opcode::p_fs_buffer_store_smem
;
6112 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6113 store
->operands
[0] = Operand(rsrc
);
6115 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6116 offset
, Operand(offsets
[i
]));
6117 store
->operands
[1] = Operand(off
);
6119 store
->operands
[1] = Operand(offset
);
6121 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6122 store
->operands
[1].setFixed(m0
);
6123 store
->operands
[2] = Operand(write_datas
[i
]);
6126 store
->disable_wqm
= true;
6128 ctx
->block
->instructions
.emplace_back(std::move(store
));
6129 ctx
->program
->wb_smem_l1_on_end
= true;
6130 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6131 ctx
->block
->kind
|= block_kind_needs_lowering
;
6132 ctx
->program
->needs_exact
= true;
6135 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6136 store
->operands
[0] = Operand(rsrc
);
6137 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6138 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6139 store
->operands
[3] = Operand(write_datas
[i
]);
6140 store
->offset
= offsets
[i
];
6141 store
->offen
= (offset
.type() == RegType::vgpr
);
6144 store
->disable_wqm
= true;
6146 ctx
->program
->needs_exact
= true;
6147 ctx
->block
->instructions
.emplace_back(std::move(store
));
6152 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6154 /* return the previous value if dest is ever used */
6155 bool return_previous
= false;
6156 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6157 return_previous
= true;
6160 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6161 return_previous
= true;
6165 Builder
bld(ctx
->program
, ctx
->block
);
6166 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6168 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6169 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6170 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6172 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6173 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6174 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6176 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6178 aco_opcode op32
, op64
;
6179 switch (instr
->intrinsic
) {
6180 case nir_intrinsic_ssbo_atomic_add
:
6181 op32
= aco_opcode::buffer_atomic_add
;
6182 op64
= aco_opcode::buffer_atomic_add_x2
;
6184 case nir_intrinsic_ssbo_atomic_imin
:
6185 op32
= aco_opcode::buffer_atomic_smin
;
6186 op64
= aco_opcode::buffer_atomic_smin_x2
;
6188 case nir_intrinsic_ssbo_atomic_umin
:
6189 op32
= aco_opcode::buffer_atomic_umin
;
6190 op64
= aco_opcode::buffer_atomic_umin_x2
;
6192 case nir_intrinsic_ssbo_atomic_imax
:
6193 op32
= aco_opcode::buffer_atomic_smax
;
6194 op64
= aco_opcode::buffer_atomic_smax_x2
;
6196 case nir_intrinsic_ssbo_atomic_umax
:
6197 op32
= aco_opcode::buffer_atomic_umax
;
6198 op64
= aco_opcode::buffer_atomic_umax_x2
;
6200 case nir_intrinsic_ssbo_atomic_and
:
6201 op32
= aco_opcode::buffer_atomic_and
;
6202 op64
= aco_opcode::buffer_atomic_and_x2
;
6204 case nir_intrinsic_ssbo_atomic_or
:
6205 op32
= aco_opcode::buffer_atomic_or
;
6206 op64
= aco_opcode::buffer_atomic_or_x2
;
6208 case nir_intrinsic_ssbo_atomic_xor
:
6209 op32
= aco_opcode::buffer_atomic_xor
;
6210 op64
= aco_opcode::buffer_atomic_xor_x2
;
6212 case nir_intrinsic_ssbo_atomic_exchange
:
6213 op32
= aco_opcode::buffer_atomic_swap
;
6214 op64
= aco_opcode::buffer_atomic_swap_x2
;
6216 case nir_intrinsic_ssbo_atomic_comp_swap
:
6217 op32
= aco_opcode::buffer_atomic_cmpswap
;
6218 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6221 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6223 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6224 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6225 mubuf
->operands
[0] = Operand(rsrc
);
6226 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6227 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6228 mubuf
->operands
[3] = Operand(data
);
6229 if (return_previous
)
6230 mubuf
->definitions
[0] = Definition(dst
);
6232 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6233 mubuf
->glc
= return_previous
;
6234 mubuf
->dlc
= false; /* Not needed for atomics */
6235 mubuf
->disable_wqm
= true;
6236 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6237 ctx
->program
->needs_exact
= true;
6238 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6241 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6243 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6244 Builder
bld(ctx
->program
, ctx
->block
);
6245 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6246 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6249 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6251 Builder
bld(ctx
->program
, ctx
->block
);
6252 unsigned num_components
= instr
->num_components
;
6253 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6255 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6256 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6257 num_components
, component_size
};
6258 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6259 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6260 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6261 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6262 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6263 * it's safe to use SMEM */
6264 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6265 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6266 emit_global_load(ctx
, bld
, &info
);
6268 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6269 emit_smem_load(ctx
, bld
, &info
);
6273 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6275 Builder
bld(ctx
->program
, ctx
->block
);
6276 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6277 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6279 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6280 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6281 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6282 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6284 if (ctx
->options
->chip_class
>= GFX7
)
6285 addr
= as_vgpr(ctx
, addr
);
6287 unsigned write_count
= 0;
6288 Temp write_datas
[32];
6289 unsigned offsets
[32];
6290 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6291 16, &write_count
, write_datas
, offsets
);
6293 for (unsigned i
= 0; i
< write_count
; i
++) {
6294 if (ctx
->options
->chip_class
>= GFX7
) {
6295 unsigned offset
= offsets
[i
];
6296 Temp store_addr
= addr
;
6297 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6298 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6299 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6300 Temp carry
= bld
.tmp(bld
.lm
);
6301 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6303 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6304 Operand(offset
), addr0
);
6305 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6307 carry
).def(1).setHint(vcc
);
6309 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6314 bool global
= ctx
->options
->chip_class
>= GFX9
;
6316 switch (write_datas
[i
].bytes()) {
6318 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6321 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6324 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6327 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6330 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6333 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6336 unreachable("store_global not implemented for this size.");
6339 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6340 flat
->operands
[0] = Operand(store_addr
);
6341 flat
->operands
[1] = Operand(s1
);
6342 flat
->operands
[2] = Operand(write_datas
[i
]);
6345 flat
->offset
= offset
;
6346 flat
->disable_wqm
= true;
6348 ctx
->program
->needs_exact
= true;
6349 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6351 assert(ctx
->options
->chip_class
== GFX6
);
6353 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6355 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6357 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6358 mubuf
->operands
[0] = Operand(rsrc
);
6359 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6360 mubuf
->operands
[2] = Operand(0u);
6361 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6364 mubuf
->offset
= offsets
[i
];
6365 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6366 mubuf
->disable_wqm
= true;
6368 ctx
->program
->needs_exact
= true;
6369 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6374 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6376 /* return the previous value if dest is ever used */
6377 bool return_previous
= false;
6378 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6379 return_previous
= true;
6382 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6383 return_previous
= true;
6387 Builder
bld(ctx
->program
, ctx
->block
);
6388 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6389 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6391 if (ctx
->options
->chip_class
>= GFX7
)
6392 addr
= as_vgpr(ctx
, addr
);
6394 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6395 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6396 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6398 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6400 aco_opcode op32
, op64
;
6402 if (ctx
->options
->chip_class
>= GFX7
) {
6403 bool global
= ctx
->options
->chip_class
>= GFX9
;
6404 switch (instr
->intrinsic
) {
6405 case nir_intrinsic_global_atomic_add
:
6406 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6407 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6409 case nir_intrinsic_global_atomic_imin
:
6410 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6411 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6413 case nir_intrinsic_global_atomic_umin
:
6414 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6415 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6417 case nir_intrinsic_global_atomic_imax
:
6418 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6419 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6421 case nir_intrinsic_global_atomic_umax
:
6422 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6423 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6425 case nir_intrinsic_global_atomic_and
:
6426 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6427 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6429 case nir_intrinsic_global_atomic_or
:
6430 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6431 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6433 case nir_intrinsic_global_atomic_xor
:
6434 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6435 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6437 case nir_intrinsic_global_atomic_exchange
:
6438 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6439 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6441 case nir_intrinsic_global_atomic_comp_swap
:
6442 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6443 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6446 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6449 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6450 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6451 flat
->operands
[0] = Operand(addr
);
6452 flat
->operands
[1] = Operand(s1
);
6453 flat
->operands
[2] = Operand(data
);
6454 if (return_previous
)
6455 flat
->definitions
[0] = Definition(dst
);
6456 flat
->glc
= return_previous
;
6457 flat
->dlc
= false; /* Not needed for atomics */
6459 flat
->disable_wqm
= true;
6460 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6461 ctx
->program
->needs_exact
= true;
6462 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6464 assert(ctx
->options
->chip_class
== GFX6
);
6466 switch (instr
->intrinsic
) {
6467 case nir_intrinsic_global_atomic_add
:
6468 op32
= aco_opcode::buffer_atomic_add
;
6469 op64
= aco_opcode::buffer_atomic_add_x2
;
6471 case nir_intrinsic_global_atomic_imin
:
6472 op32
= aco_opcode::buffer_atomic_smin
;
6473 op64
= aco_opcode::buffer_atomic_smin_x2
;
6475 case nir_intrinsic_global_atomic_umin
:
6476 op32
= aco_opcode::buffer_atomic_umin
;
6477 op64
= aco_opcode::buffer_atomic_umin_x2
;
6479 case nir_intrinsic_global_atomic_imax
:
6480 op32
= aco_opcode::buffer_atomic_smax
;
6481 op64
= aco_opcode::buffer_atomic_smax_x2
;
6483 case nir_intrinsic_global_atomic_umax
:
6484 op32
= aco_opcode::buffer_atomic_umax
;
6485 op64
= aco_opcode::buffer_atomic_umax_x2
;
6487 case nir_intrinsic_global_atomic_and
:
6488 op32
= aco_opcode::buffer_atomic_and
;
6489 op64
= aco_opcode::buffer_atomic_and_x2
;
6491 case nir_intrinsic_global_atomic_or
:
6492 op32
= aco_opcode::buffer_atomic_or
;
6493 op64
= aco_opcode::buffer_atomic_or_x2
;
6495 case nir_intrinsic_global_atomic_xor
:
6496 op32
= aco_opcode::buffer_atomic_xor
;
6497 op64
= aco_opcode::buffer_atomic_xor_x2
;
6499 case nir_intrinsic_global_atomic_exchange
:
6500 op32
= aco_opcode::buffer_atomic_swap
;
6501 op64
= aco_opcode::buffer_atomic_swap_x2
;
6503 case nir_intrinsic_global_atomic_comp_swap
:
6504 op32
= aco_opcode::buffer_atomic_cmpswap
;
6505 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6508 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6511 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6513 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6515 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6516 mubuf
->operands
[0] = Operand(rsrc
);
6517 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6518 mubuf
->operands
[2] = Operand(0u);
6519 mubuf
->operands
[3] = Operand(data
);
6520 if (return_previous
)
6521 mubuf
->definitions
[0] = Definition(dst
);
6522 mubuf
->glc
= return_previous
;
6525 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6526 mubuf
->disable_wqm
= true;
6527 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6528 ctx
->program
->needs_exact
= true;
6529 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6533 sync_scope
translate_nir_scope(nir_scope scope
)
6536 case NIR_SCOPE_NONE
:
6537 case NIR_SCOPE_INVOCATION
:
6538 return scope_invocation
;
6539 case NIR_SCOPE_SUBGROUP
:
6540 return scope_subgroup
;
6541 case NIR_SCOPE_WORKGROUP
:
6542 return scope_workgroup
;
6543 case NIR_SCOPE_QUEUE_FAMILY
:
6544 return scope_queuefamily
;
6545 case NIR_SCOPE_DEVICE
:
6546 return scope_device
;
6548 unreachable("invalid scope");
6551 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6552 Builder
bld(ctx
->program
, ctx
->block
);
6554 unsigned semantics
= 0;
6555 unsigned storage
= 0;
6556 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6557 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6559 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6560 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6561 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6562 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6563 storage
|= storage_shared
;
6564 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6565 storage
|= storage_shared
;
6567 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6568 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6569 semantics
|= semantic_acquire
| semantic_release
;
6570 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6571 semantics
|= semantic_acquire
| semantic_release
;
6573 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6575 bld
.barrier(aco_opcode::p_barrier
,
6576 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6580 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6582 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6583 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6584 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6585 Builder
bld(ctx
->program
, ctx
->block
);
6587 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6588 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6589 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6592 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6594 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6595 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6596 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6597 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6599 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6600 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6603 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6605 unsigned offset
= nir_intrinsic_base(instr
);
6606 Builder
bld(ctx
->program
, ctx
->block
);
6607 Operand m
= load_lds_size_m0(bld
);
6608 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6609 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6611 unsigned num_operands
= 3;
6612 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6613 switch(instr
->intrinsic
) {
6614 case nir_intrinsic_shared_atomic_add
:
6615 op32
= aco_opcode::ds_add_u32
;
6616 op64
= aco_opcode::ds_add_u64
;
6617 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6618 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6620 case nir_intrinsic_shared_atomic_imin
:
6621 op32
= aco_opcode::ds_min_i32
;
6622 op64
= aco_opcode::ds_min_i64
;
6623 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6624 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6626 case nir_intrinsic_shared_atomic_umin
:
6627 op32
= aco_opcode::ds_min_u32
;
6628 op64
= aco_opcode::ds_min_u64
;
6629 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6630 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6632 case nir_intrinsic_shared_atomic_imax
:
6633 op32
= aco_opcode::ds_max_i32
;
6634 op64
= aco_opcode::ds_max_i64
;
6635 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6636 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6638 case nir_intrinsic_shared_atomic_umax
:
6639 op32
= aco_opcode::ds_max_u32
;
6640 op64
= aco_opcode::ds_max_u64
;
6641 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6642 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6644 case nir_intrinsic_shared_atomic_and
:
6645 op32
= aco_opcode::ds_and_b32
;
6646 op64
= aco_opcode::ds_and_b64
;
6647 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6648 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6650 case nir_intrinsic_shared_atomic_or
:
6651 op32
= aco_opcode::ds_or_b32
;
6652 op64
= aco_opcode::ds_or_b64
;
6653 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6654 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6656 case nir_intrinsic_shared_atomic_xor
:
6657 op32
= aco_opcode::ds_xor_b32
;
6658 op64
= aco_opcode::ds_xor_b64
;
6659 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6660 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6662 case nir_intrinsic_shared_atomic_exchange
:
6663 op32
= aco_opcode::ds_write_b32
;
6664 op64
= aco_opcode::ds_write_b64
;
6665 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6666 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6668 case nir_intrinsic_shared_atomic_comp_swap
:
6669 op32
= aco_opcode::ds_cmpst_b32
;
6670 op64
= aco_opcode::ds_cmpst_b64
;
6671 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6672 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6675 case nir_intrinsic_shared_atomic_fadd
:
6676 op32
= aco_opcode::ds_add_f32
;
6677 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6678 op64
= aco_opcode::num_opcodes
;
6679 op64_rtn
= aco_opcode::num_opcodes
;
6682 unreachable("Unhandled shared atomic intrinsic");
6685 /* return the previous value if dest is ever used */
6686 bool return_previous
= false;
6687 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6688 return_previous
= true;
6691 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6692 return_previous
= true;
6697 if (data
.size() == 1) {
6698 assert(instr
->dest
.ssa
.bit_size
== 32);
6699 op
= return_previous
? op32_rtn
: op32
;
6701 assert(instr
->dest
.ssa
.bit_size
== 64);
6702 op
= return_previous
? op64_rtn
: op64
;
6705 if (offset
> 65535) {
6706 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6710 aco_ptr
<DS_instruction
> ds
;
6711 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6712 ds
->operands
[0] = Operand(address
);
6713 ds
->operands
[1] = Operand(data
);
6714 if (num_operands
== 4)
6715 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6716 ds
->operands
[num_operands
- 1] = m
;
6717 ds
->offset0
= offset
;
6718 if (return_previous
)
6719 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6720 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6721 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6724 Temp
get_scratch_resource(isel_context
*ctx
)
6726 Builder
bld(ctx
->program
, ctx
->block
);
6727 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6728 if (ctx
->stage
!= compute_cs
)
6729 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6731 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6732 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6734 if (ctx
->program
->chip_class
>= GFX10
) {
6735 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6736 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6737 S_008F0C_RESOURCE_LEVEL(1);
6738 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6739 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6740 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6743 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6744 if (ctx
->program
->chip_class
<= GFX8
)
6745 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6747 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6750 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6751 Builder
bld(ctx
->program
, ctx
->block
);
6752 Temp rsrc
= get_scratch_resource(ctx
);
6753 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6754 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6756 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6757 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6758 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6759 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6760 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6761 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6762 info
.soffset
= ctx
->program
->scratch_offset
;
6763 emit_scratch_load(ctx
, bld
, &info
);
6766 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6767 Builder
bld(ctx
->program
, ctx
->block
);
6768 Temp rsrc
= get_scratch_resource(ctx
);
6769 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6770 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6772 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6773 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6775 unsigned write_count
= 0;
6776 Temp write_datas
[32];
6777 unsigned offsets
[32];
6778 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6779 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6780 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6782 for (unsigned i
= 0; i
< write_count
; i
++) {
6783 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6784 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6785 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6789 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6790 uint8_t log2_ps_iter_samples
;
6791 if (ctx
->program
->info
->ps
.force_persample
) {
6792 log2_ps_iter_samples
=
6793 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6795 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6798 /* The bit pattern matches that used by fixed function fragment
6800 static const unsigned ps_iter_masks
[] = {
6801 0xffff, /* not used */
6807 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6809 Builder
bld(ctx
->program
, ctx
->block
);
6811 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6812 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6813 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6814 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6815 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6816 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6819 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6820 Builder
bld(ctx
->program
, ctx
->block
);
6822 unsigned stream
= nir_intrinsic_stream_id(instr
);
6823 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6824 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6825 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6828 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6830 unsigned num_components
=
6831 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6832 assert(num_components
);
6834 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6835 unsigned stream_offset
= 0;
6836 for (unsigned i
= 0; i
< stream
; i
++) {
6837 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6838 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6841 /* Limit on the stride field for <= GFX7. */
6842 assert(stride
< (1 << 14));
6844 Temp gsvs_dwords
[4];
6845 for (unsigned i
= 0; i
< 4; i
++)
6846 gsvs_dwords
[i
] = bld
.tmp(s1
);
6847 bld
.pseudo(aco_opcode::p_split_vector
,
6848 Definition(gsvs_dwords
[0]),
6849 Definition(gsvs_dwords
[1]),
6850 Definition(gsvs_dwords
[2]),
6851 Definition(gsvs_dwords
[3]),
6854 if (stream_offset
) {
6855 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6857 Temp carry
= bld
.tmp(s1
);
6858 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6859 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6862 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6863 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6865 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6866 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6868 unsigned offset
= 0;
6869 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6870 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6873 for (unsigned j
= 0; j
< 4; j
++) {
6874 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6877 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6878 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6879 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6880 if (const_offset
>= 4096u) {
6881 if (vaddr_offset
.isUndefined())
6882 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6884 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6885 const_offset
%= 4096u;
6888 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6889 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6890 mtbuf
->operands
[1] = vaddr_offset
;
6891 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6892 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6893 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6894 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6895 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6896 mtbuf
->offset
= const_offset
;
6899 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
6900 bld
.insert(std::move(mtbuf
));
6903 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6906 /* outputs for the next vertex are undefined and keeping them around can
6907 * create invalid IR with control flow */
6908 ctx
->outputs
.mask
[i
] = 0;
6911 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6914 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6916 Builder
bld(ctx
->program
, ctx
->block
);
6918 if (cluster_size
== 1) {
6920 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6921 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6922 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6923 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6924 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6925 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6926 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6927 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6928 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6929 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6930 //subgroupAnd(val) -> (exec & ~val) == 0
6931 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6932 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6933 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6934 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6935 //subgroupOr(val) -> (val & exec) != 0
6936 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6937 return bool_to_vector_condition(ctx
, tmp
);
6938 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6939 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6940 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6941 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6942 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6943 return bool_to_vector_condition(ctx
, tmp
);
6945 //subgroupClustered{And,Or,Xor}(val, n) ->
6946 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6947 //cluster_offset = ~(n - 1) & lane_id
6948 //cluster_mask = ((1 << n) - 1)
6949 //subgroupClusteredAnd():
6950 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6951 //subgroupClusteredOr():
6952 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6953 //subgroupClusteredXor():
6954 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6955 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6956 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6959 if (op
== nir_op_iand
)
6960 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6962 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6964 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6966 if (ctx
->program
->chip_class
<= GFX7
)
6967 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6968 else if (ctx
->program
->wave_size
== 64)
6969 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6971 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6972 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6973 if (cluster_mask
!= 0xffffffff)
6974 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6976 Definition cmp_def
= Definition();
6977 if (op
== nir_op_iand
) {
6978 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6979 } else if (op
== nir_op_ior
) {
6980 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6981 } else if (op
== nir_op_ixor
) {
6982 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6983 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6984 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6986 cmp_def
.setHint(vcc
);
6987 return cmp_def
.getTemp();
6991 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6993 Builder
bld(ctx
->program
, ctx
->block
);
6995 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6996 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6997 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6999 if (op
== nir_op_iand
)
7000 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7002 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7004 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7005 Temp lo
= lohi
.def(0).getTemp();
7006 Temp hi
= lohi
.def(1).getTemp();
7007 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7009 Definition cmp_def
= Definition();
7010 if (op
== nir_op_iand
)
7011 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7012 else if (op
== nir_op_ior
)
7013 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7014 else if (op
== nir_op_ixor
)
7015 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7016 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7017 cmp_def
.setHint(vcc
);
7018 return cmp_def
.getTemp();
7021 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7023 Builder
bld(ctx
->program
, ctx
->block
);
7025 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7026 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7027 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7028 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7029 if (op
== nir_op_iand
)
7030 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7031 else if (op
== nir_op_ior
)
7032 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7033 else if (op
== nir_op_ixor
)
7034 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7040 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7042 Builder
bld(ctx
->program
, ctx
->block
);
7043 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7044 if (src
.regClass().type() == RegType::vgpr
) {
7045 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7046 } else if (src
.regClass() == s1
) {
7047 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7048 } else if (src
.regClass() == s2
) {
7049 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7051 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7055 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7057 Builder
bld(ctx
->program
, ctx
->block
);
7058 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7059 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7060 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7062 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7063 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7064 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7065 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7068 if (ctx
->program
->chip_class
>= GFX8
) {
7069 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7070 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7071 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7072 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7073 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7074 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7076 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7077 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7078 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7079 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7080 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7081 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7082 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7083 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7084 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7085 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7088 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7089 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7090 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7091 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7092 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7093 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7094 Temp wqm1
= bld
.tmp(v1
);
7095 emit_wqm(ctx
, tmp1
, wqm1
, true);
7096 Temp wqm2
= bld
.tmp(v1
);
7097 emit_wqm(ctx
, tmp2
, wqm2
, true);
7098 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7102 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7104 Builder
bld(ctx
->program
, ctx
->block
);
7105 switch(instr
->intrinsic
) {
7106 case nir_intrinsic_load_barycentric_sample
:
7107 case nir_intrinsic_load_barycentric_pixel
:
7108 case nir_intrinsic_load_barycentric_centroid
: {
7109 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7110 Temp bary
= Temp(0, s2
);
7112 case INTERP_MODE_SMOOTH
:
7113 case INTERP_MODE_NONE
:
7114 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7115 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7116 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7117 bary
= ctx
->persp_centroid
;
7118 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7119 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7121 case INTERP_MODE_NOPERSPECTIVE
:
7122 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7123 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7124 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7125 bary
= ctx
->linear_centroid
;
7126 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7127 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7132 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7133 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7134 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7135 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7136 Operand(p1
), Operand(p2
));
7137 emit_split_vector(ctx
, dst
, 2);
7140 case nir_intrinsic_load_barycentric_model
: {
7141 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7143 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7144 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7145 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7146 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7147 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7148 Operand(p1
), Operand(p2
), Operand(p3
));
7149 emit_split_vector(ctx
, dst
, 3);
7152 case nir_intrinsic_load_barycentric_at_sample
: {
7153 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7154 switch (ctx
->options
->key
.fs
.num_samples
) {
7155 case 2: sample_pos_offset
+= 1 << 3; break;
7156 case 4: sample_pos_offset
+= 3 << 3; break;
7157 case 8: sample_pos_offset
+= 7 << 3; break;
7161 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7162 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7163 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7164 //TODO: bounds checking?
7165 if (addr
.type() == RegType::sgpr
) {
7168 sample_pos_offset
+= const_addr
->u32
<< 3;
7169 offset
= Operand(sample_pos_offset
);
7170 } else if (ctx
->options
->chip_class
>= GFX9
) {
7171 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7173 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7174 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7177 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7178 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7180 } else if (ctx
->options
->chip_class
>= GFX9
) {
7181 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7182 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7183 } else if (ctx
->options
->chip_class
>= GFX7
) {
7184 /* addr += private_segment_buffer + sample_pos_offset */
7185 Temp tmp0
= bld
.tmp(s1
);
7186 Temp tmp1
= bld
.tmp(s1
);
7187 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7188 Definition scc_tmp
= bld
.def(s1
, scc
);
7189 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7190 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7191 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7192 Temp pck0
= bld
.tmp(v1
);
7193 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7194 tmp1
= as_vgpr(ctx
, tmp1
);
7195 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7196 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7198 /* sample_pos = flat_load_dwordx2 addr */
7199 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7201 assert(ctx
->options
->chip_class
== GFX6
);
7203 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7204 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7205 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7207 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7208 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7210 sample_pos
= bld
.tmp(v2
);
7212 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7213 load
->definitions
[0] = Definition(sample_pos
);
7214 load
->operands
[0] = Operand(rsrc
);
7215 load
->operands
[1] = Operand(addr
);
7216 load
->operands
[2] = Operand(0u);
7217 load
->offset
= sample_pos_offset
;
7219 load
->addr64
= true;
7222 load
->disable_wqm
= false;
7223 ctx
->block
->instructions
.emplace_back(std::move(load
));
7226 /* sample_pos -= 0.5 */
7227 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7228 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7229 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7230 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7231 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7233 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7236 case nir_intrinsic_load_barycentric_at_offset
: {
7237 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7238 RegClass rc
= RegClass(offset
.type(), 1);
7239 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7240 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7241 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7244 case nir_intrinsic_load_front_face
: {
7245 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7246 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7249 case nir_intrinsic_load_view_index
: {
7250 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7251 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7252 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7258 case nir_intrinsic_load_layer_id
: {
7259 unsigned idx
= nir_intrinsic_base(instr
);
7260 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7261 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7264 case nir_intrinsic_load_frag_coord
: {
7265 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7268 case nir_intrinsic_load_sample_pos
: {
7269 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7270 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7271 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7272 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7273 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7276 case nir_intrinsic_load_tess_coord
:
7277 visit_load_tess_coord(ctx
, instr
);
7279 case nir_intrinsic_load_interpolated_input
:
7280 visit_load_interpolated_input(ctx
, instr
);
7282 case nir_intrinsic_store_output
:
7283 visit_store_output(ctx
, instr
);
7285 case nir_intrinsic_load_input
:
7286 case nir_intrinsic_load_input_vertex
:
7287 visit_load_input(ctx
, instr
);
7289 case nir_intrinsic_load_output
:
7290 visit_load_output(ctx
, instr
);
7292 case nir_intrinsic_load_per_vertex_input
:
7293 visit_load_per_vertex_input(ctx
, instr
);
7295 case nir_intrinsic_load_per_vertex_output
:
7296 visit_load_per_vertex_output(ctx
, instr
);
7298 case nir_intrinsic_store_per_vertex_output
:
7299 visit_store_per_vertex_output(ctx
, instr
);
7301 case nir_intrinsic_load_ubo
:
7302 visit_load_ubo(ctx
, instr
);
7304 case nir_intrinsic_load_push_constant
:
7305 visit_load_push_constant(ctx
, instr
);
7307 case nir_intrinsic_load_constant
:
7308 visit_load_constant(ctx
, instr
);
7310 case nir_intrinsic_vulkan_resource_index
:
7311 visit_load_resource(ctx
, instr
);
7313 case nir_intrinsic_discard
:
7314 visit_discard(ctx
, instr
);
7316 case nir_intrinsic_discard_if
:
7317 visit_discard_if(ctx
, instr
);
7319 case nir_intrinsic_load_shared
:
7320 visit_load_shared(ctx
, instr
);
7322 case nir_intrinsic_store_shared
:
7323 visit_store_shared(ctx
, instr
);
7325 case nir_intrinsic_shared_atomic_add
:
7326 case nir_intrinsic_shared_atomic_imin
:
7327 case nir_intrinsic_shared_atomic_umin
:
7328 case nir_intrinsic_shared_atomic_imax
:
7329 case nir_intrinsic_shared_atomic_umax
:
7330 case nir_intrinsic_shared_atomic_and
:
7331 case nir_intrinsic_shared_atomic_or
:
7332 case nir_intrinsic_shared_atomic_xor
:
7333 case nir_intrinsic_shared_atomic_exchange
:
7334 case nir_intrinsic_shared_atomic_comp_swap
:
7335 case nir_intrinsic_shared_atomic_fadd
:
7336 visit_shared_atomic(ctx
, instr
);
7338 case nir_intrinsic_image_deref_load
:
7339 visit_image_load(ctx
, instr
);
7341 case nir_intrinsic_image_deref_store
:
7342 visit_image_store(ctx
, instr
);
7344 case nir_intrinsic_image_deref_atomic_add
:
7345 case nir_intrinsic_image_deref_atomic_umin
:
7346 case nir_intrinsic_image_deref_atomic_imin
:
7347 case nir_intrinsic_image_deref_atomic_umax
:
7348 case nir_intrinsic_image_deref_atomic_imax
:
7349 case nir_intrinsic_image_deref_atomic_and
:
7350 case nir_intrinsic_image_deref_atomic_or
:
7351 case nir_intrinsic_image_deref_atomic_xor
:
7352 case nir_intrinsic_image_deref_atomic_exchange
:
7353 case nir_intrinsic_image_deref_atomic_comp_swap
:
7354 visit_image_atomic(ctx
, instr
);
7356 case nir_intrinsic_image_deref_size
:
7357 visit_image_size(ctx
, instr
);
7359 case nir_intrinsic_load_ssbo
:
7360 visit_load_ssbo(ctx
, instr
);
7362 case nir_intrinsic_store_ssbo
:
7363 visit_store_ssbo(ctx
, instr
);
7365 case nir_intrinsic_load_global
:
7366 visit_load_global(ctx
, instr
);
7368 case nir_intrinsic_store_global
:
7369 visit_store_global(ctx
, instr
);
7371 case nir_intrinsic_global_atomic_add
:
7372 case nir_intrinsic_global_atomic_imin
:
7373 case nir_intrinsic_global_atomic_umin
:
7374 case nir_intrinsic_global_atomic_imax
:
7375 case nir_intrinsic_global_atomic_umax
:
7376 case nir_intrinsic_global_atomic_and
:
7377 case nir_intrinsic_global_atomic_or
:
7378 case nir_intrinsic_global_atomic_xor
:
7379 case nir_intrinsic_global_atomic_exchange
:
7380 case nir_intrinsic_global_atomic_comp_swap
:
7381 visit_global_atomic(ctx
, instr
);
7383 case nir_intrinsic_ssbo_atomic_add
:
7384 case nir_intrinsic_ssbo_atomic_imin
:
7385 case nir_intrinsic_ssbo_atomic_umin
:
7386 case nir_intrinsic_ssbo_atomic_imax
:
7387 case nir_intrinsic_ssbo_atomic_umax
:
7388 case nir_intrinsic_ssbo_atomic_and
:
7389 case nir_intrinsic_ssbo_atomic_or
:
7390 case nir_intrinsic_ssbo_atomic_xor
:
7391 case nir_intrinsic_ssbo_atomic_exchange
:
7392 case nir_intrinsic_ssbo_atomic_comp_swap
:
7393 visit_atomic_ssbo(ctx
, instr
);
7395 case nir_intrinsic_load_scratch
:
7396 visit_load_scratch(ctx
, instr
);
7398 case nir_intrinsic_store_scratch
:
7399 visit_store_scratch(ctx
, instr
);
7401 case nir_intrinsic_get_buffer_size
:
7402 visit_get_buffer_size(ctx
, instr
);
7404 case nir_intrinsic_scoped_barrier
:
7405 emit_scoped_barrier(ctx
, instr
);
7407 case nir_intrinsic_load_num_work_groups
: {
7408 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7409 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7410 emit_split_vector(ctx
, dst
, 3);
7413 case nir_intrinsic_load_local_invocation_id
: {
7414 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7415 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7416 emit_split_vector(ctx
, dst
, 3);
7419 case nir_intrinsic_load_work_group_id
: {
7420 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7421 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7422 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7423 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7424 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7425 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7426 emit_split_vector(ctx
, dst
, 3);
7429 case nir_intrinsic_load_local_invocation_index
: {
7430 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7432 /* The tg_size bits [6:11] contain the subgroup id,
7433 * we need this multiplied by the wave size, and then OR the thread id to it.
7435 if (ctx
->program
->wave_size
== 64) {
7436 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7437 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7438 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7439 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7441 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7442 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7443 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7444 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7448 case nir_intrinsic_load_subgroup_id
: {
7449 if (ctx
->stage
== compute_cs
) {
7450 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7451 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7453 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7457 case nir_intrinsic_load_subgroup_invocation
: {
7458 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7461 case nir_intrinsic_load_num_subgroups
: {
7462 if (ctx
->stage
== compute_cs
)
7463 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7464 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7466 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7469 case nir_intrinsic_ballot
: {
7470 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7471 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7472 Definition tmp
= bld
.def(dst
.regClass());
7473 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7474 if (instr
->src
[0].ssa
->bit_size
== 1) {
7475 assert(src
.regClass() == bld
.lm
);
7476 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7477 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7478 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7479 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7480 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7482 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7484 if (dst
.size() != bld
.lm
.size()) {
7485 /* Wave32 with ballot size set to 64 */
7486 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7488 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7491 case nir_intrinsic_shuffle
:
7492 case nir_intrinsic_read_invocation
: {
7493 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7494 if (!nir_src_is_divergent(instr
->src
[0])) {
7495 emit_uniform_subgroup(ctx
, instr
, src
);
7497 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7498 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7499 tid
= bld
.as_uniform(tid
);
7500 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7501 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7502 Temp tmp
= bld
.tmp(v1
);
7503 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7504 if (dst
.type() == RegType::vgpr
)
7505 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7507 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7508 } else if (src
.regClass() == v1
) {
7509 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7510 } else if (src
.regClass() == v2
) {
7511 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7512 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7513 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7514 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7515 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7516 emit_split_vector(ctx
, dst
, 2);
7517 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7518 assert(src
.regClass() == bld
.lm
);
7519 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7520 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7521 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7522 assert(src
.regClass() == bld
.lm
);
7524 if (ctx
->program
->chip_class
<= GFX7
)
7525 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7526 else if (ctx
->program
->wave_size
== 64)
7527 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7529 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7530 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7531 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7532 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7534 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7539 case nir_intrinsic_load_sample_id
: {
7540 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7541 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7544 case nir_intrinsic_load_sample_mask_in
: {
7545 visit_load_sample_mask_in(ctx
, instr
);
7548 case nir_intrinsic_read_first_invocation
: {
7549 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7550 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7551 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7553 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7555 } else if (src
.regClass() == v2
) {
7556 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7557 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7558 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7559 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7560 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7561 emit_split_vector(ctx
, dst
, 2);
7562 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7563 assert(src
.regClass() == bld
.lm
);
7564 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7565 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7566 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7567 } else if (src
.regClass() == s1
) {
7568 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7569 } else if (src
.regClass() == s2
) {
7570 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7572 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7576 case nir_intrinsic_vote_all
: {
7577 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7578 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7579 assert(src
.regClass() == bld
.lm
);
7580 assert(dst
.regClass() == bld
.lm
);
7582 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7583 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7584 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7587 case nir_intrinsic_vote_any
: {
7588 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7589 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7590 assert(src
.regClass() == bld
.lm
);
7591 assert(dst
.regClass() == bld
.lm
);
7593 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7594 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7597 case nir_intrinsic_reduce
:
7598 case nir_intrinsic_inclusive_scan
:
7599 case nir_intrinsic_exclusive_scan
: {
7600 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7601 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7602 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7603 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7604 nir_intrinsic_cluster_size(instr
) : 0;
7605 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7607 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7608 emit_uniform_subgroup(ctx
, instr
, src
);
7609 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7610 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7612 else if (op
== nir_op_iadd
)
7614 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7616 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7618 switch (instr
->intrinsic
) {
7619 case nir_intrinsic_reduce
:
7620 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7622 case nir_intrinsic_exclusive_scan
:
7623 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7625 case nir_intrinsic_inclusive_scan
:
7626 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7631 } else if (cluster_size
== 1) {
7632 bld
.copy(Definition(dst
), src
);
7634 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7636 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7640 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7641 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7656 unreachable("unknown reduction op");
7662 switch (instr
->intrinsic
) {
7663 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7664 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7665 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7667 unreachable("unknown reduce intrinsic");
7670 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7671 reduce
->operands
[0] = Operand(src
);
7672 // filled in by aco_reduce_assign.cpp, used internally as part of the
7674 assert(dst
.size() == 1 || dst
.size() == 2);
7675 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7676 reduce
->operands
[2] = Operand(v1
.as_linear());
7678 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7679 reduce
->definitions
[0] = Definition(tmp_dst
);
7680 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7681 reduce
->definitions
[2] = Definition();
7682 reduce
->definitions
[3] = Definition(scc
, s1
);
7683 reduce
->definitions
[4] = Definition();
7684 reduce
->reduce_op
= reduce_op
;
7685 reduce
->cluster_size
= cluster_size
;
7686 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7688 emit_wqm(ctx
, tmp_dst
, dst
);
7692 case nir_intrinsic_quad_broadcast
: {
7693 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7694 if (!nir_dest_is_divergent(instr
->dest
)) {
7695 emit_uniform_subgroup(ctx
, instr
, src
);
7697 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7698 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7699 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7701 if (instr
->dest
.ssa
.bit_size
== 1) {
7702 assert(src
.regClass() == bld
.lm
);
7703 assert(dst
.regClass() == bld
.lm
);
7704 uint32_t half_mask
= 0x11111111u
<< lane
;
7705 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7706 Temp tmp
= bld
.tmp(bld
.lm
);
7707 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7708 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7709 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7710 emit_wqm(ctx
, tmp
, dst
);
7711 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7712 Temp tmp
= bld
.tmp(v1
);
7713 if (ctx
->program
->chip_class
>= GFX8
)
7714 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7716 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7717 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7718 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7719 Temp tmp
= bld
.tmp(v1
);
7720 if (ctx
->program
->chip_class
>= GFX8
)
7721 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7723 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7724 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7725 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7726 if (ctx
->program
->chip_class
>= GFX8
)
7727 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7729 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7730 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7731 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7732 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7733 if (ctx
->program
->chip_class
>= GFX8
) {
7734 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7735 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7737 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7738 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7740 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7741 emit_split_vector(ctx
, dst
, 2);
7743 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7748 case nir_intrinsic_quad_swap_horizontal
:
7749 case nir_intrinsic_quad_swap_vertical
:
7750 case nir_intrinsic_quad_swap_diagonal
:
7751 case nir_intrinsic_quad_swizzle_amd
: {
7752 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7753 if (!nir_dest_is_divergent(instr
->dest
)) {
7754 emit_uniform_subgroup(ctx
, instr
, src
);
7757 uint16_t dpp_ctrl
= 0;
7758 switch (instr
->intrinsic
) {
7759 case nir_intrinsic_quad_swap_horizontal
:
7760 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7762 case nir_intrinsic_quad_swap_vertical
:
7763 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7765 case nir_intrinsic_quad_swap_diagonal
:
7766 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7768 case nir_intrinsic_quad_swizzle_amd
:
7769 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7774 if (ctx
->program
->chip_class
< GFX8
)
7775 dpp_ctrl
|= (1 << 15);
7777 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7778 if (instr
->dest
.ssa
.bit_size
== 1) {
7779 assert(src
.regClass() == bld
.lm
);
7780 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7781 if (ctx
->program
->chip_class
>= GFX8
)
7782 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7784 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7785 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7786 emit_wqm(ctx
, tmp
, dst
);
7787 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7788 Temp tmp
= bld
.tmp(v1
);
7789 if (ctx
->program
->chip_class
>= GFX8
)
7790 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7792 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7793 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7794 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7795 Temp tmp
= bld
.tmp(v1
);
7796 if (ctx
->program
->chip_class
>= GFX8
)
7797 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7799 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7800 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7801 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7803 if (ctx
->program
->chip_class
>= GFX8
)
7804 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7806 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7807 emit_wqm(ctx
, tmp
, dst
);
7808 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7809 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7810 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7811 if (ctx
->program
->chip_class
>= GFX8
) {
7812 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7813 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7815 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7816 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7818 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7819 emit_split_vector(ctx
, dst
, 2);
7821 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7825 case nir_intrinsic_masked_swizzle_amd
: {
7826 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7827 if (!nir_dest_is_divergent(instr
->dest
)) {
7828 emit_uniform_subgroup(ctx
, instr
, src
);
7831 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7832 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7833 if (instr
->dest
.ssa
.bit_size
== 1) {
7834 assert(src
.regClass() == bld
.lm
);
7835 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7836 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7837 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7838 emit_wqm(ctx
, tmp
, dst
);
7839 } else if (dst
.regClass() == v1b
) {
7840 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7841 emit_extract_vector(ctx
, tmp
, 0, dst
);
7842 } else if (dst
.regClass() == v2b
) {
7843 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7844 emit_extract_vector(ctx
, tmp
, 0, dst
);
7845 } else if (dst
.regClass() == v1
) {
7846 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7847 } else if (dst
.regClass() == v2
) {
7848 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7849 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7850 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7851 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7852 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7853 emit_split_vector(ctx
, dst
, 2);
7855 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7859 case nir_intrinsic_write_invocation_amd
: {
7860 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7861 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7862 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7863 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7864 if (dst
.regClass() == v1
) {
7865 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7866 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7867 } else if (dst
.regClass() == v2
) {
7868 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7869 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7870 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7871 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7872 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7873 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7874 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7875 emit_split_vector(ctx
, dst
, 2);
7877 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7881 case nir_intrinsic_mbcnt_amd
: {
7882 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7883 RegClass rc
= RegClass(src
.type(), 1);
7884 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7885 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7886 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7887 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7888 emit_wqm(ctx
, wqm_tmp
, dst
);
7891 case nir_intrinsic_load_helper_invocation
: {
7892 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7893 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7894 ctx
->block
->kind
|= block_kind_needs_lowering
;
7895 ctx
->program
->needs_exact
= true;
7898 case nir_intrinsic_is_helper_invocation
: {
7899 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7900 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7901 ctx
->block
->kind
|= block_kind_needs_lowering
;
7902 ctx
->program
->needs_exact
= true;
7905 case nir_intrinsic_demote
:
7906 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7908 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7909 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7910 ctx
->block
->kind
|= block_kind_uses_demote
;
7911 ctx
->program
->needs_exact
= true;
7913 case nir_intrinsic_demote_if
: {
7914 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7915 assert(src
.regClass() == bld
.lm
);
7916 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7917 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7919 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7920 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7921 ctx
->block
->kind
|= block_kind_uses_demote
;
7922 ctx
->program
->needs_exact
= true;
7925 case nir_intrinsic_first_invocation
: {
7926 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7927 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7930 case nir_intrinsic_shader_clock
: {
7931 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7932 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
7933 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
7934 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
7935 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
7938 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7939 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7940 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
7942 emit_split_vector(ctx
, dst
, 2);
7945 case nir_intrinsic_load_vertex_id_zero_base
: {
7946 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7947 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7950 case nir_intrinsic_load_first_vertex
: {
7951 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7952 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7955 case nir_intrinsic_load_base_instance
: {
7956 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7957 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7960 case nir_intrinsic_load_instance_id
: {
7961 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7962 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7965 case nir_intrinsic_load_draw_id
: {
7966 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7967 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7970 case nir_intrinsic_load_invocation_id
: {
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7973 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7974 if (ctx
->options
->chip_class
>= GFX10
)
7975 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7977 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7978 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7979 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7980 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7982 unreachable("Unsupported stage for load_invocation_id");
7987 case nir_intrinsic_load_primitive_id
: {
7988 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7990 switch (ctx
->shader
->info
.stage
) {
7991 case MESA_SHADER_GEOMETRY
:
7992 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7994 case MESA_SHADER_TESS_CTRL
:
7995 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7997 case MESA_SHADER_TESS_EVAL
:
7998 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8001 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8006 case nir_intrinsic_load_patch_vertices_in
: {
8007 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8008 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8010 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8011 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8014 case nir_intrinsic_emit_vertex_with_counter
: {
8015 visit_emit_vertex_with_counter(ctx
, instr
);
8018 case nir_intrinsic_end_primitive_with_counter
: {
8019 unsigned stream
= nir_intrinsic_stream_id(instr
);
8020 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8023 case nir_intrinsic_set_vertex_count
: {
8024 /* unused, the HW keeps track of this for us */
8028 isel_err(&instr
->instr
, "Unimplemented intrinsic instr");
8036 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8037 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8038 enum glsl_base_type
*stype
)
8040 nir_deref_instr
*texture_deref_instr
= NULL
;
8041 nir_deref_instr
*sampler_deref_instr
= NULL
;
8044 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8045 switch (instr
->src
[i
].src_type
) {
8046 case nir_tex_src_texture_deref
:
8047 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8049 case nir_tex_src_sampler_deref
:
8050 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8052 case nir_tex_src_plane
:
8053 plane
= nir_src_as_int(instr
->src
[i
].src
);
8060 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8062 if (!sampler_deref_instr
)
8063 sampler_deref_instr
= texture_deref_instr
;
8066 assert(instr
->op
!= nir_texop_txf_ms
&&
8067 instr
->op
!= nir_texop_samples_identical
);
8068 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8069 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8070 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8071 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8072 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8073 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8075 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8078 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8080 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8081 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8082 Builder
bld(ctx
->program
, ctx
->block
);
8084 /* to avoid unnecessary moves, we split and recombine sampler and image */
8085 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8086 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8087 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8088 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8089 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8090 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8091 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8092 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8094 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8095 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8096 img
[0], img
[1], img
[2], img
[3],
8097 img
[4], img
[5], img
[6], img
[7]);
8098 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8099 samp
[0], samp
[1], samp
[2], samp
[3]);
8102 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8103 instr
->op
== nir_texop_samples_identical
))
8104 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8107 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8108 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8110 Builder
bld(ctx
->program
, ctx
->block
);
8112 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8113 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8114 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8116 Operand
neg_one(0xbf800000u
);
8117 Operand
one(0x3f800000u
);
8118 Operand
two(0x40000000u
);
8119 Operand
four(0x40800000u
);
8121 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8122 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8123 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8125 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8126 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8127 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8128 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8131 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8132 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8133 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8135 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8138 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8139 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8140 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8143 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8144 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8146 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8147 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8150 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8152 Builder
bld(ctx
->program
, ctx
->block
);
8153 Temp ma
, tc
, sc
, id
;
8154 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8155 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8158 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8160 // see comment in ac_prepare_cube_coords()
8161 if (ctx
->options
->chip_class
<= GFX8
)
8162 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8165 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8167 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8168 vop3a
->operands
[0] = Operand(ma
);
8169 vop3a
->abs
[0] = true;
8170 Temp invma
= bld
.tmp(v1
);
8171 vop3a
->definitions
[0] = Definition(invma
);
8172 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8174 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8176 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8178 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8180 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8182 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8185 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8186 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8188 for (unsigned i
= 0; i
< 2; i
++) {
8189 // see comment in ac_prepare_cube_coords()
8191 Temp deriv_sc
, deriv_tc
;
8192 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8193 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8195 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8197 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8198 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8199 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8200 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8201 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8202 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8203 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8206 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8207 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8211 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8218 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8220 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8222 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8223 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8226 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8227 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8228 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8232 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8234 Builder
bld(ctx
->program
, ctx
->block
);
8235 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8236 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8237 has_clamped_lod
= false;
8238 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8239 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8240 clamped_lod
= Temp();
8241 std::vector
<Temp
> coords
;
8242 std::vector
<Temp
> derivs
;
8243 nir_const_value
*sample_index_cv
= NULL
;
8244 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8245 enum glsl_base_type stype
;
8246 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8248 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8249 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8250 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8251 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8253 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8254 switch (instr
->src
[i
].src_type
) {
8255 case nir_tex_src_coord
: {
8256 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8257 for (unsigned i
= 0; i
< coord
.size(); i
++)
8258 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8261 case nir_tex_src_bias
:
8262 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8265 case nir_tex_src_lod
: {
8266 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8268 if (val
&& val
->f32
<= 0.0) {
8271 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8276 case nir_tex_src_min_lod
:
8277 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8278 has_clamped_lod
= true;
8280 case nir_tex_src_comparator
:
8281 if (instr
->is_shadow
) {
8282 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8286 case nir_tex_src_offset
:
8287 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8288 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8291 case nir_tex_src_ddx
:
8292 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8295 case nir_tex_src_ddy
:
8296 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8299 case nir_tex_src_ms_index
:
8300 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8301 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8302 has_sample_index
= true;
8304 case nir_tex_src_texture_offset
:
8305 case nir_tex_src_sampler_offset
:
8311 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8312 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8314 if (instr
->op
== nir_texop_texture_samples
) {
8315 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8317 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8318 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8319 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8321 Operand default_sample
= Operand(1u);
8322 if (ctx
->options
->robust_buffer_access
) {
8323 /* Extract the second dword of the descriptor, if it's
8324 * all zero, then it's a null descriptor.
8326 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8327 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8328 default_sample
= Operand(is_non_null_descriptor
);
8331 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8332 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8333 samples
, default_sample
, bld
.scc(is_msaa
));
8337 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8338 aco_ptr
<Instruction
> tmp_instr
;
8339 Temp acc
, pack
= Temp();
8341 uint32_t pack_const
= 0;
8342 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8343 if (!const_offset
[i
])
8345 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8348 if (offset
.type() == RegType::sgpr
) {
8349 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8350 if (const_offset
[i
])
8353 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8354 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8357 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8360 if (pack
== Temp()) {
8363 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8367 if (pack_const
&& pack
!= Temp())
8368 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8370 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8371 if (const_offset
[i
])
8374 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8375 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8378 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8381 if (pack
== Temp()) {
8384 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8388 if (pack_const
&& pack
!= Temp())
8389 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8391 if (pack_const
&& pack
== Temp())
8392 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8393 else if (pack
== Temp())
8399 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8400 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8402 /* pack derivatives */
8403 if (has_ddx
|| has_ddy
) {
8404 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8405 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8406 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8407 derivs
= {ddx
, zero
, ddy
, zero
};
8409 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8410 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8411 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8412 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8417 if (instr
->coord_components
> 1 &&
8418 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8420 instr
->op
!= nir_texop_txf
)
8421 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8423 if (instr
->coord_components
> 2 &&
8424 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8425 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8426 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8427 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8429 instr
->op
!= nir_texop_txf
&&
8430 instr
->op
!= nir_texop_txf_ms
&&
8431 instr
->op
!= nir_texop_fragment_fetch
&&
8432 instr
->op
!= nir_texop_fragment_mask_fetch
)
8433 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8435 if (ctx
->options
->chip_class
== GFX9
&&
8436 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8437 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8438 assert(coords
.size() > 0 && coords
.size() < 3);
8440 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8441 Operand((uint32_t) 0) :
8442 Operand((uint32_t) 0x3f000000)));
8445 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8447 if (instr
->op
== nir_texop_samples_identical
)
8448 resource
= fmask_ptr
;
8450 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8451 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8452 instr
->op
!= nir_texop_txs
&&
8453 instr
->op
!= nir_texop_fragment_fetch
&&
8454 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8455 assert(has_sample_index
);
8456 Operand
op(sample_index
);
8457 if (sample_index_cv
)
8458 op
= Operand(sample_index_cv
->u32
);
8459 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8462 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8463 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8464 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8465 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8470 /* Build tex instruction */
8471 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8472 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8473 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8475 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8478 /* gather4 selects the component by dmask and always returns vec4 */
8479 if (instr
->op
== nir_texop_tg4
) {
8480 assert(instr
->dest
.ssa
.num_components
== 4);
8481 if (instr
->is_shadow
)
8484 dmask
= 1 << instr
->component
;
8485 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8486 tmp_dst
= bld
.tmp(v4
);
8487 } else if (instr
->op
== nir_texop_samples_identical
) {
8488 tmp_dst
= bld
.tmp(v1
);
8489 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8490 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8493 aco_ptr
<MIMG_instruction
> tex
;
8494 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8496 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8498 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8499 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8502 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8503 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8505 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8506 tex
->operands
[0] = Operand(resource
);
8507 tex
->operands
[1] = Operand(s4
); /* no sampler */
8508 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8509 if (ctx
->options
->chip_class
== GFX9
&&
8510 instr
->op
== nir_texop_txs
&&
8511 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8513 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8514 } else if (instr
->op
== nir_texop_query_levels
) {
8515 tex
->dmask
= 1 << 3;
8520 tex
->definitions
[0] = Definition(tmp_dst
);
8522 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8525 /* divide 3rd value by 6 by multiplying with magic number */
8526 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8527 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8528 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8529 assert(instr
->dest
.ssa
.num_components
== 3);
8530 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8531 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8532 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8533 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8538 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8542 Temp tg4_compare_cube_wa64
= Temp();
8544 if (tg4_integer_workarounds
) {
8545 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8546 tex
->operands
[0] = Operand(resource
);
8547 tex
->operands
[1] = Operand(s4
); /* no sampler */
8548 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8552 Temp size
= bld
.tmp(v2
);
8553 tex
->definitions
[0] = Definition(size
);
8554 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8555 emit_split_vector(ctx
, size
, size
.size());
8558 for (unsigned i
= 0; i
< 2; i
++) {
8559 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8560 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8561 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8562 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8565 Temp new_coords
[2] = {
8566 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8567 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8570 if (tg4_integer_cube_workaround
) {
8571 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8572 Temp desc
[resource
.size()];
8573 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8574 Format::PSEUDO
, 1, resource
.size())};
8575 split
->operands
[0] = Operand(resource
);
8576 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8577 desc
[i
] = bld
.tmp(s1
);
8578 split
->definitions
[i
] = Definition(desc
[i
]);
8580 ctx
->block
->instructions
.emplace_back(std::move(split
));
8582 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8583 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8584 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8587 if (stype
== GLSL_TYPE_UINT
) {
8588 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8589 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8590 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8591 bld
.scc(compare_cube_wa
));
8593 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8594 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8595 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8596 bld
.scc(compare_cube_wa
));
8598 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8599 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8601 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8603 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8604 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8605 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8607 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8608 Format::PSEUDO
, resource
.size(), 1)};
8609 for (unsigned i
= 0; i
< resource
.size(); i
++)
8610 vec
->operands
[i
] = Operand(desc
[i
]);
8611 resource
= bld
.tmp(resource
.regClass());
8612 vec
->definitions
[0] = Definition(resource
);
8613 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8615 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8616 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8617 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8618 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8620 coords
[0] = new_coords
[0];
8621 coords
[1] = new_coords
[1];
8624 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8625 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8627 assert(coords
.size() == 1);
8628 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8632 op
= aco_opcode::buffer_load_format_x
; break;
8634 op
= aco_opcode::buffer_load_format_xy
; break;
8636 op
= aco_opcode::buffer_load_format_xyz
; break;
8638 op
= aco_opcode::buffer_load_format_xyzw
; break;
8640 unreachable("Tex instruction loads more than 4 components.");
8643 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8644 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8647 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8649 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8650 mubuf
->operands
[0] = Operand(resource
);
8651 mubuf
->operands
[1] = Operand(coords
[0]);
8652 mubuf
->operands
[2] = Operand((uint32_t) 0);
8653 mubuf
->definitions
[0] = Definition(tmp_dst
);
8654 mubuf
->idxen
= true;
8655 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8657 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8661 /* gather MIMG address components */
8662 std::vector
<Temp
> args
;
8664 args
.emplace_back(offset
);
8666 args
.emplace_back(bias
);
8668 args
.emplace_back(compare
);
8670 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8672 args
.insert(args
.end(), coords
.begin(), coords
.end());
8673 if (has_sample_index
)
8674 args
.emplace_back(sample_index
);
8676 args
.emplace_back(lod
);
8677 if (has_clamped_lod
)
8678 args
.emplace_back(clamped_lod
);
8680 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8681 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8682 vec
->definitions
[0] = Definition(arg
);
8683 for (unsigned i
= 0; i
< args
.size(); i
++)
8684 vec
->operands
[i
] = Operand(args
[i
]);
8685 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8688 if (instr
->op
== nir_texop_txf
||
8689 instr
->op
== nir_texop_txf_ms
||
8690 instr
->op
== nir_texop_samples_identical
||
8691 instr
->op
== nir_texop_fragment_fetch
||
8692 instr
->op
== nir_texop_fragment_mask_fetch
) {
8693 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8694 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8695 tex
->operands
[0] = Operand(resource
);
8696 tex
->operands
[1] = Operand(s4
); /* no sampler */
8697 tex
->operands
[2] = Operand(arg
);
8702 tex
->definitions
[0] = Definition(tmp_dst
);
8703 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8705 if (instr
->op
== nir_texop_samples_identical
) {
8706 assert(dmask
== 1 && dst
.regClass() == v1
);
8707 assert(dst
.id() != tmp_dst
.id());
8709 Temp tmp
= bld
.tmp(bld
.lm
);
8710 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8711 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8714 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8719 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8720 aco_opcode opcode
= aco_opcode::image_sample
;
8721 if (has_offset
) { /* image_sample_*_o */
8722 if (has_clamped_lod
) {
8724 opcode
= aco_opcode::image_sample_c_cl_o
;
8726 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8728 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8730 opcode
= aco_opcode::image_sample_cl_o
;
8732 opcode
= aco_opcode::image_sample_d_cl_o
;
8734 opcode
= aco_opcode::image_sample_b_cl_o
;
8736 } else if (has_compare
) {
8737 opcode
= aco_opcode::image_sample_c_o
;
8739 opcode
= aco_opcode::image_sample_c_d_o
;
8741 opcode
= aco_opcode::image_sample_c_b_o
;
8743 opcode
= aco_opcode::image_sample_c_lz_o
;
8745 opcode
= aco_opcode::image_sample_c_l_o
;
8747 opcode
= aco_opcode::image_sample_o
;
8749 opcode
= aco_opcode::image_sample_d_o
;
8751 opcode
= aco_opcode::image_sample_b_o
;
8753 opcode
= aco_opcode::image_sample_lz_o
;
8755 opcode
= aco_opcode::image_sample_l_o
;
8757 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8759 opcode
= aco_opcode::image_sample_c_cl
;
8761 opcode
= aco_opcode::image_sample_c_d_cl
;
8763 opcode
= aco_opcode::image_sample_c_b_cl
;
8765 opcode
= aco_opcode::image_sample_cl
;
8767 opcode
= aco_opcode::image_sample_d_cl
;
8769 opcode
= aco_opcode::image_sample_b_cl
;
8771 } else { /* no offset */
8773 opcode
= aco_opcode::image_sample_c
;
8775 opcode
= aco_opcode::image_sample_c_d
;
8777 opcode
= aco_opcode::image_sample_c_b
;
8779 opcode
= aco_opcode::image_sample_c_lz
;
8781 opcode
= aco_opcode::image_sample_c_l
;
8783 opcode
= aco_opcode::image_sample
;
8785 opcode
= aco_opcode::image_sample_d
;
8787 opcode
= aco_opcode::image_sample_b
;
8789 opcode
= aco_opcode::image_sample_lz
;
8791 opcode
= aco_opcode::image_sample_l
;
8795 if (instr
->op
== nir_texop_tg4
) {
8796 if (has_offset
) { /* image_gather4_*_o */
8798 opcode
= aco_opcode::image_gather4_c_lz_o
;
8800 opcode
= aco_opcode::image_gather4_c_l_o
;
8802 opcode
= aco_opcode::image_gather4_c_b_o
;
8804 opcode
= aco_opcode::image_gather4_lz_o
;
8806 opcode
= aco_opcode::image_gather4_l_o
;
8808 opcode
= aco_opcode::image_gather4_b_o
;
8812 opcode
= aco_opcode::image_gather4_c_lz
;
8814 opcode
= aco_opcode::image_gather4_c_l
;
8816 opcode
= aco_opcode::image_gather4_c_b
;
8818 opcode
= aco_opcode::image_gather4_lz
;
8820 opcode
= aco_opcode::image_gather4_l
;
8822 opcode
= aco_opcode::image_gather4_b
;
8825 } else if (instr
->op
== nir_texop_lod
) {
8826 opcode
= aco_opcode::image_get_lod
;
8829 /* we don't need the bias, sample index, compare value or offset to be
8830 * computed in WQM but if the p_create_vector copies the coordinates, then it
8831 * needs to be in WQM */
8832 if (ctx
->stage
== fragment_fs
&&
8833 !has_derivs
&& !has_lod
&& !level_zero
&&
8834 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8835 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8836 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8838 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8839 tex
->operands
[0] = Operand(resource
);
8840 tex
->operands
[1] = Operand(sampler
);
8841 tex
->operands
[2] = Operand(arg
);
8845 tex
->definitions
[0] = Definition(tmp_dst
);
8846 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8848 if (tg4_integer_cube_workaround
) {
8849 assert(tmp_dst
.id() != dst
.id());
8850 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8852 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8854 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8855 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8857 if (stype
== GLSL_TYPE_UINT
)
8858 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8860 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8861 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8863 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8864 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8865 val
[0], val
[1], val
[2], val
[3]);
8867 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8868 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8873 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8875 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8876 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8878 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8879 if (ctx
->program
->wave_size
== 64)
8880 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8882 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8884 return Operand(tmp
);
8888 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8890 aco_ptr
<Pseudo_instruction
> phi
;
8891 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8892 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8894 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8895 logical
|= ctx
->block
->kind
& block_kind_merge
;
8896 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8898 /* we want a sorted list of sources, since the predecessor list is also sorted */
8899 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8900 nir_foreach_phi_src(src
, instr
)
8901 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8903 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8904 unsigned num_operands
= 0;
8905 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8906 unsigned num_defined
= 0;
8907 unsigned cur_pred_idx
= 0;
8908 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8909 if (cur_pred_idx
< preds
.size()) {
8910 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8911 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8912 unsigned skipped
= 0;
8913 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8915 if (cur_pred_idx
+ skipped
< preds
.size()) {
8916 for (unsigned i
= 0; i
< skipped
; i
++)
8917 operands
[num_operands
++] = Operand(dst
.regClass());
8918 cur_pred_idx
+= skipped
;
8923 /* Handle missing predecessors at the end. This shouldn't happen with loop
8924 * headers and we can't ignore these sources for loop header phis. */
8925 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8928 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
8929 operands
[num_operands
++] = op
;
8930 num_defined
+= !op
.isUndefined();
8932 /* handle block_kind_continue_or_break at loop exit blocks */
8933 while (cur_pred_idx
++ < preds
.size())
8934 operands
[num_operands
++] = Operand(dst
.regClass());
8936 /* If the loop ends with a break, still add a linear continue edge in case
8937 * that break is divergent or continue_or_break is used. We'll either remove
8938 * this operand later in visit_loop() if it's not necessary or replace the
8939 * undef with something correct. */
8940 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8941 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8942 nir_block
*last
= nir_loop_last_block(loop
);
8943 if (last
->successors
[0] != instr
->instr
.block
)
8944 operands
[num_operands
++] = Operand(RegClass());
8947 if (num_defined
== 0) {
8948 Builder
bld(ctx
->program
, ctx
->block
);
8949 if (dst
.regClass() == s1
) {
8950 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8951 } else if (dst
.regClass() == v1
) {
8952 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8954 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8955 for (unsigned i
= 0; i
< dst
.size(); i
++)
8956 vec
->operands
[i
] = Operand(0u);
8957 vec
->definitions
[0] = Definition(dst
);
8958 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8963 /* we can use a linear phi in some cases if one src is undef */
8964 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8965 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8967 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8968 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8969 assert(invert
->kind
& block_kind_invert
);
8971 unsigned then_block
= invert
->linear_preds
[0];
8973 Block
* insert_block
= NULL
;
8974 for (unsigned i
= 0; i
< num_operands
; i
++) {
8975 Operand op
= operands
[i
];
8976 if (op
.isUndefined())
8978 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8979 phi
->operands
[0] = op
;
8982 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8983 phi
->operands
[1] = Operand(dst
.regClass());
8984 phi
->definitions
[0] = Definition(dst
);
8985 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8989 /* try to scalarize vector phis */
8990 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8991 // TODO: scalarize linear phis on divergent ifs
8992 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8993 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8994 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8995 Operand src
= operands
[i
];
8996 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8997 can_scalarize
= false;
8999 if (can_scalarize
) {
9000 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9001 assert(dst
.size() % num_components
== 0);
9002 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9004 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9005 for (unsigned k
= 0; k
< num_components
; k
++) {
9006 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9007 for (unsigned i
= 0; i
< num_operands
; i
++) {
9008 Operand src
= operands
[i
];
9009 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9011 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9012 phi
->definitions
[0] = Definition(phi_dst
);
9013 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9014 new_vec
[k
] = phi_dst
;
9015 vec
->operands
[k
] = Operand(phi_dst
);
9017 vec
->definitions
[0] = Definition(dst
);
9018 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9019 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9024 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9025 for (unsigned i
= 0; i
< num_operands
; i
++)
9026 phi
->operands
[i
] = operands
[i
];
9027 phi
->definitions
[0] = Definition(dst
);
9028 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9032 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9034 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9036 assert(dst
.type() == RegType::sgpr
);
9038 if (dst
.size() == 1) {
9039 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9041 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9042 for (unsigned i
= 0; i
< dst
.size(); i
++)
9043 vec
->operands
[i
] = Operand(0u);
9044 vec
->definitions
[0] = Definition(dst
);
9045 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9049 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9051 Builder
bld(ctx
->program
, ctx
->block
);
9052 Block
*logical_target
;
9053 append_logical_end(ctx
->block
);
9054 unsigned idx
= ctx
->block
->index
;
9056 switch (instr
->type
) {
9057 case nir_jump_break
:
9058 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9059 add_logical_edge(idx
, logical_target
);
9060 ctx
->block
->kind
|= block_kind_break
;
9062 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9063 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9064 /* uniform break - directly jump out of the loop */
9065 ctx
->block
->kind
|= block_kind_uniform
;
9066 ctx
->cf_info
.has_branch
= true;
9067 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9068 add_linear_edge(idx
, logical_target
);
9071 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9072 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9074 case nir_jump_continue
:
9075 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9076 add_logical_edge(idx
, logical_target
);
9077 ctx
->block
->kind
|= block_kind_continue
;
9079 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9080 /* for potential uniform breaks after this continue,
9081 we must ensure that they are handled correctly */
9082 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9083 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9084 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9086 /* uniform continue - directly jump to the loop header */
9087 ctx
->block
->kind
|= block_kind_uniform
;
9088 ctx
->cf_info
.has_branch
= true;
9089 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9090 add_linear_edge(idx
, logical_target
);
9095 isel_err(&instr
->instr
, "Unknown NIR jump instr");
9099 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9100 ctx
->cf_info
.exec_potentially_empty_break
= true;
9101 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9104 /* remove critical edges from linear CFG */
9105 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9106 Block
* break_block
= ctx
->program
->create_and_insert_block();
9107 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9108 break_block
->kind
|= block_kind_uniform
;
9109 add_linear_edge(idx
, break_block
);
9110 /* the loop_header pointer might be invalidated by this point */
9111 if (instr
->type
== nir_jump_continue
)
9112 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9113 add_linear_edge(break_block
->index
, logical_target
);
9114 bld
.reset(break_block
);
9115 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9117 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9118 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9119 add_linear_edge(idx
, continue_block
);
9120 append_logical_start(continue_block
);
9121 ctx
->block
= continue_block
;
9125 void visit_block(isel_context
*ctx
, nir_block
*block
)
9127 nir_foreach_instr(instr
, block
) {
9128 switch (instr
->type
) {
9129 case nir_instr_type_alu
:
9130 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9132 case nir_instr_type_load_const
:
9133 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9135 case nir_instr_type_intrinsic
:
9136 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9138 case nir_instr_type_tex
:
9139 visit_tex(ctx
, nir_instr_as_tex(instr
));
9141 case nir_instr_type_phi
:
9142 visit_phi(ctx
, nir_instr_as_phi(instr
));
9144 case nir_instr_type_ssa_undef
:
9145 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9147 case nir_instr_type_deref
:
9149 case nir_instr_type_jump
:
9150 visit_jump(ctx
, nir_instr_as_jump(instr
));
9153 isel_err(instr
, "Unknown NIR instr type");
9158 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9159 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9164 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9165 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9167 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9168 RegClass rc
= vals
[0].regClass();
9170 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9172 unsigned next_pred
= 1;
9174 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9175 Block
& block
= ctx
->program
->blocks
[idx
];
9176 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9177 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9181 if (block
.kind
& block_kind_continue
) {
9182 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9187 bool all_same
= true;
9188 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9189 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9193 val
= vals
[block
.linear_preds
[0] - first
];
9195 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9196 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9197 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9198 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9199 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9200 phi
->definitions
[0] = Definition(val
.getTemp());
9201 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9203 vals
[idx
- first
] = val
;
9206 return vals
[last
- first
];
9209 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9211 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9212 append_logical_end(ctx
->block
);
9213 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9214 Builder
bld(ctx
->program
, ctx
->block
);
9215 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9216 unsigned loop_preheader_idx
= ctx
->block
->index
;
9218 Block loop_exit
= Block();
9219 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9220 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9222 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9223 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9224 loop_header
->kind
|= block_kind_loop_header
;
9225 add_edge(loop_preheader_idx
, loop_header
);
9226 ctx
->block
= loop_header
;
9228 /* emit loop body */
9229 unsigned loop_header_idx
= loop_header
->index
;
9230 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9231 append_logical_start(ctx
->block
);
9232 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9234 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9235 if (!ctx
->cf_info
.has_branch
) {
9236 append_logical_end(ctx
->block
);
9237 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9238 /* Discards can result in code running with an empty exec mask.
9239 * This would result in divergent breaks not ever being taken. As a
9240 * workaround, break the loop when the loop mask is empty instead of
9241 * always continuing. */
9242 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9243 unsigned block_idx
= ctx
->block
->index
;
9245 /* create helper blocks to avoid critical edges */
9246 Block
*break_block
= ctx
->program
->create_and_insert_block();
9247 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9248 break_block
->kind
= block_kind_uniform
;
9249 bld
.reset(break_block
);
9250 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9251 add_linear_edge(block_idx
, break_block
);
9252 add_linear_edge(break_block
->index
, &loop_exit
);
9254 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9255 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9256 continue_block
->kind
= block_kind_uniform
;
9257 bld
.reset(continue_block
);
9258 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9259 add_linear_edge(block_idx
, continue_block
);
9260 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9262 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9263 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9264 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9266 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9267 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9268 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9270 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9273 bld
.reset(ctx
->block
);
9274 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9277 /* Fixup phis in loop header from unreachable blocks.
9278 * has_branch/has_divergent_branch also indicates if the loop ends with a
9279 * break/continue instruction, but we don't emit those if unreachable=true */
9281 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9282 bool linear
= ctx
->cf_info
.has_branch
;
9283 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9284 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9285 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9286 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9287 /* the last operand should be the one that needs to be removed */
9288 instr
->operands
.pop_back();
9289 } else if (!is_phi(instr
)) {
9295 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9296 * and the previous one shouldn't both happen at once because a break in the
9297 * merge block would get CSE'd */
9298 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9299 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9300 Operand vals
[num_vals
];
9301 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9302 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9303 if (ctx
->cf_info
.has_branch
)
9304 instr
->operands
.pop_back();
9306 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9307 } else if (!is_phi(instr
)) {
9313 ctx
->cf_info
.has_branch
= false;
9315 // TODO: if the loop has not a single exit, we must add one °°
9316 /* emit loop successor block */
9317 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9318 append_logical_start(ctx
->block
);
9321 // TODO: check if it is beneficial to not branch on continues
9322 /* trim linear phis in loop header */
9323 for (auto&& instr
: loop_entry
->instructions
) {
9324 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9325 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9326 new_phi
->definitions
[0] = instr
->definitions
[0];
9327 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9328 new_phi
->operands
[i
] = instr
->operands
[i
];
9329 /* check that the remaining operands are all the same */
9330 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9331 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9332 instr
.swap(new_phi
);
9333 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9342 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9346 append_logical_end(ctx
->block
);
9347 ctx
->block
->kind
|= block_kind_branch
;
9349 /* branch to linear then block */
9350 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9351 aco_ptr
<Pseudo_branch_instruction
> branch
;
9352 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 1));
9353 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9354 branch
->definitions
[0].setHint(vcc
);
9355 branch
->operands
[0] = Operand(cond
);
9356 ctx
->block
->instructions
.push_back(std::move(branch
));
9358 ic
->BB_if_idx
= ctx
->block
->index
;
9359 ic
->BB_invert
= Block();
9360 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9361 /* Invert blocks are intentionally not marked as top level because they
9362 * are not part of the logical cfg. */
9363 ic
->BB_invert
.kind
|= block_kind_invert
;
9364 ic
->BB_endif
= Block();
9365 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9366 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9368 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9369 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9370 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9371 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9372 ctx
->cf_info
.parent_if
.is_divergent
= true;
9374 /* divergent branches use cbranch_execz */
9375 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9376 ctx
->cf_info
.exec_potentially_empty_break
= false;
9377 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9379 /** emit logical then block */
9380 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9381 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9382 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9383 ctx
->block
= BB_then_logical
;
9384 append_logical_start(BB_then_logical
);
9387 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9389 Block
*BB_then_logical
= ctx
->block
;
9390 append_logical_end(BB_then_logical
);
9391 /* branch from logical then block to invert block */
9392 aco_ptr
<Pseudo_branch_instruction
> branch
;
9393 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9394 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9395 branch
->definitions
[0].setHint(vcc
);
9396 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9397 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9398 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9399 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9400 BB_then_logical
->kind
|= block_kind_uniform
;
9401 assert(!ctx
->cf_info
.has_branch
);
9402 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9403 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9405 /** emit linear then block */
9406 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9407 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9408 BB_then_linear
->kind
|= block_kind_uniform
;
9409 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9410 /* branch from linear then block to invert block */
9411 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9412 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9413 branch
->definitions
[0].setHint(vcc
);
9414 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9415 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9417 /** emit invert merge block */
9418 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9419 ic
->invert_idx
= ctx
->block
->index
;
9421 /* branch to linear else block (skip else) */
9422 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 1));
9423 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9424 branch
->definitions
[0].setHint(vcc
);
9425 branch
->operands
[0] = Operand(ic
->cond
);
9426 ctx
->block
->instructions
.push_back(std::move(branch
));
9428 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9429 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9430 ic
->exec_potentially_empty_break_depth_old
=
9431 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9432 /* divergent branches use cbranch_execz */
9433 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9434 ctx
->cf_info
.exec_potentially_empty_break
= false;
9435 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9437 /** emit logical else block */
9438 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9439 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9440 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9441 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9442 ctx
->block
= BB_else_logical
;
9443 append_logical_start(BB_else_logical
);
9446 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9448 Block
*BB_else_logical
= ctx
->block
;
9449 append_logical_end(BB_else_logical
);
9451 /* branch from logical else block to endif block */
9452 aco_ptr
<Pseudo_branch_instruction
> branch
;
9453 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9454 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9455 branch
->definitions
[0].setHint(vcc
);
9456 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9457 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9458 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9459 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9460 BB_else_logical
->kind
|= block_kind_uniform
;
9462 assert(!ctx
->cf_info
.has_branch
);
9463 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9466 /** emit linear else block */
9467 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9468 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9469 BB_else_linear
->kind
|= block_kind_uniform
;
9470 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9472 /* branch from linear else block to endif block */
9473 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9474 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9475 branch
->definitions
[0].setHint(vcc
);
9476 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9477 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9480 /** emit endif merge block */
9481 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9482 append_logical_start(ctx
->block
);
9485 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9486 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9487 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9488 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9489 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9490 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9491 !ctx
->cf_info
.parent_if
.is_divergent
) {
9492 ctx
->cf_info
.exec_potentially_empty_break
= false;
9493 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9495 /* uniform control flow never has an empty exec-mask */
9496 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9497 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9498 ctx
->cf_info
.exec_potentially_empty_break
= false;
9499 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9503 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9505 assert(cond
.regClass() == s1
);
9507 append_logical_end(ctx
->block
);
9508 ctx
->block
->kind
|= block_kind_uniform
;
9510 aco_ptr
<Pseudo_branch_instruction
> branch
;
9511 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9512 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 1));
9513 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9514 branch
->definitions
[0].setHint(vcc
);
9515 branch
->operands
[0] = Operand(cond
);
9516 branch
->operands
[0].setFixed(scc
);
9517 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9519 ic
->BB_if_idx
= ctx
->block
->index
;
9520 ic
->BB_endif
= Block();
9521 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9522 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9524 ctx
->cf_info
.has_branch
= false;
9525 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9527 /** emit then block */
9528 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9529 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9530 add_edge(ic
->BB_if_idx
, BB_then
);
9531 append_logical_start(BB_then
);
9532 ctx
->block
= BB_then
;
9535 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9537 Block
*BB_then
= ctx
->block
;
9539 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9540 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9542 if (!ic
->uniform_has_then_branch
) {
9543 append_logical_end(BB_then
);
9544 /* branch from then block to endif block */
9545 aco_ptr
<Pseudo_branch_instruction
> branch
;
9546 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9547 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9548 branch
->definitions
[0].setHint(vcc
);
9549 BB_then
->instructions
.emplace_back(std::move(branch
));
9550 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9551 if (!ic
->then_branch_divergent
)
9552 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9553 BB_then
->kind
|= block_kind_uniform
;
9556 ctx
->cf_info
.has_branch
= false;
9557 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9559 /** emit else block */
9560 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9561 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9562 add_edge(ic
->BB_if_idx
, BB_else
);
9563 append_logical_start(BB_else
);
9564 ctx
->block
= BB_else
;
9567 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9569 Block
*BB_else
= ctx
->block
;
9571 if (!ctx
->cf_info
.has_branch
) {
9572 append_logical_end(BB_else
);
9573 /* branch from then block to endif block */
9574 aco_ptr
<Pseudo_branch_instruction
> branch
;
9575 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9576 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9577 branch
->definitions
[0].setHint(vcc
);
9578 BB_else
->instructions
.emplace_back(std::move(branch
));
9579 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9580 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9581 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9582 BB_else
->kind
|= block_kind_uniform
;
9585 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9586 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9588 /** emit endif merge block */
9589 if (!ctx
->cf_info
.has_branch
) {
9590 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9591 append_logical_start(ctx
->block
);
9595 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9597 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9598 Builder
bld(ctx
->program
, ctx
->block
);
9599 aco_ptr
<Pseudo_branch_instruction
> branch
;
9602 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9604 * Uniform conditionals are represented in the following way*) :
9606 * The linear and logical CFG:
9609 * BB_THEN (logical) BB_ELSE (logical)
9613 * *) Exceptions may be due to break and continue statements within loops
9614 * If a break/continue happens within uniform control flow, it branches
9615 * to the loop exit/entry block. Otherwise, it branches to the next
9619 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9620 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9621 cond
= bool_to_scalar_condition(ctx
, cond
);
9623 begin_uniform_if_then(ctx
, &ic
, cond
);
9624 visit_cf_list(ctx
, &if_stmt
->then_list
);
9626 begin_uniform_if_else(ctx
, &ic
);
9627 visit_cf_list(ctx
, &if_stmt
->else_list
);
9629 end_uniform_if(ctx
, &ic
);
9630 } else { /* non-uniform condition */
9632 * To maintain a logical and linear CFG without critical edges,
9633 * non-uniform conditionals are represented in the following way*) :
9638 * BB_THEN (logical) BB_THEN (linear)
9640 * BB_INVERT (linear)
9642 * BB_ELSE (logical) BB_ELSE (linear)
9649 * BB_THEN (logical) BB_ELSE (logical)
9653 * *) Exceptions may be due to break and continue statements within loops
9656 begin_divergent_if_then(ctx
, &ic
, cond
);
9657 visit_cf_list(ctx
, &if_stmt
->then_list
);
9659 begin_divergent_if_else(ctx
, &ic
);
9660 visit_cf_list(ctx
, &if_stmt
->else_list
);
9662 end_divergent_if(ctx
, &ic
);
9665 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9668 static bool visit_cf_list(isel_context
*ctx
,
9669 struct exec_list
*list
)
9671 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9672 switch (node
->type
) {
9673 case nir_cf_node_block
:
9674 visit_block(ctx
, nir_cf_node_as_block(node
));
9676 case nir_cf_node_if
:
9677 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9680 case nir_cf_node_loop
:
9681 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9684 unreachable("unimplemented cf list type");
9690 static void create_null_export(isel_context
*ctx
)
9692 /* Some shader stages always need to have exports.
9693 * So when there is none, we need to add a null export.
9696 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9697 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9698 Builder
bld(ctx
->program
, ctx
->block
);
9699 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9700 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9703 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9705 assert(ctx
->stage
== vertex_vs
||
9706 ctx
->stage
== tess_eval_vs
||
9707 ctx
->stage
== gs_copy_vs
||
9708 ctx
->stage
== ngg_vertex_gs
||
9709 ctx
->stage
== ngg_tess_eval_gs
);
9711 int offset
= (ctx
->stage
& sw_tes
)
9712 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9713 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9714 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9715 if (!is_pos
&& !mask
)
9717 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9719 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9720 exp
->enabled_mask
= mask
;
9721 for (unsigned i
= 0; i
< 4; ++i
) {
9722 if (mask
& (1 << i
))
9723 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9725 exp
->operands
[i
] = Operand(v1
);
9727 /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9728 * Setting valid_mask=1 prevents it and has no other effect.
9730 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& is_pos
&& *next_pos
== 0;
9732 exp
->compressed
= false;
9734 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9736 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9737 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9742 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9744 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9745 exp
->enabled_mask
= 0;
9746 for (unsigned i
= 0; i
< 4; ++i
)
9747 exp
->operands
[i
] = Operand(v1
);
9748 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9749 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9750 exp
->enabled_mask
|= 0x1;
9752 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9753 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9754 exp
->enabled_mask
|= 0x4;
9756 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9757 if (ctx
->options
->chip_class
< GFX9
) {
9758 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9759 exp
->enabled_mask
|= 0x8;
9761 Builder
bld(ctx
->program
, ctx
->block
);
9763 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9764 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9765 if (exp
->operands
[2].isTemp())
9766 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9768 exp
->operands
[2] = Operand(out
);
9769 exp
->enabled_mask
|= 0x4;
9772 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& *next_pos
== 0;
9774 exp
->compressed
= false;
9775 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9776 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9779 static void create_export_phis(isel_context
*ctx
)
9781 /* Used when exports are needed, but the output temps are defined in a preceding block.
9782 * This function will set up phis in order to access the outputs in the next block.
9785 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9786 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9787 ctx
->block
->instructions
.pop_back();
9789 Builder
bld(ctx
->program
, ctx
->block
);
9791 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9792 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9793 for (unsigned i
= 0; i
< 4; ++i
) {
9794 if (!(mask
& (1 << i
)))
9797 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9798 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9799 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9803 bld
.insert(std::move(logical_start
));
9806 static void create_vs_exports(isel_context
*ctx
)
9808 assert(ctx
->stage
== vertex_vs
||
9809 ctx
->stage
== tess_eval_vs
||
9810 ctx
->stage
== gs_copy_vs
||
9811 ctx
->stage
== ngg_vertex_gs
||
9812 ctx
->stage
== ngg_tess_eval_gs
);
9814 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9815 ? &ctx
->program
->info
->tes
.outinfo
9816 : &ctx
->program
->info
->vs
.outinfo
;
9818 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9819 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9820 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9823 if (ctx
->options
->key
.has_multiview_view_index
) {
9824 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9825 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9828 /* the order these position exports are created is important */
9830 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9831 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9832 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9833 exported_pos
= true;
9835 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9836 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9837 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9838 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9840 if (ctx
->export_clip_dists
) {
9841 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9842 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9843 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9844 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9847 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9848 if (i
< VARYING_SLOT_VAR0
&&
9849 i
!= VARYING_SLOT_LAYER
&&
9850 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9851 i
!= VARYING_SLOT_VIEWPORT
)
9854 export_vs_varying(ctx
, i
, false, NULL
);
9858 create_null_export(ctx
);
9861 static bool export_fs_mrt_z(isel_context
*ctx
)
9863 Builder
bld(ctx
->program
, ctx
->block
);
9864 unsigned enabled_channels
= 0;
9868 for (unsigned i
= 0; i
< 4; ++i
) {
9869 values
[i
] = Operand(v1
);
9872 /* Both stencil and sample mask only need 16-bits. */
9873 if (!ctx
->program
->info
->ps
.writes_z
&&
9874 (ctx
->program
->info
->ps
.writes_stencil
||
9875 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9876 compr
= true; /* COMPR flag */
9878 if (ctx
->program
->info
->ps
.writes_stencil
) {
9879 /* Stencil should be in X[23:16]. */
9880 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9881 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9882 enabled_channels
|= 0x3;
9885 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9886 /* SampleMask should be in Y[15:0]. */
9887 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9888 enabled_channels
|= 0xc;
9891 if (ctx
->program
->info
->ps
.writes_z
) {
9892 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9893 enabled_channels
|= 0x1;
9896 if (ctx
->program
->info
->ps
.writes_stencil
) {
9897 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9898 enabled_channels
|= 0x2;
9901 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9902 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9903 enabled_channels
|= 0x4;
9907 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9908 * writemask component.
9910 if (ctx
->options
->chip_class
== GFX6
&&
9911 ctx
->options
->family
!= CHIP_OLAND
&&
9912 ctx
->options
->family
!= CHIP_HAINAN
) {
9913 enabled_channels
|= 0x1;
9916 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9917 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9922 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9924 Builder
bld(ctx
->program
, ctx
->block
);
9925 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9928 for (unsigned i
= 0; i
< 4; ++i
) {
9929 if (write_mask
& (1 << i
)) {
9930 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9932 values
[i
] = Operand(v1
);
9936 unsigned target
, col_format
;
9937 unsigned enabled_channels
= 0;
9938 aco_opcode compr_op
= (aco_opcode
)0;
9940 slot
-= FRAG_RESULT_DATA0
;
9941 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9942 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9944 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9945 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9946 bool is_16bit
= values
[0].regClass() == v2b
;
9950 case V_028714_SPI_SHADER_ZERO
:
9951 enabled_channels
= 0; /* writemask */
9952 target
= V_008DFC_SQ_EXP_NULL
;
9955 case V_028714_SPI_SHADER_32_R
:
9956 enabled_channels
= 1;
9959 case V_028714_SPI_SHADER_32_GR
:
9960 enabled_channels
= 0x3;
9963 case V_028714_SPI_SHADER_32_AR
:
9964 if (ctx
->options
->chip_class
>= GFX10
) {
9965 /* Special case: on GFX10, the outputs are different for 32_AR */
9966 enabled_channels
= 0x3;
9967 values
[1] = values
[3];
9968 values
[3] = Operand(v1
);
9970 enabled_channels
= 0x9;
9974 case V_028714_SPI_SHADER_FP16_ABGR
:
9975 enabled_channels
= 0x5;
9976 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9978 if (ctx
->options
->chip_class
>= GFX9
) {
9979 /* Pack the FP16 values together instead of converting them to
9980 * FP32 and back to FP16.
9981 * TODO: use p_create_vector and let the compiler optimizes.
9983 compr_op
= aco_opcode::v_pack_b32_f16
;
9985 for (unsigned i
= 0; i
< 4; i
++) {
9986 if ((write_mask
>> i
) & 1)
9987 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9993 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9994 enabled_channels
= 0x5;
9995 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9996 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9998 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10002 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10003 enabled_channels
= 0x5;
10004 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10005 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10007 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10011 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10012 enabled_channels
= 0x5;
10013 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10014 if (is_int8
|| is_int10
) {
10016 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10017 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10019 for (unsigned i
= 0; i
< 4; i
++) {
10020 if ((write_mask
>> i
) & 1) {
10021 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10022 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10026 } else if (is_16bit
) {
10027 for (unsigned i
= 0; i
< 4; i
++) {
10028 if ((write_mask
>> i
) & 1) {
10029 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10030 values
[i
] = Operand(tmp
);
10037 case V_028714_SPI_SHADER_SINT16_ABGR
:
10038 enabled_channels
= 0x5;
10039 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10040 if (is_int8
|| is_int10
) {
10042 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10043 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10044 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10045 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10047 for (unsigned i
= 0; i
< 4; i
++) {
10048 if ((write_mask
>> i
) & 1) {
10049 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10050 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10052 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10053 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10057 } else if (is_16bit
) {
10058 for (unsigned i
= 0; i
< 4; i
++) {
10059 if ((write_mask
>> i
) & 1) {
10060 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10061 values
[i
] = Operand(tmp
);
10067 case V_028714_SPI_SHADER_32_ABGR
:
10068 enabled_channels
= 0xF;
10075 if (target
== V_008DFC_SQ_EXP_NULL
)
10078 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10079 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10081 (col_format
== V_028714_SPI_SHADER_32_R
||
10082 col_format
== V_028714_SPI_SHADER_32_GR
||
10083 col_format
== V_028714_SPI_SHADER_32_AR
||
10084 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10085 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10086 for (int i
= 0; i
< 4; i
++) {
10087 if (!(write_mask
& (1 << i
)))
10090 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10091 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10092 bld
.copy(bld
.def(v1
), Operand(3u)));
10093 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10094 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10098 if ((bool) compr_op
) {
10099 for (int i
= 0; i
< 2; i
++) {
10100 /* check if at least one of the values to be compressed is enabled */
10101 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10103 enabled_channels
|= enabled
<< (i
*2);
10104 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10105 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10106 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10108 values
[i
] = Operand(v1
);
10111 values
[2] = Operand(v1
);
10112 values
[3] = Operand(v1
);
10114 for (int i
= 0; i
< 4; i
++)
10115 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10118 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10119 enabled_channels
, target
, (bool) compr_op
);
10123 static void create_fs_exports(isel_context
*ctx
)
10125 bool exported
= false;
10127 /* Export depth, stencil and sample mask. */
10128 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10129 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10130 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10131 exported
|= export_fs_mrt_z(ctx
);
10133 /* Export all color render targets. */
10134 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10135 if (ctx
->outputs
.mask
[i
])
10136 exported
|= export_fs_mrt_color(ctx
, i
);
10139 create_null_export(ctx
);
10142 static void create_workgroup_barrier(Builder
& bld
)
10144 bld
.barrier(aco_opcode::p_barrier
,
10145 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10149 static void write_tcs_tess_factors(isel_context
*ctx
)
10151 unsigned outer_comps
;
10152 unsigned inner_comps
;
10154 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10171 Builder
bld(ctx
->program
, ctx
->block
);
10173 create_workgroup_barrier(bld
);
10175 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10176 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10178 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10179 if_context ic_invocation_id_is_zero
;
10180 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10181 bld
.reset(ctx
->block
);
10183 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10185 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10186 unsigned stride
= inner_comps
+ outer_comps
;
10187 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10191 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10193 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10195 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10196 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10197 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10199 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10200 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10202 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10203 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10204 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10205 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10208 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10209 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10210 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10211 unsigned tf_const_offset
= 0;
10213 if (ctx
->program
->chip_class
<= GFX8
) {
10214 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10215 if_context ic_rel_patch_id_is_zero
;
10216 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10217 bld
.reset(ctx
->block
);
10219 /* Store the dynamic HS control word. */
10220 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10221 bld
.mubuf(aco_opcode::buffer_store_dword
,
10222 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10223 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10224 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10225 tf_const_offset
+= 4;
10227 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10228 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10229 bld
.reset(ctx
->block
);
10232 assert(stride
== 2 || stride
== 4 || stride
== 6);
10233 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10234 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10236 /* Store to offchip for TES to read - only if TES reads them */
10237 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10238 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10239 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10241 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10242 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10244 if (likely(inner_comps
)) {
10245 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10246 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10250 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10251 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10254 static void emit_stream_output(isel_context
*ctx
,
10255 Temp
const *so_buffers
,
10256 Temp
const *so_write_offset
,
10257 const struct radv_stream_output
*output
)
10259 unsigned num_comps
= util_bitcount(output
->component_mask
);
10260 unsigned writemask
= (1 << num_comps
) - 1;
10261 unsigned loc
= output
->location
;
10262 unsigned buf
= output
->buffer
;
10264 assert(num_comps
&& num_comps
<= 4);
10265 if (!num_comps
|| num_comps
> 4)
10268 unsigned start
= ffs(output
->component_mask
) - 1;
10271 bool all_undef
= true;
10272 assert(ctx
->stage
& hw_vs
);
10273 for (unsigned i
= 0; i
< num_comps
; i
++) {
10274 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10275 all_undef
= all_undef
&& !out
[i
].id();
10280 while (writemask
) {
10282 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10283 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10284 /* GFX6 doesn't support storing vec3, split it. */
10285 writemask
|= 1u << (start
+ 2);
10289 unsigned offset
= output
->offset
+ start
* 4;
10291 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10292 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10293 for (int i
= 0; i
< count
; ++i
)
10294 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10295 vec
->definitions
[0] = Definition(write_data
);
10296 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10301 opcode
= aco_opcode::buffer_store_dword
;
10304 opcode
= aco_opcode::buffer_store_dwordx2
;
10307 opcode
= aco_opcode::buffer_store_dwordx3
;
10310 opcode
= aco_opcode::buffer_store_dwordx4
;
10313 unreachable("Unsupported dword count.");
10316 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10317 store
->operands
[0] = Operand(so_buffers
[buf
]);
10318 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10319 store
->operands
[2] = Operand((uint32_t) 0);
10320 store
->operands
[3] = Operand(write_data
);
10321 if (offset
> 4095) {
10322 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10323 Builder
bld(ctx
->program
, ctx
->block
);
10324 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10326 store
->offset
= offset
;
10328 store
->offen
= true;
10330 store
->dlc
= false;
10332 ctx
->block
->instructions
.emplace_back(std::move(store
));
10336 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10338 Builder
bld(ctx
->program
, ctx
->block
);
10340 Temp so_buffers
[4];
10341 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10342 for (unsigned i
= 0; i
< 4; i
++) {
10343 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10347 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10348 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10351 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10352 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10354 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10356 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10359 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10361 bld
.reset(ctx
->block
);
10363 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10365 Temp so_write_offset
[4];
10367 for (unsigned i
= 0; i
< 4; i
++) {
10368 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10373 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10374 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10375 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10376 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10378 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10380 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10381 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10382 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10383 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10387 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10388 struct radv_stream_output
*output
=
10389 &ctx
->program
->info
->so
.outputs
[i
];
10390 if (stream
!= output
->stream
)
10393 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10396 begin_divergent_if_else(ctx
, &ic
);
10397 end_divergent_if(ctx
, &ic
);
10400 } /* end namespace */
10402 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10404 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10405 Builder
bld(ctx
->program
, ctx
->block
);
10406 constexpr unsigned hs_idx
= 1u;
10407 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10408 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10409 Operand((8u << 16) | (hs_idx
* 8u)));
10410 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10412 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10414 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10415 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10416 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10417 ls_has_nonzero_hs_threads
);
10418 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10419 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10420 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10421 ls_has_nonzero_hs_threads
);
10422 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10423 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10424 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10425 ls_has_nonzero_hs_threads
);
10427 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10428 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10429 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10432 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10434 /* Split all arguments except for the first (ring_offsets) and the last
10435 * (exec) so that the dead channels don't stay live throughout the program.
10437 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10438 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10439 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10440 startpgm
->definitions
[i
].regClass().size());
10445 void handle_bc_optimize(isel_context
*ctx
)
10447 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10448 Builder
bld(ctx
->program
, ctx
->block
);
10449 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10450 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10451 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10452 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10453 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10454 if (uses_center
&& uses_centroid
) {
10455 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10456 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10458 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10460 for (unsigned i
= 0; i
< 2; i
++) {
10461 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10462 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10463 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10464 persp_centroid
, persp_center
, sel
);
10466 ctx
->persp_centroid
= bld
.tmp(v2
);
10467 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10468 Operand(new_coord
[0]), Operand(new_coord
[1]));
10469 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10472 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10474 for (unsigned i
= 0; i
< 2; i
++) {
10475 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10476 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10477 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10478 linear_centroid
, linear_center
, sel
);
10480 ctx
->linear_centroid
= bld
.tmp(v2
);
10481 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10482 Operand(new_coord
[0]), Operand(new_coord
[1]));
10483 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10488 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10490 Program
*program
= ctx
->program
;
10492 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10494 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10495 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10496 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10497 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10498 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10500 program
->next_fp_mode
.must_flush_denorms32
=
10501 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10502 program
->next_fp_mode
.must_flush_denorms16_64
=
10503 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10504 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10506 program
->next_fp_mode
.care_about_round32
=
10507 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10509 program
->next_fp_mode
.care_about_round16_64
=
10510 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10511 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10513 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10514 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10515 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10516 program
->next_fp_mode
.denorm16_64
= 0;
10518 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10520 /* preserving fp32 denorms is expensive, so only do it if asked */
10521 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10522 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10524 program
->next_fp_mode
.denorm32
= 0;
10526 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10527 program
->next_fp_mode
.round32
= fp_round_tz
;
10529 program
->next_fp_mode
.round32
= fp_round_ne
;
10531 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10532 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10534 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10536 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10539 void cleanup_cfg(Program
*program
)
10541 /* create linear_succs/logical_succs */
10542 for (Block
& BB
: program
->blocks
) {
10543 for (unsigned idx
: BB
.linear_preds
)
10544 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10545 for (unsigned idx
: BB
.logical_preds
)
10546 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10550 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10552 Builder
bld(ctx
->program
, ctx
->block
);
10554 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10555 Temp count
= i
== 0
10556 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10557 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10558 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10560 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10563 if (ctx
->program
->wave_size
== 64) {
10564 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10565 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10566 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10568 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10569 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10575 bool ngg_early_prim_export(isel_context
*ctx
)
10577 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10581 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10583 Builder
bld(ctx
->program
, ctx
->block
);
10585 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10586 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10588 /* Get the id of the current wave within the threadgroup (workgroup) */
10589 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10590 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10592 /* Execute the following code only on the first wave (wave id 0),
10593 * use the SCC def to tell if the wave id is zero or not.
10595 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10597 begin_uniform_if_then(ctx
, &ic
, cond
);
10598 begin_uniform_if_else(ctx
, &ic
);
10599 bld
.reset(ctx
->block
);
10601 /* Number of vertices output by VS/TES */
10602 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10603 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10604 /* Number of primitives output by VS/TES */
10605 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10606 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10608 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10609 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10610 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10612 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10613 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10615 end_uniform_if(ctx
, &ic
);
10617 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10618 bld
.reset(ctx
->block
);
10619 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10622 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10624 Builder
bld(ctx
->program
, ctx
->block
);
10626 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10627 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10630 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10633 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10634 assert(vtxindex
[i
].id());
10637 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10641 /* The initial edge flag is always false in tess eval shaders. */
10642 if (ctx
->stage
== ngg_vertex_gs
) {
10643 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10644 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10648 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10653 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10655 Builder
bld(ctx
->program
, ctx
->block
);
10656 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10658 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10659 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10660 false /* compressed */, true/* done */, false /* valid mask */);
10663 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10665 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10666 * These must always come before VS exports.
10668 * It is recommended to do these as early as possible. They can be at the beginning when
10669 * there is no SW GS and the shader doesn't write edge flags.
10673 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10674 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10676 Builder
bld(ctx
->program
, ctx
->block
);
10677 constexpr unsigned max_vertices_per_primitive
= 3;
10678 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10680 if (ctx
->stage
== ngg_vertex_gs
) {
10681 /* TODO: optimize for points & lines */
10682 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10683 if (ctx
->shader
->info
.tess
.point_mode
)
10684 num_vertices_per_primitive
= 1;
10685 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10686 num_vertices_per_primitive
= 2;
10688 unreachable("Unsupported NGG shader stage");
10691 Temp vtxindex
[max_vertices_per_primitive
];
10692 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10693 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10694 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10695 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10696 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10697 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10698 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10699 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10701 /* Export primitive data to the index buffer. */
10702 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10704 /* Export primitive ID. */
10705 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10706 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10707 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10708 Temp provoking_vtx_index
= vtxindex
[0];
10709 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10711 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10714 begin_divergent_if_else(ctx
, &ic
);
10715 end_divergent_if(ctx
, &ic
);
10718 void ngg_emit_nogs_output(isel_context
*ctx
)
10720 /* Emits NGG GS output, for stages that don't have SW GS. */
10723 Builder
bld(ctx
->program
, ctx
->block
);
10724 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10726 /* NGG streamout is currently disabled by default. */
10727 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10729 if (late_prim_export
) {
10730 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10731 create_export_phis(ctx
);
10732 /* Do what we need to do in the GS threads. */
10733 ngg_emit_nogs_gsthreads(ctx
);
10735 /* What comes next should be executed on ES threads. */
10736 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10737 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10738 bld
.reset(ctx
->block
);
10741 /* Export VS outputs */
10742 ctx
->block
->kind
|= block_kind_export_end
;
10743 create_vs_exports(ctx
);
10745 /* Export primitive ID */
10746 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10749 if (ctx
->stage
== ngg_vertex_gs
) {
10750 /* Wait for GS threads to store primitive ID in LDS. */
10751 create_workgroup_barrier(bld
);
10753 /* Calculate LDS address where the GS threads stored the primitive ID. */
10754 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10755 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10756 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10757 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10758 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10759 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10761 /* Load primitive ID from LDS. */
10762 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10763 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10764 /* TES: Just use the patch ID as the primitive ID. */
10765 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10767 unreachable("unsupported NGG shader stage.");
10770 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10771 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10773 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10776 if (late_prim_export
) {
10777 begin_divergent_if_else(ctx
, &ic
);
10778 end_divergent_if(ctx
, &ic
);
10779 bld
.reset(ctx
->block
);
10783 void select_program(Program
*program
,
10784 unsigned shader_count
,
10785 struct nir_shader
*const *shaders
,
10786 ac_shader_config
* config
,
10787 struct radv_shader_args
*args
)
10789 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10790 if_context ic_merged_wave_info
;
10791 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10793 for (unsigned i
= 0; i
< shader_count
; i
++) {
10794 nir_shader
*nir
= shaders
[i
];
10795 init_context(&ctx
, nir
);
10797 setup_fp_mode(&ctx
, nir
);
10800 /* needs to be after init_context() for FS */
10801 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10802 append_logical_start(ctx
.block
);
10804 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10805 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10807 split_arguments(&ctx
, startpgm
);
10811 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10813 if (ngg_early_prim_export(&ctx
))
10814 ngg_emit_nogs_gsthreads(&ctx
);
10817 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10818 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10819 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10820 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10821 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10822 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10823 ctx
.stage
== tess_eval_geometry_gs
));
10825 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10826 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10827 if (check_merged_wave_info
) {
10828 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10829 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10833 Builder
bld(ctx
.program
, ctx
.block
);
10835 create_workgroup_barrier(bld
);
10837 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10838 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10840 } else if (ctx
.stage
== geometry_gs
)
10841 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10843 if (ctx
.stage
== fragment_fs
)
10844 handle_bc_optimize(&ctx
);
10846 visit_cf_list(&ctx
, &func
->body
);
10848 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10849 emit_streamout(&ctx
, 0);
10851 if (ctx
.stage
& hw_vs
) {
10852 create_vs_exports(&ctx
);
10853 ctx
.block
->kind
|= block_kind_export_end
;
10854 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10855 ngg_emit_nogs_output(&ctx
);
10856 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10857 Builder
bld(ctx
.program
, ctx
.block
);
10858 bld
.barrier(aco_opcode::p_barrier
,
10859 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
10860 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10861 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10862 write_tcs_tess_factors(&ctx
);
10865 if (ctx
.stage
== fragment_fs
) {
10866 create_fs_exports(&ctx
);
10867 ctx
.block
->kind
|= block_kind_export_end
;
10870 if (endif_merged_wave_info
) {
10871 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10872 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10875 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10876 ngg_emit_nogs_output(&ctx
);
10878 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10879 /* Outputs of the previous stage are inputs to the next stage */
10880 ctx
.inputs
= ctx
.outputs
;
10881 ctx
.outputs
= shader_io_state();
10885 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10887 append_logical_end(ctx
.block
);
10888 ctx
.block
->kind
|= block_kind_uniform
;
10889 Builder
bld(ctx
.program
, ctx
.block
);
10890 if (ctx
.program
->wb_smem_l1_on_end
)
10891 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
10892 bld
.sopp(aco_opcode::s_endpgm
);
10894 cleanup_cfg(program
);
10897 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10898 ac_shader_config
* config
,
10899 struct radv_shader_args
*args
)
10901 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10903 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10905 add_startpgm(&ctx
);
10906 append_logical_start(ctx
.block
);
10908 Builder
bld(ctx
.program
, ctx
.block
);
10910 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10912 Operand
stream_id(0u);
10913 if (args
->shader_info
->so
.num_outputs
)
10914 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10915 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10917 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10919 std::stack
<Block
> endif_blocks
;
10921 for (unsigned stream
= 0; stream
< 4; stream
++) {
10922 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10925 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10926 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10929 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10931 unsigned BB_if_idx
= ctx
.block
->index
;
10932 Block BB_endif
= Block();
10933 if (!stream_id
.isConstant()) {
10935 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10936 append_logical_end(ctx
.block
);
10937 ctx
.block
->kind
|= block_kind_uniform
;
10938 bld
.branch(aco_opcode::p_cbranch_z
, bld
.hint_vcc(bld
.def(s2
)), cond
);
10940 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10942 ctx
.block
= ctx
.program
->create_and_insert_block();
10943 add_edge(BB_if_idx
, ctx
.block
);
10944 bld
.reset(ctx
.block
);
10945 append_logical_start(ctx
.block
);
10948 unsigned offset
= 0;
10949 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10950 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10953 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10954 unsigned length
= util_last_bit(output_usage_mask
);
10955 for (unsigned j
= 0; j
< length
; ++j
) {
10956 if (!(output_usage_mask
& (1 << j
)))
10959 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10960 Temp voffset
= vtx_offset
;
10961 if (const_offset
>= 4096u) {
10962 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10963 const_offset
%= 4096u;
10966 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10967 mubuf
->definitions
[0] = bld
.def(v1
);
10968 mubuf
->operands
[0] = Operand(gsvs_ring
);
10969 mubuf
->operands
[1] = Operand(voffset
);
10970 mubuf
->operands
[2] = Operand(0u);
10971 mubuf
->offen
= true;
10972 mubuf
->offset
= const_offset
;
10975 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10977 ctx
.outputs
.mask
[i
] |= 1 << j
;
10978 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10980 bld
.insert(std::move(mubuf
));
10986 if (args
->shader_info
->so
.num_outputs
) {
10987 emit_streamout(&ctx
, stream
);
10988 bld
.reset(ctx
.block
);
10992 create_vs_exports(&ctx
);
10993 ctx
.block
->kind
|= block_kind_export_end
;
10996 if (!stream_id
.isConstant()) {
10997 append_logical_end(ctx
.block
);
10999 /* branch from then block to endif block */
11000 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
11001 add_edge(ctx
.block
->index
, &BB_endif
);
11002 ctx
.block
->kind
|= block_kind_uniform
;
11004 /* emit else block */
11005 ctx
.block
= ctx
.program
->create_and_insert_block();
11006 add_edge(BB_if_idx
, ctx
.block
);
11007 bld
.reset(ctx
.block
);
11008 append_logical_start(ctx
.block
);
11010 endif_blocks
.push(std::move(BB_endif
));
11014 while (!endif_blocks
.empty()) {
11015 Block BB_endif
= std::move(endif_blocks
.top());
11016 endif_blocks
.pop();
11018 Block
*BB_else
= ctx
.block
;
11020 append_logical_end(BB_else
);
11021 /* branch from else block to endif block */
11022 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
11023 add_edge(BB_else
->index
, &BB_endif
);
11024 BB_else
->kind
|= block_kind_uniform
;
11026 /** emit endif merge block */
11027 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11028 bld
.reset(ctx
.block
);
11029 append_logical_start(ctx
.block
);
11032 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11034 append_logical_end(ctx
.block
);
11035 ctx
.block
->kind
|= block_kind_uniform
;
11036 bld
.sopp(aco_opcode::s_endpgm
);
11038 cleanup_cfg(program
);
11041 void select_trap_handler_shader(Program
*program
, struct nir_shader
*shader
,
11042 ac_shader_config
* config
,
11043 struct radv_shader_args
*args
)
11045 assert(args
->options
->chip_class
== GFX8
);
11047 init_program(program
, compute_cs
, args
->shader_info
,
11048 args
->options
->chip_class
, args
->options
->family
, config
);
11050 isel_context ctx
= {};
11051 ctx
.program
= program
;
11053 ctx
.options
= args
->options
;
11054 ctx
.stage
= program
->stage
;
11056 ctx
.block
= ctx
.program
->create_and_insert_block();
11057 ctx
.block
->loop_nest_depth
= 0;
11058 ctx
.block
->kind
= block_kind_top_level
;
11060 program
->workgroup_size
= 1; /* XXX */
11062 add_startpgm(&ctx
);
11063 append_logical_start(ctx
.block
);
11065 Builder
bld(ctx
.program
, ctx
.block
);
11067 /* Load the buffer descriptor from TMA. */
11068 bld
.smem(aco_opcode::s_load_dwordx4
, Definition(PhysReg
{ttmp4
}, s4
),
11069 Operand(PhysReg
{tma
}, s2
), Operand(0u));
11071 /* Store TTMP0-TTMP1. */
11072 bld
.smem(aco_opcode::s_buffer_store_dwordx2
, Operand(PhysReg
{ttmp4
}, s4
),
11073 Operand(0u), Operand(PhysReg
{ttmp0
}, s2
), memory_sync_info(), true);
11075 uint32_t hw_regs_idx
[] = {
11076 2, /* HW_REG_STATUS */
11077 3, /* HW_REG_TRAP_STS */
11078 4, /* HW_REG_HW_ID */
11079 7, /* HW_REG_IB_STS */
11082 /* Store some hardware registers. */
11083 for (unsigned i
= 0; i
< ARRAY_SIZE(hw_regs_idx
); i
++) {
11084 /* "((size - 1) << 11) | register" */
11085 bld
.sopk(aco_opcode::s_getreg_b32
, Definition(PhysReg
{ttmp8
}, s1
),
11086 ((20 - 1) << 11) | hw_regs_idx
[i
]);
11088 bld
.smem(aco_opcode::s_buffer_store_dword
, Operand(PhysReg
{ttmp4
}, s4
),
11089 Operand(8u + i
* 4), Operand(PhysReg
{ttmp8
}, s1
), memory_sync_info(), true);
11092 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11094 append_logical_end(ctx
.block
);
11095 ctx
.block
->kind
|= block_kind_uniform
;
11096 bld
.sopp(aco_opcode::s_endpgm
);
11098 cleanup_cfg(program
);