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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
509 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
513 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
515 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
518 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
519 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
520 for (unsigned i
= 0; i
< size
; ++i
) {
521 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
522 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
524 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
525 vec_instr
->definitions
[0] = Definition(dst
);
526 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
527 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
532 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
536 Builder
bld(ctx
->program
, ctx
->block
);
537 if (ptr
.type() == RegType::vgpr
)
538 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
539 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
540 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
543 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
545 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
546 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
547 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
548 sop2
->definitions
[0] = Definition(dst
);
550 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
551 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
554 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
555 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
557 Builder
bld(ctx
->program
, ctx
->block
);
558 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
559 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
560 if (src1
.type() == RegType::sgpr
) {
561 if (commutative
&& src0
.type() == RegType::vgpr
) {
566 src1
= as_vgpr(ctx
, src1
);
570 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
571 assert(dst
.size() == 1);
572 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
573 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
575 bld
.vop2(op
, Definition(dst
), src0
, src1
);
579 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
580 bool flush_denorms
= false)
582 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
583 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
584 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
586 /* ensure that the instruction has at most 1 sgpr operand
587 * The optimizer will inline constants for us */
588 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
589 src0
= as_vgpr(ctx
, src0
);
590 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
591 src1
= as_vgpr(ctx
, src1
);
592 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
593 src2
= as_vgpr(ctx
, src2
);
595 Builder
bld(ctx
->program
, ctx
->block
);
596 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
597 assert(dst
.size() == 1);
598 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
599 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
601 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
605 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
607 Builder
bld(ctx
->program
, ctx
->block
);
608 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
611 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
613 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
614 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
615 assert(src0
.size() == src1
.size());
617 aco_ptr
<Instruction
> vopc
;
618 if (src1
.type() == RegType::sgpr
) {
619 if (src0
.type() == RegType::vgpr
) {
620 /* to swap the operands, we might also have to change the opcode */
622 case aco_opcode::v_cmp_lt_f16
:
623 op
= aco_opcode::v_cmp_gt_f16
;
625 case aco_opcode::v_cmp_ge_f16
:
626 op
= aco_opcode::v_cmp_le_f16
;
628 case aco_opcode::v_cmp_lt_i16
:
629 op
= aco_opcode::v_cmp_gt_i16
;
631 case aco_opcode::v_cmp_ge_i16
:
632 op
= aco_opcode::v_cmp_le_i16
;
634 case aco_opcode::v_cmp_lt_u16
:
635 op
= aco_opcode::v_cmp_gt_u16
;
637 case aco_opcode::v_cmp_ge_u16
:
638 op
= aco_opcode::v_cmp_le_u16
;
640 case aco_opcode::v_cmp_lt_f32
:
641 op
= aco_opcode::v_cmp_gt_f32
;
643 case aco_opcode::v_cmp_ge_f32
:
644 op
= aco_opcode::v_cmp_le_f32
;
646 case aco_opcode::v_cmp_lt_i32
:
647 op
= aco_opcode::v_cmp_gt_i32
;
649 case aco_opcode::v_cmp_ge_i32
:
650 op
= aco_opcode::v_cmp_le_i32
;
652 case aco_opcode::v_cmp_lt_u32
:
653 op
= aco_opcode::v_cmp_gt_u32
;
655 case aco_opcode::v_cmp_ge_u32
:
656 op
= aco_opcode::v_cmp_le_u32
;
658 case aco_opcode::v_cmp_lt_f64
:
659 op
= aco_opcode::v_cmp_gt_f64
;
661 case aco_opcode::v_cmp_ge_f64
:
662 op
= aco_opcode::v_cmp_le_f64
;
664 case aco_opcode::v_cmp_lt_i64
:
665 op
= aco_opcode::v_cmp_gt_i64
;
667 case aco_opcode::v_cmp_ge_i64
:
668 op
= aco_opcode::v_cmp_le_i64
;
670 case aco_opcode::v_cmp_lt_u64
:
671 op
= aco_opcode::v_cmp_gt_u64
;
673 case aco_opcode::v_cmp_ge_u64
:
674 op
= aco_opcode::v_cmp_le_u64
;
676 default: /* eq and ne are commutative */
683 src1
= as_vgpr(ctx
, src1
);
687 Builder
bld(ctx
->program
, ctx
->block
);
688 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
691 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
693 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
694 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
695 Builder
bld(ctx
->program
, ctx
->block
);
697 assert(dst
.regClass() == bld
.lm
);
698 assert(src0
.type() == RegType::sgpr
);
699 assert(src1
.type() == RegType::sgpr
);
700 assert(src0
.regClass() == src1
.regClass());
702 /* Emit the SALU comparison instruction */
703 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
704 /* Turn the result into a per-lane bool */
705 bool_to_vector_condition(ctx
, cmp
, dst
);
708 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
709 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
711 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
712 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
713 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
714 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
716 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
717 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
718 aco_opcode op
= use_valu
? v_op
: s_op
;
719 assert(op
!= aco_opcode::num_opcodes
);
720 assert(dst
.regClass() == ctx
->program
->lane_mask
);
723 emit_vopc_instruction(ctx
, instr
, op
, dst
);
725 emit_sopc_instruction(ctx
, instr
, op
, dst
);
728 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
730 Builder
bld(ctx
->program
, ctx
->block
);
731 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
734 assert(dst
.regClass() == bld
.lm
);
735 assert(src0
.regClass() == bld
.lm
);
736 assert(src1
.regClass() == bld
.lm
);
738 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
741 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
743 Builder
bld(ctx
->program
, ctx
->block
);
744 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
745 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
746 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
748 assert(cond
.regClass() == bld
.lm
);
750 if (dst
.type() == RegType::vgpr
) {
751 aco_ptr
<Instruction
> bcsel
;
752 if (dst
.regClass() == v2b
) {
753 then
= as_vgpr(ctx
, then
);
754 els
= as_vgpr(ctx
, els
);
756 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
757 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
758 } else if (dst
.regClass() == v1
) {
759 then
= as_vgpr(ctx
, then
);
760 els
= as_vgpr(ctx
, els
);
762 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
763 } else if (dst
.regClass() == v2
) {
764 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
765 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
766 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
767 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
769 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
770 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
772 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
774 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
775 nir_print_instr(&instr
->instr
, stderr
);
776 fprintf(stderr
, "\n");
781 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
782 assert(dst
.regClass() == bld
.lm
);
783 assert(then
.regClass() == bld
.lm
);
784 assert(els
.regClass() == bld
.lm
);
787 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
788 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
789 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
790 assert(dst
.size() == then
.size());
791 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
792 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
794 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
795 nir_print_instr(&instr
->instr
, stderr
);
796 fprintf(stderr
, "\n");
801 /* divergent boolean bcsel
802 * this implements bcsel on bools: dst = s0 ? s1 : s2
803 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
804 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
806 if (cond
.id() != then
.id())
807 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
809 if (cond
.id() == els
.id())
810 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
812 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
813 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
816 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
817 aco_opcode op
, uint32_t undo
)
819 /* multiply by 16777216 to handle denormals */
820 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
821 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
822 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
823 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
824 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
826 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
828 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
831 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
833 if (ctx
->block
->fp_mode
.denorm32
== 0) {
834 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
838 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
841 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
843 if (ctx
->block
->fp_mode
.denorm32
== 0) {
844 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
848 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
851 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
853 if (ctx
->block
->fp_mode
.denorm32
== 0) {
854 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
858 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
861 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
863 if (ctx
->block
->fp_mode
.denorm32
== 0) {
864 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
868 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
871 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
873 if (ctx
->options
->chip_class
>= GFX7
)
874 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
876 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
877 /* TODO: create more efficient code! */
878 if (val
.type() == RegType::sgpr
)
879 val
= as_vgpr(ctx
, val
);
881 /* Split the input value. */
882 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
883 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
885 /* Extract the exponent and compute the unbiased value. */
886 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
888 /* Extract the fractional part. */
889 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
890 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
892 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
893 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
895 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
896 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
897 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
898 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
899 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
901 /* Get the sign bit. */
902 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
904 /* Decide the operation to apply depending on the unbiased exponent. */
905 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
906 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
907 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
908 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
909 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
910 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
912 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
915 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
917 if (ctx
->options
->chip_class
>= GFX7
)
918 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
920 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
921 Temp src0
= as_vgpr(ctx
, val
);
923 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
924 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
926 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
927 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
928 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
930 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
931 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
932 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
933 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
935 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
936 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
938 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
940 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
941 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
943 return add
->definitions
[0].getTemp();
946 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
948 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
949 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
951 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
954 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
955 return bld
.copy(Definition(dst
), src
);
956 else if (dst
.bytes() < src
.bytes())
957 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
961 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
964 } else if (src
.regClass() == s1
) {
966 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
968 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
970 assert(src_bits
!= 8 || src
.regClass() == v1b
);
971 assert(src_bits
!= 16 || src
.regClass() == v2b
);
972 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
973 sdwa
->operands
[0] = Operand(src
);
974 sdwa
->definitions
[0] = Definition(tmp
);
976 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
978 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
979 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
980 bld
.insert(std::move(sdwa
));
983 if (dst_bits
== 64) {
984 if (is_signed
&& dst
.regClass() == s2
) {
985 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
986 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
987 } else if (is_signed
&& dst
.regClass() == v2
) {
988 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
989 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
991 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
998 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1000 if (!instr
->dest
.dest
.is_ssa
) {
1001 fprintf(stderr
, "nir alu dst not in ssa: ");
1002 nir_print_instr(&instr
->instr
, stderr
);
1003 fprintf(stderr
, "\n");
1006 Builder
bld(ctx
->program
, ctx
->block
);
1007 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1012 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1013 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1014 for (unsigned i
= 0; i
< num
; ++i
)
1015 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1017 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1018 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1019 for (unsigned i
= 0; i
< num
; ++i
)
1020 vec
->operands
[i
] = Operand
{elems
[i
]};
1021 vec
->definitions
[0] = Definition(dst
);
1022 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1023 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1025 // TODO: that is a bit suboptimal..
1026 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1027 for (unsigned i
= 0; i
< num
- 1; ++i
)
1028 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1029 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1030 for (unsigned i
= 0; i
< num
; ++i
) {
1031 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1032 if (bit
% 32 == 0) {
1033 elems
[bit
/ 32] = elems
[i
];
1035 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1036 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1037 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1040 if (dst
.size() == 1)
1041 bld
.copy(Definition(dst
), elems
[0]);
1043 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1048 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1049 aco_ptr
<Instruction
> mov
;
1050 if (dst
.type() == RegType::sgpr
) {
1051 if (src
.type() == RegType::vgpr
)
1052 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1053 else if (src
.regClass() == s1
)
1054 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1055 else if (src
.regClass() == s2
)
1056 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1058 unreachable("wrong src register class for nir_op_imov");
1059 } else if (dst
.regClass() == v1
) {
1060 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1061 } else if (dst
.regClass() == v2
) {
1062 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1064 nir_print_instr(&instr
->instr
, stderr
);
1065 unreachable("Should have been lowered to scalar.");
1070 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1071 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1072 assert(src
.regClass() == bld
.lm
);
1073 assert(dst
.regClass() == bld
.lm
);
1074 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1075 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1076 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1077 } else if (dst
.regClass() == v1
) {
1078 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1079 } else if (dst
.type() == RegType::sgpr
) {
1080 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1081 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1083 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1084 nir_print_instr(&instr
->instr
, stderr
);
1085 fprintf(stderr
, "\n");
1090 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1091 if (dst
.regClass() == v1
) {
1092 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1093 } else if (dst
.regClass() == s1
) {
1094 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1095 } else if (dst
.size() == 2) {
1096 Temp src0
= bld
.tmp(dst
.type(), 1);
1097 Temp src1
= bld
.tmp(dst
.type(), 1);
1098 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1100 if (dst
.regClass() == s2
) {
1101 Temp carry
= bld
.tmp(s1
);
1102 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1103 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1104 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1106 Temp lower
= bld
.tmp(v1
);
1107 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1108 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1109 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1112 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1113 nir_print_instr(&instr
->instr
, stderr
);
1114 fprintf(stderr
, "\n");
1119 if (dst
.regClass() == s1
) {
1120 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1121 } else if (dst
.regClass() == v1
) {
1122 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1123 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1131 case nir_op_isign
: {
1132 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1133 if (dst
.regClass() == s1
) {
1134 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1135 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1136 } else if (dst
.regClass() == s2
) {
1137 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1139 if (ctx
->program
->chip_class
>= GFX8
)
1140 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1142 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1143 /* SCC gets zero-extended to 64 bit */
1144 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1145 } else if (dst
.regClass() == v1
) {
1146 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1147 } else if (dst
.regClass() == v2
) {
1148 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1149 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1150 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1151 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1152 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1156 nir_print_instr(&instr
->instr
, stderr
);
1157 fprintf(stderr
, "\n");
1162 if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1167 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1168 nir_print_instr(&instr
->instr
, stderr
);
1169 fprintf(stderr
, "\n");
1174 if (dst
.regClass() == v1
) {
1175 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1176 } else if (dst
.regClass() == s1
) {
1177 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1179 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1180 nir_print_instr(&instr
->instr
, stderr
);
1181 fprintf(stderr
, "\n");
1186 if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1191 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1192 nir_print_instr(&instr
->instr
, stderr
);
1193 fprintf(stderr
, "\n");
1198 if (dst
.regClass() == v1
) {
1199 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1200 } else if (dst
.regClass() == s1
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1203 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1204 nir_print_instr(&instr
->instr
, stderr
);
1205 fprintf(stderr
, "\n");
1210 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1211 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1212 } else if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1214 } else if (dst
.regClass() == s1
) {
1215 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1216 } else if (dst
.regClass() == s2
) {
1217 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1219 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1220 nir_print_instr(&instr
->instr
, stderr
);
1221 fprintf(stderr
, "\n");
1226 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1227 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1228 } else if (dst
.regClass() == v1
) {
1229 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1230 } else if (dst
.regClass() == s1
) {
1231 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1232 } else if (dst
.regClass() == s2
) {
1233 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1235 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1236 nir_print_instr(&instr
->instr
, stderr
);
1237 fprintf(stderr
, "\n");
1242 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1243 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1244 } else if (dst
.regClass() == v1
) {
1245 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1246 } else if (dst
.regClass() == s1
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1248 } else if (dst
.regClass() == s2
) {
1249 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1251 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1252 nir_print_instr(&instr
->instr
, stderr
);
1253 fprintf(stderr
, "\n");
1258 if (dst
.regClass() == v1
) {
1259 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1260 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1261 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1262 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1263 } else if (dst
.regClass() == v2
) {
1264 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1265 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1266 } else if (dst
.regClass() == s2
) {
1267 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1268 } else if (dst
.regClass() == s1
) {
1269 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1271 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1272 nir_print_instr(&instr
->instr
, stderr
);
1273 fprintf(stderr
, "\n");
1278 if (dst
.regClass() == v1
) {
1279 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1280 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1281 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1282 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1283 } else if (dst
.regClass() == v2
) {
1284 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1285 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1286 } else if (dst
.regClass() == s1
) {
1287 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1288 } else if (dst
.regClass() == s2
) {
1289 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1291 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1292 nir_print_instr(&instr
->instr
, stderr
);
1293 fprintf(stderr
, "\n");
1298 if (dst
.regClass() == v1
) {
1299 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1300 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1301 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1302 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1303 } else if (dst
.regClass() == v2
) {
1304 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1305 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1306 } else if (dst
.regClass() == s1
) {
1307 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1308 } else if (dst
.regClass() == s2
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1311 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1312 nir_print_instr(&instr
->instr
, stderr
);
1313 fprintf(stderr
, "\n");
1317 case nir_op_find_lsb
: {
1318 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1319 if (src
.regClass() == s1
) {
1320 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1321 } else if (src
.regClass() == v1
) {
1322 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1323 } else if (src
.regClass() == s2
) {
1324 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1326 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1327 nir_print_instr(&instr
->instr
, stderr
);
1328 fprintf(stderr
, "\n");
1332 case nir_op_ufind_msb
:
1333 case nir_op_ifind_msb
: {
1334 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1335 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1336 aco_opcode op
= src
.regClass() == s2
?
1337 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1338 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1339 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1341 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1342 Operand(src
.size() * 32u - 1u), msb_rev
);
1343 Temp msb
= sub
.def(0).getTemp();
1344 Temp carry
= sub
.def(1).getTemp();
1346 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1347 } else if (src
.regClass() == v1
) {
1348 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1349 Temp msb_rev
= bld
.tmp(v1
);
1350 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1351 Temp msb
= bld
.tmp(v1
);
1352 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1353 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1355 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1356 nir_print_instr(&instr
->instr
, stderr
);
1357 fprintf(stderr
, "\n");
1361 case nir_op_bitfield_reverse
: {
1362 if (dst
.regClass() == s1
) {
1363 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1364 } else if (dst
.regClass() == v1
) {
1365 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1367 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1368 nir_print_instr(&instr
->instr
, stderr
);
1369 fprintf(stderr
, "\n");
1374 if (dst
.regClass() == s1
) {
1375 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1379 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1380 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1381 if (dst
.regClass() == v1
) {
1382 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1386 assert(src0
.size() == 2 && src1
.size() == 2);
1387 Temp src00
= bld
.tmp(src0
.type(), 1);
1388 Temp src01
= bld
.tmp(dst
.type(), 1);
1389 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1390 Temp src10
= bld
.tmp(src1
.type(), 1);
1391 Temp src11
= bld
.tmp(dst
.type(), 1);
1392 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1394 if (dst
.regClass() == s2
) {
1395 Temp carry
= bld
.tmp(s1
);
1396 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1397 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1398 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1399 } else if (dst
.regClass() == v2
) {
1400 Temp dst0
= bld
.tmp(v1
);
1401 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1402 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1403 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1405 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1406 nir_print_instr(&instr
->instr
, stderr
);
1407 fprintf(stderr
, "\n");
1411 case nir_op_uadd_sat
: {
1412 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1413 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1414 if (dst
.regClass() == s1
) {
1415 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1416 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1418 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1419 } else if (dst
.regClass() == v1
) {
1420 if (ctx
->options
->chip_class
>= GFX9
) {
1421 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1422 add
->operands
[0] = Operand(src0
);
1423 add
->operands
[1] = Operand(src1
);
1424 add
->definitions
[0] = Definition(dst
);
1426 ctx
->block
->instructions
.emplace_back(std::move(add
));
1428 if (src1
.regClass() != v1
)
1429 std::swap(src0
, src1
);
1430 assert(src1
.regClass() == v1
);
1431 Temp tmp
= bld
.tmp(v1
);
1432 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1433 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1436 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1437 nir_print_instr(&instr
->instr
, stderr
);
1438 fprintf(stderr
, "\n");
1442 case nir_op_uadd_carry
: {
1443 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1444 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1445 if (dst
.regClass() == s1
) {
1446 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1449 if (dst
.regClass() == v1
) {
1450 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1451 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1455 Temp src00
= bld
.tmp(src0
.type(), 1);
1456 Temp src01
= bld
.tmp(dst
.type(), 1);
1457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1458 Temp src10
= bld
.tmp(src1
.type(), 1);
1459 Temp src11
= bld
.tmp(dst
.type(), 1);
1460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1461 if (dst
.regClass() == s2
) {
1462 Temp carry
= bld
.tmp(s1
);
1463 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1464 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1465 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1466 } else if (dst
.regClass() == v2
) {
1467 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1468 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1469 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1472 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1473 nir_print_instr(&instr
->instr
, stderr
);
1474 fprintf(stderr
, "\n");
1479 if (dst
.regClass() == s1
) {
1480 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1484 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1485 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1486 if (dst
.regClass() == v1
) {
1487 bld
.vsub32(Definition(dst
), src0
, src1
);
1491 Temp src00
= bld
.tmp(src0
.type(), 1);
1492 Temp src01
= bld
.tmp(dst
.type(), 1);
1493 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1494 Temp src10
= bld
.tmp(src1
.type(), 1);
1495 Temp src11
= bld
.tmp(dst
.type(), 1);
1496 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1497 if (dst
.regClass() == s2
) {
1498 Temp carry
= bld
.tmp(s1
);
1499 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1500 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1501 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1502 } else if (dst
.regClass() == v2
) {
1503 Temp lower
= bld
.tmp(v1
);
1504 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1505 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1506 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1508 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1509 nir_print_instr(&instr
->instr
, stderr
);
1510 fprintf(stderr
, "\n");
1514 case nir_op_usub_borrow
: {
1515 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1516 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1517 if (dst
.regClass() == s1
) {
1518 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1520 } else if (dst
.regClass() == v1
) {
1521 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1522 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1526 Temp src00
= bld
.tmp(src0
.type(), 1);
1527 Temp src01
= bld
.tmp(dst
.type(), 1);
1528 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1529 Temp src10
= bld
.tmp(src1
.type(), 1);
1530 Temp src11
= bld
.tmp(dst
.type(), 1);
1531 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1532 if (dst
.regClass() == s2
) {
1533 Temp borrow
= bld
.tmp(s1
);
1534 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1535 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1536 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1537 } else if (dst
.regClass() == v2
) {
1538 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1539 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1540 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1543 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1544 nir_print_instr(&instr
->instr
, stderr
);
1545 fprintf(stderr
, "\n");
1550 if (dst
.regClass() == v1
) {
1551 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1552 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1553 } else if (dst
.regClass() == s1
) {
1554 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1556 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1557 nir_print_instr(&instr
->instr
, stderr
);
1558 fprintf(stderr
, "\n");
1562 case nir_op_umul_high
: {
1563 if (dst
.regClass() == v1
) {
1564 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1565 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1566 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1567 } else if (dst
.regClass() == s1
) {
1568 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1569 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1570 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1572 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1573 nir_print_instr(&instr
->instr
, stderr
);
1574 fprintf(stderr
, "\n");
1578 case nir_op_imul_high
: {
1579 if (dst
.regClass() == v1
) {
1580 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1581 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1582 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1583 } else if (dst
.regClass() == s1
) {
1584 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1585 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1586 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1588 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1589 nir_print_instr(&instr
->instr
, stderr
);
1590 fprintf(stderr
, "\n");
1595 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1596 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1597 if (dst
.regClass() == v2b
) {
1598 Temp tmp
= bld
.tmp(v1
);
1599 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1600 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1601 } else if (dst
.regClass() == v1
) {
1602 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1603 } else if (dst
.regClass() == v2
) {
1604 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1606 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1607 nir_print_instr(&instr
->instr
, stderr
);
1608 fprintf(stderr
, "\n");
1613 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1614 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1615 if (dst
.regClass() == v2b
) {
1616 Temp tmp
= bld
.tmp(v1
);
1617 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1618 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1619 } else if (dst
.regClass() == v1
) {
1620 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1621 } else if (dst
.regClass() == v2
) {
1622 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1624 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1625 nir_print_instr(&instr
->instr
, stderr
);
1626 fprintf(stderr
, "\n");
1631 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1632 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1633 if (dst
.regClass() == v2b
) {
1634 Temp tmp
= bld
.tmp(v1
);
1635 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1636 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1638 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1639 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1640 } else if (dst
.regClass() == v1
) {
1641 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1642 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1644 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1645 } else if (dst
.regClass() == v2
) {
1646 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1647 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1648 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1651 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1652 nir_print_instr(&instr
->instr
, stderr
);
1653 fprintf(stderr
, "\n");
1658 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1659 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1660 if (dst
.regClass() == v2b
) {
1661 // TODO: check fp_mode.must_flush_denorms16_64
1662 Temp tmp
= bld
.tmp(v1
);
1663 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1664 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1665 } else if (dst
.regClass() == v1
) {
1666 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1667 } else if (dst
.regClass() == v2
) {
1668 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1669 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1670 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1672 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1675 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1676 nir_print_instr(&instr
->instr
, stderr
);
1677 fprintf(stderr
, "\n");
1682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1683 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1684 if (dst
.regClass() == v2b
) {
1685 // TODO: check fp_mode.must_flush_denorms16_64
1686 Temp tmp
= bld
.tmp(v1
);
1687 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1688 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1689 } else if (dst
.regClass() == v1
) {
1690 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1691 } else if (dst
.regClass() == v2
) {
1692 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1693 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1694 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1696 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1705 case nir_op_fmax3
: {
1706 if (dst
.regClass() == v2b
) {
1707 Temp tmp
= bld
.tmp(v1
);
1708 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1709 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1713 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1714 nir_print_instr(&instr
->instr
, stderr
);
1715 fprintf(stderr
, "\n");
1719 case nir_op_fmin3
: {
1720 if (dst
.regClass() == v2b
) {
1721 Temp tmp
= bld
.tmp(v1
);
1722 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1723 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1727 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1728 nir_print_instr(&instr
->instr
, stderr
);
1729 fprintf(stderr
, "\n");
1733 case nir_op_fmed3
: {
1734 if (dst
.regClass() == v2b
) {
1735 Temp tmp
= bld
.tmp(v1
);
1736 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1737 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1738 } else if (dst
.regClass() == v1
) {
1739 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1742 nir_print_instr(&instr
->instr
, stderr
);
1743 fprintf(stderr
, "\n");
1747 case nir_op_umax3
: {
1748 if (dst
.size() == 1) {
1749 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1751 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1752 nir_print_instr(&instr
->instr
, stderr
);
1753 fprintf(stderr
, "\n");
1757 case nir_op_umin3
: {
1758 if (dst
.size() == 1) {
1759 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1761 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1762 nir_print_instr(&instr
->instr
, stderr
);
1763 fprintf(stderr
, "\n");
1767 case nir_op_umed3
: {
1768 if (dst
.size() == 1) {
1769 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1771 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1772 nir_print_instr(&instr
->instr
, stderr
);
1773 fprintf(stderr
, "\n");
1777 case nir_op_imax3
: {
1778 if (dst
.size() == 1) {
1779 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1781 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1782 nir_print_instr(&instr
->instr
, stderr
);
1783 fprintf(stderr
, "\n");
1787 case nir_op_imin3
: {
1788 if (dst
.size() == 1) {
1789 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1791 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1792 nir_print_instr(&instr
->instr
, stderr
);
1793 fprintf(stderr
, "\n");
1797 case nir_op_imed3
: {
1798 if (dst
.size() == 1) {
1799 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1802 nir_print_instr(&instr
->instr
, stderr
);
1803 fprintf(stderr
, "\n");
1807 case nir_op_cube_face_coord
: {
1808 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1809 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1810 emit_extract_vector(ctx
, in
, 1, v1
),
1811 emit_extract_vector(ctx
, in
, 2, v1
) };
1812 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1813 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1814 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1815 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1816 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1817 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1818 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1821 case nir_op_cube_face_index
: {
1822 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1823 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1824 emit_extract_vector(ctx
, in
, 1, v1
),
1825 emit_extract_vector(ctx
, in
, 2, v1
) };
1826 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1829 case nir_op_bcsel
: {
1830 emit_bcsel(ctx
, instr
, dst
);
1834 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1835 if (dst
.regClass() == v2b
) {
1836 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1837 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1838 } else if (dst
.regClass() == v1
) {
1839 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1840 } else if (dst
.regClass() == v2
) {
1841 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1843 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1844 nir_print_instr(&instr
->instr
, stderr
);
1845 fprintf(stderr
, "\n");
1850 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1851 if (dst
.regClass() == v2b
) {
1852 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1853 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1854 } else if (dst
.regClass() == v1
) {
1855 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1856 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1857 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1858 } else if (dst
.regClass() == v2
) {
1859 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1860 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1861 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1862 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1863 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1864 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1866 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1867 nir_print_instr(&instr
->instr
, stderr
);
1868 fprintf(stderr
, "\n");
1873 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1874 if (dst
.regClass() == v2b
) {
1875 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1877 } else if (dst
.regClass() == v1
) {
1878 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1879 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1880 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1881 } else if (dst
.regClass() == v2
) {
1882 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1883 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1884 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1885 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1886 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1887 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1889 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1890 nir_print_instr(&instr
->instr
, stderr
);
1891 fprintf(stderr
, "\n");
1896 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1897 if (dst
.regClass() == v2b
) {
1898 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1899 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1900 } else if (dst
.regClass() == v1
) {
1901 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1902 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1903 // TODO: confirm that this holds under any circumstances
1904 } else if (dst
.regClass() == v2
) {
1905 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1906 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1909 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1910 nir_print_instr(&instr
->instr
, stderr
);
1911 fprintf(stderr
, "\n");
1915 case nir_op_flog2
: {
1916 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1917 if (dst
.regClass() == v2b
) {
1918 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1919 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1920 } else if (dst
.regClass() == v1
) {
1921 emit_log2(ctx
, bld
, Definition(dst
), src
);
1923 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1924 nir_print_instr(&instr
->instr
, stderr
);
1925 fprintf(stderr
, "\n");
1930 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1931 if (dst
.regClass() == v2b
) {
1932 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1933 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1934 } else if (dst
.regClass() == v1
) {
1935 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1936 } else if (dst
.regClass() == v2
) {
1937 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1939 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1940 nir_print_instr(&instr
->instr
, stderr
);
1941 fprintf(stderr
, "\n");
1945 case nir_op_fexp2
: {
1946 if (dst
.regClass() == v2b
) {
1947 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1948 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1949 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1950 } else if (dst
.regClass() == v1
) {
1951 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1953 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1954 nir_print_instr(&instr
->instr
, stderr
);
1955 fprintf(stderr
, "\n");
1959 case nir_op_fsqrt
: {
1960 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1961 if (dst
.regClass() == v2b
) {
1962 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1963 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1964 } else if (dst
.regClass() == v1
) {
1965 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1966 } else if (dst
.regClass() == v2
) {
1967 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1969 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1970 nir_print_instr(&instr
->instr
, stderr
);
1971 fprintf(stderr
, "\n");
1975 case nir_op_ffract
: {
1976 if (dst
.regClass() == v2b
) {
1977 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1978 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1979 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1980 } else if (dst
.regClass() == v1
) {
1981 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1982 } else if (dst
.regClass() == v2
) {
1983 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1985 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1986 nir_print_instr(&instr
->instr
, stderr
);
1987 fprintf(stderr
, "\n");
1991 case nir_op_ffloor
: {
1992 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1993 if (dst
.regClass() == v2b
) {
1994 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1995 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1996 } else if (dst
.regClass() == v1
) {
1997 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1998 } else if (dst
.regClass() == v2
) {
1999 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2001 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2002 nir_print_instr(&instr
->instr
, stderr
);
2003 fprintf(stderr
, "\n");
2007 case nir_op_fceil
: {
2008 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2009 if (dst
.regClass() == v2b
) {
2010 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
2011 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2012 } else if (dst
.regClass() == v1
) {
2013 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2014 } else if (dst
.regClass() == v2
) {
2015 if (ctx
->options
->chip_class
>= GFX7
) {
2016 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2018 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2019 /* trunc = trunc(src0)
2020 * if (src0 > 0.0 && src0 != trunc)
2023 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2024 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2025 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2026 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2027 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2028 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2029 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2032 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2033 nir_print_instr(&instr
->instr
, stderr
);
2034 fprintf(stderr
, "\n");
2038 case nir_op_ftrunc
: {
2039 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2040 if (dst
.regClass() == v2b
) {
2041 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2042 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2043 } else if (dst
.regClass() == v1
) {
2044 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2045 } else if (dst
.regClass() == v2
) {
2046 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2048 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2049 nir_print_instr(&instr
->instr
, stderr
);
2050 fprintf(stderr
, "\n");
2054 case nir_op_fround_even
: {
2055 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2056 if (dst
.regClass() == v2b
) {
2057 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2058 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2059 } else if (dst
.regClass() == v1
) {
2060 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2061 } else if (dst
.regClass() == v2
) {
2062 if (ctx
->options
->chip_class
>= GFX7
) {
2063 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2065 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2066 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2067 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2069 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2070 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2071 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2072 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2073 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2074 tmp
= sub
->definitions
[0].getTemp();
2076 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2077 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2078 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2079 Temp cond
= vop3
->definitions
[0].getTemp();
2081 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2082 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2083 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2084 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2086 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2090 nir_print_instr(&instr
->instr
, stderr
);
2091 fprintf(stderr
, "\n");
2097 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2098 aco_ptr
<Instruction
> norm
;
2099 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2100 if (dst
.regClass() == v2b
) {
2101 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2102 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2103 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2104 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2105 } else if (dst
.regClass() == v1
) {
2106 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2108 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2109 if (ctx
->options
->chip_class
< GFX9
)
2110 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2112 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2113 bld
.vop1(opcode
, Definition(dst
), tmp
);
2115 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2116 nir_print_instr(&instr
->instr
, stderr
);
2117 fprintf(stderr
, "\n");
2121 case nir_op_ldexp
: {
2122 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2123 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2124 if (dst
.regClass() == v2b
) {
2125 Temp tmp
= bld
.tmp(v1
);
2126 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2127 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2128 } else if (dst
.regClass() == v1
) {
2129 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2130 } else if (dst
.regClass() == v2
) {
2131 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2133 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2134 nir_print_instr(&instr
->instr
, stderr
);
2135 fprintf(stderr
, "\n");
2139 case nir_op_frexp_sig
: {
2140 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2141 if (dst
.regClass() == v2b
) {
2142 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2143 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2144 } else if (dst
.regClass() == v1
) {
2145 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2146 } else if (dst
.regClass() == v2
) {
2147 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2150 nir_print_instr(&instr
->instr
, stderr
);
2151 fprintf(stderr
, "\n");
2155 case nir_op_frexp_exp
: {
2156 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2157 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2158 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2159 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2160 convert_int(bld
, tmp
, 8, 32, true, dst
);
2161 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2162 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2163 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2164 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2166 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2167 nir_print_instr(&instr
->instr
, stderr
);
2168 fprintf(stderr
, "\n");
2172 case nir_op_fsign
: {
2173 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2174 if (dst
.regClass() == v2b
) {
2175 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2176 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2177 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2178 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2179 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2180 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2181 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2182 } else if (dst
.regClass() == v1
) {
2183 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2184 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2185 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2186 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2187 } else if (dst
.regClass() == v2
) {
2188 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2189 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2190 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2192 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2193 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2194 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2196 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2198 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2199 nir_print_instr(&instr
->instr
, stderr
);
2200 fprintf(stderr
, "\n");
2205 case nir_op_f2f16_rtne
: {
2206 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2207 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2208 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2209 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2210 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2213 case nir_op_f2f16_rtz
: {
2214 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2215 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2216 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2217 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2218 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2221 case nir_op_f2f32
: {
2222 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2223 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2224 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2225 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2227 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2228 nir_print_instr(&instr
->instr
, stderr
);
2229 fprintf(stderr
, "\n");
2233 case nir_op_f2f64
: {
2234 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2235 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2236 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2237 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2240 case nir_op_i2f16
: {
2241 assert(dst
.regClass() == v2b
);
2242 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2243 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2244 src
= convert_int(bld
, src
, 8, 16, true);
2245 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
), src
);
2246 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2249 case nir_op_i2f32
: {
2250 assert(dst
.size() == 1);
2251 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2252 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2253 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2254 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2257 case nir_op_i2f64
: {
2258 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2259 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2260 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2261 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2262 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2263 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2264 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2265 RegClass rc
= RegClass(src
.type(), 1);
2266 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2267 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2268 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2269 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2270 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2271 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2274 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2275 nir_print_instr(&instr
->instr
, stderr
);
2276 fprintf(stderr
, "\n");
2280 case nir_op_u2f16
: {
2281 assert(dst
.regClass() == v2b
);
2282 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2283 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2284 src
= convert_int(bld
, src
, 8, 16, false);
2285 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
), src
);
2286 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2289 case nir_op_u2f32
: {
2290 assert(dst
.size() == 1);
2291 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2292 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2293 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2294 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2296 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2297 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2298 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2302 case nir_op_u2f64
: {
2303 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2304 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2305 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2306 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2307 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2308 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2309 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2310 RegClass rc
= RegClass(src
.type(), 1);
2311 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2312 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2313 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2314 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2315 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2316 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2318 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2319 nir_print_instr(&instr
->instr
, stderr
);
2320 fprintf(stderr
, "\n");
2325 case nir_op_f2i16
: {
2326 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2327 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2328 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2329 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2330 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2332 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2334 if (dst
.type() == RegType::vgpr
)
2335 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2337 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2341 case nir_op_f2u16
: {
2342 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2343 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2344 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2345 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2346 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2348 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2350 if (dst
.type() == RegType::vgpr
)
2351 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2353 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2356 case nir_op_f2i32
: {
2357 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2358 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2359 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2360 if (dst
.type() == RegType::vgpr
) {
2361 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2363 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2364 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2366 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2367 if (dst
.type() == RegType::vgpr
)
2368 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2370 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2371 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2373 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2374 if (dst
.type() == RegType::vgpr
)
2375 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2377 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2378 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2381 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2382 nir_print_instr(&instr
->instr
, stderr
);
2383 fprintf(stderr
, "\n");
2387 case nir_op_f2u32
: {
2388 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2389 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2390 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2391 if (dst
.type() == RegType::vgpr
) {
2392 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2394 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2395 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2397 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2398 if (dst
.type() == RegType::vgpr
)
2399 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2401 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2402 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2404 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2405 if (dst
.type() == RegType::vgpr
)
2406 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2408 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2409 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2412 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2413 nir_print_instr(&instr
->instr
, stderr
);
2414 fprintf(stderr
, "\n");
2418 case nir_op_f2i64
: {
2419 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2420 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2421 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2423 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2424 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2425 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2426 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2427 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2428 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2429 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2430 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2431 Temp new_exponent
= bld
.tmp(v1
);
2432 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2433 if (ctx
->program
->chip_class
>= GFX8
)
2434 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2436 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2437 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2438 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2439 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2440 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2441 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2442 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2443 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2444 Temp new_lower
= bld
.tmp(v1
);
2445 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2446 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2447 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2449 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2450 if (src
.type() == RegType::vgpr
)
2451 src
= bld
.as_uniform(src
);
2452 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2453 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2454 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2455 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2456 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2457 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2458 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2459 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2460 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2461 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2462 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2463 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2464 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2465 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2466 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2467 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2468 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2469 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2470 Temp borrow
= bld
.tmp(s1
);
2471 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2472 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2473 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2475 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2476 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2477 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2478 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2479 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2480 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2481 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2482 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2483 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2484 if (dst
.type() == RegType::sgpr
) {
2485 lower
= bld
.as_uniform(lower
);
2486 upper
= bld
.as_uniform(upper
);
2488 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2491 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2492 nir_print_instr(&instr
->instr
, stderr
);
2493 fprintf(stderr
, "\n");
2497 case nir_op_f2u64
: {
2498 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2499 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2500 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2502 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2503 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2504 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2505 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2506 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2507 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2508 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2509 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2510 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2511 Temp new_exponent
= bld
.tmp(v1
);
2512 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2513 if (ctx
->program
->chip_class
>= GFX8
)
2514 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2516 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2517 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2518 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2519 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2520 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2521 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2522 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2525 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2526 if (src
.type() == RegType::vgpr
)
2527 src
= bld
.as_uniform(src
);
2528 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2529 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2530 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2531 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2532 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2533 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2534 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2535 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2536 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2537 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2538 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2539 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2540 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2541 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2542 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2543 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2544 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2545 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2547 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2548 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2549 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2550 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2551 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2552 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2553 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2554 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2555 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2556 if (dst
.type() == RegType::sgpr
) {
2557 lower
= bld
.as_uniform(lower
);
2558 upper
= bld
.as_uniform(upper
);
2560 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2563 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2564 nir_print_instr(&instr
->instr
, stderr
);
2565 fprintf(stderr
, "\n");
2569 case nir_op_b2f16
: {
2570 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2571 assert(src
.regClass() == bld
.lm
);
2573 if (dst
.regClass() == s1
) {
2574 src
= bool_to_scalar_condition(ctx
, src
);
2575 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2576 } else if (dst
.regClass() == v2b
) {
2577 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2578 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2579 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2581 unreachable("Wrong destination register class for nir_op_b2f16.");
2585 case nir_op_b2f32
: {
2586 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2587 assert(src
.regClass() == bld
.lm
);
2589 if (dst
.regClass() == s1
) {
2590 src
= bool_to_scalar_condition(ctx
, src
);
2591 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2592 } else if (dst
.regClass() == v1
) {
2593 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2595 unreachable("Wrong destination register class for nir_op_b2f32.");
2599 case nir_op_b2f64
: {
2600 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2601 assert(src
.regClass() == bld
.lm
);
2603 if (dst
.regClass() == s2
) {
2604 src
= bool_to_scalar_condition(ctx
, src
);
2605 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2606 } else if (dst
.regClass() == v2
) {
2607 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2608 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2609 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2611 unreachable("Wrong destination register class for nir_op_b2f64.");
2618 case nir_op_i2i64
: {
2619 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2620 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2626 case nir_op_u2u64
: {
2627 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2628 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2632 case nir_op_b2i32
: {
2633 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2634 assert(src
.regClass() == bld
.lm
);
2636 if (dst
.regClass() == s1
) {
2637 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2638 bool_to_scalar_condition(ctx
, src
, dst
);
2639 } else if (dst
.regClass() == v1
) {
2640 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2642 unreachable("Invalid register class for b2i32");
2648 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2649 assert(dst
.regClass() == bld
.lm
);
2651 if (src
.type() == RegType::vgpr
) {
2652 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2653 assert(dst
.regClass() == bld
.lm
);
2654 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2655 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2657 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2659 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2660 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2662 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2663 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2665 bool_to_vector_condition(ctx
, tmp
, dst
);
2669 case nir_op_pack_64_2x32_split
: {
2670 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2671 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2673 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2676 case nir_op_unpack_64_2x32_split_x
:
2677 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2679 case nir_op_unpack_64_2x32_split_y
:
2680 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2682 case nir_op_unpack_32_2x16_split_x
:
2683 if (dst
.type() == RegType::vgpr
) {
2684 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2686 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2689 case nir_op_unpack_32_2x16_split_y
:
2690 if (dst
.type() == RegType::vgpr
) {
2691 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2693 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2696 case nir_op_pack_32_2x16_split
: {
2697 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2698 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2699 if (dst
.regClass() == v1
) {
2700 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2701 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2702 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2704 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2705 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2706 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2710 case nir_op_pack_half_2x16
: {
2711 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2713 if (dst
.regClass() == v1
) {
2714 Temp src0
= bld
.tmp(v1
);
2715 Temp src1
= bld
.tmp(v1
);
2716 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2717 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2718 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2720 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2721 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2722 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2724 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2725 nir_print_instr(&instr
->instr
, stderr
);
2726 fprintf(stderr
, "\n");
2730 case nir_op_unpack_half_2x16_split_x
: {
2731 if (dst
.regClass() == v1
) {
2732 Builder
bld(ctx
->program
, ctx
->block
);
2733 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2735 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2736 nir_print_instr(&instr
->instr
, stderr
);
2737 fprintf(stderr
, "\n");
2741 case nir_op_unpack_half_2x16_split_y
: {
2742 if (dst
.regClass() == v1
) {
2743 Builder
bld(ctx
->program
, ctx
->block
);
2744 /* TODO: use SDWA here */
2745 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2746 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2748 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2749 nir_print_instr(&instr
->instr
, stderr
);
2750 fprintf(stderr
, "\n");
2754 case nir_op_fquantize2f16
: {
2755 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2756 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2759 if (ctx
->program
->chip_class
>= GFX8
) {
2760 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2761 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2762 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2764 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2765 * so compare the result and flush to 0 if it's smaller.
2767 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2768 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2769 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2770 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2771 cmp_res
= vop3
->definitions
[0].getTemp();
2774 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2775 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2776 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2778 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2783 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2784 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2786 if (dst
.regClass() == s1
) {
2787 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2788 } else if (dst
.regClass() == v1
) {
2789 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2791 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2792 nir_print_instr(&instr
->instr
, stderr
);
2793 fprintf(stderr
, "\n");
2797 case nir_op_bitfield_select
: {
2798 /* (mask & insert) | (~mask & base) */
2799 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2800 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2801 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2803 /* dst = (insert & bitmask) | (base & ~bitmask) */
2804 if (dst
.regClass() == s1
) {
2805 aco_ptr
<Instruction
> sop2
;
2806 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2807 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2809 if (const_insert
&& const_bitmask
) {
2810 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2812 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2813 lhs
= Operand(insert
);
2817 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2818 if (const_base
&& const_bitmask
) {
2819 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2821 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2822 rhs
= Operand(base
);
2825 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2827 } else if (dst
.regClass() == v1
) {
2828 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2829 base
= as_vgpr(ctx
, base
);
2830 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2831 insert
= as_vgpr(ctx
, insert
);
2833 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2836 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2837 nir_print_instr(&instr
->instr
, stderr
);
2838 fprintf(stderr
, "\n");
2844 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2845 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2846 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2848 if (dst
.type() == RegType::sgpr
) {
2850 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2851 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2852 if (const_offset
&& const_bits
) {
2853 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2854 extract
= Operand(const_extract
);
2858 width
= Operand(const_bits
->u32
<< 16);
2860 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2862 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2866 if (dst
.regClass() == s1
) {
2867 if (instr
->op
== nir_op_ubfe
)
2868 opcode
= aco_opcode::s_bfe_u32
;
2870 opcode
= aco_opcode::s_bfe_i32
;
2871 } else if (dst
.regClass() == s2
) {
2872 if (instr
->op
== nir_op_ubfe
)
2873 opcode
= aco_opcode::s_bfe_u64
;
2875 opcode
= aco_opcode::s_bfe_i64
;
2877 unreachable("Unsupported BFE bit size");
2880 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2884 if (dst
.regClass() == v1
) {
2885 if (instr
->op
== nir_op_ubfe
)
2886 opcode
= aco_opcode::v_bfe_u32
;
2888 opcode
= aco_opcode::v_bfe_i32
;
2890 unreachable("Unsupported BFE bit size");
2893 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2897 case nir_op_bit_count
: {
2898 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2899 if (src
.regClass() == s1
) {
2900 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2901 } else if (src
.regClass() == v1
) {
2902 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2903 } else if (src
.regClass() == v2
) {
2904 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2905 emit_extract_vector(ctx
, src
, 1, v1
),
2906 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2907 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2908 } else if (src
.regClass() == s2
) {
2909 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2912 nir_print_instr(&instr
->instr
, stderr
);
2913 fprintf(stderr
, "\n");
2918 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2922 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2926 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2930 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2934 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2938 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2942 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2943 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2945 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2946 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2950 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2951 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2953 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2954 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2958 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2962 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2967 case nir_op_fddx_fine
:
2968 case nir_op_fddy_fine
:
2969 case nir_op_fddx_coarse
:
2970 case nir_op_fddy_coarse
: {
2971 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2972 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2973 if (instr
->op
== nir_op_fddx_fine
) {
2974 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2975 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2976 } else if (instr
->op
== nir_op_fddy_fine
) {
2977 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2978 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2980 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2981 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2982 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2984 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2988 if (ctx
->program
->chip_class
>= GFX8
) {
2989 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2990 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2992 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2993 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2994 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2996 emit_wqm(ctx
, tmp
, dst
, true);
3000 fprintf(stderr
, "Unknown NIR ALU instr: ");
3001 nir_print_instr(&instr
->instr
, stderr
);
3002 fprintf(stderr
, "\n");
3006 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3008 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3010 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3011 // which get truncated the lsb if double and msb if int
3012 // for now, we only use s_mov_b64 with 64bit inline constants
3013 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3014 assert(dst
.type() == RegType::sgpr
);
3016 Builder
bld(ctx
->program
, ctx
->block
);
3018 if (instr
->def
.bit_size
== 1) {
3019 assert(dst
.regClass() == bld
.lm
);
3020 int val
= instr
->value
[0].b
? -1 : 0;
3021 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3022 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3023 } else if (instr
->def
.bit_size
== 8) {
3024 /* ensure that the value is correctly represented in the low byte of the register */
3025 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3026 } else if (instr
->def
.bit_size
== 16) {
3027 /* ensure that the value is correctly represented in the low half of the register */
3028 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3029 } else if (dst
.size() == 1) {
3030 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3032 assert(dst
.size() != 1);
3033 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3034 if (instr
->def
.bit_size
== 64)
3035 for (unsigned i
= 0; i
< dst
.size(); i
++)
3036 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3038 for (unsigned i
= 0; i
< dst
.size(); i
++)
3039 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3041 vec
->definitions
[0] = Definition(dst
);
3042 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3046 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3048 uint32_t new_mask
= 0;
3049 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3050 if (mask
& (1u << i
))
3051 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3055 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3057 Builder
bld(ctx
->program
, ctx
->block
);
3058 if (offset
.isTemp()) {
3059 Temp tmp
[3] = {vec
, vec
, vec
};
3061 if (vec
.size() == 3) {
3062 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3063 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3064 } else if (vec
.size() == 2) {
3065 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3066 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3068 for (unsigned i
= 0; i
< dst
.size(); i
++)
3069 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3072 if (dst
.size() == 2)
3073 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3075 offset
= Operand(0u);
3078 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3079 bld
.copy(Definition(dst
), vec
);
3081 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3084 struct LoadEmitInfo
{
3087 unsigned num_components
;
3088 unsigned component_size
;
3089 Temp resource
= Temp(0, s1
);
3090 unsigned component_stride
= 0;
3091 unsigned const_offset
= 0;
3092 unsigned align_mul
= 0;
3093 unsigned align_offset
= 0;
3096 unsigned swizzle_component_size
= 0;
3097 barrier_interaction barrier
= barrier_none
;
3098 bool can_reorder
= true;
3099 Temp soffset
= Temp(0, s1
);
3102 using LoadCallback
= Temp(*)(
3103 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3104 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3106 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3107 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3109 unsigned load_size
= info
->num_components
* info
->component_size
;
3110 unsigned component_size
= info
->component_size
;
3112 unsigned num_vals
= 0;
3113 Temp vals
[info
->dst
.bytes()];
3115 unsigned const_offset
= info
->const_offset
;
3117 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3118 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3120 unsigned bytes_read
= 0;
3121 while (bytes_read
< load_size
) {
3122 unsigned bytes_needed
= load_size
- bytes_read
;
3124 /* add buffer for unaligned loads */
3125 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3128 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3129 if (info
->component_stride
) {
3130 assert(supports_8bit_16bit_loads
&& "unimplemented");
3134 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3135 bytes_needed
= align(bytes_needed
, 4);
3142 if (info
->swizzle_component_size
)
3143 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3144 if (info
->component_stride
)
3145 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3147 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3149 /* reduce constant offset */
3150 Operand offset
= info
->offset
;
3151 unsigned reduced_const_offset
= const_offset
;
3152 bool remove_const_offset_completely
= need_to_align_offset
;
3153 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3154 unsigned to_add
= const_offset
;
3155 if (remove_const_offset_completely
) {
3156 reduced_const_offset
= 0;
3158 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3159 reduced_const_offset
%= max_const_offset_plus_one
;
3161 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3162 if (offset
.isConstant()) {
3163 offset
= Operand(offset
.constantValue() + to_add
);
3164 } else if (offset_tmp
.regClass() == s1
) {
3165 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3166 offset_tmp
, Operand(to_add
));
3167 } else if (offset_tmp
.regClass() == v1
) {
3168 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3170 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3171 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3172 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3174 if (offset_tmp
.regClass() == s2
) {
3175 Temp carry
= bld
.tmp(s1
);
3176 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3177 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3178 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3180 Temp new_lo
= bld
.tmp(v1
);
3181 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3182 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3183 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3188 /* align offset down if needed */
3189 Operand aligned_offset
= offset
;
3190 if (need_to_align_offset
) {
3191 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3192 if (offset
.isConstant()) {
3193 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3194 } else if (offset_tmp
.regClass() == s1
) {
3195 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3196 } else if (offset_tmp
.regClass() == s2
) {
3197 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3198 } else if (offset_tmp
.regClass() == v1
) {
3199 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3200 } else if (offset_tmp
.regClass() == v2
) {
3201 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3202 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3203 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3204 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3207 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3208 bld
.copy(bld
.def(s1
), aligned_offset
);
3210 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3211 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3212 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3214 /* shift result right if needed */
3216 Operand
align((uint32_t)byte_align
);
3217 if (byte_align
== -1) {
3218 if (offset
.isConstant())
3219 align
= Operand(offset
.constantValue() % 4u);
3220 else if (offset
.size() == 2)
3221 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3226 if (align
.isTemp() || align
.constantValue()) {
3227 assert(val
.bytes() >= load_size
&& "unimplemented");
3228 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3229 if (val
.type() == RegType::sgpr
)
3230 byte_align_scalar(ctx
, val
, align
, new_val
);
3232 byte_align_vector(ctx
, val
, align
, new_val
);
3237 /* add result to list and advance */
3238 if (info
->component_stride
) {
3239 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3240 const_offset
+= info
->component_stride
;
3241 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3243 const_offset
+= val
.bytes();
3244 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3246 bytes_read
+= val
.bytes();
3247 vals
[num_vals
++] = val
;
3250 /* the callback wrote directly to dst */
3251 if (vals
[0] == info
->dst
) {
3252 assert(num_vals
== 1);
3253 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3257 /* create array of components */
3258 unsigned components_split
= 0;
3259 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3260 bool has_vgprs
= false;
3261 for (unsigned i
= 0; i
< num_vals
;) {
3263 unsigned num_tmps
= 0;
3264 unsigned tmp_size
= 0;
3265 RegType reg_type
= RegType::sgpr
;
3266 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3267 if (vals
[i
].type() == RegType::vgpr
)
3268 reg_type
= RegType::vgpr
;
3269 tmp_size
+= vals
[i
].bytes();
3270 tmp
[num_tmps
++] = vals
[i
++];
3273 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3274 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3275 for (unsigned i
= 0; i
< num_vals
; i
++)
3276 vec
->operands
[i
] = Operand(tmp
[i
]);
3277 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3278 vec
->definitions
[0] = Definition(tmp
[0]);
3279 bld
.insert(std::move(vec
));
3282 if (tmp
[0].bytes() % component_size
) {
3284 assert(i
== num_vals
);
3285 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3286 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3289 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3291 unsigned start
= components_split
;
3293 if (tmp_size
== elem_rc
.bytes()) {
3294 allocated_vec
[components_split
++] = tmp
[0];
3296 assert(tmp_size
% elem_rc
.bytes() == 0);
3297 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3298 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3299 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3300 Temp component
= bld
.tmp(elem_rc
);
3301 allocated_vec
[components_split
++] = component
;
3302 split
->definitions
[i
] = Definition(component
);
3304 split
->operands
[0] = Operand(tmp
[0]);
3305 bld
.insert(std::move(split
));
3308 /* try to p_as_uniform early so we can create more optimizable code and
3309 * also update allocated_vec */
3310 for (unsigned j
= start
; j
< components_split
; j
++) {
3311 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3312 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3313 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3317 /* concatenate components and p_as_uniform() result if needed */
3318 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3319 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3321 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3323 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3324 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3325 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3326 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3328 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3329 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3330 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3331 vec
->definitions
[0] = Definition(tmp
);
3332 bld
.insert(std::move(vec
));
3333 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3335 vec
->definitions
[0] = Definition(info
->dst
);
3336 bld
.insert(std::move(vec
));
3340 Operand
load_lds_size_m0(Builder
& bld
)
3342 /* TODO: m0 does not need to be initialized on GFX9+ */
3343 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3346 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3347 Temp offset
, unsigned bytes_needed
,
3348 unsigned align
, unsigned const_offset
,
3351 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3353 Operand m
= load_lds_size_m0(bld
);
3355 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3356 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3361 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3362 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3364 op
= aco_opcode::ds_read_b128
;
3365 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3368 op
= aco_opcode::ds_read2_b64
;
3369 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3371 op
= aco_opcode::ds_read_b96
;
3372 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3374 op
= aco_opcode::ds_read_b64
;
3375 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3378 op
= aco_opcode::ds_read2_b32
;
3379 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3381 op
= aco_opcode::ds_read_b32
;
3382 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3384 op
= aco_opcode::ds_read_u16
;
3387 op
= aco_opcode::ds_read_u8
;
3390 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3391 if (const_offset
>= max_offset_plus_one
) {
3392 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3393 const_offset
%= max_offset_plus_one
;
3397 const_offset
/= (size
/ 2u);
3399 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3400 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3402 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3404 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3407 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3412 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3414 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3415 Temp offset
, unsigned bytes_needed
,
3416 unsigned align
, unsigned const_offset
,
3421 if (bytes_needed
<= 4) {
3423 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3424 } else if (bytes_needed
<= 8) {
3426 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3427 } else if (bytes_needed
<= 16) {
3429 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3430 } else if (bytes_needed
<= 32) {
3432 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3435 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3437 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3438 if (info
->resource
.id()) {
3439 load
->operands
[0] = Operand(info
->resource
);
3440 load
->operands
[1] = Operand(offset
);
3442 load
->operands
[0] = Operand(offset
);
3443 load
->operands
[1] = Operand(0u);
3445 RegClass
rc(RegType::sgpr
, size
);
3446 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3447 load
->definitions
[0] = Definition(val
);
3448 load
->glc
= info
->glc
;
3449 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3450 load
->barrier
= info
->barrier
;
3451 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3452 bld
.insert(std::move(load
));
3456 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3458 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3459 Temp offset
, unsigned bytes_needed
,
3460 unsigned align_
, unsigned const_offset
,
3463 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3464 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3466 if (info
->soffset
.id()) {
3467 if (soffset
.isTemp())
3468 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3469 soffset
= Operand(info
->soffset
);
3472 unsigned bytes_size
= 0;
3474 if (bytes_needed
== 1) {
3476 op
= aco_opcode::buffer_load_ubyte
;
3477 } else if (bytes_needed
== 2) {
3479 op
= aco_opcode::buffer_load_ushort
;
3480 } else if (bytes_needed
<= 4) {
3482 op
= aco_opcode::buffer_load_dword
;
3483 } else if (bytes_needed
<= 8) {
3485 op
= aco_opcode::buffer_load_dwordx2
;
3486 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3488 op
= aco_opcode::buffer_load_dwordx3
;
3491 op
= aco_opcode::buffer_load_dwordx4
;
3493 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3494 mubuf
->operands
[0] = Operand(info
->resource
);
3495 mubuf
->operands
[1] = vaddr
;
3496 mubuf
->operands
[2] = soffset
;
3497 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3498 mubuf
->glc
= info
->glc
;
3499 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3500 mubuf
->barrier
= info
->barrier
;
3501 mubuf
->can_reorder
= info
->can_reorder
;
3502 mubuf
->offset
= const_offset
;
3503 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3504 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3505 mubuf
->definitions
[0] = Definition(val
);
3506 bld
.insert(std::move(mubuf
));
3509 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3514 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3516 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3518 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3519 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3521 if (addr
.type() == RegType::vgpr
)
3522 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3523 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3526 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3527 Temp offset
, unsigned bytes_needed
,
3528 unsigned align_
, unsigned const_offset
,
3531 unsigned bytes_size
= 0;
3532 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3533 bool global
= bld
.program
->chip_class
>= GFX9
;
3535 if (bytes_needed
== 1) {
3537 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3538 } else if (bytes_needed
== 2) {
3540 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3541 } else if (bytes_needed
<= 4) {
3543 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3544 } else if (bytes_needed
<= 8) {
3546 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3547 } else if (bytes_needed
<= 12 && !mubuf
) {
3549 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3552 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3554 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3555 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3557 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3558 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3559 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3560 mubuf
->operands
[2] = Operand(0u);
3561 mubuf
->glc
= info
->glc
;
3564 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3565 mubuf
->disable_wqm
= false;
3566 mubuf
->barrier
= info
->barrier
;
3567 mubuf
->definitions
[0] = Definition(val
);
3568 bld
.insert(std::move(mubuf
));
3570 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3572 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3573 flat
->operands
[0] = Operand(offset
);
3574 flat
->operands
[1] = Operand(s1
);
3575 flat
->glc
= info
->glc
;
3576 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3577 flat
->barrier
= info
->barrier
;
3579 flat
->definitions
[0] = Definition(val
);
3580 bld
.insert(std::move(flat
));
3584 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3589 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3591 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3592 Temp address
, unsigned base_offset
, unsigned align
)
3594 assert(util_is_power_of_two_nonzero(align
));
3596 Builder
bld(ctx
->program
, ctx
->block
);
3598 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3599 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3600 info
.align_mul
= align
;
3601 info
.align_offset
= 0;
3602 info
.barrier
= barrier_shared
;
3603 info
.can_reorder
= false;
3604 info
.const_offset
= base_offset
;
3605 emit_lds_load(ctx
, bld
, &info
);
3610 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3615 Builder
bld(ctx
->program
, ctx
->block
);
3617 ASSERTED
bool is_subdword
= false;
3618 for (unsigned i
= 0; i
< count
; i
++)
3619 is_subdword
|= offsets
[i
] % 4;
3620 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3621 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3623 /* count == 1 fast path */
3625 if (dst_type
== RegType::sgpr
)
3626 dst
[0] = bld
.as_uniform(src
);
3628 dst
[0] = as_vgpr(ctx
, src
);
3632 for (unsigned i
= 0; i
< count
- 1; i
++)
3633 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3634 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3636 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3637 src
= as_vgpr(ctx
, src
);
3639 /* use allocated_vec if possible */
3640 auto it
= ctx
->allocated_vec
.find(src
.id());
3641 if (it
!= ctx
->allocated_vec
.end()) {
3642 unsigned total_size
= 0;
3643 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3644 total_size
+= it
->second
[i
].bytes();
3645 if (total_size
!= src
.bytes())
3648 unsigned elem_size
= it
->second
[0].bytes();
3650 for (unsigned i
= 0; i
< count
; i
++) {
3651 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3655 for (unsigned i
= 0; i
< count
; i
++) {
3656 unsigned start_idx
= offsets
[i
] / elem_size
;
3657 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3658 if (op_count
== 1) {
3659 if (dst_type
== RegType::sgpr
)
3660 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3662 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3666 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3667 for (unsigned j
= 0; j
< op_count
; j
++) {
3668 Temp tmp
= it
->second
[start_idx
+ j
];
3669 if (dst_type
== RegType::sgpr
)
3670 tmp
= bld
.as_uniform(tmp
);
3671 vec
->operands
[j
] = Operand(tmp
);
3673 vec
->definitions
[0] = Definition(dst
[i
]);
3674 bld
.insert(std::move(vec
));
3680 if (dst_type
== RegType::sgpr
)
3681 src
= bld
.as_uniform(src
);
3685 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3686 split
->operands
[0] = Operand(src
);
3687 for (unsigned i
= 0; i
< count
; i
++)
3688 split
->definitions
[i
] = Definition(dst
[i
]);
3689 bld
.insert(std::move(split
));
3692 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3693 int *start
, int *count
)
3695 unsigned start_elem
= ffs(todo_mask
) - 1;
3696 bool skip
= !(mask
& (1 << start_elem
));
3698 mask
= ~mask
& todo_mask
;
3702 u_bit_scan_consecutive_range(&mask
, start
, count
);
3707 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3709 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3712 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3713 Temp address
, unsigned base_offset
, unsigned align
)
3715 assert(util_is_power_of_two_nonzero(align
));
3716 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3718 Builder
bld(ctx
->program
, ctx
->block
);
3719 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3720 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3722 unsigned write_count
= 0;
3723 Temp write_datas
[32];
3724 unsigned offsets
[32];
3725 aco_opcode opcodes
[32];
3727 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3729 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3732 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3733 offsets
[write_count
] = offset
;
3734 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3736 advance_write_mask(&todo
, offset
, bytes
);
3740 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3741 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3742 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3743 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3745 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3746 aco_opcode op
= aco_opcode::num_opcodes
;
3747 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3748 op
= aco_opcode::ds_write_b128
;
3750 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3751 op
= aco_opcode::ds_write_b96
;
3753 } else if (bytes
>= 8 && aligned8
) {
3754 op
= aco_opcode::ds_write_b64
;
3756 } else if (bytes
>= 4 && aligned4
) {
3757 op
= aco_opcode::ds_write_b32
;
3759 } else if (bytes
>= 2 && aligned2
) {
3760 op
= aco_opcode::ds_write_b16
;
3762 } else if (bytes
>= 1) {
3763 op
= aco_opcode::ds_write_b8
;
3769 offsets
[write_count
] = offset
;
3770 opcodes
[write_count
] = op
;
3772 advance_write_mask(&todo
, offset
, bytes
);
3775 Operand m
= load_lds_size_m0(bld
);
3777 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3779 for (unsigned i
= 0; i
< write_count
; i
++) {
3780 aco_opcode op
= opcodes
[i
];
3781 if (op
== aco_opcode::num_opcodes
)
3784 Temp data
= write_datas
[i
];
3786 unsigned second
= write_count
;
3787 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3788 for (second
= i
+ 1; second
< write_count
; second
++) {
3789 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3790 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3791 opcodes
[second
] = aco_opcode::num_opcodes
;
3797 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3798 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3800 unsigned inline_offset
= base_offset
+ offsets
[i
];
3801 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3802 Temp address_offset
= address
;
3803 if (inline_offset
> max_offset
) {
3804 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3805 inline_offset
= offsets
[i
];
3807 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3810 Temp second_data
= write_datas
[second
];
3811 inline_offset
/= data
.bytes();
3812 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3814 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3819 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3821 unsigned align
= 16;
3823 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3829 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3834 return aco_opcode::buffer_store_byte
;
3837 return aco_opcode::buffer_store_short
;
3839 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3841 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3844 return aco_opcode::buffer_store_dwordx3
;
3846 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3848 unreachable("Unexpected store size");
3849 return aco_opcode::num_opcodes
;
3852 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3853 Temp data
, unsigned writemask
, int swizzle_element_size
,
3854 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3856 unsigned write_count_with_skips
= 0;
3859 /* determine how to split the data */
3860 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3863 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3864 offsets
[write_count_with_skips
] = offset
;
3865 if (skips
[write_count_with_skips
]) {
3866 advance_write_mask(&todo
, offset
, bytes
);
3867 write_count_with_skips
++;
3871 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3872 * larger than swizzle_element_size */
3873 bytes
= MIN2(bytes
, swizzle_element_size
);
3875 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3877 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3878 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3881 /* dword or larger stores have to be dword-aligned */
3882 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3883 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3884 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3885 if (bytes
>= 4 && !dword_aligned
)
3886 bytes
= MIN2(bytes
, 2);
3888 advance_write_mask(&todo
, offset
, bytes
);
3889 write_count_with_skips
++;
3892 /* actually split data */
3893 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3896 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3899 write_datas
[*write_count
] = write_datas
[i
];
3900 offsets
[*write_count
] = offsets
[i
];
3905 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3906 unsigned split_cnt
= 0u, Temp dst
= Temp())
3908 Builder
bld(ctx
->program
, ctx
->block
);
3909 unsigned dword_size
= elem_size_bytes
/ 4;
3912 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3914 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3915 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3916 instr
->definitions
[0] = Definition(dst
);
3918 for (unsigned i
= 0; i
< cnt
; ++i
) {
3920 assert(arr
[i
].size() == dword_size
);
3921 allocated_vec
[i
] = arr
[i
];
3922 instr
->operands
[i
] = Operand(arr
[i
]);
3924 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3925 allocated_vec
[i
] = zero
;
3926 instr
->operands
[i
] = Operand(zero
);
3930 bld
.insert(std::move(instr
));
3933 emit_split_vector(ctx
, dst
, split_cnt
);
3935 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3940 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3942 if (const_offset
>= 4096) {
3943 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3944 const_offset
%= 4096u;
3947 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3948 else if (unlikely(voffset
.regClass() == s1
))
3949 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3950 else if (likely(voffset
.regClass() == v1
))
3951 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3953 unreachable("Unsupported register class of voffset");
3956 return const_offset
;
3959 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3960 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3963 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3964 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3966 Builder
bld(ctx
->program
, ctx
->block
);
3967 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3968 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3970 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3971 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3972 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3973 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3974 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3976 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3979 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3980 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3981 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3983 Builder
bld(ctx
->program
, ctx
->block
);
3984 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3986 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3988 unsigned write_count
= 0;
3989 Temp write_datas
[32];
3990 unsigned offsets
[32];
3991 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3992 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3994 for (unsigned i
= 0; i
< write_count
; i
++) {
3995 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3996 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
4000 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4001 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4002 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4004 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
4005 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
4006 assert(!!stride
!= allow_combining
);
4008 Builder
bld(ctx
->program
, ctx
->block
);
4010 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4011 info
.component_stride
= allow_combining
? 0 : stride
;
4013 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4014 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4015 info
.align_offset
= 0;
4016 info
.soffset
= soffset
;
4017 info
.const_offset
= base_const_offset
;
4018 emit_mubuf_load(ctx
, bld
, &info
);
4021 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4023 Builder
bld(ctx
->program
, ctx
->block
);
4024 Temp offset
= base_offset
.first
;
4025 unsigned const_offset
= base_offset
.second
;
4027 if (!nir_src_is_const(*off_src
)) {
4028 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4031 /* Calculate indirect offset with stride */
4032 if (likely(indirect_offset_arg
.regClass() == v1
))
4033 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4034 else if (indirect_offset_arg
.regClass() == s1
)
4035 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4037 unreachable("Unsupported register class of indirect offset");
4039 /* Add to the supplied base offset */
4040 if (offset
.id() == 0)
4041 offset
= with_stride
;
4042 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4043 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4044 else if (offset
.size() == 1 && with_stride
.size() == 1)
4045 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4047 unreachable("Unsupported register class of indirect offset");
4049 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4050 const_offset
+= const_offset_arg
* stride
;
4053 return std::make_pair(offset
, const_offset
);
4056 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4058 Builder
bld(ctx
->program
, ctx
->block
);
4061 if (off1
.first
.id() && off2
.first
.id()) {
4062 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4063 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4064 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4065 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4067 unreachable("Unsupported register class of indirect offset");
4069 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4072 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4075 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4077 Builder
bld(ctx
->program
, ctx
->block
);
4078 unsigned const_offset
= offs
.second
* multiplier
;
4080 if (!offs
.first
.id())
4081 return std::make_pair(offs
.first
, const_offset
);
4083 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4084 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4085 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4087 return std::make_pair(offset
, const_offset
);
4090 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4092 Builder
bld(ctx
->program
, ctx
->block
);
4094 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4095 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4096 /* component is in bytes */
4097 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4099 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4100 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4101 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4104 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4106 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4109 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4111 Builder
bld(ctx
->program
, ctx
->block
);
4113 switch (ctx
->shader
->info
.stage
) {
4114 case MESA_SHADER_TESS_CTRL
:
4115 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4116 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4117 case MESA_SHADER_TESS_EVAL
:
4118 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4120 unreachable("Unsupported stage in get_tess_rel_patch_id");
4124 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4126 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4127 Builder
bld(ctx
->program
, ctx
->block
);
4129 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4130 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4132 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4134 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4135 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4137 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4138 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4139 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4141 return offset_mul(ctx
, offs
, 4u);
4144 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4146 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4147 Builder
bld(ctx
->program
, ctx
->block
);
4149 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4150 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
4151 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
4152 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
4153 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4154 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
4156 std::pair
<Temp
, unsigned> offs
= instr
4157 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4158 : std::make_pair(Temp(), 0u);
4160 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4161 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4166 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4167 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4169 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4170 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4172 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4173 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4179 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4181 Builder
bld(ctx
->program
, ctx
->block
);
4183 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4184 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4186 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4188 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4189 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4190 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4192 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4193 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4198 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4200 Builder
bld(ctx
->program
, ctx
->block
);
4202 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
4203 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
4204 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
4206 unsigned output_vertex_size
= num_tcs_outputs
* 16;
4207 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4208 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4209 unsigned attr_stride
= ctx
->tcs_num_patches
;
4211 std::pair
<Temp
, unsigned> offs
= instr
4212 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4213 : std::make_pair(Temp(), 0u);
4215 if (const_base_offset
)
4216 offs
.second
+= const_base_offset
* attr_stride
;
4218 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4219 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4220 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4225 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4230 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4231 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4233 if (!nir_src_is_const(*off_src
)) {
4239 off
+= nir_src_as_uint(*off_src
) * 16u;
4242 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
4243 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
4250 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4252 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4253 unsigned component
= nir_intrinsic_component(instr
);
4254 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4256 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4257 if (off_instr
->type
!= nir_instr_type_load_const
)
4260 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4261 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4263 if (instr
->src
[0].ssa
->bit_size
== 64)
4264 write_mask
= widen_mask(write_mask
, 2);
4266 for (unsigned i
= 0; i
< 8; ++i
) {
4267 if (write_mask
& (1 << i
)) {
4268 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4269 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
4277 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4279 /* Only TCS per-vertex inputs are supported by this function.
4280 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4282 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4285 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4286 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4287 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4288 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4289 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4290 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4295 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4296 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4297 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4302 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4304 Builder
bld(ctx
->program
, ctx
->block
);
4306 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4307 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4308 bool indirect_write
;
4309 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4310 if (temp_only_input
&& !indirect_write
)
4314 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4315 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4316 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4317 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4319 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4320 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4321 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4322 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4323 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4327 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4328 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4329 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4330 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4331 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4332 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4333 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4334 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4335 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4336 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4337 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4338 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4339 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4341 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
4342 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4343 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
4345 unreachable("Invalid LS or ES stage");
4348 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4349 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4350 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4354 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4359 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4360 return off
== ctx
->tcs_tess_lvl_out_loc
||
4361 off
== ctx
->tcs_tess_lvl_in_loc
;
4365 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4367 uint64_t mask
= per_vertex
4368 ? ctx
->program
->info
->tcs
.tes_inputs_read
4369 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4371 bool indirect_write
= false;
4372 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4373 return indirect_write
|| output_read_by_tes
;
4376 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4378 uint64_t mask
= per_vertex
4379 ? ctx
->shader
->info
.outputs_read
4380 : ctx
->shader
->info
.patch_outputs_read
;
4382 bool indirect_write
= false;
4383 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4384 return indirect_write
|| output_read
;
4387 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4389 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4390 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4392 Builder
bld(ctx
->program
, ctx
->block
);
4394 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4395 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4396 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4398 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4399 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4400 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4402 if (write_to_vmem
) {
4403 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4404 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4405 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4407 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4408 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4409 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4413 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4414 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4415 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4419 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4421 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4422 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4424 Builder
bld(ctx
->program
, ctx
->block
);
4426 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4427 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4428 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4429 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4431 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4434 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4436 if (ctx
->stage
== vertex_vs
||
4437 ctx
->stage
== tess_eval_vs
||
4438 ctx
->stage
== fragment_fs
||
4439 ctx
->stage
== ngg_vertex_gs
||
4440 ctx
->stage
== ngg_tess_eval_gs
||
4441 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4442 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4443 if (!stored_to_temps
) {
4444 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4445 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4446 fprintf(stderr
, "\n");
4449 } else if (ctx
->stage
== vertex_es
||
4450 ctx
->stage
== vertex_ls
||
4451 ctx
->stage
== tess_eval_es
||
4452 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4453 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4454 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4455 visit_store_ls_or_es_output(ctx
, instr
);
4456 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4457 visit_store_tcs_output(ctx
, instr
, false);
4459 unreachable("Shader stage not implemented");
4463 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4465 visit_load_tcs_output(ctx
, instr
, false);
4468 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4470 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4471 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4473 Builder
bld(ctx
->program
, ctx
->block
);
4474 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4475 if (ctx
->program
->has_16bank_lds
)
4476 interp_p1
.instr
->operands
[0].setLateKill(true);
4477 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4480 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4482 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4483 for (unsigned i
= 0; i
< num_components
; i
++)
4484 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4485 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4486 assert(num_components
== 4);
4487 Builder
bld(ctx
->program
, ctx
->block
);
4488 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4491 for (Operand
& op
: vec
->operands
)
4492 op
= op
.isUndefined() ? Operand(0u) : op
;
4494 vec
->definitions
[0] = Definition(dst
);
4495 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4496 emit_split_vector(ctx
, dst
, num_components
);
4500 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4502 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4503 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4504 unsigned idx
= nir_intrinsic_base(instr
);
4505 unsigned component
= nir_intrinsic_component(instr
);
4506 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4508 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4510 assert(offset
->u32
== 0);
4512 /* the lower 15bit of the prim_mask contain the offset into LDS
4513 * while the upper bits contain the number of prims */
4514 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4515 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4516 Builder
bld(ctx
->program
, ctx
->block
);
4517 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4518 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4519 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4520 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4521 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4524 if (instr
->dest
.ssa
.num_components
== 1) {
4525 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4527 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4528 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4530 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4531 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4532 vec
->operands
[i
] = Operand(tmp
);
4534 vec
->definitions
[0] = Definition(dst
);
4535 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4539 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4540 unsigned offset
, unsigned stride
, unsigned channels
)
4542 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4543 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4545 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4546 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4549 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4550 unsigned offset
, unsigned stride
, unsigned *channels
)
4552 if (!vtx_info
->chan_byte_size
) {
4553 *channels
= vtx_info
->num_channels
;
4554 return vtx_info
->chan_format
;
4557 unsigned num_channels
= *channels
;
4558 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4559 unsigned new_channels
= num_channels
+ 1;
4560 /* first, assume more loads is worse and try using a larger data format */
4561 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4563 /* don't make the attribute potentially out-of-bounds */
4564 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4568 if (new_channels
== 5) {
4569 /* then try decreasing load size (at the cost of more loads) */
4570 new_channels
= *channels
;
4571 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4575 if (new_channels
< *channels
)
4576 *channels
= new_channels
;
4577 num_channels
= new_channels
;
4580 switch (vtx_info
->chan_format
) {
4581 case V_008F0C_BUF_DATA_FORMAT_8
:
4582 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4583 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4584 case V_008F0C_BUF_DATA_FORMAT_16
:
4585 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4586 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4587 case V_008F0C_BUF_DATA_FORMAT_32
:
4588 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4589 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4591 unreachable("shouldn't reach here");
4592 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4595 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4596 * so we may need to fix it up. */
4597 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4599 Builder
bld(ctx
->program
, ctx
->block
);
4601 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4602 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4604 /* For the integer-like cases, do a natural sign extension.
4606 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4607 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4610 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4611 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4613 /* Convert back to the right type. */
4614 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4615 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4616 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4617 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4618 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4619 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4625 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4627 Builder
bld(ctx
->program
, ctx
->block
);
4628 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4629 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4631 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4632 if (off_instr
->type
!= nir_instr_type_load_const
) {
4633 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4634 nir_print_instr(off_instr
, stderr
);
4635 fprintf(stderr
, "\n");
4637 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4639 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4641 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4642 unsigned component
= nir_intrinsic_component(instr
);
4643 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4644 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4645 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4646 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4648 unsigned dfmt
= attrib_format
& 0xf;
4649 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4650 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4652 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4653 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4654 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4655 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4657 num_channels
= MAX2(num_channels
, 3);
4659 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4660 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4663 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4664 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4665 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4667 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4669 Temp divided
= bld
.tmp(v1
);
4670 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4671 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4673 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4676 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4679 index
= bld
.vadd32(bld
.def(v1
),
4680 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4681 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4684 Temp channels
[num_channels
];
4685 unsigned channel_start
= 0;
4686 bool direct_fetch
= false;
4688 /* skip unused channels at the start */
4689 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4690 channel_start
= ffs(mask
) - 1;
4691 for (unsigned i
= 0; i
< channel_start
; i
++)
4692 channels
[i
] = Temp(0, s1
);
4693 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4694 num_channels
= 3 - (ffs(mask
) - 1);
4698 while (channel_start
< num_channels
) {
4699 unsigned fetch_size
= num_channels
- channel_start
;
4700 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4701 bool expanded
= false;
4703 /* use MUBUF when possible to avoid possible alignment issues */
4704 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4705 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4706 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4707 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4708 vtx_info
->chan_byte_size
== 4;
4709 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4711 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4713 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4714 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4720 Temp fetch_index
= index
;
4721 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4722 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4723 fetch_offset
= fetch_offset
% attrib_stride
;
4726 Operand
soffset(0u);
4727 if (fetch_offset
>= 4096) {
4728 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4729 fetch_offset
%= 4096;
4733 switch (fetch_size
) {
4735 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4738 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4741 assert(ctx
->options
->chip_class
>= GFX7
||
4742 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4743 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4746 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4749 unreachable("Unimplemented load_input vector size");
4753 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4754 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4755 num_channels
<= 3)) {
4756 direct_fetch
= true;
4759 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4763 Instruction
*mubuf
= bld
.mubuf(opcode
,
4764 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4765 fetch_offset
, false, true).instr
;
4766 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4768 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4769 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4770 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4771 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4774 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4776 if (fetch_size
== 1) {
4777 channels
[channel_start
] = fetch_dst
;
4779 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4780 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4783 channel_start
+= fetch_size
;
4786 if (!direct_fetch
) {
4787 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4788 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4790 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4791 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4792 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4794 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4795 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4796 unsigned num_temp
= 0;
4797 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4798 unsigned idx
= i
+ component
;
4799 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4800 Temp channel
= channels
[swizzle
[idx
]];
4801 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4802 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4803 vec
->operands
[i
] = Operand(channel
);
4807 } else if (is_float
&& idx
== 3) {
4808 vec
->operands
[i
] = Operand(0x3f800000u
);
4809 } else if (!is_float
&& idx
== 3) {
4810 vec
->operands
[i
] = Operand(1u);
4812 vec
->operands
[i
] = Operand(0u);
4815 vec
->definitions
[0] = Definition(dst
);
4816 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4817 emit_split_vector(ctx
, dst
, dst
.size());
4819 if (num_temp
== dst
.size())
4820 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4822 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4823 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4824 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4825 if (off_instr
->type
!= nir_instr_type_load_const
||
4826 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4827 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4828 nir_print_instr(off_instr
, stderr
);
4829 fprintf(stderr
, "\n");
4832 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4833 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4835 assert(offset
->u32
== 0);
4837 /* the lower 15bit of the prim_mask contain the offset into LDS
4838 * while the upper bits contain the number of prims */
4839 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4840 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4841 Builder
bld(ctx
->program
, ctx
->block
);
4842 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4843 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4844 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4845 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4846 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4849 unsigned idx
= nir_intrinsic_base(instr
);
4850 unsigned component
= nir_intrinsic_component(instr
);
4851 unsigned vertex_id
= 2; /* P0 */
4853 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4854 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4855 switch (src0
->u32
) {
4857 vertex_id
= 2; /* P0 */
4860 vertex_id
= 0; /* P10 */
4863 vertex_id
= 1; /* P20 */
4866 unreachable("invalid vertex index");
4870 if (dst
.size() == 1) {
4871 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4873 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4874 for (unsigned i
= 0; i
< dst
.size(); i
++)
4875 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4876 vec
->definitions
[0] = Definition(dst
);
4877 bld
.insert(std::move(vec
));
4880 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4881 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4882 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4883 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4884 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4886 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4888 unreachable("Shader stage not implemented");
4892 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4894 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4896 Builder
bld(ctx
->program
, ctx
->block
);
4897 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4900 if (!nir_src_is_const(*vertex_src
)) {
4901 /* better code could be created, but this case probably doesn't happen
4902 * much in practice */
4903 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4904 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4907 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4908 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4910 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4912 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4915 if (vertex_offset
.id()) {
4916 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4917 Operand(i
), indirect_vertex
);
4918 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4920 vertex_offset
= elem
;
4924 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4925 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4927 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4928 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4929 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4930 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4931 Operand((vertex
% 2u) * 16u), Operand(16u));
4933 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4936 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4937 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4938 return offset_mul(ctx
, offs
, 4u);
4941 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4943 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4945 Builder
bld(ctx
->program
, ctx
->block
);
4946 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4947 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4949 if (ctx
->stage
== geometry_gs
) {
4950 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4951 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4952 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4953 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4954 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4955 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4956 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4958 unreachable("Unsupported GS stage.");
4962 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4964 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4966 Builder
bld(ctx
->program
, ctx
->block
);
4967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4969 if (load_input_from_temps(ctx
, instr
, dst
))
4972 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4973 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4974 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4976 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4979 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4981 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4983 Builder
bld(ctx
->program
, ctx
->block
);
4985 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4986 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4987 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4989 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4990 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4992 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4995 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4997 switch (ctx
->shader
->info
.stage
) {
4998 case MESA_SHADER_GEOMETRY
:
4999 visit_load_gs_per_vertex_input(ctx
, instr
);
5001 case MESA_SHADER_TESS_CTRL
:
5002 visit_load_tcs_per_vertex_input(ctx
, instr
);
5004 case MESA_SHADER_TESS_EVAL
:
5005 visit_load_tes_per_vertex_input(ctx
, instr
);
5008 unreachable("Unimplemented shader stage");
5012 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5014 visit_load_tcs_output(ctx
, instr
, true);
5017 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5019 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5020 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5022 visit_store_tcs_output(ctx
, instr
, true);
5025 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5027 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5029 Builder
bld(ctx
->program
, ctx
->block
);
5030 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5032 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5033 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5036 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5037 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5038 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5039 tes_w
= Operand(tmp
);
5042 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5043 emit_split_vector(ctx
, tess_coord
, 3);
5046 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5048 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5049 Builder
bld(ctx
->program
, ctx
->block
);
5050 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5051 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5052 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5055 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5059 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5061 Builder
bld(ctx
->program
, ctx
->block
);
5062 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5063 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
5064 index
= bld
.as_uniform(index
);
5065 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5066 unsigned binding
= nir_intrinsic_binding(instr
);
5069 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5070 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5071 unsigned offset
= layout
->binding
[binding
].offset
;
5073 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5074 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5075 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5076 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5077 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5080 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5081 stride
= layout
->binding
[binding
].size
;
5084 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5085 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5087 if (nir_const_index
) {
5088 const_index
= const_index
* stride
;
5089 } else if (index
.type() == RegType::vgpr
) {
5090 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5091 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5093 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5097 if (nir_const_index
) {
5098 const_index
= const_index
+ offset
;
5099 } else if (index
.type() == RegType::vgpr
) {
5100 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5102 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5106 if (nir_const_index
&& const_index
== 0) {
5108 } else if (index
.type() == RegType::vgpr
) {
5109 index
= bld
.vadd32(bld
.def(v1
),
5110 nir_const_index
? Operand(const_index
) : Operand(index
),
5113 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5114 nir_const_index
? Operand(const_index
) : Operand(index
),
5118 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5121 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5122 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5123 bool glc
=false, bool readonly
=true)
5125 Builder
bld(ctx
->program
, ctx
->block
);
5127 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5129 offset
= bld
.as_uniform(offset
);
5131 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5133 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5134 info
.can_reorder
= readonly
;
5135 info
.align_mul
= align_mul
;
5136 info
.align_offset
= align_offset
;
5138 emit_smem_load(ctx
, bld
, &info
);
5140 emit_mubuf_load(ctx
, bld
, &info
);
5143 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5145 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5146 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5148 Builder
bld(ctx
->program
, ctx
->block
);
5150 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5151 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5152 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5153 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5155 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5156 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5157 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5158 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5159 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5160 if (ctx
->options
->chip_class
>= GFX10
) {
5161 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5162 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5163 S_008F0C_RESOURCE_LEVEL(1);
5165 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5166 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5168 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5169 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5170 Operand(0xFFFFFFFFu
),
5171 Operand(desc_type
));
5172 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5173 rsrc
, upper_dwords
);
5175 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5176 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5178 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5179 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5180 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5183 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5185 Builder
bld(ctx
->program
, ctx
->block
);
5186 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5187 unsigned offset
= nir_intrinsic_base(instr
);
5188 unsigned count
= instr
->dest
.ssa
.num_components
;
5189 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5191 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5192 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5193 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5194 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5195 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5196 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5197 for (unsigned i
= 0; i
< count
; ++i
) {
5198 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5199 vec
->operands
[i
] = Operand
{elems
[i
]};
5201 vec
->definitions
[0] = Definition(dst
);
5202 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5203 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5208 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5209 if (offset
!= 0) // TODO check if index != 0 as well
5210 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5211 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5214 bool aligned
= true;
5216 if (instr
->dest
.ssa
.bit_size
== 8) {
5217 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5218 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5220 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5221 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5222 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5224 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5229 switch (vec
.size()) {
5231 op
= aco_opcode::s_load_dword
;
5234 op
= aco_opcode::s_load_dwordx2
;
5240 op
= aco_opcode::s_load_dwordx4
;
5246 op
= aco_opcode::s_load_dwordx8
;
5249 unreachable("unimplemented or forbidden load_push_constant.");
5252 bld
.smem(op
, Definition(vec
), ptr
, index
);
5255 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5256 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5261 emit_split_vector(ctx
, vec
, 4);
5262 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5263 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5264 emit_extract_vector(ctx
, vec
, 0, rc
),
5265 emit_extract_vector(ctx
, vec
, 1, rc
),
5266 emit_extract_vector(ctx
, vec
, 2, rc
));
5269 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5272 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5274 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5276 Builder
bld(ctx
->program
, ctx
->block
);
5278 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5279 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5280 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5281 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5282 if (ctx
->options
->chip_class
>= GFX10
) {
5283 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5284 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5285 S_008F0C_RESOURCE_LEVEL(1);
5287 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5288 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5291 unsigned base
= nir_intrinsic_base(instr
);
5292 unsigned range
= nir_intrinsic_range(instr
);
5294 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5295 if (base
&& offset
.type() == RegType::sgpr
)
5296 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5297 else if (base
&& offset
.type() == RegType::vgpr
)
5298 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5300 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5301 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5302 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5303 Operand(desc_type
));
5304 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5305 // TODO: get alignment information for subdword constants
5306 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5309 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5311 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5312 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5314 ctx
->program
->needs_exact
= true;
5316 // TODO: optimize uniform conditions
5317 Builder
bld(ctx
->program
, ctx
->block
);
5318 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5319 assert(src
.regClass() == bld
.lm
);
5320 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5321 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5322 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5326 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5328 Builder
bld(ctx
->program
, ctx
->block
);
5330 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5331 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5333 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5334 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5336 if (ctx
->block
->loop_nest_depth
&&
5337 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5338 /* we handle discards the same way as jump instructions */
5339 append_logical_end(ctx
->block
);
5341 /* in loops, discard behaves like break */
5342 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5343 ctx
->block
->kind
|= block_kind_discard
;
5346 /* uniform discard - loop ends here */
5347 assert(nir_instr_is_last(&instr
->instr
));
5348 ctx
->block
->kind
|= block_kind_uniform
;
5349 ctx
->cf_info
.has_branch
= true;
5350 bld
.branch(aco_opcode::p_branch
);
5351 add_linear_edge(ctx
->block
->index
, linear_target
);
5355 /* we add a break right behind the discard() instructions */
5356 ctx
->block
->kind
|= block_kind_break
;
5357 unsigned idx
= ctx
->block
->index
;
5359 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5360 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5362 /* remove critical edges from linear CFG */
5363 bld
.branch(aco_opcode::p_branch
);
5364 Block
* break_block
= ctx
->program
->create_and_insert_block();
5365 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5366 break_block
->kind
|= block_kind_uniform
;
5367 add_linear_edge(idx
, break_block
);
5368 add_linear_edge(break_block
->index
, linear_target
);
5369 bld
.reset(break_block
);
5370 bld
.branch(aco_opcode::p_branch
);
5372 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5373 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5374 add_linear_edge(idx
, continue_block
);
5375 append_logical_start(continue_block
);
5376 ctx
->block
= continue_block
;
5381 /* it can currently happen that NIR doesn't remove the unreachable code */
5382 if (!nir_instr_is_last(&instr
->instr
)) {
5383 ctx
->program
->needs_exact
= true;
5384 /* save exec somewhere temporarily so that it doesn't get
5385 * overwritten before the discard from outer exec masks */
5386 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5387 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5388 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5392 /* This condition is incorrect for uniformly branched discards in a loop
5393 * predicated by a divergent condition, but the above code catches that case
5394 * and the discard would end up turning into a discard_if.
5404 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5405 /* program just ends here */
5406 ctx
->block
->kind
|= block_kind_uniform
;
5407 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5408 0 /* enabled mask */, 9 /* dest */,
5409 false /* compressed */, true/* done */, true /* valid mask */);
5410 bld
.sopp(aco_opcode::s_endpgm
);
5411 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5413 ctx
->block
->kind
|= block_kind_discard
;
5414 /* branch and linear edge is added by visit_if() */
5418 enum aco_descriptor_type
{
5429 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5430 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5432 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5433 return dim
== ac_image_cube
||
5434 dim
== ac_image_1darray
||
5435 dim
== ac_image_2darray
||
5436 dim
== ac_image_2darraymsaa
;
5439 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5440 enum aco_descriptor_type desc_type
,
5441 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5443 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5444 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5445 if (it != ctx->tex_desc.end())
5448 Temp index
= Temp();
5449 bool index_set
= false;
5450 unsigned constant_index
= 0;
5451 unsigned descriptor_set
;
5452 unsigned base_index
;
5453 Builder
bld(ctx
->program
, ctx
->block
);
5456 assert(tex_instr
&& !image
);
5458 base_index
= tex_instr
->sampler_index
;
5460 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5461 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5465 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5466 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5468 constant_index
+= array_size
* const_value
->u32
;
5470 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5471 if (indirect
.type() == RegType::vgpr
)
5472 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5474 if (array_size
!= 1)
5475 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5481 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5485 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5487 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5488 base_index
= deref_instr
->var
->data
.binding
;
5491 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5492 list
= convert_pointer_to_64_bit(ctx
, list
);
5494 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5495 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5496 unsigned offset
= binding
->offset
;
5497 unsigned stride
= binding
->size
;
5501 assert(base_index
< layout
->binding_count
);
5503 switch (desc_type
) {
5504 case ACO_DESC_IMAGE
:
5506 opcode
= aco_opcode::s_load_dwordx8
;
5508 case ACO_DESC_FMASK
:
5510 opcode
= aco_opcode::s_load_dwordx8
;
5513 case ACO_DESC_SAMPLER
:
5515 opcode
= aco_opcode::s_load_dwordx4
;
5516 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5517 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5519 case ACO_DESC_BUFFER
:
5521 opcode
= aco_opcode::s_load_dwordx4
;
5523 case ACO_DESC_PLANE_0
:
5524 case ACO_DESC_PLANE_1
:
5526 opcode
= aco_opcode::s_load_dwordx8
;
5527 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5529 case ACO_DESC_PLANE_2
:
5531 opcode
= aco_opcode::s_load_dwordx4
;
5535 unreachable("invalid desc_type\n");
5538 offset
+= constant_index
* stride
;
5540 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5541 (!index_set
|| binding
->immutable_samplers_equal
)) {
5542 if (binding
->immutable_samplers_equal
)
5545 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5546 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5547 Operand(samplers
[constant_index
* 4 + 0]),
5548 Operand(samplers
[constant_index
* 4 + 1]),
5549 Operand(samplers
[constant_index
* 4 + 2]),
5550 Operand(samplers
[constant_index
* 4 + 3]));
5555 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5557 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5558 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5561 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5563 if (desc_type
== ACO_DESC_PLANE_2
) {
5565 for (unsigned i
= 0; i
< 8; i
++)
5566 components
[i
] = bld
.tmp(s1
);
5567 bld
.pseudo(aco_opcode::p_split_vector
,
5568 Definition(components
[0]),
5569 Definition(components
[1]),
5570 Definition(components
[2]),
5571 Definition(components
[3]),
5574 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5575 bld
.pseudo(aco_opcode::p_split_vector
,
5576 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5577 Definition(components
[4]),
5578 Definition(components
[5]),
5579 Definition(components
[6]),
5580 Definition(components
[7]),
5583 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5584 components
[0], components
[1], components
[2], components
[3],
5585 components
[4], components
[5], components
[6], components
[7]);
5591 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5594 case GLSL_SAMPLER_DIM_BUF
:
5596 case GLSL_SAMPLER_DIM_1D
:
5597 return array
? 2 : 1;
5598 case GLSL_SAMPLER_DIM_2D
:
5599 return array
? 3 : 2;
5600 case GLSL_SAMPLER_DIM_MS
:
5601 return array
? 4 : 3;
5602 case GLSL_SAMPLER_DIM_3D
:
5603 case GLSL_SAMPLER_DIM_CUBE
:
5605 case GLSL_SAMPLER_DIM_RECT
:
5606 case GLSL_SAMPLER_DIM_SUBPASS
:
5608 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5617 /* Adjust the sample index according to FMASK.
5619 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5620 * which is the identity mapping. Each nibble says which physical sample
5621 * should be fetched to get that sample.
5623 * For example, 0x11111100 means there are only 2 samples stored and
5624 * the second sample covers 3/4 of the pixel. When reading samples 0
5625 * and 1, return physical sample 0 (determined by the first two 0s
5626 * in FMASK), otherwise return physical sample 1.
5628 * The sample index should be adjusted as follows:
5629 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5631 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5633 Builder
bld(ctx
->program
, ctx
->block
);
5634 Temp fmask
= bld
.tmp(v1
);
5635 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5636 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5639 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5640 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5641 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5642 load
->operands
[0] = Operand(fmask_desc_ptr
);
5643 load
->operands
[1] = Operand(s4
); /* no sampler */
5644 load
->operands
[2] = Operand(coord
);
5645 load
->definitions
[0] = Definition(fmask
);
5652 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5653 ctx
->block
->instructions
.emplace_back(std::move(load
));
5655 Operand sample_index4
;
5656 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5657 sample_index4
= Operand(sample_index
.constantValue() << 2);
5658 } else if (sample_index
.regClass() == s1
) {
5659 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5661 assert(sample_index
.regClass() == v1
);
5662 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5666 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5667 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5668 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5669 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5671 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5673 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5674 * resource descriptor is 0 (invalid),
5676 Temp compare
= bld
.tmp(bld
.lm
);
5677 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5678 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5680 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5682 /* Replace the MSAA sample index. */
5683 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5686 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5689 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5690 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5691 bool is_array
= glsl_sampler_type_is_array(type
);
5692 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5693 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5694 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5695 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5696 int count
= image_type_to_components_count(dim
, is_array
);
5697 std::vector
<Temp
> coords(count
);
5698 Builder
bld(ctx
->program
, ctx
->block
);
5702 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5703 /* get sample index */
5704 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5705 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5706 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5707 std::vector
<Temp
> fmask_load_address
;
5708 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5709 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5711 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5712 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5714 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5719 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5720 coords
.resize(coords
.size() + 1);
5721 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5723 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5725 for (int i
= 0; i
< count
; i
++)
5726 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5729 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5730 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5731 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5732 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5735 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5738 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5739 for (unsigned i
= 0; i
< coords
.size(); i
++)
5740 vec
->operands
[i
] = Operand(coords
[i
]);
5741 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5742 vec
->definitions
[0] = Definition(res
);
5743 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5748 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5750 Builder
bld(ctx
->program
, ctx
->block
);
5751 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5752 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5753 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5754 bool is_array
= glsl_sampler_type_is_array(type
);
5755 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5757 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5758 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5759 unsigned num_channels
= util_last_bit(mask
);
5760 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5761 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5764 switch (num_channels
) {
5766 opcode
= aco_opcode::buffer_load_format_x
;
5769 opcode
= aco_opcode::buffer_load_format_xy
;
5772 opcode
= aco_opcode::buffer_load_format_xyz
;
5775 opcode
= aco_opcode::buffer_load_format_xyzw
;
5778 unreachable(">4 channel buffer image load");
5780 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5781 load
->operands
[0] = Operand(rsrc
);
5782 load
->operands
[1] = Operand(vindex
);
5783 load
->operands
[2] = Operand((uint32_t) 0);
5785 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5788 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5789 load
->definitions
[0] = Definition(tmp
);
5791 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5792 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5793 load
->barrier
= barrier_image
;
5794 ctx
->block
->instructions
.emplace_back(std::move(load
));
5796 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5800 Temp coords
= get_image_coords(ctx
, instr
, type
);
5801 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5803 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5804 unsigned num_components
= util_bitcount(dmask
);
5806 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5809 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5811 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5812 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5814 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5815 load
->operands
[0] = Operand(resource
);
5816 load
->operands
[1] = Operand(s4
); /* no sampler */
5817 load
->operands
[2] = Operand(coords
);
5818 load
->definitions
[0] = Definition(tmp
);
5819 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5820 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5821 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5822 load
->dmask
= dmask
;
5824 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5825 load
->barrier
= barrier_image
;
5826 ctx
->block
->instructions
.emplace_back(std::move(load
));
5828 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5832 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5834 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5835 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5836 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5837 bool is_array
= glsl_sampler_type_is_array(type
);
5838 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5840 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5842 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5843 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5844 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5846 switch (data
.size()) {
5848 opcode
= aco_opcode::buffer_store_format_x
;
5851 opcode
= aco_opcode::buffer_store_format_xy
;
5854 opcode
= aco_opcode::buffer_store_format_xyz
;
5857 opcode
= aco_opcode::buffer_store_format_xyzw
;
5860 unreachable(">4 channel buffer image store");
5862 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5863 store
->operands
[0] = Operand(rsrc
);
5864 store
->operands
[1] = Operand(vindex
);
5865 store
->operands
[2] = Operand((uint32_t) 0);
5866 store
->operands
[3] = Operand(data
);
5867 store
->idxen
= true;
5870 store
->disable_wqm
= true;
5871 store
->barrier
= barrier_image
;
5872 ctx
->program
->needs_exact
= true;
5873 ctx
->block
->instructions
.emplace_back(std::move(store
));
5877 assert(data
.type() == RegType::vgpr
);
5878 Temp coords
= get_image_coords(ctx
, instr
, type
);
5879 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5881 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5882 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5884 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5885 store
->operands
[0] = Operand(resource
);
5886 store
->operands
[1] = Operand(data
);
5887 store
->operands
[2] = Operand(coords
);
5890 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5891 store
->dmask
= (1 << data
.size()) - 1;
5893 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5894 store
->disable_wqm
= true;
5895 store
->barrier
= barrier_image
;
5896 ctx
->program
->needs_exact
= true;
5897 ctx
->block
->instructions
.emplace_back(std::move(store
));
5901 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5903 /* return the previous value if dest is ever used */
5904 bool return_previous
= false;
5905 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5906 return_previous
= true;
5909 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5910 return_previous
= true;
5914 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5915 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5916 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5917 bool is_array
= glsl_sampler_type_is_array(type
);
5918 Builder
bld(ctx
->program
, ctx
->block
);
5920 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5921 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5923 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5924 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5926 aco_opcode buf_op
, image_op
;
5927 switch (instr
->intrinsic
) {
5928 case nir_intrinsic_image_deref_atomic_add
:
5929 buf_op
= aco_opcode::buffer_atomic_add
;
5930 image_op
= aco_opcode::image_atomic_add
;
5932 case nir_intrinsic_image_deref_atomic_umin
:
5933 buf_op
= aco_opcode::buffer_atomic_umin
;
5934 image_op
= aco_opcode::image_atomic_umin
;
5936 case nir_intrinsic_image_deref_atomic_imin
:
5937 buf_op
= aco_opcode::buffer_atomic_smin
;
5938 image_op
= aco_opcode::image_atomic_smin
;
5940 case nir_intrinsic_image_deref_atomic_umax
:
5941 buf_op
= aco_opcode::buffer_atomic_umax
;
5942 image_op
= aco_opcode::image_atomic_umax
;
5944 case nir_intrinsic_image_deref_atomic_imax
:
5945 buf_op
= aco_opcode::buffer_atomic_smax
;
5946 image_op
= aco_opcode::image_atomic_smax
;
5948 case nir_intrinsic_image_deref_atomic_and
:
5949 buf_op
= aco_opcode::buffer_atomic_and
;
5950 image_op
= aco_opcode::image_atomic_and
;
5952 case nir_intrinsic_image_deref_atomic_or
:
5953 buf_op
= aco_opcode::buffer_atomic_or
;
5954 image_op
= aco_opcode::image_atomic_or
;
5956 case nir_intrinsic_image_deref_atomic_xor
:
5957 buf_op
= aco_opcode::buffer_atomic_xor
;
5958 image_op
= aco_opcode::image_atomic_xor
;
5960 case nir_intrinsic_image_deref_atomic_exchange
:
5961 buf_op
= aco_opcode::buffer_atomic_swap
;
5962 image_op
= aco_opcode::image_atomic_swap
;
5964 case nir_intrinsic_image_deref_atomic_comp_swap
:
5965 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5966 image_op
= aco_opcode::image_atomic_cmpswap
;
5969 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5972 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5974 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5975 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5976 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5977 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5978 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5979 mubuf
->operands
[0] = Operand(resource
);
5980 mubuf
->operands
[1] = Operand(vindex
);
5981 mubuf
->operands
[2] = Operand((uint32_t)0);
5982 mubuf
->operands
[3] = Operand(data
);
5983 if (return_previous
)
5984 mubuf
->definitions
[0] = Definition(dst
);
5986 mubuf
->idxen
= true;
5987 mubuf
->glc
= return_previous
;
5988 mubuf
->dlc
= false; /* Not needed for atomics */
5989 mubuf
->disable_wqm
= true;
5990 mubuf
->barrier
= barrier_image
;
5991 ctx
->program
->needs_exact
= true;
5992 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5996 Temp coords
= get_image_coords(ctx
, instr
, type
);
5997 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5998 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5999 mimg
->operands
[0] = Operand(resource
);
6000 mimg
->operands
[1] = Operand(data
);
6001 mimg
->operands
[2] = Operand(coords
);
6002 if (return_previous
)
6003 mimg
->definitions
[0] = Definition(dst
);
6004 mimg
->glc
= return_previous
;
6005 mimg
->dlc
= false; /* Not needed for atomics */
6006 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6007 mimg
->dmask
= (1 << data
.size()) - 1;
6009 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6010 mimg
->disable_wqm
= true;
6011 mimg
->barrier
= barrier_image
;
6012 ctx
->program
->needs_exact
= true;
6013 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6017 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6019 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6020 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6021 Builder
bld(ctx
->program
, ctx
->block
);
6023 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6025 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6026 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6028 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6029 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6031 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6032 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6034 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6035 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6036 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6037 if (dst
.type() == RegType::vgpr
)
6038 bld
.copy(Definition(dst
), shr_dst
);
6040 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6042 emit_extract_vector(ctx
, desc
, 2, dst
);
6046 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6048 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6049 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6050 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6051 bool is_array
= glsl_sampler_type_is_array(type
);
6052 Builder
bld(ctx
->program
, ctx
->block
);
6054 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6055 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6056 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6060 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6063 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6065 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6067 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6068 mimg
->operands
[0] = Operand(resource
);
6069 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6070 mimg
->operands
[2] = Operand(lod
);
6071 uint8_t& dmask
= mimg
->dmask
;
6072 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6073 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6074 mimg
->da
= glsl_sampler_type_is_array(type
);
6075 mimg
->can_reorder
= true;
6076 Definition
& def
= mimg
->definitions
[0];
6077 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6079 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6080 glsl_sampler_type_is_array(type
)) {
6082 assert(instr
->dest
.ssa
.num_components
== 3);
6083 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6084 def
= Definition(tmp
);
6085 emit_split_vector(ctx
, tmp
, 3);
6087 /* divide 3rd value by 6 by multiplying with magic number */
6088 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6089 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6091 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6092 emit_extract_vector(ctx
, tmp
, 0, v1
),
6093 emit_extract_vector(ctx
, tmp
, 1, v1
),
6096 } else if (ctx
->options
->chip_class
== GFX9
&&
6097 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6098 glsl_sampler_type_is_array(type
)) {
6099 assert(instr
->dest
.ssa
.num_components
== 2);
6100 def
= Definition(dst
);
6103 def
= Definition(dst
);
6106 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6109 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6111 Builder
bld(ctx
->program
, ctx
->block
);
6112 unsigned num_components
= instr
->num_components
;
6114 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6115 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6116 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6118 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6119 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6120 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6121 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6124 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6126 Builder
bld(ctx
->program
, ctx
->block
);
6127 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6128 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6129 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6130 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6132 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6133 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6135 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
6136 ctx
->options
->chip_class
>= GFX8
&&
6137 elem_size_bytes
>= 4;
6139 offset
= bld
.as_uniform(offset
);
6140 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6142 unsigned write_count
= 0;
6143 Temp write_datas
[32];
6144 unsigned offsets
[32];
6145 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6146 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6148 for (unsigned i
= 0; i
< write_count
; i
++) {
6149 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6150 if (smem
&& ctx
->stage
== fragment_fs
)
6151 op
= aco_opcode::p_fs_buffer_store_smem
;
6154 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6155 store
->operands
[0] = Operand(rsrc
);
6157 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6158 offset
, Operand(offsets
[i
]));
6159 store
->operands
[1] = Operand(off
);
6161 store
->operands
[1] = Operand(offset
);
6163 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6164 store
->operands
[1].setFixed(m0
);
6165 store
->operands
[2] = Operand(write_datas
[i
]);
6166 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6168 store
->disable_wqm
= true;
6169 store
->barrier
= barrier_buffer
;
6170 ctx
->block
->instructions
.emplace_back(std::move(store
));
6171 ctx
->program
->wb_smem_l1_on_end
= true;
6172 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6173 ctx
->block
->kind
|= block_kind_needs_lowering
;
6174 ctx
->program
->needs_exact
= true;
6177 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6178 store
->operands
[0] = Operand(rsrc
);
6179 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6180 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6181 store
->operands
[3] = Operand(write_datas
[i
]);
6182 store
->offset
= offsets
[i
];
6183 store
->offen
= (offset
.type() == RegType::vgpr
);
6184 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6186 store
->disable_wqm
= true;
6187 store
->barrier
= barrier_buffer
;
6188 ctx
->program
->needs_exact
= true;
6189 ctx
->block
->instructions
.emplace_back(std::move(store
));
6194 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6196 /* return the previous value if dest is ever used */
6197 bool return_previous
= false;
6198 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6199 return_previous
= true;
6202 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6203 return_previous
= true;
6207 Builder
bld(ctx
->program
, ctx
->block
);
6208 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6210 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6211 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6212 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6214 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6215 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6216 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6218 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6220 aco_opcode op32
, op64
;
6221 switch (instr
->intrinsic
) {
6222 case nir_intrinsic_ssbo_atomic_add
:
6223 op32
= aco_opcode::buffer_atomic_add
;
6224 op64
= aco_opcode::buffer_atomic_add_x2
;
6226 case nir_intrinsic_ssbo_atomic_imin
:
6227 op32
= aco_opcode::buffer_atomic_smin
;
6228 op64
= aco_opcode::buffer_atomic_smin_x2
;
6230 case nir_intrinsic_ssbo_atomic_umin
:
6231 op32
= aco_opcode::buffer_atomic_umin
;
6232 op64
= aco_opcode::buffer_atomic_umin_x2
;
6234 case nir_intrinsic_ssbo_atomic_imax
:
6235 op32
= aco_opcode::buffer_atomic_smax
;
6236 op64
= aco_opcode::buffer_atomic_smax_x2
;
6238 case nir_intrinsic_ssbo_atomic_umax
:
6239 op32
= aco_opcode::buffer_atomic_umax
;
6240 op64
= aco_opcode::buffer_atomic_umax_x2
;
6242 case nir_intrinsic_ssbo_atomic_and
:
6243 op32
= aco_opcode::buffer_atomic_and
;
6244 op64
= aco_opcode::buffer_atomic_and_x2
;
6246 case nir_intrinsic_ssbo_atomic_or
:
6247 op32
= aco_opcode::buffer_atomic_or
;
6248 op64
= aco_opcode::buffer_atomic_or_x2
;
6250 case nir_intrinsic_ssbo_atomic_xor
:
6251 op32
= aco_opcode::buffer_atomic_xor
;
6252 op64
= aco_opcode::buffer_atomic_xor_x2
;
6254 case nir_intrinsic_ssbo_atomic_exchange
:
6255 op32
= aco_opcode::buffer_atomic_swap
;
6256 op64
= aco_opcode::buffer_atomic_swap_x2
;
6258 case nir_intrinsic_ssbo_atomic_comp_swap
:
6259 op32
= aco_opcode::buffer_atomic_cmpswap
;
6260 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6263 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6265 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6266 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6267 mubuf
->operands
[0] = Operand(rsrc
);
6268 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6269 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6270 mubuf
->operands
[3] = Operand(data
);
6271 if (return_previous
)
6272 mubuf
->definitions
[0] = Definition(dst
);
6274 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6275 mubuf
->glc
= return_previous
;
6276 mubuf
->dlc
= false; /* Not needed for atomics */
6277 mubuf
->disable_wqm
= true;
6278 mubuf
->barrier
= barrier_buffer
;
6279 ctx
->program
->needs_exact
= true;
6280 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6283 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6285 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6286 Builder
bld(ctx
->program
, ctx
->block
);
6287 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6288 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6291 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6293 Builder
bld(ctx
->program
, ctx
->block
);
6294 unsigned num_components
= instr
->num_components
;
6295 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6297 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6298 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6299 num_components
, component_size
};
6300 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6301 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6302 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6303 info
.barrier
= barrier_buffer
;
6304 info
.can_reorder
= false;
6305 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6306 * it's safe to use SMEM */
6307 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6308 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6309 emit_global_load(ctx
, bld
, &info
);
6311 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6312 emit_smem_load(ctx
, bld
, &info
);
6316 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6318 Builder
bld(ctx
->program
, ctx
->block
);
6319 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6320 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6322 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6323 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6324 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6326 if (ctx
->options
->chip_class
>= GFX7
)
6327 addr
= as_vgpr(ctx
, addr
);
6329 unsigned write_count
= 0;
6330 Temp write_datas
[32];
6331 unsigned offsets
[32];
6332 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6333 16, &write_count
, write_datas
, offsets
);
6335 for (unsigned i
= 0; i
< write_count
; i
++) {
6336 if (ctx
->options
->chip_class
>= GFX7
) {
6337 unsigned offset
= offsets
[i
];
6338 Temp store_addr
= addr
;
6339 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6340 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6341 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6342 Temp carry
= bld
.tmp(bld
.lm
);
6343 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6345 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6346 Operand(offset
), addr0
);
6347 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6349 carry
).def(1).setHint(vcc
);
6351 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6356 bool global
= ctx
->options
->chip_class
>= GFX9
;
6358 switch (write_datas
[i
].bytes()) {
6360 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6363 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6366 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6369 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6372 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6375 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6378 unreachable("store_global not implemented for this size.");
6381 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6382 flat
->operands
[0] = Operand(store_addr
);
6383 flat
->operands
[1] = Operand(s1
);
6384 flat
->operands
[2] = Operand(write_datas
[i
]);
6387 flat
->offset
= offset
;
6388 flat
->disable_wqm
= true;
6389 flat
->barrier
= barrier_buffer
;
6390 ctx
->program
->needs_exact
= true;
6391 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6393 assert(ctx
->options
->chip_class
== GFX6
);
6395 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6397 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6399 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6400 mubuf
->operands
[0] = Operand(rsrc
);
6401 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6402 mubuf
->operands
[2] = Operand(0u);
6403 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6406 mubuf
->offset
= offsets
[i
];
6407 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6408 mubuf
->disable_wqm
= true;
6409 mubuf
->barrier
= barrier_buffer
;
6410 ctx
->program
->needs_exact
= true;
6411 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6416 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6418 /* return the previous value if dest is ever used */
6419 bool return_previous
= false;
6420 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6421 return_previous
= true;
6424 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6425 return_previous
= true;
6429 Builder
bld(ctx
->program
, ctx
->block
);
6430 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6431 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6433 if (ctx
->options
->chip_class
>= GFX7
)
6434 addr
= as_vgpr(ctx
, addr
);
6436 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6437 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6438 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6440 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6442 aco_opcode op32
, op64
;
6444 if (ctx
->options
->chip_class
>= GFX7
) {
6445 bool global
= ctx
->options
->chip_class
>= GFX9
;
6446 switch (instr
->intrinsic
) {
6447 case nir_intrinsic_global_atomic_add
:
6448 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6449 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6451 case nir_intrinsic_global_atomic_imin
:
6452 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6453 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6455 case nir_intrinsic_global_atomic_umin
:
6456 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6457 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6459 case nir_intrinsic_global_atomic_imax
:
6460 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6461 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6463 case nir_intrinsic_global_atomic_umax
:
6464 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6465 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6467 case nir_intrinsic_global_atomic_and
:
6468 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6469 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6471 case nir_intrinsic_global_atomic_or
:
6472 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6473 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6475 case nir_intrinsic_global_atomic_xor
:
6476 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6477 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6479 case nir_intrinsic_global_atomic_exchange
:
6480 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6481 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6483 case nir_intrinsic_global_atomic_comp_swap
:
6484 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6485 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6488 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6491 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6492 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6493 flat
->operands
[0] = Operand(addr
);
6494 flat
->operands
[1] = Operand(s1
);
6495 flat
->operands
[2] = Operand(data
);
6496 if (return_previous
)
6497 flat
->definitions
[0] = Definition(dst
);
6498 flat
->glc
= return_previous
;
6499 flat
->dlc
= false; /* Not needed for atomics */
6501 flat
->disable_wqm
= true;
6502 flat
->barrier
= barrier_buffer
;
6503 ctx
->program
->needs_exact
= true;
6504 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6506 assert(ctx
->options
->chip_class
== GFX6
);
6508 switch (instr
->intrinsic
) {
6509 case nir_intrinsic_global_atomic_add
:
6510 op32
= aco_opcode::buffer_atomic_add
;
6511 op64
= aco_opcode::buffer_atomic_add_x2
;
6513 case nir_intrinsic_global_atomic_imin
:
6514 op32
= aco_opcode::buffer_atomic_smin
;
6515 op64
= aco_opcode::buffer_atomic_smin_x2
;
6517 case nir_intrinsic_global_atomic_umin
:
6518 op32
= aco_opcode::buffer_atomic_umin
;
6519 op64
= aco_opcode::buffer_atomic_umin_x2
;
6521 case nir_intrinsic_global_atomic_imax
:
6522 op32
= aco_opcode::buffer_atomic_smax
;
6523 op64
= aco_opcode::buffer_atomic_smax_x2
;
6525 case nir_intrinsic_global_atomic_umax
:
6526 op32
= aco_opcode::buffer_atomic_umax
;
6527 op64
= aco_opcode::buffer_atomic_umax_x2
;
6529 case nir_intrinsic_global_atomic_and
:
6530 op32
= aco_opcode::buffer_atomic_and
;
6531 op64
= aco_opcode::buffer_atomic_and_x2
;
6533 case nir_intrinsic_global_atomic_or
:
6534 op32
= aco_opcode::buffer_atomic_or
;
6535 op64
= aco_opcode::buffer_atomic_or_x2
;
6537 case nir_intrinsic_global_atomic_xor
:
6538 op32
= aco_opcode::buffer_atomic_xor
;
6539 op64
= aco_opcode::buffer_atomic_xor_x2
;
6541 case nir_intrinsic_global_atomic_exchange
:
6542 op32
= aco_opcode::buffer_atomic_swap
;
6543 op64
= aco_opcode::buffer_atomic_swap_x2
;
6545 case nir_intrinsic_global_atomic_comp_swap
:
6546 op32
= aco_opcode::buffer_atomic_cmpswap
;
6547 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6550 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6553 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6555 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6557 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6558 mubuf
->operands
[0] = Operand(rsrc
);
6559 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6560 mubuf
->operands
[2] = Operand(0u);
6561 mubuf
->operands
[3] = Operand(data
);
6562 if (return_previous
)
6563 mubuf
->definitions
[0] = Definition(dst
);
6564 mubuf
->glc
= return_previous
;
6567 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6568 mubuf
->disable_wqm
= true;
6569 mubuf
->barrier
= barrier_buffer
;
6570 ctx
->program
->needs_exact
= true;
6571 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6575 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6576 Builder
bld(ctx
->program
, ctx
->block
);
6577 switch(instr
->intrinsic
) {
6578 case nir_intrinsic_group_memory_barrier
:
6579 case nir_intrinsic_memory_barrier
:
6580 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6582 case nir_intrinsic_memory_barrier_buffer
:
6583 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6585 case nir_intrinsic_memory_barrier_image
:
6586 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6588 case nir_intrinsic_memory_barrier_tcs_patch
:
6589 case nir_intrinsic_memory_barrier_shared
:
6590 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6593 unreachable("Unimplemented memory barrier intrinsic");
6598 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6600 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6601 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6602 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6603 Builder
bld(ctx
->program
, ctx
->block
);
6605 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6606 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6607 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6610 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6612 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6613 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6614 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6615 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6617 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6618 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6621 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6623 unsigned offset
= nir_intrinsic_base(instr
);
6624 Builder
bld(ctx
->program
, ctx
->block
);
6625 Operand m
= load_lds_size_m0(bld
);
6626 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6627 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6629 unsigned num_operands
= 3;
6630 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6631 switch(instr
->intrinsic
) {
6632 case nir_intrinsic_shared_atomic_add
:
6633 op32
= aco_opcode::ds_add_u32
;
6634 op64
= aco_opcode::ds_add_u64
;
6635 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6636 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6638 case nir_intrinsic_shared_atomic_imin
:
6639 op32
= aco_opcode::ds_min_i32
;
6640 op64
= aco_opcode::ds_min_i64
;
6641 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6642 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6644 case nir_intrinsic_shared_atomic_umin
:
6645 op32
= aco_opcode::ds_min_u32
;
6646 op64
= aco_opcode::ds_min_u64
;
6647 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6648 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6650 case nir_intrinsic_shared_atomic_imax
:
6651 op32
= aco_opcode::ds_max_i32
;
6652 op64
= aco_opcode::ds_max_i64
;
6653 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6654 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6656 case nir_intrinsic_shared_atomic_umax
:
6657 op32
= aco_opcode::ds_max_u32
;
6658 op64
= aco_opcode::ds_max_u64
;
6659 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6660 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6662 case nir_intrinsic_shared_atomic_and
:
6663 op32
= aco_opcode::ds_and_b32
;
6664 op64
= aco_opcode::ds_and_b64
;
6665 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6666 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6668 case nir_intrinsic_shared_atomic_or
:
6669 op32
= aco_opcode::ds_or_b32
;
6670 op64
= aco_opcode::ds_or_b64
;
6671 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6672 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6674 case nir_intrinsic_shared_atomic_xor
:
6675 op32
= aco_opcode::ds_xor_b32
;
6676 op64
= aco_opcode::ds_xor_b64
;
6677 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6678 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6680 case nir_intrinsic_shared_atomic_exchange
:
6681 op32
= aco_opcode::ds_write_b32
;
6682 op64
= aco_opcode::ds_write_b64
;
6683 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6684 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6686 case nir_intrinsic_shared_atomic_comp_swap
:
6687 op32
= aco_opcode::ds_cmpst_b32
;
6688 op64
= aco_opcode::ds_cmpst_b64
;
6689 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6690 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6694 unreachable("Unhandled shared atomic intrinsic");
6697 /* return the previous value if dest is ever used */
6698 bool return_previous
= false;
6699 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6700 return_previous
= true;
6703 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6704 return_previous
= true;
6709 if (data
.size() == 1) {
6710 assert(instr
->dest
.ssa
.bit_size
== 32);
6711 op
= return_previous
? op32_rtn
: op32
;
6713 assert(instr
->dest
.ssa
.bit_size
== 64);
6714 op
= return_previous
? op64_rtn
: op64
;
6717 if (offset
> 65535) {
6718 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6722 aco_ptr
<DS_instruction
> ds
;
6723 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6724 ds
->operands
[0] = Operand(address
);
6725 ds
->operands
[1] = Operand(data
);
6726 if (num_operands
== 4)
6727 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6728 ds
->operands
[num_operands
- 1] = m
;
6729 ds
->offset0
= offset
;
6730 if (return_previous
)
6731 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6732 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6735 Temp
get_scratch_resource(isel_context
*ctx
)
6737 Builder
bld(ctx
->program
, ctx
->block
);
6738 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6739 if (ctx
->stage
!= compute_cs
)
6740 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6742 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6743 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6745 if (ctx
->program
->chip_class
>= GFX10
) {
6746 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6747 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6748 S_008F0C_RESOURCE_LEVEL(1);
6749 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6750 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6751 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6754 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6755 if (ctx
->program
->chip_class
<= GFX8
)
6756 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6758 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6761 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6762 Builder
bld(ctx
->program
, ctx
->block
);
6763 Temp rsrc
= get_scratch_resource(ctx
);
6764 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6765 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6767 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6768 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6769 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6770 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6771 info
.swizzle_component_size
= 16;
6772 info
.can_reorder
= false;
6773 info
.soffset
= ctx
->program
->scratch_offset
;
6774 emit_mubuf_load(ctx
, bld
, &info
);
6777 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6778 Builder
bld(ctx
->program
, ctx
->block
);
6779 Temp rsrc
= get_scratch_resource(ctx
);
6780 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6781 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6783 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6784 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6786 unsigned write_count
= 0;
6787 Temp write_datas
[32];
6788 unsigned offsets
[32];
6789 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6790 16, &write_count
, write_datas
, offsets
);
6792 for (unsigned i
= 0; i
< write_count
; i
++) {
6793 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6794 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6798 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6799 uint8_t log2_ps_iter_samples
;
6800 if (ctx
->program
->info
->ps
.force_persample
) {
6801 log2_ps_iter_samples
=
6802 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6804 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6807 /* The bit pattern matches that used by fixed function fragment
6809 static const unsigned ps_iter_masks
[] = {
6810 0xffff, /* not used */
6816 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6818 Builder
bld(ctx
->program
, ctx
->block
);
6820 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6821 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6822 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6823 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6824 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6825 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6828 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6829 Builder
bld(ctx
->program
, ctx
->block
);
6831 unsigned stream
= nir_intrinsic_stream_id(instr
);
6832 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6833 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6834 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6837 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6839 unsigned num_components
=
6840 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6841 assert(num_components
);
6843 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6844 unsigned stream_offset
= 0;
6845 for (unsigned i
= 0; i
< stream
; i
++) {
6846 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6847 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6850 /* Limit on the stride field for <= GFX7. */
6851 assert(stride
< (1 << 14));
6853 Temp gsvs_dwords
[4];
6854 for (unsigned i
= 0; i
< 4; i
++)
6855 gsvs_dwords
[i
] = bld
.tmp(s1
);
6856 bld
.pseudo(aco_opcode::p_split_vector
,
6857 Definition(gsvs_dwords
[0]),
6858 Definition(gsvs_dwords
[1]),
6859 Definition(gsvs_dwords
[2]),
6860 Definition(gsvs_dwords
[3]),
6863 if (stream_offset
) {
6864 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6866 Temp carry
= bld
.tmp(s1
);
6867 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6868 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6871 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6872 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6874 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6875 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6877 unsigned offset
= 0;
6878 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6879 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6882 for (unsigned j
= 0; j
< 4; j
++) {
6883 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6886 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6887 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6888 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6889 if (const_offset
>= 4096u) {
6890 if (vaddr_offset
.isUndefined())
6891 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6893 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6894 const_offset
%= 4096u;
6897 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6898 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6899 mtbuf
->operands
[1] = vaddr_offset
;
6900 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6901 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6902 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6903 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6904 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6905 mtbuf
->offset
= const_offset
;
6908 mtbuf
->barrier
= barrier_gs_data
;
6909 mtbuf
->can_reorder
= true;
6910 bld
.insert(std::move(mtbuf
));
6913 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6916 /* outputs for the next vertex are undefined and keeping them around can
6917 * create invalid IR with control flow */
6918 ctx
->outputs
.mask
[i
] = 0;
6921 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6924 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6926 Builder
bld(ctx
->program
, ctx
->block
);
6928 if (cluster_size
== 1) {
6930 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6931 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6932 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6933 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6934 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6935 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6936 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6937 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6938 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6939 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6940 //subgroupAnd(val) -> (exec & ~val) == 0
6941 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6942 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6943 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6944 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6945 //subgroupOr(val) -> (val & exec) != 0
6946 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6947 return bool_to_vector_condition(ctx
, tmp
);
6948 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6949 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6950 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6951 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6952 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6953 return bool_to_vector_condition(ctx
, tmp
);
6955 //subgroupClustered{And,Or,Xor}(val, n) ->
6956 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6957 //cluster_offset = ~(n - 1) & lane_id
6958 //cluster_mask = ((1 << n) - 1)
6959 //subgroupClusteredAnd():
6960 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6961 //subgroupClusteredOr():
6962 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6963 //subgroupClusteredXor():
6964 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6965 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6966 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6969 if (op
== nir_op_iand
)
6970 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6972 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6974 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6976 if (ctx
->program
->chip_class
<= GFX7
)
6977 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6978 else if (ctx
->program
->wave_size
== 64)
6979 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6981 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6982 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6983 if (cluster_mask
!= 0xffffffff)
6984 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6986 Definition cmp_def
= Definition();
6987 if (op
== nir_op_iand
) {
6988 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6989 } else if (op
== nir_op_ior
) {
6990 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6991 } else if (op
== nir_op_ixor
) {
6992 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6993 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6994 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6996 cmp_def
.setHint(vcc
);
6997 return cmp_def
.getTemp();
7001 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7003 Builder
bld(ctx
->program
, ctx
->block
);
7005 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7006 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7007 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7009 if (op
== nir_op_iand
)
7010 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7012 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7014 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7015 Temp lo
= lohi
.def(0).getTemp();
7016 Temp hi
= lohi
.def(1).getTemp();
7017 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7019 Definition cmp_def
= Definition();
7020 if (op
== nir_op_iand
)
7021 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7022 else if (op
== nir_op_ior
)
7023 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7024 else if (op
== nir_op_ixor
)
7025 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7026 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7027 cmp_def
.setHint(vcc
);
7028 return cmp_def
.getTemp();
7031 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7033 Builder
bld(ctx
->program
, ctx
->block
);
7035 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7036 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7037 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7038 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7039 if (op
== nir_op_iand
)
7040 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7041 else if (op
== nir_op_ior
)
7042 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7043 else if (op
== nir_op_ixor
)
7044 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7050 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7052 Builder
bld(ctx
->program
, ctx
->block
);
7053 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7054 if (src
.regClass().type() == RegType::vgpr
) {
7055 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7056 } else if (src
.regClass() == s1
) {
7057 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7058 } else if (src
.regClass() == s2
) {
7059 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7061 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7062 nir_print_instr(&instr
->instr
, stderr
);
7063 fprintf(stderr
, "\n");
7067 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7069 Builder
bld(ctx
->program
, ctx
->block
);
7070 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7071 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7072 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7074 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7075 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7076 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7077 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7080 if (ctx
->program
->chip_class
>= GFX8
) {
7081 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7082 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7083 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7084 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7085 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7086 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7088 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7089 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7090 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7091 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7092 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7093 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7094 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7095 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7096 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7097 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7100 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7101 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7102 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7103 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7104 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7105 Temp wqm1
= bld
.tmp(v1
);
7106 emit_wqm(ctx
, tmp1
, wqm1
, true);
7107 Temp wqm2
= bld
.tmp(v1
);
7108 emit_wqm(ctx
, tmp2
, wqm2
, true);
7109 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7113 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7115 Builder
bld(ctx
->program
, ctx
->block
);
7116 switch(instr
->intrinsic
) {
7117 case nir_intrinsic_load_barycentric_sample
:
7118 case nir_intrinsic_load_barycentric_pixel
:
7119 case nir_intrinsic_load_barycentric_centroid
: {
7120 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7121 Temp bary
= Temp(0, s2
);
7123 case INTERP_MODE_SMOOTH
:
7124 case INTERP_MODE_NONE
:
7125 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7126 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7127 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7128 bary
= ctx
->persp_centroid
;
7129 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7130 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7132 case INTERP_MODE_NOPERSPECTIVE
:
7133 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7134 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7135 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7136 bary
= ctx
->linear_centroid
;
7137 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7138 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7143 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7144 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7145 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7146 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7147 Operand(p1
), Operand(p2
));
7148 emit_split_vector(ctx
, dst
, 2);
7151 case nir_intrinsic_load_barycentric_model
: {
7152 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7154 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7155 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7156 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7157 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7159 Operand(p1
), Operand(p2
), Operand(p3
));
7160 emit_split_vector(ctx
, dst
, 3);
7163 case nir_intrinsic_load_barycentric_at_sample
: {
7164 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7165 switch (ctx
->options
->key
.fs
.num_samples
) {
7166 case 2: sample_pos_offset
+= 1 << 3; break;
7167 case 4: sample_pos_offset
+= 3 << 3; break;
7168 case 8: sample_pos_offset
+= 7 << 3; break;
7172 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7173 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7174 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7175 if (addr
.type() == RegType::sgpr
) {
7178 sample_pos_offset
+= const_addr
->u32
<< 3;
7179 offset
= Operand(sample_pos_offset
);
7180 } else if (ctx
->options
->chip_class
>= GFX9
) {
7181 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7183 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7184 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7187 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7188 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7190 } else if (ctx
->options
->chip_class
>= GFX9
) {
7191 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7192 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7193 } else if (ctx
->options
->chip_class
>= GFX7
) {
7194 /* addr += private_segment_buffer + sample_pos_offset */
7195 Temp tmp0
= bld
.tmp(s1
);
7196 Temp tmp1
= bld
.tmp(s1
);
7197 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7198 Definition scc_tmp
= bld
.def(s1
, scc
);
7199 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7200 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7201 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7202 Temp pck0
= bld
.tmp(v1
);
7203 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7204 tmp1
= as_vgpr(ctx
, tmp1
);
7205 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7206 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7208 /* sample_pos = flat_load_dwordx2 addr */
7209 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7211 assert(ctx
->options
->chip_class
== GFX6
);
7213 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7214 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7215 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7217 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7218 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7220 sample_pos
= bld
.tmp(v2
);
7222 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7223 load
->definitions
[0] = Definition(sample_pos
);
7224 load
->operands
[0] = Operand(rsrc
);
7225 load
->operands
[1] = Operand(addr
);
7226 load
->operands
[2] = Operand(0u);
7227 load
->offset
= sample_pos_offset
;
7229 load
->addr64
= true;
7232 load
->disable_wqm
= false;
7233 load
->barrier
= barrier_none
;
7234 load
->can_reorder
= true;
7235 ctx
->block
->instructions
.emplace_back(std::move(load
));
7238 /* sample_pos -= 0.5 */
7239 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7240 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7241 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7242 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7243 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7245 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7248 case nir_intrinsic_load_barycentric_at_offset
: {
7249 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7250 RegClass rc
= RegClass(offset
.type(), 1);
7251 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7252 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7253 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7256 case nir_intrinsic_load_front_face
: {
7257 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7258 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7261 case nir_intrinsic_load_view_index
: {
7262 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7263 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7264 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7270 case nir_intrinsic_load_layer_id
: {
7271 unsigned idx
= nir_intrinsic_base(instr
);
7272 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7273 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7276 case nir_intrinsic_load_frag_coord
: {
7277 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7280 case nir_intrinsic_load_sample_pos
: {
7281 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7282 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7283 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7284 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7285 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7288 case nir_intrinsic_load_tess_coord
:
7289 visit_load_tess_coord(ctx
, instr
);
7291 case nir_intrinsic_load_interpolated_input
:
7292 visit_load_interpolated_input(ctx
, instr
);
7294 case nir_intrinsic_store_output
:
7295 visit_store_output(ctx
, instr
);
7297 case nir_intrinsic_load_input
:
7298 case nir_intrinsic_load_input_vertex
:
7299 visit_load_input(ctx
, instr
);
7301 case nir_intrinsic_load_output
:
7302 visit_load_output(ctx
, instr
);
7304 case nir_intrinsic_load_per_vertex_input
:
7305 visit_load_per_vertex_input(ctx
, instr
);
7307 case nir_intrinsic_load_per_vertex_output
:
7308 visit_load_per_vertex_output(ctx
, instr
);
7310 case nir_intrinsic_store_per_vertex_output
:
7311 visit_store_per_vertex_output(ctx
, instr
);
7313 case nir_intrinsic_load_ubo
:
7314 visit_load_ubo(ctx
, instr
);
7316 case nir_intrinsic_load_push_constant
:
7317 visit_load_push_constant(ctx
, instr
);
7319 case nir_intrinsic_load_constant
:
7320 visit_load_constant(ctx
, instr
);
7322 case nir_intrinsic_vulkan_resource_index
:
7323 visit_load_resource(ctx
, instr
);
7325 case nir_intrinsic_discard
:
7326 visit_discard(ctx
, instr
);
7328 case nir_intrinsic_discard_if
:
7329 visit_discard_if(ctx
, instr
);
7331 case nir_intrinsic_load_shared
:
7332 visit_load_shared(ctx
, instr
);
7334 case nir_intrinsic_store_shared
:
7335 visit_store_shared(ctx
, instr
);
7337 case nir_intrinsic_shared_atomic_add
:
7338 case nir_intrinsic_shared_atomic_imin
:
7339 case nir_intrinsic_shared_atomic_umin
:
7340 case nir_intrinsic_shared_atomic_imax
:
7341 case nir_intrinsic_shared_atomic_umax
:
7342 case nir_intrinsic_shared_atomic_and
:
7343 case nir_intrinsic_shared_atomic_or
:
7344 case nir_intrinsic_shared_atomic_xor
:
7345 case nir_intrinsic_shared_atomic_exchange
:
7346 case nir_intrinsic_shared_atomic_comp_swap
:
7347 visit_shared_atomic(ctx
, instr
);
7349 case nir_intrinsic_image_deref_load
:
7350 visit_image_load(ctx
, instr
);
7352 case nir_intrinsic_image_deref_store
:
7353 visit_image_store(ctx
, instr
);
7355 case nir_intrinsic_image_deref_atomic_add
:
7356 case nir_intrinsic_image_deref_atomic_umin
:
7357 case nir_intrinsic_image_deref_atomic_imin
:
7358 case nir_intrinsic_image_deref_atomic_umax
:
7359 case nir_intrinsic_image_deref_atomic_imax
:
7360 case nir_intrinsic_image_deref_atomic_and
:
7361 case nir_intrinsic_image_deref_atomic_or
:
7362 case nir_intrinsic_image_deref_atomic_xor
:
7363 case nir_intrinsic_image_deref_atomic_exchange
:
7364 case nir_intrinsic_image_deref_atomic_comp_swap
:
7365 visit_image_atomic(ctx
, instr
);
7367 case nir_intrinsic_image_deref_size
:
7368 visit_image_size(ctx
, instr
);
7370 case nir_intrinsic_load_ssbo
:
7371 visit_load_ssbo(ctx
, instr
);
7373 case nir_intrinsic_store_ssbo
:
7374 visit_store_ssbo(ctx
, instr
);
7376 case nir_intrinsic_load_global
:
7377 visit_load_global(ctx
, instr
);
7379 case nir_intrinsic_store_global
:
7380 visit_store_global(ctx
, instr
);
7382 case nir_intrinsic_global_atomic_add
:
7383 case nir_intrinsic_global_atomic_imin
:
7384 case nir_intrinsic_global_atomic_umin
:
7385 case nir_intrinsic_global_atomic_imax
:
7386 case nir_intrinsic_global_atomic_umax
:
7387 case nir_intrinsic_global_atomic_and
:
7388 case nir_intrinsic_global_atomic_or
:
7389 case nir_intrinsic_global_atomic_xor
:
7390 case nir_intrinsic_global_atomic_exchange
:
7391 case nir_intrinsic_global_atomic_comp_swap
:
7392 visit_global_atomic(ctx
, instr
);
7394 case nir_intrinsic_ssbo_atomic_add
:
7395 case nir_intrinsic_ssbo_atomic_imin
:
7396 case nir_intrinsic_ssbo_atomic_umin
:
7397 case nir_intrinsic_ssbo_atomic_imax
:
7398 case nir_intrinsic_ssbo_atomic_umax
:
7399 case nir_intrinsic_ssbo_atomic_and
:
7400 case nir_intrinsic_ssbo_atomic_or
:
7401 case nir_intrinsic_ssbo_atomic_xor
:
7402 case nir_intrinsic_ssbo_atomic_exchange
:
7403 case nir_intrinsic_ssbo_atomic_comp_swap
:
7404 visit_atomic_ssbo(ctx
, instr
);
7406 case nir_intrinsic_load_scratch
:
7407 visit_load_scratch(ctx
, instr
);
7409 case nir_intrinsic_store_scratch
:
7410 visit_store_scratch(ctx
, instr
);
7412 case nir_intrinsic_get_buffer_size
:
7413 visit_get_buffer_size(ctx
, instr
);
7415 case nir_intrinsic_control_barrier
: {
7416 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7417 /* GFX6 only (thanks to a hw bug workaround):
7418 * The real barrier instruction isn’t needed, because an entire patch
7419 * always fits into a single wave.
7424 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7425 bld
.sopp(aco_opcode::s_barrier
);
7429 case nir_intrinsic_memory_barrier_tcs_patch
:
7430 case nir_intrinsic_group_memory_barrier
:
7431 case nir_intrinsic_memory_barrier
:
7432 case nir_intrinsic_memory_barrier_buffer
:
7433 case nir_intrinsic_memory_barrier_image
:
7434 case nir_intrinsic_memory_barrier_shared
:
7435 emit_memory_barrier(ctx
, instr
);
7437 case nir_intrinsic_load_num_work_groups
: {
7438 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7439 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7440 emit_split_vector(ctx
, dst
, 3);
7443 case nir_intrinsic_load_local_invocation_id
: {
7444 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7445 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7446 emit_split_vector(ctx
, dst
, 3);
7449 case nir_intrinsic_load_work_group_id
: {
7450 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7451 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7452 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7453 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7454 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7455 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7456 emit_split_vector(ctx
, dst
, 3);
7459 case nir_intrinsic_load_local_invocation_index
: {
7460 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7462 /* The tg_size bits [6:11] contain the subgroup id,
7463 * we need this multiplied by the wave size, and then OR the thread id to it.
7465 if (ctx
->program
->wave_size
== 64) {
7466 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7467 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7468 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7469 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7471 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7472 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7473 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7474 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7478 case nir_intrinsic_load_subgroup_id
: {
7479 if (ctx
->stage
== compute_cs
) {
7480 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7481 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7483 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7487 case nir_intrinsic_load_subgroup_invocation
: {
7488 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7491 case nir_intrinsic_load_num_subgroups
: {
7492 if (ctx
->stage
== compute_cs
)
7493 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7494 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7496 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7499 case nir_intrinsic_ballot
: {
7500 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7501 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7502 Definition tmp
= bld
.def(dst
.regClass());
7503 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7504 if (instr
->src
[0].ssa
->bit_size
== 1) {
7505 assert(src
.regClass() == bld
.lm
);
7506 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7507 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7508 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7509 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7510 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7512 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7513 nir_print_instr(&instr
->instr
, stderr
);
7514 fprintf(stderr
, "\n");
7516 if (dst
.size() != bld
.lm
.size()) {
7517 /* Wave32 with ballot size set to 64 */
7518 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7520 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7523 case nir_intrinsic_shuffle
:
7524 case nir_intrinsic_read_invocation
: {
7525 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7526 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7527 emit_uniform_subgroup(ctx
, instr
, src
);
7529 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7530 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7531 tid
= bld
.as_uniform(tid
);
7532 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7533 if (src
.regClass() == v1
) {
7534 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7535 } else if (src
.regClass() == v2
) {
7536 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7537 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7538 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7539 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7541 emit_split_vector(ctx
, dst
, 2);
7542 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7543 assert(src
.regClass() == bld
.lm
);
7544 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7545 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7546 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7547 assert(src
.regClass() == bld
.lm
);
7549 if (ctx
->program
->chip_class
<= GFX7
)
7550 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7551 else if (ctx
->program
->wave_size
== 64)
7552 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7554 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7555 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7556 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7557 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7560 nir_print_instr(&instr
->instr
, stderr
);
7561 fprintf(stderr
, "\n");
7566 case nir_intrinsic_load_sample_id
: {
7567 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7568 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7571 case nir_intrinsic_load_sample_mask_in
: {
7572 visit_load_sample_mask_in(ctx
, instr
);
7575 case nir_intrinsic_read_first_invocation
: {
7576 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7577 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7578 if (src
.regClass() == v1
) {
7580 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7582 } else if (src
.regClass() == v2
) {
7583 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7584 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7585 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7586 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7587 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7588 emit_split_vector(ctx
, dst
, 2);
7589 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7590 assert(src
.regClass() == bld
.lm
);
7591 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7592 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7593 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7594 } else if (src
.regClass() == s1
) {
7595 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7596 } else if (src
.regClass() == s2
) {
7597 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7599 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7600 nir_print_instr(&instr
->instr
, stderr
);
7601 fprintf(stderr
, "\n");
7605 case nir_intrinsic_vote_all
: {
7606 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7607 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7608 assert(src
.regClass() == bld
.lm
);
7609 assert(dst
.regClass() == bld
.lm
);
7611 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7612 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7613 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7616 case nir_intrinsic_vote_any
: {
7617 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7618 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7619 assert(src
.regClass() == bld
.lm
);
7620 assert(dst
.regClass() == bld
.lm
);
7622 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7623 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7626 case nir_intrinsic_reduce
:
7627 case nir_intrinsic_inclusive_scan
:
7628 case nir_intrinsic_exclusive_scan
: {
7629 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7630 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7631 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7632 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7633 nir_intrinsic_cluster_size(instr
) : 0;
7634 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7636 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7637 emit_uniform_subgroup(ctx
, instr
, src
);
7638 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7639 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7641 else if (op
== nir_op_iadd
)
7643 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7645 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7647 switch (instr
->intrinsic
) {
7648 case nir_intrinsic_reduce
:
7649 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7651 case nir_intrinsic_exclusive_scan
:
7652 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7654 case nir_intrinsic_inclusive_scan
:
7655 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7660 } else if (cluster_size
== 1) {
7661 bld
.copy(Definition(dst
), src
);
7663 src
= as_vgpr(ctx
, src
);
7667 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7682 unreachable("unknown reduction op");
7687 switch (instr
->intrinsic
) {
7688 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7689 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7690 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7692 unreachable("unknown reduce intrinsic");
7695 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7696 reduce
->operands
[0] = Operand(src
);
7697 // filled in by aco_reduce_assign.cpp, used internally as part of the
7699 assert(dst
.size() == 1 || dst
.size() == 2);
7700 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7701 reduce
->operands
[2] = Operand(v1
.as_linear());
7703 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7704 reduce
->definitions
[0] = Definition(tmp_dst
);
7705 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7706 reduce
->definitions
[2] = Definition();
7707 reduce
->definitions
[3] = Definition(scc
, s1
);
7708 reduce
->definitions
[4] = Definition();
7709 reduce
->reduce_op
= reduce_op
;
7710 reduce
->cluster_size
= cluster_size
;
7711 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7713 emit_wqm(ctx
, tmp_dst
, dst
);
7717 case nir_intrinsic_quad_broadcast
: {
7718 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7719 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7720 emit_uniform_subgroup(ctx
, instr
, src
);
7722 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7723 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7724 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7726 if (instr
->dest
.ssa
.bit_size
== 1) {
7727 assert(src
.regClass() == bld
.lm
);
7728 assert(dst
.regClass() == bld
.lm
);
7729 uint32_t half_mask
= 0x11111111u
<< lane
;
7730 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7731 Temp tmp
= bld
.tmp(bld
.lm
);
7732 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7733 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7734 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7735 emit_wqm(ctx
, tmp
, dst
);
7736 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7737 if (ctx
->program
->chip_class
>= GFX8
)
7738 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7740 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7741 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7742 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7743 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7744 if (ctx
->program
->chip_class
>= GFX8
) {
7745 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7746 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7748 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7749 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7751 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7752 emit_split_vector(ctx
, dst
, 2);
7754 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7755 nir_print_instr(&instr
->instr
, stderr
);
7756 fprintf(stderr
, "\n");
7761 case nir_intrinsic_quad_swap_horizontal
:
7762 case nir_intrinsic_quad_swap_vertical
:
7763 case nir_intrinsic_quad_swap_diagonal
:
7764 case nir_intrinsic_quad_swizzle_amd
: {
7765 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7766 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7767 emit_uniform_subgroup(ctx
, instr
, src
);
7770 uint16_t dpp_ctrl
= 0;
7771 switch (instr
->intrinsic
) {
7772 case nir_intrinsic_quad_swap_horizontal
:
7773 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7775 case nir_intrinsic_quad_swap_vertical
:
7776 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7778 case nir_intrinsic_quad_swap_diagonal
:
7779 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7781 case nir_intrinsic_quad_swizzle_amd
:
7782 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7787 if (ctx
->program
->chip_class
< GFX8
)
7788 dpp_ctrl
|= (1 << 15);
7790 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7791 if (instr
->dest
.ssa
.bit_size
== 1) {
7792 assert(src
.regClass() == bld
.lm
);
7793 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7794 if (ctx
->program
->chip_class
>= GFX8
)
7795 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7797 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7798 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7799 emit_wqm(ctx
, tmp
, dst
);
7800 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7802 if (ctx
->program
->chip_class
>= GFX8
)
7803 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7805 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7806 emit_wqm(ctx
, tmp
, dst
);
7807 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7808 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7809 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7810 if (ctx
->program
->chip_class
>= GFX8
) {
7811 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7812 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7814 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7815 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7817 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7818 emit_split_vector(ctx
, dst
, 2);
7820 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7821 nir_print_instr(&instr
->instr
, stderr
);
7822 fprintf(stderr
, "\n");
7826 case nir_intrinsic_masked_swizzle_amd
: {
7827 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7828 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7829 emit_uniform_subgroup(ctx
, instr
, src
);
7832 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7833 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7834 if (dst
.regClass() == v1
) {
7836 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7838 } else if (dst
.regClass() == v2
) {
7839 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7840 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7841 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7842 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7843 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7844 emit_split_vector(ctx
, dst
, 2);
7846 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7847 nir_print_instr(&instr
->instr
, stderr
);
7848 fprintf(stderr
, "\n");
7852 case nir_intrinsic_write_invocation_amd
: {
7853 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7854 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7855 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7856 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7857 if (dst
.regClass() == v1
) {
7858 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7859 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7860 } else if (dst
.regClass() == v2
) {
7861 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7862 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7863 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7864 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7865 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7866 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7867 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7868 emit_split_vector(ctx
, dst
, 2);
7870 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7871 nir_print_instr(&instr
->instr
, stderr
);
7872 fprintf(stderr
, "\n");
7876 case nir_intrinsic_mbcnt_amd
: {
7877 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7878 RegClass rc
= RegClass(src
.type(), 1);
7879 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7880 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7881 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7882 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7883 emit_wqm(ctx
, wqm_tmp
, dst
);
7886 case nir_intrinsic_load_helper_invocation
: {
7887 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7888 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7889 ctx
->block
->kind
|= block_kind_needs_lowering
;
7890 ctx
->program
->needs_exact
= true;
7893 case nir_intrinsic_is_helper_invocation
: {
7894 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7895 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7896 ctx
->block
->kind
|= block_kind_needs_lowering
;
7897 ctx
->program
->needs_exact
= true;
7900 case nir_intrinsic_demote
:
7901 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7903 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7904 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7905 ctx
->block
->kind
|= block_kind_uses_demote
;
7906 ctx
->program
->needs_exact
= true;
7908 case nir_intrinsic_demote_if
: {
7909 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7910 assert(src
.regClass() == bld
.lm
);
7911 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7912 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7914 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7915 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7916 ctx
->block
->kind
|= block_kind_uses_demote
;
7917 ctx
->program
->needs_exact
= true;
7920 case nir_intrinsic_first_invocation
: {
7921 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7922 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7925 case nir_intrinsic_shader_clock
:
7926 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7927 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7929 case nir_intrinsic_load_vertex_id_zero_base
: {
7930 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7931 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7934 case nir_intrinsic_load_first_vertex
: {
7935 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7936 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7939 case nir_intrinsic_load_base_instance
: {
7940 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7941 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7944 case nir_intrinsic_load_instance_id
: {
7945 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7946 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7949 case nir_intrinsic_load_draw_id
: {
7950 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7951 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7954 case nir_intrinsic_load_invocation_id
: {
7955 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7957 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7958 if (ctx
->options
->chip_class
>= GFX10
)
7959 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7961 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7962 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7963 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7964 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7966 unreachable("Unsupported stage for load_invocation_id");
7971 case nir_intrinsic_load_primitive_id
: {
7972 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7974 switch (ctx
->shader
->info
.stage
) {
7975 case MESA_SHADER_GEOMETRY
:
7976 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7978 case MESA_SHADER_TESS_CTRL
:
7979 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7981 case MESA_SHADER_TESS_EVAL
:
7982 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7985 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7990 case nir_intrinsic_load_patch_vertices_in
: {
7991 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7992 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7994 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7995 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7998 case nir_intrinsic_emit_vertex_with_counter
: {
7999 visit_emit_vertex_with_counter(ctx
, instr
);
8002 case nir_intrinsic_end_primitive_with_counter
: {
8003 unsigned stream
= nir_intrinsic_stream_id(instr
);
8004 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8007 case nir_intrinsic_set_vertex_count
: {
8008 /* unused, the HW keeps track of this for us */
8012 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8013 nir_print_instr(&instr
->instr
, stderr
);
8014 fprintf(stderr
, "\n");
8022 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8023 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8024 enum glsl_base_type
*stype
)
8026 nir_deref_instr
*texture_deref_instr
= NULL
;
8027 nir_deref_instr
*sampler_deref_instr
= NULL
;
8030 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8031 switch (instr
->src
[i
].src_type
) {
8032 case nir_tex_src_texture_deref
:
8033 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8035 case nir_tex_src_sampler_deref
:
8036 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8038 case nir_tex_src_plane
:
8039 plane
= nir_src_as_int(instr
->src
[i
].src
);
8046 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8048 if (!sampler_deref_instr
)
8049 sampler_deref_instr
= texture_deref_instr
;
8052 assert(instr
->op
!= nir_texop_txf_ms
&&
8053 instr
->op
!= nir_texop_samples_identical
);
8054 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8055 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8056 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8057 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8058 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8059 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8061 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8064 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8066 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8067 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8068 Builder
bld(ctx
->program
, ctx
->block
);
8070 /* to avoid unnecessary moves, we split and recombine sampler and image */
8071 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8072 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8073 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8074 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8075 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8076 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8077 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8078 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8080 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8081 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8082 img
[0], img
[1], img
[2], img
[3],
8083 img
[4], img
[5], img
[6], img
[7]);
8084 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8085 samp
[0], samp
[1], samp
[2], samp
[3]);
8088 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8089 instr
->op
== nir_texop_samples_identical
))
8090 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8093 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8094 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8096 Builder
bld(ctx
->program
, ctx
->block
);
8098 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8099 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8100 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8102 Operand
neg_one(0xbf800000u
);
8103 Operand
one(0x3f800000u
);
8104 Operand
two(0x40000000u
);
8105 Operand
four(0x40800000u
);
8107 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8108 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8109 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8111 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8112 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8113 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8114 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8117 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8118 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8119 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8121 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8124 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8125 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8126 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8129 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8130 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8132 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8133 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8136 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8138 Builder
bld(ctx
->program
, ctx
->block
);
8139 Temp ma
, tc
, sc
, id
;
8142 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8144 // see comment in ac_prepare_cube_coords()
8145 if (ctx
->options
->chip_class
<= GFX8
)
8146 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8149 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8151 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8152 vop3a
->operands
[0] = Operand(ma
);
8153 vop3a
->abs
[0] = true;
8154 Temp invma
= bld
.tmp(v1
);
8155 vop3a
->definitions
[0] = Definition(invma
);
8156 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8158 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8160 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8162 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8164 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8166 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8169 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8170 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8172 for (unsigned i
= 0; i
< 2; i
++) {
8173 // see comment in ac_prepare_cube_coords()
8175 Temp deriv_sc
, deriv_tc
;
8176 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8177 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8179 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8181 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8182 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8183 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8184 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8185 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8186 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8187 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8190 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8191 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8195 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8202 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8204 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8206 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8207 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8210 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8211 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8212 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8216 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8218 Builder
bld(ctx
->program
, ctx
->block
);
8219 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8220 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8221 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8222 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8223 std::vector
<Temp
> coords
;
8224 std::vector
<Temp
> derivs
;
8225 nir_const_value
*sample_index_cv
= NULL
;
8226 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8227 enum glsl_base_type stype
;
8228 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8230 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8231 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8232 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8233 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8235 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8236 switch (instr
->src
[i
].src_type
) {
8237 case nir_tex_src_coord
: {
8238 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8239 for (unsigned i
= 0; i
< coord
.size(); i
++)
8240 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8243 case nir_tex_src_bias
:
8244 if (instr
->op
== nir_texop_txb
) {
8245 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8249 case nir_tex_src_lod
: {
8250 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8252 if (val
&& val
->f32
<= 0.0) {
8255 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8260 case nir_tex_src_comparator
:
8261 if (instr
->is_shadow
) {
8262 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8266 case nir_tex_src_offset
:
8267 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8268 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8271 case nir_tex_src_ddx
:
8272 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8275 case nir_tex_src_ddy
:
8276 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8279 case nir_tex_src_ms_index
:
8280 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8281 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8282 has_sample_index
= true;
8284 case nir_tex_src_texture_offset
:
8285 case nir_tex_src_sampler_offset
:
8291 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8292 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8294 if (instr
->op
== nir_texop_texture_samples
) {
8295 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8297 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8298 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8299 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8300 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8302 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8303 samples
, Operand(1u), bld
.scc(is_msaa
));
8307 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8308 aco_ptr
<Instruction
> tmp_instr
;
8309 Temp acc
, pack
= Temp();
8311 uint32_t pack_const
= 0;
8312 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8313 if (!const_offset
[i
])
8315 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8318 if (offset
.type() == RegType::sgpr
) {
8319 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8320 if (const_offset
[i
])
8323 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8324 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8327 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8330 if (pack
== Temp()) {
8333 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8337 if (pack_const
&& pack
!= Temp())
8338 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8340 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8341 if (const_offset
[i
])
8344 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8345 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8348 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8351 if (pack
== Temp()) {
8354 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8358 if (pack_const
&& pack
!= Temp())
8359 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8361 if (pack_const
&& pack
== Temp())
8362 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8363 else if (pack
== Temp())
8369 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8370 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8372 /* pack derivatives */
8373 if (has_ddx
|| has_ddy
) {
8374 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8375 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8376 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8377 derivs
= {ddx
, zero
, ddy
, zero
};
8379 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8380 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8381 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8382 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8387 if (instr
->coord_components
> 1 &&
8388 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8390 instr
->op
!= nir_texop_txf
)
8391 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8393 if (instr
->coord_components
> 2 &&
8394 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8395 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8396 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8397 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8399 instr
->op
!= nir_texop_txf
&&
8400 instr
->op
!= nir_texop_txf_ms
&&
8401 instr
->op
!= nir_texop_fragment_fetch
&&
8402 instr
->op
!= nir_texop_fragment_mask_fetch
)
8403 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8405 if (ctx
->options
->chip_class
== GFX9
&&
8406 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8407 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8408 assert(coords
.size() > 0 && coords
.size() < 3);
8410 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8411 Operand((uint32_t) 0) :
8412 Operand((uint32_t) 0x3f000000)));
8415 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8417 if (instr
->op
== nir_texop_samples_identical
)
8418 resource
= fmask_ptr
;
8420 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8421 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8422 instr
->op
!= nir_texop_txs
&&
8423 instr
->op
!= nir_texop_fragment_fetch
&&
8424 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8425 assert(has_sample_index
);
8426 Operand
op(sample_index
);
8427 if (sample_index_cv
)
8428 op
= Operand(sample_index_cv
->u32
);
8429 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8432 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8433 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8434 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8435 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8440 /* Build tex instruction */
8441 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8442 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8443 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8445 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8448 /* gather4 selects the component by dmask and always returns vec4 */
8449 if (instr
->op
== nir_texop_tg4
) {
8450 assert(instr
->dest
.ssa
.num_components
== 4);
8451 if (instr
->is_shadow
)
8454 dmask
= 1 << instr
->component
;
8455 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8456 tmp_dst
= bld
.tmp(v4
);
8457 } else if (instr
->op
== nir_texop_samples_identical
) {
8458 tmp_dst
= bld
.tmp(v1
);
8459 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8460 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8463 aco_ptr
<MIMG_instruction
> tex
;
8464 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8466 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8468 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8469 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8472 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8473 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8475 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8476 tex
->operands
[0] = Operand(resource
);
8477 tex
->operands
[1] = Operand(s4
); /* no sampler */
8478 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8479 if (ctx
->options
->chip_class
== GFX9
&&
8480 instr
->op
== nir_texop_txs
&&
8481 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8483 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8484 } else if (instr
->op
== nir_texop_query_levels
) {
8485 tex
->dmask
= 1 << 3;
8490 tex
->definitions
[0] = Definition(tmp_dst
);
8492 tex
->can_reorder
= true;
8493 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8496 /* divide 3rd value by 6 by multiplying with magic number */
8497 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8498 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8499 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8500 assert(instr
->dest
.ssa
.num_components
== 3);
8501 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8502 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8503 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8504 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8509 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8513 Temp tg4_compare_cube_wa64
= Temp();
8515 if (tg4_integer_workarounds
) {
8516 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8517 tex
->operands
[0] = Operand(resource
);
8518 tex
->operands
[1] = Operand(s4
); /* no sampler */
8519 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8523 Temp size
= bld
.tmp(v2
);
8524 tex
->definitions
[0] = Definition(size
);
8525 tex
->can_reorder
= true;
8526 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8527 emit_split_vector(ctx
, size
, size
.size());
8530 for (unsigned i
= 0; i
< 2; i
++) {
8531 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8532 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8533 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8534 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8537 Temp new_coords
[2] = {
8538 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8539 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8542 if (tg4_integer_cube_workaround
) {
8543 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8544 Temp desc
[resource
.size()];
8545 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8546 Format::PSEUDO
, 1, resource
.size())};
8547 split
->operands
[0] = Operand(resource
);
8548 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8549 desc
[i
] = bld
.tmp(s1
);
8550 split
->definitions
[i
] = Definition(desc
[i
]);
8552 ctx
->block
->instructions
.emplace_back(std::move(split
));
8554 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8555 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8556 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8559 if (stype
== GLSL_TYPE_UINT
) {
8560 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8561 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8562 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8563 bld
.scc(compare_cube_wa
));
8565 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8566 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8567 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8568 bld
.scc(compare_cube_wa
));
8570 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8571 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8573 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8575 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8576 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8577 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8579 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8580 Format::PSEUDO
, resource
.size(), 1)};
8581 for (unsigned i
= 0; i
< resource
.size(); i
++)
8582 vec
->operands
[i
] = Operand(desc
[i
]);
8583 resource
= bld
.tmp(resource
.regClass());
8584 vec
->definitions
[0] = Definition(resource
);
8585 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8587 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8588 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8589 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8590 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8592 coords
[0] = new_coords
[0];
8593 coords
[1] = new_coords
[1];
8596 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8597 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8599 assert(coords
.size() == 1);
8600 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8604 op
= aco_opcode::buffer_load_format_x
; break;
8606 op
= aco_opcode::buffer_load_format_xy
; break;
8608 op
= aco_opcode::buffer_load_format_xyz
; break;
8610 op
= aco_opcode::buffer_load_format_xyzw
; break;
8612 unreachable("Tex instruction loads more than 4 components.");
8615 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8616 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8619 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8621 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8622 mubuf
->operands
[0] = Operand(resource
);
8623 mubuf
->operands
[1] = Operand(coords
[0]);
8624 mubuf
->operands
[2] = Operand((uint32_t) 0);
8625 mubuf
->definitions
[0] = Definition(tmp_dst
);
8626 mubuf
->idxen
= true;
8627 mubuf
->can_reorder
= true;
8628 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8630 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8634 /* gather MIMG address components */
8635 std::vector
<Temp
> args
;
8637 args
.emplace_back(offset
);
8639 args
.emplace_back(bias
);
8641 args
.emplace_back(compare
);
8643 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8645 args
.insert(args
.end(), coords
.begin(), coords
.end());
8646 if (has_sample_index
)
8647 args
.emplace_back(sample_index
);
8649 args
.emplace_back(lod
);
8651 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8652 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8653 vec
->definitions
[0] = Definition(arg
);
8654 for (unsigned i
= 0; i
< args
.size(); i
++)
8655 vec
->operands
[i
] = Operand(args
[i
]);
8656 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8659 if (instr
->op
== nir_texop_txf
||
8660 instr
->op
== nir_texop_txf_ms
||
8661 instr
->op
== nir_texop_samples_identical
||
8662 instr
->op
== nir_texop_fragment_fetch
||
8663 instr
->op
== nir_texop_fragment_mask_fetch
) {
8664 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8665 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8666 tex
->operands
[0] = Operand(resource
);
8667 tex
->operands
[1] = Operand(s4
); /* no sampler */
8668 tex
->operands
[2] = Operand(arg
);
8673 tex
->definitions
[0] = Definition(tmp_dst
);
8674 tex
->can_reorder
= true;
8675 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8677 if (instr
->op
== nir_texop_samples_identical
) {
8678 assert(dmask
== 1 && dst
.regClass() == v1
);
8679 assert(dst
.id() != tmp_dst
.id());
8681 Temp tmp
= bld
.tmp(bld
.lm
);
8682 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8683 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8686 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8691 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8692 aco_opcode opcode
= aco_opcode::image_sample
;
8693 if (has_offset
) { /* image_sample_*_o */
8695 opcode
= aco_opcode::image_sample_c_o
;
8697 opcode
= aco_opcode::image_sample_c_d_o
;
8699 opcode
= aco_opcode::image_sample_c_b_o
;
8701 opcode
= aco_opcode::image_sample_c_lz_o
;
8703 opcode
= aco_opcode::image_sample_c_l_o
;
8705 opcode
= aco_opcode::image_sample_o
;
8707 opcode
= aco_opcode::image_sample_d_o
;
8709 opcode
= aco_opcode::image_sample_b_o
;
8711 opcode
= aco_opcode::image_sample_lz_o
;
8713 opcode
= aco_opcode::image_sample_l_o
;
8715 } else { /* no offset */
8717 opcode
= aco_opcode::image_sample_c
;
8719 opcode
= aco_opcode::image_sample_c_d
;
8721 opcode
= aco_opcode::image_sample_c_b
;
8723 opcode
= aco_opcode::image_sample_c_lz
;
8725 opcode
= aco_opcode::image_sample_c_l
;
8727 opcode
= aco_opcode::image_sample
;
8729 opcode
= aco_opcode::image_sample_d
;
8731 opcode
= aco_opcode::image_sample_b
;
8733 opcode
= aco_opcode::image_sample_lz
;
8735 opcode
= aco_opcode::image_sample_l
;
8739 if (instr
->op
== nir_texop_tg4
) {
8741 opcode
= aco_opcode::image_gather4_lz_o
;
8743 opcode
= aco_opcode::image_gather4_c_lz_o
;
8745 opcode
= aco_opcode::image_gather4_lz
;
8747 opcode
= aco_opcode::image_gather4_c_lz
;
8749 } else if (instr
->op
== nir_texop_lod
) {
8750 opcode
= aco_opcode::image_get_lod
;
8753 /* we don't need the bias, sample index, compare value or offset to be
8754 * computed in WQM but if the p_create_vector copies the coordinates, then it
8755 * needs to be in WQM */
8756 if (ctx
->stage
== fragment_fs
&&
8757 !has_derivs
&& !has_lod
&& !level_zero
&&
8758 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8759 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8760 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8762 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8763 tex
->operands
[0] = Operand(resource
);
8764 tex
->operands
[1] = Operand(sampler
);
8765 tex
->operands
[2] = Operand(arg
);
8769 tex
->definitions
[0] = Definition(tmp_dst
);
8770 tex
->can_reorder
= true;
8771 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8773 if (tg4_integer_cube_workaround
) {
8774 assert(tmp_dst
.id() != dst
.id());
8775 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8777 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8779 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8780 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8782 if (stype
== GLSL_TYPE_UINT
)
8783 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8785 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8786 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8788 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8789 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8790 val
[0], val
[1], val
[2], val
[3]);
8792 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8793 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8798 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8800 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8801 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8802 return Operand(tmp
.regClass());
8804 return Operand(tmp
);
8807 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8809 aco_ptr
<Pseudo_instruction
> phi
;
8810 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8811 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8813 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8814 logical
|= ctx
->block
->kind
& block_kind_merge
;
8815 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8817 /* we want a sorted list of sources, since the predecessor list is also sorted */
8818 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8819 nir_foreach_phi_src(src
, instr
)
8820 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8822 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8823 unsigned num_operands
= 0;
8824 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8825 unsigned num_defined
= 0;
8826 unsigned cur_pred_idx
= 0;
8827 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8828 if (cur_pred_idx
< preds
.size()) {
8829 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8830 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8831 unsigned skipped
= 0;
8832 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8834 if (cur_pred_idx
+ skipped
< preds
.size()) {
8835 for (unsigned i
= 0; i
< skipped
; i
++)
8836 operands
[num_operands
++] = Operand(dst
.regClass());
8837 cur_pred_idx
+= skipped
;
8842 /* Handle missing predecessors at the end. This shouldn't happen with loop
8843 * headers and we can't ignore these sources for loop header phis. */
8844 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8847 Operand op
= get_phi_operand(ctx
, src
.second
);
8848 operands
[num_operands
++] = op
;
8849 num_defined
+= !op
.isUndefined();
8851 /* handle block_kind_continue_or_break at loop exit blocks */
8852 while (cur_pred_idx
++ < preds
.size())
8853 operands
[num_operands
++] = Operand(dst
.regClass());
8855 /* If the loop ends with a break, still add a linear continue edge in case
8856 * that break is divergent or continue_or_break is used. We'll either remove
8857 * this operand later in visit_loop() if it's not necessary or replace the
8858 * undef with something correct. */
8859 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8860 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8861 nir_block
*last
= nir_loop_last_block(loop
);
8862 if (last
->successors
[0] != instr
->instr
.block
)
8863 operands
[num_operands
++] = Operand(RegClass());
8866 if (num_defined
== 0) {
8867 Builder
bld(ctx
->program
, ctx
->block
);
8868 if (dst
.regClass() == s1
) {
8869 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8870 } else if (dst
.regClass() == v1
) {
8871 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8873 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8874 for (unsigned i
= 0; i
< dst
.size(); i
++)
8875 vec
->operands
[i
] = Operand(0u);
8876 vec
->definitions
[0] = Definition(dst
);
8877 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8882 /* we can use a linear phi in some cases if one src is undef */
8883 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8884 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8886 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8887 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8888 assert(invert
->kind
& block_kind_invert
);
8890 unsigned then_block
= invert
->linear_preds
[0];
8892 Block
* insert_block
= NULL
;
8893 for (unsigned i
= 0; i
< num_operands
; i
++) {
8894 Operand op
= operands
[i
];
8895 if (op
.isUndefined())
8897 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8898 phi
->operands
[0] = op
;
8901 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8902 phi
->operands
[1] = Operand(dst
.regClass());
8903 phi
->definitions
[0] = Definition(dst
);
8904 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8908 /* try to scalarize vector phis */
8909 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8910 // TODO: scalarize linear phis on divergent ifs
8911 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8912 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8913 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8914 Operand src
= operands
[i
];
8915 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8916 can_scalarize
= false;
8918 if (can_scalarize
) {
8919 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8920 assert(dst
.size() % num_components
== 0);
8921 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8923 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8924 for (unsigned k
= 0; k
< num_components
; k
++) {
8925 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8926 for (unsigned i
= 0; i
< num_operands
; i
++) {
8927 Operand src
= operands
[i
];
8928 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8930 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8931 phi
->definitions
[0] = Definition(phi_dst
);
8932 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8933 new_vec
[k
] = phi_dst
;
8934 vec
->operands
[k
] = Operand(phi_dst
);
8936 vec
->definitions
[0] = Definition(dst
);
8937 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8938 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8943 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8944 for (unsigned i
= 0; i
< num_operands
; i
++)
8945 phi
->operands
[i
] = operands
[i
];
8946 phi
->definitions
[0] = Definition(dst
);
8947 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8951 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8953 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8955 assert(dst
.type() == RegType::sgpr
);
8957 if (dst
.size() == 1) {
8958 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8960 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8961 for (unsigned i
= 0; i
< dst
.size(); i
++)
8962 vec
->operands
[i
] = Operand(0u);
8963 vec
->definitions
[0] = Definition(dst
);
8964 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8968 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8970 Builder
bld(ctx
->program
, ctx
->block
);
8971 Block
*logical_target
;
8972 append_logical_end(ctx
->block
);
8973 unsigned idx
= ctx
->block
->index
;
8975 switch (instr
->type
) {
8976 case nir_jump_break
:
8977 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8978 add_logical_edge(idx
, logical_target
);
8979 ctx
->block
->kind
|= block_kind_break
;
8981 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8982 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8983 /* uniform break - directly jump out of the loop */
8984 ctx
->block
->kind
|= block_kind_uniform
;
8985 ctx
->cf_info
.has_branch
= true;
8986 bld
.branch(aco_opcode::p_branch
);
8987 add_linear_edge(idx
, logical_target
);
8990 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8991 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8993 case nir_jump_continue
:
8994 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8995 add_logical_edge(idx
, logical_target
);
8996 ctx
->block
->kind
|= block_kind_continue
;
8998 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8999 /* for potential uniform breaks after this continue,
9000 we must ensure that they are handled correctly */
9001 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9002 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9003 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9005 /* uniform continue - directly jump to the loop header */
9006 ctx
->block
->kind
|= block_kind_uniform
;
9007 ctx
->cf_info
.has_branch
= true;
9008 bld
.branch(aco_opcode::p_branch
);
9009 add_linear_edge(idx
, logical_target
);
9014 fprintf(stderr
, "Unknown NIR jump instr: ");
9015 nir_print_instr(&instr
->instr
, stderr
);
9016 fprintf(stderr
, "\n");
9020 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9021 ctx
->cf_info
.exec_potentially_empty_break
= true;
9022 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9025 /* remove critical edges from linear CFG */
9026 bld
.branch(aco_opcode::p_branch
);
9027 Block
* break_block
= ctx
->program
->create_and_insert_block();
9028 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9029 break_block
->kind
|= block_kind_uniform
;
9030 add_linear_edge(idx
, break_block
);
9031 /* the loop_header pointer might be invalidated by this point */
9032 if (instr
->type
== nir_jump_continue
)
9033 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9034 add_linear_edge(break_block
->index
, logical_target
);
9035 bld
.reset(break_block
);
9036 bld
.branch(aco_opcode::p_branch
);
9038 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9039 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9040 add_linear_edge(idx
, continue_block
);
9041 append_logical_start(continue_block
);
9042 ctx
->block
= continue_block
;
9046 void visit_block(isel_context
*ctx
, nir_block
*block
)
9048 nir_foreach_instr(instr
, block
) {
9049 switch (instr
->type
) {
9050 case nir_instr_type_alu
:
9051 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9053 case nir_instr_type_load_const
:
9054 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9056 case nir_instr_type_intrinsic
:
9057 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9059 case nir_instr_type_tex
:
9060 visit_tex(ctx
, nir_instr_as_tex(instr
));
9062 case nir_instr_type_phi
:
9063 visit_phi(ctx
, nir_instr_as_phi(instr
));
9065 case nir_instr_type_ssa_undef
:
9066 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9068 case nir_instr_type_deref
:
9070 case nir_instr_type_jump
:
9071 visit_jump(ctx
, nir_instr_as_jump(instr
));
9074 fprintf(stderr
, "Unknown NIR instr type: ");
9075 nir_print_instr(instr
, stderr
);
9076 fprintf(stderr
, "\n");
9081 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9082 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9087 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9088 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9090 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9091 RegClass rc
= vals
[0].regClass();
9093 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9095 unsigned next_pred
= 1;
9097 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9098 Block
& block
= ctx
->program
->blocks
[idx
];
9099 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9100 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9104 if (block
.kind
& block_kind_continue
) {
9105 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9110 bool all_same
= true;
9111 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9112 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9116 val
= vals
[block
.linear_preds
[0] - first
];
9118 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9119 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9120 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9121 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9122 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9123 phi
->definitions
[0] = Definition(val
.getTemp());
9124 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9126 vals
[idx
- first
] = val
;
9129 return vals
[last
- first
];
9132 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9134 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9135 append_logical_end(ctx
->block
);
9136 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9137 Builder
bld(ctx
->program
, ctx
->block
);
9138 bld
.branch(aco_opcode::p_branch
);
9139 unsigned loop_preheader_idx
= ctx
->block
->index
;
9141 Block loop_exit
= Block();
9142 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9143 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9145 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9146 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9147 loop_header
->kind
|= block_kind_loop_header
;
9148 add_edge(loop_preheader_idx
, loop_header
);
9149 ctx
->block
= loop_header
;
9151 /* emit loop body */
9152 unsigned loop_header_idx
= loop_header
->index
;
9153 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9154 append_logical_start(ctx
->block
);
9155 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9157 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9158 if (!ctx
->cf_info
.has_branch
) {
9159 append_logical_end(ctx
->block
);
9160 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9161 /* Discards can result in code running with an empty exec mask.
9162 * This would result in divergent breaks not ever being taken. As a
9163 * workaround, break the loop when the loop mask is empty instead of
9164 * always continuing. */
9165 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9166 unsigned block_idx
= ctx
->block
->index
;
9168 /* create helper blocks to avoid critical edges */
9169 Block
*break_block
= ctx
->program
->create_and_insert_block();
9170 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9171 break_block
->kind
= block_kind_uniform
;
9172 bld
.reset(break_block
);
9173 bld
.branch(aco_opcode::p_branch
);
9174 add_linear_edge(block_idx
, break_block
);
9175 add_linear_edge(break_block
->index
, &loop_exit
);
9177 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9178 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9179 continue_block
->kind
= block_kind_uniform
;
9180 bld
.reset(continue_block
);
9181 bld
.branch(aco_opcode::p_branch
);
9182 add_linear_edge(block_idx
, continue_block
);
9183 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9185 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9186 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9187 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9189 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9190 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9191 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9193 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9196 bld
.reset(ctx
->block
);
9197 bld
.branch(aco_opcode::p_branch
);
9200 /* Fixup phis in loop header from unreachable blocks.
9201 * has_branch/has_divergent_branch also indicates if the loop ends with a
9202 * break/continue instruction, but we don't emit those if unreachable=true */
9204 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9205 bool linear
= ctx
->cf_info
.has_branch
;
9206 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9207 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9208 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9209 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9210 /* the last operand should be the one that needs to be removed */
9211 instr
->operands
.pop_back();
9212 } else if (!is_phi(instr
)) {
9218 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9219 * and the previous one shouldn't both happen at once because a break in the
9220 * merge block would get CSE'd */
9221 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9222 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9223 Operand vals
[num_vals
];
9224 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9225 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9226 if (ctx
->cf_info
.has_branch
)
9227 instr
->operands
.pop_back();
9229 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9230 } else if (!is_phi(instr
)) {
9236 ctx
->cf_info
.has_branch
= false;
9238 // TODO: if the loop has not a single exit, we must add one °°
9239 /* emit loop successor block */
9240 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9241 append_logical_start(ctx
->block
);
9244 // TODO: check if it is beneficial to not branch on continues
9245 /* trim linear phis in loop header */
9246 for (auto&& instr
: loop_entry
->instructions
) {
9247 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9248 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9249 new_phi
->definitions
[0] = instr
->definitions
[0];
9250 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9251 new_phi
->operands
[i
] = instr
->operands
[i
];
9252 /* check that the remaining operands are all the same */
9253 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9254 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9255 instr
.swap(new_phi
);
9256 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9265 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9269 append_logical_end(ctx
->block
);
9270 ctx
->block
->kind
|= block_kind_branch
;
9272 /* branch to linear then block */
9273 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9274 aco_ptr
<Pseudo_branch_instruction
> branch
;
9275 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9276 branch
->operands
[0] = Operand(cond
);
9277 ctx
->block
->instructions
.push_back(std::move(branch
));
9279 ic
->BB_if_idx
= ctx
->block
->index
;
9280 ic
->BB_invert
= Block();
9281 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9282 /* Invert blocks are intentionally not marked as top level because they
9283 * are not part of the logical cfg. */
9284 ic
->BB_invert
.kind
|= block_kind_invert
;
9285 ic
->BB_endif
= Block();
9286 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9287 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9289 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9290 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9291 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9292 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9293 ctx
->cf_info
.parent_if
.is_divergent
= true;
9295 /* divergent branches use cbranch_execz */
9296 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9297 ctx
->cf_info
.exec_potentially_empty_break
= false;
9298 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9300 /** emit logical then block */
9301 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9302 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9303 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9304 ctx
->block
= BB_then_logical
;
9305 append_logical_start(BB_then_logical
);
9308 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9310 Block
*BB_then_logical
= ctx
->block
;
9311 append_logical_end(BB_then_logical
);
9312 /* branch from logical then block to invert block */
9313 aco_ptr
<Pseudo_branch_instruction
> branch
;
9314 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9315 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9316 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9317 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9318 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9319 BB_then_logical
->kind
|= block_kind_uniform
;
9320 assert(!ctx
->cf_info
.has_branch
);
9321 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9322 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9324 /** emit linear then block */
9325 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9326 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9327 BB_then_linear
->kind
|= block_kind_uniform
;
9328 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9329 /* branch from linear then block to invert block */
9330 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9331 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9332 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9334 /** emit invert merge block */
9335 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9336 ic
->invert_idx
= ctx
->block
->index
;
9338 /* branch to linear else block (skip else) */
9339 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9340 branch
->operands
[0] = Operand(ic
->cond
);
9341 ctx
->block
->instructions
.push_back(std::move(branch
));
9343 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9344 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9345 ic
->exec_potentially_empty_break_depth_old
=
9346 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9347 /* divergent branches use cbranch_execz */
9348 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9349 ctx
->cf_info
.exec_potentially_empty_break
= false;
9350 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9352 /** emit logical else block */
9353 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9354 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9355 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9356 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9357 ctx
->block
= BB_else_logical
;
9358 append_logical_start(BB_else_logical
);
9361 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9363 Block
*BB_else_logical
= ctx
->block
;
9364 append_logical_end(BB_else_logical
);
9366 /* branch from logical else block to endif block */
9367 aco_ptr
<Pseudo_branch_instruction
> branch
;
9368 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9369 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9370 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9371 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9372 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9373 BB_else_logical
->kind
|= block_kind_uniform
;
9375 assert(!ctx
->cf_info
.has_branch
);
9376 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9379 /** emit linear else block */
9380 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9381 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9382 BB_else_linear
->kind
|= block_kind_uniform
;
9383 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9385 /* branch from linear else block to endif block */
9386 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9387 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9388 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9391 /** emit endif merge block */
9392 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9393 append_logical_start(ctx
->block
);
9396 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9397 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9398 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9399 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9400 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9401 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9402 !ctx
->cf_info
.parent_if
.is_divergent
) {
9403 ctx
->cf_info
.exec_potentially_empty_break
= false;
9404 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9406 /* uniform control flow never has an empty exec-mask */
9407 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9408 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9409 ctx
->cf_info
.exec_potentially_empty_break
= false;
9410 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9414 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9416 assert(cond
.regClass() == s1
);
9418 append_logical_end(ctx
->block
);
9419 ctx
->block
->kind
|= block_kind_uniform
;
9421 aco_ptr
<Pseudo_branch_instruction
> branch
;
9422 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9423 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9424 branch
->operands
[0] = Operand(cond
);
9425 branch
->operands
[0].setFixed(scc
);
9426 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9428 ic
->BB_if_idx
= ctx
->block
->index
;
9429 ic
->BB_endif
= Block();
9430 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9431 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9433 ctx
->cf_info
.has_branch
= false;
9434 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9436 /** emit then block */
9437 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9438 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9439 add_edge(ic
->BB_if_idx
, BB_then
);
9440 append_logical_start(BB_then
);
9441 ctx
->block
= BB_then
;
9444 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9446 Block
*BB_then
= ctx
->block
;
9448 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9449 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9451 if (!ic
->uniform_has_then_branch
) {
9452 append_logical_end(BB_then
);
9453 /* branch from then block to endif block */
9454 aco_ptr
<Pseudo_branch_instruction
> branch
;
9455 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9456 BB_then
->instructions
.emplace_back(std::move(branch
));
9457 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9458 if (!ic
->then_branch_divergent
)
9459 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9460 BB_then
->kind
|= block_kind_uniform
;
9463 ctx
->cf_info
.has_branch
= false;
9464 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9466 /** emit else block */
9467 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9468 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9469 add_edge(ic
->BB_if_idx
, BB_else
);
9470 append_logical_start(BB_else
);
9471 ctx
->block
= BB_else
;
9474 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9476 Block
*BB_else
= ctx
->block
;
9478 if (!ctx
->cf_info
.has_branch
) {
9479 append_logical_end(BB_else
);
9480 /* branch from then block to endif block */
9481 aco_ptr
<Pseudo_branch_instruction
> branch
;
9482 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9483 BB_else
->instructions
.emplace_back(std::move(branch
));
9484 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9485 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9486 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9487 BB_else
->kind
|= block_kind_uniform
;
9490 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9491 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9493 /** emit endif merge block */
9494 if (!ctx
->cf_info
.has_branch
) {
9495 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9496 append_logical_start(ctx
->block
);
9500 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9502 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9503 Builder
bld(ctx
->program
, ctx
->block
);
9504 aco_ptr
<Pseudo_branch_instruction
> branch
;
9507 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9509 * Uniform conditionals are represented in the following way*) :
9511 * The linear and logical CFG:
9514 * BB_THEN (logical) BB_ELSE (logical)
9518 * *) Exceptions may be due to break and continue statements within loops
9519 * If a break/continue happens within uniform control flow, it branches
9520 * to the loop exit/entry block. Otherwise, it branches to the next
9524 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9525 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9526 cond
= bool_to_scalar_condition(ctx
, cond
);
9528 begin_uniform_if_then(ctx
, &ic
, cond
);
9529 visit_cf_list(ctx
, &if_stmt
->then_list
);
9531 begin_uniform_if_else(ctx
, &ic
);
9532 visit_cf_list(ctx
, &if_stmt
->else_list
);
9534 end_uniform_if(ctx
, &ic
);
9536 return !ctx
->cf_info
.has_branch
;
9537 } else { /* non-uniform condition */
9539 * To maintain a logical and linear CFG without critical edges,
9540 * non-uniform conditionals are represented in the following way*) :
9545 * BB_THEN (logical) BB_THEN (linear)
9547 * BB_INVERT (linear)
9549 * BB_ELSE (logical) BB_ELSE (linear)
9556 * BB_THEN (logical) BB_ELSE (logical)
9560 * *) Exceptions may be due to break and continue statements within loops
9563 begin_divergent_if_then(ctx
, &ic
, cond
);
9564 visit_cf_list(ctx
, &if_stmt
->then_list
);
9566 begin_divergent_if_else(ctx
, &ic
);
9567 visit_cf_list(ctx
, &if_stmt
->else_list
);
9569 end_divergent_if(ctx
, &ic
);
9575 static bool visit_cf_list(isel_context
*ctx
,
9576 struct exec_list
*list
)
9578 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9579 switch (node
->type
) {
9580 case nir_cf_node_block
:
9581 visit_block(ctx
, nir_cf_node_as_block(node
));
9583 case nir_cf_node_if
:
9584 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9587 case nir_cf_node_loop
:
9588 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9591 unreachable("unimplemented cf list type");
9597 static void create_null_export(isel_context
*ctx
)
9599 /* Some shader stages always need to have exports.
9600 * So when there is none, we need to add a null export.
9603 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9604 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9605 Builder
bld(ctx
->program
, ctx
->block
);
9606 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9607 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9610 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9612 assert(ctx
->stage
== vertex_vs
||
9613 ctx
->stage
== tess_eval_vs
||
9614 ctx
->stage
== gs_copy_vs
||
9615 ctx
->stage
== ngg_vertex_gs
||
9616 ctx
->stage
== ngg_tess_eval_gs
);
9618 int offset
= (ctx
->stage
& sw_tes
)
9619 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9620 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9621 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9622 if (!is_pos
&& !mask
)
9624 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9626 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9627 exp
->enabled_mask
= mask
;
9628 for (unsigned i
= 0; i
< 4; ++i
) {
9629 if (mask
& (1 << i
))
9630 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9632 exp
->operands
[i
] = Operand(v1
);
9634 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9635 * Setting valid_mask=1 prevents it and has no other effect.
9637 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9639 exp
->compressed
= false;
9641 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9643 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9644 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9649 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9651 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9652 exp
->enabled_mask
= 0;
9653 for (unsigned i
= 0; i
< 4; ++i
)
9654 exp
->operands
[i
] = Operand(v1
);
9655 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9656 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9657 exp
->enabled_mask
|= 0x1;
9659 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9660 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9661 exp
->enabled_mask
|= 0x4;
9663 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9664 if (ctx
->options
->chip_class
< GFX9
) {
9665 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9666 exp
->enabled_mask
|= 0x8;
9668 Builder
bld(ctx
->program
, ctx
->block
);
9670 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9671 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9672 if (exp
->operands
[2].isTemp())
9673 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9675 exp
->operands
[2] = Operand(out
);
9676 exp
->enabled_mask
|= 0x4;
9679 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9681 exp
->compressed
= false;
9682 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9683 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9686 static void create_export_phis(isel_context
*ctx
)
9688 /* Used when exports are needed, but the output temps are defined in a preceding block.
9689 * This function will set up phis in order to access the outputs in the next block.
9692 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9693 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9694 ctx
->block
->instructions
.pop_back();
9696 Builder
bld(ctx
->program
, ctx
->block
);
9698 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9699 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9700 for (unsigned i
= 0; i
< 4; ++i
) {
9701 if (!(mask
& (1 << i
)))
9704 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9705 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9706 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9710 bld
.insert(std::move(logical_start
));
9713 static void create_vs_exports(isel_context
*ctx
)
9715 assert(ctx
->stage
== vertex_vs
||
9716 ctx
->stage
== tess_eval_vs
||
9717 ctx
->stage
== gs_copy_vs
||
9718 ctx
->stage
== ngg_vertex_gs
||
9719 ctx
->stage
== ngg_tess_eval_gs
);
9721 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9722 ? &ctx
->program
->info
->tes
.outinfo
9723 : &ctx
->program
->info
->vs
.outinfo
;
9725 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9726 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9727 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9730 if (ctx
->options
->key
.has_multiview_view_index
) {
9731 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9732 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9735 /* the order these position exports are created is important */
9737 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9738 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9739 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9740 exported_pos
= true;
9742 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9743 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9744 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9745 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9747 if (ctx
->export_clip_dists
) {
9748 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9749 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9750 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9751 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9754 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9755 if (i
< VARYING_SLOT_VAR0
&&
9756 i
!= VARYING_SLOT_LAYER
&&
9757 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9758 i
!= VARYING_SLOT_VIEWPORT
)
9761 export_vs_varying(ctx
, i
, false, NULL
);
9765 create_null_export(ctx
);
9768 static bool export_fs_mrt_z(isel_context
*ctx
)
9770 Builder
bld(ctx
->program
, ctx
->block
);
9771 unsigned enabled_channels
= 0;
9775 for (unsigned i
= 0; i
< 4; ++i
) {
9776 values
[i
] = Operand(v1
);
9779 /* Both stencil and sample mask only need 16-bits. */
9780 if (!ctx
->program
->info
->ps
.writes_z
&&
9781 (ctx
->program
->info
->ps
.writes_stencil
||
9782 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9783 compr
= true; /* COMPR flag */
9785 if (ctx
->program
->info
->ps
.writes_stencil
) {
9786 /* Stencil should be in X[23:16]. */
9787 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9788 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9789 enabled_channels
|= 0x3;
9792 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9793 /* SampleMask should be in Y[15:0]. */
9794 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9795 enabled_channels
|= 0xc;
9798 if (ctx
->program
->info
->ps
.writes_z
) {
9799 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9800 enabled_channels
|= 0x1;
9803 if (ctx
->program
->info
->ps
.writes_stencil
) {
9804 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9805 enabled_channels
|= 0x2;
9808 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9809 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9810 enabled_channels
|= 0x4;
9814 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9815 * writemask component.
9817 if (ctx
->options
->chip_class
== GFX6
&&
9818 ctx
->options
->family
!= CHIP_OLAND
&&
9819 ctx
->options
->family
!= CHIP_HAINAN
) {
9820 enabled_channels
|= 0x1;
9823 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9824 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9829 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9831 Builder
bld(ctx
->program
, ctx
->block
);
9832 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9835 for (unsigned i
= 0; i
< 4; ++i
) {
9836 if (write_mask
& (1 << i
)) {
9837 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9839 values
[i
] = Operand(v1
);
9843 unsigned target
, col_format
;
9844 unsigned enabled_channels
= 0;
9845 aco_opcode compr_op
= (aco_opcode
)0;
9847 slot
-= FRAG_RESULT_DATA0
;
9848 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9849 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9851 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9852 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9856 case V_028714_SPI_SHADER_ZERO
:
9857 enabled_channels
= 0; /* writemask */
9858 target
= V_008DFC_SQ_EXP_NULL
;
9861 case V_028714_SPI_SHADER_32_R
:
9862 enabled_channels
= 1;
9865 case V_028714_SPI_SHADER_32_GR
:
9866 enabled_channels
= 0x3;
9869 case V_028714_SPI_SHADER_32_AR
:
9870 if (ctx
->options
->chip_class
>= GFX10
) {
9871 /* Special case: on GFX10, the outputs are different for 32_AR */
9872 enabled_channels
= 0x3;
9873 values
[1] = values
[3];
9874 values
[3] = Operand(v1
);
9876 enabled_channels
= 0x9;
9880 case V_028714_SPI_SHADER_FP16_ABGR
:
9881 enabled_channels
= 0x5;
9882 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9885 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9886 enabled_channels
= 0x5;
9887 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9890 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9891 enabled_channels
= 0x5;
9892 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9895 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9896 enabled_channels
= 0x5;
9897 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9898 if (is_int8
|| is_int10
) {
9900 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9901 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9903 for (unsigned i
= 0; i
< 4; i
++) {
9904 if ((write_mask
>> i
) & 1) {
9905 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9906 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9914 case V_028714_SPI_SHADER_SINT16_ABGR
:
9915 enabled_channels
= 0x5;
9916 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9917 if (is_int8
|| is_int10
) {
9919 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9920 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9921 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9922 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9924 for (unsigned i
= 0; i
< 4; i
++) {
9925 if ((write_mask
>> i
) & 1) {
9926 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9927 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9929 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9930 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9937 case V_028714_SPI_SHADER_32_ABGR
:
9938 enabled_channels
= 0xF;
9945 if (target
== V_008DFC_SQ_EXP_NULL
)
9948 if ((bool) compr_op
) {
9949 for (int i
= 0; i
< 2; i
++) {
9950 /* check if at least one of the values to be compressed is enabled */
9951 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9953 enabled_channels
|= enabled
<< (i
*2);
9954 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9955 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9956 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9958 values
[i
] = Operand(v1
);
9961 values
[2] = Operand(v1
);
9962 values
[3] = Operand(v1
);
9964 for (int i
= 0; i
< 4; i
++)
9965 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9968 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9969 enabled_channels
, target
, (bool) compr_op
);
9973 static void create_fs_exports(isel_context
*ctx
)
9975 bool exported
= false;
9977 /* Export depth, stencil and sample mask. */
9978 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9979 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9980 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9981 exported
|= export_fs_mrt_z(ctx
);
9983 /* Export all color render targets. */
9984 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9985 if (ctx
->outputs
.mask
[i
])
9986 exported
|= export_fs_mrt_color(ctx
, i
);
9989 create_null_export(ctx
);
9992 static void write_tcs_tess_factors(isel_context
*ctx
)
9994 unsigned outer_comps
;
9995 unsigned inner_comps
;
9997 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10014 Builder
bld(ctx
->program
, ctx
->block
);
10016 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10017 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10018 bld
.sopp(aco_opcode::s_barrier
);
10020 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10021 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10023 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10024 if_context ic_invocation_id_is_zero
;
10025 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10026 bld
.reset(ctx
->block
);
10028 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10030 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10031 unsigned stride
= inner_comps
+ outer_comps
;
10032 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10036 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10038 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10040 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10041 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10042 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10044 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10045 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10047 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10048 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10049 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10050 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10053 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10054 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10055 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10056 unsigned tf_const_offset
= 0;
10058 if (ctx
->program
->chip_class
<= GFX8
) {
10059 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10060 if_context ic_rel_patch_id_is_zero
;
10061 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10062 bld
.reset(ctx
->block
);
10064 /* Store the dynamic HS control word. */
10065 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10066 bld
.mubuf(aco_opcode::buffer_store_dword
,
10067 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10068 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10069 /* disable_wqm */ false, /* glc */ true);
10070 tf_const_offset
+= 4;
10072 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10073 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10074 bld
.reset(ctx
->block
);
10077 assert(stride
== 2 || stride
== 4 || stride
== 6);
10078 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10079 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10081 /* Store to offchip for TES to read - only if TES reads them */
10082 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10083 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10084 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10086 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10087 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10089 if (likely(inner_comps
)) {
10090 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10091 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10095 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10096 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10099 static void emit_stream_output(isel_context
*ctx
,
10100 Temp
const *so_buffers
,
10101 Temp
const *so_write_offset
,
10102 const struct radv_stream_output
*output
)
10104 unsigned num_comps
= util_bitcount(output
->component_mask
);
10105 unsigned writemask
= (1 << num_comps
) - 1;
10106 unsigned loc
= output
->location
;
10107 unsigned buf
= output
->buffer
;
10109 assert(num_comps
&& num_comps
<= 4);
10110 if (!num_comps
|| num_comps
> 4)
10113 unsigned start
= ffs(output
->component_mask
) - 1;
10116 bool all_undef
= true;
10117 assert(ctx
->stage
& hw_vs
);
10118 for (unsigned i
= 0; i
< num_comps
; i
++) {
10119 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10120 all_undef
= all_undef
&& !out
[i
].id();
10125 while (writemask
) {
10127 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10128 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10129 /* GFX6 doesn't support storing vec3, split it. */
10130 writemask
|= 1u << (start
+ 2);
10134 unsigned offset
= output
->offset
+ start
* 4;
10136 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10137 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10138 for (int i
= 0; i
< count
; ++i
)
10139 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10140 vec
->definitions
[0] = Definition(write_data
);
10141 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10146 opcode
= aco_opcode::buffer_store_dword
;
10149 opcode
= aco_opcode::buffer_store_dwordx2
;
10152 opcode
= aco_opcode::buffer_store_dwordx3
;
10155 opcode
= aco_opcode::buffer_store_dwordx4
;
10158 unreachable("Unsupported dword count.");
10161 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10162 store
->operands
[0] = Operand(so_buffers
[buf
]);
10163 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10164 store
->operands
[2] = Operand((uint32_t) 0);
10165 store
->operands
[3] = Operand(write_data
);
10166 if (offset
> 4095) {
10167 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10168 Builder
bld(ctx
->program
, ctx
->block
);
10169 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10171 store
->offset
= offset
;
10173 store
->offen
= true;
10175 store
->dlc
= false;
10177 store
->can_reorder
= true;
10178 ctx
->block
->instructions
.emplace_back(std::move(store
));
10182 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10184 Builder
bld(ctx
->program
, ctx
->block
);
10186 Temp so_buffers
[4];
10187 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10188 for (unsigned i
= 0; i
< 4; i
++) {
10189 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10193 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10194 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10197 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10198 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10200 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10202 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10205 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10207 bld
.reset(ctx
->block
);
10209 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10211 Temp so_write_offset
[4];
10213 for (unsigned i
= 0; i
< 4; i
++) {
10214 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10219 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10220 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10221 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10222 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10224 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10226 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10227 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10228 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10229 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10233 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10234 struct radv_stream_output
*output
=
10235 &ctx
->program
->info
->so
.outputs
[i
];
10236 if (stream
!= output
->stream
)
10239 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10242 begin_divergent_if_else(ctx
, &ic
);
10243 end_divergent_if(ctx
, &ic
);
10246 } /* end namespace */
10248 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10250 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10251 Builder
bld(ctx
->program
, ctx
->block
);
10252 constexpr unsigned hs_idx
= 1u;
10253 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10254 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10255 Operand((8u << 16) | (hs_idx
* 8u)));
10256 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10258 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10260 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10261 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10262 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10263 ls_has_nonzero_hs_threads
);
10264 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10265 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10266 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10267 ls_has_nonzero_hs_threads
);
10268 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10269 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10270 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10271 ls_has_nonzero_hs_threads
);
10273 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10274 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10275 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10278 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10280 /* Split all arguments except for the first (ring_offsets) and the last
10281 * (exec) so that the dead channels don't stay live throughout the program.
10283 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10284 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10285 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10286 startpgm
->definitions
[i
].regClass().size());
10291 void handle_bc_optimize(isel_context
*ctx
)
10293 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10294 Builder
bld(ctx
->program
, ctx
->block
);
10295 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10296 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10297 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10298 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10299 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10300 if (uses_center
&& uses_centroid
) {
10301 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10302 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10304 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10306 for (unsigned i
= 0; i
< 2; i
++) {
10307 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10308 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10309 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10310 persp_centroid
, persp_center
, sel
);
10312 ctx
->persp_centroid
= bld
.tmp(v2
);
10313 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10314 Operand(new_coord
[0]), Operand(new_coord
[1]));
10315 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10318 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10320 for (unsigned i
= 0; i
< 2; i
++) {
10321 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10322 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10323 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10324 linear_centroid
, linear_center
, sel
);
10326 ctx
->linear_centroid
= bld
.tmp(v2
);
10327 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10328 Operand(new_coord
[0]), Operand(new_coord
[1]));
10329 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10334 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10336 Program
*program
= ctx
->program
;
10338 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10340 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10341 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10342 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10343 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10344 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10346 program
->next_fp_mode
.must_flush_denorms32
=
10347 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10348 program
->next_fp_mode
.must_flush_denorms16_64
=
10349 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10350 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10352 program
->next_fp_mode
.care_about_round32
=
10353 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10355 program
->next_fp_mode
.care_about_round16_64
=
10356 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10357 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10359 /* default to preserving fp16 and fp64 denorms, since it's free */
10360 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10361 program
->next_fp_mode
.denorm16_64
= 0;
10363 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10365 /* preserving fp32 denorms is expensive, so only do it if asked */
10366 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10367 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10369 program
->next_fp_mode
.denorm32
= 0;
10371 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10372 program
->next_fp_mode
.round32
= fp_round_tz
;
10374 program
->next_fp_mode
.round32
= fp_round_ne
;
10376 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10377 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10379 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10381 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10384 void cleanup_cfg(Program
*program
)
10386 /* create linear_succs/logical_succs */
10387 for (Block
& BB
: program
->blocks
) {
10388 for (unsigned idx
: BB
.linear_preds
)
10389 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10390 for (unsigned idx
: BB
.logical_preds
)
10391 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10395 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10397 Builder
bld(ctx
->program
, ctx
->block
);
10399 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10400 Temp count
= i
== 0
10401 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10402 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10403 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10405 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10408 if (ctx
->program
->wave_size
== 64) {
10409 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10410 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10411 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10413 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10414 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10420 bool ngg_early_prim_export(isel_context
*ctx
)
10422 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10426 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10428 Builder
bld(ctx
->program
, ctx
->block
);
10430 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10431 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10433 /* Get the id of the current wave within the threadgroup (workgroup) */
10434 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10435 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10437 /* Execute the following code only on the first wave (wave id 0),
10438 * use the SCC def to tell if the wave id is zero or not.
10440 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10442 begin_uniform_if_then(ctx
, &ic
, cond
);
10443 begin_uniform_if_else(ctx
, &ic
);
10444 bld
.reset(ctx
->block
);
10446 /* Number of vertices output by VS/TES */
10447 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10448 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10449 /* Number of primitives output by VS/TES */
10450 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10451 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10453 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10454 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10455 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10457 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10458 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10460 end_uniform_if(ctx
, &ic
);
10462 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10463 bld
.reset(ctx
->block
);
10464 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10467 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10469 Builder
bld(ctx
->program
, ctx
->block
);
10471 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10472 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10475 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10478 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10479 assert(vtxindex
[i
].id());
10482 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10486 /* The initial edge flag is always false in tess eval shaders. */
10487 if (ctx
->stage
== ngg_vertex_gs
) {
10488 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10489 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10493 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10498 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10500 Builder
bld(ctx
->program
, ctx
->block
);
10501 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10503 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10504 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10505 false /* compressed */, true/* done */, false /* valid mask */);
10508 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10510 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10511 * These must always come before VS exports.
10513 * It is recommended to do these as early as possible. They can be at the beginning when
10514 * there is no SW GS and the shader doesn't write edge flags.
10518 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10519 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10521 Builder
bld(ctx
->program
, ctx
->block
);
10522 constexpr unsigned max_vertices_per_primitive
= 3;
10523 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10525 if (ctx
->stage
== ngg_vertex_gs
) {
10526 /* TODO: optimize for points & lines */
10527 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10528 if (ctx
->shader
->info
.tess
.point_mode
)
10529 num_vertices_per_primitive
= 1;
10530 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10531 num_vertices_per_primitive
= 2;
10533 unreachable("Unsupported NGG shader stage");
10536 Temp vtxindex
[max_vertices_per_primitive
];
10537 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10538 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10539 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10540 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10541 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10542 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10543 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10544 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10546 /* Export primitive data to the index buffer. */
10547 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10549 /* Export primitive ID. */
10550 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10551 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10552 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10553 Temp provoking_vtx_index
= vtxindex
[0];
10554 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10556 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10559 begin_divergent_if_else(ctx
, &ic
);
10560 end_divergent_if(ctx
, &ic
);
10563 void ngg_emit_nogs_output(isel_context
*ctx
)
10565 /* Emits NGG GS output, for stages that don't have SW GS. */
10568 Builder
bld(ctx
->program
, ctx
->block
);
10569 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10571 /* NGG streamout is currently disabled by default. */
10572 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10574 if (late_prim_export
) {
10575 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10576 create_export_phis(ctx
);
10577 /* Do what we need to do in the GS threads. */
10578 ngg_emit_nogs_gsthreads(ctx
);
10580 /* What comes next should be executed on ES threads. */
10581 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10582 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10583 bld
.reset(ctx
->block
);
10586 /* Export VS outputs */
10587 ctx
->block
->kind
|= block_kind_export_end
;
10588 create_vs_exports(ctx
);
10590 /* Export primitive ID */
10591 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10594 if (ctx
->stage
== ngg_vertex_gs
) {
10595 /* Wait for GS threads to store primitive ID in LDS. */
10596 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10597 bld
.sopp(aco_opcode::s_barrier
);
10599 /* Calculate LDS address where the GS threads stored the primitive ID. */
10600 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10601 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10602 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10603 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10604 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10605 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10607 /* Load primitive ID from LDS. */
10608 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10609 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10610 /* TES: Just use the patch ID as the primitive ID. */
10611 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10613 unreachable("unsupported NGG shader stage.");
10616 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10617 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10619 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10622 if (late_prim_export
) {
10623 begin_divergent_if_else(ctx
, &ic
);
10624 end_divergent_if(ctx
, &ic
);
10625 bld
.reset(ctx
->block
);
10629 void select_program(Program
*program
,
10630 unsigned shader_count
,
10631 struct nir_shader
*const *shaders
,
10632 ac_shader_config
* config
,
10633 struct radv_shader_args
*args
)
10635 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10636 if_context ic_merged_wave_info
;
10637 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10639 for (unsigned i
= 0; i
< shader_count
; i
++) {
10640 nir_shader
*nir
= shaders
[i
];
10641 init_context(&ctx
, nir
);
10643 setup_fp_mode(&ctx
, nir
);
10646 /* needs to be after init_context() for FS */
10647 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10648 append_logical_start(ctx
.block
);
10650 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10651 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10653 split_arguments(&ctx
, startpgm
);
10657 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10659 if (ngg_early_prim_export(&ctx
))
10660 ngg_emit_nogs_gsthreads(&ctx
);
10663 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10664 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10665 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10666 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10667 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10668 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10669 ctx
.stage
== tess_eval_geometry_gs
));
10671 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10672 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10673 if (check_merged_wave_info
) {
10674 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10675 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10679 Builder
bld(ctx
.program
, ctx
.block
);
10681 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10682 bld
.sopp(aco_opcode::s_barrier
);
10684 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10685 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10687 } else if (ctx
.stage
== geometry_gs
)
10688 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10690 if (ctx
.stage
== fragment_fs
)
10691 handle_bc_optimize(&ctx
);
10693 visit_cf_list(&ctx
, &func
->body
);
10695 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10696 emit_streamout(&ctx
, 0);
10698 if (ctx
.stage
& hw_vs
) {
10699 create_vs_exports(&ctx
);
10700 ctx
.block
->kind
|= block_kind_export_end
;
10701 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10702 ngg_emit_nogs_output(&ctx
);
10703 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10704 Builder
bld(ctx
.program
, ctx
.block
);
10705 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10706 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10707 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10708 write_tcs_tess_factors(&ctx
);
10711 if (ctx
.stage
== fragment_fs
) {
10712 create_fs_exports(&ctx
);
10713 ctx
.block
->kind
|= block_kind_export_end
;
10716 if (endif_merged_wave_info
) {
10717 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10718 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10721 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10722 ngg_emit_nogs_output(&ctx
);
10724 ralloc_free(ctx
.divergent_vals
);
10726 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10727 /* Outputs of the previous stage are inputs to the next stage */
10728 ctx
.inputs
= ctx
.outputs
;
10729 ctx
.outputs
= shader_io_state();
10733 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10735 append_logical_end(ctx
.block
);
10736 ctx
.block
->kind
|= block_kind_uniform
;
10737 Builder
bld(ctx
.program
, ctx
.block
);
10738 if (ctx
.program
->wb_smem_l1_on_end
)
10739 bld
.smem(aco_opcode::s_dcache_wb
, false);
10740 bld
.sopp(aco_opcode::s_endpgm
);
10742 cleanup_cfg(program
);
10745 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10746 ac_shader_config
* config
,
10747 struct radv_shader_args
*args
)
10749 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10751 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10752 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10753 program
->next_fp_mode
.must_flush_denorms32
= false;
10754 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10755 program
->next_fp_mode
.care_about_round32
= false;
10756 program
->next_fp_mode
.care_about_round16_64
= false;
10757 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10758 program
->next_fp_mode
.denorm32
= 0;
10759 program
->next_fp_mode
.round32
= fp_round_ne
;
10760 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10761 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10763 add_startpgm(&ctx
);
10764 append_logical_start(ctx
.block
);
10766 Builder
bld(ctx
.program
, ctx
.block
);
10768 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10770 Operand
stream_id(0u);
10771 if (args
->shader_info
->so
.num_outputs
)
10772 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10773 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10775 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10777 std::stack
<Block
> endif_blocks
;
10779 for (unsigned stream
= 0; stream
< 4; stream
++) {
10780 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10783 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10784 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10787 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10789 unsigned BB_if_idx
= ctx
.block
->index
;
10790 Block BB_endif
= Block();
10791 if (!stream_id
.isConstant()) {
10793 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10794 append_logical_end(ctx
.block
);
10795 ctx
.block
->kind
|= block_kind_uniform
;
10796 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10798 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10800 ctx
.block
= ctx
.program
->create_and_insert_block();
10801 add_edge(BB_if_idx
, ctx
.block
);
10802 bld
.reset(ctx
.block
);
10803 append_logical_start(ctx
.block
);
10806 unsigned offset
= 0;
10807 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10808 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10811 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10812 unsigned length
= util_last_bit(output_usage_mask
);
10813 for (unsigned j
= 0; j
< length
; ++j
) {
10814 if (!(output_usage_mask
& (1 << j
)))
10817 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10818 Temp voffset
= vtx_offset
;
10819 if (const_offset
>= 4096u) {
10820 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10821 const_offset
%= 4096u;
10824 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10825 mubuf
->definitions
[0] = bld
.def(v1
);
10826 mubuf
->operands
[0] = Operand(gsvs_ring
);
10827 mubuf
->operands
[1] = Operand(voffset
);
10828 mubuf
->operands
[2] = Operand(0u);
10829 mubuf
->offen
= true;
10830 mubuf
->offset
= const_offset
;
10833 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10834 mubuf
->barrier
= barrier_none
;
10835 mubuf
->can_reorder
= true;
10837 ctx
.outputs
.mask
[i
] |= 1 << j
;
10838 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10840 bld
.insert(std::move(mubuf
));
10846 if (args
->shader_info
->so
.num_outputs
) {
10847 emit_streamout(&ctx
, stream
);
10848 bld
.reset(ctx
.block
);
10852 create_vs_exports(&ctx
);
10853 ctx
.block
->kind
|= block_kind_export_end
;
10856 if (!stream_id
.isConstant()) {
10857 append_logical_end(ctx
.block
);
10859 /* branch from then block to endif block */
10860 bld
.branch(aco_opcode::p_branch
);
10861 add_edge(ctx
.block
->index
, &BB_endif
);
10862 ctx
.block
->kind
|= block_kind_uniform
;
10864 /* emit else block */
10865 ctx
.block
= ctx
.program
->create_and_insert_block();
10866 add_edge(BB_if_idx
, ctx
.block
);
10867 bld
.reset(ctx
.block
);
10868 append_logical_start(ctx
.block
);
10870 endif_blocks
.push(std::move(BB_endif
));
10874 while (!endif_blocks
.empty()) {
10875 Block BB_endif
= std::move(endif_blocks
.top());
10876 endif_blocks
.pop();
10878 Block
*BB_else
= ctx
.block
;
10880 append_logical_end(BB_else
);
10881 /* branch from else block to endif block */
10882 bld
.branch(aco_opcode::p_branch
);
10883 add_edge(BB_else
->index
, &BB_endif
);
10884 BB_else
->kind
|= block_kind_uniform
;
10886 /** emit endif merge block */
10887 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10888 bld
.reset(ctx
.block
);
10889 append_logical_start(ctx
.block
);
10892 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10894 append_logical_end(ctx
.block
);
10895 ctx
.block
->kind
|= block_kind_uniform
;
10896 bld
.sopp(aco_opcode::s_endpgm
);
10898 cleanup_cfg(program
);