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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
594 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
595 if (src1
.type() == RegType::sgpr
) {
596 if (commutative
&& src0
.type() == RegType::vgpr
) {
601 src1
= as_vgpr(ctx
, src1
);
605 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
606 assert(dst
.size() == 1);
607 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
608 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
610 bld
.vop2(op
, Definition(dst
), src0
, src1
);
614 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
615 bool flush_denorms
= false)
617 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
618 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
619 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
621 /* ensure that the instruction has at most 1 sgpr operand
622 * The optimizer will inline constants for us */
623 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
624 src0
= as_vgpr(ctx
, src0
);
625 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
626 src1
= as_vgpr(ctx
, src1
);
627 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
628 src2
= as_vgpr(ctx
, src2
);
630 Builder
bld(ctx
->program
, ctx
->block
);
631 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
632 assert(dst
.size() == 1);
633 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
634 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
636 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
640 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
642 Builder
bld(ctx
->program
, ctx
->block
);
643 if (dst
.type() == RegType::sgpr
)
644 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
645 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
647 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
650 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
652 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
653 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
654 assert(src0
.size() == src1
.size());
656 aco_ptr
<Instruction
> vopc
;
657 if (src1
.type() == RegType::sgpr
) {
658 if (src0
.type() == RegType::vgpr
) {
659 /* to swap the operands, we might also have to change the opcode */
661 case aco_opcode::v_cmp_lt_f16
:
662 op
= aco_opcode::v_cmp_gt_f16
;
664 case aco_opcode::v_cmp_ge_f16
:
665 op
= aco_opcode::v_cmp_le_f16
;
667 case aco_opcode::v_cmp_lt_i16
:
668 op
= aco_opcode::v_cmp_gt_i16
;
670 case aco_opcode::v_cmp_ge_i16
:
671 op
= aco_opcode::v_cmp_le_i16
;
673 case aco_opcode::v_cmp_lt_u16
:
674 op
= aco_opcode::v_cmp_gt_u16
;
676 case aco_opcode::v_cmp_ge_u16
:
677 op
= aco_opcode::v_cmp_le_u16
;
679 case aco_opcode::v_cmp_lt_f32
:
680 op
= aco_opcode::v_cmp_gt_f32
;
682 case aco_opcode::v_cmp_ge_f32
:
683 op
= aco_opcode::v_cmp_le_f32
;
685 case aco_opcode::v_cmp_lt_i32
:
686 op
= aco_opcode::v_cmp_gt_i32
;
688 case aco_opcode::v_cmp_ge_i32
:
689 op
= aco_opcode::v_cmp_le_i32
;
691 case aco_opcode::v_cmp_lt_u32
:
692 op
= aco_opcode::v_cmp_gt_u32
;
694 case aco_opcode::v_cmp_ge_u32
:
695 op
= aco_opcode::v_cmp_le_u32
;
697 case aco_opcode::v_cmp_lt_f64
:
698 op
= aco_opcode::v_cmp_gt_f64
;
700 case aco_opcode::v_cmp_ge_f64
:
701 op
= aco_opcode::v_cmp_le_f64
;
703 case aco_opcode::v_cmp_lt_i64
:
704 op
= aco_opcode::v_cmp_gt_i64
;
706 case aco_opcode::v_cmp_ge_i64
:
707 op
= aco_opcode::v_cmp_le_i64
;
709 case aco_opcode::v_cmp_lt_u64
:
710 op
= aco_opcode::v_cmp_gt_u64
;
712 case aco_opcode::v_cmp_ge_u64
:
713 op
= aco_opcode::v_cmp_le_u64
;
715 default: /* eq and ne are commutative */
722 src1
= as_vgpr(ctx
, src1
);
726 Builder
bld(ctx
->program
, ctx
->block
);
727 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
730 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
732 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
733 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
734 Builder
bld(ctx
->program
, ctx
->block
);
736 assert(dst
.regClass() == bld
.lm
);
737 assert(src0
.type() == RegType::sgpr
);
738 assert(src1
.type() == RegType::sgpr
);
739 assert(src0
.regClass() == src1
.regClass());
741 /* Emit the SALU comparison instruction */
742 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
743 /* Turn the result into a per-lane bool */
744 bool_to_vector_condition(ctx
, cmp
, dst
);
747 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
748 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
750 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
751 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
752 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
753 nir_dest_is_divergent(instr
->dest
.dest
) ||
754 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
755 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
756 aco_opcode op
= use_valu
? v_op
: s_op
;
757 assert(op
!= aco_opcode::num_opcodes
);
758 assert(dst
.regClass() == ctx
->program
->lane_mask
);
761 emit_vopc_instruction(ctx
, instr
, op
, dst
);
763 emit_sopc_instruction(ctx
, instr
, op
, dst
);
766 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
768 Builder
bld(ctx
->program
, ctx
->block
);
769 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
770 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
772 assert(dst
.regClass() == bld
.lm
);
773 assert(src0
.regClass() == bld
.lm
);
774 assert(src1
.regClass() == bld
.lm
);
776 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
779 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
781 Builder
bld(ctx
->program
, ctx
->block
);
782 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
783 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
784 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
786 assert(cond
.regClass() == bld
.lm
);
788 if (dst
.type() == RegType::vgpr
) {
789 aco_ptr
<Instruction
> bcsel
;
790 if (dst
.size() == 1) {
791 then
= as_vgpr(ctx
, then
);
792 els
= as_vgpr(ctx
, els
);
794 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
795 } else if (dst
.size() == 2) {
796 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
797 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
798 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
799 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
801 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
802 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
804 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
806 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
807 nir_print_instr(&instr
->instr
, stderr
);
808 fprintf(stderr
, "\n");
813 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
814 assert(dst
.regClass() == bld
.lm
);
815 assert(then
.regClass() == bld
.lm
);
816 assert(els
.regClass() == bld
.lm
);
819 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
820 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
821 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
822 assert(dst
.size() == then
.size());
823 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
824 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
826 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
827 nir_print_instr(&instr
->instr
, stderr
);
828 fprintf(stderr
, "\n");
833 /* divergent boolean bcsel
834 * this implements bcsel on bools: dst = s0 ? s1 : s2
835 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
836 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
838 if (cond
.id() != then
.id())
839 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
841 if (cond
.id() == els
.id())
842 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
844 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
845 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
848 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
849 aco_opcode op
, uint32_t undo
)
851 /* multiply by 16777216 to handle denormals */
852 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
853 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
854 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
855 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
856 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
858 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
860 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
863 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
865 if (ctx
->block
->fp_mode
.denorm32
== 0) {
866 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
870 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
873 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
875 if (ctx
->block
->fp_mode
.denorm32
== 0) {
876 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
880 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
883 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
885 if (ctx
->block
->fp_mode
.denorm32
== 0) {
886 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
890 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
893 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
895 if (ctx
->block
->fp_mode
.denorm32
== 0) {
896 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
900 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
903 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
905 if (ctx
->options
->chip_class
>= GFX7
)
906 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
908 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
909 /* TODO: create more efficient code! */
910 if (val
.type() == RegType::sgpr
)
911 val
= as_vgpr(ctx
, val
);
913 /* Split the input value. */
914 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
915 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
917 /* Extract the exponent and compute the unbiased value. */
918 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
919 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
921 /* Extract the fractional part. */
922 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
923 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
925 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
926 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
928 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
929 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
930 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
931 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
932 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
934 /* Get the sign bit. */
935 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
937 /* Decide the operation to apply depending on the unbiased exponent. */
938 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
939 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
940 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
941 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
942 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
943 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
945 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
948 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
950 if (ctx
->options
->chip_class
>= GFX7
)
951 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
953 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
954 Temp src0
= as_vgpr(ctx
, val
);
956 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
957 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
959 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
960 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
961 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
963 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
965 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
966 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
968 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
969 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
971 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
973 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
974 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
976 return add
->definitions
[0].getTemp();
979 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
981 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
982 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
984 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
987 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
988 return bld
.copy(Definition(dst
), src
);
989 else if (dst
.bytes() < src
.bytes())
990 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
994 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
997 } else if (src
.regClass() == s1
) {
999 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1001 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1002 } else if (ctx
->options
->chip_class
>= GFX8
) {
1003 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1004 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1005 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1006 sdwa
->operands
[0] = Operand(src
);
1007 sdwa
->definitions
[0] = Definition(tmp
);
1009 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1011 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1012 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1013 bld
.insert(std::move(sdwa
));
1015 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1016 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1017 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1020 if (dst_bits
== 64) {
1021 if (is_signed
&& dst
.regClass() == s2
) {
1022 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1023 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1024 } else if (is_signed
&& dst
.regClass() == v2
) {
1025 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1026 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1028 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1035 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1037 if (!instr
->dest
.dest
.is_ssa
) {
1038 fprintf(stderr
, "nir alu dst not in ssa: ");
1039 nir_print_instr(&instr
->instr
, stderr
);
1040 fprintf(stderr
, "\n");
1043 Builder
bld(ctx
->program
, ctx
->block
);
1044 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1049 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1050 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1051 for (unsigned i
= 0; i
< num
; ++i
)
1052 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1054 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1055 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1056 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1057 for (unsigned i
= 0; i
< num
; ++i
) {
1058 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1059 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1061 vec
->operands
[i
] = Operand
{elems
[i
]};
1063 vec
->definitions
[0] = Definition(dst
);
1064 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1065 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1067 // TODO: that is a bit suboptimal..
1068 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1069 for (unsigned i
= 0; i
< num
- 1; ++i
)
1070 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1071 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1072 for (unsigned i
= 0; i
< num
; ++i
) {
1073 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1074 if (bit
% 32 == 0) {
1075 elems
[bit
/ 32] = elems
[i
];
1077 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1078 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1079 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1082 if (dst
.size() == 1)
1083 bld
.copy(Definition(dst
), elems
[0]);
1085 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1090 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1091 aco_ptr
<Instruction
> mov
;
1092 if (dst
.type() == RegType::sgpr
) {
1093 if (src
.type() == RegType::vgpr
)
1094 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1095 else if (src
.regClass() == s1
)
1096 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1097 else if (src
.regClass() == s2
)
1098 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1100 unreachable("wrong src register class for nir_op_imov");
1102 if (dst
.regClass() == v1
)
1103 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1104 else if (dst
.regClass() == v1b
||
1105 dst
.regClass() == v2b
||
1106 dst
.regClass() == v2
)
1107 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1109 unreachable("wrong src register class for nir_op_imov");
1114 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1115 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1116 assert(src
.regClass() == bld
.lm
);
1117 assert(dst
.regClass() == bld
.lm
);
1118 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1119 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1120 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1121 } else if (dst
.regClass() == v1
) {
1122 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1123 } else if (dst
.type() == RegType::sgpr
) {
1124 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1125 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1127 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1128 nir_print_instr(&instr
->instr
, stderr
);
1129 fprintf(stderr
, "\n");
1134 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1135 if (dst
.regClass() == v1
) {
1136 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1137 } else if (dst
.regClass() == s1
) {
1138 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1139 } else if (dst
.size() == 2) {
1140 Temp src0
= bld
.tmp(dst
.type(), 1);
1141 Temp src1
= bld
.tmp(dst
.type(), 1);
1142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1144 if (dst
.regClass() == s2
) {
1145 Temp carry
= bld
.tmp(s1
);
1146 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1147 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1148 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1150 Temp lower
= bld
.tmp(v1
);
1151 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1152 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1156 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1157 nir_print_instr(&instr
->instr
, stderr
);
1158 fprintf(stderr
, "\n");
1163 if (dst
.regClass() == s1
) {
1164 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1165 } else if (dst
.regClass() == v1
) {
1166 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1167 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1175 case nir_op_isign
: {
1176 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1177 if (dst
.regClass() == s1
) {
1178 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1179 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1180 } else if (dst
.regClass() == s2
) {
1181 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1183 if (ctx
->program
->chip_class
>= GFX8
)
1184 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1186 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1187 /* SCC gets zero-extended to 64 bit */
1188 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1189 } else if (dst
.regClass() == v1
) {
1190 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1191 } else if (dst
.regClass() == v2
) {
1192 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1193 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1194 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1195 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1196 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1197 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1199 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1200 nir_print_instr(&instr
->instr
, stderr
);
1201 fprintf(stderr
, "\n");
1206 if (dst
.regClass() == v1
) {
1207 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1208 } else if (dst
.regClass() == s1
) {
1209 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1211 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1212 nir_print_instr(&instr
->instr
, stderr
);
1213 fprintf(stderr
, "\n");
1218 if (dst
.regClass() == v1
) {
1219 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1223 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1224 nir_print_instr(&instr
->instr
, stderr
);
1225 fprintf(stderr
, "\n");
1230 if (dst
.regClass() == v1
) {
1231 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1232 } else if (dst
.regClass() == s1
) {
1233 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1235 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1236 nir_print_instr(&instr
->instr
, stderr
);
1237 fprintf(stderr
, "\n");
1242 if (dst
.regClass() == v1
) {
1243 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1247 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1248 nir_print_instr(&instr
->instr
, stderr
);
1249 fprintf(stderr
, "\n");
1254 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1255 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1256 } else if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1258 } else if (dst
.regClass() == s1
) {
1259 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1260 } else if (dst
.regClass() == s2
) {
1261 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1263 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1264 nir_print_instr(&instr
->instr
, stderr
);
1265 fprintf(stderr
, "\n");
1270 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1271 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1272 } else if (dst
.regClass() == v1
) {
1273 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1274 } else if (dst
.regClass() == s1
) {
1275 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1276 } else if (dst
.regClass() == s2
) {
1277 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1279 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1280 nir_print_instr(&instr
->instr
, stderr
);
1281 fprintf(stderr
, "\n");
1286 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1287 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1288 } else if (dst
.regClass() == v1
) {
1289 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1290 } else if (dst
.regClass() == s1
) {
1291 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1292 } else if (dst
.regClass() == s2
) {
1293 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1295 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1296 nir_print_instr(&instr
->instr
, stderr
);
1297 fprintf(stderr
, "\n");
1302 if (dst
.regClass() == v1
) {
1303 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1304 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1305 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1306 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1307 } else if (dst
.regClass() == v2
) {
1308 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1309 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1310 } else if (dst
.regClass() == s2
) {
1311 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1312 } else if (dst
.regClass() == s1
) {
1313 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1315 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1316 nir_print_instr(&instr
->instr
, stderr
);
1317 fprintf(stderr
, "\n");
1322 if (dst
.regClass() == v1
) {
1323 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1324 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1325 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1326 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1327 } else if (dst
.regClass() == v2
) {
1328 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1329 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1330 } else if (dst
.regClass() == s1
) {
1331 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1332 } else if (dst
.regClass() == s2
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1335 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1336 nir_print_instr(&instr
->instr
, stderr
);
1337 fprintf(stderr
, "\n");
1342 if (dst
.regClass() == v1
) {
1343 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1344 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1345 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1346 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1347 } else if (dst
.regClass() == v2
) {
1348 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1349 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1350 } else if (dst
.regClass() == s1
) {
1351 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1352 } else if (dst
.regClass() == s2
) {
1353 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1355 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1356 nir_print_instr(&instr
->instr
, stderr
);
1357 fprintf(stderr
, "\n");
1361 case nir_op_find_lsb
: {
1362 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1363 if (src
.regClass() == s1
) {
1364 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1365 } else if (src
.regClass() == v1
) {
1366 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1367 } else if (src
.regClass() == s2
) {
1368 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1376 case nir_op_ufind_msb
:
1377 case nir_op_ifind_msb
: {
1378 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1379 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1380 aco_opcode op
= src
.regClass() == s2
?
1381 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1382 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1383 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1385 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1386 Operand(src
.size() * 32u - 1u), msb_rev
);
1387 Temp msb
= sub
.def(0).getTemp();
1388 Temp carry
= sub
.def(1).getTemp();
1390 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1391 } else if (src
.regClass() == v1
) {
1392 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1393 Temp msb_rev
= bld
.tmp(v1
);
1394 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1395 Temp msb
= bld
.tmp(v1
);
1396 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1397 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1399 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1400 nir_print_instr(&instr
->instr
, stderr
);
1401 fprintf(stderr
, "\n");
1405 case nir_op_bitfield_reverse
: {
1406 if (dst
.regClass() == s1
) {
1407 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1408 } else if (dst
.regClass() == v1
) {
1409 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1412 nir_print_instr(&instr
->instr
, stderr
);
1413 fprintf(stderr
, "\n");
1418 if (dst
.regClass() == s1
) {
1419 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1423 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1424 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1425 if (dst
.regClass() == v1
) {
1426 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1430 assert(src0
.size() == 2 && src1
.size() == 2);
1431 Temp src00
= bld
.tmp(src0
.type(), 1);
1432 Temp src01
= bld
.tmp(dst
.type(), 1);
1433 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1434 Temp src10
= bld
.tmp(src1
.type(), 1);
1435 Temp src11
= bld
.tmp(dst
.type(), 1);
1436 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1438 if (dst
.regClass() == s2
) {
1439 Temp carry
= bld
.tmp(s1
);
1440 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1441 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1442 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1443 } else if (dst
.regClass() == v2
) {
1444 Temp dst0
= bld
.tmp(v1
);
1445 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1446 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1447 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1449 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1450 nir_print_instr(&instr
->instr
, stderr
);
1451 fprintf(stderr
, "\n");
1455 case nir_op_uadd_sat
: {
1456 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1457 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1458 if (dst
.regClass() == s1
) {
1459 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1460 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1462 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1463 } else if (dst
.regClass() == v1
) {
1464 if (ctx
->options
->chip_class
>= GFX9
) {
1465 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1466 add
->operands
[0] = Operand(src0
);
1467 add
->operands
[1] = Operand(src1
);
1468 add
->definitions
[0] = Definition(dst
);
1470 ctx
->block
->instructions
.emplace_back(std::move(add
));
1472 if (src1
.regClass() != v1
)
1473 std::swap(src0
, src1
);
1474 assert(src1
.regClass() == v1
);
1475 Temp tmp
= bld
.tmp(v1
);
1476 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1477 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1480 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1481 nir_print_instr(&instr
->instr
, stderr
);
1482 fprintf(stderr
, "\n");
1486 case nir_op_uadd_carry
: {
1487 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1488 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1489 if (dst
.regClass() == s1
) {
1490 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1493 if (dst
.regClass() == v1
) {
1494 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1495 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1499 Temp src00
= bld
.tmp(src0
.type(), 1);
1500 Temp src01
= bld
.tmp(dst
.type(), 1);
1501 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1502 Temp src10
= bld
.tmp(src1
.type(), 1);
1503 Temp src11
= bld
.tmp(dst
.type(), 1);
1504 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1505 if (dst
.regClass() == s2
) {
1506 Temp carry
= bld
.tmp(s1
);
1507 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1508 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1509 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1510 } else if (dst
.regClass() == v2
) {
1511 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1512 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1513 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1514 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1516 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1517 nir_print_instr(&instr
->instr
, stderr
);
1518 fprintf(stderr
, "\n");
1523 if (dst
.regClass() == s1
) {
1524 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1528 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1529 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1530 if (dst
.regClass() == v1
) {
1531 bld
.vsub32(Definition(dst
), src0
, src1
);
1535 Temp src00
= bld
.tmp(src0
.type(), 1);
1536 Temp src01
= bld
.tmp(dst
.type(), 1);
1537 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1538 Temp src10
= bld
.tmp(src1
.type(), 1);
1539 Temp src11
= bld
.tmp(dst
.type(), 1);
1540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1541 if (dst
.regClass() == s2
) {
1542 Temp carry
= bld
.tmp(s1
);
1543 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1544 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1545 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1546 } else if (dst
.regClass() == v2
) {
1547 Temp lower
= bld
.tmp(v1
);
1548 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1549 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1550 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1552 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1553 nir_print_instr(&instr
->instr
, stderr
);
1554 fprintf(stderr
, "\n");
1558 case nir_op_usub_borrow
: {
1559 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1560 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1561 if (dst
.regClass() == s1
) {
1562 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1564 } else if (dst
.regClass() == v1
) {
1565 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1566 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1570 Temp src00
= bld
.tmp(src0
.type(), 1);
1571 Temp src01
= bld
.tmp(dst
.type(), 1);
1572 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1573 Temp src10
= bld
.tmp(src1
.type(), 1);
1574 Temp src11
= bld
.tmp(dst
.type(), 1);
1575 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1576 if (dst
.regClass() == s2
) {
1577 Temp borrow
= bld
.tmp(s1
);
1578 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1579 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1580 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1581 } else if (dst
.regClass() == v2
) {
1582 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1583 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1584 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1587 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1588 nir_print_instr(&instr
->instr
, stderr
);
1589 fprintf(stderr
, "\n");
1594 if (dst
.regClass() == v1
) {
1595 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1596 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1597 } else if (dst
.regClass() == s1
) {
1598 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1600 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1601 nir_print_instr(&instr
->instr
, stderr
);
1602 fprintf(stderr
, "\n");
1606 case nir_op_umul_high
: {
1607 if (dst
.regClass() == v1
) {
1608 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1609 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1610 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1611 } else if (dst
.regClass() == s1
) {
1612 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1613 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1614 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1616 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1617 nir_print_instr(&instr
->instr
, stderr
);
1618 fprintf(stderr
, "\n");
1622 case nir_op_imul_high
: {
1623 if (dst
.regClass() == v1
) {
1624 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1625 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1626 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1627 } else if (dst
.regClass() == s1
) {
1628 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1629 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1630 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1632 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1633 nir_print_instr(&instr
->instr
, stderr
);
1634 fprintf(stderr
, "\n");
1639 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1640 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1641 if (dst
.regClass() == v2b
) {
1642 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1643 } else if (dst
.regClass() == v1
) {
1644 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1645 } else if (dst
.regClass() == v2
) {
1646 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1648 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1649 nir_print_instr(&instr
->instr
, stderr
);
1650 fprintf(stderr
, "\n");
1655 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1656 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1657 if (dst
.regClass() == v2b
) {
1658 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1659 } else if (dst
.regClass() == v1
) {
1660 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1661 } else if (dst
.regClass() == v2
) {
1662 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1664 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1665 nir_print_instr(&instr
->instr
, stderr
);
1666 fprintf(stderr
, "\n");
1671 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1672 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1673 if (dst
.regClass() == v2b
) {
1674 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1675 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1677 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1678 } else if (dst
.regClass() == v1
) {
1679 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1680 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1682 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1683 } else if (dst
.regClass() == v2
) {
1684 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1685 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1686 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1689 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1690 nir_print_instr(&instr
->instr
, stderr
);
1691 fprintf(stderr
, "\n");
1696 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1697 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1698 if (dst
.regClass() == v2b
) {
1699 // TODO: check fp_mode.must_flush_denorms16_64
1700 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1701 } else if (dst
.regClass() == v1
) {
1702 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1703 } else if (dst
.regClass() == v2
) {
1704 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1705 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1706 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1708 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1711 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1712 nir_print_instr(&instr
->instr
, stderr
);
1713 fprintf(stderr
, "\n");
1718 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1719 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1720 if (dst
.regClass() == v2b
) {
1721 // TODO: check fp_mode.must_flush_denorms16_64
1722 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1723 } else if (dst
.regClass() == v1
) {
1724 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1725 } else if (dst
.regClass() == v2
) {
1726 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1727 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1728 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1730 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1733 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1734 nir_print_instr(&instr
->instr
, stderr
);
1735 fprintf(stderr
, "\n");
1739 case nir_op_fmax3
: {
1740 if (dst
.regClass() == v2b
) {
1741 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1742 } else if (dst
.regClass() == v1
) {
1743 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1745 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1746 nir_print_instr(&instr
->instr
, stderr
);
1747 fprintf(stderr
, "\n");
1751 case nir_op_fmin3
: {
1752 if (dst
.regClass() == v2b
) {
1753 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1754 } else if (dst
.regClass() == v1
) {
1755 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1758 nir_print_instr(&instr
->instr
, stderr
);
1759 fprintf(stderr
, "\n");
1763 case nir_op_fmed3
: {
1764 if (dst
.regClass() == v2b
) {
1765 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1766 } else if (dst
.regClass() == v1
) {
1767 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1769 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1770 nir_print_instr(&instr
->instr
, stderr
);
1771 fprintf(stderr
, "\n");
1775 case nir_op_umax3
: {
1776 if (dst
.size() == 1) {
1777 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1779 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1780 nir_print_instr(&instr
->instr
, stderr
);
1781 fprintf(stderr
, "\n");
1785 case nir_op_umin3
: {
1786 if (dst
.size() == 1) {
1787 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1789 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1790 nir_print_instr(&instr
->instr
, stderr
);
1791 fprintf(stderr
, "\n");
1795 case nir_op_umed3
: {
1796 if (dst
.size() == 1) {
1797 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1799 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1800 nir_print_instr(&instr
->instr
, stderr
);
1801 fprintf(stderr
, "\n");
1805 case nir_op_imax3
: {
1806 if (dst
.size() == 1) {
1807 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1809 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1810 nir_print_instr(&instr
->instr
, stderr
);
1811 fprintf(stderr
, "\n");
1815 case nir_op_imin3
: {
1816 if (dst
.size() == 1) {
1817 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1819 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1820 nir_print_instr(&instr
->instr
, stderr
);
1821 fprintf(stderr
, "\n");
1825 case nir_op_imed3
: {
1826 if (dst
.size() == 1) {
1827 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1829 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1830 nir_print_instr(&instr
->instr
, stderr
);
1831 fprintf(stderr
, "\n");
1835 case nir_op_cube_face_coord
: {
1836 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1837 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1838 emit_extract_vector(ctx
, in
, 1, v1
),
1839 emit_extract_vector(ctx
, in
, 2, v1
) };
1840 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1841 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1842 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1843 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1844 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1845 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1846 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1849 case nir_op_cube_face_index
: {
1850 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1851 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1852 emit_extract_vector(ctx
, in
, 1, v1
),
1853 emit_extract_vector(ctx
, in
, 2, v1
) };
1854 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1857 case nir_op_bcsel
: {
1858 emit_bcsel(ctx
, instr
, dst
);
1862 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1863 if (dst
.regClass() == v2b
) {
1864 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1865 } else if (dst
.regClass() == v1
) {
1866 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1867 } else if (dst
.regClass() == v2
) {
1868 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1870 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1871 nir_print_instr(&instr
->instr
, stderr
);
1872 fprintf(stderr
, "\n");
1877 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1878 if (dst
.regClass() == v2b
) {
1879 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1880 } else if (dst
.regClass() == v1
) {
1881 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1882 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1883 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1884 } else if (dst
.regClass() == v2
) {
1885 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1886 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1887 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1888 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1889 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1890 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1892 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1893 nir_print_instr(&instr
->instr
, stderr
);
1894 fprintf(stderr
, "\n");
1899 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1900 if (dst
.regClass() == v2b
) {
1901 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1902 } else if (dst
.regClass() == v1
) {
1903 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1904 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1905 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1906 } else if (dst
.regClass() == v2
) {
1907 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1908 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1909 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1910 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1911 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1912 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1914 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1915 nir_print_instr(&instr
->instr
, stderr
);
1916 fprintf(stderr
, "\n");
1921 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1922 if (dst
.regClass() == v2b
) {
1923 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1924 } else if (dst
.regClass() == v1
) {
1925 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1926 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1927 // TODO: confirm that this holds under any circumstances
1928 } else if (dst
.regClass() == v2
) {
1929 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1930 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1933 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1934 nir_print_instr(&instr
->instr
, stderr
);
1935 fprintf(stderr
, "\n");
1939 case nir_op_flog2
: {
1940 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1941 if (dst
.regClass() == v2b
) {
1942 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1943 } else if (dst
.regClass() == v1
) {
1944 emit_log2(ctx
, bld
, Definition(dst
), src
);
1946 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1947 nir_print_instr(&instr
->instr
, stderr
);
1948 fprintf(stderr
, "\n");
1953 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1954 if (dst
.regClass() == v2b
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1956 } else if (dst
.regClass() == v1
) {
1957 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1958 } else if (dst
.regClass() == v2
) {
1959 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1961 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1962 nir_print_instr(&instr
->instr
, stderr
);
1963 fprintf(stderr
, "\n");
1967 case nir_op_fexp2
: {
1968 if (dst
.regClass() == v2b
) {
1969 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1973 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1974 nir_print_instr(&instr
->instr
, stderr
);
1975 fprintf(stderr
, "\n");
1979 case nir_op_fsqrt
: {
1980 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1981 if (dst
.regClass() == v2b
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1983 } else if (dst
.regClass() == v1
) {
1984 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1985 } else if (dst
.regClass() == v2
) {
1986 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1988 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1989 nir_print_instr(&instr
->instr
, stderr
);
1990 fprintf(stderr
, "\n");
1994 case nir_op_ffract
: {
1995 if (dst
.regClass() == v2b
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1997 } else if (dst
.regClass() == v1
) {
1998 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1999 } else if (dst
.regClass() == v2
) {
2000 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2002 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2003 nir_print_instr(&instr
->instr
, stderr
);
2004 fprintf(stderr
, "\n");
2008 case nir_op_ffloor
: {
2009 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2010 if (dst
.regClass() == v2b
) {
2011 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2012 } else if (dst
.regClass() == v1
) {
2013 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2014 } else if (dst
.regClass() == v2
) {
2015 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2017 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2018 nir_print_instr(&instr
->instr
, stderr
);
2019 fprintf(stderr
, "\n");
2023 case nir_op_fceil
: {
2024 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2025 if (dst
.regClass() == v2b
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2027 } else if (dst
.regClass() == v1
) {
2028 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2029 } else if (dst
.regClass() == v2
) {
2030 if (ctx
->options
->chip_class
>= GFX7
) {
2031 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2033 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2034 /* trunc = trunc(src0)
2035 * if (src0 > 0.0 && src0 != trunc)
2038 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2039 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2040 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2041 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2042 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2043 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2044 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2053 case nir_op_ftrunc
: {
2054 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2055 if (dst
.regClass() == v2b
) {
2056 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2057 } else if (dst
.regClass() == v1
) {
2058 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2059 } else if (dst
.regClass() == v2
) {
2060 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2062 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2063 nir_print_instr(&instr
->instr
, stderr
);
2064 fprintf(stderr
, "\n");
2068 case nir_op_fround_even
: {
2069 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2070 if (dst
.regClass() == v2b
) {
2071 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2072 } else if (dst
.regClass() == v1
) {
2073 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2074 } else if (dst
.regClass() == v2
) {
2075 if (ctx
->options
->chip_class
>= GFX7
) {
2076 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2078 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2079 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2080 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2082 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2083 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2084 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2085 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2086 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2087 tmp
= sub
->definitions
[0].getTemp();
2089 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2090 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2091 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2092 Temp cond
= vop3
->definitions
[0].getTemp();
2094 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2095 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2096 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2097 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2099 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2102 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2103 nir_print_instr(&instr
->instr
, stderr
);
2104 fprintf(stderr
, "\n");
2110 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2111 aco_ptr
<Instruction
> norm
;
2112 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2113 if (dst
.regClass() == v2b
) {
2114 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2115 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2116 bld
.vop1(opcode
, Definition(dst
), tmp
);
2117 } else if (dst
.regClass() == v1
) {
2118 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2120 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2121 if (ctx
->options
->chip_class
< GFX9
)
2122 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2124 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2125 bld
.vop1(opcode
, Definition(dst
), tmp
);
2127 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2128 nir_print_instr(&instr
->instr
, stderr
);
2129 fprintf(stderr
, "\n");
2133 case nir_op_ldexp
: {
2134 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2135 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2136 if (dst
.regClass() == v2b
) {
2137 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2138 } else if (dst
.regClass() == v1
) {
2139 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2140 } else if (dst
.regClass() == v2
) {
2141 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2143 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2144 nir_print_instr(&instr
->instr
, stderr
);
2145 fprintf(stderr
, "\n");
2149 case nir_op_frexp_sig
: {
2150 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2151 if (dst
.regClass() == v2b
) {
2152 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2153 } else if (dst
.regClass() == v1
) {
2154 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2155 } else if (dst
.regClass() == v2
) {
2156 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2158 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2159 nir_print_instr(&instr
->instr
, stderr
);
2160 fprintf(stderr
, "\n");
2164 case nir_op_frexp_exp
: {
2165 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2166 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2167 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2168 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2169 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2170 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2171 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2172 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2173 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2175 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2176 nir_print_instr(&instr
->instr
, stderr
);
2177 fprintf(stderr
, "\n");
2181 case nir_op_fsign
: {
2182 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2183 if (dst
.regClass() == v2b
) {
2184 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2185 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2186 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2187 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2188 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2189 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2190 } else if (dst
.regClass() == v1
) {
2191 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2193 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2194 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2195 } else if (dst
.regClass() == v2
) {
2196 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2197 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2198 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2200 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2201 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2202 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2204 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2206 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2207 nir_print_instr(&instr
->instr
, stderr
);
2208 fprintf(stderr
, "\n");
2213 case nir_op_f2f16_rtne
: {
2214 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2215 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2216 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2217 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2220 case nir_op_f2f16_rtz
: {
2221 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2222 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2223 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2224 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2227 case nir_op_f2f32
: {
2228 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2229 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2230 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2231 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2233 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2234 nir_print_instr(&instr
->instr
, stderr
);
2235 fprintf(stderr
, "\n");
2239 case nir_op_f2f64
: {
2240 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2241 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2242 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2243 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2246 case nir_op_i2f16
: {
2247 assert(dst
.regClass() == v2b
);
2248 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2249 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2250 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2251 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2252 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2253 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2256 case nir_op_i2f32
: {
2257 assert(dst
.size() == 1);
2258 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2259 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2260 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2261 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2264 case nir_op_i2f64
: {
2265 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2266 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2267 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2268 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2269 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2270 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2271 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2272 RegClass rc
= RegClass(src
.type(), 1);
2273 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2274 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2275 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2276 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2277 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2278 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2281 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2282 nir_print_instr(&instr
->instr
, stderr
);
2283 fprintf(stderr
, "\n");
2287 case nir_op_u2f16
: {
2288 assert(dst
.regClass() == v2b
);
2289 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2290 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2291 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2292 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2293 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2294 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2297 case nir_op_u2f32
: {
2298 assert(dst
.size() == 1);
2299 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2300 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2301 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2303 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2304 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2305 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2309 case nir_op_u2f64
: {
2310 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2311 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2312 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2313 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2314 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2315 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2316 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2317 RegClass rc
= RegClass(src
.type(), 1);
2318 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2319 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2320 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2321 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2322 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2323 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2326 nir_print_instr(&instr
->instr
, stderr
);
2327 fprintf(stderr
, "\n");
2332 case nir_op_f2i16
: {
2333 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2334 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2335 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2336 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2338 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2342 case nir_op_f2u16
: {
2343 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2344 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2345 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2346 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2348 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2351 case nir_op_f2i32
: {
2352 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2353 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2354 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2355 if (dst
.type() == RegType::vgpr
) {
2356 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2358 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2359 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2361 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2362 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2363 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2364 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2366 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2367 nir_print_instr(&instr
->instr
, stderr
);
2368 fprintf(stderr
, "\n");
2372 case nir_op_f2u32
: {
2373 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2374 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2375 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2376 if (dst
.type() == RegType::vgpr
) {
2377 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2379 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2380 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2382 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2383 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2384 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2385 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2387 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2388 nir_print_instr(&instr
->instr
, stderr
);
2389 fprintf(stderr
, "\n");
2393 case nir_op_f2i64
: {
2394 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2395 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2396 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2398 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2399 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2400 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2401 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2402 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2403 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2404 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2405 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2406 Temp new_exponent
= bld
.tmp(v1
);
2407 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2408 if (ctx
->program
->chip_class
>= GFX8
)
2409 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2411 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2412 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2413 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2414 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2415 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2416 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2417 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2418 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2419 Temp new_lower
= bld
.tmp(v1
);
2420 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2421 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2422 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2424 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2425 if (src
.type() == RegType::vgpr
)
2426 src
= bld
.as_uniform(src
);
2427 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2428 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2429 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2430 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2431 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2432 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2433 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2434 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2435 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2436 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2437 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2438 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2439 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2440 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2441 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2442 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2443 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2444 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2445 Temp borrow
= bld
.tmp(s1
);
2446 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2447 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2448 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2450 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2451 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2452 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2453 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2454 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2455 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2456 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2457 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2458 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2459 if (dst
.type() == RegType::sgpr
) {
2460 lower
= bld
.as_uniform(lower
);
2461 upper
= bld
.as_uniform(upper
);
2463 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2467 nir_print_instr(&instr
->instr
, stderr
);
2468 fprintf(stderr
, "\n");
2472 case nir_op_f2u64
: {
2473 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2474 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2475 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2477 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2478 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2479 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2480 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2481 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2482 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2483 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2484 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2485 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2486 Temp new_exponent
= bld
.tmp(v1
);
2487 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2488 if (ctx
->program
->chip_class
>= GFX8
)
2489 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2491 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2492 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2493 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2494 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2495 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2496 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2497 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2498 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2500 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2501 if (src
.type() == RegType::vgpr
)
2502 src
= bld
.as_uniform(src
);
2503 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2504 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2505 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2506 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2507 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2508 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2509 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2510 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2511 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2512 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2513 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2514 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2515 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2517 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2518 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2519 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2520 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2522 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2523 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2524 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2525 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2526 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2527 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2528 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2529 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2530 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2531 if (dst
.type() == RegType::sgpr
) {
2532 lower
= bld
.as_uniform(lower
);
2533 upper
= bld
.as_uniform(upper
);
2535 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2538 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2539 nir_print_instr(&instr
->instr
, stderr
);
2540 fprintf(stderr
, "\n");
2544 case nir_op_b2f16
: {
2545 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2546 assert(src
.regClass() == bld
.lm
);
2548 if (dst
.regClass() == s1
) {
2549 src
= bool_to_scalar_condition(ctx
, src
);
2550 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2551 } else if (dst
.regClass() == v2b
) {
2552 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2553 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2555 unreachable("Wrong destination register class for nir_op_b2f16.");
2559 case nir_op_b2f32
: {
2560 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2561 assert(src
.regClass() == bld
.lm
);
2563 if (dst
.regClass() == s1
) {
2564 src
= bool_to_scalar_condition(ctx
, src
);
2565 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2566 } else if (dst
.regClass() == v1
) {
2567 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2569 unreachable("Wrong destination register class for nir_op_b2f32.");
2573 case nir_op_b2f64
: {
2574 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2575 assert(src
.regClass() == bld
.lm
);
2577 if (dst
.regClass() == s2
) {
2578 src
= bool_to_scalar_condition(ctx
, src
);
2579 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2580 } else if (dst
.regClass() == v2
) {
2581 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2582 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2583 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2585 unreachable("Wrong destination register class for nir_op_b2f64.");
2592 case nir_op_i2i64
: {
2593 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2594 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2600 case nir_op_u2u64
: {
2601 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2602 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2606 case nir_op_b2i32
: {
2607 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2608 assert(src
.regClass() == bld
.lm
);
2610 if (dst
.regClass() == s1
) {
2611 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2612 bool_to_scalar_condition(ctx
, src
, dst
);
2613 } else if (dst
.regClass() == v1
) {
2614 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2616 unreachable("Invalid register class for b2i32");
2622 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2623 assert(dst
.regClass() == bld
.lm
);
2625 if (src
.type() == RegType::vgpr
) {
2626 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2627 assert(dst
.regClass() == bld
.lm
);
2628 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2629 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2631 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2633 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2634 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2636 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2637 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2639 bool_to_vector_condition(ctx
, tmp
, dst
);
2643 case nir_op_pack_64_2x32_split
: {
2644 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2645 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2647 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2650 case nir_op_unpack_64_2x32_split_x
:
2651 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2653 case nir_op_unpack_64_2x32_split_y
:
2654 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2656 case nir_op_unpack_32_2x16_split_x
:
2657 if (dst
.type() == RegType::vgpr
) {
2658 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2660 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2663 case nir_op_unpack_32_2x16_split_y
:
2664 if (dst
.type() == RegType::vgpr
) {
2665 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2667 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2670 case nir_op_pack_32_2x16_split
: {
2671 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2672 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2673 if (dst
.regClass() == v1
) {
2674 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2675 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2676 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2678 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2679 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2680 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2684 case nir_op_pack_half_2x16
: {
2685 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2687 if (dst
.regClass() == v1
) {
2688 Temp src0
= bld
.tmp(v1
);
2689 Temp src1
= bld
.tmp(v1
);
2690 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2691 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2692 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2694 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2695 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2696 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2698 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2699 nir_print_instr(&instr
->instr
, stderr
);
2700 fprintf(stderr
, "\n");
2704 case nir_op_unpack_half_2x16_split_x
: {
2705 if (dst
.regClass() == v1
) {
2706 Builder
bld(ctx
->program
, ctx
->block
);
2707 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2710 nir_print_instr(&instr
->instr
, stderr
);
2711 fprintf(stderr
, "\n");
2715 case nir_op_unpack_half_2x16_split_y
: {
2716 if (dst
.regClass() == v1
) {
2717 Builder
bld(ctx
->program
, ctx
->block
);
2718 /* TODO: use SDWA here */
2719 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2720 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2722 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2723 nir_print_instr(&instr
->instr
, stderr
);
2724 fprintf(stderr
, "\n");
2728 case nir_op_fquantize2f16
: {
2729 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2730 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2733 if (ctx
->program
->chip_class
>= GFX8
) {
2734 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2735 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2736 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2738 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2739 * so compare the result and flush to 0 if it's smaller.
2741 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2742 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2743 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2744 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2745 cmp_res
= vop3
->definitions
[0].getTemp();
2748 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2749 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2750 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2752 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2757 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2758 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2760 if (dst
.regClass() == s1
) {
2761 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2762 } else if (dst
.regClass() == v1
) {
2763 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2765 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2766 nir_print_instr(&instr
->instr
, stderr
);
2767 fprintf(stderr
, "\n");
2771 case nir_op_bitfield_select
: {
2772 /* (mask & insert) | (~mask & base) */
2773 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2774 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2775 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2777 /* dst = (insert & bitmask) | (base & ~bitmask) */
2778 if (dst
.regClass() == s1
) {
2779 aco_ptr
<Instruction
> sop2
;
2780 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2781 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2783 if (const_insert
&& const_bitmask
) {
2784 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2786 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2787 lhs
= Operand(insert
);
2791 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2792 if (const_base
&& const_bitmask
) {
2793 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2795 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2796 rhs
= Operand(base
);
2799 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2801 } else if (dst
.regClass() == v1
) {
2802 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2803 base
= as_vgpr(ctx
, base
);
2804 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2805 insert
= as_vgpr(ctx
, insert
);
2807 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2810 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2811 nir_print_instr(&instr
->instr
, stderr
);
2812 fprintf(stderr
, "\n");
2818 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2819 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2820 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2822 if (dst
.type() == RegType::sgpr
) {
2824 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2825 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2826 if (const_offset
&& const_bits
) {
2827 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2828 extract
= Operand(const_extract
);
2832 width
= Operand(const_bits
->u32
<< 16);
2834 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2836 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2840 if (dst
.regClass() == s1
) {
2841 if (instr
->op
== nir_op_ubfe
)
2842 opcode
= aco_opcode::s_bfe_u32
;
2844 opcode
= aco_opcode::s_bfe_i32
;
2845 } else if (dst
.regClass() == s2
) {
2846 if (instr
->op
== nir_op_ubfe
)
2847 opcode
= aco_opcode::s_bfe_u64
;
2849 opcode
= aco_opcode::s_bfe_i64
;
2851 unreachable("Unsupported BFE bit size");
2854 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2858 if (dst
.regClass() == v1
) {
2859 if (instr
->op
== nir_op_ubfe
)
2860 opcode
= aco_opcode::v_bfe_u32
;
2862 opcode
= aco_opcode::v_bfe_i32
;
2864 unreachable("Unsupported BFE bit size");
2867 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2871 case nir_op_bit_count
: {
2872 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2873 if (src
.regClass() == s1
) {
2874 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2875 } else if (src
.regClass() == v1
) {
2876 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2877 } else if (src
.regClass() == v2
) {
2878 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2879 emit_extract_vector(ctx
, src
, 1, v1
),
2880 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2881 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2882 } else if (src
.regClass() == s2
) {
2883 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2885 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2886 nir_print_instr(&instr
->instr
, stderr
);
2887 fprintf(stderr
, "\n");
2892 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2896 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2900 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2904 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2908 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2912 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2916 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2917 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2919 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2920 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2924 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2925 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2927 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2928 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2932 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2936 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2941 case nir_op_fddx_fine
:
2942 case nir_op_fddy_fine
:
2943 case nir_op_fddx_coarse
:
2944 case nir_op_fddy_coarse
: {
2945 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2946 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2947 if (instr
->op
== nir_op_fddx_fine
) {
2948 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2949 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2950 } else if (instr
->op
== nir_op_fddy_fine
) {
2951 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2952 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2954 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2955 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2956 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2958 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2962 if (ctx
->program
->chip_class
>= GFX8
) {
2963 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2964 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2966 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2967 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2968 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2970 emit_wqm(ctx
, tmp
, dst
, true);
2974 fprintf(stderr
, "Unknown NIR ALU instr: ");
2975 nir_print_instr(&instr
->instr
, stderr
);
2976 fprintf(stderr
, "\n");
2980 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2982 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2984 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2985 // which get truncated the lsb if double and msb if int
2986 // for now, we only use s_mov_b64 with 64bit inline constants
2987 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2988 assert(dst
.type() == RegType::sgpr
);
2990 Builder
bld(ctx
->program
, ctx
->block
);
2992 if (instr
->def
.bit_size
== 1) {
2993 assert(dst
.regClass() == bld
.lm
);
2994 int val
= instr
->value
[0].b
? -1 : 0;
2995 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2996 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2997 } else if (instr
->def
.bit_size
== 8) {
2998 /* ensure that the value is correctly represented in the low byte of the register */
2999 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3000 } else if (instr
->def
.bit_size
== 16) {
3001 /* ensure that the value is correctly represented in the low half of the register */
3002 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3003 } else if (dst
.size() == 1) {
3004 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3006 assert(dst
.size() != 1);
3007 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3008 if (instr
->def
.bit_size
== 64)
3009 for (unsigned i
= 0; i
< dst
.size(); i
++)
3010 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3012 for (unsigned i
= 0; i
< dst
.size(); i
++)
3013 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3015 vec
->definitions
[0] = Definition(dst
);
3016 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3020 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3022 uint32_t new_mask
= 0;
3023 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3024 if (mask
& (1u << i
))
3025 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3029 struct LoadEmitInfo
{
3032 unsigned num_components
;
3033 unsigned component_size
;
3034 Temp resource
= Temp(0, s1
);
3035 unsigned component_stride
= 0;
3036 unsigned const_offset
= 0;
3037 unsigned align_mul
= 0;
3038 unsigned align_offset
= 0;
3041 unsigned swizzle_component_size
= 0;
3042 barrier_interaction barrier
= barrier_none
;
3043 bool can_reorder
= true;
3044 Temp soffset
= Temp(0, s1
);
3047 using LoadCallback
= Temp(*)(
3048 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3049 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3051 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3052 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3054 unsigned load_size
= info
->num_components
* info
->component_size
;
3055 unsigned component_size
= info
->component_size
;
3057 unsigned num_vals
= 0;
3058 Temp vals
[info
->dst
.bytes()];
3060 unsigned const_offset
= info
->const_offset
;
3062 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3063 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3065 unsigned bytes_read
= 0;
3066 while (bytes_read
< load_size
) {
3067 unsigned bytes_needed
= load_size
- bytes_read
;
3069 /* add buffer for unaligned loads */
3070 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3073 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3074 if (info
->component_stride
) {
3075 assert(supports_8bit_16bit_loads
&& "unimplemented");
3079 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3080 bytes_needed
= align(bytes_needed
, 4);
3087 if (info
->swizzle_component_size
)
3088 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3089 if (info
->component_stride
)
3090 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3092 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3094 /* reduce constant offset */
3095 Operand offset
= info
->offset
;
3096 unsigned reduced_const_offset
= const_offset
;
3097 bool remove_const_offset_completely
= need_to_align_offset
;
3098 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3099 unsigned to_add
= const_offset
;
3100 if (remove_const_offset_completely
) {
3101 reduced_const_offset
= 0;
3103 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3104 reduced_const_offset
%= max_const_offset_plus_one
;
3106 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3107 if (offset
.isConstant()) {
3108 offset
= Operand(offset
.constantValue() + to_add
);
3109 } else if (offset_tmp
.regClass() == s1
) {
3110 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3111 offset_tmp
, Operand(to_add
));
3112 } else if (offset_tmp
.regClass() == v1
) {
3113 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3115 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3116 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3117 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3119 if (offset_tmp
.regClass() == s2
) {
3120 Temp carry
= bld
.tmp(s1
);
3121 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3122 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3123 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3125 Temp new_lo
= bld
.tmp(v1
);
3126 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3127 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3128 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3133 /* align offset down if needed */
3134 Operand aligned_offset
= offset
;
3135 if (need_to_align_offset
) {
3136 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3137 if (offset
.isConstant()) {
3138 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3139 } else if (offset_tmp
.regClass() == s1
) {
3140 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3141 } else if (offset_tmp
.regClass() == s2
) {
3142 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3143 } else if (offset_tmp
.regClass() == v1
) {
3144 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3145 } else if (offset_tmp
.regClass() == v2
) {
3146 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3147 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3148 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3149 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3152 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3153 bld
.copy(bld
.def(s1
), aligned_offset
);
3155 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3156 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3157 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3159 /* the callback wrote directly to dst */
3160 if (val
== info
->dst
) {
3161 assert(num_vals
== 0);
3162 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3166 /* shift result right if needed */
3167 if (info
->component_size
< 4 && byte_align_loads
) {
3168 Operand
align((uint32_t)byte_align
);
3169 if (byte_align
== -1) {
3170 if (offset
.isConstant())
3171 align
= Operand(offset
.constantValue() % 4u);
3172 else if (offset
.size() == 2)
3173 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3178 assert(val
.bytes() >= load_size
&& "unimplemented");
3179 if (val
.type() == RegType::sgpr
)
3180 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3182 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3186 /* add result to list and advance */
3187 if (info
->component_stride
) {
3188 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3189 const_offset
+= info
->component_stride
;
3190 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3192 const_offset
+= val
.bytes();
3193 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3195 bytes_read
+= val
.bytes();
3196 vals
[num_vals
++] = val
;
3199 /* create array of components */
3200 unsigned components_split
= 0;
3201 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3202 bool has_vgprs
= false;
3203 for (unsigned i
= 0; i
< num_vals
;) {
3205 unsigned num_tmps
= 0;
3206 unsigned tmp_size
= 0;
3207 RegType reg_type
= RegType::sgpr
;
3208 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3209 if (vals
[i
].type() == RegType::vgpr
)
3210 reg_type
= RegType::vgpr
;
3211 tmp_size
+= vals
[i
].bytes();
3212 tmp
[num_tmps
++] = vals
[i
++];
3215 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3216 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3217 for (unsigned i
= 0; i
< num_vals
; i
++)
3218 vec
->operands
[i
] = Operand(tmp
[i
]);
3219 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3220 vec
->definitions
[0] = Definition(tmp
[0]);
3221 bld
.insert(std::move(vec
));
3224 if (tmp
[0].bytes() % component_size
) {
3226 assert(i
== num_vals
);
3227 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3228 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3231 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3233 unsigned start
= components_split
;
3235 if (tmp_size
== elem_rc
.bytes()) {
3236 allocated_vec
[components_split
++] = tmp
[0];
3238 assert(tmp_size
% elem_rc
.bytes() == 0);
3239 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3240 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3241 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3242 Temp component
= bld
.tmp(elem_rc
);
3243 allocated_vec
[components_split
++] = component
;
3244 split
->definitions
[i
] = Definition(component
);
3246 split
->operands
[0] = Operand(tmp
[0]);
3247 bld
.insert(std::move(split
));
3250 /* try to p_as_uniform early so we can create more optimizable code and
3251 * also update allocated_vec */
3252 for (unsigned j
= start
; j
< components_split
; j
++) {
3253 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3254 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3255 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3259 /* concatenate components and p_as_uniform() result if needed */
3260 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3261 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3263 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3265 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3266 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3267 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3268 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3270 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3271 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3272 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3273 vec
->definitions
[0] = Definition(tmp
);
3274 bld
.insert(std::move(vec
));
3275 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3277 vec
->definitions
[0] = Definition(info
->dst
);
3278 bld
.insert(std::move(vec
));
3282 Operand
load_lds_size_m0(Builder
& bld
)
3284 /* TODO: m0 does not need to be initialized on GFX9+ */
3285 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3288 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3289 Temp offset
, unsigned bytes_needed
,
3290 unsigned align
, unsigned const_offset
,
3293 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3295 Operand m
= load_lds_size_m0(bld
);
3297 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3298 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3303 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3304 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3306 op
= aco_opcode::ds_read_b128
;
3307 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3310 op
= aco_opcode::ds_read2_b64
;
3311 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3313 op
= aco_opcode::ds_read_b96
;
3314 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3316 op
= aco_opcode::ds_read_b64
;
3317 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3320 op
= aco_opcode::ds_read2_b32
;
3321 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3323 op
= aco_opcode::ds_read_b32
;
3324 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3326 op
= aco_opcode::ds_read_u16
;
3329 op
= aco_opcode::ds_read_u8
;
3332 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3333 if (const_offset
>= max_offset_plus_one
) {
3334 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3335 const_offset
%= max_offset_plus_one
;
3339 const_offset
/= (size
/ 2u);
3341 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3342 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3344 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3346 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3349 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3354 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3356 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3357 Temp offset
, unsigned bytes_needed
,
3358 unsigned align
, unsigned const_offset
,
3363 if (bytes_needed
<= 4) {
3365 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3366 } else if (bytes_needed
<= 8) {
3368 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3369 } else if (bytes_needed
<= 16) {
3371 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3372 } else if (bytes_needed
<= 32) {
3374 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3377 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3379 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3380 if (info
->resource
.id()) {
3381 load
->operands
[0] = Operand(info
->resource
);
3382 load
->operands
[1] = Operand(offset
);
3384 load
->operands
[0] = Operand(offset
);
3385 load
->operands
[1] = Operand(0u);
3387 RegClass
rc(RegType::sgpr
, size
);
3388 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3389 load
->definitions
[0] = Definition(val
);
3390 load
->glc
= info
->glc
;
3391 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3392 load
->barrier
= info
->barrier
;
3393 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3394 bld
.insert(std::move(load
));
3398 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3400 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3401 Temp offset
, unsigned bytes_needed
,
3402 unsigned align_
, unsigned const_offset
,
3405 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3406 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3408 if (info
->soffset
.id()) {
3409 if (soffset
.isTemp())
3410 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3411 soffset
= Operand(info
->soffset
);
3414 unsigned bytes_size
= 0;
3416 if (bytes_needed
== 1) {
3418 op
= aco_opcode::buffer_load_ubyte
;
3419 } else if (bytes_needed
== 2) {
3421 op
= aco_opcode::buffer_load_ushort
;
3422 } else if (bytes_needed
<= 4) {
3424 op
= aco_opcode::buffer_load_dword
;
3425 } else if (bytes_needed
<= 8) {
3427 op
= aco_opcode::buffer_load_dwordx2
;
3428 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3430 op
= aco_opcode::buffer_load_dwordx3
;
3433 op
= aco_opcode::buffer_load_dwordx4
;
3435 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3436 mubuf
->operands
[0] = Operand(info
->resource
);
3437 mubuf
->operands
[1] = vaddr
;
3438 mubuf
->operands
[2] = soffset
;
3439 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3440 mubuf
->glc
= info
->glc
;
3441 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3442 mubuf
->barrier
= info
->barrier
;
3443 mubuf
->can_reorder
= info
->can_reorder
;
3444 mubuf
->offset
= const_offset
;
3445 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3446 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3447 mubuf
->definitions
[0] = Definition(val
);
3448 bld
.insert(std::move(mubuf
));
3453 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3455 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3457 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3458 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3460 if (addr
.type() == RegType::vgpr
)
3461 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3462 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3465 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3466 Temp offset
, unsigned bytes_needed
,
3467 unsigned align_
, unsigned const_offset
,
3470 unsigned bytes_size
= 0;
3471 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3472 bool global
= bld
.program
->chip_class
>= GFX9
;
3474 if (bytes_needed
== 1) {
3476 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3477 } else if (bytes_needed
== 2) {
3479 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3480 } else if (bytes_needed
<= 4) {
3482 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3483 } else if (bytes_needed
<= 8) {
3485 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3486 } else if (bytes_needed
<= 12 && !mubuf
) {
3488 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3491 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3493 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3494 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3496 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3497 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3498 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3499 mubuf
->operands
[2] = Operand(0u);
3500 mubuf
->glc
= info
->glc
;
3503 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3504 mubuf
->disable_wqm
= false;
3505 mubuf
->barrier
= info
->barrier
;
3506 mubuf
->definitions
[0] = Definition(val
);
3507 bld
.insert(std::move(mubuf
));
3509 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3511 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3512 flat
->operands
[0] = Operand(offset
);
3513 flat
->operands
[1] = Operand(s1
);
3514 flat
->glc
= info
->glc
;
3515 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3516 flat
->barrier
= info
->barrier
;
3518 flat
->definitions
[0] = Definition(val
);
3519 bld
.insert(std::move(flat
));
3525 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3527 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3528 Temp address
, unsigned base_offset
, unsigned align
)
3530 assert(util_is_power_of_two_nonzero(align
));
3532 Builder
bld(ctx
->program
, ctx
->block
);
3534 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3535 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3536 info
.align_mul
= align
;
3537 info
.align_offset
= 0;
3538 info
.barrier
= barrier_shared
;
3539 info
.can_reorder
= false;
3540 info
.const_offset
= base_offset
;
3541 emit_lds_load(ctx
, bld
, &info
);
3546 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3551 Builder
bld(ctx
->program
, ctx
->block
);
3553 ASSERTED
bool is_subdword
= false;
3554 for (unsigned i
= 0; i
< count
; i
++)
3555 is_subdword
|= offsets
[i
] % 4;
3556 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3557 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3559 /* count == 1 fast path */
3561 if (dst_type
== RegType::sgpr
)
3562 dst
[0] = bld
.as_uniform(src
);
3564 dst
[0] = as_vgpr(ctx
, src
);
3568 for (unsigned i
= 0; i
< count
- 1; i
++)
3569 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3570 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3572 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3573 src
= as_vgpr(ctx
, src
);
3575 /* use allocated_vec if possible */
3576 auto it
= ctx
->allocated_vec
.find(src
.id());
3577 if (it
!= ctx
->allocated_vec
.end()) {
3578 unsigned total_size
= 0;
3579 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3580 total_size
+= it
->second
[i
].bytes();
3581 if (total_size
!= src
.bytes())
3584 unsigned elem_size
= it
->second
[0].bytes();
3586 for (unsigned i
= 0; i
< count
; i
++) {
3587 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3591 for (unsigned i
= 0; i
< count
; i
++) {
3592 unsigned start_idx
= offsets
[i
] / elem_size
;
3593 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3594 if (op_count
== 1) {
3595 if (dst_type
== RegType::sgpr
)
3596 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3598 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3602 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3603 for (unsigned j
= 0; j
< op_count
; j
++) {
3604 Temp tmp
= it
->second
[start_idx
+ j
];
3605 if (dst_type
== RegType::sgpr
)
3606 tmp
= bld
.as_uniform(tmp
);
3607 vec
->operands
[j
] = Operand(tmp
);
3609 vec
->definitions
[0] = Definition(dst
[i
]);
3610 bld
.insert(std::move(vec
));
3616 if (dst_type
== RegType::sgpr
)
3617 src
= bld
.as_uniform(src
);
3621 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3622 split
->operands
[0] = Operand(src
);
3623 for (unsigned i
= 0; i
< count
; i
++)
3624 split
->definitions
[i
] = Definition(dst
[i
]);
3625 bld
.insert(std::move(split
));
3628 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3629 int *start
, int *count
)
3631 unsigned start_elem
= ffs(todo_mask
) - 1;
3632 bool skip
= !(mask
& (1 << start_elem
));
3634 mask
= ~mask
& todo_mask
;
3638 u_bit_scan_consecutive_range(&mask
, start
, count
);
3643 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3645 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3648 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3649 Temp address
, unsigned base_offset
, unsigned align
)
3651 assert(util_is_power_of_two_nonzero(align
));
3652 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3654 Builder
bld(ctx
->program
, ctx
->block
);
3655 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3656 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3658 unsigned write_count
= 0;
3659 Temp write_datas
[32];
3660 unsigned offsets
[32];
3661 aco_opcode opcodes
[32];
3663 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3665 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3668 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3669 offsets
[write_count
] = offset
;
3670 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3672 advance_write_mask(&todo
, offset
, bytes
);
3676 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3677 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3678 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3679 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3681 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3682 aco_opcode op
= aco_opcode::num_opcodes
;
3683 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3684 op
= aco_opcode::ds_write_b128
;
3686 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3687 op
= aco_opcode::ds_write_b96
;
3689 } else if (bytes
>= 8 && aligned8
) {
3690 op
= aco_opcode::ds_write_b64
;
3692 } else if (bytes
>= 4 && aligned4
) {
3693 op
= aco_opcode::ds_write_b32
;
3695 } else if (bytes
>= 2 && aligned2
) {
3696 op
= aco_opcode::ds_write_b16
;
3698 } else if (bytes
>= 1) {
3699 op
= aco_opcode::ds_write_b8
;
3705 offsets
[write_count
] = offset
;
3706 opcodes
[write_count
] = op
;
3708 advance_write_mask(&todo
, offset
, bytes
);
3711 Operand m
= load_lds_size_m0(bld
);
3713 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3715 for (unsigned i
= 0; i
< write_count
; i
++) {
3716 aco_opcode op
= opcodes
[i
];
3717 if (op
== aco_opcode::num_opcodes
)
3720 Temp data
= write_datas
[i
];
3722 unsigned second
= write_count
;
3723 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3724 for (second
= i
+ 1; second
< write_count
; second
++) {
3725 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3726 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3727 opcodes
[second
] = aco_opcode::num_opcodes
;
3733 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3734 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3736 unsigned inline_offset
= base_offset
+ offsets
[i
];
3737 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3738 Temp address_offset
= address
;
3739 if (inline_offset
> max_offset
) {
3740 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3741 inline_offset
= offsets
[i
];
3743 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3746 Temp second_data
= write_datas
[second
];
3747 inline_offset
/= data
.bytes();
3748 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3750 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3755 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3757 unsigned align
= 16;
3759 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3765 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3770 return aco_opcode::buffer_store_byte
;
3773 return aco_opcode::buffer_store_short
;
3775 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3777 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3780 return aco_opcode::buffer_store_dwordx3
;
3782 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3784 unreachable("Unexpected store size");
3785 return aco_opcode::num_opcodes
;
3788 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3789 Temp data
, unsigned writemask
, int swizzle_element_size
,
3790 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3792 unsigned write_count_with_skips
= 0;
3795 /* determine how to split the data */
3796 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3799 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3800 offsets
[write_count_with_skips
] = offset
;
3801 if (skips
[write_count_with_skips
]) {
3802 advance_write_mask(&todo
, offset
, bytes
);
3803 write_count_with_skips
++;
3807 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3808 * larger than swizzle_element_size */
3809 bytes
= MIN2(bytes
, swizzle_element_size
);
3811 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3813 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3814 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3817 /* dword or larger stores have to be dword-aligned */
3818 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3819 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3820 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3821 if (bytes
>= 4 && !dword_aligned
)
3822 bytes
= MIN2(bytes
, 2);
3824 advance_write_mask(&todo
, offset
, bytes
);
3825 write_count_with_skips
++;
3828 /* actually split data */
3829 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3832 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3835 write_datas
[*write_count
] = write_datas
[i
];
3836 offsets
[*write_count
] = offsets
[i
];
3841 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3842 unsigned split_cnt
= 0u, Temp dst
= Temp())
3844 Builder
bld(ctx
->program
, ctx
->block
);
3845 unsigned dword_size
= elem_size_bytes
/ 4;
3848 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3850 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3851 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3852 instr
->definitions
[0] = Definition(dst
);
3854 for (unsigned i
= 0; i
< cnt
; ++i
) {
3856 assert(arr
[i
].size() == dword_size
);
3857 allocated_vec
[i
] = arr
[i
];
3858 instr
->operands
[i
] = Operand(arr
[i
]);
3860 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3861 allocated_vec
[i
] = zero
;
3862 instr
->operands
[i
] = Operand(zero
);
3866 bld
.insert(std::move(instr
));
3869 emit_split_vector(ctx
, dst
, split_cnt
);
3871 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3876 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3878 if (const_offset
>= 4096) {
3879 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3880 const_offset
%= 4096u;
3883 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3884 else if (unlikely(voffset
.regClass() == s1
))
3885 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3886 else if (likely(voffset
.regClass() == v1
))
3887 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3889 unreachable("Unsupported register class of voffset");
3892 return const_offset
;
3895 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3896 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3899 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3900 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3902 Builder
bld(ctx
->program
, ctx
->block
);
3903 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3904 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3906 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3907 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3908 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3909 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3910 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3912 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3915 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3916 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3917 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3919 Builder
bld(ctx
->program
, ctx
->block
);
3920 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3922 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3924 unsigned write_count
= 0;
3925 Temp write_datas
[32];
3926 unsigned offsets
[32];
3927 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3928 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3930 for (unsigned i
= 0; i
< write_count
; i
++) {
3931 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3932 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3936 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3937 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3938 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3940 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3941 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3942 assert(!!stride
!= allow_combining
);
3944 Builder
bld(ctx
->program
, ctx
->block
);
3946 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3947 info
.component_stride
= allow_combining
? 0 : stride
;
3949 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3950 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3951 info
.align_offset
= 0;
3952 info
.soffset
= soffset
;
3953 info
.const_offset
= base_const_offset
;
3954 emit_mubuf_load(ctx
, bld
, &info
);
3957 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3959 Builder
bld(ctx
->program
, ctx
->block
);
3960 Temp offset
= base_offset
.first
;
3961 unsigned const_offset
= base_offset
.second
;
3963 if (!nir_src_is_const(*off_src
)) {
3964 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3967 /* Calculate indirect offset with stride */
3968 if (likely(indirect_offset_arg
.regClass() == v1
))
3969 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3970 else if (indirect_offset_arg
.regClass() == s1
)
3971 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3973 unreachable("Unsupported register class of indirect offset");
3975 /* Add to the supplied base offset */
3976 if (offset
.id() == 0)
3977 offset
= with_stride
;
3978 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3979 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3980 else if (offset
.size() == 1 && with_stride
.size() == 1)
3981 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3983 unreachable("Unsupported register class of indirect offset");
3985 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3986 const_offset
+= const_offset_arg
* stride
;
3989 return std::make_pair(offset
, const_offset
);
3992 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3994 Builder
bld(ctx
->program
, ctx
->block
);
3997 if (off1
.first
.id() && off2
.first
.id()) {
3998 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3999 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4000 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4001 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4003 unreachable("Unsupported register class of indirect offset");
4005 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4008 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4011 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4013 Builder
bld(ctx
->program
, ctx
->block
);
4014 unsigned const_offset
= offs
.second
* multiplier
;
4016 if (!offs
.first
.id())
4017 return std::make_pair(offs
.first
, const_offset
);
4019 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4020 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4021 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4023 return std::make_pair(offset
, const_offset
);
4026 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4028 Builder
bld(ctx
->program
, ctx
->block
);
4030 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4031 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4032 /* component is in bytes */
4033 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4035 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4036 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4037 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4040 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4042 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4045 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4047 Builder
bld(ctx
->program
, ctx
->block
);
4049 switch (ctx
->shader
->info
.stage
) {
4050 case MESA_SHADER_TESS_CTRL
:
4051 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4052 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4053 case MESA_SHADER_TESS_EVAL
:
4054 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4056 unreachable("Unsupported stage in get_tess_rel_patch_id");
4060 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4062 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4063 Builder
bld(ctx
->program
, ctx
->block
);
4065 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4066 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4068 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4070 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4071 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4073 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4074 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4075 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4077 return offset_mul(ctx
, offs
, 4u);
4080 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4082 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4083 Builder
bld(ctx
->program
, ctx
->block
);
4085 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4086 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4087 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4088 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4090 std::pair
<Temp
, unsigned> offs
= instr
4091 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4092 : std::make_pair(Temp(), 0u);
4094 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4095 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4100 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4101 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4103 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4104 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4106 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4107 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4113 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4115 Builder
bld(ctx
->program
, ctx
->block
);
4117 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4118 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4120 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4122 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4123 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4124 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4126 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4127 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4132 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4134 Builder
bld(ctx
->program
, ctx
->block
);
4136 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4137 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4138 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4139 unsigned attr_stride
= ctx
->tcs_num_patches
;
4141 std::pair
<Temp
, unsigned> offs
= instr
4142 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4143 : std::make_pair(Temp(), 0u);
4145 if (const_base_offset
)
4146 offs
.second
+= const_base_offset
* attr_stride
;
4148 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4149 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4150 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4155 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4157 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4162 unsigned drv_loc
= nir_intrinsic_base(instr
);
4163 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4165 if (!nir_src_is_const(*off_src
)) {
4171 uint64_t slot
= per_vertex
4172 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4173 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4174 return (((uint64_t) 1) << slot
) & mask
;
4177 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4179 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4180 unsigned component
= nir_intrinsic_component(instr
);
4181 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4183 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4184 if (off_instr
->type
!= nir_instr_type_load_const
)
4187 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4188 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4190 if (instr
->src
[0].ssa
->bit_size
== 64)
4191 write_mask
= widen_mask(write_mask
, 2);
4193 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4195 for (unsigned i
= 0; i
< 8; ++i
) {
4196 if (write_mask
& (1 << i
)) {
4197 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4198 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4206 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4208 /* Only TCS per-vertex inputs are supported by this function.
4209 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4211 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4214 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4215 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4216 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4217 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4218 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4219 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4224 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4225 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4226 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4231 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4233 Builder
bld(ctx
->program
, ctx
->block
);
4235 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4236 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4237 bool indirect_write
;
4238 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4239 if (temp_only_input
&& !indirect_write
)
4243 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4244 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4245 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4246 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4248 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4249 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4250 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4251 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4252 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4256 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4257 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4258 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4259 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4260 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4261 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4262 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4263 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4264 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4265 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4266 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4267 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4268 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4270 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4271 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4273 unreachable("Invalid LS or ES stage");
4276 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4277 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4278 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4282 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4287 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4288 return off
== ctx
->tcs_tess_lvl_out_loc
||
4289 off
== ctx
->tcs_tess_lvl_in_loc
;
4293 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4295 uint64_t mask
= per_vertex
4296 ? ctx
->program
->info
->tcs
.tes_inputs_read
4297 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4299 bool indirect_write
= false;
4300 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4301 return indirect_write
|| output_read_by_tes
;
4304 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4306 uint64_t mask
= per_vertex
4307 ? ctx
->shader
->info
.outputs_read
4308 : ctx
->shader
->info
.patch_outputs_read
;
4310 bool indirect_write
= false;
4311 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4312 return indirect_write
|| output_read
;
4315 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4317 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4318 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4320 Builder
bld(ctx
->program
, ctx
->block
);
4322 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4323 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4324 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4326 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4327 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4328 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4330 if (write_to_vmem
) {
4331 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4332 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4333 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4335 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4336 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4337 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4341 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4342 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4343 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4347 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4349 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4350 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4352 Builder
bld(ctx
->program
, ctx
->block
);
4354 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4355 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4356 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4357 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4359 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4362 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4364 if (ctx
->stage
== vertex_vs
||
4365 ctx
->stage
== tess_eval_vs
||
4366 ctx
->stage
== fragment_fs
||
4367 ctx
->stage
== ngg_vertex_gs
||
4368 ctx
->stage
== ngg_tess_eval_gs
||
4369 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4370 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4371 if (!stored_to_temps
) {
4372 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4373 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4374 fprintf(stderr
, "\n");
4377 } else if (ctx
->stage
== vertex_es
||
4378 ctx
->stage
== vertex_ls
||
4379 ctx
->stage
== tess_eval_es
||
4380 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4381 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4382 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4383 visit_store_ls_or_es_output(ctx
, instr
);
4384 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4385 visit_store_tcs_output(ctx
, instr
, false);
4387 unreachable("Shader stage not implemented");
4391 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4393 visit_load_tcs_output(ctx
, instr
, false);
4396 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4398 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4399 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4401 Builder
bld(ctx
->program
, ctx
->block
);
4403 if (dst
.regClass() == v2b
) {
4404 if (ctx
->program
->has_16bank_lds
) {
4405 assert(ctx
->options
->chip_class
<= GFX8
);
4406 Builder::Result interp_p1
=
4407 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4408 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4409 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4410 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4411 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4412 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4414 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4416 if (ctx
->options
->chip_class
== GFX8
)
4417 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4419 Builder::Result interp_p1
=
4420 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4421 coord1
, bld
.m0(prim_mask
), idx
, component
);
4422 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4423 interp_p1
, idx
, component
);
4426 Builder::Result interp_p1
=
4427 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4428 bld
.m0(prim_mask
), idx
, component
);
4430 if (ctx
->program
->has_16bank_lds
)
4431 interp_p1
.instr
->operands
[0].setLateKill(true);
4433 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4434 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4438 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4440 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4441 for (unsigned i
= 0; i
< num_components
; i
++)
4442 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4443 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4444 assert(num_components
== 4);
4445 Builder
bld(ctx
->program
, ctx
->block
);
4446 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4449 for (Operand
& op
: vec
->operands
)
4450 op
= op
.isUndefined() ? Operand(0u) : op
;
4452 vec
->definitions
[0] = Definition(dst
);
4453 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4454 emit_split_vector(ctx
, dst
, num_components
);
4458 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4460 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4461 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4462 unsigned idx
= nir_intrinsic_base(instr
);
4463 unsigned component
= nir_intrinsic_component(instr
);
4464 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4466 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4468 assert(offset
->u32
== 0);
4470 /* the lower 15bit of the prim_mask contain the offset into LDS
4471 * while the upper bits contain the number of prims */
4472 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4473 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4474 Builder
bld(ctx
->program
, ctx
->block
);
4475 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4476 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4477 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4478 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4479 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4482 if (instr
->dest
.ssa
.num_components
== 1) {
4483 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4485 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4486 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4488 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4489 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4490 vec
->operands
[i
] = Operand(tmp
);
4492 vec
->definitions
[0] = Definition(dst
);
4493 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4497 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4498 unsigned offset
, unsigned stride
, unsigned channels
)
4500 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4501 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4503 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4504 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4507 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4508 unsigned offset
, unsigned stride
, unsigned *channels
)
4510 if (!vtx_info
->chan_byte_size
) {
4511 *channels
= vtx_info
->num_channels
;
4512 return vtx_info
->chan_format
;
4515 unsigned num_channels
= *channels
;
4516 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4517 unsigned new_channels
= num_channels
+ 1;
4518 /* first, assume more loads is worse and try using a larger data format */
4519 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4521 /* don't make the attribute potentially out-of-bounds */
4522 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4526 if (new_channels
== 5) {
4527 /* then try decreasing load size (at the cost of more loads) */
4528 new_channels
= *channels
;
4529 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4533 if (new_channels
< *channels
)
4534 *channels
= new_channels
;
4535 num_channels
= new_channels
;
4538 switch (vtx_info
->chan_format
) {
4539 case V_008F0C_BUF_DATA_FORMAT_8
:
4540 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4541 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4542 case V_008F0C_BUF_DATA_FORMAT_16
:
4543 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4544 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4545 case V_008F0C_BUF_DATA_FORMAT_32
:
4546 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4547 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4549 unreachable("shouldn't reach here");
4550 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4553 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4554 * so we may need to fix it up. */
4555 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4557 Builder
bld(ctx
->program
, ctx
->block
);
4559 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4560 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4562 /* For the integer-like cases, do a natural sign extension.
4564 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4565 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4568 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4569 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4571 /* Convert back to the right type. */
4572 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4573 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4574 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4575 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4576 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4577 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4583 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4585 Builder
bld(ctx
->program
, ctx
->block
);
4586 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4587 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4589 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4590 if (off_instr
->type
!= nir_instr_type_load_const
) {
4591 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4592 nir_print_instr(off_instr
, stderr
);
4593 fprintf(stderr
, "\n");
4595 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4597 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4599 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4600 unsigned component
= nir_intrinsic_component(instr
);
4601 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4602 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4603 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4604 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4605 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4607 unsigned dfmt
= attrib_format
& 0xf;
4608 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4609 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4611 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4612 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4613 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4614 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4616 num_channels
= MAX2(num_channels
, 3);
4618 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4619 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4622 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4623 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4624 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4626 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4628 Temp divided
= bld
.tmp(v1
);
4629 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4630 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4632 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4635 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4638 index
= bld
.vadd32(bld
.def(v1
),
4639 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4640 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4643 Temp channels
[num_channels
];
4644 unsigned channel_start
= 0;
4645 bool direct_fetch
= false;
4647 /* skip unused channels at the start */
4648 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4649 channel_start
= ffs(mask
) - 1;
4650 for (unsigned i
= 0; i
< channel_start
; i
++)
4651 channels
[i
] = Temp(0, s1
);
4652 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4653 num_channels
= 3 - (ffs(mask
) - 1);
4657 while (channel_start
< num_channels
) {
4658 unsigned fetch_component
= num_channels
- channel_start
;
4659 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4660 bool expanded
= false;
4662 /* use MUBUF when possible to avoid possible alignment issues */
4663 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4664 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4665 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4666 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4667 vtx_info
->chan_byte_size
== 4;
4668 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4670 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4672 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4673 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4674 fetch_component
= 4;
4679 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4681 Temp fetch_index
= index
;
4682 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4683 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4684 fetch_offset
= fetch_offset
% attrib_stride
;
4687 Operand
soffset(0u);
4688 if (fetch_offset
>= 4096) {
4689 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4690 fetch_offset
%= 4096;
4694 switch (fetch_bytes
) {
4696 assert(!use_mubuf
&& bitsize
== 16);
4697 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4700 if (bitsize
== 16) {
4702 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4704 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4708 assert(!use_mubuf
&& bitsize
== 16);
4709 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4712 if (bitsize
== 16) {
4714 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4716 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4720 assert(ctx
->options
->chip_class
>= GFX7
||
4721 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4722 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4725 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4728 unreachable("Unimplemented load_input vector size");
4732 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4733 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4734 num_channels
<= 3)) {
4735 direct_fetch
= true;
4738 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4742 Instruction
*mubuf
= bld
.mubuf(opcode
,
4743 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4744 fetch_offset
, false, true).instr
;
4745 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4747 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4748 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4749 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4750 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4753 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4755 if (fetch_component
== 1) {
4756 channels
[channel_start
] = fetch_dst
;
4758 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4759 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4760 bitsize
== 16 ? v2b
: v1
);
4763 channel_start
+= fetch_component
;
4766 if (!direct_fetch
) {
4767 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4768 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4770 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4771 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4772 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4774 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4775 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4776 unsigned num_temp
= 0;
4777 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4778 unsigned idx
= i
+ component
;
4779 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4780 Temp channel
= channels
[swizzle
[idx
]];
4781 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4782 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4783 vec
->operands
[i
] = Operand(channel
);
4787 } else if (is_float
&& idx
== 3) {
4788 vec
->operands
[i
] = Operand(0x3f800000u
);
4789 } else if (!is_float
&& idx
== 3) {
4790 vec
->operands
[i
] = Operand(1u);
4792 vec
->operands
[i
] = Operand(0u);
4795 vec
->definitions
[0] = Definition(dst
);
4796 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4797 emit_split_vector(ctx
, dst
, dst
.size());
4799 if (num_temp
== dst
.size())
4800 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4802 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4803 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4804 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4805 if (off_instr
->type
!= nir_instr_type_load_const
||
4806 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4807 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4808 nir_print_instr(off_instr
, stderr
);
4809 fprintf(stderr
, "\n");
4812 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4813 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4815 assert(offset
->u32
== 0);
4817 /* the lower 15bit of the prim_mask contain the offset into LDS
4818 * while the upper bits contain the number of prims */
4819 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4820 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4821 Builder
bld(ctx
->program
, ctx
->block
);
4822 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4823 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4824 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4825 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4826 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4829 unsigned idx
= nir_intrinsic_base(instr
);
4830 unsigned component
= nir_intrinsic_component(instr
);
4831 unsigned vertex_id
= 2; /* P0 */
4833 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4834 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4835 switch (src0
->u32
) {
4837 vertex_id
= 2; /* P0 */
4840 vertex_id
= 0; /* P10 */
4843 vertex_id
= 1; /* P20 */
4846 unreachable("invalid vertex index");
4850 if (dst
.size() == 1) {
4851 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4853 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4854 for (unsigned i
= 0; i
< dst
.size(); i
++)
4855 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4856 vec
->definitions
[0] = Definition(dst
);
4857 bld
.insert(std::move(vec
));
4860 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4861 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4862 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4863 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4864 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4866 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4868 unreachable("Shader stage not implemented");
4872 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4874 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4876 Builder
bld(ctx
->program
, ctx
->block
);
4877 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4880 if (!nir_src_is_const(*vertex_src
)) {
4881 /* better code could be created, but this case probably doesn't happen
4882 * much in practice */
4883 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4884 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4887 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4888 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4890 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4892 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4895 if (vertex_offset
.id()) {
4896 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4897 Operand(i
), indirect_vertex
);
4898 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4900 vertex_offset
= elem
;
4904 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4905 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4907 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4908 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4909 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4910 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4911 Operand((vertex
% 2u) * 16u), Operand(16u));
4913 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4916 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4917 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4918 return offset_mul(ctx
, offs
, 4u);
4921 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4923 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4925 Builder
bld(ctx
->program
, ctx
->block
);
4926 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4927 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4929 if (ctx
->stage
== geometry_gs
) {
4930 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4931 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4932 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4933 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4934 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4935 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4936 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4938 unreachable("Unsupported GS stage.");
4942 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4944 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4946 Builder
bld(ctx
->program
, ctx
->block
);
4947 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4949 if (load_input_from_temps(ctx
, instr
, dst
))
4952 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4953 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4954 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4956 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4959 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4961 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4963 Builder
bld(ctx
->program
, ctx
->block
);
4965 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4966 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4969 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4970 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4972 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4975 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4977 switch (ctx
->shader
->info
.stage
) {
4978 case MESA_SHADER_GEOMETRY
:
4979 visit_load_gs_per_vertex_input(ctx
, instr
);
4981 case MESA_SHADER_TESS_CTRL
:
4982 visit_load_tcs_per_vertex_input(ctx
, instr
);
4984 case MESA_SHADER_TESS_EVAL
:
4985 visit_load_tes_per_vertex_input(ctx
, instr
);
4988 unreachable("Unimplemented shader stage");
4992 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4994 visit_load_tcs_output(ctx
, instr
, true);
4997 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4999 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5000 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5002 visit_store_tcs_output(ctx
, instr
, true);
5005 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5007 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5009 Builder
bld(ctx
->program
, ctx
->block
);
5010 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5012 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5013 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5016 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5017 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5018 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5019 tes_w
= Operand(tmp
);
5022 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5023 emit_split_vector(ctx
, tess_coord
, 3);
5026 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5028 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5029 Builder
bld(ctx
->program
, ctx
->block
);
5030 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5031 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5032 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5035 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5039 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5041 Builder
bld(ctx
->program
, ctx
->block
);
5042 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5043 if (!nir_dest_is_divergent(instr
->dest
))
5044 index
= bld
.as_uniform(index
);
5045 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5046 unsigned binding
= nir_intrinsic_binding(instr
);
5049 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5050 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5051 unsigned offset
= layout
->binding
[binding
].offset
;
5053 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5054 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5055 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5056 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5057 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5060 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5061 stride
= layout
->binding
[binding
].size
;
5064 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5065 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5067 if (nir_const_index
) {
5068 const_index
= const_index
* stride
;
5069 } else if (index
.type() == RegType::vgpr
) {
5070 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5071 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5073 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5077 if (nir_const_index
) {
5078 const_index
= const_index
+ offset
;
5079 } else if (index
.type() == RegType::vgpr
) {
5080 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5082 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5086 if (nir_const_index
&& const_index
== 0) {
5088 } else if (index
.type() == RegType::vgpr
) {
5089 index
= bld
.vadd32(bld
.def(v1
),
5090 nir_const_index
? Operand(const_index
) : Operand(index
),
5093 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5094 nir_const_index
? Operand(const_index
) : Operand(index
),
5098 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5101 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5102 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5103 bool glc
=false, bool readonly
=true)
5105 Builder
bld(ctx
->program
, ctx
->block
);
5107 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5109 offset
= bld
.as_uniform(offset
);
5111 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5113 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5114 info
.can_reorder
= readonly
;
5115 info
.align_mul
= align_mul
;
5116 info
.align_offset
= align_offset
;
5118 emit_smem_load(ctx
, bld
, &info
);
5120 emit_mubuf_load(ctx
, bld
, &info
);
5123 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5125 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5126 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5128 Builder
bld(ctx
->program
, ctx
->block
);
5130 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5131 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5132 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5133 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5135 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5136 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5137 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5138 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5139 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5140 if (ctx
->options
->chip_class
>= GFX10
) {
5141 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5142 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5143 S_008F0C_RESOURCE_LEVEL(1);
5145 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5146 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5148 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5149 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5150 Operand(0xFFFFFFFFu
),
5151 Operand(desc_type
));
5152 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5153 rsrc
, upper_dwords
);
5155 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5156 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5158 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5159 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5160 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5163 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5165 Builder
bld(ctx
->program
, ctx
->block
);
5166 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5167 unsigned offset
= nir_intrinsic_base(instr
);
5168 unsigned count
= instr
->dest
.ssa
.num_components
;
5169 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5171 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5172 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5173 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5174 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5175 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5176 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5177 for (unsigned i
= 0; i
< count
; ++i
) {
5178 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5179 vec
->operands
[i
] = Operand
{elems
[i
]};
5181 vec
->definitions
[0] = Definition(dst
);
5182 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5183 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5188 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5189 if (offset
!= 0) // TODO check if index != 0 as well
5190 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5191 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5194 bool aligned
= true;
5196 if (instr
->dest
.ssa
.bit_size
== 8) {
5197 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5198 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5200 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5201 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5202 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5204 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5209 switch (vec
.size()) {
5211 op
= aco_opcode::s_load_dword
;
5214 op
= aco_opcode::s_load_dwordx2
;
5220 op
= aco_opcode::s_load_dwordx4
;
5226 op
= aco_opcode::s_load_dwordx8
;
5229 unreachable("unimplemented or forbidden load_push_constant.");
5232 bld
.smem(op
, Definition(vec
), ptr
, index
);
5235 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5236 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5241 emit_split_vector(ctx
, vec
, 4);
5242 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5243 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5244 emit_extract_vector(ctx
, vec
, 0, rc
),
5245 emit_extract_vector(ctx
, vec
, 1, rc
),
5246 emit_extract_vector(ctx
, vec
, 2, rc
));
5249 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5252 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5254 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5256 Builder
bld(ctx
->program
, ctx
->block
);
5258 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5259 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5260 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5261 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5262 if (ctx
->options
->chip_class
>= GFX10
) {
5263 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5264 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5265 S_008F0C_RESOURCE_LEVEL(1);
5267 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5268 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5271 unsigned base
= nir_intrinsic_base(instr
);
5272 unsigned range
= nir_intrinsic_range(instr
);
5274 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5275 if (base
&& offset
.type() == RegType::sgpr
)
5276 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5277 else if (base
&& offset
.type() == RegType::vgpr
)
5278 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5280 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5281 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5282 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5283 Operand(desc_type
));
5284 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5285 // TODO: get alignment information for subdword constants
5286 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5289 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5291 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5292 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5294 ctx
->program
->needs_exact
= true;
5296 // TODO: optimize uniform conditions
5297 Builder
bld(ctx
->program
, ctx
->block
);
5298 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5299 assert(src
.regClass() == bld
.lm
);
5300 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5301 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5302 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5306 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5308 Builder
bld(ctx
->program
, ctx
->block
);
5310 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5311 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5313 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5314 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5316 if (ctx
->block
->loop_nest_depth
&&
5317 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5318 /* we handle discards the same way as jump instructions */
5319 append_logical_end(ctx
->block
);
5321 /* in loops, discard behaves like break */
5322 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5323 ctx
->block
->kind
|= block_kind_discard
;
5326 /* uniform discard - loop ends here */
5327 assert(nir_instr_is_last(&instr
->instr
));
5328 ctx
->block
->kind
|= block_kind_uniform
;
5329 ctx
->cf_info
.has_branch
= true;
5330 bld
.branch(aco_opcode::p_branch
);
5331 add_linear_edge(ctx
->block
->index
, linear_target
);
5335 /* we add a break right behind the discard() instructions */
5336 ctx
->block
->kind
|= block_kind_break
;
5337 unsigned idx
= ctx
->block
->index
;
5339 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5340 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5342 /* remove critical edges from linear CFG */
5343 bld
.branch(aco_opcode::p_branch
);
5344 Block
* break_block
= ctx
->program
->create_and_insert_block();
5345 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5346 break_block
->kind
|= block_kind_uniform
;
5347 add_linear_edge(idx
, break_block
);
5348 add_linear_edge(break_block
->index
, linear_target
);
5349 bld
.reset(break_block
);
5350 bld
.branch(aco_opcode::p_branch
);
5352 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5353 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5354 add_linear_edge(idx
, continue_block
);
5355 append_logical_start(continue_block
);
5356 ctx
->block
= continue_block
;
5361 /* it can currently happen that NIR doesn't remove the unreachable code */
5362 if (!nir_instr_is_last(&instr
->instr
)) {
5363 ctx
->program
->needs_exact
= true;
5364 /* save exec somewhere temporarily so that it doesn't get
5365 * overwritten before the discard from outer exec masks */
5366 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5367 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5368 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5372 /* This condition is incorrect for uniformly branched discards in a loop
5373 * predicated by a divergent condition, but the above code catches that case
5374 * and the discard would end up turning into a discard_if.
5384 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5385 /* program just ends here */
5386 ctx
->block
->kind
|= block_kind_uniform
;
5387 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5388 0 /* enabled mask */, 9 /* dest */,
5389 false /* compressed */, true/* done */, true /* valid mask */);
5390 bld
.sopp(aco_opcode::s_endpgm
);
5391 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5393 ctx
->block
->kind
|= block_kind_discard
;
5394 /* branch and linear edge is added by visit_if() */
5398 enum aco_descriptor_type
{
5409 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5410 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5412 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5413 return dim
== ac_image_cube
||
5414 dim
== ac_image_1darray
||
5415 dim
== ac_image_2darray
||
5416 dim
== ac_image_2darraymsaa
;
5419 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5420 enum aco_descriptor_type desc_type
,
5421 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5423 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5424 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5425 if (it != ctx->tex_desc.end())
5428 Temp index
= Temp();
5429 bool index_set
= false;
5430 unsigned constant_index
= 0;
5431 unsigned descriptor_set
;
5432 unsigned base_index
;
5433 Builder
bld(ctx
->program
, ctx
->block
);
5436 assert(tex_instr
&& !image
);
5438 base_index
= tex_instr
->sampler_index
;
5440 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5441 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5445 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5446 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5448 constant_index
+= array_size
* const_value
->u32
;
5450 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5451 if (indirect
.type() == RegType::vgpr
)
5452 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5454 if (array_size
!= 1)
5455 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5461 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5465 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5467 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5468 base_index
= deref_instr
->var
->data
.binding
;
5471 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5472 list
= convert_pointer_to_64_bit(ctx
, list
);
5474 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5475 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5476 unsigned offset
= binding
->offset
;
5477 unsigned stride
= binding
->size
;
5481 assert(base_index
< layout
->binding_count
);
5483 switch (desc_type
) {
5484 case ACO_DESC_IMAGE
:
5486 opcode
= aco_opcode::s_load_dwordx8
;
5488 case ACO_DESC_FMASK
:
5490 opcode
= aco_opcode::s_load_dwordx8
;
5493 case ACO_DESC_SAMPLER
:
5495 opcode
= aco_opcode::s_load_dwordx4
;
5496 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5497 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5499 case ACO_DESC_BUFFER
:
5501 opcode
= aco_opcode::s_load_dwordx4
;
5503 case ACO_DESC_PLANE_0
:
5504 case ACO_DESC_PLANE_1
:
5506 opcode
= aco_opcode::s_load_dwordx8
;
5507 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5509 case ACO_DESC_PLANE_2
:
5511 opcode
= aco_opcode::s_load_dwordx4
;
5515 unreachable("invalid desc_type\n");
5518 offset
+= constant_index
* stride
;
5520 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5521 (!index_set
|| binding
->immutable_samplers_equal
)) {
5522 if (binding
->immutable_samplers_equal
)
5525 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5526 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5527 Operand(samplers
[constant_index
* 4 + 0]),
5528 Operand(samplers
[constant_index
* 4 + 1]),
5529 Operand(samplers
[constant_index
* 4 + 2]),
5530 Operand(samplers
[constant_index
* 4 + 3]));
5535 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5537 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5538 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5541 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5543 if (desc_type
== ACO_DESC_PLANE_2
) {
5545 for (unsigned i
= 0; i
< 8; i
++)
5546 components
[i
] = bld
.tmp(s1
);
5547 bld
.pseudo(aco_opcode::p_split_vector
,
5548 Definition(components
[0]),
5549 Definition(components
[1]),
5550 Definition(components
[2]),
5551 Definition(components
[3]),
5554 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5555 bld
.pseudo(aco_opcode::p_split_vector
,
5556 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5557 Definition(components
[4]),
5558 Definition(components
[5]),
5559 Definition(components
[6]),
5560 Definition(components
[7]),
5563 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5564 components
[0], components
[1], components
[2], components
[3],
5565 components
[4], components
[5], components
[6], components
[7]);
5571 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5574 case GLSL_SAMPLER_DIM_BUF
:
5576 case GLSL_SAMPLER_DIM_1D
:
5577 return array
? 2 : 1;
5578 case GLSL_SAMPLER_DIM_2D
:
5579 return array
? 3 : 2;
5580 case GLSL_SAMPLER_DIM_MS
:
5581 return array
? 4 : 3;
5582 case GLSL_SAMPLER_DIM_3D
:
5583 case GLSL_SAMPLER_DIM_CUBE
:
5585 case GLSL_SAMPLER_DIM_RECT
:
5586 case GLSL_SAMPLER_DIM_SUBPASS
:
5588 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5597 /* Adjust the sample index according to FMASK.
5599 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5600 * which is the identity mapping. Each nibble says which physical sample
5601 * should be fetched to get that sample.
5603 * For example, 0x11111100 means there are only 2 samples stored and
5604 * the second sample covers 3/4 of the pixel. When reading samples 0
5605 * and 1, return physical sample 0 (determined by the first two 0s
5606 * in FMASK), otherwise return physical sample 1.
5608 * The sample index should be adjusted as follows:
5609 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5611 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5613 Builder
bld(ctx
->program
, ctx
->block
);
5614 Temp fmask
= bld
.tmp(v1
);
5615 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5616 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5619 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5620 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5621 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5622 load
->operands
[0] = Operand(fmask_desc_ptr
);
5623 load
->operands
[1] = Operand(s4
); /* no sampler */
5624 load
->operands
[2] = Operand(coord
);
5625 load
->definitions
[0] = Definition(fmask
);
5632 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5633 ctx
->block
->instructions
.emplace_back(std::move(load
));
5635 Operand sample_index4
;
5636 if (sample_index
.isConstant()) {
5637 if (sample_index
.constantValue() < 16) {
5638 sample_index4
= Operand(sample_index
.constantValue() << 2);
5640 sample_index4
= Operand(0u);
5642 } else if (sample_index
.regClass() == s1
) {
5643 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5645 assert(sample_index
.regClass() == v1
);
5646 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5650 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5651 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5652 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5653 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5655 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5657 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5658 * resource descriptor is 0 (invalid),
5660 Temp compare
= bld
.tmp(bld
.lm
);
5661 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5662 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5664 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5666 /* Replace the MSAA sample index. */
5667 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5670 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5673 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5674 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5675 bool is_array
= glsl_sampler_type_is_array(type
);
5676 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5677 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5678 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5679 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5680 int count
= image_type_to_components_count(dim
, is_array
);
5681 std::vector
<Temp
> coords(count
);
5682 Builder
bld(ctx
->program
, ctx
->block
);
5686 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5687 /* get sample index */
5688 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5689 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5690 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5691 std::vector
<Temp
> fmask_load_address
;
5692 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5693 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5695 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5696 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5698 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5703 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5704 coords
.resize(coords
.size() + 1);
5705 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5707 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5709 for (int i
= 0; i
< count
; i
++)
5710 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5713 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5714 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5715 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5716 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5719 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5722 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5723 for (unsigned i
= 0; i
< coords
.size(); i
++)
5724 vec
->operands
[i
] = Operand(coords
[i
]);
5725 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5726 vec
->definitions
[0] = Definition(res
);
5727 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5732 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5734 Builder
bld(ctx
->program
, ctx
->block
);
5735 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5736 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5737 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5738 bool is_array
= glsl_sampler_type_is_array(type
);
5739 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5741 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5742 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5743 unsigned num_channels
= util_last_bit(mask
);
5744 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5745 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5748 switch (num_channels
) {
5750 opcode
= aco_opcode::buffer_load_format_x
;
5753 opcode
= aco_opcode::buffer_load_format_xy
;
5756 opcode
= aco_opcode::buffer_load_format_xyz
;
5759 opcode
= aco_opcode::buffer_load_format_xyzw
;
5762 unreachable(">4 channel buffer image load");
5764 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5765 load
->operands
[0] = Operand(rsrc
);
5766 load
->operands
[1] = Operand(vindex
);
5767 load
->operands
[2] = Operand((uint32_t) 0);
5769 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5772 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5773 load
->definitions
[0] = Definition(tmp
);
5775 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5776 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5777 load
->barrier
= barrier_image
;
5778 ctx
->block
->instructions
.emplace_back(std::move(load
));
5780 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5784 Temp coords
= get_image_coords(ctx
, instr
, type
);
5785 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5787 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5788 unsigned num_components
= util_bitcount(dmask
);
5790 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5793 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5795 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5796 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5798 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5799 load
->operands
[0] = Operand(resource
);
5800 load
->operands
[1] = Operand(s4
); /* no sampler */
5801 load
->operands
[2] = Operand(coords
);
5802 load
->definitions
[0] = Definition(tmp
);
5803 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5804 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5805 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5806 load
->dmask
= dmask
;
5808 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5809 load
->barrier
= barrier_image
;
5810 ctx
->block
->instructions
.emplace_back(std::move(load
));
5812 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5816 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5818 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5819 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5820 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5821 bool is_array
= glsl_sampler_type_is_array(type
);
5822 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5824 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5826 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5827 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5828 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5830 switch (data
.size()) {
5832 opcode
= aco_opcode::buffer_store_format_x
;
5835 opcode
= aco_opcode::buffer_store_format_xy
;
5838 opcode
= aco_opcode::buffer_store_format_xyz
;
5841 opcode
= aco_opcode::buffer_store_format_xyzw
;
5844 unreachable(">4 channel buffer image store");
5846 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5847 store
->operands
[0] = Operand(rsrc
);
5848 store
->operands
[1] = Operand(vindex
);
5849 store
->operands
[2] = Operand((uint32_t) 0);
5850 store
->operands
[3] = Operand(data
);
5851 store
->idxen
= true;
5854 store
->disable_wqm
= true;
5855 store
->barrier
= barrier_image
;
5856 ctx
->program
->needs_exact
= true;
5857 ctx
->block
->instructions
.emplace_back(std::move(store
));
5861 assert(data
.type() == RegType::vgpr
);
5862 Temp coords
= get_image_coords(ctx
, instr
, type
);
5863 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5865 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5866 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5868 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5869 store
->operands
[0] = Operand(resource
);
5870 store
->operands
[1] = Operand(data
);
5871 store
->operands
[2] = Operand(coords
);
5874 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5875 store
->dmask
= (1 << data
.size()) - 1;
5877 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5878 store
->disable_wqm
= true;
5879 store
->barrier
= barrier_image
;
5880 ctx
->program
->needs_exact
= true;
5881 ctx
->block
->instructions
.emplace_back(std::move(store
));
5885 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5887 /* return the previous value if dest is ever used */
5888 bool return_previous
= false;
5889 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5890 return_previous
= true;
5893 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5894 return_previous
= true;
5898 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5899 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5900 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5901 bool is_array
= glsl_sampler_type_is_array(type
);
5902 Builder
bld(ctx
->program
, ctx
->block
);
5904 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5905 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5907 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5908 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5910 aco_opcode buf_op
, image_op
;
5911 switch (instr
->intrinsic
) {
5912 case nir_intrinsic_image_deref_atomic_add
:
5913 buf_op
= aco_opcode::buffer_atomic_add
;
5914 image_op
= aco_opcode::image_atomic_add
;
5916 case nir_intrinsic_image_deref_atomic_umin
:
5917 buf_op
= aco_opcode::buffer_atomic_umin
;
5918 image_op
= aco_opcode::image_atomic_umin
;
5920 case nir_intrinsic_image_deref_atomic_imin
:
5921 buf_op
= aco_opcode::buffer_atomic_smin
;
5922 image_op
= aco_opcode::image_atomic_smin
;
5924 case nir_intrinsic_image_deref_atomic_umax
:
5925 buf_op
= aco_opcode::buffer_atomic_umax
;
5926 image_op
= aco_opcode::image_atomic_umax
;
5928 case nir_intrinsic_image_deref_atomic_imax
:
5929 buf_op
= aco_opcode::buffer_atomic_smax
;
5930 image_op
= aco_opcode::image_atomic_smax
;
5932 case nir_intrinsic_image_deref_atomic_and
:
5933 buf_op
= aco_opcode::buffer_atomic_and
;
5934 image_op
= aco_opcode::image_atomic_and
;
5936 case nir_intrinsic_image_deref_atomic_or
:
5937 buf_op
= aco_opcode::buffer_atomic_or
;
5938 image_op
= aco_opcode::image_atomic_or
;
5940 case nir_intrinsic_image_deref_atomic_xor
:
5941 buf_op
= aco_opcode::buffer_atomic_xor
;
5942 image_op
= aco_opcode::image_atomic_xor
;
5944 case nir_intrinsic_image_deref_atomic_exchange
:
5945 buf_op
= aco_opcode::buffer_atomic_swap
;
5946 image_op
= aco_opcode::image_atomic_swap
;
5948 case nir_intrinsic_image_deref_atomic_comp_swap
:
5949 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5950 image_op
= aco_opcode::image_atomic_cmpswap
;
5953 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5956 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5958 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5959 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5960 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5961 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5962 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5963 mubuf
->operands
[0] = Operand(resource
);
5964 mubuf
->operands
[1] = Operand(vindex
);
5965 mubuf
->operands
[2] = Operand((uint32_t)0);
5966 mubuf
->operands
[3] = Operand(data
);
5967 if (return_previous
)
5968 mubuf
->definitions
[0] = Definition(dst
);
5970 mubuf
->idxen
= true;
5971 mubuf
->glc
= return_previous
;
5972 mubuf
->dlc
= false; /* Not needed for atomics */
5973 mubuf
->disable_wqm
= true;
5974 mubuf
->barrier
= barrier_image
;
5975 ctx
->program
->needs_exact
= true;
5976 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5980 Temp coords
= get_image_coords(ctx
, instr
, type
);
5981 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5982 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5983 mimg
->operands
[0] = Operand(resource
);
5984 mimg
->operands
[1] = Operand(data
);
5985 mimg
->operands
[2] = Operand(coords
);
5986 if (return_previous
)
5987 mimg
->definitions
[0] = Definition(dst
);
5988 mimg
->glc
= return_previous
;
5989 mimg
->dlc
= false; /* Not needed for atomics */
5990 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5991 mimg
->dmask
= (1 << data
.size()) - 1;
5993 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5994 mimg
->disable_wqm
= true;
5995 mimg
->barrier
= barrier_image
;
5996 ctx
->program
->needs_exact
= true;
5997 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6001 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6003 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6004 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6005 Builder
bld(ctx
->program
, ctx
->block
);
6007 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6009 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6010 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6012 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6013 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6015 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6016 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6018 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6019 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6020 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6021 if (dst
.type() == RegType::vgpr
)
6022 bld
.copy(Definition(dst
), shr_dst
);
6024 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6026 emit_extract_vector(ctx
, desc
, 2, dst
);
6030 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6032 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6033 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6034 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6035 bool is_array
= glsl_sampler_type_is_array(type
);
6036 Builder
bld(ctx
->program
, ctx
->block
);
6038 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6039 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6040 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6044 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6047 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6049 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6051 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6052 mimg
->operands
[0] = Operand(resource
);
6053 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6054 mimg
->operands
[2] = Operand(lod
);
6055 uint8_t& dmask
= mimg
->dmask
;
6056 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6057 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6058 mimg
->da
= glsl_sampler_type_is_array(type
);
6059 mimg
->can_reorder
= true;
6060 Definition
& def
= mimg
->definitions
[0];
6061 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6063 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6064 glsl_sampler_type_is_array(type
)) {
6066 assert(instr
->dest
.ssa
.num_components
== 3);
6067 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6068 def
= Definition(tmp
);
6069 emit_split_vector(ctx
, tmp
, 3);
6071 /* divide 3rd value by 6 by multiplying with magic number */
6072 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6073 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6075 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6076 emit_extract_vector(ctx
, tmp
, 0, v1
),
6077 emit_extract_vector(ctx
, tmp
, 1, v1
),
6080 } else if (ctx
->options
->chip_class
== GFX9
&&
6081 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6082 glsl_sampler_type_is_array(type
)) {
6083 assert(instr
->dest
.ssa
.num_components
== 2);
6084 def
= Definition(dst
);
6087 def
= Definition(dst
);
6090 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6093 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6095 Builder
bld(ctx
->program
, ctx
->block
);
6096 unsigned num_components
= instr
->num_components
;
6098 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6099 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6100 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6102 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6103 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6104 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6105 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6108 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6110 Builder
bld(ctx
->program
, ctx
->block
);
6111 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6112 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6113 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6114 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6116 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6117 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6119 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6120 ctx
->options
->chip_class
>= GFX8
&&
6121 elem_size_bytes
>= 4;
6123 offset
= bld
.as_uniform(offset
);
6124 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6126 unsigned write_count
= 0;
6127 Temp write_datas
[32];
6128 unsigned offsets
[32];
6129 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6130 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6132 for (unsigned i
= 0; i
< write_count
; i
++) {
6133 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6134 if (smem
&& ctx
->stage
== fragment_fs
)
6135 op
= aco_opcode::p_fs_buffer_store_smem
;
6138 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6139 store
->operands
[0] = Operand(rsrc
);
6141 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6142 offset
, Operand(offsets
[i
]));
6143 store
->operands
[1] = Operand(off
);
6145 store
->operands
[1] = Operand(offset
);
6147 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6148 store
->operands
[1].setFixed(m0
);
6149 store
->operands
[2] = Operand(write_datas
[i
]);
6150 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6152 store
->disable_wqm
= true;
6153 store
->barrier
= barrier_buffer
;
6154 ctx
->block
->instructions
.emplace_back(std::move(store
));
6155 ctx
->program
->wb_smem_l1_on_end
= true;
6156 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6157 ctx
->block
->kind
|= block_kind_needs_lowering
;
6158 ctx
->program
->needs_exact
= true;
6161 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6162 store
->operands
[0] = Operand(rsrc
);
6163 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6164 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6165 store
->operands
[3] = Operand(write_datas
[i
]);
6166 store
->offset
= offsets
[i
];
6167 store
->offen
= (offset
.type() == RegType::vgpr
);
6168 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6170 store
->disable_wqm
= true;
6171 store
->barrier
= barrier_buffer
;
6172 ctx
->program
->needs_exact
= true;
6173 ctx
->block
->instructions
.emplace_back(std::move(store
));
6178 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6180 /* return the previous value if dest is ever used */
6181 bool return_previous
= false;
6182 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6183 return_previous
= true;
6186 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6187 return_previous
= true;
6191 Builder
bld(ctx
->program
, ctx
->block
);
6192 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6194 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6195 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6196 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6198 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6199 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6200 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6202 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6204 aco_opcode op32
, op64
;
6205 switch (instr
->intrinsic
) {
6206 case nir_intrinsic_ssbo_atomic_add
:
6207 op32
= aco_opcode::buffer_atomic_add
;
6208 op64
= aco_opcode::buffer_atomic_add_x2
;
6210 case nir_intrinsic_ssbo_atomic_imin
:
6211 op32
= aco_opcode::buffer_atomic_smin
;
6212 op64
= aco_opcode::buffer_atomic_smin_x2
;
6214 case nir_intrinsic_ssbo_atomic_umin
:
6215 op32
= aco_opcode::buffer_atomic_umin
;
6216 op64
= aco_opcode::buffer_atomic_umin_x2
;
6218 case nir_intrinsic_ssbo_atomic_imax
:
6219 op32
= aco_opcode::buffer_atomic_smax
;
6220 op64
= aco_opcode::buffer_atomic_smax_x2
;
6222 case nir_intrinsic_ssbo_atomic_umax
:
6223 op32
= aco_opcode::buffer_atomic_umax
;
6224 op64
= aco_opcode::buffer_atomic_umax_x2
;
6226 case nir_intrinsic_ssbo_atomic_and
:
6227 op32
= aco_opcode::buffer_atomic_and
;
6228 op64
= aco_opcode::buffer_atomic_and_x2
;
6230 case nir_intrinsic_ssbo_atomic_or
:
6231 op32
= aco_opcode::buffer_atomic_or
;
6232 op64
= aco_opcode::buffer_atomic_or_x2
;
6234 case nir_intrinsic_ssbo_atomic_xor
:
6235 op32
= aco_opcode::buffer_atomic_xor
;
6236 op64
= aco_opcode::buffer_atomic_xor_x2
;
6238 case nir_intrinsic_ssbo_atomic_exchange
:
6239 op32
= aco_opcode::buffer_atomic_swap
;
6240 op64
= aco_opcode::buffer_atomic_swap_x2
;
6242 case nir_intrinsic_ssbo_atomic_comp_swap
:
6243 op32
= aco_opcode::buffer_atomic_cmpswap
;
6244 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6247 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6249 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6250 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6251 mubuf
->operands
[0] = Operand(rsrc
);
6252 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6253 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6254 mubuf
->operands
[3] = Operand(data
);
6255 if (return_previous
)
6256 mubuf
->definitions
[0] = Definition(dst
);
6258 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6259 mubuf
->glc
= return_previous
;
6260 mubuf
->dlc
= false; /* Not needed for atomics */
6261 mubuf
->disable_wqm
= true;
6262 mubuf
->barrier
= barrier_buffer
;
6263 ctx
->program
->needs_exact
= true;
6264 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6267 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6269 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6270 Builder
bld(ctx
->program
, ctx
->block
);
6271 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6272 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6275 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6277 Builder
bld(ctx
->program
, ctx
->block
);
6278 unsigned num_components
= instr
->num_components
;
6279 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6281 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6282 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6283 num_components
, component_size
};
6284 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6285 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6286 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6287 info
.barrier
= barrier_buffer
;
6288 info
.can_reorder
= false;
6289 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6290 * it's safe to use SMEM */
6291 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6292 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6293 emit_global_load(ctx
, bld
, &info
);
6295 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6296 emit_smem_load(ctx
, bld
, &info
);
6300 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6302 Builder
bld(ctx
->program
, ctx
->block
);
6303 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6304 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6306 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6307 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6308 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6310 if (ctx
->options
->chip_class
>= GFX7
)
6311 addr
= as_vgpr(ctx
, addr
);
6313 unsigned write_count
= 0;
6314 Temp write_datas
[32];
6315 unsigned offsets
[32];
6316 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6317 16, &write_count
, write_datas
, offsets
);
6319 for (unsigned i
= 0; i
< write_count
; i
++) {
6320 if (ctx
->options
->chip_class
>= GFX7
) {
6321 unsigned offset
= offsets
[i
];
6322 Temp store_addr
= addr
;
6323 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6324 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6325 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6326 Temp carry
= bld
.tmp(bld
.lm
);
6327 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6329 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6330 Operand(offset
), addr0
);
6331 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6333 carry
).def(1).setHint(vcc
);
6335 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6340 bool global
= ctx
->options
->chip_class
>= GFX9
;
6342 switch (write_datas
[i
].bytes()) {
6344 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6347 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6350 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6353 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6356 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6359 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6362 unreachable("store_global not implemented for this size.");
6365 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6366 flat
->operands
[0] = Operand(store_addr
);
6367 flat
->operands
[1] = Operand(s1
);
6368 flat
->operands
[2] = Operand(write_datas
[i
]);
6371 flat
->offset
= offset
;
6372 flat
->disable_wqm
= true;
6373 flat
->barrier
= barrier_buffer
;
6374 ctx
->program
->needs_exact
= true;
6375 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6377 assert(ctx
->options
->chip_class
== GFX6
);
6379 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6381 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6383 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6384 mubuf
->operands
[0] = Operand(rsrc
);
6385 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6386 mubuf
->operands
[2] = Operand(0u);
6387 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6390 mubuf
->offset
= offsets
[i
];
6391 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6392 mubuf
->disable_wqm
= true;
6393 mubuf
->barrier
= barrier_buffer
;
6394 ctx
->program
->needs_exact
= true;
6395 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6400 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6402 /* return the previous value if dest is ever used */
6403 bool return_previous
= false;
6404 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6405 return_previous
= true;
6408 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6409 return_previous
= true;
6413 Builder
bld(ctx
->program
, ctx
->block
);
6414 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6415 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6417 if (ctx
->options
->chip_class
>= GFX7
)
6418 addr
= as_vgpr(ctx
, addr
);
6420 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6421 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6422 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6424 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6426 aco_opcode op32
, op64
;
6428 if (ctx
->options
->chip_class
>= GFX7
) {
6429 bool global
= ctx
->options
->chip_class
>= GFX9
;
6430 switch (instr
->intrinsic
) {
6431 case nir_intrinsic_global_atomic_add
:
6432 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6433 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6435 case nir_intrinsic_global_atomic_imin
:
6436 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6437 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6439 case nir_intrinsic_global_atomic_umin
:
6440 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6441 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6443 case nir_intrinsic_global_atomic_imax
:
6444 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6445 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6447 case nir_intrinsic_global_atomic_umax
:
6448 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6449 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6451 case nir_intrinsic_global_atomic_and
:
6452 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6453 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6455 case nir_intrinsic_global_atomic_or
:
6456 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6457 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6459 case nir_intrinsic_global_atomic_xor
:
6460 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6461 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6463 case nir_intrinsic_global_atomic_exchange
:
6464 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6465 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6467 case nir_intrinsic_global_atomic_comp_swap
:
6468 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6469 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6472 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6475 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6476 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6477 flat
->operands
[0] = Operand(addr
);
6478 flat
->operands
[1] = Operand(s1
);
6479 flat
->operands
[2] = Operand(data
);
6480 if (return_previous
)
6481 flat
->definitions
[0] = Definition(dst
);
6482 flat
->glc
= return_previous
;
6483 flat
->dlc
= false; /* Not needed for atomics */
6485 flat
->disable_wqm
= true;
6486 flat
->barrier
= barrier_buffer
;
6487 ctx
->program
->needs_exact
= true;
6488 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6490 assert(ctx
->options
->chip_class
== GFX6
);
6492 switch (instr
->intrinsic
) {
6493 case nir_intrinsic_global_atomic_add
:
6494 op32
= aco_opcode::buffer_atomic_add
;
6495 op64
= aco_opcode::buffer_atomic_add_x2
;
6497 case nir_intrinsic_global_atomic_imin
:
6498 op32
= aco_opcode::buffer_atomic_smin
;
6499 op64
= aco_opcode::buffer_atomic_smin_x2
;
6501 case nir_intrinsic_global_atomic_umin
:
6502 op32
= aco_opcode::buffer_atomic_umin
;
6503 op64
= aco_opcode::buffer_atomic_umin_x2
;
6505 case nir_intrinsic_global_atomic_imax
:
6506 op32
= aco_opcode::buffer_atomic_smax
;
6507 op64
= aco_opcode::buffer_atomic_smax_x2
;
6509 case nir_intrinsic_global_atomic_umax
:
6510 op32
= aco_opcode::buffer_atomic_umax
;
6511 op64
= aco_opcode::buffer_atomic_umax_x2
;
6513 case nir_intrinsic_global_atomic_and
:
6514 op32
= aco_opcode::buffer_atomic_and
;
6515 op64
= aco_opcode::buffer_atomic_and_x2
;
6517 case nir_intrinsic_global_atomic_or
:
6518 op32
= aco_opcode::buffer_atomic_or
;
6519 op64
= aco_opcode::buffer_atomic_or_x2
;
6521 case nir_intrinsic_global_atomic_xor
:
6522 op32
= aco_opcode::buffer_atomic_xor
;
6523 op64
= aco_opcode::buffer_atomic_xor_x2
;
6525 case nir_intrinsic_global_atomic_exchange
:
6526 op32
= aco_opcode::buffer_atomic_swap
;
6527 op64
= aco_opcode::buffer_atomic_swap_x2
;
6529 case nir_intrinsic_global_atomic_comp_swap
:
6530 op32
= aco_opcode::buffer_atomic_cmpswap
;
6531 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6534 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6537 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6539 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6541 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6542 mubuf
->operands
[0] = Operand(rsrc
);
6543 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6544 mubuf
->operands
[2] = Operand(0u);
6545 mubuf
->operands
[3] = Operand(data
);
6546 if (return_previous
)
6547 mubuf
->definitions
[0] = Definition(dst
);
6548 mubuf
->glc
= return_previous
;
6551 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6552 mubuf
->disable_wqm
= true;
6553 mubuf
->barrier
= barrier_buffer
;
6554 ctx
->program
->needs_exact
= true;
6555 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6559 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6560 Builder
bld(ctx
->program
, ctx
->block
);
6561 switch(instr
->intrinsic
) {
6562 case nir_intrinsic_group_memory_barrier
:
6563 case nir_intrinsic_memory_barrier
:
6564 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6566 case nir_intrinsic_memory_barrier_buffer
:
6567 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6569 case nir_intrinsic_memory_barrier_image
:
6570 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6572 case nir_intrinsic_memory_barrier_tcs_patch
:
6573 case nir_intrinsic_memory_barrier_shared
:
6574 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6577 unreachable("Unimplemented memory barrier intrinsic");
6582 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6584 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6585 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6586 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6587 Builder
bld(ctx
->program
, ctx
->block
);
6589 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6590 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6591 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6594 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6596 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6597 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6598 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6599 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6601 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6602 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6605 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6607 unsigned offset
= nir_intrinsic_base(instr
);
6608 Builder
bld(ctx
->program
, ctx
->block
);
6609 Operand m
= load_lds_size_m0(bld
);
6610 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6611 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6613 unsigned num_operands
= 3;
6614 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6615 switch(instr
->intrinsic
) {
6616 case nir_intrinsic_shared_atomic_add
:
6617 op32
= aco_opcode::ds_add_u32
;
6618 op64
= aco_opcode::ds_add_u64
;
6619 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6620 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6622 case nir_intrinsic_shared_atomic_imin
:
6623 op32
= aco_opcode::ds_min_i32
;
6624 op64
= aco_opcode::ds_min_i64
;
6625 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6626 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6628 case nir_intrinsic_shared_atomic_umin
:
6629 op32
= aco_opcode::ds_min_u32
;
6630 op64
= aco_opcode::ds_min_u64
;
6631 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6632 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6634 case nir_intrinsic_shared_atomic_imax
:
6635 op32
= aco_opcode::ds_max_i32
;
6636 op64
= aco_opcode::ds_max_i64
;
6637 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6638 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6640 case nir_intrinsic_shared_atomic_umax
:
6641 op32
= aco_opcode::ds_max_u32
;
6642 op64
= aco_opcode::ds_max_u64
;
6643 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6644 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6646 case nir_intrinsic_shared_atomic_and
:
6647 op32
= aco_opcode::ds_and_b32
;
6648 op64
= aco_opcode::ds_and_b64
;
6649 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6650 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6652 case nir_intrinsic_shared_atomic_or
:
6653 op32
= aco_opcode::ds_or_b32
;
6654 op64
= aco_opcode::ds_or_b64
;
6655 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6656 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6658 case nir_intrinsic_shared_atomic_xor
:
6659 op32
= aco_opcode::ds_xor_b32
;
6660 op64
= aco_opcode::ds_xor_b64
;
6661 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6662 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6664 case nir_intrinsic_shared_atomic_exchange
:
6665 op32
= aco_opcode::ds_write_b32
;
6666 op64
= aco_opcode::ds_write_b64
;
6667 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6668 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6670 case nir_intrinsic_shared_atomic_comp_swap
:
6671 op32
= aco_opcode::ds_cmpst_b32
;
6672 op64
= aco_opcode::ds_cmpst_b64
;
6673 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6674 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6678 unreachable("Unhandled shared atomic intrinsic");
6681 /* return the previous value if dest is ever used */
6682 bool return_previous
= false;
6683 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6684 return_previous
= true;
6687 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6688 return_previous
= true;
6693 if (data
.size() == 1) {
6694 assert(instr
->dest
.ssa
.bit_size
== 32);
6695 op
= return_previous
? op32_rtn
: op32
;
6697 assert(instr
->dest
.ssa
.bit_size
== 64);
6698 op
= return_previous
? op64_rtn
: op64
;
6701 if (offset
> 65535) {
6702 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6706 aco_ptr
<DS_instruction
> ds
;
6707 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6708 ds
->operands
[0] = Operand(address
);
6709 ds
->operands
[1] = Operand(data
);
6710 if (num_operands
== 4)
6711 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6712 ds
->operands
[num_operands
- 1] = m
;
6713 ds
->offset0
= offset
;
6714 if (return_previous
)
6715 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6716 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6719 Temp
get_scratch_resource(isel_context
*ctx
)
6721 Builder
bld(ctx
->program
, ctx
->block
);
6722 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6723 if (ctx
->stage
!= compute_cs
)
6724 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6726 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6727 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6729 if (ctx
->program
->chip_class
>= GFX10
) {
6730 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6731 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6732 S_008F0C_RESOURCE_LEVEL(1);
6733 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6734 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6735 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6738 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6739 if (ctx
->program
->chip_class
<= GFX8
)
6740 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6742 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6745 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6746 Builder
bld(ctx
->program
, ctx
->block
);
6747 Temp rsrc
= get_scratch_resource(ctx
);
6748 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6749 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6751 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6752 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6753 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6754 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6755 info
.swizzle_component_size
= 16;
6756 info
.can_reorder
= false;
6757 info
.soffset
= ctx
->program
->scratch_offset
;
6758 emit_mubuf_load(ctx
, bld
, &info
);
6761 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6762 Builder
bld(ctx
->program
, ctx
->block
);
6763 Temp rsrc
= get_scratch_resource(ctx
);
6764 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6765 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6767 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6768 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6770 unsigned write_count
= 0;
6771 Temp write_datas
[32];
6772 unsigned offsets
[32];
6773 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6774 16, &write_count
, write_datas
, offsets
);
6776 for (unsigned i
= 0; i
< write_count
; i
++) {
6777 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6778 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6782 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6783 uint8_t log2_ps_iter_samples
;
6784 if (ctx
->program
->info
->ps
.force_persample
) {
6785 log2_ps_iter_samples
=
6786 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6788 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6791 /* The bit pattern matches that used by fixed function fragment
6793 static const unsigned ps_iter_masks
[] = {
6794 0xffff, /* not used */
6800 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6802 Builder
bld(ctx
->program
, ctx
->block
);
6804 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6805 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6806 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6807 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6808 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6809 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6812 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6813 Builder
bld(ctx
->program
, ctx
->block
);
6815 unsigned stream
= nir_intrinsic_stream_id(instr
);
6816 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6817 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6818 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6821 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6823 unsigned num_components
=
6824 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6825 assert(num_components
);
6827 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6828 unsigned stream_offset
= 0;
6829 for (unsigned i
= 0; i
< stream
; i
++) {
6830 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6831 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6834 /* Limit on the stride field for <= GFX7. */
6835 assert(stride
< (1 << 14));
6837 Temp gsvs_dwords
[4];
6838 for (unsigned i
= 0; i
< 4; i
++)
6839 gsvs_dwords
[i
] = bld
.tmp(s1
);
6840 bld
.pseudo(aco_opcode::p_split_vector
,
6841 Definition(gsvs_dwords
[0]),
6842 Definition(gsvs_dwords
[1]),
6843 Definition(gsvs_dwords
[2]),
6844 Definition(gsvs_dwords
[3]),
6847 if (stream_offset
) {
6848 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6850 Temp carry
= bld
.tmp(s1
);
6851 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6852 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6855 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6856 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6858 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6859 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6861 unsigned offset
= 0;
6862 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6863 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6866 for (unsigned j
= 0; j
< 4; j
++) {
6867 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6870 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6871 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6872 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6873 if (const_offset
>= 4096u) {
6874 if (vaddr_offset
.isUndefined())
6875 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6877 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6878 const_offset
%= 4096u;
6881 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6882 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6883 mtbuf
->operands
[1] = vaddr_offset
;
6884 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6885 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6886 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6887 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6888 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6889 mtbuf
->offset
= const_offset
;
6892 mtbuf
->barrier
= barrier_gs_data
;
6893 mtbuf
->can_reorder
= true;
6894 bld
.insert(std::move(mtbuf
));
6897 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6900 /* outputs for the next vertex are undefined and keeping them around can
6901 * create invalid IR with control flow */
6902 ctx
->outputs
.mask
[i
] = 0;
6905 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6908 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6910 Builder
bld(ctx
->program
, ctx
->block
);
6912 if (cluster_size
== 1) {
6914 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6915 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6916 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6917 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6918 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6919 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6920 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6921 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6922 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6923 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6924 //subgroupAnd(val) -> (exec & ~val) == 0
6925 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6926 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6927 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6928 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6929 //subgroupOr(val) -> (val & exec) != 0
6930 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6931 return bool_to_vector_condition(ctx
, tmp
);
6932 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6933 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6934 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6935 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6936 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6937 return bool_to_vector_condition(ctx
, tmp
);
6939 //subgroupClustered{And,Or,Xor}(val, n) ->
6940 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6941 //cluster_offset = ~(n - 1) & lane_id
6942 //cluster_mask = ((1 << n) - 1)
6943 //subgroupClusteredAnd():
6944 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6945 //subgroupClusteredOr():
6946 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6947 //subgroupClusteredXor():
6948 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6949 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6950 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6953 if (op
== nir_op_iand
)
6954 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6956 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6958 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6960 if (ctx
->program
->chip_class
<= GFX7
)
6961 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6962 else if (ctx
->program
->wave_size
== 64)
6963 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6965 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6966 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6967 if (cluster_mask
!= 0xffffffff)
6968 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6970 Definition cmp_def
= Definition();
6971 if (op
== nir_op_iand
) {
6972 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6973 } else if (op
== nir_op_ior
) {
6974 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6975 } else if (op
== nir_op_ixor
) {
6976 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6977 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6978 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6980 cmp_def
.setHint(vcc
);
6981 return cmp_def
.getTemp();
6985 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6987 Builder
bld(ctx
->program
, ctx
->block
);
6989 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6990 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6991 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6993 if (op
== nir_op_iand
)
6994 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6996 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6998 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6999 Temp lo
= lohi
.def(0).getTemp();
7000 Temp hi
= lohi
.def(1).getTemp();
7001 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7003 Definition cmp_def
= Definition();
7004 if (op
== nir_op_iand
)
7005 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7006 else if (op
== nir_op_ior
)
7007 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7008 else if (op
== nir_op_ixor
)
7009 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7010 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7011 cmp_def
.setHint(vcc
);
7012 return cmp_def
.getTemp();
7015 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7017 Builder
bld(ctx
->program
, ctx
->block
);
7019 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7020 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7021 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7022 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7023 if (op
== nir_op_iand
)
7024 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7025 else if (op
== nir_op_ior
)
7026 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7027 else if (op
== nir_op_ixor
)
7028 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7034 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7036 Builder
bld(ctx
->program
, ctx
->block
);
7037 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7038 if (src
.regClass().type() == RegType::vgpr
) {
7039 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7040 } else if (src
.regClass() == s1
) {
7041 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7042 } else if (src
.regClass() == s2
) {
7043 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7045 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7046 nir_print_instr(&instr
->instr
, stderr
);
7047 fprintf(stderr
, "\n");
7051 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7053 Builder
bld(ctx
->program
, ctx
->block
);
7054 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7055 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7056 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7058 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7059 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7060 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7061 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7064 if (ctx
->program
->chip_class
>= GFX8
) {
7065 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7066 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7067 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7068 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7069 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7070 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7072 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7073 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7074 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7075 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7076 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7077 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7078 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7079 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7080 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7081 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7084 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7085 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7086 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7087 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7088 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7089 Temp wqm1
= bld
.tmp(v1
);
7090 emit_wqm(ctx
, tmp1
, wqm1
, true);
7091 Temp wqm2
= bld
.tmp(v1
);
7092 emit_wqm(ctx
, tmp2
, wqm2
, true);
7093 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7097 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7099 Builder
bld(ctx
->program
, ctx
->block
);
7100 switch(instr
->intrinsic
) {
7101 case nir_intrinsic_load_barycentric_sample
:
7102 case nir_intrinsic_load_barycentric_pixel
:
7103 case nir_intrinsic_load_barycentric_centroid
: {
7104 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7105 Temp bary
= Temp(0, s2
);
7107 case INTERP_MODE_SMOOTH
:
7108 case INTERP_MODE_NONE
:
7109 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7110 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7111 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7112 bary
= ctx
->persp_centroid
;
7113 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7114 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7116 case INTERP_MODE_NOPERSPECTIVE
:
7117 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7118 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7119 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7120 bary
= ctx
->linear_centroid
;
7121 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7122 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7127 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7128 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7129 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7130 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7131 Operand(p1
), Operand(p2
));
7132 emit_split_vector(ctx
, dst
, 2);
7135 case nir_intrinsic_load_barycentric_model
: {
7136 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7138 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7139 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7140 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7141 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7142 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7143 Operand(p1
), Operand(p2
), Operand(p3
));
7144 emit_split_vector(ctx
, dst
, 3);
7147 case nir_intrinsic_load_barycentric_at_sample
: {
7148 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7149 switch (ctx
->options
->key
.fs
.num_samples
) {
7150 case 2: sample_pos_offset
+= 1 << 3; break;
7151 case 4: sample_pos_offset
+= 3 << 3; break;
7152 case 8: sample_pos_offset
+= 7 << 3; break;
7156 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7157 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7158 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7159 if (addr
.type() == RegType::sgpr
) {
7162 sample_pos_offset
+= const_addr
->u32
<< 3;
7163 offset
= Operand(sample_pos_offset
);
7164 } else if (ctx
->options
->chip_class
>= GFX9
) {
7165 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7167 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7168 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7171 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7172 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7174 } else if (ctx
->options
->chip_class
>= GFX9
) {
7175 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7176 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7177 } else if (ctx
->options
->chip_class
>= GFX7
) {
7178 /* addr += private_segment_buffer + sample_pos_offset */
7179 Temp tmp0
= bld
.tmp(s1
);
7180 Temp tmp1
= bld
.tmp(s1
);
7181 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7182 Definition scc_tmp
= bld
.def(s1
, scc
);
7183 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7184 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7185 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7186 Temp pck0
= bld
.tmp(v1
);
7187 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7188 tmp1
= as_vgpr(ctx
, tmp1
);
7189 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7190 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7192 /* sample_pos = flat_load_dwordx2 addr */
7193 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7195 assert(ctx
->options
->chip_class
== GFX6
);
7197 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7198 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7199 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7201 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7202 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7204 sample_pos
= bld
.tmp(v2
);
7206 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7207 load
->definitions
[0] = Definition(sample_pos
);
7208 load
->operands
[0] = Operand(rsrc
);
7209 load
->operands
[1] = Operand(addr
);
7210 load
->operands
[2] = Operand(0u);
7211 load
->offset
= sample_pos_offset
;
7213 load
->addr64
= true;
7216 load
->disable_wqm
= false;
7217 load
->barrier
= barrier_none
;
7218 load
->can_reorder
= true;
7219 ctx
->block
->instructions
.emplace_back(std::move(load
));
7222 /* sample_pos -= 0.5 */
7223 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7224 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7225 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7226 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7227 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7229 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7232 case nir_intrinsic_load_barycentric_at_offset
: {
7233 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7234 RegClass rc
= RegClass(offset
.type(), 1);
7235 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7236 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7237 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7240 case nir_intrinsic_load_front_face
: {
7241 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7242 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7245 case nir_intrinsic_load_view_index
: {
7246 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7247 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7248 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7254 case nir_intrinsic_load_layer_id
: {
7255 unsigned idx
= nir_intrinsic_base(instr
);
7256 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7257 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7260 case nir_intrinsic_load_frag_coord
: {
7261 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7264 case nir_intrinsic_load_sample_pos
: {
7265 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7266 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7267 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7268 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7269 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7272 case nir_intrinsic_load_tess_coord
:
7273 visit_load_tess_coord(ctx
, instr
);
7275 case nir_intrinsic_load_interpolated_input
:
7276 visit_load_interpolated_input(ctx
, instr
);
7278 case nir_intrinsic_store_output
:
7279 visit_store_output(ctx
, instr
);
7281 case nir_intrinsic_load_input
:
7282 case nir_intrinsic_load_input_vertex
:
7283 visit_load_input(ctx
, instr
);
7285 case nir_intrinsic_load_output
:
7286 visit_load_output(ctx
, instr
);
7288 case nir_intrinsic_load_per_vertex_input
:
7289 visit_load_per_vertex_input(ctx
, instr
);
7291 case nir_intrinsic_load_per_vertex_output
:
7292 visit_load_per_vertex_output(ctx
, instr
);
7294 case nir_intrinsic_store_per_vertex_output
:
7295 visit_store_per_vertex_output(ctx
, instr
);
7297 case nir_intrinsic_load_ubo
:
7298 visit_load_ubo(ctx
, instr
);
7300 case nir_intrinsic_load_push_constant
:
7301 visit_load_push_constant(ctx
, instr
);
7303 case nir_intrinsic_load_constant
:
7304 visit_load_constant(ctx
, instr
);
7306 case nir_intrinsic_vulkan_resource_index
:
7307 visit_load_resource(ctx
, instr
);
7309 case nir_intrinsic_discard
:
7310 visit_discard(ctx
, instr
);
7312 case nir_intrinsic_discard_if
:
7313 visit_discard_if(ctx
, instr
);
7315 case nir_intrinsic_load_shared
:
7316 visit_load_shared(ctx
, instr
);
7318 case nir_intrinsic_store_shared
:
7319 visit_store_shared(ctx
, instr
);
7321 case nir_intrinsic_shared_atomic_add
:
7322 case nir_intrinsic_shared_atomic_imin
:
7323 case nir_intrinsic_shared_atomic_umin
:
7324 case nir_intrinsic_shared_atomic_imax
:
7325 case nir_intrinsic_shared_atomic_umax
:
7326 case nir_intrinsic_shared_atomic_and
:
7327 case nir_intrinsic_shared_atomic_or
:
7328 case nir_intrinsic_shared_atomic_xor
:
7329 case nir_intrinsic_shared_atomic_exchange
:
7330 case nir_intrinsic_shared_atomic_comp_swap
:
7331 visit_shared_atomic(ctx
, instr
);
7333 case nir_intrinsic_image_deref_load
:
7334 visit_image_load(ctx
, instr
);
7336 case nir_intrinsic_image_deref_store
:
7337 visit_image_store(ctx
, instr
);
7339 case nir_intrinsic_image_deref_atomic_add
:
7340 case nir_intrinsic_image_deref_atomic_umin
:
7341 case nir_intrinsic_image_deref_atomic_imin
:
7342 case nir_intrinsic_image_deref_atomic_umax
:
7343 case nir_intrinsic_image_deref_atomic_imax
:
7344 case nir_intrinsic_image_deref_atomic_and
:
7345 case nir_intrinsic_image_deref_atomic_or
:
7346 case nir_intrinsic_image_deref_atomic_xor
:
7347 case nir_intrinsic_image_deref_atomic_exchange
:
7348 case nir_intrinsic_image_deref_atomic_comp_swap
:
7349 visit_image_atomic(ctx
, instr
);
7351 case nir_intrinsic_image_deref_size
:
7352 visit_image_size(ctx
, instr
);
7354 case nir_intrinsic_load_ssbo
:
7355 visit_load_ssbo(ctx
, instr
);
7357 case nir_intrinsic_store_ssbo
:
7358 visit_store_ssbo(ctx
, instr
);
7360 case nir_intrinsic_load_global
:
7361 visit_load_global(ctx
, instr
);
7363 case nir_intrinsic_store_global
:
7364 visit_store_global(ctx
, instr
);
7366 case nir_intrinsic_global_atomic_add
:
7367 case nir_intrinsic_global_atomic_imin
:
7368 case nir_intrinsic_global_atomic_umin
:
7369 case nir_intrinsic_global_atomic_imax
:
7370 case nir_intrinsic_global_atomic_umax
:
7371 case nir_intrinsic_global_atomic_and
:
7372 case nir_intrinsic_global_atomic_or
:
7373 case nir_intrinsic_global_atomic_xor
:
7374 case nir_intrinsic_global_atomic_exchange
:
7375 case nir_intrinsic_global_atomic_comp_swap
:
7376 visit_global_atomic(ctx
, instr
);
7378 case nir_intrinsic_ssbo_atomic_add
:
7379 case nir_intrinsic_ssbo_atomic_imin
:
7380 case nir_intrinsic_ssbo_atomic_umin
:
7381 case nir_intrinsic_ssbo_atomic_imax
:
7382 case nir_intrinsic_ssbo_atomic_umax
:
7383 case nir_intrinsic_ssbo_atomic_and
:
7384 case nir_intrinsic_ssbo_atomic_or
:
7385 case nir_intrinsic_ssbo_atomic_xor
:
7386 case nir_intrinsic_ssbo_atomic_exchange
:
7387 case nir_intrinsic_ssbo_atomic_comp_swap
:
7388 visit_atomic_ssbo(ctx
, instr
);
7390 case nir_intrinsic_load_scratch
:
7391 visit_load_scratch(ctx
, instr
);
7393 case nir_intrinsic_store_scratch
:
7394 visit_store_scratch(ctx
, instr
);
7396 case nir_intrinsic_get_buffer_size
:
7397 visit_get_buffer_size(ctx
, instr
);
7399 case nir_intrinsic_control_barrier
: {
7400 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7401 /* GFX6 only (thanks to a hw bug workaround):
7402 * The real barrier instruction isn’t needed, because an entire patch
7403 * always fits into a single wave.
7408 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7409 bld
.sopp(aco_opcode::s_barrier
);
7413 case nir_intrinsic_memory_barrier_tcs_patch
:
7414 case nir_intrinsic_group_memory_barrier
:
7415 case nir_intrinsic_memory_barrier
:
7416 case nir_intrinsic_memory_barrier_buffer
:
7417 case nir_intrinsic_memory_barrier_image
:
7418 case nir_intrinsic_memory_barrier_shared
:
7419 emit_memory_barrier(ctx
, instr
);
7421 case nir_intrinsic_load_num_work_groups
: {
7422 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7423 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7424 emit_split_vector(ctx
, dst
, 3);
7427 case nir_intrinsic_load_local_invocation_id
: {
7428 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7429 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7430 emit_split_vector(ctx
, dst
, 3);
7433 case nir_intrinsic_load_work_group_id
: {
7434 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7435 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7436 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7437 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7438 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7439 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7440 emit_split_vector(ctx
, dst
, 3);
7443 case nir_intrinsic_load_local_invocation_index
: {
7444 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7446 /* The tg_size bits [6:11] contain the subgroup id,
7447 * we need this multiplied by the wave size, and then OR the thread id to it.
7449 if (ctx
->program
->wave_size
== 64) {
7450 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7451 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7452 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7453 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7455 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7456 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7457 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7458 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7462 case nir_intrinsic_load_subgroup_id
: {
7463 if (ctx
->stage
== compute_cs
) {
7464 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7465 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7467 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7471 case nir_intrinsic_load_subgroup_invocation
: {
7472 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7475 case nir_intrinsic_load_num_subgroups
: {
7476 if (ctx
->stage
== compute_cs
)
7477 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7478 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7480 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7483 case nir_intrinsic_ballot
: {
7484 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7485 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7486 Definition tmp
= bld
.def(dst
.regClass());
7487 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7488 if (instr
->src
[0].ssa
->bit_size
== 1) {
7489 assert(src
.regClass() == bld
.lm
);
7490 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7491 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7492 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7493 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7494 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7496 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7497 nir_print_instr(&instr
->instr
, stderr
);
7498 fprintf(stderr
, "\n");
7500 if (dst
.size() != bld
.lm
.size()) {
7501 /* Wave32 with ballot size set to 64 */
7502 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7504 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7507 case nir_intrinsic_shuffle
:
7508 case nir_intrinsic_read_invocation
: {
7509 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7510 if (!nir_src_is_divergent(instr
->src
[0])) {
7511 emit_uniform_subgroup(ctx
, instr
, src
);
7513 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7514 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7515 tid
= bld
.as_uniform(tid
);
7516 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7517 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7518 Temp tmp
= bld
.tmp(v1
);
7519 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7520 if (dst
.type() == RegType::vgpr
)
7521 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7523 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7524 } else if (src
.regClass() == v1
) {
7525 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7526 } else if (src
.regClass() == v2
) {
7527 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7528 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7529 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7530 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7531 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7532 emit_split_vector(ctx
, dst
, 2);
7533 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7534 assert(src
.regClass() == bld
.lm
);
7535 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7536 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7537 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7538 assert(src
.regClass() == bld
.lm
);
7540 if (ctx
->program
->chip_class
<= GFX7
)
7541 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7542 else if (ctx
->program
->wave_size
== 64)
7543 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7545 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7546 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7547 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7548 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7550 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7551 nir_print_instr(&instr
->instr
, stderr
);
7552 fprintf(stderr
, "\n");
7557 case nir_intrinsic_load_sample_id
: {
7558 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7559 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7562 case nir_intrinsic_load_sample_mask_in
: {
7563 visit_load_sample_mask_in(ctx
, instr
);
7566 case nir_intrinsic_read_first_invocation
: {
7567 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7568 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7569 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7571 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7573 } else if (src
.regClass() == v2
) {
7574 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7575 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7576 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7577 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7578 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7579 emit_split_vector(ctx
, dst
, 2);
7580 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7581 assert(src
.regClass() == bld
.lm
);
7582 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7583 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7584 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7585 } else if (src
.regClass() == s1
) {
7586 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7587 } else if (src
.regClass() == s2
) {
7588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7590 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7591 nir_print_instr(&instr
->instr
, stderr
);
7592 fprintf(stderr
, "\n");
7596 case nir_intrinsic_vote_all
: {
7597 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7598 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7599 assert(src
.regClass() == bld
.lm
);
7600 assert(dst
.regClass() == bld
.lm
);
7602 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7603 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7604 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7607 case nir_intrinsic_vote_any
: {
7608 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7609 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7610 assert(src
.regClass() == bld
.lm
);
7611 assert(dst
.regClass() == bld
.lm
);
7613 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7614 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7617 case nir_intrinsic_reduce
:
7618 case nir_intrinsic_inclusive_scan
:
7619 case nir_intrinsic_exclusive_scan
: {
7620 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7621 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7622 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7623 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7624 nir_intrinsic_cluster_size(instr
) : 0;
7625 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7627 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7628 emit_uniform_subgroup(ctx
, instr
, src
);
7629 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7630 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7632 else if (op
== nir_op_iadd
)
7634 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7636 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7638 switch (instr
->intrinsic
) {
7639 case nir_intrinsic_reduce
:
7640 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7642 case nir_intrinsic_exclusive_scan
:
7643 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7645 case nir_intrinsic_inclusive_scan
:
7646 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7651 } else if (cluster_size
== 1) {
7652 bld
.copy(Definition(dst
), src
);
7654 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7656 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7660 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7661 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7676 unreachable("unknown reduction op");
7682 switch (instr
->intrinsic
) {
7683 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7684 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7685 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7687 unreachable("unknown reduce intrinsic");
7690 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7691 reduce
->operands
[0] = Operand(src
);
7692 // filled in by aco_reduce_assign.cpp, used internally as part of the
7694 assert(dst
.size() == 1 || dst
.size() == 2);
7695 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7696 reduce
->operands
[2] = Operand(v1
.as_linear());
7698 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7699 reduce
->definitions
[0] = Definition(tmp_dst
);
7700 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7701 reduce
->definitions
[2] = Definition();
7702 reduce
->definitions
[3] = Definition(scc
, s1
);
7703 reduce
->definitions
[4] = Definition();
7704 reduce
->reduce_op
= reduce_op
;
7705 reduce
->cluster_size
= cluster_size
;
7706 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7708 emit_wqm(ctx
, tmp_dst
, dst
);
7712 case nir_intrinsic_quad_broadcast
: {
7713 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7714 if (!nir_dest_is_divergent(instr
->dest
)) {
7715 emit_uniform_subgroup(ctx
, instr
, src
);
7717 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7718 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7719 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7721 if (instr
->dest
.ssa
.bit_size
== 1) {
7722 assert(src
.regClass() == bld
.lm
);
7723 assert(dst
.regClass() == bld
.lm
);
7724 uint32_t half_mask
= 0x11111111u
<< lane
;
7725 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7726 Temp tmp
= bld
.tmp(bld
.lm
);
7727 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7728 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7729 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7730 emit_wqm(ctx
, tmp
, dst
);
7731 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7732 Temp tmp
= bld
.tmp(v1
);
7733 if (ctx
->program
->chip_class
>= GFX8
)
7734 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7736 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7737 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7738 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7739 Temp tmp
= bld
.tmp(v1
);
7740 if (ctx
->program
->chip_class
>= GFX8
)
7741 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7743 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7744 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7745 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7746 if (ctx
->program
->chip_class
>= GFX8
)
7747 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7749 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7750 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7751 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7752 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7753 if (ctx
->program
->chip_class
>= GFX8
) {
7754 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7755 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7757 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7758 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7760 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7761 emit_split_vector(ctx
, dst
, 2);
7763 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7764 nir_print_instr(&instr
->instr
, stderr
);
7765 fprintf(stderr
, "\n");
7770 case nir_intrinsic_quad_swap_horizontal
:
7771 case nir_intrinsic_quad_swap_vertical
:
7772 case nir_intrinsic_quad_swap_diagonal
:
7773 case nir_intrinsic_quad_swizzle_amd
: {
7774 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7775 if (!nir_dest_is_divergent(instr
->dest
)) {
7776 emit_uniform_subgroup(ctx
, instr
, src
);
7779 uint16_t dpp_ctrl
= 0;
7780 switch (instr
->intrinsic
) {
7781 case nir_intrinsic_quad_swap_horizontal
:
7782 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7784 case nir_intrinsic_quad_swap_vertical
:
7785 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7787 case nir_intrinsic_quad_swap_diagonal
:
7788 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7790 case nir_intrinsic_quad_swizzle_amd
:
7791 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7796 if (ctx
->program
->chip_class
< GFX8
)
7797 dpp_ctrl
|= (1 << 15);
7799 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7800 if (instr
->dest
.ssa
.bit_size
== 1) {
7801 assert(src
.regClass() == bld
.lm
);
7802 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7803 if (ctx
->program
->chip_class
>= GFX8
)
7804 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7806 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7807 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7808 emit_wqm(ctx
, tmp
, dst
);
7809 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7810 Temp tmp
= bld
.tmp(v1
);
7811 if (ctx
->program
->chip_class
>= GFX8
)
7812 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7814 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7815 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7816 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7817 Temp tmp
= bld
.tmp(v1
);
7818 if (ctx
->program
->chip_class
>= GFX8
)
7819 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7821 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7822 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7823 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7825 if (ctx
->program
->chip_class
>= GFX8
)
7826 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7828 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7829 emit_wqm(ctx
, tmp
, dst
);
7830 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7831 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7832 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7833 if (ctx
->program
->chip_class
>= GFX8
) {
7834 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7835 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7837 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7838 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7840 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7841 emit_split_vector(ctx
, dst
, 2);
7843 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7844 nir_print_instr(&instr
->instr
, stderr
);
7845 fprintf(stderr
, "\n");
7849 case nir_intrinsic_masked_swizzle_amd
: {
7850 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7851 if (!nir_dest_is_divergent(instr
->dest
)) {
7852 emit_uniform_subgroup(ctx
, instr
, src
);
7855 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7856 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7857 if (dst
.regClass() == v1
) {
7859 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7861 } else if (dst
.regClass() == v2
) {
7862 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7863 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7864 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7865 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7866 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7867 emit_split_vector(ctx
, dst
, 2);
7869 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7870 nir_print_instr(&instr
->instr
, stderr
);
7871 fprintf(stderr
, "\n");
7875 case nir_intrinsic_write_invocation_amd
: {
7876 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7877 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7878 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7879 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7880 if (dst
.regClass() == v1
) {
7881 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7882 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7883 } else if (dst
.regClass() == v2
) {
7884 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7885 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7886 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7887 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7888 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7889 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7890 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7891 emit_split_vector(ctx
, dst
, 2);
7893 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7894 nir_print_instr(&instr
->instr
, stderr
);
7895 fprintf(stderr
, "\n");
7899 case nir_intrinsic_mbcnt_amd
: {
7900 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7901 RegClass rc
= RegClass(src
.type(), 1);
7902 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7903 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7904 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7905 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7906 emit_wqm(ctx
, wqm_tmp
, dst
);
7909 case nir_intrinsic_load_helper_invocation
: {
7910 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7911 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7912 ctx
->block
->kind
|= block_kind_needs_lowering
;
7913 ctx
->program
->needs_exact
= true;
7916 case nir_intrinsic_is_helper_invocation
: {
7917 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7918 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7919 ctx
->block
->kind
|= block_kind_needs_lowering
;
7920 ctx
->program
->needs_exact
= true;
7923 case nir_intrinsic_demote
:
7924 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7926 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7927 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7928 ctx
->block
->kind
|= block_kind_uses_demote
;
7929 ctx
->program
->needs_exact
= true;
7931 case nir_intrinsic_demote_if
: {
7932 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7933 assert(src
.regClass() == bld
.lm
);
7934 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7935 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7937 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7938 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7939 ctx
->block
->kind
|= block_kind_uses_demote
;
7940 ctx
->program
->needs_exact
= true;
7943 case nir_intrinsic_first_invocation
: {
7944 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7945 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7948 case nir_intrinsic_shader_clock
: {
7950 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7951 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7952 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7953 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7956 case nir_intrinsic_load_vertex_id_zero_base
: {
7957 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7958 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7961 case nir_intrinsic_load_first_vertex
: {
7962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7963 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7966 case nir_intrinsic_load_base_instance
: {
7967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7968 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7971 case nir_intrinsic_load_instance_id
: {
7972 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7973 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7976 case nir_intrinsic_load_draw_id
: {
7977 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7978 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7981 case nir_intrinsic_load_invocation_id
: {
7982 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7984 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7985 if (ctx
->options
->chip_class
>= GFX10
)
7986 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7988 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7989 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7990 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7991 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7993 unreachable("Unsupported stage for load_invocation_id");
7998 case nir_intrinsic_load_primitive_id
: {
7999 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8001 switch (ctx
->shader
->info
.stage
) {
8002 case MESA_SHADER_GEOMETRY
:
8003 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8005 case MESA_SHADER_TESS_CTRL
:
8006 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8008 case MESA_SHADER_TESS_EVAL
:
8009 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8012 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8017 case nir_intrinsic_load_patch_vertices_in
: {
8018 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8019 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8021 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8022 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8025 case nir_intrinsic_emit_vertex_with_counter
: {
8026 visit_emit_vertex_with_counter(ctx
, instr
);
8029 case nir_intrinsic_end_primitive_with_counter
: {
8030 unsigned stream
= nir_intrinsic_stream_id(instr
);
8031 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8034 case nir_intrinsic_set_vertex_count
: {
8035 /* unused, the HW keeps track of this for us */
8039 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8040 nir_print_instr(&instr
->instr
, stderr
);
8041 fprintf(stderr
, "\n");
8049 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8050 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8051 enum glsl_base_type
*stype
)
8053 nir_deref_instr
*texture_deref_instr
= NULL
;
8054 nir_deref_instr
*sampler_deref_instr
= NULL
;
8057 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8058 switch (instr
->src
[i
].src_type
) {
8059 case nir_tex_src_texture_deref
:
8060 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8062 case nir_tex_src_sampler_deref
:
8063 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8065 case nir_tex_src_plane
:
8066 plane
= nir_src_as_int(instr
->src
[i
].src
);
8073 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8075 if (!sampler_deref_instr
)
8076 sampler_deref_instr
= texture_deref_instr
;
8079 assert(instr
->op
!= nir_texop_txf_ms
&&
8080 instr
->op
!= nir_texop_samples_identical
);
8081 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8082 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8083 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8084 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8085 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8086 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8088 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8091 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8093 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8094 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8095 Builder
bld(ctx
->program
, ctx
->block
);
8097 /* to avoid unnecessary moves, we split and recombine sampler and image */
8098 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8099 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8100 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8102 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8103 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8104 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8105 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8107 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8108 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8109 img
[0], img
[1], img
[2], img
[3],
8110 img
[4], img
[5], img
[6], img
[7]);
8111 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8112 samp
[0], samp
[1], samp
[2], samp
[3]);
8115 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8116 instr
->op
== nir_texop_samples_identical
))
8117 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8120 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8121 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8123 Builder
bld(ctx
->program
, ctx
->block
);
8125 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8126 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8127 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8129 Operand
neg_one(0xbf800000u
);
8130 Operand
one(0x3f800000u
);
8131 Operand
two(0x40000000u
);
8132 Operand
four(0x40800000u
);
8134 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8135 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8136 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8138 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8139 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8140 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8141 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8144 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8145 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8146 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8148 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8151 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8152 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8153 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8156 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8157 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8159 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8160 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8163 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8165 Builder
bld(ctx
->program
, ctx
->block
);
8166 Temp ma
, tc
, sc
, id
;
8169 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8171 // see comment in ac_prepare_cube_coords()
8172 if (ctx
->options
->chip_class
<= GFX8
)
8173 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8176 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8178 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8179 vop3a
->operands
[0] = Operand(ma
);
8180 vop3a
->abs
[0] = true;
8181 Temp invma
= bld
.tmp(v1
);
8182 vop3a
->definitions
[0] = Definition(invma
);
8183 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8185 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8187 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8189 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8191 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8193 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8196 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8197 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8199 for (unsigned i
= 0; i
< 2; i
++) {
8200 // see comment in ac_prepare_cube_coords()
8202 Temp deriv_sc
, deriv_tc
;
8203 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8204 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8206 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8208 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8209 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8210 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8211 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8212 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8213 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8214 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8217 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8218 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8222 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8229 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8231 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8233 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8234 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8237 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8238 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8239 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8243 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8245 Builder
bld(ctx
->program
, ctx
->block
);
8246 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8247 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8248 has_clamped_lod
= false;
8249 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8250 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8251 clamped_lod
= Temp();
8252 std::vector
<Temp
> coords
;
8253 std::vector
<Temp
> derivs
;
8254 nir_const_value
*sample_index_cv
= NULL
;
8255 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8256 enum glsl_base_type stype
;
8257 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8259 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8260 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8261 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8262 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8264 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8265 switch (instr
->src
[i
].src_type
) {
8266 case nir_tex_src_coord
: {
8267 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8268 for (unsigned i
= 0; i
< coord
.size(); i
++)
8269 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8272 case nir_tex_src_bias
:
8273 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8276 case nir_tex_src_lod
: {
8277 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8279 if (val
&& val
->f32
<= 0.0) {
8282 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8287 case nir_tex_src_min_lod
:
8288 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8289 has_clamped_lod
= true;
8291 case nir_tex_src_comparator
:
8292 if (instr
->is_shadow
) {
8293 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8297 case nir_tex_src_offset
:
8298 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8299 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8302 case nir_tex_src_ddx
:
8303 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8306 case nir_tex_src_ddy
:
8307 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8310 case nir_tex_src_ms_index
:
8311 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8312 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8313 has_sample_index
= true;
8315 case nir_tex_src_texture_offset
:
8316 case nir_tex_src_sampler_offset
:
8322 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8323 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8325 if (instr
->op
== nir_texop_texture_samples
) {
8326 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8328 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8329 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8330 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8332 Operand default_sample
= Operand(1u);
8333 if (ctx
->options
->robust_buffer_access
) {
8334 /* Extract the second dword of the descriptor, if it's
8335 * all zero, then it's a null descriptor.
8337 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8338 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8339 default_sample
= Operand(is_non_null_descriptor
);
8342 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8343 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8344 samples
, default_sample
, bld
.scc(is_msaa
));
8348 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8349 aco_ptr
<Instruction
> tmp_instr
;
8350 Temp acc
, pack
= Temp();
8352 uint32_t pack_const
= 0;
8353 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8354 if (!const_offset
[i
])
8356 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8359 if (offset
.type() == RegType::sgpr
) {
8360 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8361 if (const_offset
[i
])
8364 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8365 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8368 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8371 if (pack
== Temp()) {
8374 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8378 if (pack_const
&& pack
!= Temp())
8379 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8381 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8382 if (const_offset
[i
])
8385 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8386 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8389 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8392 if (pack
== Temp()) {
8395 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8399 if (pack_const
&& pack
!= Temp())
8400 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8402 if (pack_const
&& pack
== Temp())
8403 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8404 else if (pack
== Temp())
8410 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8411 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8413 /* pack derivatives */
8414 if (has_ddx
|| has_ddy
) {
8415 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8416 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8417 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8418 derivs
= {ddx
, zero
, ddy
, zero
};
8420 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8421 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8422 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8423 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8428 if (instr
->coord_components
> 1 &&
8429 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8431 instr
->op
!= nir_texop_txf
)
8432 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8434 if (instr
->coord_components
> 2 &&
8435 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8436 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8437 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8438 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8440 instr
->op
!= nir_texop_txf
&&
8441 instr
->op
!= nir_texop_txf_ms
&&
8442 instr
->op
!= nir_texop_fragment_fetch
&&
8443 instr
->op
!= nir_texop_fragment_mask_fetch
)
8444 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8446 if (ctx
->options
->chip_class
== GFX9
&&
8447 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8448 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8449 assert(coords
.size() > 0 && coords
.size() < 3);
8451 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8452 Operand((uint32_t) 0) :
8453 Operand((uint32_t) 0x3f000000)));
8456 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8458 if (instr
->op
== nir_texop_samples_identical
)
8459 resource
= fmask_ptr
;
8461 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8462 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8463 instr
->op
!= nir_texop_txs
&&
8464 instr
->op
!= nir_texop_fragment_fetch
&&
8465 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8466 assert(has_sample_index
);
8467 Operand
op(sample_index
);
8468 if (sample_index_cv
)
8469 op
= Operand(sample_index_cv
->u32
);
8470 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8473 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8474 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8475 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8476 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8481 /* Build tex instruction */
8482 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8483 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8484 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8486 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8489 /* gather4 selects the component by dmask and always returns vec4 */
8490 if (instr
->op
== nir_texop_tg4
) {
8491 assert(instr
->dest
.ssa
.num_components
== 4);
8492 if (instr
->is_shadow
)
8495 dmask
= 1 << instr
->component
;
8496 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8497 tmp_dst
= bld
.tmp(v4
);
8498 } else if (instr
->op
== nir_texop_samples_identical
) {
8499 tmp_dst
= bld
.tmp(v1
);
8500 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8501 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8504 aco_ptr
<MIMG_instruction
> tex
;
8505 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8507 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8509 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8510 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8513 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8514 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8516 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8517 tex
->operands
[0] = Operand(resource
);
8518 tex
->operands
[1] = Operand(s4
); /* no sampler */
8519 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8520 if (ctx
->options
->chip_class
== GFX9
&&
8521 instr
->op
== nir_texop_txs
&&
8522 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8524 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8525 } else if (instr
->op
== nir_texop_query_levels
) {
8526 tex
->dmask
= 1 << 3;
8531 tex
->definitions
[0] = Definition(tmp_dst
);
8533 tex
->can_reorder
= true;
8534 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8537 /* divide 3rd value by 6 by multiplying with magic number */
8538 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8539 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8540 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8541 assert(instr
->dest
.ssa
.num_components
== 3);
8542 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8543 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8544 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8545 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8550 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8554 Temp tg4_compare_cube_wa64
= Temp();
8556 if (tg4_integer_workarounds
) {
8557 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8558 tex
->operands
[0] = Operand(resource
);
8559 tex
->operands
[1] = Operand(s4
); /* no sampler */
8560 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8564 Temp size
= bld
.tmp(v2
);
8565 tex
->definitions
[0] = Definition(size
);
8566 tex
->can_reorder
= true;
8567 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8568 emit_split_vector(ctx
, size
, size
.size());
8571 for (unsigned i
= 0; i
< 2; i
++) {
8572 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8573 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8574 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8575 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8578 Temp new_coords
[2] = {
8579 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8580 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8583 if (tg4_integer_cube_workaround
) {
8584 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8585 Temp desc
[resource
.size()];
8586 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8587 Format::PSEUDO
, 1, resource
.size())};
8588 split
->operands
[0] = Operand(resource
);
8589 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8590 desc
[i
] = bld
.tmp(s1
);
8591 split
->definitions
[i
] = Definition(desc
[i
]);
8593 ctx
->block
->instructions
.emplace_back(std::move(split
));
8595 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8596 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8597 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8600 if (stype
== GLSL_TYPE_UINT
) {
8601 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8602 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8603 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8604 bld
.scc(compare_cube_wa
));
8606 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8607 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8608 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8609 bld
.scc(compare_cube_wa
));
8611 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8612 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8614 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8616 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8617 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8618 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8620 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8621 Format::PSEUDO
, resource
.size(), 1)};
8622 for (unsigned i
= 0; i
< resource
.size(); i
++)
8623 vec
->operands
[i
] = Operand(desc
[i
]);
8624 resource
= bld
.tmp(resource
.regClass());
8625 vec
->definitions
[0] = Definition(resource
);
8626 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8628 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8629 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8630 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8631 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8633 coords
[0] = new_coords
[0];
8634 coords
[1] = new_coords
[1];
8637 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8638 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8640 assert(coords
.size() == 1);
8641 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8645 op
= aco_opcode::buffer_load_format_x
; break;
8647 op
= aco_opcode::buffer_load_format_xy
; break;
8649 op
= aco_opcode::buffer_load_format_xyz
; break;
8651 op
= aco_opcode::buffer_load_format_xyzw
; break;
8653 unreachable("Tex instruction loads more than 4 components.");
8656 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8657 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8660 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8662 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8663 mubuf
->operands
[0] = Operand(resource
);
8664 mubuf
->operands
[1] = Operand(coords
[0]);
8665 mubuf
->operands
[2] = Operand((uint32_t) 0);
8666 mubuf
->definitions
[0] = Definition(tmp_dst
);
8667 mubuf
->idxen
= true;
8668 mubuf
->can_reorder
= true;
8669 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8671 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8675 /* gather MIMG address components */
8676 std::vector
<Temp
> args
;
8678 args
.emplace_back(offset
);
8680 args
.emplace_back(bias
);
8682 args
.emplace_back(compare
);
8684 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8686 args
.insert(args
.end(), coords
.begin(), coords
.end());
8687 if (has_sample_index
)
8688 args
.emplace_back(sample_index
);
8690 args
.emplace_back(lod
);
8691 if (has_clamped_lod
)
8692 args
.emplace_back(clamped_lod
);
8694 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8695 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8696 vec
->definitions
[0] = Definition(arg
);
8697 for (unsigned i
= 0; i
< args
.size(); i
++)
8698 vec
->operands
[i
] = Operand(args
[i
]);
8699 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8702 if (instr
->op
== nir_texop_txf
||
8703 instr
->op
== nir_texop_txf_ms
||
8704 instr
->op
== nir_texop_samples_identical
||
8705 instr
->op
== nir_texop_fragment_fetch
||
8706 instr
->op
== nir_texop_fragment_mask_fetch
) {
8707 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8708 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8709 tex
->operands
[0] = Operand(resource
);
8710 tex
->operands
[1] = Operand(s4
); /* no sampler */
8711 tex
->operands
[2] = Operand(arg
);
8716 tex
->definitions
[0] = Definition(tmp_dst
);
8717 tex
->can_reorder
= true;
8718 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8720 if (instr
->op
== nir_texop_samples_identical
) {
8721 assert(dmask
== 1 && dst
.regClass() == v1
);
8722 assert(dst
.id() != tmp_dst
.id());
8724 Temp tmp
= bld
.tmp(bld
.lm
);
8725 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8726 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8729 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8734 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8735 aco_opcode opcode
= aco_opcode::image_sample
;
8736 if (has_offset
) { /* image_sample_*_o */
8737 if (has_clamped_lod
) {
8739 opcode
= aco_opcode::image_sample_c_cl_o
;
8741 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8743 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8745 opcode
= aco_opcode::image_sample_cl_o
;
8747 opcode
= aco_opcode::image_sample_d_cl_o
;
8749 opcode
= aco_opcode::image_sample_b_cl_o
;
8751 } else if (has_compare
) {
8752 opcode
= aco_opcode::image_sample_c_o
;
8754 opcode
= aco_opcode::image_sample_c_d_o
;
8756 opcode
= aco_opcode::image_sample_c_b_o
;
8758 opcode
= aco_opcode::image_sample_c_lz_o
;
8760 opcode
= aco_opcode::image_sample_c_l_o
;
8762 opcode
= aco_opcode::image_sample_o
;
8764 opcode
= aco_opcode::image_sample_d_o
;
8766 opcode
= aco_opcode::image_sample_b_o
;
8768 opcode
= aco_opcode::image_sample_lz_o
;
8770 opcode
= aco_opcode::image_sample_l_o
;
8772 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8774 opcode
= aco_opcode::image_sample_c_cl
;
8776 opcode
= aco_opcode::image_sample_c_d_cl
;
8778 opcode
= aco_opcode::image_sample_c_b_cl
;
8780 opcode
= aco_opcode::image_sample_cl
;
8782 opcode
= aco_opcode::image_sample_d_cl
;
8784 opcode
= aco_opcode::image_sample_b_cl
;
8786 } else { /* no offset */
8788 opcode
= aco_opcode::image_sample_c
;
8790 opcode
= aco_opcode::image_sample_c_d
;
8792 opcode
= aco_opcode::image_sample_c_b
;
8794 opcode
= aco_opcode::image_sample_c_lz
;
8796 opcode
= aco_opcode::image_sample_c_l
;
8798 opcode
= aco_opcode::image_sample
;
8800 opcode
= aco_opcode::image_sample_d
;
8802 opcode
= aco_opcode::image_sample_b
;
8804 opcode
= aco_opcode::image_sample_lz
;
8806 opcode
= aco_opcode::image_sample_l
;
8810 if (instr
->op
== nir_texop_tg4
) {
8811 if (has_offset
) { /* image_gather4_*_o */
8813 opcode
= aco_opcode::image_gather4_c_lz_o
;
8815 opcode
= aco_opcode::image_gather4_c_l_o
;
8817 opcode
= aco_opcode::image_gather4_c_b_o
;
8819 opcode
= aco_opcode::image_gather4_lz_o
;
8821 opcode
= aco_opcode::image_gather4_l_o
;
8823 opcode
= aco_opcode::image_gather4_b_o
;
8827 opcode
= aco_opcode::image_gather4_c_lz
;
8829 opcode
= aco_opcode::image_gather4_c_l
;
8831 opcode
= aco_opcode::image_gather4_c_b
;
8833 opcode
= aco_opcode::image_gather4_lz
;
8835 opcode
= aco_opcode::image_gather4_l
;
8837 opcode
= aco_opcode::image_gather4_b
;
8840 } else if (instr
->op
== nir_texop_lod
) {
8841 opcode
= aco_opcode::image_get_lod
;
8844 /* we don't need the bias, sample index, compare value or offset to be
8845 * computed in WQM but if the p_create_vector copies the coordinates, then it
8846 * needs to be in WQM */
8847 if (ctx
->stage
== fragment_fs
&&
8848 !has_derivs
&& !has_lod
&& !level_zero
&&
8849 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8850 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8851 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8853 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8854 tex
->operands
[0] = Operand(resource
);
8855 tex
->operands
[1] = Operand(sampler
);
8856 tex
->operands
[2] = Operand(arg
);
8860 tex
->definitions
[0] = Definition(tmp_dst
);
8861 tex
->can_reorder
= true;
8862 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8864 if (tg4_integer_cube_workaround
) {
8865 assert(tmp_dst
.id() != dst
.id());
8866 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8868 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8870 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8871 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8873 if (stype
== GLSL_TYPE_UINT
)
8874 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8876 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8877 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8879 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8880 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8881 val
[0], val
[1], val
[2], val
[3]);
8883 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8884 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8889 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8891 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8892 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8893 return Operand(tmp
.regClass());
8895 return Operand(tmp
);
8898 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8900 aco_ptr
<Pseudo_instruction
> phi
;
8901 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8902 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8904 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8905 logical
|= ctx
->block
->kind
& block_kind_merge
;
8906 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8908 /* we want a sorted list of sources, since the predecessor list is also sorted */
8909 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8910 nir_foreach_phi_src(src
, instr
)
8911 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8913 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8914 unsigned num_operands
= 0;
8915 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8916 unsigned num_defined
= 0;
8917 unsigned cur_pred_idx
= 0;
8918 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8919 if (cur_pred_idx
< preds
.size()) {
8920 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8921 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8922 unsigned skipped
= 0;
8923 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8925 if (cur_pred_idx
+ skipped
< preds
.size()) {
8926 for (unsigned i
= 0; i
< skipped
; i
++)
8927 operands
[num_operands
++] = Operand(dst
.regClass());
8928 cur_pred_idx
+= skipped
;
8933 /* Handle missing predecessors at the end. This shouldn't happen with loop
8934 * headers and we can't ignore these sources for loop header phis. */
8935 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8938 Operand op
= get_phi_operand(ctx
, src
.second
);
8939 operands
[num_operands
++] = op
;
8940 num_defined
+= !op
.isUndefined();
8942 /* handle block_kind_continue_or_break at loop exit blocks */
8943 while (cur_pred_idx
++ < preds
.size())
8944 operands
[num_operands
++] = Operand(dst
.regClass());
8946 /* If the loop ends with a break, still add a linear continue edge in case
8947 * that break is divergent or continue_or_break is used. We'll either remove
8948 * this operand later in visit_loop() if it's not necessary or replace the
8949 * undef with something correct. */
8950 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8951 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8952 nir_block
*last
= nir_loop_last_block(loop
);
8953 if (last
->successors
[0] != instr
->instr
.block
)
8954 operands
[num_operands
++] = Operand(RegClass());
8957 if (num_defined
== 0) {
8958 Builder
bld(ctx
->program
, ctx
->block
);
8959 if (dst
.regClass() == s1
) {
8960 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8961 } else if (dst
.regClass() == v1
) {
8962 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8964 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8965 for (unsigned i
= 0; i
< dst
.size(); i
++)
8966 vec
->operands
[i
] = Operand(0u);
8967 vec
->definitions
[0] = Definition(dst
);
8968 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8973 /* we can use a linear phi in some cases if one src is undef */
8974 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8975 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8977 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8978 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8979 assert(invert
->kind
& block_kind_invert
);
8981 unsigned then_block
= invert
->linear_preds
[0];
8983 Block
* insert_block
= NULL
;
8984 for (unsigned i
= 0; i
< num_operands
; i
++) {
8985 Operand op
= operands
[i
];
8986 if (op
.isUndefined())
8988 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8989 phi
->operands
[0] = op
;
8992 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8993 phi
->operands
[1] = Operand(dst
.regClass());
8994 phi
->definitions
[0] = Definition(dst
);
8995 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8999 /* try to scalarize vector phis */
9000 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9001 // TODO: scalarize linear phis on divergent ifs
9002 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9003 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9004 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9005 Operand src
= operands
[i
];
9006 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9007 can_scalarize
= false;
9009 if (can_scalarize
) {
9010 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9011 assert(dst
.size() % num_components
== 0);
9012 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9014 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9015 for (unsigned k
= 0; k
< num_components
; k
++) {
9016 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9017 for (unsigned i
= 0; i
< num_operands
; i
++) {
9018 Operand src
= operands
[i
];
9019 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9021 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9022 phi
->definitions
[0] = Definition(phi_dst
);
9023 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9024 new_vec
[k
] = phi_dst
;
9025 vec
->operands
[k
] = Operand(phi_dst
);
9027 vec
->definitions
[0] = Definition(dst
);
9028 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9029 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9034 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9035 for (unsigned i
= 0; i
< num_operands
; i
++)
9036 phi
->operands
[i
] = operands
[i
];
9037 phi
->definitions
[0] = Definition(dst
);
9038 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9042 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9044 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9046 assert(dst
.type() == RegType::sgpr
);
9048 if (dst
.size() == 1) {
9049 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9051 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9052 for (unsigned i
= 0; i
< dst
.size(); i
++)
9053 vec
->operands
[i
] = Operand(0u);
9054 vec
->definitions
[0] = Definition(dst
);
9055 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9059 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9061 Builder
bld(ctx
->program
, ctx
->block
);
9062 Block
*logical_target
;
9063 append_logical_end(ctx
->block
);
9064 unsigned idx
= ctx
->block
->index
;
9066 switch (instr
->type
) {
9067 case nir_jump_break
:
9068 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9069 add_logical_edge(idx
, logical_target
);
9070 ctx
->block
->kind
|= block_kind_break
;
9072 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9073 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9074 /* uniform break - directly jump out of the loop */
9075 ctx
->block
->kind
|= block_kind_uniform
;
9076 ctx
->cf_info
.has_branch
= true;
9077 bld
.branch(aco_opcode::p_branch
);
9078 add_linear_edge(idx
, logical_target
);
9081 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9082 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9084 case nir_jump_continue
:
9085 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9086 add_logical_edge(idx
, logical_target
);
9087 ctx
->block
->kind
|= block_kind_continue
;
9089 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9090 /* for potential uniform breaks after this continue,
9091 we must ensure that they are handled correctly */
9092 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9093 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9094 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9096 /* uniform continue - directly jump to the loop header */
9097 ctx
->block
->kind
|= block_kind_uniform
;
9098 ctx
->cf_info
.has_branch
= true;
9099 bld
.branch(aco_opcode::p_branch
);
9100 add_linear_edge(idx
, logical_target
);
9105 fprintf(stderr
, "Unknown NIR jump instr: ");
9106 nir_print_instr(&instr
->instr
, stderr
);
9107 fprintf(stderr
, "\n");
9111 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9112 ctx
->cf_info
.exec_potentially_empty_break
= true;
9113 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9116 /* remove critical edges from linear CFG */
9117 bld
.branch(aco_opcode::p_branch
);
9118 Block
* break_block
= ctx
->program
->create_and_insert_block();
9119 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9120 break_block
->kind
|= block_kind_uniform
;
9121 add_linear_edge(idx
, break_block
);
9122 /* the loop_header pointer might be invalidated by this point */
9123 if (instr
->type
== nir_jump_continue
)
9124 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9125 add_linear_edge(break_block
->index
, logical_target
);
9126 bld
.reset(break_block
);
9127 bld
.branch(aco_opcode::p_branch
);
9129 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9130 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9131 add_linear_edge(idx
, continue_block
);
9132 append_logical_start(continue_block
);
9133 ctx
->block
= continue_block
;
9137 void visit_block(isel_context
*ctx
, nir_block
*block
)
9139 nir_foreach_instr(instr
, block
) {
9140 switch (instr
->type
) {
9141 case nir_instr_type_alu
:
9142 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9144 case nir_instr_type_load_const
:
9145 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9147 case nir_instr_type_intrinsic
:
9148 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9150 case nir_instr_type_tex
:
9151 visit_tex(ctx
, nir_instr_as_tex(instr
));
9153 case nir_instr_type_phi
:
9154 visit_phi(ctx
, nir_instr_as_phi(instr
));
9156 case nir_instr_type_ssa_undef
:
9157 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9159 case nir_instr_type_deref
:
9161 case nir_instr_type_jump
:
9162 visit_jump(ctx
, nir_instr_as_jump(instr
));
9165 fprintf(stderr
, "Unknown NIR instr type: ");
9166 nir_print_instr(instr
, stderr
);
9167 fprintf(stderr
, "\n");
9172 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9173 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9178 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9179 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9181 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9182 RegClass rc
= vals
[0].regClass();
9184 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9186 unsigned next_pred
= 1;
9188 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9189 Block
& block
= ctx
->program
->blocks
[idx
];
9190 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9191 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9195 if (block
.kind
& block_kind_continue
) {
9196 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9201 bool all_same
= true;
9202 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9203 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9207 val
= vals
[block
.linear_preds
[0] - first
];
9209 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9210 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9211 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9212 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9213 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9214 phi
->definitions
[0] = Definition(val
.getTemp());
9215 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9217 vals
[idx
- first
] = val
;
9220 return vals
[last
- first
];
9223 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9225 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9226 append_logical_end(ctx
->block
);
9227 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9228 Builder
bld(ctx
->program
, ctx
->block
);
9229 bld
.branch(aco_opcode::p_branch
);
9230 unsigned loop_preheader_idx
= ctx
->block
->index
;
9232 Block loop_exit
= Block();
9233 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9234 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9236 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9237 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9238 loop_header
->kind
|= block_kind_loop_header
;
9239 add_edge(loop_preheader_idx
, loop_header
);
9240 ctx
->block
= loop_header
;
9242 /* emit loop body */
9243 unsigned loop_header_idx
= loop_header
->index
;
9244 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9245 append_logical_start(ctx
->block
);
9246 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9248 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9249 if (!ctx
->cf_info
.has_branch
) {
9250 append_logical_end(ctx
->block
);
9251 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9252 /* Discards can result in code running with an empty exec mask.
9253 * This would result in divergent breaks not ever being taken. As a
9254 * workaround, break the loop when the loop mask is empty instead of
9255 * always continuing. */
9256 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9257 unsigned block_idx
= ctx
->block
->index
;
9259 /* create helper blocks to avoid critical edges */
9260 Block
*break_block
= ctx
->program
->create_and_insert_block();
9261 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9262 break_block
->kind
= block_kind_uniform
;
9263 bld
.reset(break_block
);
9264 bld
.branch(aco_opcode::p_branch
);
9265 add_linear_edge(block_idx
, break_block
);
9266 add_linear_edge(break_block
->index
, &loop_exit
);
9268 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9269 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9270 continue_block
->kind
= block_kind_uniform
;
9271 bld
.reset(continue_block
);
9272 bld
.branch(aco_opcode::p_branch
);
9273 add_linear_edge(block_idx
, continue_block
);
9274 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9276 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9277 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9278 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9280 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9281 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9282 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9284 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9287 bld
.reset(ctx
->block
);
9288 bld
.branch(aco_opcode::p_branch
);
9291 /* Fixup phis in loop header from unreachable blocks.
9292 * has_branch/has_divergent_branch also indicates if the loop ends with a
9293 * break/continue instruction, but we don't emit those if unreachable=true */
9295 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9296 bool linear
= ctx
->cf_info
.has_branch
;
9297 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9298 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9299 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9300 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9301 /* the last operand should be the one that needs to be removed */
9302 instr
->operands
.pop_back();
9303 } else if (!is_phi(instr
)) {
9309 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9310 * and the previous one shouldn't both happen at once because a break in the
9311 * merge block would get CSE'd */
9312 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9313 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9314 Operand vals
[num_vals
];
9315 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9316 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9317 if (ctx
->cf_info
.has_branch
)
9318 instr
->operands
.pop_back();
9320 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9321 } else if (!is_phi(instr
)) {
9327 ctx
->cf_info
.has_branch
= false;
9329 // TODO: if the loop has not a single exit, we must add one °°
9330 /* emit loop successor block */
9331 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9332 append_logical_start(ctx
->block
);
9335 // TODO: check if it is beneficial to not branch on continues
9336 /* trim linear phis in loop header */
9337 for (auto&& instr
: loop_entry
->instructions
) {
9338 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9339 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9340 new_phi
->definitions
[0] = instr
->definitions
[0];
9341 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9342 new_phi
->operands
[i
] = instr
->operands
[i
];
9343 /* check that the remaining operands are all the same */
9344 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9345 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9346 instr
.swap(new_phi
);
9347 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9356 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9360 append_logical_end(ctx
->block
);
9361 ctx
->block
->kind
|= block_kind_branch
;
9363 /* branch to linear then block */
9364 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9365 aco_ptr
<Pseudo_branch_instruction
> branch
;
9366 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9367 branch
->operands
[0] = Operand(cond
);
9368 ctx
->block
->instructions
.push_back(std::move(branch
));
9370 ic
->BB_if_idx
= ctx
->block
->index
;
9371 ic
->BB_invert
= Block();
9372 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9373 /* Invert blocks are intentionally not marked as top level because they
9374 * are not part of the logical cfg. */
9375 ic
->BB_invert
.kind
|= block_kind_invert
;
9376 ic
->BB_endif
= Block();
9377 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9378 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9380 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9381 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9382 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9383 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9384 ctx
->cf_info
.parent_if
.is_divergent
= true;
9386 /* divergent branches use cbranch_execz */
9387 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9388 ctx
->cf_info
.exec_potentially_empty_break
= false;
9389 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9391 /** emit logical then block */
9392 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9393 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9394 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9395 ctx
->block
= BB_then_logical
;
9396 append_logical_start(BB_then_logical
);
9399 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9401 Block
*BB_then_logical
= ctx
->block
;
9402 append_logical_end(BB_then_logical
);
9403 /* branch from logical then block to invert block */
9404 aco_ptr
<Pseudo_branch_instruction
> branch
;
9405 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9406 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9407 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9408 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9409 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9410 BB_then_logical
->kind
|= block_kind_uniform
;
9411 assert(!ctx
->cf_info
.has_branch
);
9412 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9413 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9415 /** emit linear then block */
9416 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9417 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9418 BB_then_linear
->kind
|= block_kind_uniform
;
9419 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9420 /* branch from linear then block to invert block */
9421 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9422 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9423 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9425 /** emit invert merge block */
9426 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9427 ic
->invert_idx
= ctx
->block
->index
;
9429 /* branch to linear else block (skip else) */
9430 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9431 branch
->operands
[0] = Operand(ic
->cond
);
9432 ctx
->block
->instructions
.push_back(std::move(branch
));
9434 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9435 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9436 ic
->exec_potentially_empty_break_depth_old
=
9437 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9438 /* divergent branches use cbranch_execz */
9439 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9440 ctx
->cf_info
.exec_potentially_empty_break
= false;
9441 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9443 /** emit logical else block */
9444 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9445 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9446 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9447 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9448 ctx
->block
= BB_else_logical
;
9449 append_logical_start(BB_else_logical
);
9452 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9454 Block
*BB_else_logical
= ctx
->block
;
9455 append_logical_end(BB_else_logical
);
9457 /* branch from logical else block to endif block */
9458 aco_ptr
<Pseudo_branch_instruction
> branch
;
9459 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9460 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9461 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9462 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9463 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9464 BB_else_logical
->kind
|= block_kind_uniform
;
9466 assert(!ctx
->cf_info
.has_branch
);
9467 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9470 /** emit linear else block */
9471 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9472 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9473 BB_else_linear
->kind
|= block_kind_uniform
;
9474 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9476 /* branch from linear else block to endif block */
9477 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9478 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9479 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9482 /** emit endif merge block */
9483 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9484 append_logical_start(ctx
->block
);
9487 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9488 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9489 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9490 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9491 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9492 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9493 !ctx
->cf_info
.parent_if
.is_divergent
) {
9494 ctx
->cf_info
.exec_potentially_empty_break
= false;
9495 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9497 /* uniform control flow never has an empty exec-mask */
9498 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9499 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9500 ctx
->cf_info
.exec_potentially_empty_break
= false;
9501 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9505 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9507 assert(cond
.regClass() == s1
);
9509 append_logical_end(ctx
->block
);
9510 ctx
->block
->kind
|= block_kind_uniform
;
9512 aco_ptr
<Pseudo_branch_instruction
> branch
;
9513 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9514 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9515 branch
->operands
[0] = Operand(cond
);
9516 branch
->operands
[0].setFixed(scc
);
9517 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9519 ic
->BB_if_idx
= ctx
->block
->index
;
9520 ic
->BB_endif
= Block();
9521 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9522 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9524 ctx
->cf_info
.has_branch
= false;
9525 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9527 /** emit then block */
9528 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9529 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9530 add_edge(ic
->BB_if_idx
, BB_then
);
9531 append_logical_start(BB_then
);
9532 ctx
->block
= BB_then
;
9535 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9537 Block
*BB_then
= ctx
->block
;
9539 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9540 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9542 if (!ic
->uniform_has_then_branch
) {
9543 append_logical_end(BB_then
);
9544 /* branch from then block to endif block */
9545 aco_ptr
<Pseudo_branch_instruction
> branch
;
9546 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9547 BB_then
->instructions
.emplace_back(std::move(branch
));
9548 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9549 if (!ic
->then_branch_divergent
)
9550 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9551 BB_then
->kind
|= block_kind_uniform
;
9554 ctx
->cf_info
.has_branch
= false;
9555 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9557 /** emit else block */
9558 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9559 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9560 add_edge(ic
->BB_if_idx
, BB_else
);
9561 append_logical_start(BB_else
);
9562 ctx
->block
= BB_else
;
9565 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9567 Block
*BB_else
= ctx
->block
;
9569 if (!ctx
->cf_info
.has_branch
) {
9570 append_logical_end(BB_else
);
9571 /* branch from then block to endif block */
9572 aco_ptr
<Pseudo_branch_instruction
> branch
;
9573 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9574 BB_else
->instructions
.emplace_back(std::move(branch
));
9575 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9576 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9577 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9578 BB_else
->kind
|= block_kind_uniform
;
9581 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9582 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9584 /** emit endif merge block */
9585 if (!ctx
->cf_info
.has_branch
) {
9586 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9587 append_logical_start(ctx
->block
);
9591 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9593 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9594 Builder
bld(ctx
->program
, ctx
->block
);
9595 aco_ptr
<Pseudo_branch_instruction
> branch
;
9598 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9600 * Uniform conditionals are represented in the following way*) :
9602 * The linear and logical CFG:
9605 * BB_THEN (logical) BB_ELSE (logical)
9609 * *) Exceptions may be due to break and continue statements within loops
9610 * If a break/continue happens within uniform control flow, it branches
9611 * to the loop exit/entry block. Otherwise, it branches to the next
9615 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9616 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9617 cond
= bool_to_scalar_condition(ctx
, cond
);
9619 begin_uniform_if_then(ctx
, &ic
, cond
);
9620 visit_cf_list(ctx
, &if_stmt
->then_list
);
9622 begin_uniform_if_else(ctx
, &ic
);
9623 visit_cf_list(ctx
, &if_stmt
->else_list
);
9625 end_uniform_if(ctx
, &ic
);
9626 } else { /* non-uniform condition */
9628 * To maintain a logical and linear CFG without critical edges,
9629 * non-uniform conditionals are represented in the following way*) :
9634 * BB_THEN (logical) BB_THEN (linear)
9636 * BB_INVERT (linear)
9638 * BB_ELSE (logical) BB_ELSE (linear)
9645 * BB_THEN (logical) BB_ELSE (logical)
9649 * *) Exceptions may be due to break and continue statements within loops
9652 begin_divergent_if_then(ctx
, &ic
, cond
);
9653 visit_cf_list(ctx
, &if_stmt
->then_list
);
9655 begin_divergent_if_else(ctx
, &ic
);
9656 visit_cf_list(ctx
, &if_stmt
->else_list
);
9658 end_divergent_if(ctx
, &ic
);
9661 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9664 static bool visit_cf_list(isel_context
*ctx
,
9665 struct exec_list
*list
)
9667 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9668 switch (node
->type
) {
9669 case nir_cf_node_block
:
9670 visit_block(ctx
, nir_cf_node_as_block(node
));
9672 case nir_cf_node_if
:
9673 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9676 case nir_cf_node_loop
:
9677 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9680 unreachable("unimplemented cf list type");
9686 static void create_null_export(isel_context
*ctx
)
9688 /* Some shader stages always need to have exports.
9689 * So when there is none, we need to add a null export.
9692 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9693 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9694 Builder
bld(ctx
->program
, ctx
->block
);
9695 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9696 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9699 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9701 assert(ctx
->stage
== vertex_vs
||
9702 ctx
->stage
== tess_eval_vs
||
9703 ctx
->stage
== gs_copy_vs
||
9704 ctx
->stage
== ngg_vertex_gs
||
9705 ctx
->stage
== ngg_tess_eval_gs
);
9707 int offset
= (ctx
->stage
& sw_tes
)
9708 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9709 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9710 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9711 if (!is_pos
&& !mask
)
9713 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9715 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9716 exp
->enabled_mask
= mask
;
9717 for (unsigned i
= 0; i
< 4; ++i
) {
9718 if (mask
& (1 << i
))
9719 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9721 exp
->operands
[i
] = Operand(v1
);
9723 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9724 * Setting valid_mask=1 prevents it and has no other effect.
9726 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9728 exp
->compressed
= false;
9730 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9732 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9733 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9738 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9740 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9741 exp
->enabled_mask
= 0;
9742 for (unsigned i
= 0; i
< 4; ++i
)
9743 exp
->operands
[i
] = Operand(v1
);
9744 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9745 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9746 exp
->enabled_mask
|= 0x1;
9748 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9749 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9750 exp
->enabled_mask
|= 0x4;
9752 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9753 if (ctx
->options
->chip_class
< GFX9
) {
9754 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9755 exp
->enabled_mask
|= 0x8;
9757 Builder
bld(ctx
->program
, ctx
->block
);
9759 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9760 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9761 if (exp
->operands
[2].isTemp())
9762 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9764 exp
->operands
[2] = Operand(out
);
9765 exp
->enabled_mask
|= 0x4;
9768 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9770 exp
->compressed
= false;
9771 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9772 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9775 static void create_export_phis(isel_context
*ctx
)
9777 /* Used when exports are needed, but the output temps are defined in a preceding block.
9778 * This function will set up phis in order to access the outputs in the next block.
9781 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9782 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9783 ctx
->block
->instructions
.pop_back();
9785 Builder
bld(ctx
->program
, ctx
->block
);
9787 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9788 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9789 for (unsigned i
= 0; i
< 4; ++i
) {
9790 if (!(mask
& (1 << i
)))
9793 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9794 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9795 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9799 bld
.insert(std::move(logical_start
));
9802 static void create_vs_exports(isel_context
*ctx
)
9804 assert(ctx
->stage
== vertex_vs
||
9805 ctx
->stage
== tess_eval_vs
||
9806 ctx
->stage
== gs_copy_vs
||
9807 ctx
->stage
== ngg_vertex_gs
||
9808 ctx
->stage
== ngg_tess_eval_gs
);
9810 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9811 ? &ctx
->program
->info
->tes
.outinfo
9812 : &ctx
->program
->info
->vs
.outinfo
;
9814 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9815 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9816 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9819 if (ctx
->options
->key
.has_multiview_view_index
) {
9820 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9821 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9824 /* the order these position exports are created is important */
9826 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9827 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9828 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9829 exported_pos
= true;
9831 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9832 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9833 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9834 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9836 if (ctx
->export_clip_dists
) {
9837 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9838 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9839 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9840 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9843 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9844 if (i
< VARYING_SLOT_VAR0
&&
9845 i
!= VARYING_SLOT_LAYER
&&
9846 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9847 i
!= VARYING_SLOT_VIEWPORT
)
9850 export_vs_varying(ctx
, i
, false, NULL
);
9854 create_null_export(ctx
);
9857 static bool export_fs_mrt_z(isel_context
*ctx
)
9859 Builder
bld(ctx
->program
, ctx
->block
);
9860 unsigned enabled_channels
= 0;
9864 for (unsigned i
= 0; i
< 4; ++i
) {
9865 values
[i
] = Operand(v1
);
9868 /* Both stencil and sample mask only need 16-bits. */
9869 if (!ctx
->program
->info
->ps
.writes_z
&&
9870 (ctx
->program
->info
->ps
.writes_stencil
||
9871 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9872 compr
= true; /* COMPR flag */
9874 if (ctx
->program
->info
->ps
.writes_stencil
) {
9875 /* Stencil should be in X[23:16]. */
9876 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9877 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9878 enabled_channels
|= 0x3;
9881 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9882 /* SampleMask should be in Y[15:0]. */
9883 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9884 enabled_channels
|= 0xc;
9887 if (ctx
->program
->info
->ps
.writes_z
) {
9888 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9889 enabled_channels
|= 0x1;
9892 if (ctx
->program
->info
->ps
.writes_stencil
) {
9893 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9894 enabled_channels
|= 0x2;
9897 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9898 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9899 enabled_channels
|= 0x4;
9903 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9904 * writemask component.
9906 if (ctx
->options
->chip_class
== GFX6
&&
9907 ctx
->options
->family
!= CHIP_OLAND
&&
9908 ctx
->options
->family
!= CHIP_HAINAN
) {
9909 enabled_channels
|= 0x1;
9912 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9913 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9918 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9920 Builder
bld(ctx
->program
, ctx
->block
);
9921 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9924 for (unsigned i
= 0; i
< 4; ++i
) {
9925 if (write_mask
& (1 << i
)) {
9926 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9928 values
[i
] = Operand(v1
);
9932 unsigned target
, col_format
;
9933 unsigned enabled_channels
= 0;
9934 aco_opcode compr_op
= (aco_opcode
)0;
9936 slot
-= FRAG_RESULT_DATA0
;
9937 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9938 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9940 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9941 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9942 bool is_16bit
= values
[0].regClass() == v2b
;
9946 case V_028714_SPI_SHADER_ZERO
:
9947 enabled_channels
= 0; /* writemask */
9948 target
= V_008DFC_SQ_EXP_NULL
;
9951 case V_028714_SPI_SHADER_32_R
:
9952 enabled_channels
= 1;
9955 case V_028714_SPI_SHADER_32_GR
:
9956 enabled_channels
= 0x3;
9959 case V_028714_SPI_SHADER_32_AR
:
9960 if (ctx
->options
->chip_class
>= GFX10
) {
9961 /* Special case: on GFX10, the outputs are different for 32_AR */
9962 enabled_channels
= 0x3;
9963 values
[1] = values
[3];
9964 values
[3] = Operand(v1
);
9966 enabled_channels
= 0x9;
9970 case V_028714_SPI_SHADER_FP16_ABGR
:
9971 enabled_channels
= 0x5;
9972 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9974 if (ctx
->options
->chip_class
>= GFX9
) {
9975 /* Pack the FP16 values together instead of converting them to
9976 * FP32 and back to FP16.
9977 * TODO: use p_create_vector and let the compiler optimizes.
9979 compr_op
= aco_opcode::v_pack_b32_f16
;
9981 for (unsigned i
= 0; i
< 4; i
++) {
9982 if ((write_mask
>> i
) & 1)
9983 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9989 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9990 enabled_channels
= 0x5;
9991 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9992 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9994 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9998 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9999 enabled_channels
= 0x5;
10000 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10001 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10003 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10007 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10008 enabled_channels
= 0x5;
10009 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10010 if (is_int8
|| is_int10
) {
10012 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10013 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10015 for (unsigned i
= 0; i
< 4; i
++) {
10016 if ((write_mask
>> i
) & 1) {
10017 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10018 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10022 } else if (is_16bit
) {
10023 for (unsigned i
= 0; i
< 4; i
++) {
10024 if ((write_mask
>> i
) & 1) {
10025 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10026 values
[i
] = Operand(tmp
);
10033 case V_028714_SPI_SHADER_SINT16_ABGR
:
10034 enabled_channels
= 0x5;
10035 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10036 if (is_int8
|| is_int10
) {
10038 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10039 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10040 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10041 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10043 for (unsigned i
= 0; i
< 4; i
++) {
10044 if ((write_mask
>> i
) & 1) {
10045 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10046 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10048 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10049 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10053 } else if (is_16bit
) {
10054 for (unsigned i
= 0; i
< 4; i
++) {
10055 if ((write_mask
>> i
) & 1) {
10056 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10057 values
[i
] = Operand(tmp
);
10063 case V_028714_SPI_SHADER_32_ABGR
:
10064 enabled_channels
= 0xF;
10071 if (target
== V_008DFC_SQ_EXP_NULL
)
10074 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10075 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10077 (col_format
== V_028714_SPI_SHADER_32_R
||
10078 col_format
== V_028714_SPI_SHADER_32_GR
||
10079 col_format
== V_028714_SPI_SHADER_32_AR
||
10080 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10081 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10082 for (int i
= 0; i
< 4; i
++) {
10083 if (!(write_mask
& (1 << i
)))
10086 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10087 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10088 bld
.copy(bld
.def(v1
), Operand(3u)));
10089 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10090 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10094 if ((bool) compr_op
) {
10095 for (int i
= 0; i
< 2; i
++) {
10096 /* check if at least one of the values to be compressed is enabled */
10097 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10099 enabled_channels
|= enabled
<< (i
*2);
10100 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10101 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10102 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10104 values
[i
] = Operand(v1
);
10107 values
[2] = Operand(v1
);
10108 values
[3] = Operand(v1
);
10110 for (int i
= 0; i
< 4; i
++)
10111 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10114 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10115 enabled_channels
, target
, (bool) compr_op
);
10119 static void create_fs_exports(isel_context
*ctx
)
10121 bool exported
= false;
10123 /* Export depth, stencil and sample mask. */
10124 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10125 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10126 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10127 exported
|= export_fs_mrt_z(ctx
);
10129 /* Export all color render targets. */
10130 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10131 if (ctx
->outputs
.mask
[i
])
10132 exported
|= export_fs_mrt_color(ctx
, i
);
10135 create_null_export(ctx
);
10138 static void write_tcs_tess_factors(isel_context
*ctx
)
10140 unsigned outer_comps
;
10141 unsigned inner_comps
;
10143 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10160 Builder
bld(ctx
->program
, ctx
->block
);
10162 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10163 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10164 bld
.sopp(aco_opcode::s_barrier
);
10166 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10167 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10169 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10170 if_context ic_invocation_id_is_zero
;
10171 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10172 bld
.reset(ctx
->block
);
10174 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10176 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10177 unsigned stride
= inner_comps
+ outer_comps
;
10178 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10182 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10184 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10186 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10187 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10188 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10190 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10191 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10193 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10194 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10195 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10196 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10199 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10200 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10201 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10202 unsigned tf_const_offset
= 0;
10204 if (ctx
->program
->chip_class
<= GFX8
) {
10205 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10206 if_context ic_rel_patch_id_is_zero
;
10207 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10208 bld
.reset(ctx
->block
);
10210 /* Store the dynamic HS control word. */
10211 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10212 bld
.mubuf(aco_opcode::buffer_store_dword
,
10213 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10214 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10215 /* disable_wqm */ false, /* glc */ true);
10216 tf_const_offset
+= 4;
10218 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10219 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10220 bld
.reset(ctx
->block
);
10223 assert(stride
== 2 || stride
== 4 || stride
== 6);
10224 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10225 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10227 /* Store to offchip for TES to read - only if TES reads them */
10228 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10229 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10230 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10232 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10233 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10235 if (likely(inner_comps
)) {
10236 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10237 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10241 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10242 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10245 static void emit_stream_output(isel_context
*ctx
,
10246 Temp
const *so_buffers
,
10247 Temp
const *so_write_offset
,
10248 const struct radv_stream_output
*output
)
10250 unsigned num_comps
= util_bitcount(output
->component_mask
);
10251 unsigned writemask
= (1 << num_comps
) - 1;
10252 unsigned loc
= output
->location
;
10253 unsigned buf
= output
->buffer
;
10255 assert(num_comps
&& num_comps
<= 4);
10256 if (!num_comps
|| num_comps
> 4)
10259 unsigned start
= ffs(output
->component_mask
) - 1;
10262 bool all_undef
= true;
10263 assert(ctx
->stage
& hw_vs
);
10264 for (unsigned i
= 0; i
< num_comps
; i
++) {
10265 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10266 all_undef
= all_undef
&& !out
[i
].id();
10271 while (writemask
) {
10273 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10274 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10275 /* GFX6 doesn't support storing vec3, split it. */
10276 writemask
|= 1u << (start
+ 2);
10280 unsigned offset
= output
->offset
+ start
* 4;
10282 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10283 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10284 for (int i
= 0; i
< count
; ++i
)
10285 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10286 vec
->definitions
[0] = Definition(write_data
);
10287 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10292 opcode
= aco_opcode::buffer_store_dword
;
10295 opcode
= aco_opcode::buffer_store_dwordx2
;
10298 opcode
= aco_opcode::buffer_store_dwordx3
;
10301 opcode
= aco_opcode::buffer_store_dwordx4
;
10304 unreachable("Unsupported dword count.");
10307 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10308 store
->operands
[0] = Operand(so_buffers
[buf
]);
10309 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10310 store
->operands
[2] = Operand((uint32_t) 0);
10311 store
->operands
[3] = Operand(write_data
);
10312 if (offset
> 4095) {
10313 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10314 Builder
bld(ctx
->program
, ctx
->block
);
10315 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10317 store
->offset
= offset
;
10319 store
->offen
= true;
10321 store
->dlc
= false;
10323 store
->can_reorder
= true;
10324 ctx
->block
->instructions
.emplace_back(std::move(store
));
10328 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10330 Builder
bld(ctx
->program
, ctx
->block
);
10332 Temp so_buffers
[4];
10333 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10334 for (unsigned i
= 0; i
< 4; i
++) {
10335 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10339 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10340 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10343 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10344 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10346 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10348 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10351 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10353 bld
.reset(ctx
->block
);
10355 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10357 Temp so_write_offset
[4];
10359 for (unsigned i
= 0; i
< 4; i
++) {
10360 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10365 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10366 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10367 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10368 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10370 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10372 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10373 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10374 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10375 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10379 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10380 struct radv_stream_output
*output
=
10381 &ctx
->program
->info
->so
.outputs
[i
];
10382 if (stream
!= output
->stream
)
10385 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10388 begin_divergent_if_else(ctx
, &ic
);
10389 end_divergent_if(ctx
, &ic
);
10392 } /* end namespace */
10394 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10396 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10397 Builder
bld(ctx
->program
, ctx
->block
);
10398 constexpr unsigned hs_idx
= 1u;
10399 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10400 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10401 Operand((8u << 16) | (hs_idx
* 8u)));
10402 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10404 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10406 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10407 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10408 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10409 ls_has_nonzero_hs_threads
);
10410 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10411 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10412 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10413 ls_has_nonzero_hs_threads
);
10414 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10415 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10416 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10417 ls_has_nonzero_hs_threads
);
10419 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10420 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10421 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10424 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10426 /* Split all arguments except for the first (ring_offsets) and the last
10427 * (exec) so that the dead channels don't stay live throughout the program.
10429 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10430 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10431 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10432 startpgm
->definitions
[i
].regClass().size());
10437 void handle_bc_optimize(isel_context
*ctx
)
10439 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10440 Builder
bld(ctx
->program
, ctx
->block
);
10441 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10442 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10443 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10444 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10445 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10446 if (uses_center
&& uses_centroid
) {
10447 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10448 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10450 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10452 for (unsigned i
= 0; i
< 2; i
++) {
10453 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10454 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10455 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10456 persp_centroid
, persp_center
, sel
);
10458 ctx
->persp_centroid
= bld
.tmp(v2
);
10459 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10460 Operand(new_coord
[0]), Operand(new_coord
[1]));
10461 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10464 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10466 for (unsigned i
= 0; i
< 2; i
++) {
10467 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10468 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10469 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10470 linear_centroid
, linear_center
, sel
);
10472 ctx
->linear_centroid
= bld
.tmp(v2
);
10473 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10474 Operand(new_coord
[0]), Operand(new_coord
[1]));
10475 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10480 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10482 Program
*program
= ctx
->program
;
10484 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10486 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10487 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10488 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10489 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10490 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10492 program
->next_fp_mode
.must_flush_denorms32
=
10493 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10494 program
->next_fp_mode
.must_flush_denorms16_64
=
10495 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10496 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10498 program
->next_fp_mode
.care_about_round32
=
10499 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10501 program
->next_fp_mode
.care_about_round16_64
=
10502 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10503 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10505 /* default to preserving fp16 and fp64 denorms, since it's free */
10506 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10507 program
->next_fp_mode
.denorm16_64
= 0;
10509 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10511 /* preserving fp32 denorms is expensive, so only do it if asked */
10512 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10513 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10515 program
->next_fp_mode
.denorm32
= 0;
10517 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10518 program
->next_fp_mode
.round32
= fp_round_tz
;
10520 program
->next_fp_mode
.round32
= fp_round_ne
;
10522 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10523 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10525 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10527 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10530 void cleanup_cfg(Program
*program
)
10532 /* create linear_succs/logical_succs */
10533 for (Block
& BB
: program
->blocks
) {
10534 for (unsigned idx
: BB
.linear_preds
)
10535 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10536 for (unsigned idx
: BB
.logical_preds
)
10537 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10541 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10543 Builder
bld(ctx
->program
, ctx
->block
);
10545 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10546 Temp count
= i
== 0
10547 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10548 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10549 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10551 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10554 if (ctx
->program
->wave_size
== 64) {
10555 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10556 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10557 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10559 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10560 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10566 bool ngg_early_prim_export(isel_context
*ctx
)
10568 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10572 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10574 Builder
bld(ctx
->program
, ctx
->block
);
10576 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10577 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10579 /* Get the id of the current wave within the threadgroup (workgroup) */
10580 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10581 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10583 /* Execute the following code only on the first wave (wave id 0),
10584 * use the SCC def to tell if the wave id is zero or not.
10586 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10588 begin_uniform_if_then(ctx
, &ic
, cond
);
10589 begin_uniform_if_else(ctx
, &ic
);
10590 bld
.reset(ctx
->block
);
10592 /* Number of vertices output by VS/TES */
10593 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10594 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10595 /* Number of primitives output by VS/TES */
10596 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10597 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10599 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10600 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10601 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10603 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10604 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10606 end_uniform_if(ctx
, &ic
);
10608 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10609 bld
.reset(ctx
->block
);
10610 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10613 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10615 Builder
bld(ctx
->program
, ctx
->block
);
10617 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10618 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10621 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10624 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10625 assert(vtxindex
[i
].id());
10628 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10632 /* The initial edge flag is always false in tess eval shaders. */
10633 if (ctx
->stage
== ngg_vertex_gs
) {
10634 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10635 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10639 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10644 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10646 Builder
bld(ctx
->program
, ctx
->block
);
10647 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10649 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10650 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10651 false /* compressed */, true/* done */, false /* valid mask */);
10654 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10656 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10657 * These must always come before VS exports.
10659 * It is recommended to do these as early as possible. They can be at the beginning when
10660 * there is no SW GS and the shader doesn't write edge flags.
10664 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10665 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10667 Builder
bld(ctx
->program
, ctx
->block
);
10668 constexpr unsigned max_vertices_per_primitive
= 3;
10669 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10671 if (ctx
->stage
== ngg_vertex_gs
) {
10672 /* TODO: optimize for points & lines */
10673 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10674 if (ctx
->shader
->info
.tess
.point_mode
)
10675 num_vertices_per_primitive
= 1;
10676 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10677 num_vertices_per_primitive
= 2;
10679 unreachable("Unsupported NGG shader stage");
10682 Temp vtxindex
[max_vertices_per_primitive
];
10683 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10684 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10685 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10686 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10687 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10688 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10689 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10690 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10692 /* Export primitive data to the index buffer. */
10693 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10695 /* Export primitive ID. */
10696 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10697 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10698 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10699 Temp provoking_vtx_index
= vtxindex
[0];
10700 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10702 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10705 begin_divergent_if_else(ctx
, &ic
);
10706 end_divergent_if(ctx
, &ic
);
10709 void ngg_emit_nogs_output(isel_context
*ctx
)
10711 /* Emits NGG GS output, for stages that don't have SW GS. */
10714 Builder
bld(ctx
->program
, ctx
->block
);
10715 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10717 /* NGG streamout is currently disabled by default. */
10718 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10720 if (late_prim_export
) {
10721 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10722 create_export_phis(ctx
);
10723 /* Do what we need to do in the GS threads. */
10724 ngg_emit_nogs_gsthreads(ctx
);
10726 /* What comes next should be executed on ES threads. */
10727 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10728 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10729 bld
.reset(ctx
->block
);
10732 /* Export VS outputs */
10733 ctx
->block
->kind
|= block_kind_export_end
;
10734 create_vs_exports(ctx
);
10736 /* Export primitive ID */
10737 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10740 if (ctx
->stage
== ngg_vertex_gs
) {
10741 /* Wait for GS threads to store primitive ID in LDS. */
10742 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10743 bld
.sopp(aco_opcode::s_barrier
);
10745 /* Calculate LDS address where the GS threads stored the primitive ID. */
10746 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10747 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10748 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10749 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10750 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10751 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10753 /* Load primitive ID from LDS. */
10754 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10755 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10756 /* TES: Just use the patch ID as the primitive ID. */
10757 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10759 unreachable("unsupported NGG shader stage.");
10762 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10763 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10765 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10768 if (late_prim_export
) {
10769 begin_divergent_if_else(ctx
, &ic
);
10770 end_divergent_if(ctx
, &ic
);
10771 bld
.reset(ctx
->block
);
10775 void select_program(Program
*program
,
10776 unsigned shader_count
,
10777 struct nir_shader
*const *shaders
,
10778 ac_shader_config
* config
,
10779 struct radv_shader_args
*args
)
10781 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10782 if_context ic_merged_wave_info
;
10783 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10785 for (unsigned i
= 0; i
< shader_count
; i
++) {
10786 nir_shader
*nir
= shaders
[i
];
10787 init_context(&ctx
, nir
);
10789 setup_fp_mode(&ctx
, nir
);
10792 /* needs to be after init_context() for FS */
10793 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10794 append_logical_start(ctx
.block
);
10796 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10797 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10799 split_arguments(&ctx
, startpgm
);
10803 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10805 if (ngg_early_prim_export(&ctx
))
10806 ngg_emit_nogs_gsthreads(&ctx
);
10809 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10810 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10811 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10812 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10813 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10814 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10815 ctx
.stage
== tess_eval_geometry_gs
));
10817 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10818 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10819 if (check_merged_wave_info
) {
10820 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10821 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10825 Builder
bld(ctx
.program
, ctx
.block
);
10827 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10828 bld
.sopp(aco_opcode::s_barrier
);
10830 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10831 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10833 } else if (ctx
.stage
== geometry_gs
)
10834 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10836 if (ctx
.stage
== fragment_fs
)
10837 handle_bc_optimize(&ctx
);
10839 visit_cf_list(&ctx
, &func
->body
);
10841 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10842 emit_streamout(&ctx
, 0);
10844 if (ctx
.stage
& hw_vs
) {
10845 create_vs_exports(&ctx
);
10846 ctx
.block
->kind
|= block_kind_export_end
;
10847 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10848 ngg_emit_nogs_output(&ctx
);
10849 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10850 Builder
bld(ctx
.program
, ctx
.block
);
10851 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10852 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10853 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10854 write_tcs_tess_factors(&ctx
);
10857 if (ctx
.stage
== fragment_fs
) {
10858 create_fs_exports(&ctx
);
10859 ctx
.block
->kind
|= block_kind_export_end
;
10862 if (endif_merged_wave_info
) {
10863 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10864 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10867 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10868 ngg_emit_nogs_output(&ctx
);
10870 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10871 /* Outputs of the previous stage are inputs to the next stage */
10872 ctx
.inputs
= ctx
.outputs
;
10873 ctx
.outputs
= shader_io_state();
10877 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10879 append_logical_end(ctx
.block
);
10880 ctx
.block
->kind
|= block_kind_uniform
;
10881 Builder
bld(ctx
.program
, ctx
.block
);
10882 if (ctx
.program
->wb_smem_l1_on_end
)
10883 bld
.smem(aco_opcode::s_dcache_wb
, false);
10884 bld
.sopp(aco_opcode::s_endpgm
);
10886 cleanup_cfg(program
);
10889 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10890 ac_shader_config
* config
,
10891 struct radv_shader_args
*args
)
10893 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10895 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10896 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10897 program
->next_fp_mode
.must_flush_denorms32
= false;
10898 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10899 program
->next_fp_mode
.care_about_round32
= false;
10900 program
->next_fp_mode
.care_about_round16_64
= false;
10901 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10902 program
->next_fp_mode
.denorm32
= 0;
10903 program
->next_fp_mode
.round32
= fp_round_ne
;
10904 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10905 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10907 add_startpgm(&ctx
);
10908 append_logical_start(ctx
.block
);
10910 Builder
bld(ctx
.program
, ctx
.block
);
10912 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10914 Operand
stream_id(0u);
10915 if (args
->shader_info
->so
.num_outputs
)
10916 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10917 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10919 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10921 std::stack
<Block
> endif_blocks
;
10923 for (unsigned stream
= 0; stream
< 4; stream
++) {
10924 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10927 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10928 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10931 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10933 unsigned BB_if_idx
= ctx
.block
->index
;
10934 Block BB_endif
= Block();
10935 if (!stream_id
.isConstant()) {
10937 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10938 append_logical_end(ctx
.block
);
10939 ctx
.block
->kind
|= block_kind_uniform
;
10940 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10942 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10944 ctx
.block
= ctx
.program
->create_and_insert_block();
10945 add_edge(BB_if_idx
, ctx
.block
);
10946 bld
.reset(ctx
.block
);
10947 append_logical_start(ctx
.block
);
10950 unsigned offset
= 0;
10951 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10952 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10955 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10956 unsigned length
= util_last_bit(output_usage_mask
);
10957 for (unsigned j
= 0; j
< length
; ++j
) {
10958 if (!(output_usage_mask
& (1 << j
)))
10961 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10962 Temp voffset
= vtx_offset
;
10963 if (const_offset
>= 4096u) {
10964 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10965 const_offset
%= 4096u;
10968 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10969 mubuf
->definitions
[0] = bld
.def(v1
);
10970 mubuf
->operands
[0] = Operand(gsvs_ring
);
10971 mubuf
->operands
[1] = Operand(voffset
);
10972 mubuf
->operands
[2] = Operand(0u);
10973 mubuf
->offen
= true;
10974 mubuf
->offset
= const_offset
;
10977 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10978 mubuf
->barrier
= barrier_none
;
10979 mubuf
->can_reorder
= true;
10981 ctx
.outputs
.mask
[i
] |= 1 << j
;
10982 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10984 bld
.insert(std::move(mubuf
));
10990 if (args
->shader_info
->so
.num_outputs
) {
10991 emit_streamout(&ctx
, stream
);
10992 bld
.reset(ctx
.block
);
10996 create_vs_exports(&ctx
);
10997 ctx
.block
->kind
|= block_kind_export_end
;
11000 if (!stream_id
.isConstant()) {
11001 append_logical_end(ctx
.block
);
11003 /* branch from then block to endif block */
11004 bld
.branch(aco_opcode::p_branch
);
11005 add_edge(ctx
.block
->index
, &BB_endif
);
11006 ctx
.block
->kind
|= block_kind_uniform
;
11008 /* emit else block */
11009 ctx
.block
= ctx
.program
->create_and_insert_block();
11010 add_edge(BB_if_idx
, ctx
.block
);
11011 bld
.reset(ctx
.block
);
11012 append_logical_start(ctx
.block
);
11014 endif_blocks
.push(std::move(BB_endif
));
11018 while (!endif_blocks
.empty()) {
11019 Block BB_endif
= std::move(endif_blocks
.top());
11020 endif_blocks
.pop();
11022 Block
*BB_else
= ctx
.block
;
11024 append_logical_end(BB_else
);
11025 /* branch from else block to endif block */
11026 bld
.branch(aco_opcode::p_branch
);
11027 add_edge(BB_else
->index
, &BB_endif
);
11028 BB_else
->kind
|= block_kind_uniform
;
11030 /** emit endif merge block */
11031 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11032 bld
.reset(ctx
.block
);
11033 append_logical_start(ctx
.block
);
11036 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11038 append_logical_end(ctx
.block
);
11039 ctx
.block
->kind
|= block_kind_uniform
;
11040 bld
.sopp(aco_opcode::s_endpgm
);
11042 cleanup_cfg(program
);