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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
308 if (num_components
> vec_src
.size()) {
309 if (vec_src
.type() == RegType::sgpr
) {
310 /* should still help get_alu_src() */
311 emit_split_vector(ctx
, vec_src
, vec_src
.size());
314 /* sub-dword split */
315 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
317 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
319 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
320 split
->operands
[0] = Operand(vec_src
);
321 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
322 for (unsigned i
= 0; i
< num_components
; i
++) {
323 elems
[i
] = {ctx
->program
->allocateId(), rc
};
324 split
->definitions
[i
] = Definition(elems
[i
]);
326 ctx
->block
->instructions
.emplace_back(std::move(split
));
327 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
330 /* This vector expansion uses a mask to determine which elements in the new vector
331 * come from the original vector. The other elements are undefined. */
332 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
334 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
339 Builder
bld(ctx
->program
, ctx
->block
);
340 if (num_components
== 1) {
341 if (dst
.type() == RegType::sgpr
)
342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
344 bld
.copy(Definition(dst
), vec_src
);
348 unsigned component_size
= dst
.size() / num_components
;
349 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
351 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
352 vec
->definitions
[0] = Definition(dst
);
354 for (unsigned i
= 0; i
< num_components
; i
++) {
355 if (mask
& (1 << i
)) {
356 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
357 if (dst
.type() == RegType::sgpr
)
358 src
= bld
.as_uniform(src
);
359 vec
->operands
[i
] = Operand(src
);
361 vec
->operands
[i
] = Operand(0u);
363 elems
[i
] = vec
->operands
[i
].getTemp();
365 ctx
->block
->instructions
.emplace_back(std::move(vec
));
366 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
369 /* adjust misaligned small bit size loads */
370 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
372 Builder
bld(ctx
->program
, ctx
->block
);
374 Temp select
= Temp();
375 if (offset
.isConstant()) {
376 assert(offset
.constantValue() && offset
.constantValue() < 4);
377 shift
= Operand(offset
.constantValue() * 8);
379 /* bit_offset = 8 * (offset & 0x3) */
380 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
381 select
= bld
.tmp(s1
);
382 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
385 if (vec
.size() == 1) {
386 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
387 } else if (vec
.size() == 2) {
388 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
389 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
391 emit_split_vector(ctx
, dst
, 2);
393 emit_extract_vector(ctx
, tmp
, 0, dst
);
394 } else if (vec
.size() == 4) {
395 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
396 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
397 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
398 if (select
!= Temp())
399 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
400 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
401 Temp mid
= bld
.tmp(s1
);
402 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
403 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
404 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
406 emit_split_vector(ctx
, dst
, 2);
410 /* this function trims subdword vectors:
411 * if dst is vgpr - split the src and create a shrunk version according to the mask.
412 * if dst is sgpr - split the src, but move the original to sgpr. */
413 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
415 assert(vec_src
.type() == RegType::vgpr
);
416 emit_split_vector(ctx
, vec_src
, num_components
);
418 Builder
bld(ctx
->program
, ctx
->block
);
419 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
420 unsigned component_size
= vec_src
.bytes() / num_components
;
421 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
424 for (unsigned i
= 0; i
< num_components
; i
++) {
426 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
429 if (dst
.type() == RegType::vgpr
) {
430 assert(dst
.bytes() == k
* component_size
);
431 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
432 for (unsigned i
= 0; i
< k
; i
++)
433 vec
->operands
[i
] = Operand(elems
[i
]);
434 vec
->definitions
[0] = Definition(dst
);
435 bld
.insert(std::move(vec
));
437 // TODO: alignbyte if mask doesn't start with 1?
439 assert(dst
.size() == vec_src
.size());
440 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
442 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
445 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
447 Builder
bld(ctx
->program
, ctx
->block
);
449 dst
= bld
.tmp(bld
.lm
);
451 assert(val
.regClass() == s1
);
452 assert(dst
.regClass() == bld
.lm
);
454 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
457 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
459 Builder
bld(ctx
->program
, ctx
->block
);
463 assert(val
.regClass() == bld
.lm
);
464 assert(dst
.regClass() == s1
);
466 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
467 Temp tmp
= bld
.tmp(s1
);
468 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
469 return emit_wqm(ctx
, tmp
, dst
);
472 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
474 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
475 return get_ssa_temp(ctx
, src
.src
.ssa
);
477 if (src
.src
.ssa
->num_components
== size
) {
478 bool identity_swizzle
= true;
479 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
480 if (src
.swizzle
[i
] != i
)
481 identity_swizzle
= false;
483 if (identity_swizzle
)
484 return get_ssa_temp(ctx
, src
.src
.ssa
);
487 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
488 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
489 assert(elem_size
> 0);
490 assert(vec
.bytes() % elem_size
== 0);
492 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
493 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
495 unsigned swizzle
= src
.swizzle
[0];
496 if (vec
.size() > 1) {
497 assert(src
.src
.ssa
->bit_size
== 16);
498 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
499 swizzle
= swizzle
& 1;
504 Temp dst
{ctx
->program
->allocateId(), s1
};
505 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
506 bfe
->operands
[0] = Operand(vec
);
507 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
508 bfe
->definitions
[0] = Definition(dst
);
509 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
510 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
514 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
516 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
519 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
520 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
521 for (unsigned i
= 0; i
< size
; ++i
) {
522 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
523 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
525 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
526 vec_instr
->definitions
[0] = Definition(dst
);
527 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
528 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
533 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
537 Builder
bld(ctx
->program
, ctx
->block
);
538 if (ptr
.type() == RegType::vgpr
)
539 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
540 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
541 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
544 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
546 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
547 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
548 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
549 sop2
->definitions
[0] = Definition(dst
);
551 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
552 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
555 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
556 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
558 Builder
bld(ctx
->program
, ctx
->block
);
559 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
560 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
561 if (src1
.type() == RegType::sgpr
) {
562 if (commutative
&& src0
.type() == RegType::vgpr
) {
567 src1
= as_vgpr(ctx
, src1
);
571 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
572 assert(dst
.size() == 1);
573 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
574 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
576 bld
.vop2(op
, Definition(dst
), src0
, src1
);
580 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
581 bool flush_denorms
= false)
583 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
584 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
585 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
587 /* ensure that the instruction has at most 1 sgpr operand
588 * The optimizer will inline constants for us */
589 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
590 src0
= as_vgpr(ctx
, src0
);
591 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
592 src1
= as_vgpr(ctx
, src1
);
593 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
594 src2
= as_vgpr(ctx
, src2
);
596 Builder
bld(ctx
->program
, ctx
->block
);
597 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
598 assert(dst
.size() == 1);
599 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
600 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
602 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
608 Builder
bld(ctx
->program
, ctx
->block
);
609 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
612 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
615 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
616 assert(src0
.size() == src1
.size());
618 aco_ptr
<Instruction
> vopc
;
619 if (src1
.type() == RegType::sgpr
) {
620 if (src0
.type() == RegType::vgpr
) {
621 /* to swap the operands, we might also have to change the opcode */
623 case aco_opcode::v_cmp_lt_f16
:
624 op
= aco_opcode::v_cmp_gt_f16
;
626 case aco_opcode::v_cmp_ge_f16
:
627 op
= aco_opcode::v_cmp_le_f16
;
629 case aco_opcode::v_cmp_lt_i16
:
630 op
= aco_opcode::v_cmp_gt_i16
;
632 case aco_opcode::v_cmp_ge_i16
:
633 op
= aco_opcode::v_cmp_le_i16
;
635 case aco_opcode::v_cmp_lt_u16
:
636 op
= aco_opcode::v_cmp_gt_u16
;
638 case aco_opcode::v_cmp_ge_u16
:
639 op
= aco_opcode::v_cmp_le_u16
;
641 case aco_opcode::v_cmp_lt_f32
:
642 op
= aco_opcode::v_cmp_gt_f32
;
644 case aco_opcode::v_cmp_ge_f32
:
645 op
= aco_opcode::v_cmp_le_f32
;
647 case aco_opcode::v_cmp_lt_i32
:
648 op
= aco_opcode::v_cmp_gt_i32
;
650 case aco_opcode::v_cmp_ge_i32
:
651 op
= aco_opcode::v_cmp_le_i32
;
653 case aco_opcode::v_cmp_lt_u32
:
654 op
= aco_opcode::v_cmp_gt_u32
;
656 case aco_opcode::v_cmp_ge_u32
:
657 op
= aco_opcode::v_cmp_le_u32
;
659 case aco_opcode::v_cmp_lt_f64
:
660 op
= aco_opcode::v_cmp_gt_f64
;
662 case aco_opcode::v_cmp_ge_f64
:
663 op
= aco_opcode::v_cmp_le_f64
;
665 case aco_opcode::v_cmp_lt_i64
:
666 op
= aco_opcode::v_cmp_gt_i64
;
668 case aco_opcode::v_cmp_ge_i64
:
669 op
= aco_opcode::v_cmp_le_i64
;
671 case aco_opcode::v_cmp_lt_u64
:
672 op
= aco_opcode::v_cmp_gt_u64
;
674 case aco_opcode::v_cmp_ge_u64
:
675 op
= aco_opcode::v_cmp_le_u64
;
677 default: /* eq and ne are commutative */
684 src1
= as_vgpr(ctx
, src1
);
688 Builder
bld(ctx
->program
, ctx
->block
);
689 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
692 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
694 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
695 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
696 Builder
bld(ctx
->program
, ctx
->block
);
698 assert(dst
.regClass() == bld
.lm
);
699 assert(src0
.type() == RegType::sgpr
);
700 assert(src1
.type() == RegType::sgpr
);
701 assert(src0
.regClass() == src1
.regClass());
703 /* Emit the SALU comparison instruction */
704 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
705 /* Turn the result into a per-lane bool */
706 bool_to_vector_condition(ctx
, cmp
, dst
);
709 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
710 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
712 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
713 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
714 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
715 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
717 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
718 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
719 aco_opcode op
= use_valu
? v_op
: s_op
;
720 assert(op
!= aco_opcode::num_opcodes
);
721 assert(dst
.regClass() == ctx
->program
->lane_mask
);
724 emit_vopc_instruction(ctx
, instr
, op
, dst
);
726 emit_sopc_instruction(ctx
, instr
, op
, dst
);
729 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
731 Builder
bld(ctx
->program
, ctx
->block
);
732 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
733 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
735 assert(dst
.regClass() == bld
.lm
);
736 assert(src0
.regClass() == bld
.lm
);
737 assert(src1
.regClass() == bld
.lm
);
739 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
742 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
744 Builder
bld(ctx
->program
, ctx
->block
);
745 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
746 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
747 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
749 assert(cond
.regClass() == bld
.lm
);
751 if (dst
.type() == RegType::vgpr
) {
752 aco_ptr
<Instruction
> bcsel
;
753 if (dst
.regClass() == v2b
) {
754 then
= as_vgpr(ctx
, then
);
755 els
= as_vgpr(ctx
, els
);
757 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
758 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
759 } else if (dst
.regClass() == v1
) {
760 then
= as_vgpr(ctx
, then
);
761 els
= as_vgpr(ctx
, els
);
763 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
764 } else if (dst
.regClass() == v2
) {
765 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
767 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
770 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
771 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
773 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
776 nir_print_instr(&instr
->instr
, stderr
);
777 fprintf(stderr
, "\n");
782 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
783 assert(dst
.regClass() == bld
.lm
);
784 assert(then
.regClass() == bld
.lm
);
785 assert(els
.regClass() == bld
.lm
);
788 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
789 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
790 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
791 assert(dst
.size() == then
.size());
792 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
793 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
795 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
796 nir_print_instr(&instr
->instr
, stderr
);
797 fprintf(stderr
, "\n");
802 /* divergent boolean bcsel
803 * this implements bcsel on bools: dst = s0 ? s1 : s2
804 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
805 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
807 if (cond
.id() != then
.id())
808 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
810 if (cond
.id() == els
.id())
811 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
813 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
814 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
817 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
818 aco_opcode op
, uint32_t undo
)
820 /* multiply by 16777216 to handle denormals */
821 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
822 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
823 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
824 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
825 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
827 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
829 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
832 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
834 if (ctx
->block
->fp_mode
.denorm32
== 0) {
835 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
839 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
842 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
844 if (ctx
->block
->fp_mode
.denorm32
== 0) {
845 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
849 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
852 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
854 if (ctx
->block
->fp_mode
.denorm32
== 0) {
855 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
859 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
862 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
864 if (ctx
->block
->fp_mode
.denorm32
== 0) {
865 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
869 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
872 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
874 if (ctx
->options
->chip_class
>= GFX7
)
875 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
877 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
878 /* TODO: create more efficient code! */
879 if (val
.type() == RegType::sgpr
)
880 val
= as_vgpr(ctx
, val
);
882 /* Split the input value. */
883 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
886 /* Extract the exponent and compute the unbiased value. */
887 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
889 /* Extract the fractional part. */
890 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
891 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
893 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
894 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
896 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
897 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
898 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
899 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
900 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
902 /* Get the sign bit. */
903 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
905 /* Decide the operation to apply depending on the unbiased exponent. */
906 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
907 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
908 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
909 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
910 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
911 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
913 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
916 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
918 if (ctx
->options
->chip_class
>= GFX7
)
919 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
921 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
922 Temp src0
= as_vgpr(ctx
, val
);
924 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
925 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
927 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
928 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
929 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
931 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
933 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
934 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
936 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
937 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
939 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
941 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
942 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
944 return add
->definitions
[0].getTemp();
947 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
949 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
950 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
952 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
955 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
956 return bld
.copy(Definition(dst
), src
);
957 else if (dst
.bytes() < src
.bytes())
958 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
962 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
965 } else if (src
.regClass() == s1
) {
967 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
969 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
971 assert(src_bits
!= 8 || src
.regClass() == v1b
);
972 assert(src_bits
!= 16 || src
.regClass() == v2b
);
973 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
974 sdwa
->operands
[0] = Operand(src
);
975 sdwa
->definitions
[0] = Definition(tmp
);
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
979 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
980 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
981 bld
.insert(std::move(sdwa
));
984 if (dst_bits
== 64) {
985 if (is_signed
&& dst
.regClass() == s2
) {
986 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
987 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
988 } else if (is_signed
&& dst
.regClass() == v2
) {
989 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
990 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
992 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
999 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1001 if (!instr
->dest
.dest
.is_ssa
) {
1002 fprintf(stderr
, "nir alu dst not in ssa: ");
1003 nir_print_instr(&instr
->instr
, stderr
);
1004 fprintf(stderr
, "\n");
1007 Builder
bld(ctx
->program
, ctx
->block
);
1008 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1013 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1014 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1015 for (unsigned i
= 0; i
< num
; ++i
)
1016 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1018 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1019 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1020 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1021 for (unsigned i
= 0; i
< num
; ++i
) {
1022 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1023 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1025 vec
->operands
[i
] = Operand
{elems
[i
]};
1027 vec
->definitions
[0] = Definition(dst
);
1028 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1029 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1031 // TODO: that is a bit suboptimal..
1032 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1033 for (unsigned i
= 0; i
< num
- 1; ++i
)
1034 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1035 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1036 for (unsigned i
= 0; i
< num
; ++i
) {
1037 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1038 if (bit
% 32 == 0) {
1039 elems
[bit
/ 32] = elems
[i
];
1041 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1042 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1043 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1046 if (dst
.size() == 1)
1047 bld
.copy(Definition(dst
), elems
[0]);
1049 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1054 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1055 aco_ptr
<Instruction
> mov
;
1056 if (dst
.type() == RegType::sgpr
) {
1057 if (src
.type() == RegType::vgpr
)
1058 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1059 else if (src
.regClass() == s1
)
1060 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1061 else if (src
.regClass() == s2
)
1062 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1064 unreachable("wrong src register class for nir_op_imov");
1065 } else if (dst
.regClass() == v1
) {
1066 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1067 } else if (dst
.regClass() == v2
) {
1068 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1070 nir_print_instr(&instr
->instr
, stderr
);
1071 unreachable("Should have been lowered to scalar.");
1076 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1077 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1078 assert(src
.regClass() == bld
.lm
);
1079 assert(dst
.regClass() == bld
.lm
);
1080 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1081 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1082 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1083 } else if (dst
.regClass() == v1
) {
1084 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1085 } else if (dst
.type() == RegType::sgpr
) {
1086 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1087 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1097 if (dst
.regClass() == v1
) {
1098 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1099 } else if (dst
.regClass() == s1
) {
1100 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1101 } else if (dst
.size() == 2) {
1102 Temp src0
= bld
.tmp(dst
.type(), 1);
1103 Temp src1
= bld
.tmp(dst
.type(), 1);
1104 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1106 if (dst
.regClass() == s2
) {
1107 Temp carry
= bld
.tmp(s1
);
1108 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1109 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1110 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1112 Temp lower
= bld
.tmp(v1
);
1113 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1114 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1115 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1118 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1119 nir_print_instr(&instr
->instr
, stderr
);
1120 fprintf(stderr
, "\n");
1125 if (dst
.regClass() == s1
) {
1126 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1127 } else if (dst
.regClass() == v1
) {
1128 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1129 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1131 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1132 nir_print_instr(&instr
->instr
, stderr
);
1133 fprintf(stderr
, "\n");
1137 case nir_op_isign
: {
1138 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1139 if (dst
.regClass() == s1
) {
1140 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1141 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1142 } else if (dst
.regClass() == s2
) {
1143 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1145 if (ctx
->program
->chip_class
>= GFX8
)
1146 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1148 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1149 /* SCC gets zero-extended to 64 bit */
1150 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1151 } else if (dst
.regClass() == v1
) {
1152 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1153 } else if (dst
.regClass() == v2
) {
1154 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1155 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1156 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1157 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1158 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1159 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (dst
.regClass() == v1
) {
1169 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1170 } else if (dst
.regClass() == s1
) {
1171 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1173 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1174 nir_print_instr(&instr
->instr
, stderr
);
1175 fprintf(stderr
, "\n");
1180 if (dst
.regClass() == v1
) {
1181 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1182 } else if (dst
.regClass() == s1
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1194 } else if (dst
.regClass() == s1
) {
1195 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1198 nir_print_instr(&instr
->instr
, stderr
);
1199 fprintf(stderr
, "\n");
1204 if (dst
.regClass() == v1
) {
1205 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1206 } else if (dst
.regClass() == s1
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1209 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1210 nir_print_instr(&instr
->instr
, stderr
);
1211 fprintf(stderr
, "\n");
1216 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1217 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1218 } else if (dst
.regClass() == v1
) {
1219 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1233 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1234 } else if (dst
.regClass() == v1
) {
1235 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1236 } else if (dst
.regClass() == s1
) {
1237 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1238 } else if (dst
.regClass() == s2
) {
1239 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1241 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1242 nir_print_instr(&instr
->instr
, stderr
);
1243 fprintf(stderr
, "\n");
1248 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1249 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1250 } else if (dst
.regClass() == v1
) {
1251 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1252 } else if (dst
.regClass() == s1
) {
1253 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1254 } else if (dst
.regClass() == s2
) {
1255 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1257 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1258 nir_print_instr(&instr
->instr
, stderr
);
1259 fprintf(stderr
, "\n");
1264 if (dst
.regClass() == v1
) {
1265 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1266 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1267 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1268 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1269 } else if (dst
.regClass() == v2
) {
1270 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1271 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1272 } else if (dst
.regClass() == s2
) {
1273 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1274 } else if (dst
.regClass() == s1
) {
1275 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1277 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1278 nir_print_instr(&instr
->instr
, stderr
);
1279 fprintf(stderr
, "\n");
1284 if (dst
.regClass() == v1
) {
1285 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1286 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1287 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1288 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1289 } else if (dst
.regClass() == v2
) {
1290 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1291 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1292 } else if (dst
.regClass() == s1
) {
1293 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1294 } else if (dst
.regClass() == s2
) {
1295 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1297 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1298 nir_print_instr(&instr
->instr
, stderr
);
1299 fprintf(stderr
, "\n");
1304 if (dst
.regClass() == v1
) {
1305 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1306 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1307 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1308 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1309 } else if (dst
.regClass() == v2
) {
1310 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1311 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1312 } else if (dst
.regClass() == s1
) {
1313 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1314 } else if (dst
.regClass() == s2
) {
1315 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1318 nir_print_instr(&instr
->instr
, stderr
);
1319 fprintf(stderr
, "\n");
1323 case nir_op_find_lsb
: {
1324 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1325 if (src
.regClass() == s1
) {
1326 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1327 } else if (src
.regClass() == v1
) {
1328 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1329 } else if (src
.regClass() == s2
) {
1330 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1332 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1333 nir_print_instr(&instr
->instr
, stderr
);
1334 fprintf(stderr
, "\n");
1338 case nir_op_ufind_msb
:
1339 case nir_op_ifind_msb
: {
1340 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1341 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1342 aco_opcode op
= src
.regClass() == s2
?
1343 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1344 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1345 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1347 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1348 Operand(src
.size() * 32u - 1u), msb_rev
);
1349 Temp msb
= sub
.def(0).getTemp();
1350 Temp carry
= sub
.def(1).getTemp();
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1353 } else if (src
.regClass() == v1
) {
1354 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1355 Temp msb_rev
= bld
.tmp(v1
);
1356 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1357 Temp msb
= bld
.tmp(v1
);
1358 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1359 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1361 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1362 nir_print_instr(&instr
->instr
, stderr
);
1363 fprintf(stderr
, "\n");
1367 case nir_op_bitfield_reverse
: {
1368 if (dst
.regClass() == s1
) {
1369 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1370 } else if (dst
.regClass() == v1
) {
1371 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1373 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1374 nir_print_instr(&instr
->instr
, stderr
);
1375 fprintf(stderr
, "\n");
1380 if (dst
.regClass() == s1
) {
1381 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1385 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1386 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1387 if (dst
.regClass() == v1
) {
1388 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1392 assert(src0
.size() == 2 && src1
.size() == 2);
1393 Temp src00
= bld
.tmp(src0
.type(), 1);
1394 Temp src01
= bld
.tmp(dst
.type(), 1);
1395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1396 Temp src10
= bld
.tmp(src1
.type(), 1);
1397 Temp src11
= bld
.tmp(dst
.type(), 1);
1398 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1400 if (dst
.regClass() == s2
) {
1401 Temp carry
= bld
.tmp(s1
);
1402 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1403 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1405 } else if (dst
.regClass() == v2
) {
1406 Temp dst0
= bld
.tmp(v1
);
1407 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1408 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1409 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1412 nir_print_instr(&instr
->instr
, stderr
);
1413 fprintf(stderr
, "\n");
1417 case nir_op_uadd_sat
: {
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == s1
) {
1421 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1422 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1424 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1425 } else if (dst
.regClass() == v1
) {
1426 if (ctx
->options
->chip_class
>= GFX9
) {
1427 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1428 add
->operands
[0] = Operand(src0
);
1429 add
->operands
[1] = Operand(src1
);
1430 add
->definitions
[0] = Definition(dst
);
1432 ctx
->block
->instructions
.emplace_back(std::move(add
));
1434 if (src1
.regClass() != v1
)
1435 std::swap(src0
, src1
);
1436 assert(src1
.regClass() == v1
);
1437 Temp tmp
= bld
.tmp(v1
);
1438 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1439 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_uadd_carry
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1455 if (dst
.regClass() == v1
) {
1456 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1457 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1461 Temp src00
= bld
.tmp(src0
.type(), 1);
1462 Temp src01
= bld
.tmp(dst
.type(), 1);
1463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1464 Temp src10
= bld
.tmp(src1
.type(), 1);
1465 Temp src11
= bld
.tmp(dst
.type(), 1);
1466 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1467 if (dst
.regClass() == s2
) {
1468 Temp carry
= bld
.tmp(s1
);
1469 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1470 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1471 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1472 } else if (dst
.regClass() == v2
) {
1473 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1474 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1475 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1476 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1478 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1479 nir_print_instr(&instr
->instr
, stderr
);
1480 fprintf(stderr
, "\n");
1485 if (dst
.regClass() == s1
) {
1486 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1490 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1491 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1492 if (dst
.regClass() == v1
) {
1493 bld
.vsub32(Definition(dst
), src0
, src1
);
1497 Temp src00
= bld
.tmp(src0
.type(), 1);
1498 Temp src01
= bld
.tmp(dst
.type(), 1);
1499 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1500 Temp src10
= bld
.tmp(src1
.type(), 1);
1501 Temp src11
= bld
.tmp(dst
.type(), 1);
1502 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1503 if (dst
.regClass() == s2
) {
1504 Temp carry
= bld
.tmp(s1
);
1505 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1506 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1507 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1508 } else if (dst
.regClass() == v2
) {
1509 Temp lower
= bld
.tmp(v1
);
1510 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1511 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1512 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1515 nir_print_instr(&instr
->instr
, stderr
);
1516 fprintf(stderr
, "\n");
1520 case nir_op_usub_borrow
: {
1521 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1522 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1523 if (dst
.regClass() == s1
) {
1524 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1526 } else if (dst
.regClass() == v1
) {
1527 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1528 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1532 Temp src00
= bld
.tmp(src0
.type(), 1);
1533 Temp src01
= bld
.tmp(dst
.type(), 1);
1534 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1535 Temp src10
= bld
.tmp(src1
.type(), 1);
1536 Temp src11
= bld
.tmp(dst
.type(), 1);
1537 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1538 if (dst
.regClass() == s2
) {
1539 Temp borrow
= bld
.tmp(s1
);
1540 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1541 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1543 } else if (dst
.regClass() == v2
) {
1544 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1545 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1546 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1547 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1549 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1550 nir_print_instr(&instr
->instr
, stderr
);
1551 fprintf(stderr
, "\n");
1556 if (dst
.regClass() == v1
) {
1557 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1558 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1559 } else if (dst
.regClass() == s1
) {
1560 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1563 nir_print_instr(&instr
->instr
, stderr
);
1564 fprintf(stderr
, "\n");
1568 case nir_op_umul_high
: {
1569 if (dst
.regClass() == v1
) {
1570 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1571 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1572 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1573 } else if (dst
.regClass() == s1
) {
1574 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1575 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1576 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1578 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1579 nir_print_instr(&instr
->instr
, stderr
);
1580 fprintf(stderr
, "\n");
1584 case nir_op_imul_high
: {
1585 if (dst
.regClass() == v1
) {
1586 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1587 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1588 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1589 } else if (dst
.regClass() == s1
) {
1590 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1591 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1592 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1594 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1595 nir_print_instr(&instr
->instr
, stderr
);
1596 fprintf(stderr
, "\n");
1601 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1602 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1603 if (dst
.regClass() == v2b
) {
1604 Temp tmp
= bld
.tmp(v1
);
1605 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1607 } else if (dst
.regClass() == v1
) {
1608 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1609 } else if (dst
.regClass() == v2
) {
1610 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1612 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1613 nir_print_instr(&instr
->instr
, stderr
);
1614 fprintf(stderr
, "\n");
1619 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1620 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1621 if (dst
.regClass() == v2b
) {
1622 Temp tmp
= bld
.tmp(v1
);
1623 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1624 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1625 } else if (dst
.regClass() == v1
) {
1626 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1627 } else if (dst
.regClass() == v2
) {
1628 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1630 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1631 nir_print_instr(&instr
->instr
, stderr
);
1632 fprintf(stderr
, "\n");
1637 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1638 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1639 if (dst
.regClass() == v2b
) {
1640 Temp tmp
= bld
.tmp(v1
);
1641 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1642 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1644 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1645 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1646 } else if (dst
.regClass() == v1
) {
1647 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1650 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1651 } else if (dst
.regClass() == v2
) {
1652 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1653 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1654 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1664 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1665 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1666 if (dst
.regClass() == v2b
) {
1667 // TODO: check fp_mode.must_flush_denorms16_64
1668 Temp tmp
= bld
.tmp(v1
);
1669 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1670 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1671 } else if (dst
.regClass() == v1
) {
1672 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1673 } else if (dst
.regClass() == v2
) {
1674 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1675 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1676 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1678 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1681 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1682 nir_print_instr(&instr
->instr
, stderr
);
1683 fprintf(stderr
, "\n");
1688 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1689 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1690 if (dst
.regClass() == v2b
) {
1691 // TODO: check fp_mode.must_flush_denorms16_64
1692 Temp tmp
= bld
.tmp(v1
);
1693 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1694 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1695 } else if (dst
.regClass() == v1
) {
1696 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1697 } else if (dst
.regClass() == v2
) {
1698 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1699 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1700 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1702 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1705 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1706 nir_print_instr(&instr
->instr
, stderr
);
1707 fprintf(stderr
, "\n");
1711 case nir_op_fmax3
: {
1712 if (dst
.regClass() == v2b
) {
1713 Temp tmp
= bld
.tmp(v1
);
1714 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1716 } else if (dst
.regClass() == v1
) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_fmin3
: {
1726 if (dst
.regClass() == v2b
) {
1727 Temp tmp
= bld
.tmp(v1
);
1728 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1729 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1730 } else if (dst
.regClass() == v1
) {
1731 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1733 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1734 nir_print_instr(&instr
->instr
, stderr
);
1735 fprintf(stderr
, "\n");
1739 case nir_op_fmed3
: {
1740 if (dst
.regClass() == v2b
) {
1741 Temp tmp
= bld
.tmp(v1
);
1742 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1743 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1744 } else if (dst
.regClass() == v1
) {
1745 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1748 nir_print_instr(&instr
->instr
, stderr
);
1749 fprintf(stderr
, "\n");
1753 case nir_op_umax3
: {
1754 if (dst
.size() == 1) {
1755 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1758 nir_print_instr(&instr
->instr
, stderr
);
1759 fprintf(stderr
, "\n");
1763 case nir_op_umin3
: {
1764 if (dst
.size() == 1) {
1765 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1768 nir_print_instr(&instr
->instr
, stderr
);
1769 fprintf(stderr
, "\n");
1773 case nir_op_umed3
: {
1774 if (dst
.size() == 1) {
1775 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1777 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1778 nir_print_instr(&instr
->instr
, stderr
);
1779 fprintf(stderr
, "\n");
1783 case nir_op_imax3
: {
1784 if (dst
.size() == 1) {
1785 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1793 case nir_op_imin3
: {
1794 if (dst
.size() == 1) {
1795 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1797 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1798 nir_print_instr(&instr
->instr
, stderr
);
1799 fprintf(stderr
, "\n");
1803 case nir_op_imed3
: {
1804 if (dst
.size() == 1) {
1805 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1807 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1808 nir_print_instr(&instr
->instr
, stderr
);
1809 fprintf(stderr
, "\n");
1813 case nir_op_cube_face_coord
: {
1814 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1815 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1816 emit_extract_vector(ctx
, in
, 1, v1
),
1817 emit_extract_vector(ctx
, in
, 2, v1
) };
1818 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1819 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1820 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1821 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1822 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1823 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1824 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1827 case nir_op_cube_face_index
: {
1828 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1829 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1830 emit_extract_vector(ctx
, in
, 1, v1
),
1831 emit_extract_vector(ctx
, in
, 2, v1
) };
1832 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1835 case nir_op_bcsel
: {
1836 emit_bcsel(ctx
, instr
, dst
);
1840 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1841 if (dst
.regClass() == v2b
) {
1842 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1844 } else if (dst
.regClass() == v1
) {
1845 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1846 } else if (dst
.regClass() == v2
) {
1847 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1849 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1850 nir_print_instr(&instr
->instr
, stderr
);
1851 fprintf(stderr
, "\n");
1856 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1857 if (dst
.regClass() == v2b
) {
1858 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1859 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1860 } else if (dst
.regClass() == v1
) {
1861 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1862 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1863 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1864 } else if (dst
.regClass() == v2
) {
1865 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1866 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1867 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1868 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1869 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1870 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1873 nir_print_instr(&instr
->instr
, stderr
);
1874 fprintf(stderr
, "\n");
1879 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1880 if (dst
.regClass() == v2b
) {
1881 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1883 } else if (dst
.regClass() == v1
) {
1884 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1885 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1886 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1887 } else if (dst
.regClass() == v2
) {
1888 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1889 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1890 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1892 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1893 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1895 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1896 nir_print_instr(&instr
->instr
, stderr
);
1897 fprintf(stderr
, "\n");
1902 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1903 if (dst
.regClass() == v2b
) {
1904 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1905 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1906 } else if (dst
.regClass() == v1
) {
1907 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1908 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1909 // TODO: confirm that this holds under any circumstances
1910 } else if (dst
.regClass() == v2
) {
1911 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1912 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1915 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1916 nir_print_instr(&instr
->instr
, stderr
);
1917 fprintf(stderr
, "\n");
1921 case nir_op_flog2
: {
1922 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1923 if (dst
.regClass() == v2b
) {
1924 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1925 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1926 } else if (dst
.regClass() == v1
) {
1927 emit_log2(ctx
, bld
, Definition(dst
), src
);
1929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1930 nir_print_instr(&instr
->instr
, stderr
);
1931 fprintf(stderr
, "\n");
1936 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1937 if (dst
.regClass() == v2b
) {
1938 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1939 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1940 } else if (dst
.regClass() == v1
) {
1941 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1942 } else if (dst
.regClass() == v2
) {
1943 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1945 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1946 nir_print_instr(&instr
->instr
, stderr
);
1947 fprintf(stderr
, "\n");
1951 case nir_op_fexp2
: {
1952 if (dst
.regClass() == v2b
) {
1953 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1954 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1956 } else if (dst
.regClass() == v1
) {
1957 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_fsqrt
: {
1966 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1972 } else if (dst
.regClass() == v2
) {
1973 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1975 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1976 nir_print_instr(&instr
->instr
, stderr
);
1977 fprintf(stderr
, "\n");
1981 case nir_op_ffract
: {
1982 if (dst
.regClass() == v2b
) {
1983 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1984 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1985 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1986 } else if (dst
.regClass() == v1
) {
1987 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1988 } else if (dst
.regClass() == v2
) {
1989 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1991 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1992 nir_print_instr(&instr
->instr
, stderr
);
1993 fprintf(stderr
, "\n");
1997 case nir_op_ffloor
: {
1998 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1999 if (dst
.regClass() == v2b
) {
2000 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
2001 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2002 } else if (dst
.regClass() == v1
) {
2003 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2004 } else if (dst
.regClass() == v2
) {
2005 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2007 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2008 nir_print_instr(&instr
->instr
, stderr
);
2009 fprintf(stderr
, "\n");
2013 case nir_op_fceil
: {
2014 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2015 if (dst
.regClass() == v2b
) {
2016 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
2017 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2018 } else if (dst
.regClass() == v1
) {
2019 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2020 } else if (dst
.regClass() == v2
) {
2021 if (ctx
->options
->chip_class
>= GFX7
) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2024 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2025 /* trunc = trunc(src0)
2026 * if (src0 > 0.0 && src0 != trunc)
2029 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2030 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2031 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2032 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2033 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2034 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2035 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2039 nir_print_instr(&instr
->instr
, stderr
);
2040 fprintf(stderr
, "\n");
2044 case nir_op_ftrunc
: {
2045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2046 if (dst
.regClass() == v2b
) {
2047 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2048 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2049 } else if (dst
.regClass() == v1
) {
2050 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2051 } else if (dst
.regClass() == v2
) {
2052 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2054 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2055 nir_print_instr(&instr
->instr
, stderr
);
2056 fprintf(stderr
, "\n");
2060 case nir_op_fround_even
: {
2061 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2062 if (dst
.regClass() == v2b
) {
2063 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2064 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2065 } else if (dst
.regClass() == v1
) {
2066 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2067 } else if (dst
.regClass() == v2
) {
2068 if (ctx
->options
->chip_class
>= GFX7
) {
2069 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2071 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2072 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2073 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2075 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2076 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2077 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2078 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2079 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2080 tmp
= sub
->definitions
[0].getTemp();
2082 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2083 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2084 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2085 Temp cond
= vop3
->definitions
[0].getTemp();
2087 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2088 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2089 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2090 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2092 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2095 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2096 nir_print_instr(&instr
->instr
, stderr
);
2097 fprintf(stderr
, "\n");
2103 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2104 aco_ptr
<Instruction
> norm
;
2105 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2106 if (dst
.regClass() == v2b
) {
2107 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2108 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2109 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2110 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2111 } else if (dst
.regClass() == v1
) {
2112 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2114 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2115 if (ctx
->options
->chip_class
< GFX9
)
2116 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2118 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2119 bld
.vop1(opcode
, Definition(dst
), tmp
);
2121 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2122 nir_print_instr(&instr
->instr
, stderr
);
2123 fprintf(stderr
, "\n");
2127 case nir_op_ldexp
: {
2128 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2129 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2130 if (dst
.regClass() == v2b
) {
2131 Temp tmp
= bld
.tmp(v1
);
2132 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2133 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2134 } else if (dst
.regClass() == v1
) {
2135 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2136 } else if (dst
.regClass() == v2
) {
2137 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2139 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2140 nir_print_instr(&instr
->instr
, stderr
);
2141 fprintf(stderr
, "\n");
2145 case nir_op_frexp_sig
: {
2146 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2147 if (dst
.regClass() == v2b
) {
2148 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2149 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2150 } else if (dst
.regClass() == v1
) {
2151 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2152 } else if (dst
.regClass() == v2
) {
2153 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2161 case nir_op_frexp_exp
: {
2162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2163 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2164 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2165 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2166 convert_int(bld
, tmp
, 8, 32, true, dst
);
2167 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2168 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2169 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2170 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2172 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2173 nir_print_instr(&instr
->instr
, stderr
);
2174 fprintf(stderr
, "\n");
2178 case nir_op_fsign
: {
2179 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2180 if (dst
.regClass() == v2b
) {
2181 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2182 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2183 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2184 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2185 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2186 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2187 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2188 } else if (dst
.regClass() == v1
) {
2189 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2190 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2191 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2193 } else if (dst
.regClass() == v2
) {
2194 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2195 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2196 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2198 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2199 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2200 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2202 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2204 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2205 nir_print_instr(&instr
->instr
, stderr
);
2206 fprintf(stderr
, "\n");
2211 case nir_op_f2f16_rtne
: {
2212 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2213 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2214 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2215 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2219 case nir_op_f2f16_rtz
: {
2220 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2221 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2222 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2223 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2224 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2227 case nir_op_f2f32
: {
2228 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2229 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2230 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2231 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2233 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2234 nir_print_instr(&instr
->instr
, stderr
);
2235 fprintf(stderr
, "\n");
2239 case nir_op_f2f64
: {
2240 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2241 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2242 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2243 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2246 case nir_op_i2f16
: {
2247 assert(dst
.regClass() == v2b
);
2248 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2249 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2250 src
= convert_int(bld
, src
, 8, 16, true);
2251 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
), src
);
2252 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2255 case nir_op_i2f32
: {
2256 assert(dst
.size() == 1);
2257 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2258 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2259 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2260 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2263 case nir_op_i2f64
: {
2264 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2265 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2266 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2267 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2268 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2269 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2270 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2271 RegClass rc
= RegClass(src
.type(), 1);
2272 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2273 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2274 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2275 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2276 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2277 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2280 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2281 nir_print_instr(&instr
->instr
, stderr
);
2282 fprintf(stderr
, "\n");
2286 case nir_op_u2f16
: {
2287 assert(dst
.regClass() == v2b
);
2288 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2289 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2290 src
= convert_int(bld
, src
, 8, 16, false);
2291 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
), src
);
2292 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2295 case nir_op_u2f32
: {
2296 assert(dst
.size() == 1);
2297 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2298 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2299 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2300 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2302 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2303 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2304 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2308 case nir_op_u2f64
: {
2309 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2310 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2311 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2312 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2313 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2314 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2315 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2316 RegClass rc
= RegClass(src
.type(), 1);
2317 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2318 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2319 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2320 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2321 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2322 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2324 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2325 nir_print_instr(&instr
->instr
, stderr
);
2326 fprintf(stderr
, "\n");
2331 case nir_op_f2i16
: {
2332 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2333 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2334 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2335 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2336 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2338 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2340 if (dst
.type() == RegType::vgpr
)
2341 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2343 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2347 case nir_op_f2u16
: {
2348 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2349 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2350 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2351 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2352 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2354 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2356 if (dst
.type() == RegType::vgpr
)
2357 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2359 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2362 case nir_op_f2i32
: {
2363 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2364 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2365 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2366 if (dst
.type() == RegType::vgpr
) {
2367 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2369 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2370 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2372 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2373 if (dst
.type() == RegType::vgpr
)
2374 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2376 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2377 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2379 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2380 if (dst
.type() == RegType::vgpr
)
2381 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2383 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2384 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2387 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2388 nir_print_instr(&instr
->instr
, stderr
);
2389 fprintf(stderr
, "\n");
2393 case nir_op_f2u32
: {
2394 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2395 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2396 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2397 if (dst
.type() == RegType::vgpr
) {
2398 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2400 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2401 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2403 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2404 if (dst
.type() == RegType::vgpr
)
2405 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2407 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2408 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2410 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2411 if (dst
.type() == RegType::vgpr
)
2412 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2414 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2415 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2418 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2419 nir_print_instr(&instr
->instr
, stderr
);
2420 fprintf(stderr
, "\n");
2424 case nir_op_f2i64
: {
2425 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2426 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2427 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2429 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2430 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2431 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2432 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2433 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2434 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2435 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2436 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2437 Temp new_exponent
= bld
.tmp(v1
);
2438 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2439 if (ctx
->program
->chip_class
>= GFX8
)
2440 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2442 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2443 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2444 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2445 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2446 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2447 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2448 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2449 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2450 Temp new_lower
= bld
.tmp(v1
);
2451 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2452 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2453 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2455 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2456 if (src
.type() == RegType::vgpr
)
2457 src
= bld
.as_uniform(src
);
2458 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2459 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2460 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2461 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2462 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2463 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2464 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2465 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2466 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2467 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2468 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2469 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2470 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2471 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2472 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2473 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2474 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2475 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2476 Temp borrow
= bld
.tmp(s1
);
2477 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2478 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2479 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2481 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2482 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2483 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2484 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2485 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2486 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2487 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2488 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2489 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2490 if (dst
.type() == RegType::sgpr
) {
2491 lower
= bld
.as_uniform(lower
);
2492 upper
= bld
.as_uniform(upper
);
2494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2497 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2498 nir_print_instr(&instr
->instr
, stderr
);
2499 fprintf(stderr
, "\n");
2503 case nir_op_f2u64
: {
2504 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2505 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2506 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2508 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2509 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2510 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2511 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2512 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2513 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2514 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2515 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2516 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2517 Temp new_exponent
= bld
.tmp(v1
);
2518 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2519 if (ctx
->program
->chip_class
>= GFX8
)
2520 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2522 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2523 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2524 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2525 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2526 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2527 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2528 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2529 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2531 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2532 if (src
.type() == RegType::vgpr
)
2533 src
= bld
.as_uniform(src
);
2534 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2535 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2536 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2537 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2538 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2539 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2540 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2541 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2542 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2543 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2544 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2545 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2546 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2547 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2548 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2549 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2550 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2551 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2553 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2554 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2555 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2556 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2557 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2558 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2559 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2560 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2561 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2562 if (dst
.type() == RegType::sgpr
) {
2563 lower
= bld
.as_uniform(lower
);
2564 upper
= bld
.as_uniform(upper
);
2566 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2569 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2570 nir_print_instr(&instr
->instr
, stderr
);
2571 fprintf(stderr
, "\n");
2575 case nir_op_b2f16
: {
2576 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2577 assert(src
.regClass() == bld
.lm
);
2579 if (dst
.regClass() == s1
) {
2580 src
= bool_to_scalar_condition(ctx
, src
);
2581 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2582 } else if (dst
.regClass() == v2b
) {
2583 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2584 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2585 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2587 unreachable("Wrong destination register class for nir_op_b2f16.");
2591 case nir_op_b2f32
: {
2592 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2593 assert(src
.regClass() == bld
.lm
);
2595 if (dst
.regClass() == s1
) {
2596 src
= bool_to_scalar_condition(ctx
, src
);
2597 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2598 } else if (dst
.regClass() == v1
) {
2599 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2601 unreachable("Wrong destination register class for nir_op_b2f32.");
2605 case nir_op_b2f64
: {
2606 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2607 assert(src
.regClass() == bld
.lm
);
2609 if (dst
.regClass() == s2
) {
2610 src
= bool_to_scalar_condition(ctx
, src
);
2611 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2612 } else if (dst
.regClass() == v2
) {
2613 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2614 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2615 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2617 unreachable("Wrong destination register class for nir_op_b2f64.");
2624 case nir_op_i2i64
: {
2625 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2626 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2632 case nir_op_u2u64
: {
2633 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2634 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2638 case nir_op_b2i32
: {
2639 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2640 assert(src
.regClass() == bld
.lm
);
2642 if (dst
.regClass() == s1
) {
2643 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2644 bool_to_scalar_condition(ctx
, src
, dst
);
2645 } else if (dst
.regClass() == v1
) {
2646 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2648 unreachable("Invalid register class for b2i32");
2654 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2655 assert(dst
.regClass() == bld
.lm
);
2657 if (src
.type() == RegType::vgpr
) {
2658 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2659 assert(dst
.regClass() == bld
.lm
);
2660 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2661 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2663 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2665 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2666 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2668 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2669 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2671 bool_to_vector_condition(ctx
, tmp
, dst
);
2675 case nir_op_pack_64_2x32_split
: {
2676 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2677 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2679 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2682 case nir_op_unpack_64_2x32_split_x
:
2683 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2685 case nir_op_unpack_64_2x32_split_y
:
2686 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2688 case nir_op_unpack_32_2x16_split_x
:
2689 if (dst
.type() == RegType::vgpr
) {
2690 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2692 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2695 case nir_op_unpack_32_2x16_split_y
:
2696 if (dst
.type() == RegType::vgpr
) {
2697 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2699 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2702 case nir_op_pack_32_2x16_split
: {
2703 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2704 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2705 if (dst
.regClass() == v1
) {
2706 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2707 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2708 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2710 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2711 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2712 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2716 case nir_op_pack_half_2x16
: {
2717 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2719 if (dst
.regClass() == v1
) {
2720 Temp src0
= bld
.tmp(v1
);
2721 Temp src1
= bld
.tmp(v1
);
2722 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2723 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2724 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2726 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2727 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2728 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2730 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2731 nir_print_instr(&instr
->instr
, stderr
);
2732 fprintf(stderr
, "\n");
2736 case nir_op_unpack_half_2x16_split_x
: {
2737 if (dst
.regClass() == v1
) {
2738 Builder
bld(ctx
->program
, ctx
->block
);
2739 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2742 nir_print_instr(&instr
->instr
, stderr
);
2743 fprintf(stderr
, "\n");
2747 case nir_op_unpack_half_2x16_split_y
: {
2748 if (dst
.regClass() == v1
) {
2749 Builder
bld(ctx
->program
, ctx
->block
);
2750 /* TODO: use SDWA here */
2751 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2752 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2754 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2755 nir_print_instr(&instr
->instr
, stderr
);
2756 fprintf(stderr
, "\n");
2760 case nir_op_fquantize2f16
: {
2761 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2762 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2765 if (ctx
->program
->chip_class
>= GFX8
) {
2766 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2767 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2768 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2770 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2771 * so compare the result and flush to 0 if it's smaller.
2773 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2774 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2775 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2776 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2777 cmp_res
= vop3
->definitions
[0].getTemp();
2780 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2781 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2782 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2784 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2789 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2790 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2792 if (dst
.regClass() == s1
) {
2793 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2794 } else if (dst
.regClass() == v1
) {
2795 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2797 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2798 nir_print_instr(&instr
->instr
, stderr
);
2799 fprintf(stderr
, "\n");
2803 case nir_op_bitfield_select
: {
2804 /* (mask & insert) | (~mask & base) */
2805 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2806 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2807 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2809 /* dst = (insert & bitmask) | (base & ~bitmask) */
2810 if (dst
.regClass() == s1
) {
2811 aco_ptr
<Instruction
> sop2
;
2812 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2813 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2815 if (const_insert
&& const_bitmask
) {
2816 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2818 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2819 lhs
= Operand(insert
);
2823 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2824 if (const_base
&& const_bitmask
) {
2825 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2827 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2828 rhs
= Operand(base
);
2831 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2833 } else if (dst
.regClass() == v1
) {
2834 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2835 base
= as_vgpr(ctx
, base
);
2836 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2837 insert
= as_vgpr(ctx
, insert
);
2839 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2843 nir_print_instr(&instr
->instr
, stderr
);
2844 fprintf(stderr
, "\n");
2850 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2851 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2852 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2854 if (dst
.type() == RegType::sgpr
) {
2856 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2857 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2858 if (const_offset
&& const_bits
) {
2859 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2860 extract
= Operand(const_extract
);
2864 width
= Operand(const_bits
->u32
<< 16);
2866 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2868 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2872 if (dst
.regClass() == s1
) {
2873 if (instr
->op
== nir_op_ubfe
)
2874 opcode
= aco_opcode::s_bfe_u32
;
2876 opcode
= aco_opcode::s_bfe_i32
;
2877 } else if (dst
.regClass() == s2
) {
2878 if (instr
->op
== nir_op_ubfe
)
2879 opcode
= aco_opcode::s_bfe_u64
;
2881 opcode
= aco_opcode::s_bfe_i64
;
2883 unreachable("Unsupported BFE bit size");
2886 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2890 if (dst
.regClass() == v1
) {
2891 if (instr
->op
== nir_op_ubfe
)
2892 opcode
= aco_opcode::v_bfe_u32
;
2894 opcode
= aco_opcode::v_bfe_i32
;
2896 unreachable("Unsupported BFE bit size");
2899 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2903 case nir_op_bit_count
: {
2904 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2905 if (src
.regClass() == s1
) {
2906 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2907 } else if (src
.regClass() == v1
) {
2908 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2909 } else if (src
.regClass() == v2
) {
2910 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2911 emit_extract_vector(ctx
, src
, 1, v1
),
2912 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2913 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2914 } else if (src
.regClass() == s2
) {
2915 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2917 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2918 nir_print_instr(&instr
->instr
, stderr
);
2919 fprintf(stderr
, "\n");
2924 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2928 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2932 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2936 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2940 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2948 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2949 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2951 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2952 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2956 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2957 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2959 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2960 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2964 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2968 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2973 case nir_op_fddx_fine
:
2974 case nir_op_fddy_fine
:
2975 case nir_op_fddx_coarse
:
2976 case nir_op_fddy_coarse
: {
2977 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2978 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2979 if (instr
->op
== nir_op_fddx_fine
) {
2980 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2981 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2982 } else if (instr
->op
== nir_op_fddy_fine
) {
2983 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2984 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2986 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2987 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2988 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2990 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2994 if (ctx
->program
->chip_class
>= GFX8
) {
2995 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2996 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2998 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2999 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3000 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3002 emit_wqm(ctx
, tmp
, dst
, true);
3006 fprintf(stderr
, "Unknown NIR ALU instr: ");
3007 nir_print_instr(&instr
->instr
, stderr
);
3008 fprintf(stderr
, "\n");
3012 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3014 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3016 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3017 // which get truncated the lsb if double and msb if int
3018 // for now, we only use s_mov_b64 with 64bit inline constants
3019 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3020 assert(dst
.type() == RegType::sgpr
);
3022 Builder
bld(ctx
->program
, ctx
->block
);
3024 if (instr
->def
.bit_size
== 1) {
3025 assert(dst
.regClass() == bld
.lm
);
3026 int val
= instr
->value
[0].b
? -1 : 0;
3027 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3028 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3029 } else if (instr
->def
.bit_size
== 8) {
3030 /* ensure that the value is correctly represented in the low byte of the register */
3031 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3032 } else if (instr
->def
.bit_size
== 16) {
3033 /* ensure that the value is correctly represented in the low half of the register */
3034 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3035 } else if (dst
.size() == 1) {
3036 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3038 assert(dst
.size() != 1);
3039 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3040 if (instr
->def
.bit_size
== 64)
3041 for (unsigned i
= 0; i
< dst
.size(); i
++)
3042 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3044 for (unsigned i
= 0; i
< dst
.size(); i
++)
3045 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3047 vec
->definitions
[0] = Definition(dst
);
3048 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3052 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3054 uint32_t new_mask
= 0;
3055 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3056 if (mask
& (1u << i
))
3057 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3061 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3063 Builder
bld(ctx
->program
, ctx
->block
);
3064 if (offset
.isTemp()) {
3065 Temp tmp
[3] = {vec
, vec
, vec
};
3067 if (vec
.size() == 3) {
3068 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3069 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3070 } else if (vec
.size() == 2) {
3071 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3072 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3074 for (unsigned i
= 0; i
< dst
.size(); i
++)
3075 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3078 if (dst
.size() == 2)
3079 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3081 offset
= Operand(0u);
3084 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3085 bld
.copy(Definition(dst
), vec
);
3087 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3090 struct LoadEmitInfo
{
3093 unsigned num_components
;
3094 unsigned component_size
;
3095 Temp resource
= Temp(0, s1
);
3096 unsigned component_stride
= 0;
3097 unsigned const_offset
= 0;
3098 unsigned align_mul
= 0;
3099 unsigned align_offset
= 0;
3102 unsigned swizzle_component_size
= 0;
3103 barrier_interaction barrier
= barrier_none
;
3104 bool can_reorder
= true;
3105 Temp soffset
= Temp(0, s1
);
3108 using LoadCallback
= Temp(*)(
3109 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3110 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3112 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3113 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3115 unsigned load_size
= info
->num_components
* info
->component_size
;
3116 unsigned component_size
= info
->component_size
;
3118 unsigned num_vals
= 0;
3119 Temp vals
[info
->dst
.bytes()];
3121 unsigned const_offset
= info
->const_offset
;
3123 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3124 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3126 unsigned bytes_read
= 0;
3127 while (bytes_read
< load_size
) {
3128 unsigned bytes_needed
= load_size
- bytes_read
;
3130 /* add buffer for unaligned loads */
3131 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3134 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3135 if (info
->component_stride
) {
3136 assert(supports_8bit_16bit_loads
&& "unimplemented");
3140 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3141 bytes_needed
= align(bytes_needed
, 4);
3148 if (info
->swizzle_component_size
)
3149 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3150 if (info
->component_stride
)
3151 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3153 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3155 /* reduce constant offset */
3156 Operand offset
= info
->offset
;
3157 unsigned reduced_const_offset
= const_offset
;
3158 bool remove_const_offset_completely
= need_to_align_offset
;
3159 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3160 unsigned to_add
= const_offset
;
3161 if (remove_const_offset_completely
) {
3162 reduced_const_offset
= 0;
3164 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3165 reduced_const_offset
%= max_const_offset_plus_one
;
3167 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3168 if (offset
.isConstant()) {
3169 offset
= Operand(offset
.constantValue() + to_add
);
3170 } else if (offset_tmp
.regClass() == s1
) {
3171 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3172 offset_tmp
, Operand(to_add
));
3173 } else if (offset_tmp
.regClass() == v1
) {
3174 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3176 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3177 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3178 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3180 if (offset_tmp
.regClass() == s2
) {
3181 Temp carry
= bld
.tmp(s1
);
3182 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3183 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3184 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3186 Temp new_lo
= bld
.tmp(v1
);
3187 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3188 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3189 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3194 /* align offset down if needed */
3195 Operand aligned_offset
= offset
;
3196 if (need_to_align_offset
) {
3197 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3198 if (offset
.isConstant()) {
3199 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3200 } else if (offset_tmp
.regClass() == s1
) {
3201 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3202 } else if (offset_tmp
.regClass() == s2
) {
3203 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3204 } else if (offset_tmp
.regClass() == v1
) {
3205 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3206 } else if (offset_tmp
.regClass() == v2
) {
3207 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3208 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3209 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3210 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3213 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3214 bld
.copy(bld
.def(s1
), aligned_offset
);
3216 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3217 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3218 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3220 /* shift result right if needed */
3222 Operand
align((uint32_t)byte_align
);
3223 if (byte_align
== -1) {
3224 if (offset
.isConstant())
3225 align
= Operand(offset
.constantValue() % 4u);
3226 else if (offset
.size() == 2)
3227 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3232 if (align
.isTemp() || align
.constantValue()) {
3233 assert(val
.bytes() >= load_size
&& "unimplemented");
3234 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3235 if (val
.type() == RegType::sgpr
)
3236 byte_align_scalar(ctx
, val
, align
, new_val
);
3238 byte_align_vector(ctx
, val
, align
, new_val
);
3243 /* add result to list and advance */
3244 if (info
->component_stride
) {
3245 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3246 const_offset
+= info
->component_stride
;
3247 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3249 const_offset
+= val
.bytes();
3250 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3252 bytes_read
+= val
.bytes();
3253 vals
[num_vals
++] = val
;
3256 /* the callback wrote directly to dst */
3257 if (vals
[0] == info
->dst
) {
3258 assert(num_vals
== 1);
3259 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3263 /* create array of components */
3264 unsigned components_split
= 0;
3265 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3266 bool has_vgprs
= false;
3267 for (unsigned i
= 0; i
< num_vals
;) {
3269 unsigned num_tmps
= 0;
3270 unsigned tmp_size
= 0;
3271 RegType reg_type
= RegType::sgpr
;
3272 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3273 if (vals
[i
].type() == RegType::vgpr
)
3274 reg_type
= RegType::vgpr
;
3275 tmp_size
+= vals
[i
].bytes();
3276 tmp
[num_tmps
++] = vals
[i
++];
3279 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3280 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3281 for (unsigned i
= 0; i
< num_vals
; i
++)
3282 vec
->operands
[i
] = Operand(tmp
[i
]);
3283 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3284 vec
->definitions
[0] = Definition(tmp
[0]);
3285 bld
.insert(std::move(vec
));
3288 if (tmp
[0].bytes() % component_size
) {
3290 assert(i
== num_vals
);
3291 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3292 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3295 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3297 unsigned start
= components_split
;
3299 if (tmp_size
== elem_rc
.bytes()) {
3300 allocated_vec
[components_split
++] = tmp
[0];
3302 assert(tmp_size
% elem_rc
.bytes() == 0);
3303 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3304 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3305 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3306 Temp component
= bld
.tmp(elem_rc
);
3307 allocated_vec
[components_split
++] = component
;
3308 split
->definitions
[i
] = Definition(component
);
3310 split
->operands
[0] = Operand(tmp
[0]);
3311 bld
.insert(std::move(split
));
3314 /* try to p_as_uniform early so we can create more optimizable code and
3315 * also update allocated_vec */
3316 for (unsigned j
= start
; j
< components_split
; j
++) {
3317 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3318 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3319 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3323 /* concatenate components and p_as_uniform() result if needed */
3324 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3325 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3327 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3329 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3330 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3331 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3332 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3334 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3335 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3336 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3337 vec
->definitions
[0] = Definition(tmp
);
3338 bld
.insert(std::move(vec
));
3339 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3341 vec
->definitions
[0] = Definition(info
->dst
);
3342 bld
.insert(std::move(vec
));
3346 Operand
load_lds_size_m0(Builder
& bld
)
3348 /* TODO: m0 does not need to be initialized on GFX9+ */
3349 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3352 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3353 Temp offset
, unsigned bytes_needed
,
3354 unsigned align
, unsigned const_offset
,
3357 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3359 Operand m
= load_lds_size_m0(bld
);
3361 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3362 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3367 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3368 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3370 op
= aco_opcode::ds_read_b128
;
3371 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3374 op
= aco_opcode::ds_read2_b64
;
3375 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3377 op
= aco_opcode::ds_read_b96
;
3378 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3380 op
= aco_opcode::ds_read_b64
;
3381 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3384 op
= aco_opcode::ds_read2_b32
;
3385 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3387 op
= aco_opcode::ds_read_b32
;
3388 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3390 op
= aco_opcode::ds_read_u16
;
3393 op
= aco_opcode::ds_read_u8
;
3396 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3397 if (const_offset
>= max_offset_plus_one
) {
3398 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3399 const_offset
%= max_offset_plus_one
;
3403 const_offset
/= (size
/ 2u);
3405 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3406 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3408 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3410 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3413 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3418 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3420 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3421 Temp offset
, unsigned bytes_needed
,
3422 unsigned align
, unsigned const_offset
,
3427 if (bytes_needed
<= 4) {
3429 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3430 } else if (bytes_needed
<= 8) {
3432 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3433 } else if (bytes_needed
<= 16) {
3435 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3436 } else if (bytes_needed
<= 32) {
3438 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3441 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3443 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3444 if (info
->resource
.id()) {
3445 load
->operands
[0] = Operand(info
->resource
);
3446 load
->operands
[1] = Operand(offset
);
3448 load
->operands
[0] = Operand(offset
);
3449 load
->operands
[1] = Operand(0u);
3451 RegClass
rc(RegType::sgpr
, size
);
3452 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3453 load
->definitions
[0] = Definition(val
);
3454 load
->glc
= info
->glc
;
3455 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3456 load
->barrier
= info
->barrier
;
3457 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3458 bld
.insert(std::move(load
));
3462 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3464 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3465 Temp offset
, unsigned bytes_needed
,
3466 unsigned align_
, unsigned const_offset
,
3469 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3470 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3472 if (info
->soffset
.id()) {
3473 if (soffset
.isTemp())
3474 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3475 soffset
= Operand(info
->soffset
);
3478 unsigned bytes_size
= 0;
3480 if (bytes_needed
== 1) {
3482 op
= aco_opcode::buffer_load_ubyte
;
3483 } else if (bytes_needed
== 2) {
3485 op
= aco_opcode::buffer_load_ushort
;
3486 } else if (bytes_needed
<= 4) {
3488 op
= aco_opcode::buffer_load_dword
;
3489 } else if (bytes_needed
<= 8) {
3491 op
= aco_opcode::buffer_load_dwordx2
;
3492 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3494 op
= aco_opcode::buffer_load_dwordx3
;
3497 op
= aco_opcode::buffer_load_dwordx4
;
3499 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3500 mubuf
->operands
[0] = Operand(info
->resource
);
3501 mubuf
->operands
[1] = vaddr
;
3502 mubuf
->operands
[2] = soffset
;
3503 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3504 mubuf
->glc
= info
->glc
;
3505 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3506 mubuf
->barrier
= info
->barrier
;
3507 mubuf
->can_reorder
= info
->can_reorder
;
3508 mubuf
->offset
= const_offset
;
3509 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3510 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3511 mubuf
->definitions
[0] = Definition(val
);
3512 bld
.insert(std::move(mubuf
));
3515 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3520 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3522 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3524 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3525 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3527 if (addr
.type() == RegType::vgpr
)
3528 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3529 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3532 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3533 Temp offset
, unsigned bytes_needed
,
3534 unsigned align_
, unsigned const_offset
,
3537 unsigned bytes_size
= 0;
3538 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3539 bool global
= bld
.program
->chip_class
>= GFX9
;
3541 if (bytes_needed
== 1) {
3543 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3544 } else if (bytes_needed
== 2) {
3546 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3547 } else if (bytes_needed
<= 4) {
3549 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3550 } else if (bytes_needed
<= 8) {
3552 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3553 } else if (bytes_needed
<= 12 && !mubuf
) {
3555 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3558 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3560 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3561 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3563 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3564 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3565 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3566 mubuf
->operands
[2] = Operand(0u);
3567 mubuf
->glc
= info
->glc
;
3570 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3571 mubuf
->disable_wqm
= false;
3572 mubuf
->barrier
= info
->barrier
;
3573 mubuf
->definitions
[0] = Definition(val
);
3574 bld
.insert(std::move(mubuf
));
3576 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3578 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3579 flat
->operands
[0] = Operand(offset
);
3580 flat
->operands
[1] = Operand(s1
);
3581 flat
->glc
= info
->glc
;
3582 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3583 flat
->barrier
= info
->barrier
;
3585 flat
->definitions
[0] = Definition(val
);
3586 bld
.insert(std::move(flat
));
3590 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3595 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3597 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3598 Temp address
, unsigned base_offset
, unsigned align
)
3600 assert(util_is_power_of_two_nonzero(align
));
3602 Builder
bld(ctx
->program
, ctx
->block
);
3604 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3605 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3606 info
.align_mul
= align
;
3607 info
.align_offset
= 0;
3608 info
.barrier
= barrier_shared
;
3609 info
.can_reorder
= false;
3610 info
.const_offset
= base_offset
;
3611 emit_lds_load(ctx
, bld
, &info
);
3616 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3621 Builder
bld(ctx
->program
, ctx
->block
);
3623 ASSERTED
bool is_subdword
= false;
3624 for (unsigned i
= 0; i
< count
; i
++)
3625 is_subdword
|= offsets
[i
] % 4;
3626 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3627 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3629 /* count == 1 fast path */
3631 if (dst_type
== RegType::sgpr
)
3632 dst
[0] = bld
.as_uniform(src
);
3634 dst
[0] = as_vgpr(ctx
, src
);
3638 for (unsigned i
= 0; i
< count
- 1; i
++)
3639 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3640 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3642 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3643 src
= as_vgpr(ctx
, src
);
3645 /* use allocated_vec if possible */
3646 auto it
= ctx
->allocated_vec
.find(src
.id());
3647 if (it
!= ctx
->allocated_vec
.end()) {
3648 unsigned total_size
= 0;
3649 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3650 total_size
+= it
->second
[i
].bytes();
3651 if (total_size
!= src
.bytes())
3654 unsigned elem_size
= it
->second
[0].bytes();
3656 for (unsigned i
= 0; i
< count
; i
++) {
3657 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3661 for (unsigned i
= 0; i
< count
; i
++) {
3662 unsigned start_idx
= offsets
[i
] / elem_size
;
3663 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3664 if (op_count
== 1) {
3665 if (dst_type
== RegType::sgpr
)
3666 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3668 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3672 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3673 for (unsigned j
= 0; j
< op_count
; j
++) {
3674 Temp tmp
= it
->second
[start_idx
+ j
];
3675 if (dst_type
== RegType::sgpr
)
3676 tmp
= bld
.as_uniform(tmp
);
3677 vec
->operands
[j
] = Operand(tmp
);
3679 vec
->definitions
[0] = Definition(dst
[i
]);
3680 bld
.insert(std::move(vec
));
3686 if (dst_type
== RegType::sgpr
)
3687 src
= bld
.as_uniform(src
);
3691 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3692 split
->operands
[0] = Operand(src
);
3693 for (unsigned i
= 0; i
< count
; i
++)
3694 split
->definitions
[i
] = Definition(dst
[i
]);
3695 bld
.insert(std::move(split
));
3698 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3699 int *start
, int *count
)
3701 unsigned start_elem
= ffs(todo_mask
) - 1;
3702 bool skip
= !(mask
& (1 << start_elem
));
3704 mask
= ~mask
& todo_mask
;
3708 u_bit_scan_consecutive_range(&mask
, start
, count
);
3713 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3715 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3718 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3719 Temp address
, unsigned base_offset
, unsigned align
)
3721 assert(util_is_power_of_two_nonzero(align
));
3722 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3724 Builder
bld(ctx
->program
, ctx
->block
);
3725 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3726 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3728 unsigned write_count
= 0;
3729 Temp write_datas
[32];
3730 unsigned offsets
[32];
3731 aco_opcode opcodes
[32];
3733 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3735 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3738 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3739 offsets
[write_count
] = offset
;
3740 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3742 advance_write_mask(&todo
, offset
, bytes
);
3746 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3747 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3748 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3749 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3751 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3752 aco_opcode op
= aco_opcode::num_opcodes
;
3753 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3754 op
= aco_opcode::ds_write_b128
;
3756 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3757 op
= aco_opcode::ds_write_b96
;
3759 } else if (bytes
>= 8 && aligned8
) {
3760 op
= aco_opcode::ds_write_b64
;
3762 } else if (bytes
>= 4 && aligned4
) {
3763 op
= aco_opcode::ds_write_b32
;
3765 } else if (bytes
>= 2 && aligned2
) {
3766 op
= aco_opcode::ds_write_b16
;
3768 } else if (bytes
>= 1) {
3769 op
= aco_opcode::ds_write_b8
;
3775 offsets
[write_count
] = offset
;
3776 opcodes
[write_count
] = op
;
3778 advance_write_mask(&todo
, offset
, bytes
);
3781 Operand m
= load_lds_size_m0(bld
);
3783 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3785 for (unsigned i
= 0; i
< write_count
; i
++) {
3786 aco_opcode op
= opcodes
[i
];
3787 if (op
== aco_opcode::num_opcodes
)
3790 Temp data
= write_datas
[i
];
3792 unsigned second
= write_count
;
3793 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3794 for (second
= i
+ 1; second
< write_count
; second
++) {
3795 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3796 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3797 opcodes
[second
] = aco_opcode::num_opcodes
;
3803 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3804 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3806 unsigned inline_offset
= base_offset
+ offsets
[i
];
3807 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3808 Temp address_offset
= address
;
3809 if (inline_offset
> max_offset
) {
3810 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3811 inline_offset
= offsets
[i
];
3813 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3816 Temp second_data
= write_datas
[second
];
3817 inline_offset
/= data
.bytes();
3818 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3820 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3825 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3827 unsigned align
= 16;
3829 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3835 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3840 return aco_opcode::buffer_store_byte
;
3843 return aco_opcode::buffer_store_short
;
3845 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3847 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3850 return aco_opcode::buffer_store_dwordx3
;
3852 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3854 unreachable("Unexpected store size");
3855 return aco_opcode::num_opcodes
;
3858 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3859 Temp data
, unsigned writemask
, int swizzle_element_size
,
3860 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3862 unsigned write_count_with_skips
= 0;
3865 /* determine how to split the data */
3866 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3869 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3870 offsets
[write_count_with_skips
] = offset
;
3871 if (skips
[write_count_with_skips
]) {
3872 advance_write_mask(&todo
, offset
, bytes
);
3873 write_count_with_skips
++;
3877 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3878 * larger than swizzle_element_size */
3879 bytes
= MIN2(bytes
, swizzle_element_size
);
3881 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3883 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3884 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3887 /* dword or larger stores have to be dword-aligned */
3888 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3889 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3890 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3891 if (bytes
>= 4 && !dword_aligned
)
3892 bytes
= MIN2(bytes
, 2);
3894 advance_write_mask(&todo
, offset
, bytes
);
3895 write_count_with_skips
++;
3898 /* actually split data */
3899 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3902 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3905 write_datas
[*write_count
] = write_datas
[i
];
3906 offsets
[*write_count
] = offsets
[i
];
3911 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3912 unsigned split_cnt
= 0u, Temp dst
= Temp())
3914 Builder
bld(ctx
->program
, ctx
->block
);
3915 unsigned dword_size
= elem_size_bytes
/ 4;
3918 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3920 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3921 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3922 instr
->definitions
[0] = Definition(dst
);
3924 for (unsigned i
= 0; i
< cnt
; ++i
) {
3926 assert(arr
[i
].size() == dword_size
);
3927 allocated_vec
[i
] = arr
[i
];
3928 instr
->operands
[i
] = Operand(arr
[i
]);
3930 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3931 allocated_vec
[i
] = zero
;
3932 instr
->operands
[i
] = Operand(zero
);
3936 bld
.insert(std::move(instr
));
3939 emit_split_vector(ctx
, dst
, split_cnt
);
3941 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3946 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3948 if (const_offset
>= 4096) {
3949 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3950 const_offset
%= 4096u;
3953 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3954 else if (unlikely(voffset
.regClass() == s1
))
3955 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3956 else if (likely(voffset
.regClass() == v1
))
3957 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3959 unreachable("Unsupported register class of voffset");
3962 return const_offset
;
3965 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3966 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3969 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3970 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3972 Builder
bld(ctx
->program
, ctx
->block
);
3973 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3974 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3976 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3977 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3978 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3979 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3980 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3982 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3985 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3986 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3987 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3989 Builder
bld(ctx
->program
, ctx
->block
);
3990 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3992 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3994 unsigned write_count
= 0;
3995 Temp write_datas
[32];
3996 unsigned offsets
[32];
3997 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3998 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4000 for (unsigned i
= 0; i
< write_count
; i
++) {
4001 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4002 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
4006 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4007 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4008 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4010 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
4011 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
4012 assert(!!stride
!= allow_combining
);
4014 Builder
bld(ctx
->program
, ctx
->block
);
4016 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4017 info
.component_stride
= allow_combining
? 0 : stride
;
4019 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4020 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4021 info
.align_offset
= 0;
4022 info
.soffset
= soffset
;
4023 info
.const_offset
= base_const_offset
;
4024 emit_mubuf_load(ctx
, bld
, &info
);
4027 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4029 Builder
bld(ctx
->program
, ctx
->block
);
4030 Temp offset
= base_offset
.first
;
4031 unsigned const_offset
= base_offset
.second
;
4033 if (!nir_src_is_const(*off_src
)) {
4034 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4037 /* Calculate indirect offset with stride */
4038 if (likely(indirect_offset_arg
.regClass() == v1
))
4039 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4040 else if (indirect_offset_arg
.regClass() == s1
)
4041 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4043 unreachable("Unsupported register class of indirect offset");
4045 /* Add to the supplied base offset */
4046 if (offset
.id() == 0)
4047 offset
= with_stride
;
4048 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4049 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4050 else if (offset
.size() == 1 && with_stride
.size() == 1)
4051 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4053 unreachable("Unsupported register class of indirect offset");
4055 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4056 const_offset
+= const_offset_arg
* stride
;
4059 return std::make_pair(offset
, const_offset
);
4062 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4064 Builder
bld(ctx
->program
, ctx
->block
);
4067 if (off1
.first
.id() && off2
.first
.id()) {
4068 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4069 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4070 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4071 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4073 unreachable("Unsupported register class of indirect offset");
4075 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4078 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4081 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4083 Builder
bld(ctx
->program
, ctx
->block
);
4084 unsigned const_offset
= offs
.second
* multiplier
;
4086 if (!offs
.first
.id())
4087 return std::make_pair(offs
.first
, const_offset
);
4089 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4090 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4091 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4093 return std::make_pair(offset
, const_offset
);
4096 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4098 Builder
bld(ctx
->program
, ctx
->block
);
4100 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4101 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4102 /* component is in bytes */
4103 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4105 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4106 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4107 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4110 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4112 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4115 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4117 Builder
bld(ctx
->program
, ctx
->block
);
4119 switch (ctx
->shader
->info
.stage
) {
4120 case MESA_SHADER_TESS_CTRL
:
4121 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4122 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4123 case MESA_SHADER_TESS_EVAL
:
4124 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4126 unreachable("Unsupported stage in get_tess_rel_patch_id");
4130 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4132 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4133 Builder
bld(ctx
->program
, ctx
->block
);
4135 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4136 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4138 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4140 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4141 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4143 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4144 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4145 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4147 return offset_mul(ctx
, offs
, 4u);
4150 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4152 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4153 Builder
bld(ctx
->program
, ctx
->block
);
4155 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4156 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4157 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4158 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4160 std::pair
<Temp
, unsigned> offs
= instr
4161 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4162 : std::make_pair(Temp(), 0u);
4164 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4165 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4170 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4171 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4173 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4174 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4176 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4177 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4183 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4185 Builder
bld(ctx
->program
, ctx
->block
);
4187 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4188 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4190 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4192 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4193 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4194 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4196 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4197 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4202 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4204 Builder
bld(ctx
->program
, ctx
->block
);
4206 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4207 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4208 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4209 unsigned attr_stride
= ctx
->tcs_num_patches
;
4211 std::pair
<Temp
, unsigned> offs
= instr
4212 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4213 : std::make_pair(Temp(), 0u);
4215 if (const_base_offset
)
4216 offs
.second
+= const_base_offset
* attr_stride
;
4218 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4219 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4220 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4225 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4230 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4231 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4233 if (!nir_src_is_const(*off_src
)) {
4239 off
+= nir_src_as_uint(*off_src
) * 16u;
4242 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
4243 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
4250 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4252 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4253 unsigned component
= nir_intrinsic_component(instr
);
4254 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4256 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4257 if (off_instr
->type
!= nir_instr_type_load_const
)
4260 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4261 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4263 if (instr
->src
[0].ssa
->bit_size
== 64)
4264 write_mask
= widen_mask(write_mask
, 2);
4266 for (unsigned i
= 0; i
< 8; ++i
) {
4267 if (write_mask
& (1 << i
)) {
4268 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4269 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
4277 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4279 /* Only TCS per-vertex inputs are supported by this function.
4280 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4282 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4285 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4286 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4287 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4288 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4289 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4290 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4295 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4296 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4297 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4302 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4304 Builder
bld(ctx
->program
, ctx
->block
);
4306 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4307 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4308 bool indirect_write
;
4309 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4310 if (temp_only_input
&& !indirect_write
)
4314 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4315 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4316 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4317 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4319 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4320 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4321 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4322 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4323 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4327 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4328 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4329 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4330 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4331 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4332 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4333 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4334 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4335 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4336 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4337 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4338 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4339 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4341 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4342 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4344 unreachable("Invalid LS or ES stage");
4347 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4348 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4349 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4353 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4358 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4359 return off
== ctx
->tcs_tess_lvl_out_loc
||
4360 off
== ctx
->tcs_tess_lvl_in_loc
;
4364 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4366 uint64_t mask
= per_vertex
4367 ? ctx
->program
->info
->tcs
.tes_inputs_read
4368 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4370 bool indirect_write
= false;
4371 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4372 return indirect_write
|| output_read_by_tes
;
4375 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4377 uint64_t mask
= per_vertex
4378 ? ctx
->shader
->info
.outputs_read
4379 : ctx
->shader
->info
.patch_outputs_read
;
4381 bool indirect_write
= false;
4382 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4383 return indirect_write
|| output_read
;
4386 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4388 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4389 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4391 Builder
bld(ctx
->program
, ctx
->block
);
4393 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4394 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4395 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4397 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4398 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4399 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4401 if (write_to_vmem
) {
4402 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4403 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4404 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4406 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4407 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4408 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4412 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4413 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4414 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4418 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4420 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4421 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4423 Builder
bld(ctx
->program
, ctx
->block
);
4425 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4426 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4427 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4428 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4430 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4433 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4435 if (ctx
->stage
== vertex_vs
||
4436 ctx
->stage
== tess_eval_vs
||
4437 ctx
->stage
== fragment_fs
||
4438 ctx
->stage
== ngg_vertex_gs
||
4439 ctx
->stage
== ngg_tess_eval_gs
||
4440 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4441 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4442 if (!stored_to_temps
) {
4443 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4444 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4445 fprintf(stderr
, "\n");
4448 } else if (ctx
->stage
== vertex_es
||
4449 ctx
->stage
== vertex_ls
||
4450 ctx
->stage
== tess_eval_es
||
4451 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4452 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4453 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4454 visit_store_ls_or_es_output(ctx
, instr
);
4455 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4456 visit_store_tcs_output(ctx
, instr
, false);
4458 unreachable("Shader stage not implemented");
4462 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4464 visit_load_tcs_output(ctx
, instr
, false);
4467 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4469 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4470 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4472 Builder
bld(ctx
->program
, ctx
->block
);
4473 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4474 if (ctx
->program
->has_16bank_lds
)
4475 interp_p1
.instr
->operands
[0].setLateKill(true);
4476 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4479 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4481 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4482 for (unsigned i
= 0; i
< num_components
; i
++)
4483 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4484 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4485 assert(num_components
== 4);
4486 Builder
bld(ctx
->program
, ctx
->block
);
4487 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4490 for (Operand
& op
: vec
->operands
)
4491 op
= op
.isUndefined() ? Operand(0u) : op
;
4493 vec
->definitions
[0] = Definition(dst
);
4494 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4495 emit_split_vector(ctx
, dst
, num_components
);
4499 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4501 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4502 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4503 unsigned idx
= nir_intrinsic_base(instr
);
4504 unsigned component
= nir_intrinsic_component(instr
);
4505 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4507 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4509 assert(offset
->u32
== 0);
4511 /* the lower 15bit of the prim_mask contain the offset into LDS
4512 * while the upper bits contain the number of prims */
4513 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4514 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4515 Builder
bld(ctx
->program
, ctx
->block
);
4516 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4517 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4518 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4519 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4520 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4523 if (instr
->dest
.ssa
.num_components
== 1) {
4524 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4526 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4527 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4529 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4530 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4531 vec
->operands
[i
] = Operand(tmp
);
4533 vec
->definitions
[0] = Definition(dst
);
4534 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4538 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4539 unsigned offset
, unsigned stride
, unsigned channels
)
4541 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4542 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4544 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4545 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4548 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4549 unsigned offset
, unsigned stride
, unsigned *channels
)
4551 if (!vtx_info
->chan_byte_size
) {
4552 *channels
= vtx_info
->num_channels
;
4553 return vtx_info
->chan_format
;
4556 unsigned num_channels
= *channels
;
4557 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4558 unsigned new_channels
= num_channels
+ 1;
4559 /* first, assume more loads is worse and try using a larger data format */
4560 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4562 /* don't make the attribute potentially out-of-bounds */
4563 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4567 if (new_channels
== 5) {
4568 /* then try decreasing load size (at the cost of more loads) */
4569 new_channels
= *channels
;
4570 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4574 if (new_channels
< *channels
)
4575 *channels
= new_channels
;
4576 num_channels
= new_channels
;
4579 switch (vtx_info
->chan_format
) {
4580 case V_008F0C_BUF_DATA_FORMAT_8
:
4581 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4582 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4583 case V_008F0C_BUF_DATA_FORMAT_16
:
4584 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4585 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4586 case V_008F0C_BUF_DATA_FORMAT_32
:
4587 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4588 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4590 unreachable("shouldn't reach here");
4591 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4594 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4595 * so we may need to fix it up. */
4596 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4598 Builder
bld(ctx
->program
, ctx
->block
);
4600 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4601 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4603 /* For the integer-like cases, do a natural sign extension.
4605 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4606 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4609 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4610 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4612 /* Convert back to the right type. */
4613 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4614 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4615 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4616 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4617 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4618 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4624 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4626 Builder
bld(ctx
->program
, ctx
->block
);
4627 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4628 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4630 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4631 if (off_instr
->type
!= nir_instr_type_load_const
) {
4632 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4633 nir_print_instr(off_instr
, stderr
);
4634 fprintf(stderr
, "\n");
4636 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4638 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4640 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4641 unsigned component
= nir_intrinsic_component(instr
);
4642 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4643 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4644 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4645 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4647 unsigned dfmt
= attrib_format
& 0xf;
4648 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4649 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4651 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4652 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4653 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4654 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4656 num_channels
= MAX2(num_channels
, 3);
4658 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4659 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4662 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4663 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4664 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4666 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4668 Temp divided
= bld
.tmp(v1
);
4669 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4670 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4672 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4675 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4678 index
= bld
.vadd32(bld
.def(v1
),
4679 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4680 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4683 Temp channels
[num_channels
];
4684 unsigned channel_start
= 0;
4685 bool direct_fetch
= false;
4687 /* skip unused channels at the start */
4688 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4689 channel_start
= ffs(mask
) - 1;
4690 for (unsigned i
= 0; i
< channel_start
; i
++)
4691 channels
[i
] = Temp(0, s1
);
4692 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4693 num_channels
= 3 - (ffs(mask
) - 1);
4697 while (channel_start
< num_channels
) {
4698 unsigned fetch_size
= num_channels
- channel_start
;
4699 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4700 bool expanded
= false;
4702 /* use MUBUF when possible to avoid possible alignment issues */
4703 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4704 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4705 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4706 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4707 vtx_info
->chan_byte_size
== 4;
4708 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4710 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4712 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4713 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4719 Temp fetch_index
= index
;
4720 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4721 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4722 fetch_offset
= fetch_offset
% attrib_stride
;
4725 Operand
soffset(0u);
4726 if (fetch_offset
>= 4096) {
4727 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4728 fetch_offset
%= 4096;
4732 switch (fetch_size
) {
4734 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4737 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4740 assert(ctx
->options
->chip_class
>= GFX7
||
4741 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4742 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4745 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4748 unreachable("Unimplemented load_input vector size");
4752 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4753 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4754 num_channels
<= 3)) {
4755 direct_fetch
= true;
4758 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4762 Instruction
*mubuf
= bld
.mubuf(opcode
,
4763 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4764 fetch_offset
, false, true).instr
;
4765 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4767 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4768 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4769 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4770 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4773 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4775 if (fetch_size
== 1) {
4776 channels
[channel_start
] = fetch_dst
;
4778 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4779 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4782 channel_start
+= fetch_size
;
4785 if (!direct_fetch
) {
4786 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4787 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4789 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4790 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4791 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4793 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4794 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4795 unsigned num_temp
= 0;
4796 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4797 unsigned idx
= i
+ component
;
4798 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4799 Temp channel
= channels
[swizzle
[idx
]];
4800 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4801 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4802 vec
->operands
[i
] = Operand(channel
);
4806 } else if (is_float
&& idx
== 3) {
4807 vec
->operands
[i
] = Operand(0x3f800000u
);
4808 } else if (!is_float
&& idx
== 3) {
4809 vec
->operands
[i
] = Operand(1u);
4811 vec
->operands
[i
] = Operand(0u);
4814 vec
->definitions
[0] = Definition(dst
);
4815 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4816 emit_split_vector(ctx
, dst
, dst
.size());
4818 if (num_temp
== dst
.size())
4819 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4821 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4822 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4823 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4824 if (off_instr
->type
!= nir_instr_type_load_const
||
4825 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4826 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4827 nir_print_instr(off_instr
, stderr
);
4828 fprintf(stderr
, "\n");
4831 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4832 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4834 assert(offset
->u32
== 0);
4836 /* the lower 15bit of the prim_mask contain the offset into LDS
4837 * while the upper bits contain the number of prims */
4838 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4839 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4840 Builder
bld(ctx
->program
, ctx
->block
);
4841 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4842 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4843 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4844 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4845 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4848 unsigned idx
= nir_intrinsic_base(instr
);
4849 unsigned component
= nir_intrinsic_component(instr
);
4850 unsigned vertex_id
= 2; /* P0 */
4852 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4853 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4854 switch (src0
->u32
) {
4856 vertex_id
= 2; /* P0 */
4859 vertex_id
= 0; /* P10 */
4862 vertex_id
= 1; /* P20 */
4865 unreachable("invalid vertex index");
4869 if (dst
.size() == 1) {
4870 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4872 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4873 for (unsigned i
= 0; i
< dst
.size(); i
++)
4874 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4875 vec
->definitions
[0] = Definition(dst
);
4876 bld
.insert(std::move(vec
));
4879 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4880 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4881 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4882 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4883 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4885 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4887 unreachable("Shader stage not implemented");
4891 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4893 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4895 Builder
bld(ctx
->program
, ctx
->block
);
4896 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4899 if (!nir_src_is_const(*vertex_src
)) {
4900 /* better code could be created, but this case probably doesn't happen
4901 * much in practice */
4902 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4903 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4906 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4907 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4909 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4911 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4914 if (vertex_offset
.id()) {
4915 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4916 Operand(i
), indirect_vertex
);
4917 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4919 vertex_offset
= elem
;
4923 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4924 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4926 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4927 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4928 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4929 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4930 Operand((vertex
% 2u) * 16u), Operand(16u));
4932 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4935 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4936 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4937 return offset_mul(ctx
, offs
, 4u);
4940 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4942 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4944 Builder
bld(ctx
->program
, ctx
->block
);
4945 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4946 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4948 if (ctx
->stage
== geometry_gs
) {
4949 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4950 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4951 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4952 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4953 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4954 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4955 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4957 unreachable("Unsupported GS stage.");
4961 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4963 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4965 Builder
bld(ctx
->program
, ctx
->block
);
4966 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4968 if (load_input_from_temps(ctx
, instr
, dst
))
4971 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4972 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4973 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4975 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4978 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4980 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4982 Builder
bld(ctx
->program
, ctx
->block
);
4984 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4985 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4986 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4988 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4989 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4991 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4994 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4996 switch (ctx
->shader
->info
.stage
) {
4997 case MESA_SHADER_GEOMETRY
:
4998 visit_load_gs_per_vertex_input(ctx
, instr
);
5000 case MESA_SHADER_TESS_CTRL
:
5001 visit_load_tcs_per_vertex_input(ctx
, instr
);
5003 case MESA_SHADER_TESS_EVAL
:
5004 visit_load_tes_per_vertex_input(ctx
, instr
);
5007 unreachable("Unimplemented shader stage");
5011 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5013 visit_load_tcs_output(ctx
, instr
, true);
5016 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5018 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5019 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5021 visit_store_tcs_output(ctx
, instr
, true);
5024 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5026 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5028 Builder
bld(ctx
->program
, ctx
->block
);
5029 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5031 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5032 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5035 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5036 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5037 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5038 tes_w
= Operand(tmp
);
5041 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5042 emit_split_vector(ctx
, tess_coord
, 3);
5045 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5047 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5048 Builder
bld(ctx
->program
, ctx
->block
);
5049 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5050 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5051 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5054 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5058 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5060 Builder
bld(ctx
->program
, ctx
->block
);
5061 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5062 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
5063 index
= bld
.as_uniform(index
);
5064 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5065 unsigned binding
= nir_intrinsic_binding(instr
);
5068 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5069 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5070 unsigned offset
= layout
->binding
[binding
].offset
;
5072 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5073 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5074 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5075 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5076 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5079 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5080 stride
= layout
->binding
[binding
].size
;
5083 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5084 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5086 if (nir_const_index
) {
5087 const_index
= const_index
* stride
;
5088 } else if (index
.type() == RegType::vgpr
) {
5089 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5090 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5092 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5096 if (nir_const_index
) {
5097 const_index
= const_index
+ offset
;
5098 } else if (index
.type() == RegType::vgpr
) {
5099 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5101 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5105 if (nir_const_index
&& const_index
== 0) {
5107 } else if (index
.type() == RegType::vgpr
) {
5108 index
= bld
.vadd32(bld
.def(v1
),
5109 nir_const_index
? Operand(const_index
) : Operand(index
),
5112 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5113 nir_const_index
? Operand(const_index
) : Operand(index
),
5117 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5120 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5121 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5122 bool glc
=false, bool readonly
=true)
5124 Builder
bld(ctx
->program
, ctx
->block
);
5126 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5128 offset
= bld
.as_uniform(offset
);
5130 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5132 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5133 info
.can_reorder
= readonly
;
5134 info
.align_mul
= align_mul
;
5135 info
.align_offset
= align_offset
;
5137 emit_smem_load(ctx
, bld
, &info
);
5139 emit_mubuf_load(ctx
, bld
, &info
);
5142 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5144 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5145 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5147 Builder
bld(ctx
->program
, ctx
->block
);
5149 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5150 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5151 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5152 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5154 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5155 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5156 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5157 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5158 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5159 if (ctx
->options
->chip_class
>= GFX10
) {
5160 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5161 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5162 S_008F0C_RESOURCE_LEVEL(1);
5164 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5165 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5167 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5168 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5169 Operand(0xFFFFFFFFu
),
5170 Operand(desc_type
));
5171 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5172 rsrc
, upper_dwords
);
5174 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5175 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5177 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5178 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5179 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5182 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5184 Builder
bld(ctx
->program
, ctx
->block
);
5185 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5186 unsigned offset
= nir_intrinsic_base(instr
);
5187 unsigned count
= instr
->dest
.ssa
.num_components
;
5188 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5190 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5191 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5192 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5193 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5194 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5195 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5196 for (unsigned i
= 0; i
< count
; ++i
) {
5197 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5198 vec
->operands
[i
] = Operand
{elems
[i
]};
5200 vec
->definitions
[0] = Definition(dst
);
5201 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5202 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5207 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5208 if (offset
!= 0) // TODO check if index != 0 as well
5209 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5210 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5213 bool aligned
= true;
5215 if (instr
->dest
.ssa
.bit_size
== 8) {
5216 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5217 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5219 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5220 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5221 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5223 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5228 switch (vec
.size()) {
5230 op
= aco_opcode::s_load_dword
;
5233 op
= aco_opcode::s_load_dwordx2
;
5239 op
= aco_opcode::s_load_dwordx4
;
5245 op
= aco_opcode::s_load_dwordx8
;
5248 unreachable("unimplemented or forbidden load_push_constant.");
5251 bld
.smem(op
, Definition(vec
), ptr
, index
);
5254 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5255 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5260 emit_split_vector(ctx
, vec
, 4);
5261 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5263 emit_extract_vector(ctx
, vec
, 0, rc
),
5264 emit_extract_vector(ctx
, vec
, 1, rc
),
5265 emit_extract_vector(ctx
, vec
, 2, rc
));
5268 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5271 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5273 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5275 Builder
bld(ctx
->program
, ctx
->block
);
5277 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5278 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5279 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5280 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5281 if (ctx
->options
->chip_class
>= GFX10
) {
5282 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5283 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5284 S_008F0C_RESOURCE_LEVEL(1);
5286 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5287 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5290 unsigned base
= nir_intrinsic_base(instr
);
5291 unsigned range
= nir_intrinsic_range(instr
);
5293 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5294 if (base
&& offset
.type() == RegType::sgpr
)
5295 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5296 else if (base
&& offset
.type() == RegType::vgpr
)
5297 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5299 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5300 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5301 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5302 Operand(desc_type
));
5303 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5304 // TODO: get alignment information for subdword constants
5305 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5308 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5310 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5311 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5313 ctx
->program
->needs_exact
= true;
5315 // TODO: optimize uniform conditions
5316 Builder
bld(ctx
->program
, ctx
->block
);
5317 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5318 assert(src
.regClass() == bld
.lm
);
5319 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5320 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5321 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5325 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5327 Builder
bld(ctx
->program
, ctx
->block
);
5329 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5330 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5332 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5333 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5335 if (ctx
->block
->loop_nest_depth
&&
5336 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5337 /* we handle discards the same way as jump instructions */
5338 append_logical_end(ctx
->block
);
5340 /* in loops, discard behaves like break */
5341 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5342 ctx
->block
->kind
|= block_kind_discard
;
5345 /* uniform discard - loop ends here */
5346 assert(nir_instr_is_last(&instr
->instr
));
5347 ctx
->block
->kind
|= block_kind_uniform
;
5348 ctx
->cf_info
.has_branch
= true;
5349 bld
.branch(aco_opcode::p_branch
);
5350 add_linear_edge(ctx
->block
->index
, linear_target
);
5354 /* we add a break right behind the discard() instructions */
5355 ctx
->block
->kind
|= block_kind_break
;
5356 unsigned idx
= ctx
->block
->index
;
5358 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5359 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5361 /* remove critical edges from linear CFG */
5362 bld
.branch(aco_opcode::p_branch
);
5363 Block
* break_block
= ctx
->program
->create_and_insert_block();
5364 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5365 break_block
->kind
|= block_kind_uniform
;
5366 add_linear_edge(idx
, break_block
);
5367 add_linear_edge(break_block
->index
, linear_target
);
5368 bld
.reset(break_block
);
5369 bld
.branch(aco_opcode::p_branch
);
5371 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5372 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5373 add_linear_edge(idx
, continue_block
);
5374 append_logical_start(continue_block
);
5375 ctx
->block
= continue_block
;
5380 /* it can currently happen that NIR doesn't remove the unreachable code */
5381 if (!nir_instr_is_last(&instr
->instr
)) {
5382 ctx
->program
->needs_exact
= true;
5383 /* save exec somewhere temporarily so that it doesn't get
5384 * overwritten before the discard from outer exec masks */
5385 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5386 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5387 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5391 /* This condition is incorrect for uniformly branched discards in a loop
5392 * predicated by a divergent condition, but the above code catches that case
5393 * and the discard would end up turning into a discard_if.
5403 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5404 /* program just ends here */
5405 ctx
->block
->kind
|= block_kind_uniform
;
5406 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5407 0 /* enabled mask */, 9 /* dest */,
5408 false /* compressed */, true/* done */, true /* valid mask */);
5409 bld
.sopp(aco_opcode::s_endpgm
);
5410 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5412 ctx
->block
->kind
|= block_kind_discard
;
5413 /* branch and linear edge is added by visit_if() */
5417 enum aco_descriptor_type
{
5428 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5429 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5431 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5432 return dim
== ac_image_cube
||
5433 dim
== ac_image_1darray
||
5434 dim
== ac_image_2darray
||
5435 dim
== ac_image_2darraymsaa
;
5438 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5439 enum aco_descriptor_type desc_type
,
5440 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5442 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5443 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5444 if (it != ctx->tex_desc.end())
5447 Temp index
= Temp();
5448 bool index_set
= false;
5449 unsigned constant_index
= 0;
5450 unsigned descriptor_set
;
5451 unsigned base_index
;
5452 Builder
bld(ctx
->program
, ctx
->block
);
5455 assert(tex_instr
&& !image
);
5457 base_index
= tex_instr
->sampler_index
;
5459 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5460 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5464 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5465 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5467 constant_index
+= array_size
* const_value
->u32
;
5469 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5470 if (indirect
.type() == RegType::vgpr
)
5471 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5473 if (array_size
!= 1)
5474 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5480 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5484 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5486 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5487 base_index
= deref_instr
->var
->data
.binding
;
5490 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5491 list
= convert_pointer_to_64_bit(ctx
, list
);
5493 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5494 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5495 unsigned offset
= binding
->offset
;
5496 unsigned stride
= binding
->size
;
5500 assert(base_index
< layout
->binding_count
);
5502 switch (desc_type
) {
5503 case ACO_DESC_IMAGE
:
5505 opcode
= aco_opcode::s_load_dwordx8
;
5507 case ACO_DESC_FMASK
:
5509 opcode
= aco_opcode::s_load_dwordx8
;
5512 case ACO_DESC_SAMPLER
:
5514 opcode
= aco_opcode::s_load_dwordx4
;
5515 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5516 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5518 case ACO_DESC_BUFFER
:
5520 opcode
= aco_opcode::s_load_dwordx4
;
5522 case ACO_DESC_PLANE_0
:
5523 case ACO_DESC_PLANE_1
:
5525 opcode
= aco_opcode::s_load_dwordx8
;
5526 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5528 case ACO_DESC_PLANE_2
:
5530 opcode
= aco_opcode::s_load_dwordx4
;
5534 unreachable("invalid desc_type\n");
5537 offset
+= constant_index
* stride
;
5539 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5540 (!index_set
|| binding
->immutable_samplers_equal
)) {
5541 if (binding
->immutable_samplers_equal
)
5544 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5545 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5546 Operand(samplers
[constant_index
* 4 + 0]),
5547 Operand(samplers
[constant_index
* 4 + 1]),
5548 Operand(samplers
[constant_index
* 4 + 2]),
5549 Operand(samplers
[constant_index
* 4 + 3]));
5554 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5556 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5557 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5560 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5562 if (desc_type
== ACO_DESC_PLANE_2
) {
5564 for (unsigned i
= 0; i
< 8; i
++)
5565 components
[i
] = bld
.tmp(s1
);
5566 bld
.pseudo(aco_opcode::p_split_vector
,
5567 Definition(components
[0]),
5568 Definition(components
[1]),
5569 Definition(components
[2]),
5570 Definition(components
[3]),
5573 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5574 bld
.pseudo(aco_opcode::p_split_vector
,
5575 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5576 Definition(components
[4]),
5577 Definition(components
[5]),
5578 Definition(components
[6]),
5579 Definition(components
[7]),
5582 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5583 components
[0], components
[1], components
[2], components
[3],
5584 components
[4], components
[5], components
[6], components
[7]);
5590 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5593 case GLSL_SAMPLER_DIM_BUF
:
5595 case GLSL_SAMPLER_DIM_1D
:
5596 return array
? 2 : 1;
5597 case GLSL_SAMPLER_DIM_2D
:
5598 return array
? 3 : 2;
5599 case GLSL_SAMPLER_DIM_MS
:
5600 return array
? 4 : 3;
5601 case GLSL_SAMPLER_DIM_3D
:
5602 case GLSL_SAMPLER_DIM_CUBE
:
5604 case GLSL_SAMPLER_DIM_RECT
:
5605 case GLSL_SAMPLER_DIM_SUBPASS
:
5607 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5616 /* Adjust the sample index according to FMASK.
5618 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5619 * which is the identity mapping. Each nibble says which physical sample
5620 * should be fetched to get that sample.
5622 * For example, 0x11111100 means there are only 2 samples stored and
5623 * the second sample covers 3/4 of the pixel. When reading samples 0
5624 * and 1, return physical sample 0 (determined by the first two 0s
5625 * in FMASK), otherwise return physical sample 1.
5627 * The sample index should be adjusted as follows:
5628 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5630 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5632 Builder
bld(ctx
->program
, ctx
->block
);
5633 Temp fmask
= bld
.tmp(v1
);
5634 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5635 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5638 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5639 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5640 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5641 load
->operands
[0] = Operand(fmask_desc_ptr
);
5642 load
->operands
[1] = Operand(s4
); /* no sampler */
5643 load
->operands
[2] = Operand(coord
);
5644 load
->definitions
[0] = Definition(fmask
);
5651 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5652 ctx
->block
->instructions
.emplace_back(std::move(load
));
5654 Operand sample_index4
;
5655 if (sample_index
.isConstant()) {
5656 if (sample_index
.constantValue() < 16) {
5657 sample_index4
= Operand(sample_index
.constantValue() << 2);
5659 sample_index4
= Operand(0u);
5661 } else if (sample_index
.regClass() == s1
) {
5662 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5664 assert(sample_index
.regClass() == v1
);
5665 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5669 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5670 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5671 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5672 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5674 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5676 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5677 * resource descriptor is 0 (invalid),
5679 Temp compare
= bld
.tmp(bld
.lm
);
5680 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5681 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5683 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5685 /* Replace the MSAA sample index. */
5686 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5689 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5692 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5693 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5694 bool is_array
= glsl_sampler_type_is_array(type
);
5695 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5696 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5697 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5698 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5699 int count
= image_type_to_components_count(dim
, is_array
);
5700 std::vector
<Temp
> coords(count
);
5701 Builder
bld(ctx
->program
, ctx
->block
);
5705 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5706 /* get sample index */
5707 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5708 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5709 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5710 std::vector
<Temp
> fmask_load_address
;
5711 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5712 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5714 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5715 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5717 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5722 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5723 coords
.resize(coords
.size() + 1);
5724 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5726 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5728 for (int i
= 0; i
< count
; i
++)
5729 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5732 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5733 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5734 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5735 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5738 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5741 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5742 for (unsigned i
= 0; i
< coords
.size(); i
++)
5743 vec
->operands
[i
] = Operand(coords
[i
]);
5744 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5745 vec
->definitions
[0] = Definition(res
);
5746 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5751 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5753 Builder
bld(ctx
->program
, ctx
->block
);
5754 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5755 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5756 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5757 bool is_array
= glsl_sampler_type_is_array(type
);
5758 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5760 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5761 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5762 unsigned num_channels
= util_last_bit(mask
);
5763 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5764 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5767 switch (num_channels
) {
5769 opcode
= aco_opcode::buffer_load_format_x
;
5772 opcode
= aco_opcode::buffer_load_format_xy
;
5775 opcode
= aco_opcode::buffer_load_format_xyz
;
5778 opcode
= aco_opcode::buffer_load_format_xyzw
;
5781 unreachable(">4 channel buffer image load");
5783 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5784 load
->operands
[0] = Operand(rsrc
);
5785 load
->operands
[1] = Operand(vindex
);
5786 load
->operands
[2] = Operand((uint32_t) 0);
5788 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5791 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5792 load
->definitions
[0] = Definition(tmp
);
5794 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5795 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5796 load
->barrier
= barrier_image
;
5797 ctx
->block
->instructions
.emplace_back(std::move(load
));
5799 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5803 Temp coords
= get_image_coords(ctx
, instr
, type
);
5804 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5806 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5807 unsigned num_components
= util_bitcount(dmask
);
5809 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5812 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5814 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5815 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5817 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5818 load
->operands
[0] = Operand(resource
);
5819 load
->operands
[1] = Operand(s4
); /* no sampler */
5820 load
->operands
[2] = Operand(coords
);
5821 load
->definitions
[0] = Definition(tmp
);
5822 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5823 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5824 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5825 load
->dmask
= dmask
;
5827 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5828 load
->barrier
= barrier_image
;
5829 ctx
->block
->instructions
.emplace_back(std::move(load
));
5831 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5835 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5837 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5838 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5839 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5840 bool is_array
= glsl_sampler_type_is_array(type
);
5841 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5843 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5845 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5846 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5847 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5849 switch (data
.size()) {
5851 opcode
= aco_opcode::buffer_store_format_x
;
5854 opcode
= aco_opcode::buffer_store_format_xy
;
5857 opcode
= aco_opcode::buffer_store_format_xyz
;
5860 opcode
= aco_opcode::buffer_store_format_xyzw
;
5863 unreachable(">4 channel buffer image store");
5865 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5866 store
->operands
[0] = Operand(rsrc
);
5867 store
->operands
[1] = Operand(vindex
);
5868 store
->operands
[2] = Operand((uint32_t) 0);
5869 store
->operands
[3] = Operand(data
);
5870 store
->idxen
= true;
5873 store
->disable_wqm
= true;
5874 store
->barrier
= barrier_image
;
5875 ctx
->program
->needs_exact
= true;
5876 ctx
->block
->instructions
.emplace_back(std::move(store
));
5880 assert(data
.type() == RegType::vgpr
);
5881 Temp coords
= get_image_coords(ctx
, instr
, type
);
5882 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5884 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5885 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5887 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5888 store
->operands
[0] = Operand(resource
);
5889 store
->operands
[1] = Operand(data
);
5890 store
->operands
[2] = Operand(coords
);
5893 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5894 store
->dmask
= (1 << data
.size()) - 1;
5896 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5897 store
->disable_wqm
= true;
5898 store
->barrier
= barrier_image
;
5899 ctx
->program
->needs_exact
= true;
5900 ctx
->block
->instructions
.emplace_back(std::move(store
));
5904 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5906 /* return the previous value if dest is ever used */
5907 bool return_previous
= false;
5908 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5909 return_previous
= true;
5912 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5913 return_previous
= true;
5917 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5918 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5919 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5920 bool is_array
= glsl_sampler_type_is_array(type
);
5921 Builder
bld(ctx
->program
, ctx
->block
);
5923 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5924 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5926 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5927 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5929 aco_opcode buf_op
, image_op
;
5930 switch (instr
->intrinsic
) {
5931 case nir_intrinsic_image_deref_atomic_add
:
5932 buf_op
= aco_opcode::buffer_atomic_add
;
5933 image_op
= aco_opcode::image_atomic_add
;
5935 case nir_intrinsic_image_deref_atomic_umin
:
5936 buf_op
= aco_opcode::buffer_atomic_umin
;
5937 image_op
= aco_opcode::image_atomic_umin
;
5939 case nir_intrinsic_image_deref_atomic_imin
:
5940 buf_op
= aco_opcode::buffer_atomic_smin
;
5941 image_op
= aco_opcode::image_atomic_smin
;
5943 case nir_intrinsic_image_deref_atomic_umax
:
5944 buf_op
= aco_opcode::buffer_atomic_umax
;
5945 image_op
= aco_opcode::image_atomic_umax
;
5947 case nir_intrinsic_image_deref_atomic_imax
:
5948 buf_op
= aco_opcode::buffer_atomic_smax
;
5949 image_op
= aco_opcode::image_atomic_smax
;
5951 case nir_intrinsic_image_deref_atomic_and
:
5952 buf_op
= aco_opcode::buffer_atomic_and
;
5953 image_op
= aco_opcode::image_atomic_and
;
5955 case nir_intrinsic_image_deref_atomic_or
:
5956 buf_op
= aco_opcode::buffer_atomic_or
;
5957 image_op
= aco_opcode::image_atomic_or
;
5959 case nir_intrinsic_image_deref_atomic_xor
:
5960 buf_op
= aco_opcode::buffer_atomic_xor
;
5961 image_op
= aco_opcode::image_atomic_xor
;
5963 case nir_intrinsic_image_deref_atomic_exchange
:
5964 buf_op
= aco_opcode::buffer_atomic_swap
;
5965 image_op
= aco_opcode::image_atomic_swap
;
5967 case nir_intrinsic_image_deref_atomic_comp_swap
:
5968 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5969 image_op
= aco_opcode::image_atomic_cmpswap
;
5972 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5975 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5977 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5978 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5979 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5980 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5981 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5982 mubuf
->operands
[0] = Operand(resource
);
5983 mubuf
->operands
[1] = Operand(vindex
);
5984 mubuf
->operands
[2] = Operand((uint32_t)0);
5985 mubuf
->operands
[3] = Operand(data
);
5986 if (return_previous
)
5987 mubuf
->definitions
[0] = Definition(dst
);
5989 mubuf
->idxen
= true;
5990 mubuf
->glc
= return_previous
;
5991 mubuf
->dlc
= false; /* Not needed for atomics */
5992 mubuf
->disable_wqm
= true;
5993 mubuf
->barrier
= barrier_image
;
5994 ctx
->program
->needs_exact
= true;
5995 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5999 Temp coords
= get_image_coords(ctx
, instr
, type
);
6000 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6001 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6002 mimg
->operands
[0] = Operand(resource
);
6003 mimg
->operands
[1] = Operand(data
);
6004 mimg
->operands
[2] = Operand(coords
);
6005 if (return_previous
)
6006 mimg
->definitions
[0] = Definition(dst
);
6007 mimg
->glc
= return_previous
;
6008 mimg
->dlc
= false; /* Not needed for atomics */
6009 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6010 mimg
->dmask
= (1 << data
.size()) - 1;
6012 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6013 mimg
->disable_wqm
= true;
6014 mimg
->barrier
= barrier_image
;
6015 ctx
->program
->needs_exact
= true;
6016 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6020 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6022 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6023 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6024 Builder
bld(ctx
->program
, ctx
->block
);
6026 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6028 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6029 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6031 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6032 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6034 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6035 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6037 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6038 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6039 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6040 if (dst
.type() == RegType::vgpr
)
6041 bld
.copy(Definition(dst
), shr_dst
);
6043 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6045 emit_extract_vector(ctx
, desc
, 2, dst
);
6049 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6051 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6052 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6053 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6054 bool is_array
= glsl_sampler_type_is_array(type
);
6055 Builder
bld(ctx
->program
, ctx
->block
);
6057 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6058 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6059 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6063 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6066 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6068 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6070 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6071 mimg
->operands
[0] = Operand(resource
);
6072 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6073 mimg
->operands
[2] = Operand(lod
);
6074 uint8_t& dmask
= mimg
->dmask
;
6075 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6076 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6077 mimg
->da
= glsl_sampler_type_is_array(type
);
6078 mimg
->can_reorder
= true;
6079 Definition
& def
= mimg
->definitions
[0];
6080 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6082 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6083 glsl_sampler_type_is_array(type
)) {
6085 assert(instr
->dest
.ssa
.num_components
== 3);
6086 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6087 def
= Definition(tmp
);
6088 emit_split_vector(ctx
, tmp
, 3);
6090 /* divide 3rd value by 6 by multiplying with magic number */
6091 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6092 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6094 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6095 emit_extract_vector(ctx
, tmp
, 0, v1
),
6096 emit_extract_vector(ctx
, tmp
, 1, v1
),
6099 } else if (ctx
->options
->chip_class
== GFX9
&&
6100 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6101 glsl_sampler_type_is_array(type
)) {
6102 assert(instr
->dest
.ssa
.num_components
== 2);
6103 def
= Definition(dst
);
6106 def
= Definition(dst
);
6109 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6112 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6114 Builder
bld(ctx
->program
, ctx
->block
);
6115 unsigned num_components
= instr
->num_components
;
6117 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6118 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6119 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6121 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6122 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6123 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6124 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6127 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6129 Builder
bld(ctx
->program
, ctx
->block
);
6130 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6131 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6132 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6133 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6135 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6136 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6138 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
6139 ctx
->options
->chip_class
>= GFX8
&&
6140 elem_size_bytes
>= 4;
6142 offset
= bld
.as_uniform(offset
);
6143 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6145 unsigned write_count
= 0;
6146 Temp write_datas
[32];
6147 unsigned offsets
[32];
6148 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6149 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6151 for (unsigned i
= 0; i
< write_count
; i
++) {
6152 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6153 if (smem
&& ctx
->stage
== fragment_fs
)
6154 op
= aco_opcode::p_fs_buffer_store_smem
;
6157 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6158 store
->operands
[0] = Operand(rsrc
);
6160 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6161 offset
, Operand(offsets
[i
]));
6162 store
->operands
[1] = Operand(off
);
6164 store
->operands
[1] = Operand(offset
);
6166 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6167 store
->operands
[1].setFixed(m0
);
6168 store
->operands
[2] = Operand(write_datas
[i
]);
6169 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6171 store
->disable_wqm
= true;
6172 store
->barrier
= barrier_buffer
;
6173 ctx
->block
->instructions
.emplace_back(std::move(store
));
6174 ctx
->program
->wb_smem_l1_on_end
= true;
6175 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6176 ctx
->block
->kind
|= block_kind_needs_lowering
;
6177 ctx
->program
->needs_exact
= true;
6180 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6181 store
->operands
[0] = Operand(rsrc
);
6182 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6183 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6184 store
->operands
[3] = Operand(write_datas
[i
]);
6185 store
->offset
= offsets
[i
];
6186 store
->offen
= (offset
.type() == RegType::vgpr
);
6187 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6189 store
->disable_wqm
= true;
6190 store
->barrier
= barrier_buffer
;
6191 ctx
->program
->needs_exact
= true;
6192 ctx
->block
->instructions
.emplace_back(std::move(store
));
6197 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6199 /* return the previous value if dest is ever used */
6200 bool return_previous
= false;
6201 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6202 return_previous
= true;
6205 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6206 return_previous
= true;
6210 Builder
bld(ctx
->program
, ctx
->block
);
6211 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6213 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6214 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6215 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6217 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6218 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6219 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6221 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6223 aco_opcode op32
, op64
;
6224 switch (instr
->intrinsic
) {
6225 case nir_intrinsic_ssbo_atomic_add
:
6226 op32
= aco_opcode::buffer_atomic_add
;
6227 op64
= aco_opcode::buffer_atomic_add_x2
;
6229 case nir_intrinsic_ssbo_atomic_imin
:
6230 op32
= aco_opcode::buffer_atomic_smin
;
6231 op64
= aco_opcode::buffer_atomic_smin_x2
;
6233 case nir_intrinsic_ssbo_atomic_umin
:
6234 op32
= aco_opcode::buffer_atomic_umin
;
6235 op64
= aco_opcode::buffer_atomic_umin_x2
;
6237 case nir_intrinsic_ssbo_atomic_imax
:
6238 op32
= aco_opcode::buffer_atomic_smax
;
6239 op64
= aco_opcode::buffer_atomic_smax_x2
;
6241 case nir_intrinsic_ssbo_atomic_umax
:
6242 op32
= aco_opcode::buffer_atomic_umax
;
6243 op64
= aco_opcode::buffer_atomic_umax_x2
;
6245 case nir_intrinsic_ssbo_atomic_and
:
6246 op32
= aco_opcode::buffer_atomic_and
;
6247 op64
= aco_opcode::buffer_atomic_and_x2
;
6249 case nir_intrinsic_ssbo_atomic_or
:
6250 op32
= aco_opcode::buffer_atomic_or
;
6251 op64
= aco_opcode::buffer_atomic_or_x2
;
6253 case nir_intrinsic_ssbo_atomic_xor
:
6254 op32
= aco_opcode::buffer_atomic_xor
;
6255 op64
= aco_opcode::buffer_atomic_xor_x2
;
6257 case nir_intrinsic_ssbo_atomic_exchange
:
6258 op32
= aco_opcode::buffer_atomic_swap
;
6259 op64
= aco_opcode::buffer_atomic_swap_x2
;
6261 case nir_intrinsic_ssbo_atomic_comp_swap
:
6262 op32
= aco_opcode::buffer_atomic_cmpswap
;
6263 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6266 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6268 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6269 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6270 mubuf
->operands
[0] = Operand(rsrc
);
6271 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6272 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6273 mubuf
->operands
[3] = Operand(data
);
6274 if (return_previous
)
6275 mubuf
->definitions
[0] = Definition(dst
);
6277 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6278 mubuf
->glc
= return_previous
;
6279 mubuf
->dlc
= false; /* Not needed for atomics */
6280 mubuf
->disable_wqm
= true;
6281 mubuf
->barrier
= barrier_buffer
;
6282 ctx
->program
->needs_exact
= true;
6283 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6286 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6288 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6289 Builder
bld(ctx
->program
, ctx
->block
);
6290 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6291 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6294 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6296 Builder
bld(ctx
->program
, ctx
->block
);
6297 unsigned num_components
= instr
->num_components
;
6298 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6300 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6301 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6302 num_components
, component_size
};
6303 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6304 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6305 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6306 info
.barrier
= barrier_buffer
;
6307 info
.can_reorder
= false;
6308 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6309 * it's safe to use SMEM */
6310 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6311 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6312 emit_global_load(ctx
, bld
, &info
);
6314 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6315 emit_smem_load(ctx
, bld
, &info
);
6319 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6321 Builder
bld(ctx
->program
, ctx
->block
);
6322 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6323 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6325 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6326 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6327 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6329 if (ctx
->options
->chip_class
>= GFX7
)
6330 addr
= as_vgpr(ctx
, addr
);
6332 unsigned write_count
= 0;
6333 Temp write_datas
[32];
6334 unsigned offsets
[32];
6335 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6336 16, &write_count
, write_datas
, offsets
);
6338 for (unsigned i
= 0; i
< write_count
; i
++) {
6339 if (ctx
->options
->chip_class
>= GFX7
) {
6340 unsigned offset
= offsets
[i
];
6341 Temp store_addr
= addr
;
6342 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6343 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6344 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6345 Temp carry
= bld
.tmp(bld
.lm
);
6346 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6348 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6349 Operand(offset
), addr0
);
6350 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6352 carry
).def(1).setHint(vcc
);
6354 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6359 bool global
= ctx
->options
->chip_class
>= GFX9
;
6361 switch (write_datas
[i
].bytes()) {
6363 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6366 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6369 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6372 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6375 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6378 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6381 unreachable("store_global not implemented for this size.");
6384 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6385 flat
->operands
[0] = Operand(store_addr
);
6386 flat
->operands
[1] = Operand(s1
);
6387 flat
->operands
[2] = Operand(write_datas
[i
]);
6390 flat
->offset
= offset
;
6391 flat
->disable_wqm
= true;
6392 flat
->barrier
= barrier_buffer
;
6393 ctx
->program
->needs_exact
= true;
6394 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6396 assert(ctx
->options
->chip_class
== GFX6
);
6398 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6400 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6402 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6403 mubuf
->operands
[0] = Operand(rsrc
);
6404 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6405 mubuf
->operands
[2] = Operand(0u);
6406 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6409 mubuf
->offset
= offsets
[i
];
6410 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6411 mubuf
->disable_wqm
= true;
6412 mubuf
->barrier
= barrier_buffer
;
6413 ctx
->program
->needs_exact
= true;
6414 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6419 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6421 /* return the previous value if dest is ever used */
6422 bool return_previous
= false;
6423 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6424 return_previous
= true;
6427 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6428 return_previous
= true;
6432 Builder
bld(ctx
->program
, ctx
->block
);
6433 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6434 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6436 if (ctx
->options
->chip_class
>= GFX7
)
6437 addr
= as_vgpr(ctx
, addr
);
6439 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6440 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6441 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6443 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6445 aco_opcode op32
, op64
;
6447 if (ctx
->options
->chip_class
>= GFX7
) {
6448 bool global
= ctx
->options
->chip_class
>= GFX9
;
6449 switch (instr
->intrinsic
) {
6450 case nir_intrinsic_global_atomic_add
:
6451 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6452 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6454 case nir_intrinsic_global_atomic_imin
:
6455 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6456 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6458 case nir_intrinsic_global_atomic_umin
:
6459 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6460 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6462 case nir_intrinsic_global_atomic_imax
:
6463 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6464 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6466 case nir_intrinsic_global_atomic_umax
:
6467 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6468 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6470 case nir_intrinsic_global_atomic_and
:
6471 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6472 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6474 case nir_intrinsic_global_atomic_or
:
6475 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6476 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6478 case nir_intrinsic_global_atomic_xor
:
6479 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6480 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6482 case nir_intrinsic_global_atomic_exchange
:
6483 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6484 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6486 case nir_intrinsic_global_atomic_comp_swap
:
6487 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6488 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6491 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6494 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6495 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6496 flat
->operands
[0] = Operand(addr
);
6497 flat
->operands
[1] = Operand(s1
);
6498 flat
->operands
[2] = Operand(data
);
6499 if (return_previous
)
6500 flat
->definitions
[0] = Definition(dst
);
6501 flat
->glc
= return_previous
;
6502 flat
->dlc
= false; /* Not needed for atomics */
6504 flat
->disable_wqm
= true;
6505 flat
->barrier
= barrier_buffer
;
6506 ctx
->program
->needs_exact
= true;
6507 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6509 assert(ctx
->options
->chip_class
== GFX6
);
6511 switch (instr
->intrinsic
) {
6512 case nir_intrinsic_global_atomic_add
:
6513 op32
= aco_opcode::buffer_atomic_add
;
6514 op64
= aco_opcode::buffer_atomic_add_x2
;
6516 case nir_intrinsic_global_atomic_imin
:
6517 op32
= aco_opcode::buffer_atomic_smin
;
6518 op64
= aco_opcode::buffer_atomic_smin_x2
;
6520 case nir_intrinsic_global_atomic_umin
:
6521 op32
= aco_opcode::buffer_atomic_umin
;
6522 op64
= aco_opcode::buffer_atomic_umin_x2
;
6524 case nir_intrinsic_global_atomic_imax
:
6525 op32
= aco_opcode::buffer_atomic_smax
;
6526 op64
= aco_opcode::buffer_atomic_smax_x2
;
6528 case nir_intrinsic_global_atomic_umax
:
6529 op32
= aco_opcode::buffer_atomic_umax
;
6530 op64
= aco_opcode::buffer_atomic_umax_x2
;
6532 case nir_intrinsic_global_atomic_and
:
6533 op32
= aco_opcode::buffer_atomic_and
;
6534 op64
= aco_opcode::buffer_atomic_and_x2
;
6536 case nir_intrinsic_global_atomic_or
:
6537 op32
= aco_opcode::buffer_atomic_or
;
6538 op64
= aco_opcode::buffer_atomic_or_x2
;
6540 case nir_intrinsic_global_atomic_xor
:
6541 op32
= aco_opcode::buffer_atomic_xor
;
6542 op64
= aco_opcode::buffer_atomic_xor_x2
;
6544 case nir_intrinsic_global_atomic_exchange
:
6545 op32
= aco_opcode::buffer_atomic_swap
;
6546 op64
= aco_opcode::buffer_atomic_swap_x2
;
6548 case nir_intrinsic_global_atomic_comp_swap
:
6549 op32
= aco_opcode::buffer_atomic_cmpswap
;
6550 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6553 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6556 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6558 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6560 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6561 mubuf
->operands
[0] = Operand(rsrc
);
6562 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6563 mubuf
->operands
[2] = Operand(0u);
6564 mubuf
->operands
[3] = Operand(data
);
6565 if (return_previous
)
6566 mubuf
->definitions
[0] = Definition(dst
);
6567 mubuf
->glc
= return_previous
;
6570 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6571 mubuf
->disable_wqm
= true;
6572 mubuf
->barrier
= barrier_buffer
;
6573 ctx
->program
->needs_exact
= true;
6574 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6578 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6579 Builder
bld(ctx
->program
, ctx
->block
);
6580 switch(instr
->intrinsic
) {
6581 case nir_intrinsic_group_memory_barrier
:
6582 case nir_intrinsic_memory_barrier
:
6583 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6585 case nir_intrinsic_memory_barrier_buffer
:
6586 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6588 case nir_intrinsic_memory_barrier_image
:
6589 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6591 case nir_intrinsic_memory_barrier_tcs_patch
:
6592 case nir_intrinsic_memory_barrier_shared
:
6593 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6596 unreachable("Unimplemented memory barrier intrinsic");
6601 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6603 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6604 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6605 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6606 Builder
bld(ctx
->program
, ctx
->block
);
6608 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6609 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6610 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6613 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6615 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6616 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6617 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6618 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6620 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6621 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6624 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6626 unsigned offset
= nir_intrinsic_base(instr
);
6627 Builder
bld(ctx
->program
, ctx
->block
);
6628 Operand m
= load_lds_size_m0(bld
);
6629 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6630 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6632 unsigned num_operands
= 3;
6633 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6634 switch(instr
->intrinsic
) {
6635 case nir_intrinsic_shared_atomic_add
:
6636 op32
= aco_opcode::ds_add_u32
;
6637 op64
= aco_opcode::ds_add_u64
;
6638 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6639 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6641 case nir_intrinsic_shared_atomic_imin
:
6642 op32
= aco_opcode::ds_min_i32
;
6643 op64
= aco_opcode::ds_min_i64
;
6644 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6645 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6647 case nir_intrinsic_shared_atomic_umin
:
6648 op32
= aco_opcode::ds_min_u32
;
6649 op64
= aco_opcode::ds_min_u64
;
6650 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6651 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6653 case nir_intrinsic_shared_atomic_imax
:
6654 op32
= aco_opcode::ds_max_i32
;
6655 op64
= aco_opcode::ds_max_i64
;
6656 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6657 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6659 case nir_intrinsic_shared_atomic_umax
:
6660 op32
= aco_opcode::ds_max_u32
;
6661 op64
= aco_opcode::ds_max_u64
;
6662 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6663 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6665 case nir_intrinsic_shared_atomic_and
:
6666 op32
= aco_opcode::ds_and_b32
;
6667 op64
= aco_opcode::ds_and_b64
;
6668 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6669 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6671 case nir_intrinsic_shared_atomic_or
:
6672 op32
= aco_opcode::ds_or_b32
;
6673 op64
= aco_opcode::ds_or_b64
;
6674 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6675 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6677 case nir_intrinsic_shared_atomic_xor
:
6678 op32
= aco_opcode::ds_xor_b32
;
6679 op64
= aco_opcode::ds_xor_b64
;
6680 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6681 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6683 case nir_intrinsic_shared_atomic_exchange
:
6684 op32
= aco_opcode::ds_write_b32
;
6685 op64
= aco_opcode::ds_write_b64
;
6686 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6687 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6689 case nir_intrinsic_shared_atomic_comp_swap
:
6690 op32
= aco_opcode::ds_cmpst_b32
;
6691 op64
= aco_opcode::ds_cmpst_b64
;
6692 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6693 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6697 unreachable("Unhandled shared atomic intrinsic");
6700 /* return the previous value if dest is ever used */
6701 bool return_previous
= false;
6702 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6703 return_previous
= true;
6706 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6707 return_previous
= true;
6712 if (data
.size() == 1) {
6713 assert(instr
->dest
.ssa
.bit_size
== 32);
6714 op
= return_previous
? op32_rtn
: op32
;
6716 assert(instr
->dest
.ssa
.bit_size
== 64);
6717 op
= return_previous
? op64_rtn
: op64
;
6720 if (offset
> 65535) {
6721 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6725 aco_ptr
<DS_instruction
> ds
;
6726 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6727 ds
->operands
[0] = Operand(address
);
6728 ds
->operands
[1] = Operand(data
);
6729 if (num_operands
== 4)
6730 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6731 ds
->operands
[num_operands
- 1] = m
;
6732 ds
->offset0
= offset
;
6733 if (return_previous
)
6734 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6735 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6738 Temp
get_scratch_resource(isel_context
*ctx
)
6740 Builder
bld(ctx
->program
, ctx
->block
);
6741 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6742 if (ctx
->stage
!= compute_cs
)
6743 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6745 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6746 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6748 if (ctx
->program
->chip_class
>= GFX10
) {
6749 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6750 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6751 S_008F0C_RESOURCE_LEVEL(1);
6752 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6753 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6754 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6757 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6758 if (ctx
->program
->chip_class
<= GFX8
)
6759 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6761 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6764 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6765 Builder
bld(ctx
->program
, ctx
->block
);
6766 Temp rsrc
= get_scratch_resource(ctx
);
6767 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6768 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6770 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6771 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6772 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6773 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6774 info
.swizzle_component_size
= 16;
6775 info
.can_reorder
= false;
6776 info
.soffset
= ctx
->program
->scratch_offset
;
6777 emit_mubuf_load(ctx
, bld
, &info
);
6780 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6781 Builder
bld(ctx
->program
, ctx
->block
);
6782 Temp rsrc
= get_scratch_resource(ctx
);
6783 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6784 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6786 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6787 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6789 unsigned write_count
= 0;
6790 Temp write_datas
[32];
6791 unsigned offsets
[32];
6792 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6793 16, &write_count
, write_datas
, offsets
);
6795 for (unsigned i
= 0; i
< write_count
; i
++) {
6796 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6797 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6801 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6802 uint8_t log2_ps_iter_samples
;
6803 if (ctx
->program
->info
->ps
.force_persample
) {
6804 log2_ps_iter_samples
=
6805 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6807 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6810 /* The bit pattern matches that used by fixed function fragment
6812 static const unsigned ps_iter_masks
[] = {
6813 0xffff, /* not used */
6819 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6821 Builder
bld(ctx
->program
, ctx
->block
);
6823 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6824 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6825 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6826 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6827 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6828 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6831 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6832 Builder
bld(ctx
->program
, ctx
->block
);
6834 unsigned stream
= nir_intrinsic_stream_id(instr
);
6835 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6836 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6837 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6840 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6842 unsigned num_components
=
6843 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6844 assert(num_components
);
6846 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6847 unsigned stream_offset
= 0;
6848 for (unsigned i
= 0; i
< stream
; i
++) {
6849 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6850 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6853 /* Limit on the stride field for <= GFX7. */
6854 assert(stride
< (1 << 14));
6856 Temp gsvs_dwords
[4];
6857 for (unsigned i
= 0; i
< 4; i
++)
6858 gsvs_dwords
[i
] = bld
.tmp(s1
);
6859 bld
.pseudo(aco_opcode::p_split_vector
,
6860 Definition(gsvs_dwords
[0]),
6861 Definition(gsvs_dwords
[1]),
6862 Definition(gsvs_dwords
[2]),
6863 Definition(gsvs_dwords
[3]),
6866 if (stream_offset
) {
6867 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6869 Temp carry
= bld
.tmp(s1
);
6870 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6871 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6874 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6875 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6877 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6878 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6880 unsigned offset
= 0;
6881 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6882 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6885 for (unsigned j
= 0; j
< 4; j
++) {
6886 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6889 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6890 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6891 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6892 if (const_offset
>= 4096u) {
6893 if (vaddr_offset
.isUndefined())
6894 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6896 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6897 const_offset
%= 4096u;
6900 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6901 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6902 mtbuf
->operands
[1] = vaddr_offset
;
6903 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6904 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6905 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6906 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6907 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6908 mtbuf
->offset
= const_offset
;
6911 mtbuf
->barrier
= barrier_gs_data
;
6912 mtbuf
->can_reorder
= true;
6913 bld
.insert(std::move(mtbuf
));
6916 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6919 /* outputs for the next vertex are undefined and keeping them around can
6920 * create invalid IR with control flow */
6921 ctx
->outputs
.mask
[i
] = 0;
6924 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6927 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6929 Builder
bld(ctx
->program
, ctx
->block
);
6931 if (cluster_size
== 1) {
6933 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6934 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6935 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6936 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6937 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6938 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6939 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6940 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6941 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6942 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6943 //subgroupAnd(val) -> (exec & ~val) == 0
6944 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6945 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6946 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6947 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6948 //subgroupOr(val) -> (val & exec) != 0
6949 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6950 return bool_to_vector_condition(ctx
, tmp
);
6951 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6952 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6953 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6954 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6955 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6956 return bool_to_vector_condition(ctx
, tmp
);
6958 //subgroupClustered{And,Or,Xor}(val, n) ->
6959 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6960 //cluster_offset = ~(n - 1) & lane_id
6961 //cluster_mask = ((1 << n) - 1)
6962 //subgroupClusteredAnd():
6963 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6964 //subgroupClusteredOr():
6965 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6966 //subgroupClusteredXor():
6967 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6968 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6969 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6972 if (op
== nir_op_iand
)
6973 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6975 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6977 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6979 if (ctx
->program
->chip_class
<= GFX7
)
6980 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6981 else if (ctx
->program
->wave_size
== 64)
6982 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6984 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6985 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6986 if (cluster_mask
!= 0xffffffff)
6987 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6989 Definition cmp_def
= Definition();
6990 if (op
== nir_op_iand
) {
6991 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6992 } else if (op
== nir_op_ior
) {
6993 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6994 } else if (op
== nir_op_ixor
) {
6995 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6996 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6997 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6999 cmp_def
.setHint(vcc
);
7000 return cmp_def
.getTemp();
7004 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7006 Builder
bld(ctx
->program
, ctx
->block
);
7008 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7009 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7010 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7012 if (op
== nir_op_iand
)
7013 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7015 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7017 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7018 Temp lo
= lohi
.def(0).getTemp();
7019 Temp hi
= lohi
.def(1).getTemp();
7020 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7022 Definition cmp_def
= Definition();
7023 if (op
== nir_op_iand
)
7024 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7025 else if (op
== nir_op_ior
)
7026 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7027 else if (op
== nir_op_ixor
)
7028 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7029 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7030 cmp_def
.setHint(vcc
);
7031 return cmp_def
.getTemp();
7034 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7036 Builder
bld(ctx
->program
, ctx
->block
);
7038 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7039 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7040 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7041 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7042 if (op
== nir_op_iand
)
7043 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7044 else if (op
== nir_op_ior
)
7045 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7046 else if (op
== nir_op_ixor
)
7047 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7053 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7055 Builder
bld(ctx
->program
, ctx
->block
);
7056 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7057 if (src
.regClass().type() == RegType::vgpr
) {
7058 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7059 } else if (src
.regClass() == s1
) {
7060 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7061 } else if (src
.regClass() == s2
) {
7062 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7064 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7065 nir_print_instr(&instr
->instr
, stderr
);
7066 fprintf(stderr
, "\n");
7070 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7072 Builder
bld(ctx
->program
, ctx
->block
);
7073 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7074 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7075 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7077 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7078 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7079 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7080 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7083 if (ctx
->program
->chip_class
>= GFX8
) {
7084 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7085 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7086 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7087 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7088 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7089 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7091 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7092 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7093 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7094 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7095 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7096 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7097 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7098 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7099 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7100 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7103 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7104 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7105 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7106 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7107 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7108 Temp wqm1
= bld
.tmp(v1
);
7109 emit_wqm(ctx
, tmp1
, wqm1
, true);
7110 Temp wqm2
= bld
.tmp(v1
);
7111 emit_wqm(ctx
, tmp2
, wqm2
, true);
7112 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7116 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7118 Builder
bld(ctx
->program
, ctx
->block
);
7119 switch(instr
->intrinsic
) {
7120 case nir_intrinsic_load_barycentric_sample
:
7121 case nir_intrinsic_load_barycentric_pixel
:
7122 case nir_intrinsic_load_barycentric_centroid
: {
7123 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7124 Temp bary
= Temp(0, s2
);
7126 case INTERP_MODE_SMOOTH
:
7127 case INTERP_MODE_NONE
:
7128 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7129 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7130 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7131 bary
= ctx
->persp_centroid
;
7132 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7133 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7135 case INTERP_MODE_NOPERSPECTIVE
:
7136 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7137 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7138 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7139 bary
= ctx
->linear_centroid
;
7140 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7141 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7146 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7147 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7148 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7149 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7150 Operand(p1
), Operand(p2
));
7151 emit_split_vector(ctx
, dst
, 2);
7154 case nir_intrinsic_load_barycentric_model
: {
7155 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7157 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7158 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7159 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7160 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7161 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7162 Operand(p1
), Operand(p2
), Operand(p3
));
7163 emit_split_vector(ctx
, dst
, 3);
7166 case nir_intrinsic_load_barycentric_at_sample
: {
7167 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7168 switch (ctx
->options
->key
.fs
.num_samples
) {
7169 case 2: sample_pos_offset
+= 1 << 3; break;
7170 case 4: sample_pos_offset
+= 3 << 3; break;
7171 case 8: sample_pos_offset
+= 7 << 3; break;
7175 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7176 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7177 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7178 if (addr
.type() == RegType::sgpr
) {
7181 sample_pos_offset
+= const_addr
->u32
<< 3;
7182 offset
= Operand(sample_pos_offset
);
7183 } else if (ctx
->options
->chip_class
>= GFX9
) {
7184 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7186 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7187 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7190 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7191 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7193 } else if (ctx
->options
->chip_class
>= GFX9
) {
7194 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7195 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7196 } else if (ctx
->options
->chip_class
>= GFX7
) {
7197 /* addr += private_segment_buffer + sample_pos_offset */
7198 Temp tmp0
= bld
.tmp(s1
);
7199 Temp tmp1
= bld
.tmp(s1
);
7200 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7201 Definition scc_tmp
= bld
.def(s1
, scc
);
7202 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7203 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7204 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7205 Temp pck0
= bld
.tmp(v1
);
7206 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7207 tmp1
= as_vgpr(ctx
, tmp1
);
7208 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7209 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7211 /* sample_pos = flat_load_dwordx2 addr */
7212 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7214 assert(ctx
->options
->chip_class
== GFX6
);
7216 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7217 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7218 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7220 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7221 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7223 sample_pos
= bld
.tmp(v2
);
7225 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7226 load
->definitions
[0] = Definition(sample_pos
);
7227 load
->operands
[0] = Operand(rsrc
);
7228 load
->operands
[1] = Operand(addr
);
7229 load
->operands
[2] = Operand(0u);
7230 load
->offset
= sample_pos_offset
;
7232 load
->addr64
= true;
7235 load
->disable_wqm
= false;
7236 load
->barrier
= barrier_none
;
7237 load
->can_reorder
= true;
7238 ctx
->block
->instructions
.emplace_back(std::move(load
));
7241 /* sample_pos -= 0.5 */
7242 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7243 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7244 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7245 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7246 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7248 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7251 case nir_intrinsic_load_barycentric_at_offset
: {
7252 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7253 RegClass rc
= RegClass(offset
.type(), 1);
7254 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7255 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7256 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7259 case nir_intrinsic_load_front_face
: {
7260 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7261 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7264 case nir_intrinsic_load_view_index
: {
7265 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7266 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7267 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7273 case nir_intrinsic_load_layer_id
: {
7274 unsigned idx
= nir_intrinsic_base(instr
);
7275 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7276 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7279 case nir_intrinsic_load_frag_coord
: {
7280 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7283 case nir_intrinsic_load_sample_pos
: {
7284 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7285 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7286 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7287 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7288 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7291 case nir_intrinsic_load_tess_coord
:
7292 visit_load_tess_coord(ctx
, instr
);
7294 case nir_intrinsic_load_interpolated_input
:
7295 visit_load_interpolated_input(ctx
, instr
);
7297 case nir_intrinsic_store_output
:
7298 visit_store_output(ctx
, instr
);
7300 case nir_intrinsic_load_input
:
7301 case nir_intrinsic_load_input_vertex
:
7302 visit_load_input(ctx
, instr
);
7304 case nir_intrinsic_load_output
:
7305 visit_load_output(ctx
, instr
);
7307 case nir_intrinsic_load_per_vertex_input
:
7308 visit_load_per_vertex_input(ctx
, instr
);
7310 case nir_intrinsic_load_per_vertex_output
:
7311 visit_load_per_vertex_output(ctx
, instr
);
7313 case nir_intrinsic_store_per_vertex_output
:
7314 visit_store_per_vertex_output(ctx
, instr
);
7316 case nir_intrinsic_load_ubo
:
7317 visit_load_ubo(ctx
, instr
);
7319 case nir_intrinsic_load_push_constant
:
7320 visit_load_push_constant(ctx
, instr
);
7322 case nir_intrinsic_load_constant
:
7323 visit_load_constant(ctx
, instr
);
7325 case nir_intrinsic_vulkan_resource_index
:
7326 visit_load_resource(ctx
, instr
);
7328 case nir_intrinsic_discard
:
7329 visit_discard(ctx
, instr
);
7331 case nir_intrinsic_discard_if
:
7332 visit_discard_if(ctx
, instr
);
7334 case nir_intrinsic_load_shared
:
7335 visit_load_shared(ctx
, instr
);
7337 case nir_intrinsic_store_shared
:
7338 visit_store_shared(ctx
, instr
);
7340 case nir_intrinsic_shared_atomic_add
:
7341 case nir_intrinsic_shared_atomic_imin
:
7342 case nir_intrinsic_shared_atomic_umin
:
7343 case nir_intrinsic_shared_atomic_imax
:
7344 case nir_intrinsic_shared_atomic_umax
:
7345 case nir_intrinsic_shared_atomic_and
:
7346 case nir_intrinsic_shared_atomic_or
:
7347 case nir_intrinsic_shared_atomic_xor
:
7348 case nir_intrinsic_shared_atomic_exchange
:
7349 case nir_intrinsic_shared_atomic_comp_swap
:
7350 visit_shared_atomic(ctx
, instr
);
7352 case nir_intrinsic_image_deref_load
:
7353 visit_image_load(ctx
, instr
);
7355 case nir_intrinsic_image_deref_store
:
7356 visit_image_store(ctx
, instr
);
7358 case nir_intrinsic_image_deref_atomic_add
:
7359 case nir_intrinsic_image_deref_atomic_umin
:
7360 case nir_intrinsic_image_deref_atomic_imin
:
7361 case nir_intrinsic_image_deref_atomic_umax
:
7362 case nir_intrinsic_image_deref_atomic_imax
:
7363 case nir_intrinsic_image_deref_atomic_and
:
7364 case nir_intrinsic_image_deref_atomic_or
:
7365 case nir_intrinsic_image_deref_atomic_xor
:
7366 case nir_intrinsic_image_deref_atomic_exchange
:
7367 case nir_intrinsic_image_deref_atomic_comp_swap
:
7368 visit_image_atomic(ctx
, instr
);
7370 case nir_intrinsic_image_deref_size
:
7371 visit_image_size(ctx
, instr
);
7373 case nir_intrinsic_load_ssbo
:
7374 visit_load_ssbo(ctx
, instr
);
7376 case nir_intrinsic_store_ssbo
:
7377 visit_store_ssbo(ctx
, instr
);
7379 case nir_intrinsic_load_global
:
7380 visit_load_global(ctx
, instr
);
7382 case nir_intrinsic_store_global
:
7383 visit_store_global(ctx
, instr
);
7385 case nir_intrinsic_global_atomic_add
:
7386 case nir_intrinsic_global_atomic_imin
:
7387 case nir_intrinsic_global_atomic_umin
:
7388 case nir_intrinsic_global_atomic_imax
:
7389 case nir_intrinsic_global_atomic_umax
:
7390 case nir_intrinsic_global_atomic_and
:
7391 case nir_intrinsic_global_atomic_or
:
7392 case nir_intrinsic_global_atomic_xor
:
7393 case nir_intrinsic_global_atomic_exchange
:
7394 case nir_intrinsic_global_atomic_comp_swap
:
7395 visit_global_atomic(ctx
, instr
);
7397 case nir_intrinsic_ssbo_atomic_add
:
7398 case nir_intrinsic_ssbo_atomic_imin
:
7399 case nir_intrinsic_ssbo_atomic_umin
:
7400 case nir_intrinsic_ssbo_atomic_imax
:
7401 case nir_intrinsic_ssbo_atomic_umax
:
7402 case nir_intrinsic_ssbo_atomic_and
:
7403 case nir_intrinsic_ssbo_atomic_or
:
7404 case nir_intrinsic_ssbo_atomic_xor
:
7405 case nir_intrinsic_ssbo_atomic_exchange
:
7406 case nir_intrinsic_ssbo_atomic_comp_swap
:
7407 visit_atomic_ssbo(ctx
, instr
);
7409 case nir_intrinsic_load_scratch
:
7410 visit_load_scratch(ctx
, instr
);
7412 case nir_intrinsic_store_scratch
:
7413 visit_store_scratch(ctx
, instr
);
7415 case nir_intrinsic_get_buffer_size
:
7416 visit_get_buffer_size(ctx
, instr
);
7418 case nir_intrinsic_control_barrier
: {
7419 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7420 /* GFX6 only (thanks to a hw bug workaround):
7421 * The real barrier instruction isn’t needed, because an entire patch
7422 * always fits into a single wave.
7427 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7428 bld
.sopp(aco_opcode::s_barrier
);
7432 case nir_intrinsic_memory_barrier_tcs_patch
:
7433 case nir_intrinsic_group_memory_barrier
:
7434 case nir_intrinsic_memory_barrier
:
7435 case nir_intrinsic_memory_barrier_buffer
:
7436 case nir_intrinsic_memory_barrier_image
:
7437 case nir_intrinsic_memory_barrier_shared
:
7438 emit_memory_barrier(ctx
, instr
);
7440 case nir_intrinsic_load_num_work_groups
: {
7441 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7442 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7443 emit_split_vector(ctx
, dst
, 3);
7446 case nir_intrinsic_load_local_invocation_id
: {
7447 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7448 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7449 emit_split_vector(ctx
, dst
, 3);
7452 case nir_intrinsic_load_work_group_id
: {
7453 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7454 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7455 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7456 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7457 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7458 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7459 emit_split_vector(ctx
, dst
, 3);
7462 case nir_intrinsic_load_local_invocation_index
: {
7463 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7465 /* The tg_size bits [6:11] contain the subgroup id,
7466 * we need this multiplied by the wave size, and then OR the thread id to it.
7468 if (ctx
->program
->wave_size
== 64) {
7469 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7470 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7471 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7472 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7474 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7475 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7476 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7477 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7481 case nir_intrinsic_load_subgroup_id
: {
7482 if (ctx
->stage
== compute_cs
) {
7483 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7484 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7486 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7490 case nir_intrinsic_load_subgroup_invocation
: {
7491 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7494 case nir_intrinsic_load_num_subgroups
: {
7495 if (ctx
->stage
== compute_cs
)
7496 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7497 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7499 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7502 case nir_intrinsic_ballot
: {
7503 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7504 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7505 Definition tmp
= bld
.def(dst
.regClass());
7506 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7507 if (instr
->src
[0].ssa
->bit_size
== 1) {
7508 assert(src
.regClass() == bld
.lm
);
7509 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7510 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7511 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7512 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7513 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7515 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7516 nir_print_instr(&instr
->instr
, stderr
);
7517 fprintf(stderr
, "\n");
7519 if (dst
.size() != bld
.lm
.size()) {
7520 /* Wave32 with ballot size set to 64 */
7521 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7523 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7526 case nir_intrinsic_shuffle
:
7527 case nir_intrinsic_read_invocation
: {
7528 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7529 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7530 emit_uniform_subgroup(ctx
, instr
, src
);
7532 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7533 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7534 tid
= bld
.as_uniform(tid
);
7535 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7536 if (src
.regClass() == v1
) {
7537 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7538 } else if (src
.regClass() == v2
) {
7539 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7541 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7542 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7543 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7544 emit_split_vector(ctx
, dst
, 2);
7545 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7546 assert(src
.regClass() == bld
.lm
);
7547 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7548 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7549 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7550 assert(src
.regClass() == bld
.lm
);
7552 if (ctx
->program
->chip_class
<= GFX7
)
7553 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7554 else if (ctx
->program
->wave_size
== 64)
7555 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7557 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7558 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7559 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7560 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7563 nir_print_instr(&instr
->instr
, stderr
);
7564 fprintf(stderr
, "\n");
7569 case nir_intrinsic_load_sample_id
: {
7570 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7571 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7574 case nir_intrinsic_load_sample_mask_in
: {
7575 visit_load_sample_mask_in(ctx
, instr
);
7578 case nir_intrinsic_read_first_invocation
: {
7579 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7580 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7581 if (src
.regClass() == v1
) {
7583 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7585 } else if (src
.regClass() == v2
) {
7586 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7587 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7588 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7589 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7591 emit_split_vector(ctx
, dst
, 2);
7592 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7593 assert(src
.regClass() == bld
.lm
);
7594 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7595 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7596 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7597 } else if (src
.regClass() == s1
) {
7598 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7599 } else if (src
.regClass() == s2
) {
7600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7602 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7603 nir_print_instr(&instr
->instr
, stderr
);
7604 fprintf(stderr
, "\n");
7608 case nir_intrinsic_vote_all
: {
7609 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7610 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7611 assert(src
.regClass() == bld
.lm
);
7612 assert(dst
.regClass() == bld
.lm
);
7614 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7615 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7616 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7619 case nir_intrinsic_vote_any
: {
7620 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7621 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7622 assert(src
.regClass() == bld
.lm
);
7623 assert(dst
.regClass() == bld
.lm
);
7625 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7626 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7629 case nir_intrinsic_reduce
:
7630 case nir_intrinsic_inclusive_scan
:
7631 case nir_intrinsic_exclusive_scan
: {
7632 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7633 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7634 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7635 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7636 nir_intrinsic_cluster_size(instr
) : 0;
7637 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7639 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7640 emit_uniform_subgroup(ctx
, instr
, src
);
7641 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7642 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7644 else if (op
== nir_op_iadd
)
7646 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7648 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7650 switch (instr
->intrinsic
) {
7651 case nir_intrinsic_reduce
:
7652 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7654 case nir_intrinsic_exclusive_scan
:
7655 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7657 case nir_intrinsic_inclusive_scan
:
7658 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7663 } else if (cluster_size
== 1) {
7664 bld
.copy(Definition(dst
), src
);
7666 src
= as_vgpr(ctx
, src
);
7670 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7685 unreachable("unknown reduction op");
7690 switch (instr
->intrinsic
) {
7691 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7692 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7693 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7695 unreachable("unknown reduce intrinsic");
7698 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7699 reduce
->operands
[0] = Operand(src
);
7700 // filled in by aco_reduce_assign.cpp, used internally as part of the
7702 assert(dst
.size() == 1 || dst
.size() == 2);
7703 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7704 reduce
->operands
[2] = Operand(v1
.as_linear());
7706 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7707 reduce
->definitions
[0] = Definition(tmp_dst
);
7708 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7709 reduce
->definitions
[2] = Definition();
7710 reduce
->definitions
[3] = Definition(scc
, s1
);
7711 reduce
->definitions
[4] = Definition();
7712 reduce
->reduce_op
= reduce_op
;
7713 reduce
->cluster_size
= cluster_size
;
7714 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7716 emit_wqm(ctx
, tmp_dst
, dst
);
7720 case nir_intrinsic_quad_broadcast
: {
7721 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7722 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7723 emit_uniform_subgroup(ctx
, instr
, src
);
7725 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7726 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7727 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7729 if (instr
->dest
.ssa
.bit_size
== 1) {
7730 assert(src
.regClass() == bld
.lm
);
7731 assert(dst
.regClass() == bld
.lm
);
7732 uint32_t half_mask
= 0x11111111u
<< lane
;
7733 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7734 Temp tmp
= bld
.tmp(bld
.lm
);
7735 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7736 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7737 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7738 emit_wqm(ctx
, tmp
, dst
);
7739 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7740 if (ctx
->program
->chip_class
>= GFX8
)
7741 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7743 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7744 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7745 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7746 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7747 if (ctx
->program
->chip_class
>= GFX8
) {
7748 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7749 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7751 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7752 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7754 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7755 emit_split_vector(ctx
, dst
, 2);
7757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7758 nir_print_instr(&instr
->instr
, stderr
);
7759 fprintf(stderr
, "\n");
7764 case nir_intrinsic_quad_swap_horizontal
:
7765 case nir_intrinsic_quad_swap_vertical
:
7766 case nir_intrinsic_quad_swap_diagonal
:
7767 case nir_intrinsic_quad_swizzle_amd
: {
7768 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7769 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7770 emit_uniform_subgroup(ctx
, instr
, src
);
7773 uint16_t dpp_ctrl
= 0;
7774 switch (instr
->intrinsic
) {
7775 case nir_intrinsic_quad_swap_horizontal
:
7776 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7778 case nir_intrinsic_quad_swap_vertical
:
7779 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7781 case nir_intrinsic_quad_swap_diagonal
:
7782 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7784 case nir_intrinsic_quad_swizzle_amd
:
7785 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7790 if (ctx
->program
->chip_class
< GFX8
)
7791 dpp_ctrl
|= (1 << 15);
7793 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7794 if (instr
->dest
.ssa
.bit_size
== 1) {
7795 assert(src
.regClass() == bld
.lm
);
7796 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7797 if (ctx
->program
->chip_class
>= GFX8
)
7798 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7800 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7801 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7802 emit_wqm(ctx
, tmp
, dst
);
7803 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7805 if (ctx
->program
->chip_class
>= GFX8
)
7806 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7808 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7809 emit_wqm(ctx
, tmp
, dst
);
7810 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7811 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7812 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7813 if (ctx
->program
->chip_class
>= GFX8
) {
7814 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7815 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7817 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7818 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7820 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7821 emit_split_vector(ctx
, dst
, 2);
7823 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7824 nir_print_instr(&instr
->instr
, stderr
);
7825 fprintf(stderr
, "\n");
7829 case nir_intrinsic_masked_swizzle_amd
: {
7830 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7831 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7832 emit_uniform_subgroup(ctx
, instr
, src
);
7835 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7836 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7837 if (dst
.regClass() == v1
) {
7839 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7841 } else if (dst
.regClass() == v2
) {
7842 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7844 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7845 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7846 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7847 emit_split_vector(ctx
, dst
, 2);
7849 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7850 nir_print_instr(&instr
->instr
, stderr
);
7851 fprintf(stderr
, "\n");
7855 case nir_intrinsic_write_invocation_amd
: {
7856 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7857 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7858 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7859 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7860 if (dst
.regClass() == v1
) {
7861 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7862 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7863 } else if (dst
.regClass() == v2
) {
7864 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7865 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7867 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7868 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7869 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7870 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7871 emit_split_vector(ctx
, dst
, 2);
7873 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7874 nir_print_instr(&instr
->instr
, stderr
);
7875 fprintf(stderr
, "\n");
7879 case nir_intrinsic_mbcnt_amd
: {
7880 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7881 RegClass rc
= RegClass(src
.type(), 1);
7882 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7883 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7884 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7885 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7886 emit_wqm(ctx
, wqm_tmp
, dst
);
7889 case nir_intrinsic_load_helper_invocation
: {
7890 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7891 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7892 ctx
->block
->kind
|= block_kind_needs_lowering
;
7893 ctx
->program
->needs_exact
= true;
7896 case nir_intrinsic_is_helper_invocation
: {
7897 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7898 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7899 ctx
->block
->kind
|= block_kind_needs_lowering
;
7900 ctx
->program
->needs_exact
= true;
7903 case nir_intrinsic_demote
:
7904 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7906 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7907 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7908 ctx
->block
->kind
|= block_kind_uses_demote
;
7909 ctx
->program
->needs_exact
= true;
7911 case nir_intrinsic_demote_if
: {
7912 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7913 assert(src
.regClass() == bld
.lm
);
7914 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7915 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7917 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7918 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7919 ctx
->block
->kind
|= block_kind_uses_demote
;
7920 ctx
->program
->needs_exact
= true;
7923 case nir_intrinsic_first_invocation
: {
7924 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7925 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7928 case nir_intrinsic_shader_clock
:
7929 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7930 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7932 case nir_intrinsic_load_vertex_id_zero_base
: {
7933 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7934 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7937 case nir_intrinsic_load_first_vertex
: {
7938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7939 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7942 case nir_intrinsic_load_base_instance
: {
7943 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7944 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7947 case nir_intrinsic_load_instance_id
: {
7948 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7949 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7952 case nir_intrinsic_load_draw_id
: {
7953 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7954 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7957 case nir_intrinsic_load_invocation_id
: {
7958 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7960 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7961 if (ctx
->options
->chip_class
>= GFX10
)
7962 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7964 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7965 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7966 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7967 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7969 unreachable("Unsupported stage for load_invocation_id");
7974 case nir_intrinsic_load_primitive_id
: {
7975 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7977 switch (ctx
->shader
->info
.stage
) {
7978 case MESA_SHADER_GEOMETRY
:
7979 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7981 case MESA_SHADER_TESS_CTRL
:
7982 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7984 case MESA_SHADER_TESS_EVAL
:
7985 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7988 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7993 case nir_intrinsic_load_patch_vertices_in
: {
7994 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7995 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7997 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7998 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8001 case nir_intrinsic_emit_vertex_with_counter
: {
8002 visit_emit_vertex_with_counter(ctx
, instr
);
8005 case nir_intrinsic_end_primitive_with_counter
: {
8006 unsigned stream
= nir_intrinsic_stream_id(instr
);
8007 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8010 case nir_intrinsic_set_vertex_count
: {
8011 /* unused, the HW keeps track of this for us */
8015 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8016 nir_print_instr(&instr
->instr
, stderr
);
8017 fprintf(stderr
, "\n");
8025 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8026 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8027 enum glsl_base_type
*stype
)
8029 nir_deref_instr
*texture_deref_instr
= NULL
;
8030 nir_deref_instr
*sampler_deref_instr
= NULL
;
8033 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8034 switch (instr
->src
[i
].src_type
) {
8035 case nir_tex_src_texture_deref
:
8036 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8038 case nir_tex_src_sampler_deref
:
8039 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8041 case nir_tex_src_plane
:
8042 plane
= nir_src_as_int(instr
->src
[i
].src
);
8049 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8051 if (!sampler_deref_instr
)
8052 sampler_deref_instr
= texture_deref_instr
;
8055 assert(instr
->op
!= nir_texop_txf_ms
&&
8056 instr
->op
!= nir_texop_samples_identical
);
8057 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8058 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8059 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8060 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8061 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8062 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8064 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8067 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8069 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8070 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8071 Builder
bld(ctx
->program
, ctx
->block
);
8073 /* to avoid unnecessary moves, we split and recombine sampler and image */
8074 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8075 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8076 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8077 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8078 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8079 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8080 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8081 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8083 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8084 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8085 img
[0], img
[1], img
[2], img
[3],
8086 img
[4], img
[5], img
[6], img
[7]);
8087 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8088 samp
[0], samp
[1], samp
[2], samp
[3]);
8091 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8092 instr
->op
== nir_texop_samples_identical
))
8093 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8096 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8097 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8099 Builder
bld(ctx
->program
, ctx
->block
);
8101 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8102 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8103 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8105 Operand
neg_one(0xbf800000u
);
8106 Operand
one(0x3f800000u
);
8107 Operand
two(0x40000000u
);
8108 Operand
four(0x40800000u
);
8110 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8111 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8112 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8114 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8115 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8116 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8117 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8120 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8121 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8122 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8124 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8127 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8128 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8129 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8132 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8133 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8135 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8136 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8139 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8141 Builder
bld(ctx
->program
, ctx
->block
);
8142 Temp ma
, tc
, sc
, id
;
8145 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8147 // see comment in ac_prepare_cube_coords()
8148 if (ctx
->options
->chip_class
<= GFX8
)
8149 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8152 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8154 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8155 vop3a
->operands
[0] = Operand(ma
);
8156 vop3a
->abs
[0] = true;
8157 Temp invma
= bld
.tmp(v1
);
8158 vop3a
->definitions
[0] = Definition(invma
);
8159 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8161 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8163 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8165 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8167 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8169 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8172 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8173 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8175 for (unsigned i
= 0; i
< 2; i
++) {
8176 // see comment in ac_prepare_cube_coords()
8178 Temp deriv_sc
, deriv_tc
;
8179 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8180 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8182 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8184 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8185 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8186 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8187 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8188 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8189 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8190 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8193 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8194 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8198 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8205 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8207 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8209 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8210 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8213 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8214 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8215 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8219 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8221 Builder
bld(ctx
->program
, ctx
->block
);
8222 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8223 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8224 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8225 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8226 std::vector
<Temp
> coords
;
8227 std::vector
<Temp
> derivs
;
8228 nir_const_value
*sample_index_cv
= NULL
;
8229 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8230 enum glsl_base_type stype
;
8231 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8233 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8234 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8235 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8236 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8238 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8239 switch (instr
->src
[i
].src_type
) {
8240 case nir_tex_src_coord
: {
8241 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8242 for (unsigned i
= 0; i
< coord
.size(); i
++)
8243 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8246 case nir_tex_src_bias
:
8247 if (instr
->op
== nir_texop_txb
) {
8248 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8252 case nir_tex_src_lod
: {
8253 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8255 if (val
&& val
->f32
<= 0.0) {
8258 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8263 case nir_tex_src_comparator
:
8264 if (instr
->is_shadow
) {
8265 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8269 case nir_tex_src_offset
:
8270 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8271 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8274 case nir_tex_src_ddx
:
8275 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8278 case nir_tex_src_ddy
:
8279 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8282 case nir_tex_src_ms_index
:
8283 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8284 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8285 has_sample_index
= true;
8287 case nir_tex_src_texture_offset
:
8288 case nir_tex_src_sampler_offset
:
8294 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8295 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8297 if (instr
->op
== nir_texop_texture_samples
) {
8298 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8300 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8301 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8302 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8304 Operand default_sample
= Operand(1u);
8305 if (ctx
->options
->robust_buffer_access
) {
8306 /* Extract the second dword of the descriptor, if it's
8307 * all zero, then it's a null descriptor.
8309 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8310 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8311 default_sample
= Operand(is_non_null_descriptor
);
8314 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8315 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8316 samples
, default_sample
, bld
.scc(is_msaa
));
8320 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8321 aco_ptr
<Instruction
> tmp_instr
;
8322 Temp acc
, pack
= Temp();
8324 uint32_t pack_const
= 0;
8325 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8326 if (!const_offset
[i
])
8328 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8331 if (offset
.type() == RegType::sgpr
) {
8332 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8333 if (const_offset
[i
])
8336 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8337 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8340 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8343 if (pack
== Temp()) {
8346 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8350 if (pack_const
&& pack
!= Temp())
8351 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8353 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8354 if (const_offset
[i
])
8357 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8358 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8361 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8364 if (pack
== Temp()) {
8367 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8371 if (pack_const
&& pack
!= Temp())
8372 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8374 if (pack_const
&& pack
== Temp())
8375 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8376 else if (pack
== Temp())
8382 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8383 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8385 /* pack derivatives */
8386 if (has_ddx
|| has_ddy
) {
8387 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8388 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8389 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8390 derivs
= {ddx
, zero
, ddy
, zero
};
8392 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8393 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8394 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8395 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8400 if (instr
->coord_components
> 1 &&
8401 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8403 instr
->op
!= nir_texop_txf
)
8404 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8406 if (instr
->coord_components
> 2 &&
8407 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8408 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8409 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8410 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8412 instr
->op
!= nir_texop_txf
&&
8413 instr
->op
!= nir_texop_txf_ms
&&
8414 instr
->op
!= nir_texop_fragment_fetch
&&
8415 instr
->op
!= nir_texop_fragment_mask_fetch
)
8416 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8418 if (ctx
->options
->chip_class
== GFX9
&&
8419 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8420 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8421 assert(coords
.size() > 0 && coords
.size() < 3);
8423 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8424 Operand((uint32_t) 0) :
8425 Operand((uint32_t) 0x3f000000)));
8428 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8430 if (instr
->op
== nir_texop_samples_identical
)
8431 resource
= fmask_ptr
;
8433 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8434 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8435 instr
->op
!= nir_texop_txs
&&
8436 instr
->op
!= nir_texop_fragment_fetch
&&
8437 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8438 assert(has_sample_index
);
8439 Operand
op(sample_index
);
8440 if (sample_index_cv
)
8441 op
= Operand(sample_index_cv
->u32
);
8442 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8445 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8446 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8447 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8448 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8453 /* Build tex instruction */
8454 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8455 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8456 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8458 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8461 /* gather4 selects the component by dmask and always returns vec4 */
8462 if (instr
->op
== nir_texop_tg4
) {
8463 assert(instr
->dest
.ssa
.num_components
== 4);
8464 if (instr
->is_shadow
)
8467 dmask
= 1 << instr
->component
;
8468 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8469 tmp_dst
= bld
.tmp(v4
);
8470 } else if (instr
->op
== nir_texop_samples_identical
) {
8471 tmp_dst
= bld
.tmp(v1
);
8472 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8473 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8476 aco_ptr
<MIMG_instruction
> tex
;
8477 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8479 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8481 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8482 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8485 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8486 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8488 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8489 tex
->operands
[0] = Operand(resource
);
8490 tex
->operands
[1] = Operand(s4
); /* no sampler */
8491 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8492 if (ctx
->options
->chip_class
== GFX9
&&
8493 instr
->op
== nir_texop_txs
&&
8494 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8496 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8497 } else if (instr
->op
== nir_texop_query_levels
) {
8498 tex
->dmask
= 1 << 3;
8503 tex
->definitions
[0] = Definition(tmp_dst
);
8505 tex
->can_reorder
= true;
8506 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8509 /* divide 3rd value by 6 by multiplying with magic number */
8510 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8511 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8512 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8513 assert(instr
->dest
.ssa
.num_components
== 3);
8514 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8515 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8516 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8517 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8522 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8526 Temp tg4_compare_cube_wa64
= Temp();
8528 if (tg4_integer_workarounds
) {
8529 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8530 tex
->operands
[0] = Operand(resource
);
8531 tex
->operands
[1] = Operand(s4
); /* no sampler */
8532 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8536 Temp size
= bld
.tmp(v2
);
8537 tex
->definitions
[0] = Definition(size
);
8538 tex
->can_reorder
= true;
8539 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8540 emit_split_vector(ctx
, size
, size
.size());
8543 for (unsigned i
= 0; i
< 2; i
++) {
8544 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8545 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8546 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8547 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8550 Temp new_coords
[2] = {
8551 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8552 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8555 if (tg4_integer_cube_workaround
) {
8556 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8557 Temp desc
[resource
.size()];
8558 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8559 Format::PSEUDO
, 1, resource
.size())};
8560 split
->operands
[0] = Operand(resource
);
8561 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8562 desc
[i
] = bld
.tmp(s1
);
8563 split
->definitions
[i
] = Definition(desc
[i
]);
8565 ctx
->block
->instructions
.emplace_back(std::move(split
));
8567 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8568 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8569 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8572 if (stype
== GLSL_TYPE_UINT
) {
8573 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8574 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8575 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8576 bld
.scc(compare_cube_wa
));
8578 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8579 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8580 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8581 bld
.scc(compare_cube_wa
));
8583 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8584 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8586 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8588 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8589 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8590 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8592 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8593 Format::PSEUDO
, resource
.size(), 1)};
8594 for (unsigned i
= 0; i
< resource
.size(); i
++)
8595 vec
->operands
[i
] = Operand(desc
[i
]);
8596 resource
= bld
.tmp(resource
.regClass());
8597 vec
->definitions
[0] = Definition(resource
);
8598 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8600 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8601 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8602 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8603 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8605 coords
[0] = new_coords
[0];
8606 coords
[1] = new_coords
[1];
8609 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8610 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8612 assert(coords
.size() == 1);
8613 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8617 op
= aco_opcode::buffer_load_format_x
; break;
8619 op
= aco_opcode::buffer_load_format_xy
; break;
8621 op
= aco_opcode::buffer_load_format_xyz
; break;
8623 op
= aco_opcode::buffer_load_format_xyzw
; break;
8625 unreachable("Tex instruction loads more than 4 components.");
8628 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8629 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8632 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8634 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8635 mubuf
->operands
[0] = Operand(resource
);
8636 mubuf
->operands
[1] = Operand(coords
[0]);
8637 mubuf
->operands
[2] = Operand((uint32_t) 0);
8638 mubuf
->definitions
[0] = Definition(tmp_dst
);
8639 mubuf
->idxen
= true;
8640 mubuf
->can_reorder
= true;
8641 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8643 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8647 /* gather MIMG address components */
8648 std::vector
<Temp
> args
;
8650 args
.emplace_back(offset
);
8652 args
.emplace_back(bias
);
8654 args
.emplace_back(compare
);
8656 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8658 args
.insert(args
.end(), coords
.begin(), coords
.end());
8659 if (has_sample_index
)
8660 args
.emplace_back(sample_index
);
8662 args
.emplace_back(lod
);
8664 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8665 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8666 vec
->definitions
[0] = Definition(arg
);
8667 for (unsigned i
= 0; i
< args
.size(); i
++)
8668 vec
->operands
[i
] = Operand(args
[i
]);
8669 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8672 if (instr
->op
== nir_texop_txf
||
8673 instr
->op
== nir_texop_txf_ms
||
8674 instr
->op
== nir_texop_samples_identical
||
8675 instr
->op
== nir_texop_fragment_fetch
||
8676 instr
->op
== nir_texop_fragment_mask_fetch
) {
8677 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8678 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8679 tex
->operands
[0] = Operand(resource
);
8680 tex
->operands
[1] = Operand(s4
); /* no sampler */
8681 tex
->operands
[2] = Operand(arg
);
8686 tex
->definitions
[0] = Definition(tmp_dst
);
8687 tex
->can_reorder
= true;
8688 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8690 if (instr
->op
== nir_texop_samples_identical
) {
8691 assert(dmask
== 1 && dst
.regClass() == v1
);
8692 assert(dst
.id() != tmp_dst
.id());
8694 Temp tmp
= bld
.tmp(bld
.lm
);
8695 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8696 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8699 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8704 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8705 aco_opcode opcode
= aco_opcode::image_sample
;
8706 if (has_offset
) { /* image_sample_*_o */
8708 opcode
= aco_opcode::image_sample_c_o
;
8710 opcode
= aco_opcode::image_sample_c_d_o
;
8712 opcode
= aco_opcode::image_sample_c_b_o
;
8714 opcode
= aco_opcode::image_sample_c_lz_o
;
8716 opcode
= aco_opcode::image_sample_c_l_o
;
8718 opcode
= aco_opcode::image_sample_o
;
8720 opcode
= aco_opcode::image_sample_d_o
;
8722 opcode
= aco_opcode::image_sample_b_o
;
8724 opcode
= aco_opcode::image_sample_lz_o
;
8726 opcode
= aco_opcode::image_sample_l_o
;
8728 } else { /* no offset */
8730 opcode
= aco_opcode::image_sample_c
;
8732 opcode
= aco_opcode::image_sample_c_d
;
8734 opcode
= aco_opcode::image_sample_c_b
;
8736 opcode
= aco_opcode::image_sample_c_lz
;
8738 opcode
= aco_opcode::image_sample_c_l
;
8740 opcode
= aco_opcode::image_sample
;
8742 opcode
= aco_opcode::image_sample_d
;
8744 opcode
= aco_opcode::image_sample_b
;
8746 opcode
= aco_opcode::image_sample_lz
;
8748 opcode
= aco_opcode::image_sample_l
;
8752 if (instr
->op
== nir_texop_tg4
) {
8754 opcode
= aco_opcode::image_gather4_lz_o
;
8756 opcode
= aco_opcode::image_gather4_c_lz_o
;
8758 opcode
= aco_opcode::image_gather4_lz
;
8760 opcode
= aco_opcode::image_gather4_c_lz
;
8762 } else if (instr
->op
== nir_texop_lod
) {
8763 opcode
= aco_opcode::image_get_lod
;
8766 /* we don't need the bias, sample index, compare value or offset to be
8767 * computed in WQM but if the p_create_vector copies the coordinates, then it
8768 * needs to be in WQM */
8769 if (ctx
->stage
== fragment_fs
&&
8770 !has_derivs
&& !has_lod
&& !level_zero
&&
8771 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8772 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8773 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8775 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8776 tex
->operands
[0] = Operand(resource
);
8777 tex
->operands
[1] = Operand(sampler
);
8778 tex
->operands
[2] = Operand(arg
);
8782 tex
->definitions
[0] = Definition(tmp_dst
);
8783 tex
->can_reorder
= true;
8784 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8786 if (tg4_integer_cube_workaround
) {
8787 assert(tmp_dst
.id() != dst
.id());
8788 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8790 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8792 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8793 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8795 if (stype
== GLSL_TYPE_UINT
)
8796 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8798 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8799 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8801 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8802 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8803 val
[0], val
[1], val
[2], val
[3]);
8805 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8806 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8811 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8813 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8814 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8815 return Operand(tmp
.regClass());
8817 return Operand(tmp
);
8820 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8822 aco_ptr
<Pseudo_instruction
> phi
;
8823 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8824 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8826 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8827 logical
|= ctx
->block
->kind
& block_kind_merge
;
8828 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8830 /* we want a sorted list of sources, since the predecessor list is also sorted */
8831 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8832 nir_foreach_phi_src(src
, instr
)
8833 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8835 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8836 unsigned num_operands
= 0;
8837 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8838 unsigned num_defined
= 0;
8839 unsigned cur_pred_idx
= 0;
8840 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8841 if (cur_pred_idx
< preds
.size()) {
8842 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8843 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8844 unsigned skipped
= 0;
8845 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8847 if (cur_pred_idx
+ skipped
< preds
.size()) {
8848 for (unsigned i
= 0; i
< skipped
; i
++)
8849 operands
[num_operands
++] = Operand(dst
.regClass());
8850 cur_pred_idx
+= skipped
;
8855 /* Handle missing predecessors at the end. This shouldn't happen with loop
8856 * headers and we can't ignore these sources for loop header phis. */
8857 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8860 Operand op
= get_phi_operand(ctx
, src
.second
);
8861 operands
[num_operands
++] = op
;
8862 num_defined
+= !op
.isUndefined();
8864 /* handle block_kind_continue_or_break at loop exit blocks */
8865 while (cur_pred_idx
++ < preds
.size())
8866 operands
[num_operands
++] = Operand(dst
.regClass());
8868 /* If the loop ends with a break, still add a linear continue edge in case
8869 * that break is divergent or continue_or_break is used. We'll either remove
8870 * this operand later in visit_loop() if it's not necessary or replace the
8871 * undef with something correct. */
8872 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8873 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8874 nir_block
*last
= nir_loop_last_block(loop
);
8875 if (last
->successors
[0] != instr
->instr
.block
)
8876 operands
[num_operands
++] = Operand(RegClass());
8879 if (num_defined
== 0) {
8880 Builder
bld(ctx
->program
, ctx
->block
);
8881 if (dst
.regClass() == s1
) {
8882 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8883 } else if (dst
.regClass() == v1
) {
8884 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8886 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8887 for (unsigned i
= 0; i
< dst
.size(); i
++)
8888 vec
->operands
[i
] = Operand(0u);
8889 vec
->definitions
[0] = Definition(dst
);
8890 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8895 /* we can use a linear phi in some cases if one src is undef */
8896 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8897 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8899 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8900 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8901 assert(invert
->kind
& block_kind_invert
);
8903 unsigned then_block
= invert
->linear_preds
[0];
8905 Block
* insert_block
= NULL
;
8906 for (unsigned i
= 0; i
< num_operands
; i
++) {
8907 Operand op
= operands
[i
];
8908 if (op
.isUndefined())
8910 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8911 phi
->operands
[0] = op
;
8914 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8915 phi
->operands
[1] = Operand(dst
.regClass());
8916 phi
->definitions
[0] = Definition(dst
);
8917 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8921 /* try to scalarize vector phis */
8922 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8923 // TODO: scalarize linear phis on divergent ifs
8924 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8925 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8926 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8927 Operand src
= operands
[i
];
8928 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8929 can_scalarize
= false;
8931 if (can_scalarize
) {
8932 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8933 assert(dst
.size() % num_components
== 0);
8934 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8936 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8937 for (unsigned k
= 0; k
< num_components
; k
++) {
8938 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8939 for (unsigned i
= 0; i
< num_operands
; i
++) {
8940 Operand src
= operands
[i
];
8941 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8943 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8944 phi
->definitions
[0] = Definition(phi_dst
);
8945 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8946 new_vec
[k
] = phi_dst
;
8947 vec
->operands
[k
] = Operand(phi_dst
);
8949 vec
->definitions
[0] = Definition(dst
);
8950 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8951 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8956 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8957 for (unsigned i
= 0; i
< num_operands
; i
++)
8958 phi
->operands
[i
] = operands
[i
];
8959 phi
->definitions
[0] = Definition(dst
);
8960 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8964 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8966 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8968 assert(dst
.type() == RegType::sgpr
);
8970 if (dst
.size() == 1) {
8971 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8973 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8974 for (unsigned i
= 0; i
< dst
.size(); i
++)
8975 vec
->operands
[i
] = Operand(0u);
8976 vec
->definitions
[0] = Definition(dst
);
8977 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8981 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8983 Builder
bld(ctx
->program
, ctx
->block
);
8984 Block
*logical_target
;
8985 append_logical_end(ctx
->block
);
8986 unsigned idx
= ctx
->block
->index
;
8988 switch (instr
->type
) {
8989 case nir_jump_break
:
8990 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8991 add_logical_edge(idx
, logical_target
);
8992 ctx
->block
->kind
|= block_kind_break
;
8994 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8995 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8996 /* uniform break - directly jump out of the loop */
8997 ctx
->block
->kind
|= block_kind_uniform
;
8998 ctx
->cf_info
.has_branch
= true;
8999 bld
.branch(aco_opcode::p_branch
);
9000 add_linear_edge(idx
, logical_target
);
9003 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9004 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9006 case nir_jump_continue
:
9007 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9008 add_logical_edge(idx
, logical_target
);
9009 ctx
->block
->kind
|= block_kind_continue
;
9011 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9012 /* for potential uniform breaks after this continue,
9013 we must ensure that they are handled correctly */
9014 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9015 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9016 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9018 /* uniform continue - directly jump to the loop header */
9019 ctx
->block
->kind
|= block_kind_uniform
;
9020 ctx
->cf_info
.has_branch
= true;
9021 bld
.branch(aco_opcode::p_branch
);
9022 add_linear_edge(idx
, logical_target
);
9027 fprintf(stderr
, "Unknown NIR jump instr: ");
9028 nir_print_instr(&instr
->instr
, stderr
);
9029 fprintf(stderr
, "\n");
9033 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9034 ctx
->cf_info
.exec_potentially_empty_break
= true;
9035 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9038 /* remove critical edges from linear CFG */
9039 bld
.branch(aco_opcode::p_branch
);
9040 Block
* break_block
= ctx
->program
->create_and_insert_block();
9041 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9042 break_block
->kind
|= block_kind_uniform
;
9043 add_linear_edge(idx
, break_block
);
9044 /* the loop_header pointer might be invalidated by this point */
9045 if (instr
->type
== nir_jump_continue
)
9046 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9047 add_linear_edge(break_block
->index
, logical_target
);
9048 bld
.reset(break_block
);
9049 bld
.branch(aco_opcode::p_branch
);
9051 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9052 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9053 add_linear_edge(idx
, continue_block
);
9054 append_logical_start(continue_block
);
9055 ctx
->block
= continue_block
;
9059 void visit_block(isel_context
*ctx
, nir_block
*block
)
9061 nir_foreach_instr(instr
, block
) {
9062 switch (instr
->type
) {
9063 case nir_instr_type_alu
:
9064 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9066 case nir_instr_type_load_const
:
9067 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9069 case nir_instr_type_intrinsic
:
9070 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9072 case nir_instr_type_tex
:
9073 visit_tex(ctx
, nir_instr_as_tex(instr
));
9075 case nir_instr_type_phi
:
9076 visit_phi(ctx
, nir_instr_as_phi(instr
));
9078 case nir_instr_type_ssa_undef
:
9079 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9081 case nir_instr_type_deref
:
9083 case nir_instr_type_jump
:
9084 visit_jump(ctx
, nir_instr_as_jump(instr
));
9087 fprintf(stderr
, "Unknown NIR instr type: ");
9088 nir_print_instr(instr
, stderr
);
9089 fprintf(stderr
, "\n");
9094 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9095 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9100 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9101 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9103 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9104 RegClass rc
= vals
[0].regClass();
9106 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9108 unsigned next_pred
= 1;
9110 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9111 Block
& block
= ctx
->program
->blocks
[idx
];
9112 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9113 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9117 if (block
.kind
& block_kind_continue
) {
9118 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9123 bool all_same
= true;
9124 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9125 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9129 val
= vals
[block
.linear_preds
[0] - first
];
9131 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9132 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9133 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9134 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9135 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9136 phi
->definitions
[0] = Definition(val
.getTemp());
9137 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9139 vals
[idx
- first
] = val
;
9142 return vals
[last
- first
];
9145 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9147 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9148 append_logical_end(ctx
->block
);
9149 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9150 Builder
bld(ctx
->program
, ctx
->block
);
9151 bld
.branch(aco_opcode::p_branch
);
9152 unsigned loop_preheader_idx
= ctx
->block
->index
;
9154 Block loop_exit
= Block();
9155 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9156 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9158 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9159 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9160 loop_header
->kind
|= block_kind_loop_header
;
9161 add_edge(loop_preheader_idx
, loop_header
);
9162 ctx
->block
= loop_header
;
9164 /* emit loop body */
9165 unsigned loop_header_idx
= loop_header
->index
;
9166 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9167 append_logical_start(ctx
->block
);
9168 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9170 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9171 if (!ctx
->cf_info
.has_branch
) {
9172 append_logical_end(ctx
->block
);
9173 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9174 /* Discards can result in code running with an empty exec mask.
9175 * This would result in divergent breaks not ever being taken. As a
9176 * workaround, break the loop when the loop mask is empty instead of
9177 * always continuing. */
9178 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9179 unsigned block_idx
= ctx
->block
->index
;
9181 /* create helper blocks to avoid critical edges */
9182 Block
*break_block
= ctx
->program
->create_and_insert_block();
9183 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9184 break_block
->kind
= block_kind_uniform
;
9185 bld
.reset(break_block
);
9186 bld
.branch(aco_opcode::p_branch
);
9187 add_linear_edge(block_idx
, break_block
);
9188 add_linear_edge(break_block
->index
, &loop_exit
);
9190 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9191 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9192 continue_block
->kind
= block_kind_uniform
;
9193 bld
.reset(continue_block
);
9194 bld
.branch(aco_opcode::p_branch
);
9195 add_linear_edge(block_idx
, continue_block
);
9196 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9198 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9199 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9200 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9202 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9203 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9204 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9206 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9209 bld
.reset(ctx
->block
);
9210 bld
.branch(aco_opcode::p_branch
);
9213 /* Fixup phis in loop header from unreachable blocks.
9214 * has_branch/has_divergent_branch also indicates if the loop ends with a
9215 * break/continue instruction, but we don't emit those if unreachable=true */
9217 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9218 bool linear
= ctx
->cf_info
.has_branch
;
9219 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9220 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9221 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9222 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9223 /* the last operand should be the one that needs to be removed */
9224 instr
->operands
.pop_back();
9225 } else if (!is_phi(instr
)) {
9231 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9232 * and the previous one shouldn't both happen at once because a break in the
9233 * merge block would get CSE'd */
9234 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9235 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9236 Operand vals
[num_vals
];
9237 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9238 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9239 if (ctx
->cf_info
.has_branch
)
9240 instr
->operands
.pop_back();
9242 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9243 } else if (!is_phi(instr
)) {
9249 ctx
->cf_info
.has_branch
= false;
9251 // TODO: if the loop has not a single exit, we must add one °°
9252 /* emit loop successor block */
9253 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9254 append_logical_start(ctx
->block
);
9257 // TODO: check if it is beneficial to not branch on continues
9258 /* trim linear phis in loop header */
9259 for (auto&& instr
: loop_entry
->instructions
) {
9260 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9261 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9262 new_phi
->definitions
[0] = instr
->definitions
[0];
9263 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9264 new_phi
->operands
[i
] = instr
->operands
[i
];
9265 /* check that the remaining operands are all the same */
9266 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9267 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9268 instr
.swap(new_phi
);
9269 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9278 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9282 append_logical_end(ctx
->block
);
9283 ctx
->block
->kind
|= block_kind_branch
;
9285 /* branch to linear then block */
9286 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9287 aco_ptr
<Pseudo_branch_instruction
> branch
;
9288 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9289 branch
->operands
[0] = Operand(cond
);
9290 ctx
->block
->instructions
.push_back(std::move(branch
));
9292 ic
->BB_if_idx
= ctx
->block
->index
;
9293 ic
->BB_invert
= Block();
9294 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9295 /* Invert blocks are intentionally not marked as top level because they
9296 * are not part of the logical cfg. */
9297 ic
->BB_invert
.kind
|= block_kind_invert
;
9298 ic
->BB_endif
= Block();
9299 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9300 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9302 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9303 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9304 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9305 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9306 ctx
->cf_info
.parent_if
.is_divergent
= true;
9308 /* divergent branches use cbranch_execz */
9309 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9310 ctx
->cf_info
.exec_potentially_empty_break
= false;
9311 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9313 /** emit logical then block */
9314 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9315 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9316 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9317 ctx
->block
= BB_then_logical
;
9318 append_logical_start(BB_then_logical
);
9321 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9323 Block
*BB_then_logical
= ctx
->block
;
9324 append_logical_end(BB_then_logical
);
9325 /* branch from logical then block to invert block */
9326 aco_ptr
<Pseudo_branch_instruction
> branch
;
9327 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9328 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9329 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9330 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9331 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9332 BB_then_logical
->kind
|= block_kind_uniform
;
9333 assert(!ctx
->cf_info
.has_branch
);
9334 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9335 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9337 /** emit linear then block */
9338 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9339 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9340 BB_then_linear
->kind
|= block_kind_uniform
;
9341 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9342 /* branch from linear then block to invert block */
9343 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9344 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9345 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9347 /** emit invert merge block */
9348 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9349 ic
->invert_idx
= ctx
->block
->index
;
9351 /* branch to linear else block (skip else) */
9352 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9353 branch
->operands
[0] = Operand(ic
->cond
);
9354 ctx
->block
->instructions
.push_back(std::move(branch
));
9356 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9357 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9358 ic
->exec_potentially_empty_break_depth_old
=
9359 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9360 /* divergent branches use cbranch_execz */
9361 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9362 ctx
->cf_info
.exec_potentially_empty_break
= false;
9363 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9365 /** emit logical else block */
9366 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9367 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9368 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9369 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9370 ctx
->block
= BB_else_logical
;
9371 append_logical_start(BB_else_logical
);
9374 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9376 Block
*BB_else_logical
= ctx
->block
;
9377 append_logical_end(BB_else_logical
);
9379 /* branch from logical else block to endif block */
9380 aco_ptr
<Pseudo_branch_instruction
> branch
;
9381 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9382 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9383 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9384 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9385 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9386 BB_else_logical
->kind
|= block_kind_uniform
;
9388 assert(!ctx
->cf_info
.has_branch
);
9389 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9392 /** emit linear else block */
9393 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9394 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9395 BB_else_linear
->kind
|= block_kind_uniform
;
9396 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9398 /* branch from linear else block to endif block */
9399 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9400 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9401 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9404 /** emit endif merge block */
9405 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9406 append_logical_start(ctx
->block
);
9409 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9410 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9411 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9412 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9413 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9414 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9415 !ctx
->cf_info
.parent_if
.is_divergent
) {
9416 ctx
->cf_info
.exec_potentially_empty_break
= false;
9417 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9419 /* uniform control flow never has an empty exec-mask */
9420 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9421 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9422 ctx
->cf_info
.exec_potentially_empty_break
= false;
9423 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9427 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9429 assert(cond
.regClass() == s1
);
9431 append_logical_end(ctx
->block
);
9432 ctx
->block
->kind
|= block_kind_uniform
;
9434 aco_ptr
<Pseudo_branch_instruction
> branch
;
9435 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9436 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9437 branch
->operands
[0] = Operand(cond
);
9438 branch
->operands
[0].setFixed(scc
);
9439 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9441 ic
->BB_if_idx
= ctx
->block
->index
;
9442 ic
->BB_endif
= Block();
9443 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9444 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9446 ctx
->cf_info
.has_branch
= false;
9447 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9449 /** emit then block */
9450 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9451 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9452 add_edge(ic
->BB_if_idx
, BB_then
);
9453 append_logical_start(BB_then
);
9454 ctx
->block
= BB_then
;
9457 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9459 Block
*BB_then
= ctx
->block
;
9461 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9462 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9464 if (!ic
->uniform_has_then_branch
) {
9465 append_logical_end(BB_then
);
9466 /* branch from then block to endif block */
9467 aco_ptr
<Pseudo_branch_instruction
> branch
;
9468 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9469 BB_then
->instructions
.emplace_back(std::move(branch
));
9470 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9471 if (!ic
->then_branch_divergent
)
9472 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9473 BB_then
->kind
|= block_kind_uniform
;
9476 ctx
->cf_info
.has_branch
= false;
9477 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9479 /** emit else block */
9480 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9481 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9482 add_edge(ic
->BB_if_idx
, BB_else
);
9483 append_logical_start(BB_else
);
9484 ctx
->block
= BB_else
;
9487 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9489 Block
*BB_else
= ctx
->block
;
9491 if (!ctx
->cf_info
.has_branch
) {
9492 append_logical_end(BB_else
);
9493 /* branch from then block to endif block */
9494 aco_ptr
<Pseudo_branch_instruction
> branch
;
9495 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9496 BB_else
->instructions
.emplace_back(std::move(branch
));
9497 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9498 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9499 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9500 BB_else
->kind
|= block_kind_uniform
;
9503 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9504 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9506 /** emit endif merge block */
9507 if (!ctx
->cf_info
.has_branch
) {
9508 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9509 append_logical_start(ctx
->block
);
9513 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9515 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9516 Builder
bld(ctx
->program
, ctx
->block
);
9517 aco_ptr
<Pseudo_branch_instruction
> branch
;
9520 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9522 * Uniform conditionals are represented in the following way*) :
9524 * The linear and logical CFG:
9527 * BB_THEN (logical) BB_ELSE (logical)
9531 * *) Exceptions may be due to break and continue statements within loops
9532 * If a break/continue happens within uniform control flow, it branches
9533 * to the loop exit/entry block. Otherwise, it branches to the next
9537 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9538 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9539 cond
= bool_to_scalar_condition(ctx
, cond
);
9541 begin_uniform_if_then(ctx
, &ic
, cond
);
9542 visit_cf_list(ctx
, &if_stmt
->then_list
);
9544 begin_uniform_if_else(ctx
, &ic
);
9545 visit_cf_list(ctx
, &if_stmt
->else_list
);
9547 end_uniform_if(ctx
, &ic
);
9548 } else { /* non-uniform condition */
9550 * To maintain a logical and linear CFG without critical edges,
9551 * non-uniform conditionals are represented in the following way*) :
9556 * BB_THEN (logical) BB_THEN (linear)
9558 * BB_INVERT (linear)
9560 * BB_ELSE (logical) BB_ELSE (linear)
9567 * BB_THEN (logical) BB_ELSE (logical)
9571 * *) Exceptions may be due to break and continue statements within loops
9574 begin_divergent_if_then(ctx
, &ic
, cond
);
9575 visit_cf_list(ctx
, &if_stmt
->then_list
);
9577 begin_divergent_if_else(ctx
, &ic
);
9578 visit_cf_list(ctx
, &if_stmt
->else_list
);
9580 end_divergent_if(ctx
, &ic
);
9583 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9586 static bool visit_cf_list(isel_context
*ctx
,
9587 struct exec_list
*list
)
9589 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9590 switch (node
->type
) {
9591 case nir_cf_node_block
:
9592 visit_block(ctx
, nir_cf_node_as_block(node
));
9594 case nir_cf_node_if
:
9595 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9598 case nir_cf_node_loop
:
9599 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9602 unreachable("unimplemented cf list type");
9608 static void create_null_export(isel_context
*ctx
)
9610 /* Some shader stages always need to have exports.
9611 * So when there is none, we need to add a null export.
9614 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9615 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9616 Builder
bld(ctx
->program
, ctx
->block
);
9617 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9618 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9621 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9623 assert(ctx
->stage
== vertex_vs
||
9624 ctx
->stage
== tess_eval_vs
||
9625 ctx
->stage
== gs_copy_vs
||
9626 ctx
->stage
== ngg_vertex_gs
||
9627 ctx
->stage
== ngg_tess_eval_gs
);
9629 int offset
= (ctx
->stage
& sw_tes
)
9630 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9631 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9632 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9633 if (!is_pos
&& !mask
)
9635 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9637 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9638 exp
->enabled_mask
= mask
;
9639 for (unsigned i
= 0; i
< 4; ++i
) {
9640 if (mask
& (1 << i
))
9641 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9643 exp
->operands
[i
] = Operand(v1
);
9645 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9646 * Setting valid_mask=1 prevents it and has no other effect.
9648 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9650 exp
->compressed
= false;
9652 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9654 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9655 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9660 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9662 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9663 exp
->enabled_mask
= 0;
9664 for (unsigned i
= 0; i
< 4; ++i
)
9665 exp
->operands
[i
] = Operand(v1
);
9666 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9667 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9668 exp
->enabled_mask
|= 0x1;
9670 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9671 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9672 exp
->enabled_mask
|= 0x4;
9674 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9675 if (ctx
->options
->chip_class
< GFX9
) {
9676 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9677 exp
->enabled_mask
|= 0x8;
9679 Builder
bld(ctx
->program
, ctx
->block
);
9681 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9682 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9683 if (exp
->operands
[2].isTemp())
9684 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9686 exp
->operands
[2] = Operand(out
);
9687 exp
->enabled_mask
|= 0x4;
9690 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9692 exp
->compressed
= false;
9693 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9694 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9697 static void create_export_phis(isel_context
*ctx
)
9699 /* Used when exports are needed, but the output temps are defined in a preceding block.
9700 * This function will set up phis in order to access the outputs in the next block.
9703 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9704 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9705 ctx
->block
->instructions
.pop_back();
9707 Builder
bld(ctx
->program
, ctx
->block
);
9709 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9710 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9711 for (unsigned i
= 0; i
< 4; ++i
) {
9712 if (!(mask
& (1 << i
)))
9715 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9716 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9717 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9721 bld
.insert(std::move(logical_start
));
9724 static void create_vs_exports(isel_context
*ctx
)
9726 assert(ctx
->stage
== vertex_vs
||
9727 ctx
->stage
== tess_eval_vs
||
9728 ctx
->stage
== gs_copy_vs
||
9729 ctx
->stage
== ngg_vertex_gs
||
9730 ctx
->stage
== ngg_tess_eval_gs
);
9732 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9733 ? &ctx
->program
->info
->tes
.outinfo
9734 : &ctx
->program
->info
->vs
.outinfo
;
9736 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9737 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9738 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9741 if (ctx
->options
->key
.has_multiview_view_index
) {
9742 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9743 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9746 /* the order these position exports are created is important */
9748 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9749 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9750 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9751 exported_pos
= true;
9753 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9754 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9755 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9756 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9758 if (ctx
->export_clip_dists
) {
9759 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9760 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9761 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9762 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9765 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9766 if (i
< VARYING_SLOT_VAR0
&&
9767 i
!= VARYING_SLOT_LAYER
&&
9768 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9769 i
!= VARYING_SLOT_VIEWPORT
)
9772 export_vs_varying(ctx
, i
, false, NULL
);
9776 create_null_export(ctx
);
9779 static bool export_fs_mrt_z(isel_context
*ctx
)
9781 Builder
bld(ctx
->program
, ctx
->block
);
9782 unsigned enabled_channels
= 0;
9786 for (unsigned i
= 0; i
< 4; ++i
) {
9787 values
[i
] = Operand(v1
);
9790 /* Both stencil and sample mask only need 16-bits. */
9791 if (!ctx
->program
->info
->ps
.writes_z
&&
9792 (ctx
->program
->info
->ps
.writes_stencil
||
9793 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9794 compr
= true; /* COMPR flag */
9796 if (ctx
->program
->info
->ps
.writes_stencil
) {
9797 /* Stencil should be in X[23:16]. */
9798 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9799 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9800 enabled_channels
|= 0x3;
9803 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9804 /* SampleMask should be in Y[15:0]. */
9805 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9806 enabled_channels
|= 0xc;
9809 if (ctx
->program
->info
->ps
.writes_z
) {
9810 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9811 enabled_channels
|= 0x1;
9814 if (ctx
->program
->info
->ps
.writes_stencil
) {
9815 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9816 enabled_channels
|= 0x2;
9819 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9820 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9821 enabled_channels
|= 0x4;
9825 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9826 * writemask component.
9828 if (ctx
->options
->chip_class
== GFX6
&&
9829 ctx
->options
->family
!= CHIP_OLAND
&&
9830 ctx
->options
->family
!= CHIP_HAINAN
) {
9831 enabled_channels
|= 0x1;
9834 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9835 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9840 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9842 Builder
bld(ctx
->program
, ctx
->block
);
9843 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9846 for (unsigned i
= 0; i
< 4; ++i
) {
9847 if (write_mask
& (1 << i
)) {
9848 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9850 values
[i
] = Operand(v1
);
9854 unsigned target
, col_format
;
9855 unsigned enabled_channels
= 0;
9856 aco_opcode compr_op
= (aco_opcode
)0;
9858 slot
-= FRAG_RESULT_DATA0
;
9859 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9860 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9862 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9863 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9867 case V_028714_SPI_SHADER_ZERO
:
9868 enabled_channels
= 0; /* writemask */
9869 target
= V_008DFC_SQ_EXP_NULL
;
9872 case V_028714_SPI_SHADER_32_R
:
9873 enabled_channels
= 1;
9876 case V_028714_SPI_SHADER_32_GR
:
9877 enabled_channels
= 0x3;
9880 case V_028714_SPI_SHADER_32_AR
:
9881 if (ctx
->options
->chip_class
>= GFX10
) {
9882 /* Special case: on GFX10, the outputs are different for 32_AR */
9883 enabled_channels
= 0x3;
9884 values
[1] = values
[3];
9885 values
[3] = Operand(v1
);
9887 enabled_channels
= 0x9;
9891 case V_028714_SPI_SHADER_FP16_ABGR
:
9892 enabled_channels
= 0x5;
9893 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9896 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9897 enabled_channels
= 0x5;
9898 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9901 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9902 enabled_channels
= 0x5;
9903 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9906 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9907 enabled_channels
= 0x5;
9908 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9909 if (is_int8
|| is_int10
) {
9911 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9912 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9914 for (unsigned i
= 0; i
< 4; i
++) {
9915 if ((write_mask
>> i
) & 1) {
9916 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9917 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9925 case V_028714_SPI_SHADER_SINT16_ABGR
:
9926 enabled_channels
= 0x5;
9927 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9928 if (is_int8
|| is_int10
) {
9930 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9931 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9932 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9933 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9935 for (unsigned i
= 0; i
< 4; i
++) {
9936 if ((write_mask
>> i
) & 1) {
9937 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9938 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9940 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9941 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9948 case V_028714_SPI_SHADER_32_ABGR
:
9949 enabled_channels
= 0xF;
9956 if (target
== V_008DFC_SQ_EXP_NULL
)
9959 if ((bool) compr_op
) {
9960 for (int i
= 0; i
< 2; i
++) {
9961 /* check if at least one of the values to be compressed is enabled */
9962 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9964 enabled_channels
|= enabled
<< (i
*2);
9965 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9966 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9967 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9969 values
[i
] = Operand(v1
);
9972 values
[2] = Operand(v1
);
9973 values
[3] = Operand(v1
);
9975 for (int i
= 0; i
< 4; i
++)
9976 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9979 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9980 enabled_channels
, target
, (bool) compr_op
);
9984 static void create_fs_exports(isel_context
*ctx
)
9986 bool exported
= false;
9988 /* Export depth, stencil and sample mask. */
9989 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9990 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9991 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9992 exported
|= export_fs_mrt_z(ctx
);
9994 /* Export all color render targets. */
9995 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9996 if (ctx
->outputs
.mask
[i
])
9997 exported
|= export_fs_mrt_color(ctx
, i
);
10000 create_null_export(ctx
);
10003 static void write_tcs_tess_factors(isel_context
*ctx
)
10005 unsigned outer_comps
;
10006 unsigned inner_comps
;
10008 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10025 Builder
bld(ctx
->program
, ctx
->block
);
10027 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10028 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10029 bld
.sopp(aco_opcode::s_barrier
);
10031 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10032 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10034 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10035 if_context ic_invocation_id_is_zero
;
10036 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10037 bld
.reset(ctx
->block
);
10039 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10041 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10042 unsigned stride
= inner_comps
+ outer_comps
;
10043 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10047 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10049 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10051 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10052 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10053 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10055 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10056 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10058 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10059 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10060 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10061 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10064 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10065 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10066 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10067 unsigned tf_const_offset
= 0;
10069 if (ctx
->program
->chip_class
<= GFX8
) {
10070 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10071 if_context ic_rel_patch_id_is_zero
;
10072 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10073 bld
.reset(ctx
->block
);
10075 /* Store the dynamic HS control word. */
10076 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10077 bld
.mubuf(aco_opcode::buffer_store_dword
,
10078 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10079 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10080 /* disable_wqm */ false, /* glc */ true);
10081 tf_const_offset
+= 4;
10083 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10084 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10085 bld
.reset(ctx
->block
);
10088 assert(stride
== 2 || stride
== 4 || stride
== 6);
10089 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10090 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10092 /* Store to offchip for TES to read - only if TES reads them */
10093 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10094 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10095 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10097 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10098 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10100 if (likely(inner_comps
)) {
10101 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10102 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10106 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10107 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10110 static void emit_stream_output(isel_context
*ctx
,
10111 Temp
const *so_buffers
,
10112 Temp
const *so_write_offset
,
10113 const struct radv_stream_output
*output
)
10115 unsigned num_comps
= util_bitcount(output
->component_mask
);
10116 unsigned writemask
= (1 << num_comps
) - 1;
10117 unsigned loc
= output
->location
;
10118 unsigned buf
= output
->buffer
;
10120 assert(num_comps
&& num_comps
<= 4);
10121 if (!num_comps
|| num_comps
> 4)
10124 unsigned start
= ffs(output
->component_mask
) - 1;
10127 bool all_undef
= true;
10128 assert(ctx
->stage
& hw_vs
);
10129 for (unsigned i
= 0; i
< num_comps
; i
++) {
10130 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10131 all_undef
= all_undef
&& !out
[i
].id();
10136 while (writemask
) {
10138 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10139 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10140 /* GFX6 doesn't support storing vec3, split it. */
10141 writemask
|= 1u << (start
+ 2);
10145 unsigned offset
= output
->offset
+ start
* 4;
10147 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10148 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10149 for (int i
= 0; i
< count
; ++i
)
10150 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10151 vec
->definitions
[0] = Definition(write_data
);
10152 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10157 opcode
= aco_opcode::buffer_store_dword
;
10160 opcode
= aco_opcode::buffer_store_dwordx2
;
10163 opcode
= aco_opcode::buffer_store_dwordx3
;
10166 opcode
= aco_opcode::buffer_store_dwordx4
;
10169 unreachable("Unsupported dword count.");
10172 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10173 store
->operands
[0] = Operand(so_buffers
[buf
]);
10174 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10175 store
->operands
[2] = Operand((uint32_t) 0);
10176 store
->operands
[3] = Operand(write_data
);
10177 if (offset
> 4095) {
10178 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10179 Builder
bld(ctx
->program
, ctx
->block
);
10180 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10182 store
->offset
= offset
;
10184 store
->offen
= true;
10186 store
->dlc
= false;
10188 store
->can_reorder
= true;
10189 ctx
->block
->instructions
.emplace_back(std::move(store
));
10193 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10195 Builder
bld(ctx
->program
, ctx
->block
);
10197 Temp so_buffers
[4];
10198 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10199 for (unsigned i
= 0; i
< 4; i
++) {
10200 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10204 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10205 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10208 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10209 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10211 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10213 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10216 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10218 bld
.reset(ctx
->block
);
10220 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10222 Temp so_write_offset
[4];
10224 for (unsigned i
= 0; i
< 4; i
++) {
10225 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10230 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10231 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10232 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10233 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10235 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10237 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10238 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10239 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10240 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10244 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10245 struct radv_stream_output
*output
=
10246 &ctx
->program
->info
->so
.outputs
[i
];
10247 if (stream
!= output
->stream
)
10250 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10253 begin_divergent_if_else(ctx
, &ic
);
10254 end_divergent_if(ctx
, &ic
);
10257 } /* end namespace */
10259 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10261 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10262 Builder
bld(ctx
->program
, ctx
->block
);
10263 constexpr unsigned hs_idx
= 1u;
10264 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10265 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10266 Operand((8u << 16) | (hs_idx
* 8u)));
10267 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10269 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10271 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10272 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10273 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10274 ls_has_nonzero_hs_threads
);
10275 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10276 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10277 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10278 ls_has_nonzero_hs_threads
);
10279 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10280 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10281 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10282 ls_has_nonzero_hs_threads
);
10284 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10285 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10286 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10289 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10291 /* Split all arguments except for the first (ring_offsets) and the last
10292 * (exec) so that the dead channels don't stay live throughout the program.
10294 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10295 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10296 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10297 startpgm
->definitions
[i
].regClass().size());
10302 void handle_bc_optimize(isel_context
*ctx
)
10304 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10305 Builder
bld(ctx
->program
, ctx
->block
);
10306 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10307 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10308 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10309 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10310 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10311 if (uses_center
&& uses_centroid
) {
10312 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10313 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10315 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10317 for (unsigned i
= 0; i
< 2; i
++) {
10318 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10319 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10320 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10321 persp_centroid
, persp_center
, sel
);
10323 ctx
->persp_centroid
= bld
.tmp(v2
);
10324 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10325 Operand(new_coord
[0]), Operand(new_coord
[1]));
10326 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10329 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10331 for (unsigned i
= 0; i
< 2; i
++) {
10332 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10333 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10334 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10335 linear_centroid
, linear_center
, sel
);
10337 ctx
->linear_centroid
= bld
.tmp(v2
);
10338 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10339 Operand(new_coord
[0]), Operand(new_coord
[1]));
10340 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10345 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10347 Program
*program
= ctx
->program
;
10349 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10351 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10352 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10353 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10354 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10355 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10357 program
->next_fp_mode
.must_flush_denorms32
=
10358 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10359 program
->next_fp_mode
.must_flush_denorms16_64
=
10360 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10361 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10363 program
->next_fp_mode
.care_about_round32
=
10364 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10366 program
->next_fp_mode
.care_about_round16_64
=
10367 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10368 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10370 /* default to preserving fp16 and fp64 denorms, since it's free */
10371 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10372 program
->next_fp_mode
.denorm16_64
= 0;
10374 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10376 /* preserving fp32 denorms is expensive, so only do it if asked */
10377 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10378 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10380 program
->next_fp_mode
.denorm32
= 0;
10382 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10383 program
->next_fp_mode
.round32
= fp_round_tz
;
10385 program
->next_fp_mode
.round32
= fp_round_ne
;
10387 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10388 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10390 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10392 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10395 void cleanup_cfg(Program
*program
)
10397 /* create linear_succs/logical_succs */
10398 for (Block
& BB
: program
->blocks
) {
10399 for (unsigned idx
: BB
.linear_preds
)
10400 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10401 for (unsigned idx
: BB
.logical_preds
)
10402 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10406 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10408 Builder
bld(ctx
->program
, ctx
->block
);
10410 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10411 Temp count
= i
== 0
10412 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10413 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10414 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10416 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10419 if (ctx
->program
->wave_size
== 64) {
10420 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10421 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10422 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10424 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10425 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10431 bool ngg_early_prim_export(isel_context
*ctx
)
10433 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10437 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10439 Builder
bld(ctx
->program
, ctx
->block
);
10441 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10442 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10444 /* Get the id of the current wave within the threadgroup (workgroup) */
10445 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10446 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10448 /* Execute the following code only on the first wave (wave id 0),
10449 * use the SCC def to tell if the wave id is zero or not.
10451 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10453 begin_uniform_if_then(ctx
, &ic
, cond
);
10454 begin_uniform_if_else(ctx
, &ic
);
10455 bld
.reset(ctx
->block
);
10457 /* Number of vertices output by VS/TES */
10458 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10459 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10460 /* Number of primitives output by VS/TES */
10461 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10462 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10464 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10465 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10466 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10468 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10469 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10471 end_uniform_if(ctx
, &ic
);
10473 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10474 bld
.reset(ctx
->block
);
10475 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10478 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10480 Builder
bld(ctx
->program
, ctx
->block
);
10482 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10483 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10486 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10489 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10490 assert(vtxindex
[i
].id());
10493 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10497 /* The initial edge flag is always false in tess eval shaders. */
10498 if (ctx
->stage
== ngg_vertex_gs
) {
10499 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10500 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10504 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10509 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10511 Builder
bld(ctx
->program
, ctx
->block
);
10512 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10514 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10515 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10516 false /* compressed */, true/* done */, false /* valid mask */);
10519 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10521 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10522 * These must always come before VS exports.
10524 * It is recommended to do these as early as possible. They can be at the beginning when
10525 * there is no SW GS and the shader doesn't write edge flags.
10529 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10530 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10532 Builder
bld(ctx
->program
, ctx
->block
);
10533 constexpr unsigned max_vertices_per_primitive
= 3;
10534 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10536 if (ctx
->stage
== ngg_vertex_gs
) {
10537 /* TODO: optimize for points & lines */
10538 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10539 if (ctx
->shader
->info
.tess
.point_mode
)
10540 num_vertices_per_primitive
= 1;
10541 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10542 num_vertices_per_primitive
= 2;
10544 unreachable("Unsupported NGG shader stage");
10547 Temp vtxindex
[max_vertices_per_primitive
];
10548 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10549 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10550 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10551 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10552 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10553 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10554 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10555 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10557 /* Export primitive data to the index buffer. */
10558 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10560 /* Export primitive ID. */
10561 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10562 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10563 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10564 Temp provoking_vtx_index
= vtxindex
[0];
10565 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10567 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10570 begin_divergent_if_else(ctx
, &ic
);
10571 end_divergent_if(ctx
, &ic
);
10574 void ngg_emit_nogs_output(isel_context
*ctx
)
10576 /* Emits NGG GS output, for stages that don't have SW GS. */
10579 Builder
bld(ctx
->program
, ctx
->block
);
10580 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10582 /* NGG streamout is currently disabled by default. */
10583 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10585 if (late_prim_export
) {
10586 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10587 create_export_phis(ctx
);
10588 /* Do what we need to do in the GS threads. */
10589 ngg_emit_nogs_gsthreads(ctx
);
10591 /* What comes next should be executed on ES threads. */
10592 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10593 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10594 bld
.reset(ctx
->block
);
10597 /* Export VS outputs */
10598 ctx
->block
->kind
|= block_kind_export_end
;
10599 create_vs_exports(ctx
);
10601 /* Export primitive ID */
10602 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10605 if (ctx
->stage
== ngg_vertex_gs
) {
10606 /* Wait for GS threads to store primitive ID in LDS. */
10607 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10608 bld
.sopp(aco_opcode::s_barrier
);
10610 /* Calculate LDS address where the GS threads stored the primitive ID. */
10611 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10612 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10613 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10614 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10615 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10616 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10618 /* Load primitive ID from LDS. */
10619 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10620 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10621 /* TES: Just use the patch ID as the primitive ID. */
10622 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10624 unreachable("unsupported NGG shader stage.");
10627 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10628 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10630 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10633 if (late_prim_export
) {
10634 begin_divergent_if_else(ctx
, &ic
);
10635 end_divergent_if(ctx
, &ic
);
10636 bld
.reset(ctx
->block
);
10640 void select_program(Program
*program
,
10641 unsigned shader_count
,
10642 struct nir_shader
*const *shaders
,
10643 ac_shader_config
* config
,
10644 struct radv_shader_args
*args
)
10646 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10647 if_context ic_merged_wave_info
;
10648 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10650 for (unsigned i
= 0; i
< shader_count
; i
++) {
10651 nir_shader
*nir
= shaders
[i
];
10652 init_context(&ctx
, nir
);
10654 setup_fp_mode(&ctx
, nir
);
10657 /* needs to be after init_context() for FS */
10658 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10659 append_logical_start(ctx
.block
);
10661 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10662 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10664 split_arguments(&ctx
, startpgm
);
10668 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10670 if (ngg_early_prim_export(&ctx
))
10671 ngg_emit_nogs_gsthreads(&ctx
);
10674 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10675 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10676 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10677 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10678 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10679 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10680 ctx
.stage
== tess_eval_geometry_gs
));
10682 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10683 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10684 if (check_merged_wave_info
) {
10685 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10686 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10690 Builder
bld(ctx
.program
, ctx
.block
);
10692 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10693 bld
.sopp(aco_opcode::s_barrier
);
10695 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10696 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10698 } else if (ctx
.stage
== geometry_gs
)
10699 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10701 if (ctx
.stage
== fragment_fs
)
10702 handle_bc_optimize(&ctx
);
10704 visit_cf_list(&ctx
, &func
->body
);
10706 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10707 emit_streamout(&ctx
, 0);
10709 if (ctx
.stage
& hw_vs
) {
10710 create_vs_exports(&ctx
);
10711 ctx
.block
->kind
|= block_kind_export_end
;
10712 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10713 ngg_emit_nogs_output(&ctx
);
10714 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10715 Builder
bld(ctx
.program
, ctx
.block
);
10716 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10717 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10718 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10719 write_tcs_tess_factors(&ctx
);
10722 if (ctx
.stage
== fragment_fs
) {
10723 create_fs_exports(&ctx
);
10724 ctx
.block
->kind
|= block_kind_export_end
;
10727 if (endif_merged_wave_info
) {
10728 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10729 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10732 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10733 ngg_emit_nogs_output(&ctx
);
10735 ralloc_free(ctx
.divergent_vals
);
10737 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10738 /* Outputs of the previous stage are inputs to the next stage */
10739 ctx
.inputs
= ctx
.outputs
;
10740 ctx
.outputs
= shader_io_state();
10744 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10746 append_logical_end(ctx
.block
);
10747 ctx
.block
->kind
|= block_kind_uniform
;
10748 Builder
bld(ctx
.program
, ctx
.block
);
10749 if (ctx
.program
->wb_smem_l1_on_end
)
10750 bld
.smem(aco_opcode::s_dcache_wb
, false);
10751 bld
.sopp(aco_opcode::s_endpgm
);
10753 cleanup_cfg(program
);
10756 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10757 ac_shader_config
* config
,
10758 struct radv_shader_args
*args
)
10760 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10762 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10763 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10764 program
->next_fp_mode
.must_flush_denorms32
= false;
10765 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10766 program
->next_fp_mode
.care_about_round32
= false;
10767 program
->next_fp_mode
.care_about_round16_64
= false;
10768 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10769 program
->next_fp_mode
.denorm32
= 0;
10770 program
->next_fp_mode
.round32
= fp_round_ne
;
10771 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10772 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10774 add_startpgm(&ctx
);
10775 append_logical_start(ctx
.block
);
10777 Builder
bld(ctx
.program
, ctx
.block
);
10779 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10781 Operand
stream_id(0u);
10782 if (args
->shader_info
->so
.num_outputs
)
10783 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10784 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10786 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10788 std::stack
<Block
> endif_blocks
;
10790 for (unsigned stream
= 0; stream
< 4; stream
++) {
10791 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10794 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10795 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10798 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10800 unsigned BB_if_idx
= ctx
.block
->index
;
10801 Block BB_endif
= Block();
10802 if (!stream_id
.isConstant()) {
10804 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10805 append_logical_end(ctx
.block
);
10806 ctx
.block
->kind
|= block_kind_uniform
;
10807 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10809 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10811 ctx
.block
= ctx
.program
->create_and_insert_block();
10812 add_edge(BB_if_idx
, ctx
.block
);
10813 bld
.reset(ctx
.block
);
10814 append_logical_start(ctx
.block
);
10817 unsigned offset
= 0;
10818 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10819 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10822 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10823 unsigned length
= util_last_bit(output_usage_mask
);
10824 for (unsigned j
= 0; j
< length
; ++j
) {
10825 if (!(output_usage_mask
& (1 << j
)))
10828 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10829 Temp voffset
= vtx_offset
;
10830 if (const_offset
>= 4096u) {
10831 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10832 const_offset
%= 4096u;
10835 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10836 mubuf
->definitions
[0] = bld
.def(v1
);
10837 mubuf
->operands
[0] = Operand(gsvs_ring
);
10838 mubuf
->operands
[1] = Operand(voffset
);
10839 mubuf
->operands
[2] = Operand(0u);
10840 mubuf
->offen
= true;
10841 mubuf
->offset
= const_offset
;
10844 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10845 mubuf
->barrier
= barrier_none
;
10846 mubuf
->can_reorder
= true;
10848 ctx
.outputs
.mask
[i
] |= 1 << j
;
10849 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10851 bld
.insert(std::move(mubuf
));
10857 if (args
->shader_info
->so
.num_outputs
) {
10858 emit_streamout(&ctx
, stream
);
10859 bld
.reset(ctx
.block
);
10863 create_vs_exports(&ctx
);
10864 ctx
.block
->kind
|= block_kind_export_end
;
10867 if (!stream_id
.isConstant()) {
10868 append_logical_end(ctx
.block
);
10870 /* branch from then block to endif block */
10871 bld
.branch(aco_opcode::p_branch
);
10872 add_edge(ctx
.block
->index
, &BB_endif
);
10873 ctx
.block
->kind
|= block_kind_uniform
;
10875 /* emit else block */
10876 ctx
.block
= ctx
.program
->create_and_insert_block();
10877 add_edge(BB_if_idx
, ctx
.block
);
10878 bld
.reset(ctx
.block
);
10879 append_logical_start(ctx
.block
);
10881 endif_blocks
.push(std::move(BB_endif
));
10885 while (!endif_blocks
.empty()) {
10886 Block BB_endif
= std::move(endif_blocks
.top());
10887 endif_blocks
.pop();
10889 Block
*BB_else
= ctx
.block
;
10891 append_logical_end(BB_else
);
10892 /* branch from else block to endif block */
10893 bld
.branch(aco_opcode::p_branch
);
10894 add_edge(BB_else
->index
, &BB_endif
);
10895 BB_else
->kind
|= block_kind_uniform
;
10897 /** emit endif merge block */
10898 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10899 bld
.reset(ctx
.block
);
10900 append_logical_start(ctx
.block
);
10903 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10905 append_logical_end(ctx
.block
);
10906 ctx
.block
->kind
|= block_kind_uniform
;
10907 bld
.sopp(aco_opcode::s_endpgm
);
10909 cleanup_cfg(program
);