2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "vulkan/radv_shader.h"
30 #include "vulkan/radv_descriptor_set.h"
31 #include "vulkan/radv_shader_args.h"
33 #include "ac_exp_param.h"
34 #include "ac_shader_util.h"
36 #include "util/u_math.h"
38 #define MAX_INLINE_PUSH_CONSTS 8
42 struct ge_output_state
{
43 uint8_t mask
[VARYING_SLOT_VAR31
+ 1];
44 Temp outputs
[VARYING_SLOT_VAR31
+ 1][4];
48 const struct radv_nir_compiler_options
*options
;
49 struct radv_shader_args
*args
;
52 uint32_t constant_data_offset
;
55 std::unique_ptr
<Temp
[]> allocated
;
56 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
57 Stage stage
; /* Stage */
58 bool has_gfx10_wave64_bpermute
= false;
61 uint16_t loop_nest_depth
= 0;
65 bool has_divergent_continue
= false;
66 bool has_divergent_branch
= false;
69 bool is_divergent
= false;
71 bool exec_potentially_empty
= false;
72 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
75 Temp arg_temps
[AC_MAX_ARGS
];
78 Temp persp_centroid
, linear_centroid
;
81 bool needs_instance_id
;
86 /* gathered information */
87 uint64_t input_masks
[MESA_SHADER_COMPUTE
];
88 uint64_t output_masks
[MESA_SHADER_COMPUTE
];
90 /* VS output information */
91 unsigned num_clip_distances
;
92 unsigned num_cull_distances
;
94 /* VS or GS output information */
95 ge_output_state vsgs_output
;
98 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
101 return ctx
->arg_temps
[arg
.arg_index
];
104 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
107 case INTERP_MODE_SMOOTH
:
108 case INTERP_MODE_NONE
:
109 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
110 intrin
== nir_intrinsic_load_barycentric_at_sample
||
111 intrin
== nir_intrinsic_load_barycentric_at_offset
)
112 return S_0286CC_PERSP_CENTER_ENA(1);
113 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
114 return S_0286CC_PERSP_CENTROID_ENA(1);
115 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
116 return S_0286CC_PERSP_SAMPLE_ENA(1);
118 case INTERP_MODE_NOPERSPECTIVE
:
119 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
120 return S_0286CC_LINEAR_CENTER_ENA(1);
121 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
122 return S_0286CC_LINEAR_CENTROID_ENA(1);
123 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
124 return S_0286CC_LINEAR_SAMPLE_ENA(1);
132 void init_context(isel_context
*ctx
, nir_shader
*shader
)
134 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
135 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
137 ctx
->shader
= shader
;
138 ctx
->divergent_vals
= nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
140 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
142 unsigned spi_ps_inputs
= 0;
144 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
149 nir_foreach_block(block
, impl
) {
150 nir_foreach_instr(instr
, block
) {
151 switch(instr
->type
) {
152 case nir_instr_type_alu
: {
153 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
154 unsigned size
= alu_instr
->dest
.dest
.ssa
.num_components
;
155 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 64)
157 RegType type
= RegType::sgpr
;
158 switch(alu_instr
->op
) {
180 case nir_op_fround_even
:
189 case nir_op_pack_half_2x16
:
190 case nir_op_unpack_half_2x16_split_x
:
191 case nir_op_unpack_half_2x16_split_y
:
194 case nir_op_fddx_fine
:
195 case nir_op_fddy_fine
:
196 case nir_op_fddx_coarse
:
197 case nir_op_fddy_coarse
:
198 case nir_op_fquantize2f16
:
200 case nir_op_frexp_sig
:
201 case nir_op_frexp_exp
:
202 case nir_op_cube_face_index
:
203 case nir_op_cube_face_coord
:
204 type
= RegType::vgpr
;
217 size
= lane_mask_size
;
225 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
228 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
229 size
= lane_mask_size
;
231 if (ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
]) {
232 type
= RegType::vgpr
;
234 if (allocated
[alu_instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
||
235 allocated
[alu_instr
->src
[2].src
.ssa
->index
].type() == RegType::vgpr
) {
236 type
= RegType::vgpr
;
239 if (alu_instr
->src
[1].src
.ssa
->num_components
== 1 && alu_instr
->src
[2].src
.ssa
->num_components
== 1) {
240 assert(allocated
[alu_instr
->src
[1].src
.ssa
->index
].size() == allocated
[alu_instr
->src
[2].src
.ssa
->index
].size());
241 size
= allocated
[alu_instr
->src
[1].src
.ssa
->index
].size();
246 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
247 size
= lane_mask_size
;
249 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
253 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
254 size
= lane_mask_size
;
256 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
257 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
258 type
= RegType::vgpr
;
263 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
266 case nir_instr_type_load_const
: {
267 unsigned size
= nir_instr_as_load_const(instr
)->def
.num_components
;
268 if (nir_instr_as_load_const(instr
)->def
.bit_size
== 64)
270 else if (nir_instr_as_load_const(instr
)->def
.bit_size
== 1)
271 size
*= lane_mask_size
;
272 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
275 case nir_instr_type_intrinsic
: {
276 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
277 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
279 unsigned size
= intrinsic
->dest
.ssa
.num_components
;
280 if (intrinsic
->dest
.ssa
.bit_size
== 64)
282 RegType type
= RegType::sgpr
;
283 switch(intrinsic
->intrinsic
) {
284 case nir_intrinsic_load_push_constant
:
285 case nir_intrinsic_load_work_group_id
:
286 case nir_intrinsic_load_num_work_groups
:
287 case nir_intrinsic_load_subgroup_id
:
288 case nir_intrinsic_load_num_subgroups
:
289 case nir_intrinsic_load_first_vertex
:
290 case nir_intrinsic_load_base_instance
:
291 case nir_intrinsic_get_buffer_size
:
292 case nir_intrinsic_vote_all
:
293 case nir_intrinsic_vote_any
:
294 case nir_intrinsic_read_first_invocation
:
295 case nir_intrinsic_read_invocation
:
296 case nir_intrinsic_first_invocation
:
297 type
= RegType::sgpr
;
298 if (intrinsic
->dest
.ssa
.bit_size
== 1)
299 size
= lane_mask_size
;
301 case nir_intrinsic_ballot
:
302 type
= RegType::sgpr
;
304 case nir_intrinsic_load_sample_id
:
305 case nir_intrinsic_load_sample_mask_in
:
306 case nir_intrinsic_load_input
:
307 case nir_intrinsic_load_per_vertex_input
:
308 case nir_intrinsic_load_vertex_id
:
309 case nir_intrinsic_load_vertex_id_zero_base
:
310 case nir_intrinsic_load_barycentric_sample
:
311 case nir_intrinsic_load_barycentric_pixel
:
312 case nir_intrinsic_load_barycentric_centroid
:
313 case nir_intrinsic_load_barycentric_at_sample
:
314 case nir_intrinsic_load_barycentric_at_offset
:
315 case nir_intrinsic_load_interpolated_input
:
316 case nir_intrinsic_load_frag_coord
:
317 case nir_intrinsic_load_sample_pos
:
318 case nir_intrinsic_load_layer_id
:
319 case nir_intrinsic_load_local_invocation_id
:
320 case nir_intrinsic_load_local_invocation_index
:
321 case nir_intrinsic_load_subgroup_invocation
:
322 case nir_intrinsic_write_invocation_amd
:
323 case nir_intrinsic_mbcnt_amd
:
324 case nir_intrinsic_load_instance_id
:
325 case nir_intrinsic_ssbo_atomic_add
:
326 case nir_intrinsic_ssbo_atomic_imin
:
327 case nir_intrinsic_ssbo_atomic_umin
:
328 case nir_intrinsic_ssbo_atomic_imax
:
329 case nir_intrinsic_ssbo_atomic_umax
:
330 case nir_intrinsic_ssbo_atomic_and
:
331 case nir_intrinsic_ssbo_atomic_or
:
332 case nir_intrinsic_ssbo_atomic_xor
:
333 case nir_intrinsic_ssbo_atomic_exchange
:
334 case nir_intrinsic_ssbo_atomic_comp_swap
:
335 case nir_intrinsic_global_atomic_add
:
336 case nir_intrinsic_global_atomic_imin
:
337 case nir_intrinsic_global_atomic_umin
:
338 case nir_intrinsic_global_atomic_imax
:
339 case nir_intrinsic_global_atomic_umax
:
340 case nir_intrinsic_global_atomic_and
:
341 case nir_intrinsic_global_atomic_or
:
342 case nir_intrinsic_global_atomic_xor
:
343 case nir_intrinsic_global_atomic_exchange
:
344 case nir_intrinsic_global_atomic_comp_swap
:
345 case nir_intrinsic_image_deref_atomic_add
:
346 case nir_intrinsic_image_deref_atomic_umin
:
347 case nir_intrinsic_image_deref_atomic_imin
:
348 case nir_intrinsic_image_deref_atomic_umax
:
349 case nir_intrinsic_image_deref_atomic_imax
:
350 case nir_intrinsic_image_deref_atomic_and
:
351 case nir_intrinsic_image_deref_atomic_or
:
352 case nir_intrinsic_image_deref_atomic_xor
:
353 case nir_intrinsic_image_deref_atomic_exchange
:
354 case nir_intrinsic_image_deref_atomic_comp_swap
:
355 case nir_intrinsic_image_deref_size
:
356 case nir_intrinsic_shared_atomic_add
:
357 case nir_intrinsic_shared_atomic_imin
:
358 case nir_intrinsic_shared_atomic_umin
:
359 case nir_intrinsic_shared_atomic_imax
:
360 case nir_intrinsic_shared_atomic_umax
:
361 case nir_intrinsic_shared_atomic_and
:
362 case nir_intrinsic_shared_atomic_or
:
363 case nir_intrinsic_shared_atomic_xor
:
364 case nir_intrinsic_shared_atomic_exchange
:
365 case nir_intrinsic_shared_atomic_comp_swap
:
366 case nir_intrinsic_load_scratch
:
367 case nir_intrinsic_load_invocation_id
:
368 case nir_intrinsic_load_primitive_id
:
369 type
= RegType::vgpr
;
371 case nir_intrinsic_shuffle
:
372 case nir_intrinsic_quad_broadcast
:
373 case nir_intrinsic_quad_swap_horizontal
:
374 case nir_intrinsic_quad_swap_vertical
:
375 case nir_intrinsic_quad_swap_diagonal
:
376 case nir_intrinsic_quad_swizzle_amd
:
377 case nir_intrinsic_masked_swizzle_amd
:
378 case nir_intrinsic_inclusive_scan
:
379 case nir_intrinsic_exclusive_scan
:
380 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
381 size
= lane_mask_size
;
382 type
= RegType::sgpr
;
383 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
384 type
= RegType::sgpr
;
386 type
= RegType::vgpr
;
389 case nir_intrinsic_load_view_index
:
390 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
392 case nir_intrinsic_load_front_face
:
393 case nir_intrinsic_load_helper_invocation
:
394 case nir_intrinsic_is_helper_invocation
:
395 type
= RegType::sgpr
;
396 size
= lane_mask_size
;
398 case nir_intrinsic_reduce
:
399 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
400 size
= lane_mask_size
;
401 type
= RegType::sgpr
;
402 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
403 type
= RegType::sgpr
;
405 type
= RegType::vgpr
;
408 case nir_intrinsic_load_ubo
:
409 case nir_intrinsic_load_ssbo
:
410 case nir_intrinsic_load_global
:
411 case nir_intrinsic_vulkan_resource_index
:
412 type
= ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
414 /* due to copy propagation, the swizzled imov is removed if num dest components == 1 */
415 case nir_intrinsic_load_shared
:
416 if (ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
])
417 type
= RegType::vgpr
;
419 type
= RegType::sgpr
;
422 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
423 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
424 type
= RegType::vgpr
;
428 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
430 switch(intrinsic
->intrinsic
) {
431 case nir_intrinsic_load_barycentric_sample
:
432 case nir_intrinsic_load_barycentric_pixel
:
433 case nir_intrinsic_load_barycentric_centroid
:
434 case nir_intrinsic_load_barycentric_at_sample
:
435 case nir_intrinsic_load_barycentric_at_offset
: {
436 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
437 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
440 case nir_intrinsic_load_front_face
:
441 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
443 case nir_intrinsic_load_frag_coord
:
444 case nir_intrinsic_load_sample_pos
: {
445 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
446 for (unsigned i
= 0; i
< 4; i
++) {
448 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
453 case nir_intrinsic_load_sample_id
:
454 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
456 case nir_intrinsic_load_sample_mask_in
:
457 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
458 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
465 case nir_instr_type_tex
: {
466 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
467 unsigned size
= tex
->dest
.ssa
.num_components
;
469 if (tex
->dest
.ssa
.bit_size
== 64)
471 if (tex
->op
== nir_texop_texture_samples
)
472 assert(!ctx
->divergent_vals
[tex
->dest
.ssa
.index
]);
473 if (ctx
->divergent_vals
[tex
->dest
.ssa
.index
])
474 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
476 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
479 case nir_instr_type_parallel_copy
: {
480 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
481 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
485 case nir_instr_type_ssa_undef
: {
486 unsigned size
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
487 if (nir_instr_as_ssa_undef(instr
)->def
.bit_size
== 64)
489 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
492 case nir_instr_type_phi
: {
493 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
495 unsigned size
= phi
->dest
.ssa
.num_components
;
497 if (phi
->dest
.ssa
.bit_size
== 1) {
498 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
499 type
= RegType::sgpr
;
500 size
*= lane_mask_size
;
501 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
505 if (ctx
->divergent_vals
[phi
->dest
.ssa
.index
]) {
506 type
= RegType::vgpr
;
508 type
= RegType::sgpr
;
509 nir_foreach_phi_src (src
, phi
) {
510 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
511 type
= RegType::vgpr
;
512 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
517 size
*= phi
->dest
.ssa
.bit_size
== 64 ? 2 : 1;
518 RegClass rc
= RegClass(type
, size
);
519 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
522 nir_foreach_phi_src(src
, phi
)
523 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
525 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
535 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
536 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
537 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
540 if (!(spi_ps_inputs
& 0x7F)) {
541 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
542 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
545 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
546 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
548 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
549 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
551 ctx
->allocated
.reset(allocated
.release());
552 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
555 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
557 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
558 if (ctx
->stage
== fragment_fs
) {
559 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
560 * itself and then communicates the results back via the ELF binary.
561 * Mirror what LLVM does by re-mapping the VGPR arguments here.
563 * TODO: If we made the FS input scanning code into a separate pass that
564 * could run before argument setup, then this wouldn't be necessary
567 struct ac_shader_args
*args
= &ctx
->args
->ac
;
569 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
570 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
575 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
576 args
->args
[i
].skip
= true;
578 args
->args
[i
].offset
= vgpr_reg
;
579 vgpr_reg
+= args
->args
[i
].size
;
586 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
587 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
588 if (ctx
->args
->ac
.args
[i
].skip
)
591 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
592 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
593 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
594 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
595 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
596 ctx
->arg_temps
[i
] = dst
;
597 startpgm
->definitions
[arg
] = Definition(dst
);
598 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
601 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
602 Pseudo_instruction
*instr
= startpgm
.get();
603 ctx
->block
->instructions
.push_back(std::move(startpgm
));
605 /* Stash these in the program so that they can be accessed later when
608 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
609 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
615 type_size(const struct glsl_type
*type
, bool bindless
)
617 // TODO: don't we need type->std430_base_alignment() here?
618 return glsl_count_attribute_slots(type
, false);
622 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
624 assert(glsl_type_is_vector_or_scalar(type
));
626 uint32_t comp_size
= glsl_type_is_boolean(type
)
627 ? 4 : glsl_get_bit_size(type
) / 8;
628 unsigned length
= glsl_get_vector_elements(type
);
629 *size
= comp_size
* length
,
634 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
635 unsigned num_components
, unsigned high_offset
,
636 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
638 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
641 /* >128 bit loads are split except with SMEM */
642 if (bit_size
* num_components
> 128)
645 switch (low
->intrinsic
) {
646 case nir_intrinsic_load_ubo
:
647 case nir_intrinsic_load_ssbo
:
648 case nir_intrinsic_store_ssbo
:
649 case nir_intrinsic_load_push_constant
:
650 return align
% 4 == 0;
651 case nir_intrinsic_load_deref
:
652 case nir_intrinsic_store_deref
:
653 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
655 case nir_intrinsic_load_shared
:
656 case nir_intrinsic_store_shared
:
657 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
658 return align
% 16 == 0;
660 return align
% 4 == 0;
668 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
670 nir_foreach_variable(variable
, &nir
->inputs
)
672 variable
->data
.driver_location
= variable
->data
.location
* 4;
674 nir_foreach_variable(variable
, &nir
->outputs
)
676 if (ctx
->stage
== vertex_geometry_gs
)
677 variable
->data
.driver_location
= util_bitcount64(ctx
->output_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
678 else if (ctx
->stage
== vertex_es
)
679 //TODO: make this more compact
680 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
)variable
->data
.location
) * 4;
682 variable
->data
.driver_location
= variable
->data
.location
* 4;
685 if (ctx
->stage
== vertex_vs
) {
686 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
688 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
689 sizeof(outinfo
->vs_output_param_offset
));
691 ctx
->needs_instance_id
= ctx
->program
->info
->vs
.needs_instance_id
;
693 bool export_clip_dists
= ctx
->options
->key
.vs_common_out
.export_clip_dists
;
695 outinfo
->param_exports
= 0;
696 int pos_written
= 0x1;
697 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
698 pos_written
|= 1 << 1;
700 uint64_t mask
= ctx
->output_masks
[nir
->info
.stage
];
702 int idx
= u_bit_scan64(&mask
);
703 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
|| idx
== VARYING_SLOT_PRIMITIVE_ID
||
704 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
705 if (outinfo
->vs_output_param_offset
[idx
] == AC_EXP_PARAM_UNDEFINED
)
706 outinfo
->vs_output_param_offset
[idx
] = outinfo
->param_exports
++;
709 if (outinfo
->writes_layer
&&
710 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
711 /* when ctx->options->key.has_multiview_view_index = true, the layer
712 * variable isn't declared in NIR and it's isel's job to get the layer */
713 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
716 if (outinfo
->export_prim_id
) {
717 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
718 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
721 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
722 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
724 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
726 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
727 pos_written
|= 1 << 2;
728 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
729 pos_written
|= 1 << 3;
731 outinfo
->pos_exports
= util_bitcount(pos_written
);
732 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== vertex_es
) {
733 /* TODO: radv_nir_shader_info_pass() already sets this but it's larger
734 * than it needs to be in order to set it better, we have to improve
735 * radv_nir_shader_info_pass() because gfx9_get_gs_info() uses
736 * esgs_itemsize and has to be done before compilation
738 /* radv_es_output_info *outinfo = &ctx->program->info->vs.es_info;
739 outinfo->esgs_itemsize = util_bitcount64(ctx->output_masks[nir->info.stage]) * 16u; */
744 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
746 switch (nir
->info
.stage
) {
747 case MESA_SHADER_FRAGMENT
: {
748 nir_foreach_variable(variable
, &nir
->outputs
)
750 int idx
= variable
->data
.location
+ variable
->data
.index
;
751 variable
->data
.driver_location
= idx
* 4;
755 case MESA_SHADER_COMPUTE
: {
756 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
757 ctx
->program
->lds_alloc_granule
;
760 case MESA_SHADER_VERTEX
: {
761 setup_vs_variables(ctx
, nir
);
764 case MESA_SHADER_GEOMETRY
: {
765 assert(ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== geometry_gs
);
766 if (ctx
->stage
== vertex_geometry_gs
) {
767 nir_foreach_variable(variable
, &nir
->inputs
) {
768 variable
->data
.driver_location
= util_bitcount64(ctx
->input_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
771 //TODO: make this more compact
772 nir_foreach_variable(variable
, &nir
->inputs
) {
773 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
)variable
->data
.location
) * 4;
776 nir_foreach_variable(variable
, &nir
->outputs
) {
777 variable
->data
.driver_location
= variable
->data
.location
* 4;
779 if (ctx
->stage
== vertex_geometry_gs
)
780 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_VERTEX
; /* tesselation shaders are not yet supported */
784 unreachable("Unhandled shader stage.");
789 get_io_masks(isel_context
*ctx
, unsigned shader_count
, struct nir_shader
*const *shaders
)
791 for (unsigned i
= 0; i
< shader_count
; i
++) {
792 nir_shader
*nir
= shaders
[i
];
793 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
796 uint64_t output_mask
= 0;
797 nir_foreach_variable(variable
, &nir
->outputs
) {
798 const glsl_type
*type
= variable
->type
;
799 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
800 type
= type
->fields
.array
;
801 unsigned slots
= type
->count_attribute_slots(false);
802 if (variable
->data
.compact
) {
803 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
804 slots
= (component_count
+ 3) / 4;
806 output_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
809 uint64_t input_mask
= 0;
810 nir_foreach_variable(variable
, &nir
->inputs
) {
811 const glsl_type
*type
= variable
->type
;
812 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
813 type
= type
->fields
.array
;
814 unsigned slots
= type
->count_attribute_slots(false);
815 if (variable
->data
.compact
) {
816 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
817 slots
= (component_count
+ 3) / 4;
819 input_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
822 ctx
->output_masks
[nir
->info
.stage
] |= output_mask
;
823 if (i
+ 1 < shader_count
)
824 ctx
->input_masks
[shaders
[i
+ 1]->info
.stage
] |= output_mask
;
826 ctx
->input_masks
[nir
->info
.stage
] |= input_mask
;
828 ctx
->output_masks
[shaders
[i
- 1]->info
.stage
] |= input_mask
;
833 setup_isel_context(Program
* program
,
834 unsigned shader_count
,
835 struct nir_shader
*const *shaders
,
836 ac_shader_config
* config
,
837 struct radv_shader_args
*args
)
840 for (unsigned i
= 0; i
< shader_count
; i
++) {
841 switch (shaders
[i
]->info
.stage
) {
842 case MESA_SHADER_VERTEX
:
843 program
->stage
|= sw_vs
;
845 case MESA_SHADER_TESS_CTRL
:
846 program
->stage
|= sw_tcs
;
848 case MESA_SHADER_TESS_EVAL
:
849 program
->stage
|= sw_tes
;
851 case MESA_SHADER_GEOMETRY
:
852 program
->stage
|= sw_gs
;
854 case MESA_SHADER_FRAGMENT
:
855 program
->stage
|= sw_fs
;
857 case MESA_SHADER_COMPUTE
:
858 program
->stage
|= sw_cs
;
861 unreachable("Shader stage not implemented");
864 bool gfx9_plus
= args
->options
->chip_class
>= GFX9
;
865 bool ngg
= args
->shader_info
->is_ngg
&& args
->options
->chip_class
>= GFX10
;
866 if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_es
)
867 program
->stage
|= hw_es
;
868 else if (program
->stage
== sw_vs
&& !args
->shader_info
->vs
.as_ls
)
869 program
->stage
|= hw_vs
;
870 else if (program
->stage
== sw_gs
)
871 program
->stage
|= hw_gs
;
872 else if (program
->stage
== sw_fs
)
873 program
->stage
|= hw_fs
;
874 else if (program
->stage
== sw_cs
)
875 program
->stage
|= hw_cs
;
876 else if (program
->stage
== (sw_vs
| sw_gs
) && gfx9_plus
&& !ngg
)
877 program
->stage
|= hw_gs
;
879 unreachable("Shader stage not implemented");
881 program
->config
= config
;
882 program
->info
= args
->shader_info
;
883 program
->chip_class
= args
->options
->chip_class
;
884 program
->family
= args
->options
->family
;
885 program
->wave_size
= args
->shader_info
->wave_size
;
886 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
888 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
889 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
890 program
->vgpr_limit
= 256;
891 program
->vgpr_alloc_granule
= 3;
893 if (args
->options
->chip_class
>= GFX10
) {
894 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
895 program
->sgpr_alloc_granule
= 127;
896 program
->sgpr_limit
= 106;
897 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
898 } else if (program
->chip_class
>= GFX8
) {
899 program
->physical_sgprs
= 800;
900 program
->sgpr_alloc_granule
= 15;
901 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
902 program
->sgpr_limit
= 94; /* workaround hardware bug */
904 program
->sgpr_limit
= 102;
906 program
->physical_sgprs
= 512;
907 program
->sgpr_alloc_granule
= 7;
908 program
->sgpr_limit
= 104;
911 /* TODO: we don't have to allocate VCC if we don't need it */
912 program
->needs_vcc
= true;
914 calc_min_waves(program
);
915 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
916 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
918 isel_context ctx
= {};
919 ctx
.program
= program
;
921 ctx
.options
= args
->options
;
922 ctx
.stage
= program
->stage
;
924 get_io_masks(&ctx
, shader_count
, shaders
);
926 for (unsigned i
= 0; i
< shader_count
; i
++) {
927 nir_shader
*nir
= shaders
[i
];
929 /* align and copy constant data */
930 while (program
->constant_data
.size() % 4u)
931 program
->constant_data
.push_back(0);
932 ctx
.constant_data_offset
= program
->constant_data
.size();
933 program
->constant_data
.insert(program
->constant_data
.end(),
934 (uint8_t*)nir
->constant_data
,
935 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
937 /* the variable setup has to be done before lower_io / CSE */
938 setup_variables(&ctx
, nir
);
940 /* optimize and lower memory operations */
941 bool lower_to_scalar
= false;
942 bool lower_pack
= false;
943 if (nir_opt_load_store_vectorize(nir
,
944 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
945 nir_var_mem_push_const
| nir_var_mem_shared
),
946 mem_vectorize_callback
)) {
947 lower_to_scalar
= true;
950 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
951 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
952 nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
);
955 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
959 /* lower ALU operations */
960 // TODO: implement logic64 in aco, it's more effective for sgprs
961 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
963 nir_opt_idiv_const(nir
, 32);
964 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
966 /* optimize the lowered ALU operations */
967 bool more_algebraic
= true;
968 while (more_algebraic
) {
969 more_algebraic
= false;
970 NIR_PASS_V(nir
, nir_copy_prop
);
971 NIR_PASS_V(nir
, nir_opt_dce
);
972 NIR_PASS_V(nir
, nir_opt_constant_folding
);
973 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
976 /* Do late algebraic optimization to turn add(a, neg(b)) back into
977 * subs, then the mandatory cleanup after algebraic. Note that it may
978 * produce fnegs, and if so then we need to keep running to squash
981 bool more_late_algebraic
= true;
982 while (more_late_algebraic
) {
983 more_late_algebraic
= false;
984 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
985 NIR_PASS_V(nir
, nir_opt_constant_folding
);
986 NIR_PASS_V(nir
, nir_copy_prop
);
987 NIR_PASS_V(nir
, nir_opt_dce
);
988 NIR_PASS_V(nir
, nir_opt_cse
);
992 nir_lower_load_const_to_scalar(nir
);
993 nir_opt_shrink_load(nir
);
994 nir_move_options move_opts
= (nir_move_options
)(
995 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
| nir_move_comparisons
);
996 nir_opt_sink(nir
, move_opts
);
997 nir_opt_move(nir
, move_opts
);
998 nir_convert_to_lcssa(nir
, true, false);
999 nir_lower_phis_to_scalar(nir
);
1001 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
1002 nir_index_ssa_defs(func
);
1003 nir_metadata_require(func
, nir_metadata_block_index
);
1005 if (args
->options
->dump_preoptir
) {
1006 fprintf(stderr
, "NIR shader before instruction selection:\n");
1007 nir_print_shader(nir
, stderr
);
1011 unsigned scratch_size
= 0;
1012 for (unsigned i
= 0; i
< shader_count
; i
++)
1013 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
1014 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
1016 ctx
.block
= ctx
.program
->create_and_insert_block();
1017 ctx
.block
->loop_nest_depth
= 0;
1018 ctx
.block
->kind
= block_kind_top_level
;