2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "nir_control_flow.h"
30 #include "vulkan/radv_shader.h"
31 #include "vulkan/radv_descriptor_set.h"
32 #include "vulkan/radv_shader_args.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
37 #include "util/u_math.h"
39 #define MAX_INLINE_PUSH_CONSTS 8
43 struct shader_io_state
{
44 uint8_t mask
[VARYING_SLOT_MAX
];
45 Temp temps
[VARYING_SLOT_MAX
* 4u];
48 memset(mask
, 0, sizeof(mask
));
49 std::fill_n(temps
, VARYING_SLOT_MAX
* 4u, Temp(0, RegClass::v1
));
54 has_glc_vmem_load
= 0x1,
55 has_nonglc_vmem_load
= 0x2,
56 has_glc_vmem_store
= 0x4,
57 has_nonglc_vmem_store
= 0x8,
59 has_vmem_store
= has_glc_vmem_store
| has_nonglc_vmem_store
,
60 has_vmem_loadstore
= has_vmem_store
| has_glc_vmem_load
| has_nonglc_vmem_load
,
61 has_nonglc_vmem_loadstore
= has_nonglc_vmem_load
| has_nonglc_vmem_store
,
63 buffer_is_restrict
= 0x10,
67 const struct radv_nir_compiler_options
*options
;
68 struct radv_shader_args
*args
;
71 uint32_t constant_data_offset
;
73 std::unique_ptr
<Temp
[]> allocated
;
74 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
75 Stage stage
; /* Stage */
76 bool has_gfx10_wave64_bpermute
= false;
79 uint16_t loop_nest_depth
= 0;
83 bool has_divergent_continue
= false;
84 bool has_divergent_branch
= false;
87 bool is_divergent
= false;
89 bool exec_potentially_empty_discard
= false; /* set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
90 uint16_t exec_potentially_empty_break_depth
= UINT16_MAX
;
91 /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
92 * and parent_if.is_divergent==false. Called _break but it's also used for
94 bool exec_potentially_empty_break
= false;
95 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
98 uint32_t resource_flag_offsets
[MAX_SETS
];
99 std::vector
<uint8_t> buffer_resource_flags
;
101 Temp arg_temps
[AC_MAX_ARGS
];
104 Temp persp_centroid
, linear_centroid
;
109 /* VS output information */
110 bool export_clip_dists
;
111 unsigned num_clip_distances
;
112 unsigned num_cull_distances
;
114 /* tessellation information */
115 unsigned tcs_tess_lvl_out_loc
;
116 unsigned tcs_tess_lvl_in_loc
;
117 uint64_t tcs_temp_only_inputs
;
118 uint32_t tcs_num_inputs
;
119 uint32_t tcs_num_outputs
;
120 uint32_t tcs_num_patch_outputs
;
121 uint32_t tcs_num_patches
;
122 bool tcs_in_out_eq
= false;
124 /* I/O information */
125 shader_io_state inputs
;
126 shader_io_state outputs
;
127 uint8_t output_drv_loc_to_var_slot
[MESA_SHADER_COMPUTE
][VARYING_SLOT_MAX
];
128 uint8_t output_tcs_patch_drv_loc_to_var_slot
[VARYING_SLOT_MAX
];
131 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
134 return ctx
->arg_temps
[arg
.arg_index
];
137 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
140 case INTERP_MODE_SMOOTH
:
141 case INTERP_MODE_NONE
:
142 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
143 intrin
== nir_intrinsic_load_barycentric_at_sample
||
144 intrin
== nir_intrinsic_load_barycentric_at_offset
)
145 return S_0286CC_PERSP_CENTER_ENA(1);
146 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
147 return S_0286CC_PERSP_CENTROID_ENA(1);
148 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
149 return S_0286CC_PERSP_SAMPLE_ENA(1);
151 case INTERP_MODE_NOPERSPECTIVE
:
152 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
153 return S_0286CC_LINEAR_CENTER_ENA(1);
154 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
155 return S_0286CC_LINEAR_CENTROID_ENA(1);
156 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
157 return S_0286CC_LINEAR_SAMPLE_ENA(1);
165 /* If one side of a divergent IF ends in a branch and the other doesn't, we
166 * might have to emit the contents of the side without the branch at the merge
167 * block instead. This is so that we can use any SGPR live-out of the side
168 * without the branch without creating a linear phi in the invert or merge block. */
170 sanitize_if(nir_function_impl
*impl
, nir_if
*nif
)
172 //TODO: skip this if the condition is uniform and there are no divergent breaks/continues?
174 nir_block
*then_block
= nir_if_last_then_block(nif
);
175 nir_block
*else_block
= nir_if_last_else_block(nif
);
176 bool then_jump
= nir_block_ends_in_jump(then_block
) || nir_block_is_unreachable(then_block
);
177 bool else_jump
= nir_block_ends_in_jump(else_block
) || nir_block_is_unreachable(else_block
);
178 if (then_jump
== else_jump
)
181 /* If the continue from block is empty then return as there is nothing to
184 if (nir_cf_list_is_empty_block(else_jump
? &nif
->then_list
: &nif
->else_list
))
187 /* Even though this if statement has a jump on one side, we may still have
188 * phis afterwards. Single-source phis can be produced by loop unrolling
189 * or dead control-flow passes and are perfectly legal. Run a quick phi
190 * removal on the block after the if to clean up any such phis.
192 nir_opt_remove_phis_block(nir_cf_node_as_block(nir_cf_node_next(&nif
->cf_node
)));
194 /* Finally, move the continue from branch after the if-statement. */
195 nir_block
*last_continue_from_blk
= else_jump
? then_block
: else_block
;
196 nir_block
*first_continue_from_blk
= else_jump
?
197 nir_if_first_then_block(nif
) : nir_if_first_else_block(nif
);
200 nir_cf_extract(&tmp
, nir_before_block(first_continue_from_blk
),
201 nir_after_block(last_continue_from_blk
));
202 nir_cf_reinsert(&tmp
, nir_after_cf_node(&nif
->cf_node
));
204 /* nir_cf_extract() invalidates dominance metadata, but it should still be
205 * correct because of the specific type of transformation we did. Block
206 * indices are not valid except for block_0's, which is all we care about for
207 * nir_block_is_unreachable(). */
208 impl
->valid_metadata
=
209 (nir_metadata
)(impl
->valid_metadata
| nir_metadata_dominance
| nir_metadata_block_index
);
215 sanitize_cf_list(nir_function_impl
*impl
, struct exec_list
*cf_list
)
217 bool progress
= false;
218 foreach_list_typed(nir_cf_node
, cf_node
, node
, cf_list
) {
219 switch (cf_node
->type
) {
220 case nir_cf_node_block
:
222 case nir_cf_node_if
: {
223 nir_if
*nif
= nir_cf_node_as_if(cf_node
);
224 progress
|= sanitize_cf_list(impl
, &nif
->then_list
);
225 progress
|= sanitize_cf_list(impl
, &nif
->else_list
);
226 progress
|= sanitize_if(impl
, nif
);
229 case nir_cf_node_loop
: {
230 nir_loop
*loop
= nir_cf_node_as_loop(cf_node
);
231 progress
|= sanitize_cf_list(impl
, &loop
->body
);
234 case nir_cf_node_function
:
235 unreachable("Invalid cf type");
242 void get_buffer_resource_flags(isel_context
*ctx
, nir_ssa_def
*def
, unsigned access
,
243 uint8_t **flags
, uint32_t *count
)
246 unsigned binding
= 0;
249 /* global resources are considered aliasing with all other buffers and
251 // TODO: only merge flags of resources which can really alias.
252 } else if (def
->parent_instr
->type
== nir_instr_type_intrinsic
) {
253 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(def
->parent_instr
);
254 if (intrin
->intrinsic
== nir_intrinsic_vulkan_resource_index
) {
255 desc_set
= nir_intrinsic_desc_set(intrin
);
256 binding
= nir_intrinsic_binding(intrin
);
258 } else if (def
->parent_instr
->type
== nir_instr_type_deref
) {
259 nir_deref_instr
*deref
= nir_instr_as_deref(def
->parent_instr
);
260 assert(deref
->type
->is_image());
261 if (deref
->type
->sampler_dimensionality
!= GLSL_SAMPLER_DIM_BUF
) {
267 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
268 desc_set
= var
->data
.descriptor_set
;
269 binding
= var
->data
.binding
;
273 *flags
= ctx
->buffer_resource_flags
.data();
274 *count
= ctx
->buffer_resource_flags
.size();
278 unsigned set_offset
= ctx
->resource_flag_offsets
[desc_set
];
280 if (!(ctx
->buffer_resource_flags
[set_offset
+ binding
] & buffer_is_restrict
)) {
281 /* Non-restrict buffers alias only with other non-restrict buffers.
282 * We reserve flags[0] for these. */
283 *flags
= ctx
->buffer_resource_flags
.data();
288 *flags
= ctx
->buffer_resource_flags
.data() + set_offset
+ binding
;
292 uint8_t get_all_buffer_resource_flags(isel_context
*ctx
, nir_ssa_def
*def
, unsigned access
)
296 get_buffer_resource_flags(ctx
, def
, access
, &flags
, &count
);
299 for (unsigned i
= 0; i
< count
; i
++)
304 void fill_desc_set_info(isel_context
*ctx
, nir_function_impl
*impl
)
306 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
308 unsigned resource_flag_count
= 1; /* +1 to reserve flags[0] for aliased resources */
309 for (unsigned i
= 0; i
< pipeline_layout
->num_sets
; i
++) {
310 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[i
].layout
;
311 ctx
->resource_flag_offsets
[i
] = resource_flag_count
;
312 resource_flag_count
+= layout
->binding_count
;
314 ctx
->buffer_resource_flags
= std::vector
<uint8_t>(resource_flag_count
);
316 nir_foreach_variable(var
, &impl
->function
->shader
->uniforms
) {
317 if (var
->data
.mode
== nir_var_mem_ssbo
&& (var
->data
.access
& ACCESS_RESTRICT
)) {
318 uint32_t offset
= ctx
->resource_flag_offsets
[var
->data
.descriptor_set
];
319 ctx
->buffer_resource_flags
[offset
+ var
->data
.binding
] |= buffer_is_restrict
;
323 nir_foreach_block(block
, impl
) {
324 nir_foreach_instr(instr
, block
) {
325 if (instr
->type
!= nir_instr_type_intrinsic
)
327 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
328 if (!(nir_intrinsic_infos
[intrin
->intrinsic
].index_map
[NIR_INTRINSIC_ACCESS
]))
331 nir_ssa_def
*res
= NULL
;
332 unsigned access
= nir_intrinsic_access(intrin
);
334 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
335 switch (intrin
->intrinsic
) {
336 case nir_intrinsic_load_ssbo
: {
337 unsigned elem_size
= intrin
->dest
.ssa
.bit_size
;
338 if (nir_dest_is_divergent(intrin
->dest
) || ctx
->program
->chip_class
< GFX8
|| elem_size
< 32)
339 flags
|= glc
? has_glc_vmem_load
: has_nonglc_vmem_load
;
340 res
= intrin
->src
[0].ssa
;
343 case nir_intrinsic_ssbo_atomic_add
:
344 case nir_intrinsic_ssbo_atomic_imin
:
345 case nir_intrinsic_ssbo_atomic_umin
:
346 case nir_intrinsic_ssbo_atomic_imax
:
347 case nir_intrinsic_ssbo_atomic_umax
:
348 case nir_intrinsic_ssbo_atomic_and
:
349 case nir_intrinsic_ssbo_atomic_or
:
350 case nir_intrinsic_ssbo_atomic_xor
:
351 case nir_intrinsic_ssbo_atomic_exchange
:
352 case nir_intrinsic_ssbo_atomic_comp_swap
:
353 flags
|= has_glc_vmem_load
| has_glc_vmem_store
;
354 res
= intrin
->src
[0].ssa
;
356 case nir_intrinsic_store_ssbo
: {
357 unsigned elem_size
= intrin
->src
[0].ssa
->bit_size
;
358 if (nir_src_is_divergent(intrin
->src
[2]) || ctx
->program
->chip_class
< GFX8
|| elem_size
< 32)
359 flags
|= glc
? has_glc_vmem_store
: has_nonglc_vmem_store
;
360 res
= intrin
->src
[1].ssa
;
363 case nir_intrinsic_load_global
:
364 if (!(access
& ACCESS_NON_WRITEABLE
))
365 flags
|= glc
? has_glc_vmem_load
: has_nonglc_vmem_load
;
367 case nir_intrinsic_store_global
:
368 flags
|= glc
? has_glc_vmem_store
: has_nonglc_vmem_store
;
370 case nir_intrinsic_global_atomic_add
:
371 case nir_intrinsic_global_atomic_imin
:
372 case nir_intrinsic_global_atomic_umin
:
373 case nir_intrinsic_global_atomic_imax
:
374 case nir_intrinsic_global_atomic_umax
:
375 case nir_intrinsic_global_atomic_and
:
376 case nir_intrinsic_global_atomic_or
:
377 case nir_intrinsic_global_atomic_xor
:
378 case nir_intrinsic_global_atomic_exchange
:
379 case nir_intrinsic_global_atomic_comp_swap
:
380 flags
|= has_glc_vmem_load
| has_glc_vmem_store
;
382 case nir_intrinsic_image_deref_load
:
383 res
= intrin
->src
[0].ssa
;
384 flags
|= glc
? has_glc_vmem_load
: has_nonglc_vmem_load
;
386 case nir_intrinsic_image_deref_store
:
387 res
= intrin
->src
[0].ssa
;
388 flags
|= (glc
|| ctx
->program
->chip_class
== GFX6
) ? has_glc_vmem_store
: has_nonglc_vmem_store
;
390 case nir_intrinsic_image_deref_atomic_add
:
391 case nir_intrinsic_image_deref_atomic_umin
:
392 case nir_intrinsic_image_deref_atomic_imin
:
393 case nir_intrinsic_image_deref_atomic_umax
:
394 case nir_intrinsic_image_deref_atomic_imax
:
395 case nir_intrinsic_image_deref_atomic_and
:
396 case nir_intrinsic_image_deref_atomic_or
:
397 case nir_intrinsic_image_deref_atomic_xor
:
398 case nir_intrinsic_image_deref_atomic_exchange
:
399 case nir_intrinsic_image_deref_atomic_comp_swap
:
400 res
= intrin
->src
[0].ssa
;
401 flags
|= has_glc_vmem_load
| has_glc_vmem_store
;
409 get_buffer_resource_flags(ctx
, res
, access
, &flags_ptr
, &count
);
411 for (unsigned i
= 0; i
< count
; i
++)
412 flags_ptr
[i
] |= flags
;
417 RegClass
get_reg_class(isel_context
*ctx
, RegType type
, unsigned components
, unsigned bitsize
)
420 return RegClass(RegType::sgpr
, ctx
->program
->lane_mask
.size() * components
);
422 return RegClass::get(type
, components
* bitsize
/ 8u);
425 void init_context(isel_context
*ctx
, nir_shader
*shader
)
427 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
428 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
430 ctx
->shader
= shader
;
431 nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
433 fill_desc_set_info(ctx
, impl
);
435 /* sanitize control flow */
436 nir_metadata_require(impl
, nir_metadata_dominance
);
437 sanitize_cf_list(impl
, &impl
->body
);
438 nir_metadata_preserve(impl
, (nir_metadata
)~nir_metadata_block_index
);
440 /* we'll need this for isel */
441 nir_metadata_require(impl
, nir_metadata_block_index
);
443 if (!(ctx
->stage
& sw_gs_copy
) && ctx
->options
->dump_preoptir
) {
444 fprintf(stderr
, "NIR shader before instruction selection:\n");
445 nir_print_shader(shader
, stderr
);
448 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
450 unsigned spi_ps_inputs
= 0;
452 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
454 /* TODO: make this recursive to improve compile times and merge with fill_desc_set_info() */
458 nir_foreach_block(block
, impl
) {
459 nir_foreach_instr(instr
, block
) {
460 switch(instr
->type
) {
461 case nir_instr_type_alu
: {
462 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
463 RegType type
= RegType::sgpr
;
464 switch(alu_instr
->op
) {
486 case nir_op_fround_even
:
490 case nir_op_f2f16_rtz
:
491 case nir_op_f2f16_rtne
:
500 case nir_op_pack_half_2x16
:
501 case nir_op_unpack_half_2x16_split_x
:
502 case nir_op_unpack_half_2x16_split_y
:
505 case nir_op_fddx_fine
:
506 case nir_op_fddy_fine
:
507 case nir_op_fddx_coarse
:
508 case nir_op_fddy_coarse
:
509 case nir_op_fquantize2f16
:
511 case nir_op_frexp_sig
:
512 case nir_op_frexp_exp
:
513 case nir_op_cube_face_index
:
514 case nir_op_cube_face_coord
:
515 type
= RegType::vgpr
;
528 type
= nir_dest_is_divergent(alu_instr
->dest
.dest
) ? RegType::vgpr
: RegType::sgpr
;
531 type
= nir_dest_is_divergent(alu_instr
->dest
.dest
) ? RegType::vgpr
: RegType::sgpr
;
534 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
535 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
536 type
= RegType::vgpr
;
541 RegClass rc
= get_reg_class(ctx
, type
, alu_instr
->dest
.dest
.ssa
.num_components
, alu_instr
->dest
.dest
.ssa
.bit_size
);
542 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, rc
);
545 case nir_instr_type_load_const
: {
546 unsigned num_components
= nir_instr_as_load_const(instr
)->def
.num_components
;
547 unsigned bit_size
= nir_instr_as_load_const(instr
)->def
.bit_size
;
548 RegClass rc
= get_reg_class(ctx
, RegType::sgpr
, num_components
, bit_size
);
549 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, rc
);
552 case nir_instr_type_intrinsic
: {
553 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
554 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
556 RegType type
= RegType::sgpr
;
557 switch(intrinsic
->intrinsic
) {
558 case nir_intrinsic_load_push_constant
:
559 case nir_intrinsic_load_work_group_id
:
560 case nir_intrinsic_load_num_work_groups
:
561 case nir_intrinsic_load_subgroup_id
:
562 case nir_intrinsic_load_num_subgroups
:
563 case nir_intrinsic_load_first_vertex
:
564 case nir_intrinsic_load_base_instance
:
565 case nir_intrinsic_get_buffer_size
:
566 case nir_intrinsic_vote_all
:
567 case nir_intrinsic_vote_any
:
568 case nir_intrinsic_read_first_invocation
:
569 case nir_intrinsic_read_invocation
:
570 case nir_intrinsic_first_invocation
:
571 case nir_intrinsic_ballot
:
572 type
= RegType::sgpr
;
574 case nir_intrinsic_load_sample_id
:
575 case nir_intrinsic_load_sample_mask_in
:
576 case nir_intrinsic_load_input
:
577 case nir_intrinsic_load_output
:
578 case nir_intrinsic_load_input_vertex
:
579 case nir_intrinsic_load_per_vertex_input
:
580 case nir_intrinsic_load_per_vertex_output
:
581 case nir_intrinsic_load_vertex_id
:
582 case nir_intrinsic_load_vertex_id_zero_base
:
583 case nir_intrinsic_load_barycentric_sample
:
584 case nir_intrinsic_load_barycentric_pixel
:
585 case nir_intrinsic_load_barycentric_model
:
586 case nir_intrinsic_load_barycentric_centroid
:
587 case nir_intrinsic_load_barycentric_at_sample
:
588 case nir_intrinsic_load_barycentric_at_offset
:
589 case nir_intrinsic_load_interpolated_input
:
590 case nir_intrinsic_load_frag_coord
:
591 case nir_intrinsic_load_sample_pos
:
592 case nir_intrinsic_load_layer_id
:
593 case nir_intrinsic_load_local_invocation_id
:
594 case nir_intrinsic_load_local_invocation_index
:
595 case nir_intrinsic_load_subgroup_invocation
:
596 case nir_intrinsic_load_tess_coord
:
597 case nir_intrinsic_write_invocation_amd
:
598 case nir_intrinsic_mbcnt_amd
:
599 case nir_intrinsic_load_instance_id
:
600 case nir_intrinsic_ssbo_atomic_add
:
601 case nir_intrinsic_ssbo_atomic_imin
:
602 case nir_intrinsic_ssbo_atomic_umin
:
603 case nir_intrinsic_ssbo_atomic_imax
:
604 case nir_intrinsic_ssbo_atomic_umax
:
605 case nir_intrinsic_ssbo_atomic_and
:
606 case nir_intrinsic_ssbo_atomic_or
:
607 case nir_intrinsic_ssbo_atomic_xor
:
608 case nir_intrinsic_ssbo_atomic_exchange
:
609 case nir_intrinsic_ssbo_atomic_comp_swap
:
610 case nir_intrinsic_global_atomic_add
:
611 case nir_intrinsic_global_atomic_imin
:
612 case nir_intrinsic_global_atomic_umin
:
613 case nir_intrinsic_global_atomic_imax
:
614 case nir_intrinsic_global_atomic_umax
:
615 case nir_intrinsic_global_atomic_and
:
616 case nir_intrinsic_global_atomic_or
:
617 case nir_intrinsic_global_atomic_xor
:
618 case nir_intrinsic_global_atomic_exchange
:
619 case nir_intrinsic_global_atomic_comp_swap
:
620 case nir_intrinsic_image_deref_atomic_add
:
621 case nir_intrinsic_image_deref_atomic_umin
:
622 case nir_intrinsic_image_deref_atomic_imin
:
623 case nir_intrinsic_image_deref_atomic_umax
:
624 case nir_intrinsic_image_deref_atomic_imax
:
625 case nir_intrinsic_image_deref_atomic_and
:
626 case nir_intrinsic_image_deref_atomic_or
:
627 case nir_intrinsic_image_deref_atomic_xor
:
628 case nir_intrinsic_image_deref_atomic_exchange
:
629 case nir_intrinsic_image_deref_atomic_comp_swap
:
630 case nir_intrinsic_image_deref_size
:
631 case nir_intrinsic_shared_atomic_add
:
632 case nir_intrinsic_shared_atomic_imin
:
633 case nir_intrinsic_shared_atomic_umin
:
634 case nir_intrinsic_shared_atomic_imax
:
635 case nir_intrinsic_shared_atomic_umax
:
636 case nir_intrinsic_shared_atomic_and
:
637 case nir_intrinsic_shared_atomic_or
:
638 case nir_intrinsic_shared_atomic_xor
:
639 case nir_intrinsic_shared_atomic_exchange
:
640 case nir_intrinsic_shared_atomic_comp_swap
:
641 case nir_intrinsic_load_scratch
:
642 case nir_intrinsic_load_invocation_id
:
643 case nir_intrinsic_load_primitive_id
:
644 type
= RegType::vgpr
;
646 case nir_intrinsic_shuffle
:
647 case nir_intrinsic_quad_broadcast
:
648 case nir_intrinsic_quad_swap_horizontal
:
649 case nir_intrinsic_quad_swap_vertical
:
650 case nir_intrinsic_quad_swap_diagonal
:
651 case nir_intrinsic_quad_swizzle_amd
:
652 case nir_intrinsic_masked_swizzle_amd
:
653 case nir_intrinsic_inclusive_scan
:
654 case nir_intrinsic_exclusive_scan
:
655 case nir_intrinsic_reduce
:
656 case nir_intrinsic_load_ubo
:
657 case nir_intrinsic_load_ssbo
:
658 case nir_intrinsic_load_global
:
659 case nir_intrinsic_vulkan_resource_index
:
660 case nir_intrinsic_load_shared
:
661 type
= nir_dest_is_divergent(intrinsic
->dest
) ? RegType::vgpr
: RegType::sgpr
;
663 case nir_intrinsic_load_view_index
:
664 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
667 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
668 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
669 type
= RegType::vgpr
;
673 RegClass rc
= get_reg_class(ctx
, type
, intrinsic
->dest
.ssa
.num_components
, intrinsic
->dest
.ssa
.bit_size
);
674 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, rc
);
676 switch(intrinsic
->intrinsic
) {
677 case nir_intrinsic_load_barycentric_sample
:
678 case nir_intrinsic_load_barycentric_pixel
:
679 case nir_intrinsic_load_barycentric_centroid
:
680 case nir_intrinsic_load_barycentric_at_sample
:
681 case nir_intrinsic_load_barycentric_at_offset
: {
682 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
683 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
686 case nir_intrinsic_load_barycentric_model
:
687 spi_ps_inputs
|= S_0286CC_PERSP_PULL_MODEL_ENA(1);
689 case nir_intrinsic_load_front_face
:
690 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
692 case nir_intrinsic_load_frag_coord
:
693 case nir_intrinsic_load_sample_pos
: {
694 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
695 for (unsigned i
= 0; i
< 4; i
++) {
697 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
702 case nir_intrinsic_load_sample_id
:
703 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
705 case nir_intrinsic_load_sample_mask_in
:
706 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
707 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
714 case nir_instr_type_tex
: {
715 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
716 unsigned size
= tex
->dest
.ssa
.num_components
;
718 if (tex
->dest
.ssa
.bit_size
== 64)
720 if (tex
->op
== nir_texop_texture_samples
) {
721 assert(!tex
->dest
.ssa
.divergent
);
723 if (nir_dest_is_divergent(tex
->dest
))
724 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
726 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
729 case nir_instr_type_parallel_copy
: {
730 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
731 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
735 case nir_instr_type_ssa_undef
: {
736 unsigned num_components
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
737 unsigned bit_size
= nir_instr_as_ssa_undef(instr
)->def
.bit_size
;
738 RegClass rc
= get_reg_class(ctx
, RegType::sgpr
, num_components
, bit_size
);
739 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, rc
);
742 case nir_instr_type_phi
: {
743 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
745 unsigned size
= phi
->dest
.ssa
.num_components
;
747 if (phi
->dest
.ssa
.bit_size
== 1) {
748 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
749 type
= RegType::sgpr
;
750 size
*= lane_mask_size
;
751 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
755 if (nir_dest_is_divergent(phi
->dest
)) {
756 type
= RegType::vgpr
;
758 type
= RegType::sgpr
;
759 nir_foreach_phi_src (src
, phi
) {
760 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
761 type
= RegType::vgpr
;
762 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
767 RegClass rc
= get_reg_class(ctx
, type
, phi
->dest
.ssa
.num_components
, phi
->dest
.ssa
.bit_size
);
768 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
771 nir_foreach_phi_src(src
, phi
)
772 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
774 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
784 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
785 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
786 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
789 if (!(spi_ps_inputs
& 0x7F)) {
790 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
791 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
794 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
795 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
797 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
798 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
800 ctx
->allocated
.reset(allocated
.release());
801 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
804 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
806 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
807 if (ctx
->stage
== fragment_fs
) {
808 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
809 * itself and then communicates the results back via the ELF binary.
810 * Mirror what LLVM does by re-mapping the VGPR arguments here.
812 * TODO: If we made the FS input scanning code into a separate pass that
813 * could run before argument setup, then this wouldn't be necessary
816 struct ac_shader_args
*args
= &ctx
->args
->ac
;
818 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
819 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
824 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
825 args
->args
[i
].skip
= true;
827 args
->args
[i
].offset
= vgpr_reg
;
828 vgpr_reg
+= args
->args
[i
].size
;
835 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
836 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
837 if (ctx
->args
->ac
.args
[i
].skip
)
840 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
841 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
842 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
843 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
844 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
845 ctx
->arg_temps
[i
] = dst
;
846 startpgm
->definitions
[arg
] = Definition(dst
);
847 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
850 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
851 Pseudo_instruction
*instr
= startpgm
.get();
852 ctx
->block
->instructions
.push_back(std::move(startpgm
));
854 /* Stash these in the program so that they can be accessed later when
857 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
858 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
864 type_size(const struct glsl_type
*type
, bool bindless
)
866 // TODO: don't we need type->std430_base_alignment() here?
867 return glsl_count_attribute_slots(type
, false);
871 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
873 assert(glsl_type_is_vector_or_scalar(type
));
875 uint32_t comp_size
= glsl_type_is_boolean(type
)
876 ? 4 : glsl_get_bit_size(type
) / 8;
877 unsigned length
= glsl_get_vector_elements(type
);
878 *size
= comp_size
* length
,
883 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
884 unsigned num_components
, unsigned high_offset
,
885 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
887 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
890 /* >128 bit loads are split except with SMEM */
891 if (bit_size
* num_components
> 128)
894 switch (low
->intrinsic
) {
895 case nir_intrinsic_load_global
:
896 case nir_intrinsic_store_global
:
897 return align
% 4 == 0;
898 case nir_intrinsic_store_ssbo
:
899 if (low
->src
[0].ssa
->bit_size
< 32 || high
->src
[0].ssa
->bit_size
< 32)
901 return align
% 4 == 0;
902 case nir_intrinsic_load_ssbo
:
903 if (low
->dest
.ssa
.bit_size
< 32 || high
->dest
.ssa
.bit_size
< 32)
905 case nir_intrinsic_load_ubo
:
906 case nir_intrinsic_load_push_constant
:
907 return align
% 4 == 0;
908 case nir_intrinsic_load_deref
:
909 case nir_intrinsic_store_deref
:
910 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
912 case nir_intrinsic_load_shared
:
913 case nir_intrinsic_store_shared
:
914 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
915 return align
% 16 == 0;
917 return align
% 4 == 0;
925 setup_vs_output_info(isel_context
*ctx
, nir_shader
*nir
,
926 bool export_prim_id
, bool export_clip_dists
,
927 radv_vs_output_info
*outinfo
)
929 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
930 sizeof(outinfo
->vs_output_param_offset
));
932 outinfo
->param_exports
= 0;
933 int pos_written
= 0x1;
934 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
935 pos_written
|= 1 << 1;
937 uint64_t mask
= nir
->info
.outputs_written
;
939 int idx
= u_bit_scan64(&mask
);
940 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
||
941 idx
== VARYING_SLOT_PRIMITIVE_ID
|| idx
== VARYING_SLOT_VIEWPORT
||
942 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
943 if (outinfo
->vs_output_param_offset
[idx
] == AC_EXP_PARAM_UNDEFINED
)
944 outinfo
->vs_output_param_offset
[idx
] = outinfo
->param_exports
++;
947 if (outinfo
->writes_layer
&&
948 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
949 /* when ctx->options->key.has_multiview_view_index = true, the layer
950 * variable isn't declared in NIR and it's isel's job to get the layer */
951 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
954 if (export_prim_id
) {
955 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
956 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
959 ctx
->export_clip_dists
= export_clip_dists
;
960 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
961 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
963 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
965 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
966 pos_written
|= 1 << 2;
967 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
968 pos_written
|= 1 << 3;
970 outinfo
->pos_exports
= util_bitcount(pos_written
);
974 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
976 nir_foreach_variable(variable
, &nir
->inputs
)
978 variable
->data
.driver_location
= variable
->data
.location
* 4;
980 nir_foreach_variable(variable
, &nir
->outputs
)
982 if (ctx
->stage
== vertex_vs
|| ctx
->stage
== ngg_vertex_gs
)
983 variable
->data
.driver_location
= variable
->data
.location
* 4;
985 assert(variable
->data
.location
>= 0 && variable
->data
.location
<= UINT8_MAX
);
986 ctx
->output_drv_loc_to_var_slot
[MESA_SHADER_VERTEX
][variable
->data
.driver_location
/ 4] = variable
->data
.location
;
989 if (ctx
->stage
== vertex_vs
|| ctx
->stage
== ngg_vertex_gs
) {
990 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
991 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
992 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
993 } else if (ctx
->stage
== vertex_ls
) {
994 ctx
->tcs_num_inputs
= ctx
->program
->info
->vs
.num_linked_outputs
;
997 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
998 /* We need to store the primitive IDs in LDS */
999 unsigned lds_size
= ctx
->program
->info
->ngg_info
.esgs_ring_size
;
1000 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
1001 ctx
->program
->lds_alloc_granule
;
1005 void setup_gs_variables(isel_context
*ctx
, nir_shader
*nir
)
1007 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
1008 ctx
->program
->config
->lds_size
= ctx
->program
->info
->gs_ring_info
.lds_size
; /* Already in units of the alloc granularity */
1010 nir_foreach_variable(variable
, &nir
->outputs
) {
1011 variable
->data
.driver_location
= variable
->data
.location
* 4;
1014 if (ctx
->stage
== vertex_geometry_gs
)
1015 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_VERTEX
;
1016 else if (ctx
->stage
== tess_eval_geometry_gs
)
1017 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_TESS_EVAL
;
1021 setup_tcs_info(isel_context
*ctx
, nir_shader
*nir
)
1023 /* When the number of TCS input and output vertices are the same (typically 3):
1024 * - There is an equal amount of LS and HS invocations
1025 * - In case of merged LSHS shaders, the LS and HS halves of the shader
1026 * always process the exact same vertex. We can use this knowledge to optimize them.
1028 ctx
->tcs_in_out_eq
=
1029 ctx
->stage
== vertex_tess_control_hs
&&
1030 ctx
->args
->options
->key
.tcs
.input_vertices
== nir
->info
.tess
.tcs_vertices_out
;
1032 if (ctx
->tcs_in_out_eq
) {
1033 ctx
->tcs_temp_only_inputs
= ~nir
->info
.tess
.tcs_cross_invocation_inputs_read
&
1034 ~nir
->info
.inputs_read_indirectly
&
1035 nir
->info
.inputs_read
;
1038 ctx
->tcs_num_inputs
= ctx
->program
->info
->tcs
.num_linked_inputs
;
1039 ctx
->tcs_num_outputs
= ctx
->program
->info
->tcs
.num_linked_outputs
;
1040 ctx
->tcs_num_patch_outputs
= ctx
->program
->info
->tcs
.num_linked_patch_outputs
;
1042 ctx
->tcs_num_patches
= get_tcs_num_patches(
1043 ctx
->args
->options
->key
.tcs
.input_vertices
,
1044 nir
->info
.tess
.tcs_vertices_out
,
1045 ctx
->tcs_num_inputs
,
1046 ctx
->tcs_num_outputs
,
1047 ctx
->tcs_num_patch_outputs
,
1048 ctx
->args
->options
->tess_offchip_block_dw_size
,
1049 ctx
->args
->options
->chip_class
,
1050 ctx
->args
->options
->family
);
1051 unsigned lds_size
= calculate_tess_lds_size(
1052 ctx
->args
->options
->key
.tcs
.input_vertices
,
1053 nir
->info
.tess
.tcs_vertices_out
,
1054 ctx
->tcs_num_inputs
,
1055 ctx
->tcs_num_patches
,
1056 ctx
->tcs_num_outputs
,
1057 ctx
->tcs_num_patch_outputs
);
1059 ctx
->args
->shader_info
->tcs
.num_patches
= ctx
->tcs_num_patches
;
1060 ctx
->args
->shader_info
->tcs
.lds_size
= lds_size
;
1061 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
1062 ctx
->program
->lds_alloc_granule
;
1066 setup_tcs_variables(isel_context
*ctx
, nir_shader
*nir
)
1068 nir_foreach_variable(variable
, &nir
->outputs
) {
1069 assert(variable
->data
.location
>= 0 && variable
->data
.location
<= UINT8_MAX
);
1071 if (variable
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1072 ctx
->tcs_tess_lvl_out_loc
= variable
->data
.driver_location
* 4u;
1073 else if (variable
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
)
1074 ctx
->tcs_tess_lvl_in_loc
= variable
->data
.driver_location
* 4u;
1076 if (variable
->data
.patch
)
1077 ctx
->output_tcs_patch_drv_loc_to_var_slot
[variable
->data
.driver_location
/ 4] = variable
->data
.location
;
1079 ctx
->output_drv_loc_to_var_slot
[MESA_SHADER_TESS_CTRL
][variable
->data
.driver_location
/ 4] = variable
->data
.location
;
1084 setup_tes_variables(isel_context
*ctx
, nir_shader
*nir
)
1086 ctx
->tcs_num_patches
= ctx
->args
->options
->key
.tes
.num_patches
;
1087 ctx
->tcs_num_outputs
= ctx
->program
->info
->tes
.num_linked_inputs
;
1089 nir_foreach_variable(variable
, &nir
->outputs
) {
1090 if (ctx
->stage
== tess_eval_vs
|| ctx
->stage
== ngg_tess_eval_gs
)
1091 variable
->data
.driver_location
= variable
->data
.location
* 4;
1094 if (ctx
->stage
== tess_eval_vs
|| ctx
->stage
== ngg_tess_eval_gs
) {
1095 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->tes
.outinfo
;
1096 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
1097 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
1102 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
1104 switch (nir
->info
.stage
) {
1105 case MESA_SHADER_FRAGMENT
: {
1106 nir_foreach_variable(variable
, &nir
->outputs
)
1108 int idx
= variable
->data
.location
+ variable
->data
.index
;
1109 variable
->data
.driver_location
= idx
* 4;
1113 case MESA_SHADER_COMPUTE
: {
1114 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
1115 ctx
->program
->lds_alloc_granule
;
1118 case MESA_SHADER_VERTEX
: {
1119 setup_vs_variables(ctx
, nir
);
1122 case MESA_SHADER_GEOMETRY
: {
1123 setup_gs_variables(ctx
, nir
);
1126 case MESA_SHADER_TESS_CTRL
: {
1127 setup_tcs_variables(ctx
, nir
);
1130 case MESA_SHADER_TESS_EVAL
: {
1131 setup_tes_variables(ctx
, nir
);
1135 unreachable("Unhandled shader stage.");
1140 lower_bit_size_callback(const nir_alu_instr
*alu
, void *_
)
1142 if (nir_op_is_vec(alu
->op
))
1145 unsigned bit_size
= alu
->dest
.dest
.ssa
.bit_size
;
1146 if (nir_alu_instr_is_comparison(alu
))
1147 bit_size
= nir_src_bit_size(alu
->src
[0].src
);
1149 if (bit_size
>= 32 || bit_size
== 1)
1152 if (alu
->op
== nir_op_bcsel
)
1155 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1157 if (info
->is_conversion
)
1160 bool is_integer
= info
->output_type
& (nir_type_uint
| nir_type_int
);
1161 for (unsigned i
= 0; is_integer
&& (i
< info
->num_inputs
); i
++)
1162 is_integer
= info
->input_types
[i
] & (nir_type_uint
| nir_type_int
);
1164 return is_integer
? 32 : 0;
1168 setup_nir(isel_context
*ctx
, nir_shader
*nir
)
1170 Program
*program
= ctx
->program
;
1172 /* align and copy constant data */
1173 while (program
->constant_data
.size() % 4u)
1174 program
->constant_data
.push_back(0);
1175 ctx
->constant_data_offset
= program
->constant_data
.size();
1176 program
->constant_data
.insert(program
->constant_data
.end(),
1177 (uint8_t*)nir
->constant_data
,
1178 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
1180 /* the variable setup has to be done before lower_io / CSE */
1181 setup_variables(ctx
, nir
);
1183 /* optimize and lower memory operations */
1184 if (nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
)) {
1185 nir_opt_constant_folding(nir
);
1189 bool lower_to_scalar
= false;
1190 bool lower_pack
= false;
1191 nir_variable_mode robust_modes
= (nir_variable_mode
)0;
1193 if (ctx
->options
->robust_buffer_access
) {
1194 robust_modes
= (nir_variable_mode
)(nir_var_mem_ubo
|
1196 nir_var_mem_global
|
1197 nir_var_mem_push_const
);
1200 if (nir_opt_load_store_vectorize(nir
,
1201 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
1202 nir_var_mem_push_const
| nir_var_mem_shared
|
1203 nir_var_mem_global
),
1204 mem_vectorize_callback
, robust_modes
)) {
1205 lower_to_scalar
= true;
1208 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
1209 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
1211 if (lower_to_scalar
)
1212 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
1214 nir_lower_pack(nir
);
1216 /* lower ALU operations */
1217 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
1219 if (nir_lower_bit_size(nir
, lower_bit_size_callback
, NULL
))
1220 nir_copy_prop(nir
); /* allow nir_opt_idiv_const() to optimize lowered divisions */
1222 nir_opt_idiv_const(nir
, 32);
1223 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
1225 /* optimize the lowered ALU operations */
1226 bool more_algebraic
= true;
1227 while (more_algebraic
) {
1228 more_algebraic
= false;
1229 NIR_PASS_V(nir
, nir_copy_prop
);
1230 NIR_PASS_V(nir
, nir_opt_dce
);
1231 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1232 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
1235 /* Do late algebraic optimization to turn add(a, neg(b)) back into
1236 * subs, then the mandatory cleanup after algebraic. Note that it may
1237 * produce fnegs, and if so then we need to keep running to squash
1240 bool more_late_algebraic
= true;
1241 while (more_late_algebraic
) {
1242 more_late_algebraic
= false;
1243 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
1244 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1245 NIR_PASS_V(nir
, nir_copy_prop
);
1246 NIR_PASS_V(nir
, nir_opt_dce
);
1247 NIR_PASS_V(nir
, nir_opt_cse
);
1250 /* cleanup passes */
1251 nir_lower_load_const_to_scalar(nir
);
1252 nir_opt_shrink_load(nir
);
1253 nir_move_options move_opts
= (nir_move_options
)(
1254 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
|
1255 nir_move_comparisons
| nir_move_copies
);
1256 nir_opt_sink(nir
, move_opts
);
1257 nir_opt_move(nir
, move_opts
);
1258 nir_convert_to_lcssa(nir
, true, false);
1259 nir_lower_phis_to_scalar(nir
);
1261 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
1262 nir_index_ssa_defs(func
);
1266 setup_xnack(Program
*program
)
1268 switch (program
->family
) {
1276 program
->xnack_enabled
= true;
1284 setup_isel_context(Program
* program
,
1285 unsigned shader_count
,
1286 struct nir_shader
*const *shaders
,
1287 ac_shader_config
* config
,
1288 struct radv_shader_args
*args
,
1289 bool is_gs_copy_shader
)
1292 for (unsigned i
= 0; i
< shader_count
; i
++) {
1293 switch (shaders
[i
]->info
.stage
) {
1294 case MESA_SHADER_VERTEX
:
1295 program
->stage
|= sw_vs
;
1297 case MESA_SHADER_TESS_CTRL
:
1298 program
->stage
|= sw_tcs
;
1300 case MESA_SHADER_TESS_EVAL
:
1301 program
->stage
|= sw_tes
;
1303 case MESA_SHADER_GEOMETRY
:
1304 program
->stage
|= is_gs_copy_shader
? sw_gs_copy
: sw_gs
;
1306 case MESA_SHADER_FRAGMENT
:
1307 program
->stage
|= sw_fs
;
1309 case MESA_SHADER_COMPUTE
:
1310 program
->stage
|= sw_cs
;
1313 unreachable("Shader stage not implemented");
1316 bool gfx9_plus
= args
->options
->chip_class
>= GFX9
;
1317 bool ngg
= args
->shader_info
->is_ngg
&& args
->options
->chip_class
>= GFX10
;
1318 if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_es
&& !ngg
)
1319 program
->stage
|= hw_es
;
1320 else if (program
->stage
== sw_vs
&& !args
->shader_info
->vs
.as_ls
&& !ngg
)
1321 program
->stage
|= hw_vs
;
1322 else if (program
->stage
== sw_vs
&& ngg
)
1323 program
->stage
|= hw_ngg_gs
; /* GFX10/NGG: VS without GS uses the HW GS stage */
1324 else if (program
->stage
== sw_gs
)
1325 program
->stage
|= hw_gs
;
1326 else if (program
->stage
== sw_fs
)
1327 program
->stage
|= hw_fs
;
1328 else if (program
->stage
== sw_cs
)
1329 program
->stage
|= hw_cs
;
1330 else if (program
->stage
== sw_gs_copy
)
1331 program
->stage
|= hw_vs
;
1332 else if (program
->stage
== (sw_vs
| sw_gs
) && gfx9_plus
&& !ngg
)
1333 program
->stage
|= hw_gs
;
1334 else if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_ls
)
1335 program
->stage
|= hw_ls
; /* GFX6-8: VS is a Local Shader, when tessellation is used */
1336 else if (program
->stage
== sw_tcs
)
1337 program
->stage
|= hw_hs
; /* GFX6-8: TCS is a Hull Shader */
1338 else if (program
->stage
== (sw_vs
| sw_tcs
))
1339 program
->stage
|= hw_hs
; /* GFX9-10: VS+TCS merged into a Hull Shader */
1340 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& !ngg
)
1341 program
->stage
|= hw_vs
; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
1342 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& ngg
)
1343 program
->stage
|= hw_ngg_gs
; /* GFX10/NGG: TES without GS uses the HW GS stage */
1344 else if (program
->stage
== sw_tes
&& args
->shader_info
->tes
.as_es
&& !ngg
)
1345 program
->stage
|= hw_es
; /* GFX6-8: TES is an Export Shader */
1346 else if (program
->stage
== (sw_tes
| sw_gs
) && gfx9_plus
&& !ngg
)
1347 program
->stage
|= hw_gs
; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
1349 unreachable("Shader stage not implemented");
1351 program
->config
= config
;
1352 program
->info
= args
->shader_info
;
1353 program
->chip_class
= args
->options
->chip_class
;
1354 program
->family
= args
->options
->family
;
1355 program
->wave_size
= args
->shader_info
->wave_size
;
1356 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
1358 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
1359 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
1360 /* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
1361 program
->has_16bank_lds
= args
->options
->family
== CHIP_KABINI
|| args
->options
->family
== CHIP_STONEY
;
1363 program
->vgpr_limit
= 256;
1364 program
->vgpr_alloc_granule
= 3;
1366 if (args
->options
->chip_class
>= GFX10
) {
1367 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
1368 program
->sgpr_alloc_granule
= 127;
1369 program
->sgpr_limit
= 106;
1370 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
1371 } else if (program
->chip_class
>= GFX8
) {
1372 program
->physical_sgprs
= 800;
1373 program
->sgpr_alloc_granule
= 15;
1374 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
1375 program
->sgpr_limit
= 94; /* workaround hardware bug */
1377 program
->sgpr_limit
= 102;
1379 program
->physical_sgprs
= 512;
1380 program
->sgpr_alloc_granule
= 7;
1381 program
->sgpr_limit
= 104;
1384 isel_context ctx
= {};
1385 ctx
.program
= program
;
1387 ctx
.options
= args
->options
;
1388 ctx
.stage
= program
->stage
;
1390 /* TODO: Check if we need to adjust min_waves for unknown workgroup sizes. */
1391 if (program
->stage
& (hw_vs
| hw_fs
)) {
1392 /* PS and legacy VS have separate waves, no workgroups */
1393 program
->workgroup_size
= program
->wave_size
;
1394 } else if (program
->stage
== compute_cs
) {
1395 /* CS sets the workgroup size explicitly */
1396 unsigned* bsize
= program
->info
->cs
.block_size
;
1397 program
->workgroup_size
= bsize
[0] * bsize
[1] * bsize
[2];
1398 } else if ((program
->stage
& hw_es
) || program
->stage
== geometry_gs
) {
1399 /* Unmerged ESGS operate in workgroups if on-chip GS (LDS rings) are enabled on GFX7-8 (not implemented in Mesa) */
1400 program
->workgroup_size
= program
->wave_size
;
1401 } else if (program
->stage
& hw_gs
) {
1402 /* If on-chip GS (LDS rings) are enabled on GFX9 or later, merged GS operates in workgroups */
1403 assert(program
->chip_class
>= GFX9
);
1404 uint32_t es_verts_per_subgrp
= G_028A44_ES_VERTS_PER_SUBGRP(program
->info
->gs_ring_info
.vgt_gs_onchip_cntl
);
1405 uint32_t gs_instr_prims_in_subgrp
= G_028A44_GS_INST_PRIMS_IN_SUBGRP(program
->info
->gs_ring_info
.vgt_gs_onchip_cntl
);
1406 uint32_t workgroup_size
= MAX2(es_verts_per_subgrp
, gs_instr_prims_in_subgrp
);
1407 program
->workgroup_size
= MAX2(MIN2(workgroup_size
, 256), 1);
1408 } else if (program
->stage
== vertex_ls
) {
1409 /* Unmerged LS operates in workgroups */
1410 program
->workgroup_size
= UINT_MAX
; /* TODO: probably tcs_num_patches * tcs_vertices_in, but those are not plumbed to ACO for LS */
1411 } else if (program
->stage
== tess_control_hs
) {
1412 /* Unmerged HS operates in workgroups, size is determined by the output vertices */
1413 setup_tcs_info(&ctx
, shaders
[0]);
1414 program
->workgroup_size
= ctx
.tcs_num_patches
* shaders
[0]->info
.tess
.tcs_vertices_out
;
1415 } else if (program
->stage
== vertex_tess_control_hs
) {
1416 /* Merged LSHS operates in workgroups, but can still have a different number of LS and HS invocations */
1417 setup_tcs_info(&ctx
, shaders
[1]);
1418 program
->workgroup_size
= ctx
.tcs_num_patches
* MAX2(shaders
[1]->info
.tess
.tcs_vertices_out
, ctx
.args
->options
->key
.tcs
.input_vertices
);
1419 } else if (program
->stage
& hw_ngg_gs
) {
1420 /* TODO: Calculate workgroup size of NGG shaders. */
1421 program
->workgroup_size
= UINT_MAX
;
1423 unreachable("Unsupported shader stage.");
1426 calc_min_waves(program
);
1427 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
1428 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
1430 unsigned scratch_size
= 0;
1431 if (program
->stage
== gs_copy_vs
) {
1432 assert(shader_count
== 1);
1433 setup_vs_output_info(&ctx
, shaders
[0], false, true, &args
->shader_info
->vs
.outinfo
);
1435 for (unsigned i
= 0; i
< shader_count
; i
++) {
1436 nir_shader
*nir
= shaders
[i
];
1437 setup_nir(&ctx
, nir
);
1440 for (unsigned i
= 0; i
< shader_count
; i
++)
1441 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
1444 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
1446 ctx
.block
= ctx
.program
->create_and_insert_block();
1447 ctx
.block
->loop_nest_depth
= 0;
1448 ctx
.block
->kind
= block_kind_top_level
;
1450 setup_xnack(program
);
1451 program
->sram_ecc_enabled
= args
->options
->family
== CHIP_ARCTURUS
;
1452 /* apparently gfx702 also has fast v_fma_f32 but I can't find a family for that */
1453 program
->has_fast_fma32
= program
->chip_class
>= GFX9
;
1454 if (args
->options
->family
== CHIP_TAHITI
|| args
->options
->family
== CHIP_CARRIZO
|| args
->options
->family
== CHIP_HAWAII
)
1455 program
->has_fast_fma32
= true;