2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <unordered_map>
29 #include "nir_control_flow.h"
30 #include "vulkan/radv_shader.h"
31 #include "vulkan/radv_descriptor_set.h"
32 #include "vulkan/radv_shader_args.h"
34 #include "ac_exp_param.h"
35 #include "ac_shader_util.h"
37 #include "util/u_math.h"
39 #define MAX_INLINE_PUSH_CONSTS 8
44 uint8_t mask
[VARYING_SLOT_VAR31
+ 1];
45 Temp outputs
[VARYING_SLOT_VAR31
+ 1][4];
49 const struct radv_nir_compiler_options
*options
;
50 struct radv_shader_args
*args
;
53 uint32_t constant_data_offset
;
56 std::unique_ptr
<Temp
[]> allocated
;
57 std::unordered_map
<unsigned, std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
>> allocated_vec
;
58 Stage stage
; /* Stage */
59 bool has_gfx10_wave64_bpermute
= false;
62 uint16_t loop_nest_depth
= 0;
66 bool has_divergent_continue
= false;
67 bool has_divergent_branch
= false;
70 bool is_divergent
= false;
72 bool exec_potentially_empty_discard
= false; /* set to false when loop_nest_depth==0 && parent_if.is_divergent==false */
73 uint16_t exec_potentially_empty_break_depth
= UINT16_MAX
;
74 /* Set to false when loop_nest_depth==exec_potentially_empty_break_depth
75 * and parent_if.is_divergent==false. Called _break but it's also used for
77 bool exec_potentially_empty_break
= false;
78 std::unique_ptr
<unsigned[]> nir_to_aco
; /* NIR block index to ACO block index */
81 Temp arg_temps
[AC_MAX_ARGS
];
84 Temp persp_centroid
, linear_centroid
;
89 /* gathered information */
90 uint64_t input_masks
[MESA_SHADER_COMPUTE
];
91 uint64_t output_masks
[MESA_SHADER_COMPUTE
];
93 /* VS output information */
94 bool export_clip_dists
;
95 unsigned num_clip_distances
;
96 unsigned num_cull_distances
;
98 /* tessellation information */
99 unsigned tcs_tess_lvl_out_loc
;
100 unsigned tcs_tess_lvl_in_loc
;
101 uint32_t tcs_num_inputs
;
102 uint32_t tcs_num_patches
;
104 /* VS, FS or GS output information */
105 output_state outputs
;
108 Temp
get_arg(isel_context
*ctx
, struct ac_arg arg
)
111 return ctx
->arg_temps
[arg
.arg_index
];
114 unsigned get_interp_input(nir_intrinsic_op intrin
, enum glsl_interp_mode interp
)
117 case INTERP_MODE_SMOOTH
:
118 case INTERP_MODE_NONE
:
119 if (intrin
== nir_intrinsic_load_barycentric_pixel
||
120 intrin
== nir_intrinsic_load_barycentric_at_sample
||
121 intrin
== nir_intrinsic_load_barycentric_at_offset
)
122 return S_0286CC_PERSP_CENTER_ENA(1);
123 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
124 return S_0286CC_PERSP_CENTROID_ENA(1);
125 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
126 return S_0286CC_PERSP_SAMPLE_ENA(1);
128 case INTERP_MODE_NOPERSPECTIVE
:
129 if (intrin
== nir_intrinsic_load_barycentric_pixel
)
130 return S_0286CC_LINEAR_CENTER_ENA(1);
131 else if (intrin
== nir_intrinsic_load_barycentric_centroid
)
132 return S_0286CC_LINEAR_CENTROID_ENA(1);
133 else if (intrin
== nir_intrinsic_load_barycentric_sample
)
134 return S_0286CC_LINEAR_SAMPLE_ENA(1);
142 /* If one side of a divergent IF ends in a branch and the other doesn't, we
143 * might have to emit the contents of the side without the branch at the merge
144 * block instead. This is so that we can use any SGPR live-out of the side
145 * without the branch without creating a linear phi in the invert or merge block. */
147 sanitize_if(nir_function_impl
*impl
, bool *divergent
, nir_if
*nif
)
149 if (!divergent
[nif
->condition
.ssa
->index
])
152 nir_block
*then_block
= nir_if_last_then_block(nif
);
153 nir_block
*else_block
= nir_if_last_else_block(nif
);
154 bool then_jump
= nir_block_ends_in_jump(then_block
) || nir_block_is_unreachable(then_block
);
155 bool else_jump
= nir_block_ends_in_jump(else_block
) || nir_block_is_unreachable(else_block
);
156 if (then_jump
== else_jump
)
159 /* If the continue from block is empty then return as there is nothing to
162 if (nir_cf_list_is_empty_block(else_jump
? &nif
->then_list
: &nif
->else_list
))
165 /* Even though this if statement has a jump on one side, we may still have
166 * phis afterwards. Single-source phis can be produced by loop unrolling
167 * or dead control-flow passes and are perfectly legal. Run a quick phi
168 * removal on the block after the if to clean up any such phis.
170 nir_opt_remove_phis_block(nir_cf_node_as_block(nir_cf_node_next(&nif
->cf_node
)));
172 /* Finally, move the continue from branch after the if-statement. */
173 nir_block
*last_continue_from_blk
= else_jump
? then_block
: else_block
;
174 nir_block
*first_continue_from_blk
= else_jump
?
175 nir_if_first_then_block(nif
) : nir_if_first_else_block(nif
);
178 nir_cf_extract(&tmp
, nir_before_block(first_continue_from_blk
),
179 nir_after_block(last_continue_from_blk
));
180 nir_cf_reinsert(&tmp
, nir_after_cf_node(&nif
->cf_node
));
182 /* nir_cf_extract() invalidates dominance metadata, but it should still be
183 * correct because of the specific type of transformation we did. Block
184 * indices are not valid except for block_0's, which is all we care about for
185 * nir_block_is_unreachable(). */
186 impl
->valid_metadata
=
187 (nir_metadata
)(impl
->valid_metadata
| nir_metadata_dominance
| nir_metadata_block_index
);
193 sanitize_cf_list(nir_function_impl
*impl
, bool *divergent
, struct exec_list
*cf_list
)
195 bool progress
= false;
196 foreach_list_typed(nir_cf_node
, cf_node
, node
, cf_list
) {
197 switch (cf_node
->type
) {
198 case nir_cf_node_block
:
200 case nir_cf_node_if
: {
201 nir_if
*nif
= nir_cf_node_as_if(cf_node
);
202 progress
|= sanitize_cf_list(impl
, divergent
, &nif
->then_list
);
203 progress
|= sanitize_cf_list(impl
, divergent
, &nif
->else_list
);
204 progress
|= sanitize_if(impl
, divergent
, nif
);
207 case nir_cf_node_loop
: {
208 nir_loop
*loop
= nir_cf_node_as_loop(cf_node
);
209 progress
|= sanitize_cf_list(impl
, divergent
, &loop
->body
);
212 case nir_cf_node_function
:
213 unreachable("Invalid cf type");
220 void init_context(isel_context
*ctx
, nir_shader
*shader
)
222 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
223 unsigned lane_mask_size
= ctx
->program
->lane_mask
.size();
225 ctx
->shader
= shader
;
226 ctx
->divergent_vals
= nir_divergence_analysis(shader
, nir_divergence_view_index_uniform
);
228 /* sanitize control flow */
229 nir_metadata_require(impl
, nir_metadata_dominance
);
230 sanitize_cf_list(impl
, ctx
->divergent_vals
, &impl
->body
);
231 nir_metadata_preserve(impl
, (nir_metadata
)~nir_metadata_block_index
);
233 /* we'll need this for isel */
234 nir_metadata_require(impl
, nir_metadata_block_index
);
236 if (!(ctx
->stage
& sw_gs_copy
) && ctx
->options
->dump_preoptir
) {
237 fprintf(stderr
, "NIR shader before instruction selection:\n");
238 nir_print_shader(shader
, stderr
);
241 std::unique_ptr
<Temp
[]> allocated
{new Temp
[impl
->ssa_alloc
]()};
243 unsigned spi_ps_inputs
= 0;
245 std::unique_ptr
<unsigned[]> nir_to_aco
{new unsigned[impl
->num_blocks
]()};
250 nir_foreach_block(block
, impl
) {
251 nir_foreach_instr(instr
, block
) {
252 switch(instr
->type
) {
253 case nir_instr_type_alu
: {
254 nir_alu_instr
*alu_instr
= nir_instr_as_alu(instr
);
255 unsigned size
= alu_instr
->dest
.dest
.ssa
.num_components
;
256 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 64)
258 RegType type
= RegType::sgpr
;
259 switch(alu_instr
->op
) {
281 case nir_op_fround_even
:
290 case nir_op_pack_half_2x16
:
291 case nir_op_unpack_half_2x16_split_x
:
292 case nir_op_unpack_half_2x16_split_y
:
295 case nir_op_fddx_fine
:
296 case nir_op_fddy_fine
:
297 case nir_op_fddx_coarse
:
298 case nir_op_fddy_coarse
:
299 case nir_op_fquantize2f16
:
301 case nir_op_frexp_sig
:
302 case nir_op_frexp_exp
:
303 case nir_op_cube_face_index
:
304 case nir_op_cube_face_coord
:
305 type
= RegType::vgpr
;
318 size
= lane_mask_size
;
326 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
329 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
330 size
= lane_mask_size
;
332 if (ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
]) {
333 type
= RegType::vgpr
;
335 if (allocated
[alu_instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
||
336 allocated
[alu_instr
->src
[2].src
.ssa
->index
].type() == RegType::vgpr
) {
337 type
= RegType::vgpr
;
340 if (alu_instr
->src
[1].src
.ssa
->num_components
== 1 && alu_instr
->src
[2].src
.ssa
->num_components
== 1) {
341 assert(allocated
[alu_instr
->src
[1].src
.ssa
->index
].size() == allocated
[alu_instr
->src
[2].src
.ssa
->index
].size());
342 size
= allocated
[alu_instr
->src
[1].src
.ssa
->index
].size();
347 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
348 size
= lane_mask_size
;
350 type
= ctx
->divergent_vals
[alu_instr
->dest
.dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
354 if (alu_instr
->dest
.dest
.ssa
.bit_size
== 1) {
355 size
= lane_mask_size
;
357 for (unsigned i
= 0; i
< nir_op_infos
[alu_instr
->op
].num_inputs
; i
++) {
358 if (allocated
[alu_instr
->src
[i
].src
.ssa
->index
].type() == RegType::vgpr
)
359 type
= RegType::vgpr
;
364 allocated
[alu_instr
->dest
.dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
367 case nir_instr_type_load_const
: {
368 unsigned size
= nir_instr_as_load_const(instr
)->def
.num_components
;
369 if (nir_instr_as_load_const(instr
)->def
.bit_size
== 64)
371 else if (nir_instr_as_load_const(instr
)->def
.bit_size
== 1)
372 size
*= lane_mask_size
;
373 allocated
[nir_instr_as_load_const(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
376 case nir_instr_type_intrinsic
: {
377 nir_intrinsic_instr
*intrinsic
= nir_instr_as_intrinsic(instr
);
378 if (!nir_intrinsic_infos
[intrinsic
->intrinsic
].has_dest
)
380 unsigned size
= intrinsic
->dest
.ssa
.num_components
;
381 if (intrinsic
->dest
.ssa
.bit_size
== 64)
383 RegType type
= RegType::sgpr
;
384 switch(intrinsic
->intrinsic
) {
385 case nir_intrinsic_load_push_constant
:
386 case nir_intrinsic_load_work_group_id
:
387 case nir_intrinsic_load_num_work_groups
:
388 case nir_intrinsic_load_subgroup_id
:
389 case nir_intrinsic_load_num_subgroups
:
390 case nir_intrinsic_load_first_vertex
:
391 case nir_intrinsic_load_base_instance
:
392 case nir_intrinsic_get_buffer_size
:
393 case nir_intrinsic_vote_all
:
394 case nir_intrinsic_vote_any
:
395 case nir_intrinsic_read_first_invocation
:
396 case nir_intrinsic_read_invocation
:
397 case nir_intrinsic_first_invocation
:
398 type
= RegType::sgpr
;
399 if (intrinsic
->dest
.ssa
.bit_size
== 1)
400 size
= lane_mask_size
;
402 case nir_intrinsic_ballot
:
403 type
= RegType::sgpr
;
405 case nir_intrinsic_load_sample_id
:
406 case nir_intrinsic_load_sample_mask_in
:
407 case nir_intrinsic_load_input
:
408 case nir_intrinsic_load_output
:
409 case nir_intrinsic_load_input_vertex
:
410 case nir_intrinsic_load_per_vertex_input
:
411 case nir_intrinsic_load_per_vertex_output
:
412 case nir_intrinsic_load_vertex_id
:
413 case nir_intrinsic_load_vertex_id_zero_base
:
414 case nir_intrinsic_load_barycentric_sample
:
415 case nir_intrinsic_load_barycentric_pixel
:
416 case nir_intrinsic_load_barycentric_model
:
417 case nir_intrinsic_load_barycentric_centroid
:
418 case nir_intrinsic_load_barycentric_at_sample
:
419 case nir_intrinsic_load_barycentric_at_offset
:
420 case nir_intrinsic_load_interpolated_input
:
421 case nir_intrinsic_load_frag_coord
:
422 case nir_intrinsic_load_sample_pos
:
423 case nir_intrinsic_load_layer_id
:
424 case nir_intrinsic_load_local_invocation_id
:
425 case nir_intrinsic_load_local_invocation_index
:
426 case nir_intrinsic_load_subgroup_invocation
:
427 case nir_intrinsic_load_tess_coord
:
428 case nir_intrinsic_write_invocation_amd
:
429 case nir_intrinsic_mbcnt_amd
:
430 case nir_intrinsic_load_instance_id
:
431 case nir_intrinsic_ssbo_atomic_add
:
432 case nir_intrinsic_ssbo_atomic_imin
:
433 case nir_intrinsic_ssbo_atomic_umin
:
434 case nir_intrinsic_ssbo_atomic_imax
:
435 case nir_intrinsic_ssbo_atomic_umax
:
436 case nir_intrinsic_ssbo_atomic_and
:
437 case nir_intrinsic_ssbo_atomic_or
:
438 case nir_intrinsic_ssbo_atomic_xor
:
439 case nir_intrinsic_ssbo_atomic_exchange
:
440 case nir_intrinsic_ssbo_atomic_comp_swap
:
441 case nir_intrinsic_global_atomic_add
:
442 case nir_intrinsic_global_atomic_imin
:
443 case nir_intrinsic_global_atomic_umin
:
444 case nir_intrinsic_global_atomic_imax
:
445 case nir_intrinsic_global_atomic_umax
:
446 case nir_intrinsic_global_atomic_and
:
447 case nir_intrinsic_global_atomic_or
:
448 case nir_intrinsic_global_atomic_xor
:
449 case nir_intrinsic_global_atomic_exchange
:
450 case nir_intrinsic_global_atomic_comp_swap
:
451 case nir_intrinsic_image_deref_atomic_add
:
452 case nir_intrinsic_image_deref_atomic_umin
:
453 case nir_intrinsic_image_deref_atomic_imin
:
454 case nir_intrinsic_image_deref_atomic_umax
:
455 case nir_intrinsic_image_deref_atomic_imax
:
456 case nir_intrinsic_image_deref_atomic_and
:
457 case nir_intrinsic_image_deref_atomic_or
:
458 case nir_intrinsic_image_deref_atomic_xor
:
459 case nir_intrinsic_image_deref_atomic_exchange
:
460 case nir_intrinsic_image_deref_atomic_comp_swap
:
461 case nir_intrinsic_image_deref_size
:
462 case nir_intrinsic_shared_atomic_add
:
463 case nir_intrinsic_shared_atomic_imin
:
464 case nir_intrinsic_shared_atomic_umin
:
465 case nir_intrinsic_shared_atomic_imax
:
466 case nir_intrinsic_shared_atomic_umax
:
467 case nir_intrinsic_shared_atomic_and
:
468 case nir_intrinsic_shared_atomic_or
:
469 case nir_intrinsic_shared_atomic_xor
:
470 case nir_intrinsic_shared_atomic_exchange
:
471 case nir_intrinsic_shared_atomic_comp_swap
:
472 case nir_intrinsic_load_scratch
:
473 case nir_intrinsic_load_invocation_id
:
474 case nir_intrinsic_load_primitive_id
:
475 type
= RegType::vgpr
;
477 case nir_intrinsic_shuffle
:
478 case nir_intrinsic_quad_broadcast
:
479 case nir_intrinsic_quad_swap_horizontal
:
480 case nir_intrinsic_quad_swap_vertical
:
481 case nir_intrinsic_quad_swap_diagonal
:
482 case nir_intrinsic_quad_swizzle_amd
:
483 case nir_intrinsic_masked_swizzle_amd
:
484 case nir_intrinsic_inclusive_scan
:
485 case nir_intrinsic_exclusive_scan
:
486 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
487 size
= lane_mask_size
;
488 type
= RegType::sgpr
;
489 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
490 type
= RegType::sgpr
;
492 type
= RegType::vgpr
;
495 case nir_intrinsic_load_view_index
:
496 type
= ctx
->stage
== fragment_fs
? RegType::vgpr
: RegType::sgpr
;
498 case nir_intrinsic_load_front_face
:
499 case nir_intrinsic_load_helper_invocation
:
500 case nir_intrinsic_is_helper_invocation
:
501 type
= RegType::sgpr
;
502 size
= lane_mask_size
;
504 case nir_intrinsic_reduce
:
505 if (intrinsic
->dest
.ssa
.bit_size
== 1) {
506 size
= lane_mask_size
;
507 type
= RegType::sgpr
;
508 } else if (!ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
]) {
509 type
= RegType::sgpr
;
511 type
= RegType::vgpr
;
514 case nir_intrinsic_load_ubo
:
515 case nir_intrinsic_load_ssbo
:
516 case nir_intrinsic_load_global
:
517 case nir_intrinsic_vulkan_resource_index
:
518 type
= ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
] ? RegType::vgpr
: RegType::sgpr
;
520 /* due to copy propagation, the swizzled imov is removed if num dest components == 1 */
521 case nir_intrinsic_load_shared
:
522 if (ctx
->divergent_vals
[intrinsic
->dest
.ssa
.index
])
523 type
= RegType::vgpr
;
525 type
= RegType::sgpr
;
528 for (unsigned i
= 0; i
< nir_intrinsic_infos
[intrinsic
->intrinsic
].num_srcs
; i
++) {
529 if (allocated
[intrinsic
->src
[i
].ssa
->index
].type() == RegType::vgpr
)
530 type
= RegType::vgpr
;
534 allocated
[intrinsic
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
536 switch(intrinsic
->intrinsic
) {
537 case nir_intrinsic_load_barycentric_sample
:
538 case nir_intrinsic_load_barycentric_pixel
:
539 case nir_intrinsic_load_barycentric_centroid
:
540 case nir_intrinsic_load_barycentric_at_sample
:
541 case nir_intrinsic_load_barycentric_at_offset
: {
542 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(intrinsic
);
543 spi_ps_inputs
|= get_interp_input(intrinsic
->intrinsic
, mode
);
546 case nir_intrinsic_load_barycentric_model
:
547 spi_ps_inputs
|= S_0286CC_PERSP_PULL_MODEL_ENA(1);
549 case nir_intrinsic_load_front_face
:
550 spi_ps_inputs
|= S_0286CC_FRONT_FACE_ENA(1);
552 case nir_intrinsic_load_frag_coord
:
553 case nir_intrinsic_load_sample_pos
: {
554 uint8_t mask
= nir_ssa_def_components_read(&intrinsic
->dest
.ssa
);
555 for (unsigned i
= 0; i
< 4; i
++) {
557 spi_ps_inputs
|= S_0286CC_POS_X_FLOAT_ENA(1) << i
;
562 case nir_intrinsic_load_sample_id
:
563 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
565 case nir_intrinsic_load_sample_mask_in
:
566 spi_ps_inputs
|= S_0286CC_ANCILLARY_ENA(1);
567 spi_ps_inputs
|= S_0286CC_SAMPLE_COVERAGE_ENA(1);
574 case nir_instr_type_tex
: {
575 nir_tex_instr
* tex
= nir_instr_as_tex(instr
);
576 unsigned size
= tex
->dest
.ssa
.num_components
;
578 if (tex
->dest
.ssa
.bit_size
== 64)
580 if (tex
->op
== nir_texop_texture_samples
)
581 assert(!ctx
->divergent_vals
[tex
->dest
.ssa
.index
]);
582 if (ctx
->divergent_vals
[tex
->dest
.ssa
.index
])
583 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::vgpr
, size
));
585 allocated
[tex
->dest
.ssa
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
588 case nir_instr_type_parallel_copy
: {
589 nir_foreach_parallel_copy_entry(entry
, nir_instr_as_parallel_copy(instr
)) {
590 allocated
[entry
->dest
.ssa
.index
] = allocated
[entry
->src
.ssa
->index
];
594 case nir_instr_type_ssa_undef
: {
595 unsigned size
= nir_instr_as_ssa_undef(instr
)->def
.num_components
;
596 if (nir_instr_as_ssa_undef(instr
)->def
.bit_size
== 64)
598 else if (nir_instr_as_ssa_undef(instr
)->def
.bit_size
== 1)
599 size
*= lane_mask_size
;
600 allocated
[nir_instr_as_ssa_undef(instr
)->def
.index
] = Temp(0, RegClass(RegType::sgpr
, size
));
603 case nir_instr_type_phi
: {
604 nir_phi_instr
* phi
= nir_instr_as_phi(instr
);
606 unsigned size
= phi
->dest
.ssa
.num_components
;
608 if (phi
->dest
.ssa
.bit_size
== 1) {
609 assert(size
== 1 && "multiple components not yet supported on boolean phis.");
610 type
= RegType::sgpr
;
611 size
*= lane_mask_size
;
612 allocated
[phi
->dest
.ssa
.index
] = Temp(0, RegClass(type
, size
));
616 if (ctx
->divergent_vals
[phi
->dest
.ssa
.index
]) {
617 type
= RegType::vgpr
;
619 type
= RegType::sgpr
;
620 nir_foreach_phi_src (src
, phi
) {
621 if (allocated
[src
->src
.ssa
->index
].type() == RegType::vgpr
)
622 type
= RegType::vgpr
;
623 if (allocated
[src
->src
.ssa
->index
].type() == RegType::none
)
628 size
*= phi
->dest
.ssa
.bit_size
== 64 ? 2 : 1;
629 RegClass rc
= RegClass(type
, size
);
630 if (rc
!= allocated
[phi
->dest
.ssa
.index
].regClass()) {
633 nir_foreach_phi_src(src
, phi
)
634 assert(allocated
[src
->src
.ssa
->index
].size() == rc
.size());
636 allocated
[phi
->dest
.ssa
.index
] = Temp(0, rc
);
646 if (G_0286CC_POS_W_FLOAT_ENA(spi_ps_inputs
)) {
647 /* If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be enabled too */
648 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
651 if (!(spi_ps_inputs
& 0x7F)) {
652 /* At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled */
653 spi_ps_inputs
|= S_0286CC_PERSP_CENTER_ENA(1);
656 ctx
->program
->config
->spi_ps_input_ena
= spi_ps_inputs
;
657 ctx
->program
->config
->spi_ps_input_addr
= spi_ps_inputs
;
659 for (unsigned i
= 0; i
< impl
->ssa_alloc
; i
++)
660 allocated
[i
] = Temp(ctx
->program
->allocateId(), allocated
[i
].regClass());
662 ctx
->allocated
.reset(allocated
.release());
663 ctx
->cf_info
.nir_to_aco
.reset(nir_to_aco
.release());
666 Pseudo_instruction
*add_startpgm(struct isel_context
*ctx
)
668 unsigned arg_count
= ctx
->args
->ac
.arg_count
;
669 if (ctx
->stage
== fragment_fs
) {
670 /* LLVM optimizes away unused FS inputs and computes spi_ps_input_addr
671 * itself and then communicates the results back via the ELF binary.
672 * Mirror what LLVM does by re-mapping the VGPR arguments here.
674 * TODO: If we made the FS input scanning code into a separate pass that
675 * could run before argument setup, then this wouldn't be necessary
678 struct ac_shader_args
*args
= &ctx
->args
->ac
;
680 for (unsigned i
= 0, vgpr_arg
= 0, vgpr_reg
= 0; i
< args
->arg_count
; i
++) {
681 if (args
->args
[i
].file
!= AC_ARG_VGPR
) {
686 if (!(ctx
->program
->config
->spi_ps_input_addr
& (1 << vgpr_arg
))) {
687 args
->args
[i
].skip
= true;
689 args
->args
[i
].offset
= vgpr_reg
;
690 vgpr_reg
+= args
->args
[i
].size
;
697 aco_ptr
<Pseudo_instruction
> startpgm
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_startpgm
, Format::PSEUDO
, 0, arg_count
+ 1)};
698 for (unsigned i
= 0, arg
= 0; i
< ctx
->args
->ac
.arg_count
; i
++) {
699 if (ctx
->args
->ac
.args
[i
].skip
)
702 enum ac_arg_regfile file
= ctx
->args
->ac
.args
[i
].file
;
703 unsigned size
= ctx
->args
->ac
.args
[i
].size
;
704 unsigned reg
= ctx
->args
->ac
.args
[i
].offset
;
705 RegClass type
= RegClass(file
== AC_ARG_SGPR
? RegType::sgpr
: RegType::vgpr
, size
);
706 Temp dst
= Temp
{ctx
->program
->allocateId(), type
};
707 ctx
->arg_temps
[i
] = dst
;
708 startpgm
->definitions
[arg
] = Definition(dst
);
709 startpgm
->definitions
[arg
].setFixed(PhysReg
{file
== AC_ARG_SGPR
? reg
: reg
+ 256});
712 startpgm
->definitions
[arg_count
] = Definition
{ctx
->program
->allocateId(), exec
, ctx
->program
->lane_mask
};
713 Pseudo_instruction
*instr
= startpgm
.get();
714 ctx
->block
->instructions
.push_back(std::move(startpgm
));
716 /* Stash these in the program so that they can be accessed later when
719 ctx
->program
->private_segment_buffer
= get_arg(ctx
, ctx
->args
->ring_offsets
);
720 ctx
->program
->scratch_offset
= get_arg(ctx
, ctx
->args
->scratch_offset
);
726 type_size(const struct glsl_type
*type
, bool bindless
)
728 // TODO: don't we need type->std430_base_alignment() here?
729 return glsl_count_attribute_slots(type
, false);
733 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
735 assert(glsl_type_is_vector_or_scalar(type
));
737 uint32_t comp_size
= glsl_type_is_boolean(type
)
738 ? 4 : glsl_get_bit_size(type
) / 8;
739 unsigned length
= glsl_get_vector_elements(type
);
740 *size
= comp_size
* length
,
745 mem_vectorize_callback(unsigned align
, unsigned bit_size
,
746 unsigned num_components
, unsigned high_offset
,
747 nir_intrinsic_instr
*low
, nir_intrinsic_instr
*high
)
749 if ((bit_size
!= 32 && bit_size
!= 64) || num_components
> 4)
752 /* >128 bit loads are split except with SMEM */
753 if (bit_size
* num_components
> 128)
756 switch (low
->intrinsic
) {
757 case nir_intrinsic_load_ubo
:
758 case nir_intrinsic_load_ssbo
:
759 case nir_intrinsic_store_ssbo
:
760 case nir_intrinsic_load_push_constant
:
761 return align
% 4 == 0;
762 case nir_intrinsic_load_deref
:
763 case nir_intrinsic_store_deref
:
764 assert(nir_src_as_deref(low
->src
[0])->mode
== nir_var_mem_shared
);
766 case nir_intrinsic_load_shared
:
767 case nir_intrinsic_store_shared
:
768 if (bit_size
* num_components
> 64) /* 96 and 128 bit loads require 128 bit alignment and are split otherwise */
769 return align
% 16 == 0;
771 return align
% 4 == 0;
779 setup_vs_output_info(isel_context
*ctx
, nir_shader
*nir
,
780 bool export_prim_id
, bool export_clip_dists
,
781 radv_vs_output_info
*outinfo
)
783 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
784 sizeof(outinfo
->vs_output_param_offset
));
786 outinfo
->param_exports
= 0;
787 int pos_written
= 0x1;
788 if (outinfo
->writes_pointsize
|| outinfo
->writes_viewport_index
|| outinfo
->writes_layer
)
789 pos_written
|= 1 << 1;
791 uint64_t mask
= ctx
->output_masks
[nir
->info
.stage
];
793 int idx
= u_bit_scan64(&mask
);
794 if (idx
>= VARYING_SLOT_VAR0
|| idx
== VARYING_SLOT_LAYER
|| idx
== VARYING_SLOT_PRIMITIVE_ID
||
795 ((idx
== VARYING_SLOT_CLIP_DIST0
|| idx
== VARYING_SLOT_CLIP_DIST1
) && export_clip_dists
)) {
796 if (outinfo
->vs_output_param_offset
[idx
] == AC_EXP_PARAM_UNDEFINED
)
797 outinfo
->vs_output_param_offset
[idx
] = outinfo
->param_exports
++;
800 if (outinfo
->writes_layer
&&
801 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] == AC_EXP_PARAM_UNDEFINED
) {
802 /* when ctx->options->key.has_multiview_view_index = true, the layer
803 * variable isn't declared in NIR and it's isel's job to get the layer */
804 outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
] = outinfo
->param_exports
++;
807 if (export_prim_id
) {
808 assert(outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] == AC_EXP_PARAM_UNDEFINED
);
809 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = outinfo
->param_exports
++;
812 ctx
->export_clip_dists
= export_clip_dists
;
813 ctx
->num_clip_distances
= util_bitcount(outinfo
->clip_dist_mask
);
814 ctx
->num_cull_distances
= util_bitcount(outinfo
->cull_dist_mask
);
816 assert(ctx
->num_clip_distances
+ ctx
->num_cull_distances
<= 8);
818 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
819 pos_written
|= 1 << 2;
820 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
821 pos_written
|= 1 << 3;
823 outinfo
->pos_exports
= util_bitcount(pos_written
);
827 setup_vs_variables(isel_context
*ctx
, nir_shader
*nir
)
829 nir_foreach_variable(variable
, &nir
->inputs
)
831 variable
->data
.driver_location
= variable
->data
.location
* 4;
833 nir_foreach_variable(variable
, &nir
->outputs
)
835 if (ctx
->stage
== vertex_geometry_gs
)
836 variable
->data
.driver_location
= util_bitcount64(ctx
->output_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
837 else if (ctx
->stage
== vertex_es
||
838 ctx
->stage
== vertex_ls
||
839 ctx
->stage
== vertex_tess_control_hs
)
840 // TODO: make this more compact
841 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
842 else if (ctx
->stage
== vertex_vs
)
843 variable
->data
.driver_location
= variable
->data
.location
* 4;
845 unreachable("Unsupported VS stage");
848 if (ctx
->stage
== vertex_vs
) {
849 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
850 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
851 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
852 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== vertex_es
) {
853 /* TODO: radv_nir_shader_info_pass() already sets this but it's larger
854 * than it needs to be in order to set it better, we have to improve
855 * radv_nir_shader_info_pass() because gfx9_get_gs_info() uses
856 * esgs_itemsize and has to be done before compilation
858 /* radv_es_output_info *outinfo = &ctx->program->info->vs.es_info;
859 outinfo->esgs_itemsize = util_bitcount64(ctx->output_masks[nir->info.stage]) * 16u; */
863 void setup_gs_variables(isel_context
*ctx
, nir_shader
*nir
)
865 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
866 nir_foreach_variable(variable
, &nir
->inputs
) {
867 variable
->data
.driver_location
= util_bitcount64(ctx
->input_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
869 } else if (ctx
->stage
== geometry_gs
) {
870 //TODO: make this more compact
871 nir_foreach_variable(variable
, &nir
->inputs
) {
872 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
)variable
->data
.location
) * 4;
875 unreachable("Unsupported GS stage.");
878 nir_foreach_variable(variable
, &nir
->outputs
) {
879 variable
->data
.driver_location
= variable
->data
.location
* 4;
882 if (ctx
->stage
== vertex_geometry_gs
)
883 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_VERTEX
;
884 else if (ctx
->stage
== tess_eval_geometry_gs
)
885 ctx
->program
->info
->gs
.es_type
= MESA_SHADER_TESS_EVAL
;
889 setup_tcs_variables(isel_context
*ctx
, nir_shader
*nir
)
891 switch (ctx
->stage
) {
892 case tess_control_hs
:
893 ctx
->tcs_num_inputs
= ctx
->args
->options
->key
.tcs
.num_inputs
;
895 case vertex_tess_control_hs
:
896 ctx
->tcs_num_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
899 unreachable("Unsupported TCS shader stage");
902 ctx
->tcs_num_patches
= get_tcs_num_patches(
903 ctx
->args
->options
->key
.tcs
.input_vertices
,
904 nir
->info
.tess
.tcs_vertices_out
,
906 ctx
->args
->shader_info
->tcs
.outputs_written
,
907 ctx
->args
->shader_info
->tcs
.patch_outputs_written
,
908 ctx
->args
->options
->tess_offchip_block_dw_size
,
909 ctx
->args
->options
->chip_class
,
910 ctx
->args
->options
->family
);
911 unsigned lds_size
= calculate_tess_lds_size(
912 ctx
->args
->options
->key
.tcs
.input_vertices
,
913 nir
->info
.tess
.tcs_vertices_out
,
915 ctx
->tcs_num_patches
,
916 ctx
->args
->shader_info
->tcs
.outputs_written
,
917 ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
919 ctx
->args
->shader_info
->tcs
.num_patches
= ctx
->tcs_num_patches
;
920 ctx
->args
->shader_info
->tcs
.lds_size
= lds_size
;
921 ctx
->program
->config
->lds_size
= (lds_size
+ ctx
->program
->lds_alloc_granule
- 1) /
922 ctx
->program
->lds_alloc_granule
;
924 nir_foreach_variable(variable
, &nir
->inputs
) {
925 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
928 nir_foreach_variable(variable
, &nir
->outputs
) {
929 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
932 ctx
->tcs_tess_lvl_out_loc
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
) * 16u;
933 ctx
->tcs_tess_lvl_in_loc
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
) * 16u;
937 setup_tes_variables(isel_context
*ctx
, nir_shader
*nir
)
939 ctx
->tcs_num_patches
= ctx
->args
->options
->key
.tes
.num_patches
;
941 nir_foreach_variable(variable
, &nir
->inputs
) {
942 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
945 nir_foreach_variable(variable
, &nir
->outputs
) {
946 if (ctx
->stage
== tess_eval_vs
)
947 variable
->data
.driver_location
= variable
->data
.location
* 4;
948 else if (ctx
->stage
== tess_eval_es
)
949 variable
->data
.driver_location
= shader_io_get_unique_index((gl_varying_slot
) variable
->data
.location
) * 4;
950 else if (ctx
->stage
== tess_eval_geometry_gs
)
951 variable
->data
.driver_location
= util_bitcount64(ctx
->output_masks
[nir
->info
.stage
] & ((1ull << variable
->data
.location
) - 1ull)) * 4;
953 unreachable("Unsupported TES shader stage");
956 if (ctx
->stage
== tess_eval_vs
) {
957 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->tes
.outinfo
;
958 setup_vs_output_info(ctx
, nir
, outinfo
->export_prim_id
,
959 ctx
->options
->key
.vs_common_out
.export_clip_dists
, outinfo
);
964 setup_variables(isel_context
*ctx
, nir_shader
*nir
)
966 switch (nir
->info
.stage
) {
967 case MESA_SHADER_FRAGMENT
: {
968 nir_foreach_variable(variable
, &nir
->outputs
)
970 int idx
= variable
->data
.location
+ variable
->data
.index
;
971 variable
->data
.driver_location
= idx
* 4;
975 case MESA_SHADER_COMPUTE
: {
976 ctx
->program
->config
->lds_size
= (nir
->info
.cs
.shared_size
+ ctx
->program
->lds_alloc_granule
- 1) /
977 ctx
->program
->lds_alloc_granule
;
980 case MESA_SHADER_VERTEX
: {
981 setup_vs_variables(ctx
, nir
);
984 case MESA_SHADER_GEOMETRY
: {
985 setup_gs_variables(ctx
, nir
);
988 case MESA_SHADER_TESS_CTRL
: {
989 setup_tcs_variables(ctx
, nir
);
992 case MESA_SHADER_TESS_EVAL
: {
993 setup_tes_variables(ctx
, nir
);
997 unreachable("Unhandled shader stage.");
1002 get_io_masks(isel_context
*ctx
, unsigned shader_count
, struct nir_shader
*const *shaders
)
1004 for (unsigned i
= 0; i
< shader_count
; i
++) {
1005 nir_shader
*nir
= shaders
[i
];
1006 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
)
1009 uint64_t output_mask
= 0;
1010 nir_foreach_variable(variable
, &nir
->outputs
) {
1011 const glsl_type
*type
= variable
->type
;
1012 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
1013 type
= type
->fields
.array
;
1014 unsigned slots
= type
->count_attribute_slots(false);
1015 if (variable
->data
.compact
) {
1016 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
1017 slots
= (component_count
+ 3) / 4;
1019 output_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
1022 uint64_t input_mask
= 0;
1023 nir_foreach_variable(variable
, &nir
->inputs
) {
1024 const glsl_type
*type
= variable
->type
;
1025 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
))
1026 type
= type
->fields
.array
;
1027 unsigned slots
= type
->count_attribute_slots(false);
1028 if (variable
->data
.compact
) {
1029 unsigned component_count
= variable
->data
.location_frac
+ type
->length
;
1030 slots
= (component_count
+ 3) / 4;
1032 input_mask
|= ((1ull << slots
) - 1) << variable
->data
.location
;
1035 ctx
->output_masks
[nir
->info
.stage
] |= output_mask
;
1036 if (i
+ 1 < shader_count
)
1037 ctx
->input_masks
[shaders
[i
+ 1]->info
.stage
] |= output_mask
;
1039 ctx
->input_masks
[nir
->info
.stage
] |= input_mask
;
1041 ctx
->output_masks
[shaders
[i
- 1]->info
.stage
] |= input_mask
;
1046 setup_nir(isel_context
*ctx
, nir_shader
*nir
)
1048 Program
*program
= ctx
->program
;
1050 /* align and copy constant data */
1051 while (program
->constant_data
.size() % 4u)
1052 program
->constant_data
.push_back(0);
1053 ctx
->constant_data_offset
= program
->constant_data
.size();
1054 program
->constant_data
.insert(program
->constant_data
.end(),
1055 (uint8_t*)nir
->constant_data
,
1056 (uint8_t*)nir
->constant_data
+ nir
->constant_data_size
);
1058 /* the variable setup has to be done before lower_io / CSE */
1059 setup_variables(ctx
, nir
);
1061 /* optimize and lower memory operations */
1062 bool lower_to_scalar
= false;
1063 bool lower_pack
= false;
1064 if (nir_opt_load_store_vectorize(nir
,
1065 (nir_variable_mode
)(nir_var_mem_ssbo
| nir_var_mem_ubo
|
1066 nir_var_mem_push_const
| nir_var_mem_shared
),
1067 mem_vectorize_callback
)) {
1068 lower_to_scalar
= true;
1071 if (nir
->info
.stage
!= MESA_SHADER_COMPUTE
)
1072 nir_lower_io(nir
, (nir_variable_mode
)(nir_var_shader_in
| nir_var_shader_out
), type_size
, (nir_lower_io_options
)0);
1073 nir_lower_explicit_io(nir
, nir_var_mem_global
, nir_address_format_64bit_global
);
1075 if (lower_to_scalar
)
1076 nir_lower_alu_to_scalar(nir
, NULL
, NULL
);
1078 nir_lower_pack(nir
);
1080 /* lower ALU operations */
1081 // TODO: implement logic64 in aco, it's more effective for sgprs
1082 nir_lower_int64(nir
, nir
->options
->lower_int64_options
);
1084 nir_opt_idiv_const(nir
, 32);
1085 nir_lower_idiv(nir
, nir_lower_idiv_precise
);
1087 /* optimize the lowered ALU operations */
1088 bool more_algebraic
= true;
1089 while (more_algebraic
) {
1090 more_algebraic
= false;
1091 NIR_PASS_V(nir
, nir_copy_prop
);
1092 NIR_PASS_V(nir
, nir_opt_dce
);
1093 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1094 NIR_PASS(more_algebraic
, nir
, nir_opt_algebraic
);
1097 /* Do late algebraic optimization to turn add(a, neg(b)) back into
1098 * subs, then the mandatory cleanup after algebraic. Note that it may
1099 * produce fnegs, and if so then we need to keep running to squash
1102 bool more_late_algebraic
= true;
1103 while (more_late_algebraic
) {
1104 more_late_algebraic
= false;
1105 NIR_PASS(more_late_algebraic
, nir
, nir_opt_algebraic_late
);
1106 NIR_PASS_V(nir
, nir_opt_constant_folding
);
1107 NIR_PASS_V(nir
, nir_copy_prop
);
1108 NIR_PASS_V(nir
, nir_opt_dce
);
1109 NIR_PASS_V(nir
, nir_opt_cse
);
1112 /* cleanup passes */
1113 nir_lower_load_const_to_scalar(nir
);
1114 nir_opt_shrink_load(nir
);
1115 nir_move_options move_opts
= (nir_move_options
)(
1116 nir_move_const_undef
| nir_move_load_ubo
| nir_move_load_input
|
1117 nir_move_comparisons
| nir_move_copies
);
1118 nir_opt_sink(nir
, move_opts
);
1119 nir_opt_move(nir
, move_opts
);
1120 nir_convert_to_lcssa(nir
, true, false);
1121 nir_lower_phis_to_scalar(nir
);
1123 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
1124 nir_index_ssa_defs(func
);
1128 setup_isel_context(Program
* program
,
1129 unsigned shader_count
,
1130 struct nir_shader
*const *shaders
,
1131 ac_shader_config
* config
,
1132 struct radv_shader_args
*args
,
1133 bool is_gs_copy_shader
)
1136 for (unsigned i
= 0; i
< shader_count
; i
++) {
1137 switch (shaders
[i
]->info
.stage
) {
1138 case MESA_SHADER_VERTEX
:
1139 program
->stage
|= sw_vs
;
1141 case MESA_SHADER_TESS_CTRL
:
1142 program
->stage
|= sw_tcs
;
1144 case MESA_SHADER_TESS_EVAL
:
1145 program
->stage
|= sw_tes
;
1147 case MESA_SHADER_GEOMETRY
:
1148 program
->stage
|= is_gs_copy_shader
? sw_gs_copy
: sw_gs
;
1150 case MESA_SHADER_FRAGMENT
:
1151 program
->stage
|= sw_fs
;
1153 case MESA_SHADER_COMPUTE
:
1154 program
->stage
|= sw_cs
;
1157 unreachable("Shader stage not implemented");
1160 bool gfx9_plus
= args
->options
->chip_class
>= GFX9
;
1161 bool ngg
= args
->shader_info
->is_ngg
&& args
->options
->chip_class
>= GFX10
;
1162 if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_es
)
1163 program
->stage
|= hw_es
;
1164 else if (program
->stage
== sw_vs
&& !args
->shader_info
->vs
.as_ls
)
1165 program
->stage
|= hw_vs
;
1166 else if (program
->stage
== sw_gs
)
1167 program
->stage
|= hw_gs
;
1168 else if (program
->stage
== sw_fs
)
1169 program
->stage
|= hw_fs
;
1170 else if (program
->stage
== sw_cs
)
1171 program
->stage
|= hw_cs
;
1172 else if (program
->stage
== sw_gs_copy
)
1173 program
->stage
|= hw_vs
;
1174 else if (program
->stage
== (sw_vs
| sw_gs
) && gfx9_plus
&& !ngg
)
1175 program
->stage
|= hw_gs
;
1176 else if (program
->stage
== sw_vs
&& args
->shader_info
->vs
.as_ls
)
1177 program
->stage
|= hw_ls
; /* GFX6-8: VS is a Local Shader, when tessellation is used */
1178 else if (program
->stage
== sw_tcs
)
1179 program
->stage
|= hw_hs
; /* GFX6-8: TCS is a Hull Shader */
1180 else if (program
->stage
== (sw_vs
| sw_tcs
))
1181 program
->stage
|= hw_hs
; /* GFX9-10: VS+TCS merged into a Hull Shader */
1182 else if (program
->stage
== sw_tes
&& !args
->shader_info
->tes
.as_es
&& !ngg
)
1183 program
->stage
|= hw_vs
; /* GFX6-9: TES without GS uses the HW VS stage (and GFX10/legacy) */
1184 else if (program
->stage
== sw_tes
&& args
->shader_info
->tes
.as_es
&& !ngg
)
1185 program
->stage
|= hw_es
; /* GFX6-8: TES is an Export Shader */
1186 else if (program
->stage
== (sw_tes
| sw_gs
) && gfx9_plus
&& !ngg
)
1187 program
->stage
|= hw_gs
; /* GFX9: TES+GS merged into a GS (and GFX10/legacy) */
1189 unreachable("Shader stage not implemented");
1191 program
->config
= config
;
1192 program
->info
= args
->shader_info
;
1193 program
->chip_class
= args
->options
->chip_class
;
1194 program
->family
= args
->options
->family
;
1195 program
->wave_size
= args
->shader_info
->wave_size
;
1196 program
->lane_mask
= program
->wave_size
== 32 ? s1
: s2
;
1198 program
->lds_alloc_granule
= args
->options
->chip_class
>= GFX7
? 512 : 256;
1199 program
->lds_limit
= args
->options
->chip_class
>= GFX7
? 65536 : 32768;
1200 /* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
1201 program
->has_16bank_lds
= args
->options
->family
== CHIP_KABINI
|| args
->options
->family
== CHIP_STONEY
;
1203 program
->vgpr_limit
= 256;
1204 program
->vgpr_alloc_granule
= 3;
1206 if (args
->options
->chip_class
>= GFX10
) {
1207 program
->physical_sgprs
= 2560; /* doesn't matter as long as it's at least 128 * 20 */
1208 program
->sgpr_alloc_granule
= 127;
1209 program
->sgpr_limit
= 106;
1210 program
->vgpr_alloc_granule
= program
->wave_size
== 32 ? 7 : 3;
1211 } else if (program
->chip_class
>= GFX8
) {
1212 program
->physical_sgprs
= 800;
1213 program
->sgpr_alloc_granule
= 15;
1214 if (args
->options
->family
== CHIP_TONGA
|| args
->options
->family
== CHIP_ICELAND
)
1215 program
->sgpr_limit
= 94; /* workaround hardware bug */
1217 program
->sgpr_limit
= 102;
1219 program
->physical_sgprs
= 512;
1220 program
->sgpr_alloc_granule
= 7;
1221 program
->sgpr_limit
= 104;
1224 calc_min_waves(program
);
1225 program
->vgpr_limit
= get_addr_vgpr_from_waves(program
, program
->min_waves
);
1226 program
->sgpr_limit
= get_addr_sgpr_from_waves(program
, program
->min_waves
);
1228 isel_context ctx
= {};
1229 ctx
.program
= program
;
1231 ctx
.options
= args
->options
;
1232 ctx
.stage
= program
->stage
;
1234 get_io_masks(&ctx
, shader_count
, shaders
);
1236 unsigned scratch_size
= 0;
1237 if (program
->stage
== gs_copy_vs
) {
1238 assert(shader_count
== 1);
1239 setup_vs_output_info(&ctx
, shaders
[0], false, true, &args
->shader_info
->vs
.outinfo
);
1241 for (unsigned i
= 0; i
< shader_count
; i
++) {
1242 nir_shader
*nir
= shaders
[i
];
1243 setup_nir(&ctx
, nir
);
1246 for (unsigned i
= 0; i
< shader_count
; i
++)
1247 scratch_size
= std::max(scratch_size
, shaders
[i
]->scratch_size
);
1250 ctx
.program
->config
->scratch_bytes_per_wave
= align(scratch_size
* ctx
.program
->wave_size
, 1024);
1252 ctx
.block
= ctx
.program
->create_and_insert_block();
1253 ctx
.block
->loop_nest_depth
= 0;
1254 ctx
.block
->kind
= block_kind_top_level
;