801fbc68616be47af44a9f83abb9e6c358e7454c
[mesa.git] / src / amd / compiler / aco_ir.cpp
1 /*
2 * Copyright © 2020 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24 #include "aco_ir.h"
25 #include "vulkan/radv_shader.h"
26 #include "c11/threads.h"
27 #include "util/debug.h"
28
29 namespace aco {
30
31 uint64_t debug_flags = 0;
32
33 static const struct debug_control aco_debug_options[] = {
34 {"validateir", DEBUG_VALIDATE_IR},
35 {"validatera", DEBUG_VALIDATE_RA},
36 {"perfwarn", DEBUG_PERFWARN},
37 {"force-waitcnt", DEBUG_FORCE_WAITCNT},
38 {NULL, 0}
39 };
40
41 static once_flag init_once_flag = ONCE_FLAG_INIT;
42
43 static void init_once()
44 {
45 debug_flags = parse_debug_string(getenv("ACO_DEBUG"), aco_debug_options);
46
47 #ifndef NDEBUG
48 /* enable some flags by default on debug builds */
49 debug_flags |= aco::DEBUG_VALIDATE_IR;
50 #endif
51 }
52
53 void init()
54 {
55 call_once(&init_once_flag, init_once);
56 }
57
58 void init_program(Program *program, Stage stage, struct radv_shader_info *info,
59 enum chip_class chip_class, enum radeon_family family,
60 ac_shader_config *config)
61 {
62 program->stage = stage;
63 program->config = config;
64 program->info = info;
65 program->chip_class = chip_class;
66 if (family == CHIP_UNKNOWN) {
67 switch (chip_class) {
68 case GFX6:
69 program->family = CHIP_TAHITI;
70 break;
71 case GFX7:
72 program->family = CHIP_BONAIRE;
73 break;
74 case GFX8:
75 program->family = CHIP_POLARIS10;
76 break;
77 case GFX9:
78 program->family = CHIP_VEGA10;
79 break;
80 case GFX10:
81 program->family = CHIP_NAVI10;
82 break;
83 default:
84 program->family = CHIP_UNKNOWN;
85 break;
86 }
87 } else {
88 program->family = family;
89 }
90 program->wave_size = info->wave_size;
91 program->lane_mask = program->wave_size == 32 ? s1 : s2;
92
93 program->lds_alloc_granule = chip_class >= GFX7 ? 512 : 256;
94 program->lds_limit = chip_class >= GFX7 ? 65536 : 32768;
95 /* apparently gfx702 also has 16-bank LDS but I can't find a family for that */
96 program->has_16bank_lds = family == CHIP_KABINI || family == CHIP_STONEY;
97
98 program->vgpr_limit = 256;
99 program->vgpr_alloc_granule = 3;
100
101 if (chip_class >= GFX10) {
102 program->physical_sgprs = 2560; /* doesn't matter as long as it's at least 128 * 20 */
103 program->sgpr_alloc_granule = 127;
104 program->sgpr_limit = 106;
105 if (chip_class >= GFX10_3)
106 program->vgpr_alloc_granule = program->wave_size == 32 ? 15 : 7;
107 else
108 program->vgpr_alloc_granule = program->wave_size == 32 ? 7 : 3;
109 } else if (program->chip_class >= GFX8) {
110 program->physical_sgprs = 800;
111 program->sgpr_alloc_granule = 15;
112 if (family == CHIP_TONGA || family == CHIP_ICELAND)
113 program->sgpr_limit = 94; /* workaround hardware bug */
114 else
115 program->sgpr_limit = 102;
116 } else {
117 program->physical_sgprs = 512;
118 program->sgpr_alloc_granule = 7;
119 program->sgpr_limit = 104;
120 }
121
122 program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
123 program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
124 program->next_fp_mode.must_flush_denorms32 = false;
125 program->next_fp_mode.must_flush_denorms16_64 = false;
126 program->next_fp_mode.care_about_round32 = false;
127 program->next_fp_mode.care_about_round16_64 = false;
128 program->next_fp_mode.denorm16_64 = fp_denorm_keep;
129 program->next_fp_mode.denorm32 = 0;
130 program->next_fp_mode.round16_64 = fp_round_ne;
131 program->next_fp_mode.round32 = fp_round_ne;
132 }
133
134 memory_sync_info get_sync_info(const Instruction* instr)
135 {
136 switch (instr->format) {
137 case Format::SMEM:
138 return static_cast<const SMEM_instruction*>(instr)->sync;
139 case Format::MUBUF:
140 return static_cast<const MUBUF_instruction*>(instr)->sync;
141 case Format::MIMG:
142 return static_cast<const MIMG_instruction*>(instr)->sync;
143 case Format::MTBUF:
144 return static_cast<const MTBUF_instruction*>(instr)->sync;
145 case Format::FLAT:
146 case Format::GLOBAL:
147 case Format::SCRATCH:
148 return static_cast<const FLAT_instruction*>(instr)->sync;
149 case Format::DS:
150 return static_cast<const DS_instruction*>(instr)->sync;
151 default:
152 return memory_sync_info();
153 }
154 }
155
156 bool can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr)
157 {
158 if (!instr->isVALU())
159 return false;
160
161 if (chip < GFX8 || instr->isDPP())
162 return false;
163
164 if (instr->isSDWA())
165 return true;
166
167 if (instr->isVOP3()) {
168 VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
169 if (instr->format == Format::VOP3)
170 return false;
171 if (vop3->clamp && instr->format == asVOP3(Format::VOPC) && chip != GFX8)
172 return false;
173 if (vop3->omod && chip < GFX9)
174 return false;
175
176 //TODO: return true if we know we will use vcc
177 if (instr->definitions.size() >= 2)
178 return false;
179
180 for (unsigned i = 1; i < instr->operands.size(); i++) {
181 if (instr->operands[i].isLiteral())
182 return false;
183 if (chip < GFX9 && !instr->operands[i].isOfType(RegType::vgpr))
184 return false;
185 }
186 }
187
188 if (!instr->operands.empty()) {
189 if (instr->operands[0].isLiteral())
190 return false;
191 if (chip < GFX9 && !instr->operands[0].isOfType(RegType::vgpr))
192 return false;
193 }
194
195 bool is_mac = instr->opcode == aco_opcode::v_mac_f32 ||
196 instr->opcode == aco_opcode::v_mac_f16 ||
197 instr->opcode == aco_opcode::v_fmac_f32 ||
198 instr->opcode == aco_opcode::v_fmac_f16;
199
200 if (chip != GFX8 && is_mac)
201 return false;
202
203 //TODO: return true if we know we will use vcc
204 if ((unsigned)instr->format & (unsigned)Format::VOPC)
205 return false;
206 if (instr->operands.size() >= 3 && !is_mac)
207 return false;
208
209 return instr->opcode != aco_opcode::v_madmk_f32 &&
210 instr->opcode != aco_opcode::v_madak_f32 &&
211 instr->opcode != aco_opcode::v_madmk_f16 &&
212 instr->opcode != aco_opcode::v_madak_f16 &&
213 instr->opcode != aco_opcode::v_readfirstlane_b32 &&
214 instr->opcode != aco_opcode::v_clrexcp &&
215 instr->opcode != aco_opcode::v_swap_b32;
216 }
217
218 /* updates "instr" and returns the old instruction (or NULL if no update was needed) */
219 aco_ptr<Instruction> convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr)
220 {
221 if (instr->isSDWA())
222 return NULL;
223
224 aco_ptr<Instruction> tmp = std::move(instr);
225 Format format = (Format)(((uint16_t)tmp->format & ~(uint16_t)Format::VOP3) | (uint16_t)Format::SDWA);
226 instr.reset(create_instruction<SDWA_instruction>(tmp->opcode, format, tmp->operands.size(), tmp->definitions.size()));
227 std::copy(tmp->operands.cbegin(), tmp->operands.cend(), instr->operands.begin());
228 std::copy(tmp->definitions.cbegin(), tmp->definitions.cend(), instr->definitions.begin());
229
230 SDWA_instruction *sdwa = static_cast<SDWA_instruction*>(instr.get());
231
232 if (tmp->isVOP3()) {
233 VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(tmp.get());
234 memcpy(sdwa->neg, vop3->neg, sizeof(sdwa->neg));
235 memcpy(sdwa->abs, vop3->abs, sizeof(sdwa->abs));
236 sdwa->omod = vop3->omod;
237 sdwa->clamp = vop3->clamp;
238 }
239
240 for (unsigned i = 0; i < instr->operands.size(); i++) {
241 switch (instr->operands[i].bytes()) {
242 case 1:
243 sdwa->sel[i] = sdwa_ubyte;
244 break;
245 case 2:
246 sdwa->sel[i] = sdwa_uword;
247 break;
248 case 4:
249 sdwa->sel[i] = sdwa_udword;
250 break;
251 }
252 }
253 switch (instr->definitions[0].bytes()) {
254 case 1:
255 sdwa->dst_sel = sdwa_ubyte;
256 sdwa->dst_preserve = true;
257 break;
258 case 2:
259 sdwa->dst_sel = sdwa_uword;
260 sdwa->dst_preserve = true;
261 break;
262 case 4:
263 sdwa->dst_sel = sdwa_udword;
264 break;
265 }
266
267 if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8)
268 instr->definitions[0].setFixed(vcc);
269 if (instr->definitions.size() >= 2)
270 instr->definitions[1].setFixed(vcc);
271 if (instr->operands.size() >= 3)
272 instr->operands[2].setFixed(vcc);
273
274 return tmp;
275 }
276
277 bool can_use_opsel(chip_class chip, aco_opcode op, int idx, bool high)
278 {
279 /* opsel is only GFX9+ */
280 if ((high || idx == -1) && chip < GFX9)
281 return false;
282
283 switch (op) {
284 case aco_opcode::v_div_fixup_f16:
285 case aco_opcode::v_fma_f16:
286 case aco_opcode::v_mad_f16:
287 case aco_opcode::v_mad_u16:
288 case aco_opcode::v_mad_i16:
289 case aco_opcode::v_med3_f16:
290 case aco_opcode::v_med3_i16:
291 case aco_opcode::v_med3_u16:
292 case aco_opcode::v_min3_f16:
293 case aco_opcode::v_min3_i16:
294 case aco_opcode::v_min3_u16:
295 case aco_opcode::v_max3_f16:
296 case aco_opcode::v_max3_i16:
297 case aco_opcode::v_max3_u16:
298 case aco_opcode::v_max_u16_e64:
299 case aco_opcode::v_max_i16_e64:
300 case aco_opcode::v_min_u16_e64:
301 case aco_opcode::v_min_i16_e64:
302 case aco_opcode::v_add_i16:
303 case aco_opcode::v_sub_i16:
304 case aco_opcode::v_add_u16_e64:
305 case aco_opcode::v_sub_u16_e64:
306 case aco_opcode::v_cvt_pknorm_i16_f16:
307 case aco_opcode::v_cvt_pknorm_u16_f16:
308 case aco_opcode::v_lshlrev_b16_e64:
309 case aco_opcode::v_lshrrev_b16_e64:
310 case aco_opcode::v_ashrrev_i16_e64:
311 case aco_opcode::v_mul_lo_u16_e64:
312 return true;
313 case aco_opcode::v_pack_b32_f16:
314 return idx != -1;
315 case aco_opcode::v_mad_u32_u16:
316 case aco_opcode::v_mad_i32_i16:
317 return idx >= 0 && idx < 2;
318 default:
319 return false;
320 }
321 }
322
323 }