2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
34 #include "ac_binary.h"
35 #include "amd_family.h"
36 #include "aco_opcodes.h"
39 struct radv_nir_compiler_options
;
40 struct radv_shader_args
;
41 struct radv_shader_info
;
45 extern uint64_t debug_flags
;
49 DEBUG_VALIDATE_RA
= 0x2,
54 * Representation of the instruction's microcode encoding format
55 * Note: Some Vector ALU Formats can be combined, such that:
56 * - VOP2* | VOP3A represents a VOP2 instruction in VOP3A encoding
57 * - VOP2* | DPP represents a VOP2 instruction with data parallel primitive.
58 * - VOP2* | SDWA represents a VOP2 instruction with sub-dword addressing.
60 * (*) The same is applicable for VOP1 and VOPC instructions.
62 enum class Format
: std::uint16_t {
63 /* Pseudo Instruction Format */
65 /* Scalar ALU & Control Formats */
71 /* Scalar Memory Format */
75 /* Vector Memory Buffer Formats */
78 /* Vector Memory Image Format */
89 PSEUDO_REDUCTION
= 18,
91 /* Vector ALU Formats */
99 /* Vector Parameter Interpolation Format */
105 enum barrier_interaction
: uint8_t {
107 barrier_buffer
= 0x1,
109 barrier_atomic
= 0x4,
110 barrier_shared
= 0x8,
111 /* used for geometry shaders to ensure vertex data writes are before the
112 * GS_DONE s_sendmsg. */
113 barrier_gs_data
= 0x10,
114 /* used for geometry shaders to ensure s_sendmsg instructions are in-order. */
115 barrier_gs_sendmsg
= 0x20,
116 /* used by barriers. created by s_barrier */
117 barrier_barrier
= 0x40,
129 /* Note that v_rcp_f32, v_exp_f32, v_log_f32, v_sqrt_f32, v_rsq_f32 and
130 * v_mad_f32/v_madak_f32/v_madmk_f32/v_mac_f32 always flush denormals. */
131 fp_denorm_flush
= 0x0,
132 fp_denorm_keep
= 0x3,
136 /* matches encoding of the MODE register */
140 fp_round round16_64
:2;
142 unsigned denorm16_64
:2;
146 /* if false, optimizations which may remove infs/nan/-0.0 can be done */
147 bool preserve_signed_zero_inf_nan32
:1;
148 bool preserve_signed_zero_inf_nan16_64
:1;
149 /* if false, optimizations which may remove denormal flushing can be done */
150 bool must_flush_denorms32
:1;
151 bool must_flush_denorms16_64
:1;
152 bool care_about_round32
:1;
153 bool care_about_round16_64
:1;
155 /* Returns true if instructions using the mode "other" can safely use the
156 * current one instead. */
157 bool canReplace(float_mode other
) const noexcept
{
158 return val
== other
.val
&&
159 (preserve_signed_zero_inf_nan32
|| !other
.preserve_signed_zero_inf_nan32
) &&
160 (preserve_signed_zero_inf_nan16_64
|| !other
.preserve_signed_zero_inf_nan16_64
) &&
161 (must_flush_denorms32
|| !other
.must_flush_denorms32
) &&
162 (must_flush_denorms16_64
|| !other
.must_flush_denorms16_64
) &&
163 (care_about_round32
|| !other
.care_about_round32
) &&
164 (care_about_round16_64
|| !other
.care_about_round16_64
);
168 constexpr Format
asVOP3(Format format
) {
169 return (Format
) ((uint32_t) Format::VOP3
| (uint32_t) format
);
172 constexpr Format
asSDWA(Format format
) {
173 assert(format
== Format::VOP1
|| format
== Format::VOP2
|| format
== Format::VOPC
);
174 return (Format
) ((uint32_t) Format::SDWA
| (uint32_t) format
);
202 /* byte-sized register class */
209 /* these are used for WWM and spills to vgpr */
210 v1_linear
= v1
| (1 << 6),
211 v2_linear
= v2
| (1 << 6),
214 RegClass() = default;
215 constexpr RegClass(RC rc
)
217 constexpr RegClass(RegType type
, unsigned size
)
218 : rc((RC
) ((type
== RegType::vgpr
? 1 << 5 : 0) | size
)) {}
220 constexpr operator RC() const { return rc
; }
221 explicit operator bool() = delete;
223 constexpr RegType
type() const { return rc
<= RC::s16
? RegType::sgpr
: RegType::vgpr
; }
224 constexpr bool is_subdword() const { return rc
& (1 << 7); }
225 constexpr unsigned bytes() const { return ((unsigned) rc
& 0x1F) * (is_subdword() ? 1 : 4); }
226 //TODO: use size() less in favor of bytes()
227 constexpr unsigned size() const { return (bytes() + 3) >> 2; }
228 constexpr bool is_linear() const { return rc
<= RC::s16
|| rc
& (1 << 6); }
229 constexpr RegClass
as_linear() const { return RegClass((RC
) (rc
| (1 << 6))); }
230 constexpr RegClass
as_subdword() const { return RegClass((RC
) (rc
| 1 << 7)); }
236 /* transitional helper expressions */
237 static constexpr RegClass s1
{RegClass::s1
};
238 static constexpr RegClass s2
{RegClass::s2
};
239 static constexpr RegClass s3
{RegClass::s3
};
240 static constexpr RegClass s4
{RegClass::s4
};
241 static constexpr RegClass s8
{RegClass::s8
};
242 static constexpr RegClass s16
{RegClass::s16
};
243 static constexpr RegClass v1
{RegClass::v1
};
244 static constexpr RegClass v2
{RegClass::v2
};
245 static constexpr RegClass v3
{RegClass::v3
};
246 static constexpr RegClass v4
{RegClass::v4
};
247 static constexpr RegClass v5
{RegClass::v5
};
248 static constexpr RegClass v6
{RegClass::v6
};
249 static constexpr RegClass v7
{RegClass::v7
};
250 static constexpr RegClass v8
{RegClass::v8
};
251 static constexpr RegClass v1b
{RegClass::v1b
};
252 static constexpr RegClass v2b
{RegClass::v2b
};
253 static constexpr RegClass v3b
{RegClass::v3b
};
254 static constexpr RegClass v4b
{RegClass::v4b
};
255 static constexpr RegClass v6b
{RegClass::v6b
};
256 static constexpr RegClass v8b
{RegClass::v8b
};
260 * Each temporary virtual register has a
261 * register class (i.e. size and type)
265 Temp() noexcept
: id_(0), reg_class(0) {}
266 constexpr Temp(uint32_t id
, RegClass cls
) noexcept
267 : id_(id
), reg_class(uint8_t(cls
)) {}
269 constexpr uint32_t id() const noexcept
{ return id_
; }
270 constexpr RegClass
regClass() const noexcept
{ return (RegClass::RC
)reg_class
; }
272 constexpr unsigned bytes() const noexcept
{ return regClass().bytes(); }
273 constexpr unsigned size() const noexcept
{ return regClass().size(); }
274 constexpr RegType
type() const noexcept
{ return regClass().type(); }
275 constexpr bool is_linear() const noexcept
{ return regClass().is_linear(); }
277 constexpr bool operator <(Temp other
) const noexcept
{ return id() < other
.id(); }
278 constexpr bool operator==(Temp other
) const noexcept
{ return id() == other
.id(); }
279 constexpr bool operator!=(Temp other
) const noexcept
{ return id() != other
.id(); }
283 uint32_t reg_class
: 8;
288 * Represents the physical register for each
289 * Operand and Definition.
292 constexpr PhysReg() = default;
293 explicit constexpr PhysReg(unsigned r
) : reg_b(r
<< 2) {}
294 constexpr unsigned reg() const { return reg_b
>> 2; }
295 constexpr unsigned byte() const { return reg_b
& 0x3; }
296 constexpr operator unsigned() const { return reg(); }
297 constexpr bool operator==(PhysReg other
) const { return reg_b
== other
.reg_b
; }
298 constexpr bool operator!=(PhysReg other
) const { return reg_b
!= other
.reg_b
; }
299 constexpr bool operator <(PhysReg other
) const { return reg_b
< other
.reg_b
; }
304 /* helper expressions for special registers */
305 static constexpr PhysReg m0
{124};
306 static constexpr PhysReg vcc
{106};
307 static constexpr PhysReg vcc_hi
{107};
308 static constexpr PhysReg sgpr_null
{125}; /* GFX10+ */
309 static constexpr PhysReg exec
{126};
310 static constexpr PhysReg exec_lo
{126};
311 static constexpr PhysReg exec_hi
{127};
312 static constexpr PhysReg vccz
{251};
313 static constexpr PhysReg execz
{252};
314 static constexpr PhysReg scc
{253};
318 * Initially, each Operand refers to either
319 * a temporary virtual register
320 * or to a constant value
321 * Temporary registers get mapped to physical register during RA
322 * Constant values are inlined into the instruction sequence.
328 : reg_(PhysReg
{128}), isTemp_(false), isFixed_(true), isConstant_(false),
329 isKill_(false), isUndef_(true), isFirstKill_(false), is64BitConst_(false),
330 isLateKill_(false) {}
332 explicit Operand(Temp r
) noexcept
339 setFixed(PhysReg
{128});
342 explicit Operand(uint32_t v
, bool is64bit
= false) noexcept
346 is64BitConst_
= is64bit
;
348 setFixed(PhysReg
{128 + v
});
349 else if (v
>= 0xFFFFFFF0) /* [-16 .. -1] */
350 setFixed(PhysReg
{192 - v
});
351 else if (v
== 0x3f000000) /* 0.5 */
352 setFixed(PhysReg
{240});
353 else if (v
== 0xbf000000) /* -0.5 */
354 setFixed(PhysReg
{241});
355 else if (v
== 0x3f800000) /* 1.0 */
356 setFixed(PhysReg
{242});
357 else if (v
== 0xbf800000) /* -1.0 */
358 setFixed(PhysReg
{243});
359 else if (v
== 0x40000000) /* 2.0 */
360 setFixed(PhysReg
{244});
361 else if (v
== 0xc0000000) /* -2.0 */
362 setFixed(PhysReg
{245});
363 else if (v
== 0x40800000) /* 4.0 */
364 setFixed(PhysReg
{246});
365 else if (v
== 0xc0800000) /* -4.0 */
366 setFixed(PhysReg
{247});
367 else { /* Literal Constant */
368 assert(!is64bit
&& "attempt to create a 64-bit literal constant");
369 setFixed(PhysReg
{255});
372 explicit Operand(uint64_t v
) noexcept
375 is64BitConst_
= true;
377 data_
.i
= (uint32_t) v
;
378 setFixed(PhysReg
{128 + (uint32_t) v
});
379 } else if (v
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
380 data_
.i
= (uint32_t) v
;
381 setFixed(PhysReg
{192 - (uint32_t) v
});
382 } else if (v
== 0x3FE0000000000000) { /* 0.5 */
383 data_
.i
= 0x3f000000;
384 setFixed(PhysReg
{240});
385 } else if (v
== 0xBFE0000000000000) { /* -0.5 */
386 data_
.i
= 0xbf000000;
387 setFixed(PhysReg
{241});
388 } else if (v
== 0x3FF0000000000000) { /* 1.0 */
389 data_
.i
= 0x3f800000;
390 setFixed(PhysReg
{242});
391 } else if (v
== 0xBFF0000000000000) { /* -1.0 */
392 data_
.i
= 0xbf800000;
393 setFixed(PhysReg
{243});
394 } else if (v
== 0x4000000000000000) { /* 2.0 */
395 data_
.i
= 0x40000000;
396 setFixed(PhysReg
{244});
397 } else if (v
== 0xC000000000000000) { /* -2.0 */
398 data_
.i
= 0xc0000000;
399 setFixed(PhysReg
{245});
400 } else if (v
== 0x4010000000000000) { /* 4.0 */
401 data_
.i
= 0x40800000;
402 setFixed(PhysReg
{246});
403 } else if (v
== 0xC010000000000000) { /* -4.0 */
404 data_
.i
= 0xc0800000;
405 setFixed(PhysReg
{247});
406 } else { /* Literal Constant: we don't know if it is a long or double.*/
408 assert(false && "attempt to create a 64-bit literal constant");
411 explicit Operand(RegClass type
) noexcept
414 data_
.temp
= Temp(0, type
);
415 setFixed(PhysReg
{128});
417 explicit Operand(PhysReg reg
, RegClass type
) noexcept
419 data_
.temp
= Temp(0, type
);
423 constexpr bool isTemp() const noexcept
428 constexpr void setTemp(Temp t
) noexcept
{
429 assert(!isConstant_
);
434 constexpr Temp
getTemp() const noexcept
439 constexpr uint32_t tempId() const noexcept
441 return data_
.temp
.id();
444 constexpr bool hasRegClass() const noexcept
446 return isTemp() || isUndefined();
449 constexpr RegClass
regClass() const noexcept
451 return data_
.temp
.regClass();
454 constexpr unsigned bytes() const noexcept
457 return is64BitConst_
? 8 : 4; //TODO: sub-dword constants
459 return data_
.temp
.bytes();
462 constexpr unsigned size() const noexcept
465 return is64BitConst_
? 2 : 1;
467 return data_
.temp
.size();
470 constexpr bool isFixed() const noexcept
475 constexpr PhysReg
physReg() const noexcept
480 constexpr void setFixed(PhysReg reg
) noexcept
482 isFixed_
= reg
!= unsigned(-1);
486 constexpr bool isConstant() const noexcept
491 constexpr bool isLiteral() const noexcept
493 return isConstant() && reg_
== 255;
496 constexpr bool isUndefined() const noexcept
501 constexpr uint32_t constantValue() const noexcept
506 constexpr bool constantEquals(uint32_t cmp
) const noexcept
508 return isConstant() && constantValue() == cmp
;
511 constexpr uint64_t constantValue64(bool signext
=false) const noexcept
516 else if (reg_
<= 208)
517 return 0xFFFFFFFFFFFFFFFF - (reg_
- 193);
521 return 0x3FE0000000000000;
523 return 0xBFE0000000000000;
525 return 0x3FF0000000000000;
527 return 0xBFF0000000000000;
529 return 0x4000000000000000;
531 return 0xC000000000000000;
533 return 0x4010000000000000;
535 return 0xC010000000000000;
538 return (signext
&& (data_
.i
& 0x80000000u
) ? 0xffffffff00000000ull
: 0ull) | data_
.i
;
541 /* Indicates that the killed operand's live range intersects with the
542 * instruction's definitions. Unlike isKill() and isFirstKill(), this is
543 * not set by liveness analysis. */
544 constexpr void setLateKill(bool flag
) noexcept
549 constexpr bool isLateKill() const noexcept
554 constexpr void setKill(bool flag
) noexcept
561 constexpr bool isKill() const noexcept
563 return isKill_
|| isFirstKill();
566 constexpr void setFirstKill(bool flag
) noexcept
573 /* When there are multiple operands killing the same temporary,
574 * isFirstKill() is only returns true for the first one. */
575 constexpr bool isFirstKill() const noexcept
580 constexpr bool isKillBeforeDef() const noexcept
582 return isKill() && !isLateKill();
585 constexpr bool isFirstKillBeforeDef() const noexcept
587 return isFirstKill() && !isLateKill();
590 constexpr bool operator == (Operand other
) const noexcept
592 if (other
.size() != size())
594 if (isFixed() != other
.isFixed() || isKillBeforeDef() != other
.isKillBeforeDef())
596 if (isFixed() && other
.isFixed() && physReg() != other
.physReg())
599 return other
.isLiteral() && other
.constantValue() == constantValue();
600 else if (isConstant())
601 return other
.isConstant() && other
.physReg() == physReg();
602 else if (isUndefined())
603 return other
.isUndefined() && other
.regClass() == regClass();
605 return other
.isTemp() && other
.getTemp() == getTemp();
611 Temp temp
= Temp(0, s1
);
618 uint8_t isConstant_
:1;
621 uint8_t isFirstKill_
:1;
622 uint8_t is64BitConst_
:1;
623 uint8_t isLateKill_
:1;
625 /* can't initialize bit-fields in c++11, so work around using a union */
626 uint8_t control_
= 0;
632 * Definitions are the results of Instructions
633 * and refer to temporary virtual registers
634 * which are later mapped to physical registers
636 class Definition final
639 constexpr Definition() : temp(Temp(0, s1
)), reg_(0), isFixed_(0), hasHint_(0), isKill_(0) {}
640 Definition(uint32_t index
, RegClass type
) noexcept
641 : temp(index
, type
) {}
642 explicit Definition(Temp tmp
) noexcept
644 Definition(PhysReg reg
, RegClass type
) noexcept
645 : temp(Temp(0, type
))
649 Definition(uint32_t tmpId
, PhysReg reg
, RegClass type
) noexcept
650 : temp(Temp(tmpId
, type
))
655 constexpr bool isTemp() const noexcept
660 constexpr Temp
getTemp() const noexcept
665 constexpr uint32_t tempId() const noexcept
670 constexpr void setTemp(Temp t
) noexcept
{
674 constexpr RegClass
regClass() const noexcept
676 return temp
.regClass();
679 constexpr unsigned bytes() const noexcept
684 constexpr unsigned size() const noexcept
689 constexpr bool isFixed() const noexcept
694 constexpr PhysReg
physReg() const noexcept
699 constexpr void setFixed(PhysReg reg
) noexcept
705 constexpr void setHint(PhysReg reg
) noexcept
711 constexpr bool hasHint() const noexcept
716 constexpr void setKill(bool flag
) noexcept
721 constexpr bool isKill() const noexcept
727 Temp temp
= Temp(0, s1
);
735 /* can't initialize bit-fields in c++11, so work around using a union */
736 uint8_t control_
= 0;
747 aco::span
<Operand
> operands
;
748 aco::span
<Definition
> definitions
;
750 constexpr bool isVALU() const noexcept
752 return ((uint16_t) format
& (uint16_t) Format::VOP1
) == (uint16_t) Format::VOP1
753 || ((uint16_t) format
& (uint16_t) Format::VOP2
) == (uint16_t) Format::VOP2
754 || ((uint16_t) format
& (uint16_t) Format::VOPC
) == (uint16_t) Format::VOPC
755 || ((uint16_t) format
& (uint16_t) Format::VOP3A
) == (uint16_t) Format::VOP3A
756 || ((uint16_t) format
& (uint16_t) Format::VOP3B
) == (uint16_t) Format::VOP3B
757 || ((uint16_t) format
& (uint16_t) Format::VOP3P
) == (uint16_t) Format::VOP3P
;
760 constexpr bool isSALU() const noexcept
762 return format
== Format::SOP1
||
763 format
== Format::SOP2
||
764 format
== Format::SOPC
||
765 format
== Format::SOPK
||
766 format
== Format::SOPP
;
769 constexpr bool isVMEM() const noexcept
771 return format
== Format::MTBUF
||
772 format
== Format::MUBUF
||
773 format
== Format::MIMG
;
776 constexpr bool isDPP() const noexcept
778 return (uint16_t) format
& (uint16_t) Format::DPP
;
781 constexpr bool isVOP3() const noexcept
783 return ((uint16_t) format
& (uint16_t) Format::VOP3A
) ||
784 ((uint16_t) format
& (uint16_t) Format::VOP3B
) ||
785 format
== Format::VOP3P
;
788 constexpr bool isSDWA() const noexcept
790 return (uint16_t) format
& (uint16_t) Format::SDWA
;
793 constexpr bool isFlatOrGlobal() const noexcept
795 return format
== Format::FLAT
|| format
== Format::GLOBAL
;
798 constexpr bool usesModifiers() const noexcept
;
800 constexpr bool reads_exec() const noexcept
802 for (const Operand
& op
: operands
) {
803 if (op
.isFixed() && op
.physReg() == exec
)
809 static_assert(sizeof(Instruction
) == 16);
811 struct SOPK_instruction
: public Instruction
{
815 static_assert(sizeof(SOPK_instruction
) == sizeof(Instruction
) + 4);
817 struct SOPP_instruction
: public Instruction
{
821 static_assert(sizeof(SOPP_instruction
) == sizeof(Instruction
) + 8);
823 struct SOPC_instruction
: public Instruction
{
825 static_assert(sizeof(SOPC_instruction
) == sizeof(Instruction
) + 0);
827 struct SOP1_instruction
: public Instruction
{
829 static_assert(sizeof(SOP1_instruction
) == sizeof(Instruction
) + 0);
831 struct SOP2_instruction
: public Instruction
{
833 static_assert(sizeof(SOP2_instruction
) == sizeof(Instruction
) + 0);
836 * Scalar Memory Format:
837 * For s_(buffer_)load_dword*:
838 * Operand(0): SBASE - SGPR-pair which provides base address
839 * Operand(1): Offset - immediate (un)signed offset or SGPR
840 * Operand(2) / Definition(0): SDATA - SGPR for read / write result
841 * Operand(n-1): SOffset - SGPR offset (Vega only)
843 * Having no operands is also valid for instructions such as s_dcache_inv.
846 struct SMEM_instruction
: public Instruction
{
847 barrier_interaction barrier
;
848 bool glc
: 1; /* VI+: globally coherent */
849 bool dlc
: 1; /* NAVI: device level coherent */
850 bool nv
: 1; /* VEGA only: Non-volatile */
851 bool can_reorder
: 1;
852 bool disable_wqm
: 1;
853 uint32_t padding
: 19;
855 static_assert(sizeof(SMEM_instruction
) == sizeof(Instruction
) + 4);
857 struct VOP1_instruction
: public Instruction
{
859 static_assert(sizeof(VOP1_instruction
) == sizeof(Instruction
) + 0);
861 struct VOP2_instruction
: public Instruction
{
863 static_assert(sizeof(VOP2_instruction
) == sizeof(Instruction
) + 0);
865 struct VOPC_instruction
: public Instruction
{
867 static_assert(sizeof(VOPC_instruction
) == sizeof(Instruction
) + 0);
869 struct VOP3A_instruction
: public Instruction
{
875 uint32_t padding
: 9;
877 static_assert(sizeof(VOP3A_instruction
) == sizeof(Instruction
) + 8);
880 * Data Parallel Primitives Format:
881 * This format can be used for VOP1, VOP2 or VOPC instructions.
882 * The swizzle applies to the src0 operand.
885 struct DPP_instruction
: public Instruction
{
889 uint8_t row_mask
: 4;
890 uint8_t bank_mask
: 4;
892 uint32_t padding
: 7;
894 static_assert(sizeof(DPP_instruction
) == sizeof(Instruction
) + 8);
896 enum sdwa_sel
: uint8_t {
900 sdwa_asuint
= 0x7 | 0x10,
908 /* specific values */
913 sdwa_uword0
= sdwa_isword
| 0,
914 sdwa_uword1
= sdwa_isword
| 1,
917 sdwa_sbyte0
= sdwa_ubyte0
| sdwa_sext
,
918 sdwa_sbyte1
= sdwa_ubyte1
| sdwa_sext
,
919 sdwa_sbyte2
= sdwa_ubyte2
| sdwa_sext
,
920 sdwa_sbyte3
= sdwa_ubyte3
| sdwa_sext
,
921 sdwa_sword0
= sdwa_uword0
| sdwa_sext
,
922 sdwa_sword1
= sdwa_uword1
| sdwa_sext
,
923 sdwa_sdword
= sdwa_udword
| sdwa_sext
,
925 /* register-allocated */
926 sdwa_ubyte
= 1 | sdwa_isra
,
927 sdwa_uword
= 2 | sdwa_isra
,
928 sdwa_sbyte
= sdwa_ubyte
| sdwa_sext
,
929 sdwa_sword
= sdwa_uword
| sdwa_sext
,
933 * Sub-Dword Addressing Format:
934 * This format can be used for VOP1, VOP2 or VOPC instructions.
936 * omod and SGPR/constant operands are only available on GFX9+. For VOPC,
937 * the definition doesn't have to be VCC on GFX9+.
940 struct SDWA_instruction
: public Instruction
{
941 /* these destination modifiers aren't available with VOPC except for
947 bool dst_preserve
: 1;
949 uint8_t omod
: 2; /* GFX9+ */
950 uint32_t padding
: 4;
952 static_assert(sizeof(SDWA_instruction
) == sizeof(Instruction
) + 8);
954 struct Interp_instruction
: public Instruction
{
959 static_assert(sizeof(Interp_instruction
) == sizeof(Instruction
) + 4);
962 * Local and Global Data Sharing instructions
963 * Operand(0): ADDR - VGPR which supplies the address.
964 * Operand(1): DATA0 - First data VGPR.
965 * Operand(2): DATA1 - Second data VGPR.
966 * Operand(n-1): M0 - LDS size.
967 * Definition(0): VDST - Destination VGPR when results returned to VGPRs.
970 struct DS_instruction
: public Instruction
{
975 static_assert(sizeof(DS_instruction
) == sizeof(Instruction
) + 4);
978 * Vector Memory Untyped-buffer Instructions
979 * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant)
980 * Operand(1): VADDR - Address source. Can carry an index and/or offset
981 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
982 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
985 struct MUBUF_instruction
: public Instruction
{
986 uint16_t offset
: 12; /* Unsigned byte offset - 12 bit */
987 bool offen
: 1; /* Supply an offset from VGPR (VADDR) */
988 bool idxen
: 1; /* Supply an index from VGPR (VADDR) */
989 bool addr64
: 1; /* SI, CIK: Address size is 64-bit */
990 bool glc
: 1; /* globally coherent */
991 bool dlc
: 1; /* NAVI: device level coherent */
992 bool slc
: 1; /* system level coherent */
993 bool tfe
: 1; /* texture fail enable */
994 bool lds
: 1; /* Return read-data to LDS instead of VGPRs */
995 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
996 bool can_reorder
: 1;
998 barrier_interaction barrier
;
1000 static_assert(sizeof(MUBUF_instruction
) == sizeof(Instruction
) + 4);
1003 * Vector Memory Typed-buffer Instructions
1004 * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant)
1005 * Operand(1): VADDR - Address source. Can carry an index and/or offset
1006 * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant)
1007 * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data
1010 struct MTBUF_instruction
: public Instruction
{
1011 uint16_t offset
; /* Unsigned byte offset - 12 bit */
1012 barrier_interaction barrier
;
1013 uint8_t dfmt
: 4; /* Data Format of data in memory buffer */
1014 uint8_t nfmt
: 3; /* Numeric format of data in memory */
1015 bool offen
: 1; /* Supply an offset from VGPR (VADDR) */
1016 bool idxen
: 1; /* Supply an index from VGPR (VADDR) */
1017 bool glc
: 1; /* globally coherent */
1018 bool dlc
: 1; /* NAVI: device level coherent */
1019 bool slc
: 1; /* system level coherent */
1020 bool tfe
: 1; /* texture fail enable */
1021 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
1022 bool can_reorder
: 1;
1023 uint32_t padding
: 25;
1025 static_assert(sizeof(MTBUF_instruction
) == sizeof(Instruction
) + 8);
1028 * Vector Memory Image Instructions
1029 * Operand(0) SRSRC - Scalar GPR that specifies the resource constant.
1030 * Operand(1): SSAMP - Scalar GPR that specifies sampler constant.
1031 * or VDATA - Vector GPR for write data.
1032 * Operand(2): VADDR - Address source. Can carry an offset or an index.
1033 * Definition(0): VDATA - Vector GPR for read result.
1036 struct MIMG_instruction
: public Instruction
{
1037 uint8_t dmask
; /* Data VGPR enable mask */
1038 uint8_t dim
: 3; /* NAVI: dimensionality */
1039 bool unrm
: 1; /* Force address to be un-normalized */
1040 bool dlc
: 1; /* NAVI: device level coherent */
1041 bool glc
: 1; /* globally coherent */
1042 bool slc
: 1; /* system level coherent */
1043 bool tfe
: 1; /* texture fail enable */
1044 bool da
: 1; /* declare an array */
1045 bool lwe
: 1; /* Force data to be un-normalized */
1046 bool r128
: 1; /* NAVI: Texture resource size */
1047 bool a16
: 1; /* VEGA, NAVI: Address components are 16-bits */
1048 bool d16
: 1; /* Convert 32-bit data to 16-bit data */
1049 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
1050 bool can_reorder
: 1;
1051 uint8_t padding
: 1;
1052 barrier_interaction barrier
;
1054 static_assert(sizeof(MIMG_instruction
) == sizeof(Instruction
) + 4);
1057 * Flat/Scratch/Global Instructions
1060 * Operand(2) / Definition(0): DATA/VDST
1063 struct FLAT_instruction
: public Instruction
{
1064 uint16_t offset
; /* Vega/Navi only */
1065 bool slc
: 1; /* system level coherent */
1066 bool glc
: 1; /* globally coherent */
1067 bool dlc
: 1; /* NAVI: device level coherent */
1070 bool disable_wqm
: 1; /* Require an exec mask without helper invocations */
1071 bool can_reorder
: 1;
1072 uint8_t padding
: 1;
1073 barrier_interaction barrier
;
1075 static_assert(sizeof(FLAT_instruction
) == sizeof(Instruction
) + 4);
1077 struct Export_instruction
: public Instruction
{
1078 uint8_t enabled_mask
;
1080 bool compressed
: 1;
1082 bool valid_mask
: 1;
1083 uint32_t padding
: 13;
1085 static_assert(sizeof(Export_instruction
) == sizeof(Instruction
) + 4);
1087 struct Pseudo_instruction
: public Instruction
{
1088 PhysReg scratch_sgpr
; /* might not be valid if it's not needed */
1092 static_assert(sizeof(Pseudo_instruction
) == sizeof(Instruction
) + 4);
1094 struct Pseudo_branch_instruction
: public Instruction
{
1095 /* target[0] is the block index of the branch target.
1096 * For conditional branches, target[1] contains the fall-through alternative.
1097 * A value of 0 means the target has not been initialized (BB0 cannot be a branch target).
1101 static_assert(sizeof(Pseudo_branch_instruction
) == sizeof(Instruction
) + 8);
1103 struct Pseudo_barrier_instruction
: public Instruction
{
1105 static_assert(sizeof(Pseudo_barrier_instruction
) == sizeof(Instruction
) + 0);
1107 enum ReduceOp
: uint16_t {
1121 gfx10_wave64_bpermute
1125 * Subgroup Reduction Instructions, everything except for the data to be
1126 * reduced and the result as inserted by setup_reduce_temp().
1127 * Operand(0): data to be reduced
1128 * Operand(1): reduce temporary
1129 * Operand(2): vector temporary
1130 * Definition(0): result
1131 * Definition(1): scalar temporary
1132 * Definition(2): scalar identity temporary (not used to store identity on GFX10)
1133 * Definition(3): scc clobber
1134 * Definition(4): vcc clobber
1137 struct Pseudo_reduction_instruction
: public Instruction
{
1139 uint16_t cluster_size
; // must be 0 for scans
1141 static_assert(sizeof(Pseudo_reduction_instruction
) == sizeof(Instruction
) + 4);
1143 struct instr_deleter_functor
{
1144 void operator()(void* p
) {
1149 template<typename T
>
1150 using aco_ptr
= std::unique_ptr
<T
, instr_deleter_functor
>;
1152 template<typename T
>
1153 T
* create_instruction(aco_opcode opcode
, Format format
, uint32_t num_operands
, uint32_t num_definitions
)
1155 std::size_t size
= sizeof(T
) + num_operands
* sizeof(Operand
) + num_definitions
* sizeof(Definition
);
1156 char *data
= (char*) calloc(1, size
);
1157 T
* inst
= (T
*) data
;
1159 inst
->opcode
= opcode
;
1160 inst
->format
= format
;
1162 uint16_t operands_offset
= data
+ sizeof(T
) - (char*)&inst
->operands
;
1163 inst
->operands
= aco::span
<Operand
>(operands_offset
, num_operands
);
1164 uint16_t definitions_offset
= (char*)inst
->operands
.end() - (char*)&inst
->definitions
;
1165 inst
->definitions
= aco::span
<Definition
>(definitions_offset
, num_definitions
);
1170 constexpr bool Instruction::usesModifiers() const noexcept
1172 if (isDPP() || isSDWA())
1176 const VOP3A_instruction
*vop3
= static_cast<const VOP3A_instruction
*>(this);
1177 for (unsigned i
= 0; i
< operands
.size(); i
++) {
1178 if (vop3
->abs
[i
] || vop3
->neg
[i
])
1181 return vop3
->opsel
|| vop3
->clamp
|| vop3
->omod
;
1184 constexpr bool is_phi(Instruction
* instr
)
1186 return instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
;
1189 static inline bool is_phi(aco_ptr
<Instruction
>& instr
)
1191 return is_phi(instr
.get());
1194 barrier_interaction
get_barrier_interaction(Instruction
* instr
);
1196 bool is_dead(const std::vector
<uint16_t>& uses
, Instruction
*instr
);
1199 /* uniform indicates that leaving this block,
1200 * all actives lanes stay active */
1201 block_kind_uniform
= 1 << 0,
1202 block_kind_top_level
= 1 << 1,
1203 block_kind_loop_preheader
= 1 << 2,
1204 block_kind_loop_header
= 1 << 3,
1205 block_kind_loop_exit
= 1 << 4,
1206 block_kind_continue
= 1 << 5,
1207 block_kind_break
= 1 << 6,
1208 block_kind_continue_or_break
= 1 << 7,
1209 block_kind_discard
= 1 << 8,
1210 block_kind_branch
= 1 << 9,
1211 block_kind_merge
= 1 << 10,
1212 block_kind_invert
= 1 << 11,
1213 block_kind_uses_discard_if
= 1 << 12,
1214 block_kind_needs_lowering
= 1 << 13,
1215 block_kind_uses_demote
= 1 << 14,
1216 block_kind_export_end
= 1 << 15,
1220 struct RegisterDemand
{
1221 constexpr RegisterDemand() = default;
1222 constexpr RegisterDemand(const int16_t v
, const int16_t s
) noexcept
1223 : vgpr
{v
}, sgpr
{s
} {}
1227 constexpr friend bool operator==(const RegisterDemand a
, const RegisterDemand b
) noexcept
{
1228 return a
.vgpr
== b
.vgpr
&& a
.sgpr
== b
.sgpr
;
1231 constexpr bool exceeds(const RegisterDemand other
) const noexcept
{
1232 return vgpr
> other
.vgpr
|| sgpr
> other
.sgpr
;
1235 constexpr RegisterDemand
operator+(const Temp t
) const noexcept
{
1236 if (t
.type() == RegType::sgpr
)
1237 return RegisterDemand( vgpr
, sgpr
+ t
.size() );
1239 return RegisterDemand( vgpr
+ t
.size(), sgpr
);
1242 constexpr RegisterDemand
operator+(const RegisterDemand other
) const noexcept
{
1243 return RegisterDemand(vgpr
+ other
.vgpr
, sgpr
+ other
.sgpr
);
1246 constexpr RegisterDemand
operator-(const RegisterDemand other
) const noexcept
{
1247 return RegisterDemand(vgpr
- other
.vgpr
, sgpr
- other
.sgpr
);
1250 constexpr RegisterDemand
& operator+=(const RegisterDemand other
) noexcept
{
1256 constexpr RegisterDemand
& operator-=(const RegisterDemand other
) noexcept
{
1262 constexpr RegisterDemand
& operator+=(const Temp t
) noexcept
{
1263 if (t
.type() == RegType::sgpr
)
1270 constexpr RegisterDemand
& operator-=(const Temp t
) noexcept
{
1271 if (t
.type() == RegType::sgpr
)
1278 constexpr void update(const RegisterDemand other
) noexcept
{
1279 vgpr
= std::max(vgpr
, other
.vgpr
);
1280 sgpr
= std::max(sgpr
, other
.sgpr
);
1289 unsigned offset
= 0;
1290 std::vector
<aco_ptr
<Instruction
>> instructions
;
1291 std::vector
<unsigned> logical_preds
;
1292 std::vector
<unsigned> linear_preds
;
1293 std::vector
<unsigned> logical_succs
;
1294 std::vector
<unsigned> linear_succs
;
1295 RegisterDemand register_demand
= RegisterDemand();
1296 uint16_t loop_nest_depth
= 0;
1298 int logical_idom
= -1;
1299 int linear_idom
= -1;
1300 Temp live_out_exec
= Temp();
1302 /* this information is needed for predecessors to blocks with phis when
1303 * moving out of ssa */
1304 bool scc_live_out
= false;
1305 PhysReg scratch_sgpr
= PhysReg(); /* only needs to be valid if scc_live_out != false */
1307 Block(unsigned idx
) : index(idx
) {}
1308 Block() : index(0) {}
1311 using Stage
= uint16_t;
1313 /* software stages */
1314 static constexpr Stage sw_vs
= 1 << 0;
1315 static constexpr Stage sw_gs
= 1 << 1;
1316 static constexpr Stage sw_tcs
= 1 << 2;
1317 static constexpr Stage sw_tes
= 1 << 3;
1318 static constexpr Stage sw_fs
= 1 << 4;
1319 static constexpr Stage sw_cs
= 1 << 5;
1320 static constexpr Stage sw_gs_copy
= 1 << 6;
1321 static constexpr Stage sw_mask
= 0x7f;
1323 /* hardware stages (can't be OR'd, just a mask for convenience when testing multiple) */
1324 static constexpr Stage hw_vs
= 1 << 7;
1325 static constexpr Stage hw_es
= 1 << 8; /* Export shader: pre-GS (VS or TES) on GFX6-8. Combined into GS on GFX9 (and GFX10/legacy). */
1326 static constexpr Stage hw_gs
= 1 << 9; /* Geometry shader on GFX10/legacy and GFX6-9. */
1327 static constexpr Stage hw_ngg_gs
= 1 << 10; /* Geometry shader on GFX10/NGG. */
1328 static constexpr Stage hw_ls
= 1 << 11; /* Local shader: pre-TCS (VS) on GFX6-8. Combined into HS on GFX9 (and GFX10/legacy). */
1329 static constexpr Stage hw_hs
= 1 << 12; /* Hull shader: TCS on GFX6-8. Merged VS and TCS on GFX9-10. */
1330 static constexpr Stage hw_fs
= 1 << 13;
1331 static constexpr Stage hw_cs
= 1 << 14;
1332 static constexpr Stage hw_mask
= 0xff << 7;
1334 /* possible settings of Program::stage */
1335 static constexpr Stage vertex_vs
= sw_vs
| hw_vs
;
1336 static constexpr Stage fragment_fs
= sw_fs
| hw_fs
;
1337 static constexpr Stage compute_cs
= sw_cs
| hw_cs
;
1338 static constexpr Stage tess_eval_vs
= sw_tes
| hw_vs
;
1339 static constexpr Stage gs_copy_vs
= sw_gs_copy
| hw_vs
;
1341 static constexpr Stage ngg_vertex_gs
= sw_vs
| hw_ngg_gs
;
1342 static constexpr Stage ngg_vertex_geometry_gs
= sw_vs
| sw_gs
| hw_ngg_gs
;
1343 static constexpr Stage ngg_tess_eval_gs
= sw_tes
| hw_ngg_gs
;
1344 static constexpr Stage ngg_tess_eval_geometry_gs
= sw_tes
| sw_gs
| hw_ngg_gs
;
1345 /* GFX9 (and GFX10 if NGG isn't used) */
1346 static constexpr Stage vertex_geometry_gs
= sw_vs
| sw_gs
| hw_gs
;
1347 static constexpr Stage vertex_tess_control_hs
= sw_vs
| sw_tcs
| hw_hs
;
1348 static constexpr Stage tess_eval_geometry_gs
= sw_tes
| sw_gs
| hw_gs
;
1350 static constexpr Stage vertex_ls
= sw_vs
| hw_ls
; /* vertex before tesselation control */
1351 static constexpr Stage vertex_es
= sw_vs
| hw_es
; /* vertex before geometry */
1352 static constexpr Stage tess_control_hs
= sw_tcs
| hw_hs
;
1353 static constexpr Stage tess_eval_es
= sw_tes
| hw_es
; /* tesselation evaluation before geometry */
1354 static constexpr Stage geometry_gs
= sw_gs
| hw_gs
;
1358 statistic_instructions
,
1362 statistic_vmem_clauses
,
1363 statistic_smem_clauses
,
1364 statistic_vmem_score
,
1365 statistic_smem_score
,
1366 statistic_sgpr_presched
,
1367 statistic_vgpr_presched
,
1371 class Program final
{
1373 float_mode next_fp_mode
;
1374 std::vector
<Block
> blocks
;
1375 RegisterDemand max_reg_demand
= RegisterDemand();
1376 uint16_t num_waves
= 0;
1377 uint16_t max_waves
= 0; /* maximum number of waves, regardless of register usage */
1378 ac_shader_config
* config
;
1379 struct radv_shader_info
*info
;
1380 enum chip_class chip_class
;
1381 enum radeon_family family
;
1384 Stage stage
; /* Stage */
1385 bool needs_exact
= false; /* there exists an instruction with disable_wqm = true */
1386 bool needs_wqm
= false; /* there exists a p_wqm instruction */
1387 bool wb_smem_l1_on_end
= false;
1389 std::vector
<uint8_t> constant_data
;
1390 Temp private_segment_buffer
;
1391 Temp scratch_offset
;
1393 uint16_t min_waves
= 0;
1394 uint16_t lds_alloc_granule
;
1395 uint32_t lds_limit
; /* in bytes */
1396 bool has_16bank_lds
;
1397 uint16_t vgpr_limit
;
1398 uint16_t sgpr_limit
;
1399 uint16_t physical_sgprs
;
1400 uint16_t sgpr_alloc_granule
; /* minus one. must be power of two */
1401 uint16_t vgpr_alloc_granule
; /* minus one. must be power of two */
1402 unsigned workgroup_size
; /* if known; otherwise UINT_MAX */
1404 bool xnack_enabled
= false;
1406 bool needs_vcc
= false;
1407 bool needs_flat_scr
= false;
1409 bool collect_statistics
= false;
1410 uint32_t statistics
[num_statistics
];
1412 uint32_t allocateId()
1414 assert(allocationID
<= 16777215);
1415 return allocationID
++;
1418 uint32_t peekAllocationId()
1420 return allocationID
;
1423 void setAllocationId(uint32_t id
)
1428 Block
* create_and_insert_block() {
1429 blocks
.emplace_back(blocks
.size());
1430 blocks
.back().fp_mode
= next_fp_mode
;
1431 return &blocks
.back();
1434 Block
* insert_block(Block
&& block
) {
1435 block
.index
= blocks
.size();
1436 block
.fp_mode
= next_fp_mode
;
1437 blocks
.emplace_back(std::move(block
));
1438 return &blocks
.back();
1442 uint32_t allocationID
= 1;
1446 /* live temps out per block */
1447 std::vector
<std::set
<Temp
>> live_out
;
1448 /* register demand (sgpr/vgpr) per instruction per block */
1449 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
1452 void select_program(Program
*program
,
1453 unsigned shader_count
,
1454 struct nir_shader
*const *shaders
,
1455 ac_shader_config
* config
,
1456 struct radv_shader_args
*args
);
1457 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
1458 ac_shader_config
* config
,
1459 struct radv_shader_args
*args
);
1461 void lower_wqm(Program
* program
, live
& live_vars
,
1462 const struct radv_nir_compiler_options
*options
);
1463 void lower_bool_phis(Program
* program
);
1464 void calc_min_waves(Program
* program
);
1465 void update_vgpr_sgpr_demand(Program
* program
, const RegisterDemand new_demand
);
1466 live
live_var_analysis(Program
* program
, const struct radv_nir_compiler_options
*options
);
1467 std::vector
<uint16_t> dead_code_analysis(Program
*program
);
1468 void dominator_tree(Program
* program
);
1469 void insert_exec_mask(Program
*program
);
1470 void value_numbering(Program
* program
);
1471 void optimize(Program
* program
);
1472 void setup_reduce_temp(Program
* program
);
1473 void lower_to_cssa(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
);
1474 void register_allocation(Program
*program
, std::vector
<std::set
<Temp
>>& live_out_per_block
);
1475 void ssa_elimination(Program
* program
);
1476 void lower_to_hw_instr(Program
* program
);
1477 void schedule_program(Program
* program
, live
& live_vars
);
1478 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
);
1479 void insert_wait_states(Program
* program
);
1480 void insert_NOPs(Program
* program
);
1481 unsigned emit_program(Program
* program
, std::vector
<uint32_t>& code
);
1482 void print_asm(Program
*program
, std::vector
<uint32_t>& binary
,
1483 unsigned exec_size
, std::ostream
& out
);
1484 void validate(Program
* program
, FILE *output
);
1485 bool validate_ra(Program
* program
, const struct radv_nir_compiler_options
*options
, FILE *output
);
1487 void perfwarn(bool cond
, const char *msg
, Instruction
*instr
=NULL
);
1489 #define perfwarn(program, cond, msg, ...) do {} while(0)
1492 void collect_presched_stats(Program
*program
);
1493 void collect_preasm_stats(Program
*program
);
1494 void collect_postasm_stats(Program
*program
, const std::vector
<uint32_t>& code
);
1496 void aco_print_instr(Instruction
*instr
, FILE *output
);
1497 void aco_print_program(Program
*program
, FILE *output
);
1499 /* utilities for dealing with register demand */
1500 RegisterDemand
get_live_changes(aco_ptr
<Instruction
>& instr
);
1501 RegisterDemand
get_temp_registers(aco_ptr
<Instruction
>& instr
);
1502 RegisterDemand
get_demand_before(RegisterDemand demand
, aco_ptr
<Instruction
>& instr
, aco_ptr
<Instruction
>& instr_before
);
1504 /* number of sgprs that need to be allocated but might notbe addressable as s0-s105 */
1505 uint16_t get_extra_sgprs(Program
*program
);
1507 /* get number of sgprs/vgprs allocated required to address a number of sgprs/vgprs */
1508 uint16_t get_sgpr_alloc(Program
*program
, uint16_t addressable_sgprs
);
1509 uint16_t get_vgpr_alloc(Program
*program
, uint16_t addressable_vgprs
);
1511 /* return number of addressable sgprs/vgprs for max_waves */
1512 uint16_t get_addr_sgpr_from_waves(Program
*program
, uint16_t max_waves
);
1513 uint16_t get_addr_vgpr_from_waves(Program
*program
, uint16_t max_waves
);
1516 const int16_t opcode_gfx7
[static_cast<int>(aco_opcode::num_opcodes
)];
1517 const int16_t opcode_gfx9
[static_cast<int>(aco_opcode::num_opcodes
)];
1518 const int16_t opcode_gfx10
[static_cast<int>(aco_opcode::num_opcodes
)];
1519 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> can_use_input_modifiers
;
1520 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> can_use_output_modifiers
;
1521 const std::bitset
<static_cast<int>(aco_opcode::num_opcodes
)> is_atomic
;
1522 const char *name
[static_cast<int>(aco_opcode::num_opcodes
)];
1523 const aco::Format format
[static_cast<int>(aco_opcode::num_opcodes
)];
1526 extern const Info instr_info
;
1530 #endif /* ACO_IR_H */