2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 void perfwarn(Program
*program
, bool cond
, const char *msg
, Instruction
*instr
)
43 FILE *memf
= open_memstream(&out
, &outsize
);
45 fprintf(memf
, "%s: ", msg
);
46 aco_print_instr(instr
, memf
);
49 aco_perfwarn(program
, out
);
52 if (debug_flags
& DEBUG_PERFWARN
)
59 * The optimizer works in 4 phases:
60 * (1) The first pass collects information for each ssa-def,
61 * propagates reg->reg operands of the same type, inline constants
62 * and neg/abs input modifiers.
63 * (2) The second pass combines instructions like mad, omod, clamp and
64 * propagates sgpr's on VALU instructions.
65 * This pass depends on information collected in the first pass.
66 * (3) The third pass goes backwards, and selects instructions,
67 * i.e. decides if a mad instruction is profitable and eliminates dead code.
68 * (4) The fourth pass cleans up the sequence: literals get applied and dead
69 * instructions are removed from the sequence.
74 aco_ptr
<Instruction
> add_instr
;
79 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
80 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
85 label_constant_32bit
= 1 << 1,
86 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
87 * 32-bit operations but this shouldn't cause any issues because we don't
88 * look through any conversions */
93 label_literal
= 1 << 6,
97 label_omod5
= 1 << 10,
98 label_omod_success
= 1 << 11,
99 label_clamp
= 1 << 12,
100 label_clamp_success
= 1 << 13,
101 label_undefined
= 1 << 14,
104 label_add_sub
= 1 << 17,
105 label_bitwise
= 1 << 18,
106 label_minmax
= 1 << 19,
107 label_vopc
= 1 << 20,
108 label_uniform_bool
= 1 << 21,
109 label_constant_64bit
= 1 << 22,
110 label_uniform_bitwise
= 1 << 23,
111 label_scc_invert
= 1 << 24,
112 label_vcc_hint
= 1 << 25,
113 label_scc_needed
= 1 << 26,
115 label_constant_16bit
= 1 << 29,
118 static constexpr uint64_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
119 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_vopc
;
120 static constexpr uint64_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
121 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
122 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
;
132 ssa_info() : label(0) {}
134 void add_label(Label new_label
)
136 /* Since all labels which use "instr" use it for the same thing
137 * (indicating the defining instruction), there is no need to clear
138 * any other instr labels. */
139 if (new_label
& instr_labels
)
140 label
&= ~(temp_labels
| val_labels
); /* instr, temp and val alias */
142 if (new_label
& temp_labels
) {
143 label
&= ~temp_labels
;
144 label
&= ~(instr_labels
| val_labels
); /* instr, temp and val alias */
147 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
148 if (new_label
& const_labels
) {
149 label
&= ~val_labels
| const_labels
;
150 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
151 } else if (new_label
& val_labels
) {
152 label
&= ~val_labels
;
153 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
159 void set_vec(Instruction
* vec
)
161 add_label(label_vec
);
167 return label
& label_vec
;
170 void set_constant(chip_class chip
, uint64_t constant
)
172 Operand
op16((uint16_t)constant
);
173 Operand
op32((uint32_t)constant
);
174 add_label(label_literal
);
177 if (chip
>= GFX8
&& !op16
.isLiteral())
178 add_label(label_constant_16bit
);
180 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
181 add_label(label_constant_32bit
);
183 if (constant
<= 64) {
184 add_label(label_constant_64bit
);
185 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
186 add_label(label_constant_64bit
);
187 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
188 add_label(label_constant_64bit
);
189 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
190 add_label(label_constant_64bit
);
191 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
192 add_label(label_constant_64bit
);
193 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
194 add_label(label_constant_64bit
);
195 } else if (constant
== 0x4000000000000000) { /* 2.0 */
196 add_label(label_constant_64bit
);
197 } else if (constant
== 0xC000000000000000) { /* -2.0 */
198 add_label(label_constant_64bit
);
199 } else if (constant
== 0x4010000000000000) { /* 4.0 */
200 add_label(label_constant_64bit
);
201 } else if (constant
== 0xC010000000000000) { /* -4.0 */
202 add_label(label_constant_64bit
);
205 if (label
& label_constant_64bit
) {
206 val
= Operand(constant
).constantValue();
208 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
212 bool is_constant(unsigned bits
)
216 return label
& label_literal
;
218 return label
& label_constant_16bit
;
220 return label
& label_constant_32bit
;
222 return label
& label_constant_64bit
;
227 bool is_literal(unsigned bits
)
229 bool is_lit
= label
& label_literal
;
234 return is_lit
&& ~(label
& label_constant_16bit
);
236 return is_lit
&& ~(label
& label_constant_32bit
);
243 bool is_constant_or_literal(unsigned bits
)
246 return label
& label_constant_64bit
;
248 return label
& label_literal
;
251 void set_abs(Temp abs_temp
)
253 add_label(label_abs
);
259 return label
& label_abs
;
262 void set_neg(Temp neg_temp
)
264 add_label(label_neg
);
270 return label
& label_neg
;
273 void set_neg_abs(Temp neg_abs_temp
)
275 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
279 void set_mul(Instruction
* mul
)
281 add_label(label_mul
);
287 return label
& label_mul
;
290 void set_temp(Temp tmp
)
292 add_label(label_temp
);
298 return label
& label_temp
;
301 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
303 add_label(label_mad
);
304 mad
->pass_flags
= mad_info_idx
;
310 return label
& label_mad
;
313 void set_omod2(Temp def
)
315 add_label(label_omod2
);
321 return label
& label_omod2
;
324 void set_omod4(Temp def
)
326 add_label(label_omod4
);
332 return label
& label_omod4
;
335 void set_omod5(Temp def
)
337 add_label(label_omod5
);
343 return label
& label_omod5
;
346 void set_omod_success(Instruction
* omod_instr
)
348 add_label(label_omod_success
);
352 bool is_omod_success()
354 return label
& label_omod_success
;
357 void set_clamp(Temp def
)
359 add_label(label_clamp
);
365 return label
& label_clamp
;
368 void set_clamp_success(Instruction
* clamp_instr
)
370 add_label(label_clamp_success
);
374 bool is_clamp_success()
376 return label
& label_clamp_success
;
381 add_label(label_undefined
);
386 return label
& label_undefined
;
389 void set_vcc(Temp vcc
)
391 add_label(label_vcc
);
397 return label
& label_vcc
;
400 void set_b2f(Temp val
)
402 add_label(label_b2f
);
408 return label
& label_b2f
;
411 void set_add_sub(Instruction
*add_sub_instr
)
413 add_label(label_add_sub
);
414 instr
= add_sub_instr
;
419 return label
& label_add_sub
;
422 void set_bitwise(Instruction
*bitwise_instr
)
424 add_label(label_bitwise
);
425 instr
= bitwise_instr
;
430 return label
& label_bitwise
;
433 void set_uniform_bitwise()
435 add_label(label_uniform_bitwise
);
438 bool is_uniform_bitwise()
440 return label
& label_uniform_bitwise
;
443 void set_minmax(Instruction
*minmax_instr
)
445 add_label(label_minmax
);
446 instr
= minmax_instr
;
451 return label
& label_minmax
;
454 void set_vopc(Instruction
*vopc_instr
)
456 add_label(label_vopc
);
462 return label
& label_vopc
;
465 void set_scc_needed()
467 add_label(label_scc_needed
);
472 return label
& label_scc_needed
;
475 void set_scc_invert(Temp scc_inv
)
477 add_label(label_scc_invert
);
483 return label
& label_scc_invert
;
486 void set_uniform_bool(Temp uniform_bool
)
488 add_label(label_uniform_bool
);
492 bool is_uniform_bool()
494 return label
& label_uniform_bool
;
499 add_label(label_vcc_hint
);
504 return label
& label_vcc_hint
;
507 void set_b2i(Temp val
)
509 add_label(label_b2i
);
515 return label
& label_b2i
;
522 std::vector
<aco_ptr
<Instruction
>> instructions
;
524 std::pair
<uint32_t,Temp
> last_literal
;
525 std::vector
<mad_info
> mad_infos
;
526 std::vector
<uint16_t> uses
;
531 aco_opcode unordered
;
532 aco_opcode ordered_swapped
;
533 aco_opcode unordered_swapped
;
539 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
);
541 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
543 if (instr
->operands
[0].isConstant() ||
544 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
547 switch (instr
->opcode
) {
548 case aco_opcode::v_add_u32
:
549 case aco_opcode::v_add_co_u32
:
550 case aco_opcode::v_add_co_u32_e64
:
551 case aco_opcode::v_add_i32
:
552 case aco_opcode::v_add_f16
:
553 case aco_opcode::v_add_f32
:
554 case aco_opcode::v_mul_f16
:
555 case aco_opcode::v_mul_f32
:
556 case aco_opcode::v_or_b32
:
557 case aco_opcode::v_and_b32
:
558 case aco_opcode::v_xor_b32
:
559 case aco_opcode::v_max_f16
:
560 case aco_opcode::v_max_f32
:
561 case aco_opcode::v_min_f16
:
562 case aco_opcode::v_min_f32
:
563 case aco_opcode::v_max_i32
:
564 case aco_opcode::v_min_i32
:
565 case aco_opcode::v_max_u32
:
566 case aco_opcode::v_min_u32
:
567 case aco_opcode::v_max_i16
:
568 case aco_opcode::v_min_i16
:
569 case aco_opcode::v_max_u16
:
570 case aco_opcode::v_min_u16
:
571 case aco_opcode::v_max_i16_e64
:
572 case aco_opcode::v_min_i16_e64
:
573 case aco_opcode::v_max_u16_e64
:
574 case aco_opcode::v_min_u16_e64
:
576 case aco_opcode::v_sub_f16
:
577 instr
->opcode
= aco_opcode::v_subrev_f16
;
579 case aco_opcode::v_sub_f32
:
580 instr
->opcode
= aco_opcode::v_subrev_f32
;
582 case aco_opcode::v_sub_co_u32
:
583 instr
->opcode
= aco_opcode::v_subrev_co_u32
;
585 case aco_opcode::v_sub_u16
:
586 instr
->opcode
= aco_opcode::v_subrev_u16
;
588 case aco_opcode::v_sub_u32
:
589 instr
->opcode
= aco_opcode::v_subrev_u32
;
593 get_cmp_info(instr
->opcode
, &info
);
594 if (info
.ordered
== instr
->opcode
) {
595 instr
->opcode
= info
.ordered_swapped
;
598 if (info
.unordered
== instr
->opcode
) {
599 instr
->opcode
= info
.unordered_swapped
;
607 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
612 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
615 if (instr
->isDPP() || instr
->isSDWA())
618 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
619 instr
->opcode
!= aco_opcode::v_madak_f32
&&
620 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
621 instr
->opcode
!= aco_opcode::v_madak_f16
&&
622 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
623 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
624 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
625 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
626 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
627 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
628 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
631 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
633 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
634 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
635 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
636 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
637 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
640 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
645 aco_ptr
<Instruction
> tmp
= std::move(instr
);
646 Format format
= asVOP3(tmp
->format
);
647 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
648 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
649 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
650 instr
->definitions
[i
] = tmp
->definitions
[i
];
651 if (instr
->definitions
[i
].isTemp()) {
652 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
653 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
654 info
.instr
= instr
.get();
659 /* only covers special cases */
660 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
663 case aco_opcode::v_interp_p2_f32
:
664 case aco_opcode::v_mac_f32
:
665 case aco_opcode::v_writelane_b32
:
666 case aco_opcode::v_writelane_b32_e64
:
667 case aco_opcode::v_cndmask_b32
:
669 case aco_opcode::s_addk_i32
:
670 case aco_opcode::s_mulk_i32
:
671 case aco_opcode::p_wqm
:
672 case aco_opcode::p_extract_vector
:
673 case aco_opcode::p_split_vector
:
674 case aco_opcode::v_readlane_b32
:
675 case aco_opcode::v_readlane_b32_e64
:
676 case aco_opcode::v_readfirstlane_b32
:
683 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
685 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
686 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
691 /* check constant bus and literal limitations */
692 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
694 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
695 Operand
literal32(s1
);
696 Operand
literal64(s2
);
697 unsigned num_sgprs
= 0;
698 unsigned sgpr
[] = {0, 0};
700 for (unsigned i
= 0; i
< num_operands
; i
++) {
701 Operand op
= operands
[i
];
703 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
704 /* two reads of the same SGPR count as 1 to the limit */
705 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
707 sgpr
[num_sgprs
++] = op
.tempId();
712 } else if (op
.isLiteral()) {
713 if (ctx
.program
->chip_class
< GFX10
)
716 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
718 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
721 /* Any number of 32-bit literals counts as only 1 to the limit. Same
722 * (but separately) for 64-bit literals. */
723 if (op
.size() == 1 && literal32
.isUndefined()) {
726 } else if (op
.size() == 2 && literal64
.isUndefined()) {
739 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
, bool prevent_overflow
)
741 Operand op
= instr
->operands
[op_index
];
745 Temp tmp
= op
.getTemp();
746 if (!ctx
.info
[tmp
.id()].is_add_sub())
749 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
751 switch (add_instr
->opcode
) {
752 case aco_opcode::v_add_u32
:
753 case aco_opcode::v_add_co_u32
:
754 case aco_opcode::v_add_co_u32_e64
:
755 case aco_opcode::s_add_i32
:
756 case aco_opcode::s_add_u32
:
761 if (prevent_overflow
&& !add_instr
->definitions
[0].isNUW())
764 if (add_instr
->usesModifiers())
767 for (unsigned i
= 0; i
< 2; i
++) {
768 if (add_instr
->operands
[i
].isConstant()) {
769 *offset
= add_instr
->operands
[i
].constantValue();
770 } else if (add_instr
->operands
[i
].isTemp() &&
771 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
772 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
776 if (!add_instr
->operands
[!i
].isTemp())
779 uint32_t offset2
= 0;
780 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
, prevent_overflow
)) {
783 *base
= add_instr
->operands
[!i
].getTemp();
791 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
793 if (instr
->format
== Format::PSEUDO
)
794 return instr
->operands
[index
].bytes() * 8u;
795 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
796 return index
== 2 ? 64 : 32;
797 else if (instr
->isVALU() || instr
->isSALU())
798 return instr_info
.operand_size
[(int)instr
->opcode
];
803 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
806 return Operand((uint8_t)info
.val
);
808 return Operand((uint16_t)info
.val
);
809 // TODO: this functions shouldn't be needed if we store Operand instead of value.
810 Operand
op(info
.val
, bits
== 64);
811 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
812 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
816 bool fixed_to_exec(Operand op
)
818 return op
.isFixed() && op
.physReg() == exec
;
821 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
823 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
824 ASSERTED
bool all_const
= false;
825 for (Operand
& op
: instr
->operands
)
826 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
827 perfwarn(ctx
.program
, all_const
, "All instruction operands are constant", instr
.get());
830 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
832 if (!instr
->operands
[i
].isTemp())
835 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
836 /* propagate undef */
837 if (info
.is_undefined() && is_phi(instr
))
838 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
839 /* propagate reg->reg of same type */
840 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
841 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
842 info
= ctx
.info
[info
.temp
.id()];
845 /* SALU / PSEUDO: propagate inline constants */
846 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
847 bool is_subdword
= false;
848 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
849 if (instr
->format
== Format::PSEUDO
) {
850 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
851 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
852 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
853 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
854 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
858 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
859 instr
->operands
[i
].setTemp(info
.temp
);
860 info
= ctx
.info
[info
.temp
.id()];
861 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
862 /* propagate vgpr if it can take it */
863 switch (instr
->opcode
) {
864 case aco_opcode::p_create_vector
:
865 case aco_opcode::p_split_vector
:
866 case aco_opcode::p_extract_vector
:
867 case aco_opcode::p_phi
: {
868 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
869 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
871 instr
->operands
[i
] = Operand(info
.temp
);
872 info
= ctx
.info
[info
.temp
.id()];
880 unsigned bits
= get_operand_size(instr
, i
);
881 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
882 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
883 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
888 /* VALU: propagate neg, abs & inline constants */
889 else if (instr
->isVALU()) {
890 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
891 instr
->operands
[i
].setTemp(info
.temp
);
892 info
= ctx
.info
[info
.temp
.id()];
895 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
896 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
897 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
899 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
902 instr
->operands
[i
] = Operand(info
.temp
);
904 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
906 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
908 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
909 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
910 instr
->operands
[i
].setTemp(info
.temp
);
912 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
913 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
914 instr
->operands
[i
].setTemp(info
.temp
);
916 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
919 instr
->operands
[i
].setTemp(info
.temp
);
921 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
923 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
926 unsigned bits
= get_operand_size(instr
, i
);
927 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
928 Operand op
= get_constant_op(ctx
, info
, bits
);
929 perfwarn(ctx
.program
, instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
930 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
931 instr
->operands
[i
] = op
;
933 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
934 instr
->operands
[i
] = instr
->operands
[0];
935 instr
->operands
[0] = op
;
937 } else if (can_use_VOP3(ctx
, instr
)) {
939 instr
->operands
[i
] = op
;
945 /* MUBUF: propagate constants and combine additions */
946 else if (instr
->format
== Format::MUBUF
) {
947 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
950 while (info
.is_temp())
951 info
= ctx
.info
[info
.temp
.id()];
953 /* According to AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(), vaddr
954 * overflow for scratch accesses works only on GFX9+ and saddr overflow
955 * never works. Since swizzling is the only thing that separates
956 * scratch accesses and other accesses and swizzling changing how
957 * addressing works significantly, this probably applies to swizzled
959 bool vaddr_prevent_overflow
= mubuf
->swizzled
&& ctx
.program
->chip_class
< GFX9
;
960 bool saddr_prevent_overflow
= mubuf
->swizzled
;
962 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
963 assert(!mubuf
->idxen
);
964 instr
->operands
[1] = Operand(v1
);
965 mubuf
->offset
+= info
.val
;
966 mubuf
->offen
= false;
968 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
969 instr
->operands
[2] = Operand((uint32_t) 0);
970 mubuf
->offset
+= info
.val
;
972 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, vaddr_prevent_overflow
) &&
973 base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
974 assert(!mubuf
->idxen
);
975 instr
->operands
[1].setTemp(base
);
976 mubuf
->offset
+= offset
;
978 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, saddr_prevent_overflow
) &&
979 base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
980 instr
->operands
[i
].setTemp(base
);
981 mubuf
->offset
+= offset
;
986 /* DS: combine additions */
987 else if (instr
->format
== Format::DS
) {
989 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
992 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
993 if (has_usable_ds_offset
&&
994 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, false) &&
995 base
.regClass() == instr
->operands
[i
].regClass() &&
996 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
997 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
998 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
999 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
1000 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
1002 if ((offset
& mask
) == 0 &&
1003 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
1004 ds
->offset1
+ (offset
>> shifts
) <= 255) {
1005 instr
->operands
[i
].setTemp(base
);
1006 ds
->offset0
+= offset
>> shifts
;
1007 ds
->offset1
+= offset
>> shifts
;
1010 if (ds
->offset0
+ offset
<= 65535) {
1011 instr
->operands
[i
].setTemp(base
);
1012 ds
->offset0
+= offset
;
1018 /* SMEM: propagate constants and combine additions */
1019 else if (instr
->format
== Format::SMEM
) {
1021 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
1024 bool prevent_overflow
= smem
->operands
[0].size() > 2 || smem
->prevent_overflow
;
1025 if (i
== 1 && info
.is_constant_or_literal(32) &&
1026 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
1027 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
1028 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
1029 instr
->operands
[i
] = Operand(info
.val
);
1031 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
, prevent_overflow
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
1032 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
1034 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
1035 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
1039 smem
->operands
[1] = Operand(offset
);
1040 smem
->operands
.back() = Operand(base
);
1042 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
1043 new_instr
->operands
[0] = smem
->operands
[0];
1044 new_instr
->operands
[1] = Operand(offset
);
1045 if (smem
->definitions
.empty())
1046 new_instr
->operands
[2] = smem
->operands
[2];
1047 new_instr
->operands
.back() = Operand(base
);
1048 if (!smem
->definitions
.empty())
1049 new_instr
->definitions
[0] = smem
->definitions
[0];
1050 new_instr
->sync
= smem
->sync
;
1051 new_instr
->glc
= smem
->glc
;
1052 new_instr
->dlc
= smem
->dlc
;
1053 new_instr
->nv
= smem
->nv
;
1054 new_instr
->disable_wqm
= smem
->disable_wqm
;
1055 instr
.reset(new_instr
);
1056 smem
= static_cast<SMEM_instruction
*>(instr
.get());
1062 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
1063 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1064 /* Flip the branch instruction to get rid of the scc_invert instruction */
1065 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
1066 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1071 /* if this instruction doesn't define anything, return */
1072 if (instr
->definitions
.empty())
1075 if ((uint16_t) instr
->format
& (uint16_t) Format::VOPC
) {
1076 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(instr
.get());
1080 switch (instr
->opcode
) {
1081 case aco_opcode::p_create_vector
: {
1082 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1083 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1085 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1089 unsigned num_ops
= instr
->operands
.size();
1090 for (const Operand
& op
: instr
->operands
) {
1091 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1092 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1094 if (num_ops
!= instr
->operands
.size()) {
1095 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1096 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1097 instr
->definitions
[0] = old_vec
->definitions
[0];
1099 for (Operand
& old_op
: old_vec
->operands
) {
1100 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1101 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1102 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1103 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1104 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1105 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1106 instr
->operands
[k
++] = op
;
1109 instr
->operands
[k
++] = old_op
;
1112 assert(k
== num_ops
);
1115 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1118 case aco_opcode::p_split_vector
: {
1119 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1121 if (info
.is_constant_or_literal(32)) {
1122 uint32_t val
= info
.val
;
1123 for (Definition def
: instr
->definitions
) {
1124 uint32_t mask
= u_bit_consecutive(0, def
.bytes() * 8u);
1125 ctx
.info
[def
.tempId()].set_constant(ctx
.program
->chip_class
, val
& mask
);
1126 val
>>= def
.bytes() * 8u;
1129 } else if (!info
.is_vec()) {
1133 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1134 unsigned split_offset
= 0;
1135 unsigned vec_offset
= 0;
1136 unsigned vec_index
= 0;
1137 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1138 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1139 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1141 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1144 Operand vec_op
= vec
->operands
[vec_index
];
1145 if (vec_op
.isConstant()) {
1146 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1147 } else if (vec_op
.isUndefined()) {
1148 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1150 assert(vec_op
.isTemp());
1151 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1156 case aco_opcode::p_extract_vector
: { /* mov */
1157 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1158 const unsigned index
= instr
->operands
[1].constantValue();
1159 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1161 if (info
.is_constant_or_literal(32)) {
1162 uint32_t mask
= u_bit_consecutive(0, instr
->definitions
[0].bytes() * 8u);
1163 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, (info
.val
>> (dst_offset
* 8u)) & mask
);
1165 } else if (!info
.is_vec()) {
1169 /* check if we index directly into a vector element */
1170 Instruction
* vec
= info
.instr
;
1171 unsigned offset
= 0;
1173 for (const Operand
& op
: vec
->operands
) {
1174 if (offset
< dst_offset
) {
1175 offset
+= op
.bytes();
1177 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1181 /* convert this extract into a copy instruction */
1182 instr
->opcode
= aco_opcode::p_parallelcopy
;
1183 instr
->operands
.pop_back();
1184 instr
->operands
[0] = op
;
1186 if (op
.isConstant()) {
1187 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1188 } else if (op
.isUndefined()) {
1189 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1191 assert(op
.isTemp());
1192 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1198 case aco_opcode::s_mov_b32
: /* propagate */
1199 case aco_opcode::s_mov_b64
:
1200 case aco_opcode::v_mov_b32
:
1201 case aco_opcode::p_as_uniform
:
1202 if (instr
->definitions
[0].isFixed()) {
1203 /* don't copy-propagate copies into fixed registers */
1204 } else if (instr
->usesModifiers()) {
1206 } else if (instr
->operands
[0].isConstant()) {
1207 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1208 } else if (instr
->operands
[0].isTemp()) {
1209 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1211 assert(instr
->operands
[0].isFixed());
1214 case aco_opcode::p_is_helper
:
1215 if (!ctx
.program
->needs_wqm
)
1216 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1218 case aco_opcode::s_movk_i32
: {
1219 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1220 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1221 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1224 case aco_opcode::v_bfrev_b32
:
1225 case aco_opcode::s_brev_b32
: {
1226 if (instr
->operands
[0].isConstant()) {
1227 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1228 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1232 case aco_opcode::s_bfm_b32
: {
1233 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1234 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1235 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1236 uint32_t v
= ((1u << size
) - 1u) << start
;
1237 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1241 case aco_opcode::v_mul_f16
:
1242 case aco_opcode::v_mul_f32
: { /* omod */
1243 /* TODO: try to move the negate/abs modifier to the consumer instead */
1244 if (instr
->usesModifiers())
1247 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1249 for (unsigned i
= 0; i
< 2; i
++) {
1250 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1251 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1252 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1253 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1254 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1255 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1256 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1257 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1258 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1259 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1268 case aco_opcode::v_and_b32
: { /* abs */
1269 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1270 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1271 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1272 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1273 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1275 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1278 case aco_opcode::v_xor_b32
: { /* neg */
1279 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1280 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1281 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1282 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1283 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1284 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1285 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1286 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1287 instr
->opcode
= aco_opcode::v_or_b32
;
1288 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1290 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1294 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1298 case aco_opcode::v_med3_f16
:
1299 case aco_opcode::v_med3_f32
: { /* clamp */
1300 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1301 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1302 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1303 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1307 bool found_zero
= false, found_one
= false;
1308 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1309 for (unsigned i
= 0; i
< 3; i
++)
1311 if (instr
->operands
[i
].constantEquals(0))
1313 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1318 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1319 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1323 case aco_opcode::v_cndmask_b32
:
1324 if (instr
->operands
[0].constantEquals(0) &&
1325 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1326 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1327 else if (instr
->operands
[0].constantEquals(0) &&
1328 instr
->operands
[1].constantEquals(0x3f800000u
))
1329 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1330 else if (instr
->operands
[0].constantEquals(0) &&
1331 instr
->operands
[1].constantEquals(1))
1332 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1334 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1336 case aco_opcode::v_cmp_lg_u32
:
1337 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1338 instr
->operands
[0].constantEquals(0) &&
1339 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1340 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1342 case aco_opcode::p_phi
:
1343 case aco_opcode::p_linear_phi
: {
1344 /* lower_bool_phis() can create phis like this */
1345 bool all_same_temp
= instr
->operands
[0].isTemp();
1346 /* this check is needed when moving uniform loop counters out of a divergent loop */
1348 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1349 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1350 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1351 all_same_temp
= false;
1353 if (all_same_temp
) {
1354 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1356 bool all_undef
= instr
->operands
[0].isUndefined();
1357 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1358 if (!instr
->operands
[i
].isUndefined())
1362 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1366 case aco_opcode::v_add_u32
:
1367 case aco_opcode::v_add_co_u32
:
1368 case aco_opcode::v_add_co_u32_e64
:
1369 case aco_opcode::s_add_i32
:
1370 case aco_opcode::s_add_u32
:
1371 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1373 case aco_opcode::s_not_b32
:
1374 case aco_opcode::s_not_b64
:
1375 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1376 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1377 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1378 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1379 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1380 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1382 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1384 case aco_opcode::s_and_b32
:
1385 case aco_opcode::s_and_b64
:
1386 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1387 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1388 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1389 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1390 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1392 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1393 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1394 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1395 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1397 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_vopc()) {
1398 Instruction
* vopc_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1399 /* Remove superfluous s_and when the VOPC instruction uses the same exec and thus already produces the same result */
1400 if (vopc_instr
->pass_flags
== instr
->pass_flags
) {
1401 assert(instr
->pass_flags
> 0);
1402 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vopc_instr
->definitions
[0].getTemp());
1408 case aco_opcode::s_or_b32
:
1409 case aco_opcode::s_or_b64
:
1410 case aco_opcode::s_xor_b32
:
1411 case aco_opcode::s_xor_b64
:
1412 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1413 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1415 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1418 case aco_opcode::s_lshl_b32
:
1419 case aco_opcode::v_or_b32
:
1420 case aco_opcode::v_lshlrev_b32
:
1421 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1423 case aco_opcode::v_min_f32
:
1424 case aco_opcode::v_min_f16
:
1425 case aco_opcode::v_min_u32
:
1426 case aco_opcode::v_min_i32
:
1427 case aco_opcode::v_min_u16
:
1428 case aco_opcode::v_min_i16
:
1429 case aco_opcode::v_max_f32
:
1430 case aco_opcode::v_max_f16
:
1431 case aco_opcode::v_max_u32
:
1432 case aco_opcode::v_max_i32
:
1433 case aco_opcode::v_max_u16
:
1434 case aco_opcode::v_max_i16
:
1435 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1437 case aco_opcode::s_cselect_b64
:
1438 case aco_opcode::s_cselect_b32
:
1439 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1440 instr
->operands
[1].constantEquals(0)) {
1441 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1442 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1444 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1445 /* Flip the operands to get rid of the scc_invert instruction */
1446 std::swap(instr
->operands
[0], instr
->operands
[1]);
1447 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1450 case aco_opcode::p_wqm
:
1451 if (instr
->operands
[0].isTemp() &&
1452 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1453 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1461 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
)
1463 info
->ordered
= aco_opcode::num_opcodes
;
1464 info
->unordered
= aco_opcode::num_opcodes
;
1465 info
->ordered_swapped
= aco_opcode::num_opcodes
;
1466 info
->unordered_swapped
= aco_opcode::num_opcodes
;
1468 #define CMP2(ord, unord, ord_swap, unord_swap, sz) \
1469 case aco_opcode::v_cmp_##ord##_f##sz:\
1470 case aco_opcode::v_cmp_n##unord##_f##sz:\
1471 info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
1472 info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
1473 info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz;\
1474 info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz;\
1475 info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
1476 info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
1479 #define CMP(ord, unord, ord_swap, unord_swap) \
1480 CMP2(ord, unord, ord_swap, unord_swap, 16)\
1481 CMP2(ord, unord, ord_swap, unord_swap, 32)\
1482 CMP2(ord, unord, ord_swap, unord_swap, 64)
1483 CMP(lt
, /*n*/ge
, gt
, /*n*/le
)
1484 CMP(eq
, /*n*/lg
, eq
, /*n*/lg
)
1485 CMP(le
, /*n*/gt
, ge
, /*n*/lt
)
1486 CMP(gt
, /*n*/le
, lt
, /*n*/le
)
1487 CMP(lg
, /*n*/eq
, lg
, /*n*/eq
)
1488 CMP(ge
, /*n*/lt
, le
, /*n*/gt
)
1491 #define ORD_TEST(sz) \
1492 case aco_opcode::v_cmp_u_f##sz:\
1493 info->f32 = aco_opcode::v_cmp_u_f32;\
1494 info->inverse = aco_opcode::v_cmp_o_f##sz;\
1497 case aco_opcode::v_cmp_o_f##sz:\
1498 info->f32 = aco_opcode::v_cmp_o_f32;\
1499 info->inverse = aco_opcode::v_cmp_u_f##sz;\
1511 aco_opcode
get_ordered(aco_opcode op
)
1514 return get_cmp_info(op
, &info
) ? info
.ordered
: aco_opcode::num_opcodes
;
1517 aco_opcode
get_unordered(aco_opcode op
)
1520 return get_cmp_info(op
, &info
) ? info
.unordered
: aco_opcode::num_opcodes
;
1523 aco_opcode
get_inverse(aco_opcode op
)
1526 return get_cmp_info(op
, &info
) ? info
.inverse
: aco_opcode::num_opcodes
;
1529 aco_opcode
get_f32_cmp(aco_opcode op
)
1532 return get_cmp_info(op
, &info
) ? info
.f32
: aco_opcode::num_opcodes
;
1535 unsigned get_cmp_bitsize(aco_opcode op
)
1538 return get_cmp_info(op
, &info
) ? info
.size
: 0;
1541 bool is_cmp(aco_opcode op
)
1544 return get_cmp_info(op
, &info
) && info
.ordered
!= aco_opcode::num_opcodes
;
1547 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1549 if (ctx
.info
[tmp
.id()].is_temp())
1550 return ctx
.info
[tmp
.id()].temp
.id();
1555 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1557 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1558 for (const Operand
& op
: instr
->operands
) {
1560 ctx
.uses
[op
.tempId()]--;
1565 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1567 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1569 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1572 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1574 if (instr
->definitions
.size() == 2) {
1575 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1576 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1583 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1584 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1585 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1587 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1589 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1592 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1594 bool neg
[2] = {false, false};
1595 bool abs
[2] = {false, false};
1597 Instruction
*op_instr
[2];
1600 unsigned bitsize
= 0;
1601 for (unsigned i
= 0; i
< 2; i
++) {
1602 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1606 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1607 unsigned op_bitsize
= get_cmp_bitsize(op_instr
[i
]->opcode
);
1609 if (get_f32_cmp(op_instr
[i
]->opcode
) != expected_cmp
)
1611 if (bitsize
&& op_bitsize
!= bitsize
)
1613 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1616 if (op_instr
[i
]->isVOP3()) {
1617 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1618 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1620 neg
[i
] = vop3
->neg
[0];
1621 abs
[i
] = vop3
->abs
[0];
1622 opsel
|= (vop3
->opsel
& 1) << i
;
1625 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1626 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1627 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1631 bitsize
= op_bitsize
;
1634 if (op
[1].type() == RegType::sgpr
)
1635 std::swap(op
[0], op
[1]);
1636 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1637 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1640 ctx
.uses
[op
[0].id()]++;
1641 ctx
.uses
[op
[1].id()]++;
1642 decrease_uses(ctx
, op_instr
[0]);
1643 decrease_uses(ctx
, op_instr
[1]);
1645 aco_opcode new_op
= aco_opcode::num_opcodes
;
1648 new_op
= is_or
? aco_opcode::v_cmp_u_f16
: aco_opcode::v_cmp_o_f16
;
1651 new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1654 new_op
= is_or
? aco_opcode::v_cmp_u_f64
: aco_opcode::v_cmp_o_f64
;
1657 Instruction
*new_instr
;
1658 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1659 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1660 for (unsigned i
= 0; i
< 2; i
++) {
1661 vop3
->neg
[i
] = neg
[i
];
1662 vop3
->abs
[i
] = abs
[i
];
1664 vop3
->opsel
= opsel
;
1665 new_instr
= static_cast<Instruction
*>(vop3
);
1667 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1669 new_instr
->operands
[0] = Operand(op
[0]);
1670 new_instr
->operands
[1] = Operand(op
[1]);
1671 new_instr
->definitions
[0] = instr
->definitions
[0];
1673 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1674 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1676 instr
.reset(new_instr
);
1681 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1682 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1683 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1685 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1687 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1690 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1691 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1693 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1694 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1695 if (!nan_test
|| !cmp
)
1698 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1699 std::swap(nan_test
, cmp
);
1700 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1703 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1706 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1708 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1711 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1712 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1713 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1714 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1715 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1717 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1720 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1721 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1722 decrease_uses(ctx
, nan_test
);
1723 decrease_uses(ctx
, cmp
);
1725 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1726 Instruction
*new_instr
;
1727 if (cmp
->isVOP3()) {
1728 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1729 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1730 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1731 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1732 new_vop3
->clamp
= cmp_vop3
->clamp
;
1733 new_vop3
->omod
= cmp_vop3
->omod
;
1734 new_vop3
->opsel
= cmp_vop3
->opsel
;
1735 new_instr
= new_vop3
;
1737 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1739 new_instr
->operands
[0] = cmp
->operands
[0];
1740 new_instr
->operands
[1] = cmp
->operands
[1];
1741 new_instr
->definitions
[0] = instr
->definitions
[0];
1743 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1744 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1746 instr
.reset(new_instr
);
1751 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1752 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1753 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1755 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1757 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1760 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1762 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1763 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1765 if (!nan_test
|| !cmp
)
1768 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1769 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1770 std::swap(nan_test
, cmp
);
1771 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1774 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1777 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1779 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1782 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1783 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1784 if (prop_nan0
!= prop_nan1
)
1787 if (nan_test
->isVOP3()) {
1788 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1789 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1793 int constant_operand
= -1;
1794 for (unsigned i
= 0; i
< 2; i
++) {
1795 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1796 constant_operand
= !i
;
1800 if (constant_operand
== -1)
1804 if (cmp
->operands
[constant_operand
].isConstant()) {
1805 constant
= cmp
->operands
[constant_operand
].constantValue();
1806 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1807 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1808 unsigned id
= original_temp_id(ctx
, tmp
);
1809 if (!ctx
.info
[id
].is_constant_or_literal(32))
1811 constant
= ctx
.info
[id
].val
;
1817 memcpy(&constantf
, &constant
, 4);
1818 if (isnan(constantf
))
1821 if (cmp
->operands
[0].isTemp())
1822 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1823 if (cmp
->operands
[1].isTemp())
1824 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1825 decrease_uses(ctx
, nan_test
);
1826 decrease_uses(ctx
, cmp
);
1828 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1829 Instruction
*new_instr
;
1830 if (cmp
->isVOP3()) {
1831 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1832 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1833 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1834 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1835 new_vop3
->clamp
= cmp_vop3
->clamp
;
1836 new_vop3
->omod
= cmp_vop3
->omod
;
1837 new_vop3
->opsel
= cmp_vop3
->opsel
;
1838 new_instr
= new_vop3
;
1840 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1842 new_instr
->operands
[0] = cmp
->operands
[0];
1843 new_instr
->operands
[1] = cmp
->operands
[1];
1844 new_instr
->definitions
[0] = instr
->definitions
[0];
1846 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1847 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1849 instr
.reset(new_instr
);
1854 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1855 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1857 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1859 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1861 if (!instr
->operands
[0].isTemp())
1864 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1868 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1869 if (new_opcode
== aco_opcode::num_opcodes
)
1872 if (cmp
->operands
[0].isTemp())
1873 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1874 if (cmp
->operands
[1].isTemp())
1875 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1876 decrease_uses(ctx
, cmp
);
1878 Instruction
*new_instr
;
1879 if (cmp
->isVOP3()) {
1880 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1881 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1882 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1883 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1884 new_vop3
->clamp
= cmp_vop3
->clamp
;
1885 new_vop3
->omod
= cmp_vop3
->omod
;
1886 new_vop3
->opsel
= cmp_vop3
->opsel
;
1887 new_instr
= new_vop3
;
1889 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1891 new_instr
->operands
[0] = cmp
->operands
[0];
1892 new_instr
->operands
[1] = cmp
->operands
[1];
1893 new_instr
->definitions
[0] = instr
->definitions
[0];
1895 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1896 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1898 instr
.reset(new_instr
);
1903 /* op1(op2(1, 2), 0) if swap = false
1904 * op1(0, op2(1, 2)) if swap = true */
1905 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1906 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1907 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1908 bool *op1_clamp
, uint8_t *op1_omod
,
1909 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1912 if (op1_instr
->opcode
!= op1
)
1915 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1916 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1918 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1921 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1922 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1924 /* don't support inbetween clamp/omod */
1925 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1928 /* get operands and modifiers and check inbetween modifiers */
1929 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1930 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1933 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1934 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1938 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1939 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1942 if (inbetween_opsel
)
1943 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1944 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1948 shuffle
[shuffle_str
[0] - '0'] = 0;
1949 shuffle
[shuffle_str
[1] - '0'] = 1;
1950 shuffle
[shuffle_str
[2] - '0'] = 2;
1952 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1953 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1954 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1955 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1956 *opsel
|= 1 << shuffle
[0];
1958 for (unsigned i
= 0; i
< 2; i
++) {
1959 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1960 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1961 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1962 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1963 *opsel
|= 1 << shuffle
[i
+ 1];
1966 /* check operands */
1967 if (!check_vop3_operands(ctx
, 3, operands
))
1973 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1974 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1975 bool clamp
, unsigned omod
)
1977 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1978 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1979 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1980 new_instr
->clamp
= clamp
;
1981 new_instr
->omod
= omod
;
1982 new_instr
->opsel
= opsel
;
1983 new_instr
->operands
[0] = operands
[0];
1984 new_instr
->operands
[1] = operands
[1];
1985 new_instr
->operands
[2] = operands
[2];
1986 new_instr
->definitions
[0] = instr
->definitions
[0];
1987 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1989 instr
.reset(new_instr
);
1992 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1994 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1995 (label_omod_success
| label_clamp_success
);
1997 for (unsigned swap
= 0; swap
< 2; swap
++) {
1998 if (!((1 << swap
) & ops
))
2001 Operand operands
[3];
2002 bool neg
[3], abs
[3], clamp
;
2003 uint8_t opsel
= 0, omod
= 0;
2004 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
2005 instr
.get(), swap
, shuffle
,
2006 operands
, neg
, abs
, &opsel
,
2007 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2008 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2009 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2010 if (omod_clamp
& label_omod_success
)
2011 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2012 if (omod_clamp
& label_clamp_success
)
2013 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2020 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
2022 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
2025 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2026 (label_omod_success
| label_clamp_success
);
2028 /* min(-max(a, b), c) -> min3(-a, -b, c) *
2029 * max(-min(a, b), c) -> max3(-a, -b, c) */
2030 for (unsigned swap
= 0; swap
< 2; swap
++) {
2031 Operand operands
[3];
2032 bool neg
[3], abs
[3], clamp
;
2033 uint8_t opsel
= 0, omod
= 0;
2035 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
2036 instr
.get(), swap
, "012",
2037 operands
, neg
, abs
, &opsel
,
2038 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
2040 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2043 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2044 if (omod_clamp
& label_omod_success
)
2045 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2046 if (omod_clamp
& label_clamp_success
)
2047 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2054 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
2055 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
2056 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
2057 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
2058 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
2059 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
2060 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2063 if (!instr
->operands
[0].isTemp())
2065 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
2068 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
2071 switch (op2_instr
->opcode
) {
2072 case aco_opcode::s_and_b32
:
2073 case aco_opcode::s_or_b32
:
2074 case aco_opcode::s_xor_b32
:
2075 case aco_opcode::s_and_b64
:
2076 case aco_opcode::s_or_b64
:
2077 case aco_opcode::s_xor_b64
:
2083 /* create instruction */
2084 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
2085 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
2086 ctx
.uses
[instr
->operands
[0].tempId()]--;
2087 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
2089 switch (op2_instr
->opcode
) {
2090 case aco_opcode::s_and_b32
:
2091 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
2093 case aco_opcode::s_or_b32
:
2094 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
2096 case aco_opcode::s_xor_b32
:
2097 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
2099 case aco_opcode::s_and_b64
:
2100 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
2102 case aco_opcode::s_or_b64
:
2103 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
2105 case aco_opcode::s_xor_b64
:
2106 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
2115 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
2116 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
2117 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
2118 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
2119 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2121 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
2124 for (unsigned i
= 0; i
< 2; i
++) {
2125 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2126 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
2128 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
2131 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2132 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2135 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2136 instr
->operands
[0] = instr
->operands
[!i
];
2137 instr
->operands
[1] = op2_instr
->operands
[0];
2138 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2140 switch (instr
->opcode
) {
2141 case aco_opcode::s_and_b32
:
2142 instr
->opcode
= aco_opcode::s_andn2_b32
;
2144 case aco_opcode::s_or_b32
:
2145 instr
->opcode
= aco_opcode::s_orn2_b32
;
2147 case aco_opcode::s_and_b64
:
2148 instr
->opcode
= aco_opcode::s_andn2_b64
;
2150 case aco_opcode::s_or_b64
:
2151 instr
->opcode
= aco_opcode::s_orn2_b64
;
2162 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2163 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2165 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2168 for (unsigned i
= 0; i
< 2; i
++) {
2169 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2170 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2171 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2173 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2176 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2177 if (shift
< 1 || shift
> 4)
2180 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2181 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2184 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2185 instr
->operands
[1] = instr
->operands
[!i
];
2186 instr
->operands
[0] = op2_instr
->operands
[0];
2187 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2189 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2190 aco_opcode::s_lshl2_add_u32
,
2191 aco_opcode::s_lshl3_add_u32
,
2192 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2199 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2201 if (instr
->usesModifiers())
2204 for (unsigned i
= 0; i
< 2; i
++) {
2205 if (!((1 << i
) & ops
))
2207 if (instr
->operands
[i
].isTemp() &&
2208 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2209 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2211 aco_ptr
<Instruction
> new_instr
;
2212 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2213 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2214 } else if (ctx
.program
->chip_class
>= GFX10
||
2215 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2216 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2220 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2221 new_instr
->definitions
[0] = instr
->definitions
[0];
2222 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2223 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2224 new_instr
->definitions
[1].setHint(vcc
);
2225 new_instr
->operands
[0] = Operand(0u);
2226 new_instr
->operands
[1] = instr
->operands
[!i
];
2227 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2228 instr
= std::move(new_instr
);
2229 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2237 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2240 #define MINMAX(type, gfx9) \
2241 case aco_opcode::v_min_##type:\
2242 case aco_opcode::v_max_##type:\
2243 case aco_opcode::v_med3_##type:\
2244 *min = aco_opcode::v_min_##type;\
2245 *max = aco_opcode::v_max_##type;\
2246 *med3 = aco_opcode::v_med3_##type;\
2247 *min3 = aco_opcode::v_min3_##type;\
2248 *max3 = aco_opcode::v_max3_##type;\
2249 *some_gfx9_only = gfx9;\
2263 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2264 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2265 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2266 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2268 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2269 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2270 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2271 aco_opcode other_op
;
2272 if (instr
->opcode
== min
)
2274 else if (instr
->opcode
== max
)
2279 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2280 (label_omod_success
| label_clamp_success
);
2282 for (unsigned swap
= 0; swap
< 2; swap
++) {
2283 Operand operands
[3];
2284 bool neg
[3], abs
[3], clamp
;
2285 uint8_t opsel
= 0, omod
= 0;
2286 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2287 "012", operands
, neg
, abs
, &opsel
,
2288 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2289 int const0_idx
= -1, const1_idx
= -1;
2290 uint32_t const0
= 0, const1
= 0;
2291 for (int i
= 0; i
< 3; i
++) {
2293 if (operands
[i
].isConstant()) {
2294 val
= operands
[i
].constantValue();
2295 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2296 val
= ctx
.info
[operands
[i
].tempId()].val
;
2300 if (const0_idx
>= 0) {
2308 if (const0_idx
< 0 || const1_idx
< 0)
2311 if (opsel
& (1 << const0_idx
))
2313 if (opsel
& (1 << const1_idx
))
2316 int lower_idx
= const0_idx
;
2318 case aco_opcode::v_min_f32
:
2319 case aco_opcode::v_min_f16
: {
2320 float const0_f
, const1_f
;
2321 if (min
== aco_opcode::v_min_f32
) {
2322 memcpy(&const0_f
, &const0
, 4);
2323 memcpy(&const1_f
, &const1
, 4);
2325 const0_f
= _mesa_half_to_float(const0
);
2326 const1_f
= _mesa_half_to_float(const1
);
2328 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2329 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2330 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2331 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2332 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2335 case aco_opcode::v_min_u32
: {
2336 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2339 case aco_opcode::v_min_u16
: {
2340 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2343 case aco_opcode::v_min_i32
: {
2344 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2345 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2346 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2349 case aco_opcode::v_min_i16
: {
2350 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2351 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2352 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2358 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2360 if (instr
->opcode
== min
) {
2361 if (upper_idx
!= 0 || lower_idx
== 0)
2364 if (upper_idx
== 0 || lower_idx
!= 0)
2368 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2369 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2370 if (omod_clamp
& label_omod_success
)
2371 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2372 if (omod_clamp
& label_clamp_success
)
2373 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2383 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2385 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2386 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2387 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2389 /* find candidates and create the set of sgprs already read */
2390 unsigned sgpr_ids
[2] = {0, 0};
2391 uint32_t operand_mask
= 0;
2392 bool has_literal
= false;
2393 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2394 if (instr
->operands
[i
].isLiteral())
2396 if (!instr
->operands
[i
].isTemp())
2398 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2399 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2400 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2402 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2403 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2404 operand_mask
|= 1u << i
;
2406 unsigned max_sgprs
= 1;
2407 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2412 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2414 /* keep on applying sgprs until there is nothing left to be done */
2415 while (operand_mask
) {
2416 uint32_t sgpr_idx
= 0;
2417 uint32_t sgpr_info_id
= 0;
2418 uint32_t mask
= operand_mask
;
2421 unsigned i
= u_bit_scan(&mask
);
2422 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2423 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2425 sgpr_info_id
= instr
->operands
[i
].tempId();
2428 operand_mask
&= ~(1u << sgpr_idx
);
2430 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2431 * definitively beneficial.
2432 * TODO: this is too conservative because later the use count could be reduced to 1 */
2433 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2436 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2437 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2438 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2441 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2442 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2443 } else if (can_swap_operands(instr
)) {
2444 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2445 instr
->operands
[0] = Operand(sgpr
);
2446 /* swap bits using a 4-entry LUT */
2447 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2448 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2449 } else if (can_use_VOP3(ctx
, instr
)) {
2450 to_VOP3(ctx
, instr
);
2451 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2457 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2458 ctx
.uses
[sgpr_info_id
]--;
2459 ctx
.uses
[sgpr
.id()]++;
2463 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2465 /* check if we could apply omod on predecessor */
2466 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2467 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2468 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2470 unsigned idx
= op0
? 0 : 1;
2471 /* omod was successfully applied */
2472 /* if the omod instruction is v_mad, we also have to change the original add */
2473 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2474 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2475 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2476 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2477 add_instr
->definitions
[0] = instr
->definitions
[0];
2480 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2481 /* check if we have an additional clamp modifier */
2482 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2483 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2484 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2485 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2487 /* change definition ssa-id of modified instruction */
2488 omod_instr
->definitions
[0] = instr
->definitions
[0];
2490 /* change the definition of instr to something unused, e.g. the original omod def */
2491 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2492 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2495 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2496 /* in all other cases, label this instruction as option for multiply-add */
2497 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2501 /* check if we could apply clamp on predecessor */
2502 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2503 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2505 bool found_zero
= false, found_one
= false;
2506 for (unsigned i
= 0; i
< 3; i
++)
2508 if (instr
->operands
[i
].constantEquals(0))
2510 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2515 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2516 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2517 /* clamp was successfully applied */
2518 /* if the clamp instruction is v_mad, we also have to change the original add */
2519 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2520 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2521 add_instr
->definitions
[0] = instr
->definitions
[0];
2523 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2524 /* change definition ssa-id of modified instruction */
2525 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2527 /* change the definition of instr to something unused, e.g. the original omod def */
2528 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2529 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2534 /* omod has no effect if denormals are enabled */
2535 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2536 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2537 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2538 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2539 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2540 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2541 to_VOP3(ctx
, instr
);
2542 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2543 def_info
.set_omod_success(instr
.get());
2544 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2545 to_VOP3(ctx
, instr
);
2546 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2547 def_info
.set_omod_success(instr
.get());
2548 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2549 to_VOP3(ctx
, instr
);
2550 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2551 def_info
.set_omod_success(instr
.get());
2552 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2553 to_VOP3(ctx
, instr
);
2554 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2555 def_info
.set_clamp_success(instr
.get());
2562 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2563 // this would mean that we'd have to fix the instruction uses while value propagation
2565 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2567 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2570 if (instr
->isVALU()) {
2571 if (can_apply_sgprs(instr
))
2572 apply_sgprs(ctx
, instr
);
2573 if (apply_omod_clamp(ctx
, block
, instr
))
2577 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2578 instr
->definitions
[0].setHint(vcc
);
2581 /* TODO: There are still some peephole optimizations that could be done:
2582 * - abs(a - b) -> s_absdiff_i32
2583 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2584 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2585 * These aren't probably too interesting though.
2586 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2587 * probably more useful than the previously mentioned optimizations.
2588 * The various comparison optimizations also currently only work with 32-bit
2591 /* neg(mul(a, b)) -> mul(neg(a), b) */
2592 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2593 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2595 if (!ctx
.info
[val
.id()].is_mul())
2598 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2600 if (mul_instr
->operands
[0].isLiteral())
2602 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2605 /* convert to mul(neg(a), b) */
2606 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2607 Definition def
= instr
->definitions
[0];
2608 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2609 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2610 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2611 instr
->operands
[0] = mul_instr
->operands
[0];
2612 instr
->operands
[1] = mul_instr
->operands
[1];
2613 instr
->definitions
[0] = def
;
2614 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2615 if (mul_instr
->isVOP3()) {
2616 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2617 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2618 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2619 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2620 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2621 new_mul
->omod
= mul
->omod
;
2623 new_mul
->neg
[0] ^= true;
2624 new_mul
->clamp
= false;
2626 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2630 /* combine mul+add -> mad */
2631 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2632 instr
->opcode
== aco_opcode::v_sub_f32
||
2633 instr
->opcode
== aco_opcode::v_subrev_f32
;
2634 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2635 instr
->opcode
== aco_opcode::v_sub_f16
||
2636 instr
->opcode
== aco_opcode::v_subrev_f16
;
2637 if (mad16
|| mad32
) {
2638 bool need_fma
= mad32
? (block
.fp_mode
.denorm32
!= 0 || ctx
.program
->chip_class
>= GFX10_3
) :
2639 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2640 if (need_fma
&& instr
->definitions
[0].isPrecise())
2642 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2645 uint32_t uses_src0
= UINT32_MAX
;
2646 uint32_t uses_src1
= UINT32_MAX
;
2647 Instruction
* mul_instr
= nullptr;
2648 unsigned add_op_idx
;
2649 /* check if any of the operands is a multiplication */
2650 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2651 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2652 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2653 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2654 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2655 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2657 /* find the 'best' mul instruction to combine with the add */
2658 if (uses_src0
< uses_src1
) {
2659 mul_instr
= op0_info
->instr
;
2661 } else if (uses_src1
< uses_src0
) {
2662 mul_instr
= op1_info
->instr
;
2664 } else if (uses_src0
!= UINT32_MAX
) {
2665 /* tiebreaker: quite random what to pick */
2666 if (op0_info
->instr
->operands
[0].isLiteral()) {
2667 mul_instr
= op1_info
->instr
;
2670 mul_instr
= op0_info
->instr
;
2675 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2676 bool neg
[3] = {false, false, false};
2677 bool abs
[3] = {false, false, false};
2680 op
[0] = mul_instr
->operands
[0];
2681 op
[1] = mul_instr
->operands
[1];
2682 op
[2] = instr
->operands
[add_op_idx
];
2683 // TODO: would be better to check this before selecting a mul instr?
2684 if (!check_vop3_operands(ctx
, 3, op
))
2687 if (mul_instr
->isVOP3()) {
2688 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2689 neg
[0] = vop3
->neg
[0];
2690 neg
[1] = vop3
->neg
[1];
2691 abs
[0] = vop3
->abs
[0];
2692 abs
[1] = vop3
->abs
[1];
2693 /* we cannot use these modifiers between mul and add */
2694 if (vop3
->clamp
|| vop3
->omod
)
2698 /* convert to mad */
2699 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2700 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2702 ctx
.uses
[op
[0].tempId()]++;
2704 ctx
.uses
[op
[1].tempId()]++;
2707 if (instr
->isVOP3()) {
2708 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2709 neg
[2] = vop3
->neg
[add_op_idx
];
2710 abs
[2] = vop3
->abs
[add_op_idx
];
2712 clamp
= vop3
->clamp
;
2713 /* abs of the multiplication result */
2714 if (vop3
->abs
[1 - add_op_idx
]) {
2720 /* neg of the multiplication result */
2721 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2723 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2724 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2725 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2726 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2728 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2730 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2731 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2733 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2734 for (unsigned i
= 0; i
< 3; i
++)
2736 mad
->operands
[i
] = op
[i
];
2737 mad
->neg
[i
] = neg
[i
];
2738 mad
->abs
[i
] = abs
[i
];
2742 mad
->definitions
[0] = instr
->definitions
[0];
2744 /* mark this ssa_def to be re-checked for profitability and literals */
2745 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2746 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2747 instr
.reset(mad
.release());
2751 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2752 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2753 for (unsigned i
= 0; i
< 2; i
++) {
2754 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2755 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2756 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2757 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2758 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2760 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2761 new_instr
->operands
[0] = Operand(0u);
2762 new_instr
->operands
[1] = instr
->operands
[!i
];
2763 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2764 new_instr
->definitions
[0] = instr
->definitions
[0];
2765 instr
.reset(new_instr
.release());
2766 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2770 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2771 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2772 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2773 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2774 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2775 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2776 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2777 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2778 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2779 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2780 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2781 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2782 else if (ctx
.program
->chip_class
>= GFX9
) {
2783 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2784 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2785 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2786 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2787 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2788 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2789 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2791 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2792 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2793 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2794 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2795 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2796 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2797 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2798 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2799 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2800 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2801 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2802 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2803 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2804 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2805 combine_salu_lshl_add(ctx
, instr
);
2806 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2807 combine_salu_not_bitwise(ctx
, instr
);
2808 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2809 if (combine_inverse_comparison(ctx
, instr
)) ;
2810 else combine_salu_not_bitwise(ctx
, instr
);
2811 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2812 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2813 if (combine_ordering_test(ctx
, instr
)) ;
2814 else if (combine_comparison_ordering(ctx
, instr
)) ;
2815 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2816 else combine_salu_n2(ctx
, instr
);
2818 aco_opcode min
, max
, min3
, max3
, med3
;
2819 bool some_gfx9_only
;
2820 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2821 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2822 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2823 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2828 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2830 switch (instr
->opcode
) {
2831 case aco_opcode::s_and_b32
:
2832 case aco_opcode::s_and_b64
:
2833 instr
->opcode
= aco_opcode::s_and_b32
;
2835 case aco_opcode::s_or_b32
:
2836 case aco_opcode::s_or_b64
:
2837 instr
->opcode
= aco_opcode::s_or_b32
;
2839 case aco_opcode::s_xor_b32
:
2840 case aco_opcode::s_xor_b64
:
2841 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2844 /* Don't transform other instructions. They are very unlikely to appear here. */
2848 for (Operand
&op
: instr
->operands
) {
2849 ctx
.uses
[op
.tempId()]--;
2851 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2852 /* Just use the uniform boolean temp. */
2853 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2854 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2855 /* Use the SCC definition of the predecessor instruction.
2856 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2857 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2859 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2860 assert(pred_instr
->definitions
.size() >= 2);
2861 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2862 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2864 unreachable("Invalid operand on uniform bitwise instruction.");
2867 ctx
.uses
[op
.tempId()]++;
2870 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2871 assert(instr
->operands
[0].regClass() == s1
);
2872 assert(instr
->operands
[1].regClass() == s1
);
2876 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2878 const uint32_t threshold
= 4;
2880 if (is_dead(ctx
.uses
, instr
.get())) {
2885 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2886 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2887 unsigned num_used
= 0;
2889 unsigned split_offset
= 0;
2890 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2891 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2894 split_offset
= offset
;
2898 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2899 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2900 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2904 for (Operand
& vec_op
: vec
->operands
) {
2905 if (off
== split_offset
) {
2909 off
+= vec_op
.bytes();
2911 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2912 ctx
.uses
[instr
->operands
[0].tempId()]--;
2913 for (Operand
& vec_op
: vec
->operands
) {
2914 if (vec_op
.isTemp())
2915 ctx
.uses
[vec_op
.tempId()]--;
2918 ctx
.uses
[op
.tempId()]++;
2920 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2921 extract
->operands
[0] = op
;
2922 extract
->definitions
[0] = instr
->definitions
[idx
];
2923 instr
.reset(extract
.release());
2929 if (!done
&& num_used
== 1 &&
2930 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2931 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2932 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2933 extract
->operands
[0] = instr
->operands
[0];
2934 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2935 extract
->definitions
[0] = instr
->definitions
[idx
];
2936 instr
.reset(extract
.release());
2940 mad_info
* mad_info
= NULL
;
2941 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2942 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
2943 /* re-check mad instructions */
2944 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2945 ctx
.uses
[mad_info
->mul_temp_id
]++;
2946 if (instr
->operands
[0].isTemp())
2947 ctx
.uses
[instr
->operands
[0].tempId()]--;
2948 if (instr
->operands
[1].isTemp())
2949 ctx
.uses
[instr
->operands
[1].tempId()]--;
2950 instr
.swap(mad_info
->add_instr
);
2953 /* check literals */
2954 else if (!instr
->usesModifiers()) {
2955 /* FMA can only take literals on GFX10+ */
2956 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2957 ctx
.program
->chip_class
< GFX10
)
2960 bool sgpr_used
= false;
2961 uint32_t literal_idx
= 0;
2962 uint32_t literal_uses
= UINT32_MAX
;
2963 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2965 if (instr
->operands
[i
].isConstant() && i
> 0) {
2966 literal_uses
= UINT32_MAX
;
2969 if (!instr
->operands
[i
].isTemp())
2971 unsigned bits
= get_operand_size(instr
, i
);
2972 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2973 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2974 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2975 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2978 literal_uses
= UINT32_MAX
;
2981 /* don't break because we still need to check constants */
2982 } else if (!sgpr_used
&&
2983 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2984 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2985 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2990 /* Limit the number of literals to apply to not increase the code
2991 * size too much, but always apply literals for v_mad->v_madak
2992 * because both instructions are 64-bit and this doesn't increase
2994 * TODO: try to apply the literals earlier to lower the number of
2995 * uses below threshold
2997 if (literal_uses
< threshold
|| literal_idx
== 2) {
2998 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2999 mad_info
->check_literal
= true;
3000 mad_info
->literal_idx
= literal_idx
;
3006 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
3007 if (instr
->format
== Format::PSEUDO_BRANCH
&&
3008 instr
->operands
.size() &&
3009 instr
->operands
[0].isTemp()) {
3010 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
3012 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
3013 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
3014 instr
->operands
[2].isTemp()) {
3015 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
3018 /* check for literals */
3019 if (!instr
->isSALU() && !instr
->isVALU())
3022 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
3023 if (instr
->definitions
.size() &&
3024 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
3025 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
3026 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
3028 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
3029 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
3030 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
3031 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
3032 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
3033 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
3039 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
3040 return; /* some encodings can't ever take literals */
3042 /* we do not apply the literals yet as we don't know if it is profitable */
3043 Operand
current_literal(s1
);
3045 unsigned literal_id
= 0;
3046 unsigned literal_uses
= UINT32_MAX
;
3047 Operand
literal(s1
);
3048 unsigned num_operands
= 1;
3049 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
3050 num_operands
= instr
->operands
.size();
3051 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
3052 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
3055 unsigned sgpr_ids
[2] = {0, 0};
3056 bool is_literal_sgpr
= false;
3059 /* choose a literal to apply */
3060 for (unsigned i
= 0; i
< num_operands
; i
++) {
3061 Operand op
= instr
->operands
[i
];
3062 unsigned bits
= get_operand_size(instr
, i
);
3064 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
3065 op
.tempId() != sgpr_ids
[0])
3066 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
3068 if (op
.isLiteral()) {
3069 current_literal
= op
;
3071 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
3075 if (!alu_can_accept_constant(instr
->opcode
, i
))
3078 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
3079 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
3081 literal
= Operand(ctx
.info
[op
.tempId()].val
);
3082 literal_uses
= ctx
.uses
[op
.tempId()];
3083 literal_id
= op
.tempId();
3086 mask
|= (op
.tempId() == literal_id
) << i
;
3090 /* don't go over the constant bus limit */
3091 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
3092 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
3093 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
3094 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
3095 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
3096 const_bus_limit
= 2;
3098 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
3099 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
3102 if (literal_id
&& literal_uses
< threshold
&&
3103 (current_literal
.isUndefined() ||
3104 (current_literal
.size() == literal
.size() &&
3105 current_literal
.constantValue() == literal
.constantValue()))) {
3106 /* mark the literal to be applied */
3108 unsigned i
= u_bit_scan(&mask
);
3109 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
3110 ctx
.uses
[instr
->operands
[i
].tempId()]--;
3116 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
3118 /* Cleanup Dead Instructions */
3122 /* apply literals on MAD */
3123 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
3124 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
3125 if (info
->check_literal
&&
3126 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
3127 aco_ptr
<Instruction
> new_mad
;
3129 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
3130 if (instr
->opcode
== aco_opcode::v_fma_f32
)
3131 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
3132 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
3133 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
3134 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
3135 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
3137 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
3138 if (info
->literal_idx
== 2) { /* add literal -> madak */
3139 new_mad
->operands
[0] = instr
->operands
[0];
3140 new_mad
->operands
[1] = instr
->operands
[1];
3141 } else { /* mul literal -> madmk */
3142 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
3143 new_mad
->operands
[1] = instr
->operands
[2];
3145 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
3146 new_mad
->definitions
[0] = instr
->definitions
[0];
3147 ctx
.instructions
.emplace_back(std::move(new_mad
));
3152 /* apply literals on other SALU/VALU */
3153 if (instr
->isSALU() || instr
->isVALU()) {
3154 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3155 Operand op
= instr
->operands
[i
];
3156 unsigned bits
= get_operand_size(instr
, i
);
3157 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3158 Operand
literal(ctx
.info
[op
.tempId()].val
);
3159 if (instr
->isVALU() && i
> 0)
3160 to_VOP3(ctx
, instr
);
3161 instr
->operands
[i
] = literal
;
3166 ctx
.instructions
.emplace_back(std::move(instr
));
3170 void optimize(Program
* program
)
3173 ctx
.program
= program
;
3174 std::vector
<ssa_info
> info(program
->peekAllocationId());
3175 ctx
.info
= info
.data();
3177 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3178 for (Block
& block
: program
->blocks
) {
3179 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3180 label_instruction(ctx
, block
, instr
);
3183 ctx
.uses
= dead_code_analysis(program
);
3185 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3186 for (Block
& block
: program
->blocks
) {
3187 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3188 combine_instruction(ctx
, block
, instr
);
3191 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3192 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3193 Block
* block
= &(*it
);
3194 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3195 select_instruction(ctx
, *it
);
3198 /* 4. Add literals to instructions */
3199 for (Block
& block
: program
->blocks
) {
3200 ctx
.instructions
.clear();
3201 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3202 apply_literals(ctx
, instr
);
3203 block
.instructions
.swap(ctx
.instructions
);