2 * Copyright © 2018 Valve Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
32 #include "util/half_float.h"
33 #include "util/u_math.h"
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
53 aco_ptr
<Instruction
> add_instr
;
58 mad_info(aco_ptr
<Instruction
> instr
, uint32_t id
)
59 : add_instr(std::move(instr
)), mul_temp_id(id
), check_literal(false) {}
64 label_constant_32bit
= 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
72 label_literal
= 1 << 6,
76 label_omod5
= 1 << 10,
77 label_omod_success
= 1 << 11,
78 label_clamp
= 1 << 12,
79 label_clamp_success
= 1 << 13,
80 label_undefined
= 1 << 14,
83 label_add_sub
= 1 << 17,
84 label_bitwise
= 1 << 18,
85 label_minmax
= 1 << 19,
87 label_uniform_bool
= 1 << 21,
88 label_constant_64bit
= 1 << 22,
89 label_uniform_bitwise
= 1 << 23,
90 label_scc_invert
= 1 << 24,
91 label_vcc_hint
= 1 << 25,
92 label_scc_needed
= 1 << 26,
94 label_constant_16bit
= 1 << 29,
97 static constexpr uint64_t instr_labels
= label_vec
| label_mul
| label_mad
| label_omod_success
| label_clamp_success
|
98 label_add_sub
| label_bitwise
| label_uniform_bitwise
| label_minmax
| label_vopc
;
99 static constexpr uint64_t temp_labels
= label_abs
| label_neg
| label_temp
| label_vcc
| label_b2f
| label_uniform_bool
|
100 label_omod2
| label_omod4
| label_omod5
| label_clamp
| label_scc_invert
| label_b2i
;
101 static constexpr uint32_t val_labels
= label_constant_32bit
| label_constant_64bit
| label_constant_16bit
| label_literal
;
111 ssa_info() : label(0) {}
113 void add_label(Label new_label
)
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label
& instr_labels
)
119 label
&= ~(temp_labels
| val_labels
); /* instr, temp and val alias */
121 if (new_label
& temp_labels
) {
122 label
&= ~temp_labels
;
123 label
&= ~(instr_labels
| val_labels
); /* instr, temp and val alias */
126 uint32_t const_labels
= label_literal
| label_constant_32bit
| label_constant_64bit
| label_constant_16bit
;
127 if (new_label
& const_labels
) {
128 label
&= ~val_labels
| const_labels
;
129 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
130 } else if (new_label
& val_labels
) {
131 label
&= ~val_labels
;
132 label
&= ~(instr_labels
| temp_labels
); /* instr, temp and val alias */
138 void set_vec(Instruction
* vec
)
140 add_label(label_vec
);
146 return label
& label_vec
;
149 void set_constant(chip_class chip
, uint64_t constant
)
151 Operand
op16((uint16_t)constant
);
152 Operand
op32((uint32_t)constant
);
153 add_label(label_literal
);
156 if (chip
>= GFX8
&& !op16
.isLiteral())
157 add_label(label_constant_16bit
);
159 if (!op32
.isLiteral() || ((uint32_t)constant
== 0x3e22f983 && chip
>= GFX8
))
160 add_label(label_constant_32bit
);
162 if (constant
<= 64) {
163 add_label(label_constant_64bit
);
164 } else if (constant
>= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
165 add_label(label_constant_64bit
);
166 } else if (constant
== 0x3FE0000000000000) { /* 0.5 */
167 add_label(label_constant_64bit
);
168 } else if (constant
== 0xBFE0000000000000) { /* -0.5 */
169 add_label(label_constant_64bit
);
170 } else if (constant
== 0x3FF0000000000000) { /* 1.0 */
171 add_label(label_constant_64bit
);
172 } else if (constant
== 0xBFF0000000000000) { /* -1.0 */
173 add_label(label_constant_64bit
);
174 } else if (constant
== 0x4000000000000000) { /* 2.0 */
175 add_label(label_constant_64bit
);
176 } else if (constant
== 0xC000000000000000) { /* -2.0 */
177 add_label(label_constant_64bit
);
178 } else if (constant
== 0x4010000000000000) { /* 4.0 */
179 add_label(label_constant_64bit
);
180 } else if (constant
== 0xC010000000000000) { /* -4.0 */
181 add_label(label_constant_64bit
);
184 if (label
& label_constant_64bit
) {
185 val
= Operand(constant
).constantValue();
187 label
&= ~(label_literal
| label_constant_16bit
| label_constant_32bit
);
191 bool is_constant(unsigned bits
)
195 return label
& label_literal
;
197 return label
& label_constant_16bit
;
199 return label
& label_constant_32bit
;
201 return label
& label_constant_64bit
;
206 bool is_literal(unsigned bits
)
208 bool is_lit
= label
& label_literal
;
213 return is_lit
&& ~(label
& label_constant_16bit
);
215 return is_lit
&& ~(label
& label_constant_32bit
);
222 bool is_constant_or_literal(unsigned bits
)
225 return label
& label_constant_64bit
;
227 return label
& label_literal
;
230 void set_abs(Temp abs_temp
)
232 add_label(label_abs
);
238 return label
& label_abs
;
241 void set_neg(Temp neg_temp
)
243 add_label(label_neg
);
249 return label
& label_neg
;
252 void set_neg_abs(Temp neg_abs_temp
)
254 add_label((Label
)((uint32_t)label_abs
| (uint32_t)label_neg
));
258 void set_mul(Instruction
* mul
)
260 add_label(label_mul
);
266 return label
& label_mul
;
269 void set_temp(Temp tmp
)
271 add_label(label_temp
);
277 return label
& label_temp
;
280 void set_mad(Instruction
* mad
, uint32_t mad_info_idx
)
282 add_label(label_mad
);
283 mad
->pass_flags
= mad_info_idx
;
289 return label
& label_mad
;
292 void set_omod2(Temp def
)
294 add_label(label_omod2
);
300 return label
& label_omod2
;
303 void set_omod4(Temp def
)
305 add_label(label_omod4
);
311 return label
& label_omod4
;
314 void set_omod5(Temp def
)
316 add_label(label_omod5
);
322 return label
& label_omod5
;
325 void set_omod_success(Instruction
* omod_instr
)
327 add_label(label_omod_success
);
331 bool is_omod_success()
333 return label
& label_omod_success
;
336 void set_clamp(Temp def
)
338 add_label(label_clamp
);
344 return label
& label_clamp
;
347 void set_clamp_success(Instruction
* clamp_instr
)
349 add_label(label_clamp_success
);
353 bool is_clamp_success()
355 return label
& label_clamp_success
;
360 add_label(label_undefined
);
365 return label
& label_undefined
;
368 void set_vcc(Temp vcc
)
370 add_label(label_vcc
);
376 return label
& label_vcc
;
379 void set_b2f(Temp val
)
381 add_label(label_b2f
);
387 return label
& label_b2f
;
390 void set_add_sub(Instruction
*add_sub_instr
)
392 add_label(label_add_sub
);
393 instr
= add_sub_instr
;
398 return label
& label_add_sub
;
401 void set_bitwise(Instruction
*bitwise_instr
)
403 add_label(label_bitwise
);
404 instr
= bitwise_instr
;
409 return label
& label_bitwise
;
412 void set_uniform_bitwise()
414 add_label(label_uniform_bitwise
);
417 bool is_uniform_bitwise()
419 return label
& label_uniform_bitwise
;
422 void set_minmax(Instruction
*minmax_instr
)
424 add_label(label_minmax
);
425 instr
= minmax_instr
;
430 return label
& label_minmax
;
433 void set_vopc(Instruction
*vopc_instr
)
435 add_label(label_vopc
);
441 return label
& label_vopc
;
444 void set_scc_needed()
446 add_label(label_scc_needed
);
451 return label
& label_scc_needed
;
454 void set_scc_invert(Temp scc_inv
)
456 add_label(label_scc_invert
);
462 return label
& label_scc_invert
;
465 void set_uniform_bool(Temp uniform_bool
)
467 add_label(label_uniform_bool
);
471 bool is_uniform_bool()
473 return label
& label_uniform_bool
;
478 add_label(label_vcc_hint
);
483 return label
& label_vcc_hint
;
486 void set_b2i(Temp val
)
488 add_label(label_b2i
);
494 return label
& label_b2i
;
501 std::vector
<aco_ptr
<Instruction
>> instructions
;
503 std::pair
<uint32_t,Temp
> last_literal
;
504 std::vector
<mad_info
> mad_infos
;
505 std::vector
<uint16_t> uses
;
510 aco_opcode unordered
;
511 aco_opcode ordered_swapped
;
512 aco_opcode unordered_swapped
;
518 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
);
520 bool can_swap_operands(aco_ptr
<Instruction
>& instr
)
522 if (instr
->operands
[0].isConstant() ||
523 (instr
->operands
[0].isTemp() && instr
->operands
[0].getTemp().type() == RegType::sgpr
))
526 switch (instr
->opcode
) {
527 case aco_opcode::v_add_u32
:
528 case aco_opcode::v_add_co_u32
:
529 case aco_opcode::v_add_co_u32_e64
:
530 case aco_opcode::v_add_i32
:
531 case aco_opcode::v_add_f16
:
532 case aco_opcode::v_add_f32
:
533 case aco_opcode::v_mul_f16
:
534 case aco_opcode::v_mul_f32
:
535 case aco_opcode::v_or_b32
:
536 case aco_opcode::v_and_b32
:
537 case aco_opcode::v_xor_b32
:
538 case aco_opcode::v_max_f16
:
539 case aco_opcode::v_max_f32
:
540 case aco_opcode::v_min_f16
:
541 case aco_opcode::v_min_f32
:
542 case aco_opcode::v_max_i32
:
543 case aco_opcode::v_min_i32
:
544 case aco_opcode::v_max_u32
:
545 case aco_opcode::v_min_u32
:
546 case aco_opcode::v_max_i16
:
547 case aco_opcode::v_min_i16
:
548 case aco_opcode::v_max_u16
:
549 case aco_opcode::v_min_u16
:
550 case aco_opcode::v_max_i16_e64
:
551 case aco_opcode::v_min_i16_e64
:
552 case aco_opcode::v_max_u16_e64
:
553 case aco_opcode::v_min_u16_e64
:
555 case aco_opcode::v_sub_f16
:
556 instr
->opcode
= aco_opcode::v_subrev_f16
;
558 case aco_opcode::v_sub_f32
:
559 instr
->opcode
= aco_opcode::v_subrev_f32
;
561 case aco_opcode::v_sub_co_u32
:
562 instr
->opcode
= aco_opcode::v_subrev_co_u32
;
564 case aco_opcode::v_sub_u16
:
565 instr
->opcode
= aco_opcode::v_subrev_u16
;
567 case aco_opcode::v_sub_u32
:
568 instr
->opcode
= aco_opcode::v_subrev_u32
;
572 get_cmp_info(instr
->opcode
, &info
);
573 if (info
.ordered
== instr
->opcode
) {
574 instr
->opcode
= info
.ordered_swapped
;
577 if (info
.unordered
== instr
->opcode
) {
578 instr
->opcode
= info
.unordered_swapped
;
586 bool can_use_VOP3(opt_ctx
& ctx
, const aco_ptr
<Instruction
>& instr
)
591 if (instr
->operands
.size() && instr
->operands
[0].isLiteral() && ctx
.program
->chip_class
< GFX10
)
594 if (instr
->isDPP() || instr
->isSDWA())
597 return instr
->opcode
!= aco_opcode::v_madmk_f32
&&
598 instr
->opcode
!= aco_opcode::v_madak_f32
&&
599 instr
->opcode
!= aco_opcode::v_madmk_f16
&&
600 instr
->opcode
!= aco_opcode::v_madak_f16
&&
601 instr
->opcode
!= aco_opcode::v_fmamk_f32
&&
602 instr
->opcode
!= aco_opcode::v_fmaak_f32
&&
603 instr
->opcode
!= aco_opcode::v_fmamk_f16
&&
604 instr
->opcode
!= aco_opcode::v_fmaak_f16
&&
605 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
606 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
607 instr
->opcode
!= aco_opcode::v_readfirstlane_b32
;
610 bool can_apply_sgprs(aco_ptr
<Instruction
>& instr
)
612 return instr
->opcode
!= aco_opcode::v_readfirstlane_b32
&&
613 instr
->opcode
!= aco_opcode::v_readlane_b32
&&
614 instr
->opcode
!= aco_opcode::v_readlane_b32_e64
&&
615 instr
->opcode
!= aco_opcode::v_writelane_b32
&&
616 instr
->opcode
!= aco_opcode::v_writelane_b32_e64
;
619 void to_VOP3(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
624 aco_ptr
<Instruction
> tmp
= std::move(instr
);
625 Format format
= asVOP3(tmp
->format
);
626 instr
.reset(create_instruction
<VOP3A_instruction
>(tmp
->opcode
, format
, tmp
->operands
.size(), tmp
->definitions
.size()));
627 std::copy(tmp
->operands
.cbegin(), tmp
->operands
.cend(), instr
->operands
.begin());
628 for (unsigned i
= 0; i
< instr
->definitions
.size(); i
++) {
629 instr
->definitions
[i
] = tmp
->definitions
[i
];
630 if (instr
->definitions
[i
].isTemp()) {
631 ssa_info
& info
= ctx
.info
[instr
->definitions
[i
].tempId()];
632 if (info
.label
& instr_labels
&& info
.instr
== tmp
.get())
633 info
.instr
= instr
.get();
638 /* only covers special cases */
639 bool alu_can_accept_constant(aco_opcode opcode
, unsigned operand
)
642 case aco_opcode::v_interp_p2_f32
:
643 case aco_opcode::v_mac_f32
:
644 case aco_opcode::v_writelane_b32
:
645 case aco_opcode::v_writelane_b32_e64
:
646 case aco_opcode::v_cndmask_b32
:
648 case aco_opcode::s_addk_i32
:
649 case aco_opcode::s_mulk_i32
:
650 case aco_opcode::p_wqm
:
651 case aco_opcode::p_extract_vector
:
652 case aco_opcode::p_split_vector
:
653 case aco_opcode::v_readlane_b32
:
654 case aco_opcode::v_readlane_b32_e64
:
655 case aco_opcode::v_readfirstlane_b32
:
662 bool valu_can_accept_vgpr(aco_ptr
<Instruction
>& instr
, unsigned operand
)
664 if (instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_readlane_b32_e64
||
665 instr
->opcode
== aco_opcode::v_writelane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32_e64
)
670 /* check constant bus and literal limitations */
671 bool check_vop3_operands(opt_ctx
& ctx
, unsigned num_operands
, Operand
*operands
)
673 int limit
= ctx
.program
->chip_class
>= GFX10
? 2 : 1;
674 Operand
literal32(s1
);
675 Operand
literal64(s2
);
676 unsigned num_sgprs
= 0;
677 unsigned sgpr
[] = {0, 0};
679 for (unsigned i
= 0; i
< num_operands
; i
++) {
680 Operand op
= operands
[i
];
682 if (op
.hasRegClass() && op
.regClass().type() == RegType::sgpr
) {
683 /* two reads of the same SGPR count as 1 to the limit */
684 if (op
.tempId() != sgpr
[0] && op
.tempId() != sgpr
[1]) {
686 sgpr
[num_sgprs
++] = op
.tempId();
691 } else if (op
.isLiteral()) {
692 if (ctx
.program
->chip_class
< GFX10
)
695 if (!literal32
.isUndefined() && literal32
.constantValue() != op
.constantValue())
697 if (!literal64
.isUndefined() && literal64
.constantValue() != op
.constantValue())
700 /* Any number of 32-bit literals counts as only 1 to the limit. Same
701 * (but separately) for 64-bit literals. */
702 if (op
.size() == 1 && literal32
.isUndefined()) {
705 } else if (op
.size() == 2 && literal64
.isUndefined()) {
718 bool parse_base_offset(opt_ctx
&ctx
, Instruction
* instr
, unsigned op_index
, Temp
*base
, uint32_t *offset
)
720 Operand op
= instr
->operands
[op_index
];
724 Temp tmp
= op
.getTemp();
725 if (!ctx
.info
[tmp
.id()].is_add_sub())
728 Instruction
*add_instr
= ctx
.info
[tmp
.id()].instr
;
730 switch (add_instr
->opcode
) {
731 case aco_opcode::v_add_u32
:
732 case aco_opcode::v_add_co_u32
:
733 case aco_opcode::v_add_co_u32_e64
:
734 case aco_opcode::s_add_i32
:
735 case aco_opcode::s_add_u32
:
741 if (add_instr
->usesModifiers())
744 for (unsigned i
= 0; i
< 2; i
++) {
745 if (add_instr
->operands
[i
].isConstant()) {
746 *offset
= add_instr
->operands
[i
].constantValue();
747 } else if (add_instr
->operands
[i
].isTemp() &&
748 ctx
.info
[add_instr
->operands
[i
].tempId()].is_constant_or_literal(32)) {
749 *offset
= ctx
.info
[add_instr
->operands
[i
].tempId()].val
;
753 if (!add_instr
->operands
[!i
].isTemp())
756 uint32_t offset2
= 0;
757 if (parse_base_offset(ctx
, add_instr
, !i
, base
, &offset2
)) {
760 *base
= add_instr
->operands
[!i
].getTemp();
768 unsigned get_operand_size(aco_ptr
<Instruction
>& instr
, unsigned index
)
770 if (instr
->format
== Format::PSEUDO
)
771 return instr
->operands
[index
].bytes() * 8u;
772 else if (instr
->opcode
== aco_opcode::v_mad_u64_u32
|| instr
->opcode
== aco_opcode::v_mad_i64_i32
)
773 return index
== 2 ? 64 : 32;
774 else if (instr
->isVALU() || instr
->isSALU())
775 return instr_info
.operand_size
[(int)instr
->opcode
];
780 Operand
get_constant_op(opt_ctx
&ctx
, ssa_info info
, uint32_t bits
)
783 return Operand((uint8_t)info
.val
);
785 return Operand((uint16_t)info
.val
);
786 // TODO: this functions shouldn't be needed if we store Operand instead of value.
787 Operand
op(info
.val
, bits
== 64);
788 if (info
.is_literal(32) && info
.val
== 0x3e22f983 && ctx
.program
->chip_class
>= GFX8
)
789 op
.setFixed(PhysReg
{248}); /* 1/2 PI can be an inline constant on GFX8+ */
793 bool fixed_to_exec(Operand op
)
795 return op
.isFixed() && op
.physReg() == exec
;
798 void label_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
800 if (instr
->isSALU() || instr
->isVALU() || instr
->format
== Format::PSEUDO
) {
801 ASSERTED
bool all_const
= false;
802 for (Operand
& op
: instr
->operands
)
803 all_const
= all_const
&& (!op
.isTemp() || ctx
.info
[op
.tempId()].is_constant_or_literal(32));
804 perfwarn(all_const
, "All instruction operands are constant", instr
.get());
807 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
809 if (!instr
->operands
[i
].isTemp())
812 ssa_info info
= ctx
.info
[instr
->operands
[i
].tempId()];
813 /* propagate undef */
814 if (info
.is_undefined() && is_phi(instr
))
815 instr
->operands
[i
] = Operand(instr
->operands
[i
].regClass());
816 /* propagate reg->reg of same type */
817 if (info
.is_temp() && info
.temp
.regClass() == instr
->operands
[i
].getTemp().regClass()) {
818 instr
->operands
[i
].setTemp(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
819 info
= ctx
.info
[info
.temp
.id()];
822 /* SALU / PSEUDO: propagate inline constants */
823 if (instr
->isSALU() || instr
->format
== Format::PSEUDO
) {
824 bool is_subdword
= false;
825 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
826 if (instr
->format
== Format::PSEUDO
) {
827 is_subdword
= std::any_of(instr
->definitions
.begin(), instr
->definitions
.end(),
828 [] (const Definition
& def
) { return def
.regClass().is_subdword();});
829 is_subdword
= is_subdword
|| std::any_of(instr
->operands
.begin(), instr
->operands
.end(),
830 [] (const Operand
& op
) { return op
.hasRegClass() && op
.regClass().is_subdword();});
831 if (is_subdword
&& ctx
.program
->chip_class
< GFX9
)
835 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
) {
836 instr
->operands
[i
].setTemp(info
.temp
);
837 info
= ctx
.info
[info
.temp
.id()];
838 } else if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
) {
839 /* propagate vgpr if it can take it */
840 switch (instr
->opcode
) {
841 case aco_opcode::p_create_vector
:
842 case aco_opcode::p_split_vector
:
843 case aco_opcode::p_extract_vector
:
844 case aco_opcode::p_phi
: {
845 const bool all_vgpr
= std::none_of(instr
->definitions
.begin(), instr
->definitions
.end(),
846 [] (const Definition
& def
) { return def
.getTemp().type() != RegType::vgpr
;});
848 instr
->operands
[i
] = Operand(info
.temp
);
849 info
= ctx
.info
[info
.temp
.id()];
857 unsigned bits
= get_operand_size(instr
, i
);
858 if ((info
.is_constant(bits
) || (!is_subdword
&& info
.is_literal(bits
) && instr
->format
== Format::PSEUDO
)) &&
859 !instr
->operands
[i
].isFixed() && alu_can_accept_constant(instr
->opcode
, i
)) {
860 instr
->operands
[i
] = get_constant_op(ctx
, info
, bits
);
865 /* VALU: propagate neg, abs & inline constants */
866 else if (instr
->isVALU()) {
867 if (info
.is_temp() && info
.temp
.type() == RegType::vgpr
&& valu_can_accept_vgpr(instr
, i
)) {
868 instr
->operands
[i
].setTemp(info
.temp
);
869 info
= ctx
.info
[info
.temp
.id()];
872 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
873 unsigned can_use_mod
= instr
->opcode
!= aco_opcode::v_cndmask_b32
|| instr
->operands
[i
].getTemp().bytes() == 4;
874 can_use_mod
= can_use_mod
&& instr_info
.can_use_input_modifiers
[(int)instr
->opcode
];
876 if (info
.is_abs() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
879 instr
->operands
[i
] = Operand(info
.temp
);
881 static_cast<DPP_instruction
*>(instr
.get())->abs
[i
] = true;
883 static_cast<VOP3A_instruction
*>(instr
.get())->abs
[i
] = true;
885 if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f32
) {
886 instr
->opcode
= i
? aco_opcode::v_sub_f32
: aco_opcode::v_subrev_f32
;
887 instr
->operands
[i
].setTemp(info
.temp
);
889 } else if (info
.is_neg() && instr
->opcode
== aco_opcode::v_add_f16
) {
890 instr
->opcode
= i
? aco_opcode::v_sub_f16
: aco_opcode::v_subrev_f16
;
891 instr
->operands
[i
].setTemp(info
.temp
);
893 } else if (info
.is_neg() && (can_use_VOP3(ctx
, instr
) || instr
->isDPP()) && can_use_mod
) {
896 instr
->operands
[i
].setTemp(info
.temp
);
898 static_cast<DPP_instruction
*>(instr
.get())->neg
[i
] = true;
900 static_cast<VOP3A_instruction
*>(instr
.get())->neg
[i
] = true;
903 unsigned bits
= get_operand_size(instr
, i
);
904 if (info
.is_constant(bits
) && alu_can_accept_constant(instr
->opcode
, i
)) {
905 Operand op
= get_constant_op(ctx
, info
, bits
);
906 perfwarn(instr
->opcode
== aco_opcode::v_cndmask_b32
&& i
== 2, "v_cndmask_b32 with a constant selector", instr
.get());
907 if (i
== 0 || instr
->opcode
== aco_opcode::v_readlane_b32
|| instr
->opcode
== aco_opcode::v_writelane_b32
) {
908 instr
->operands
[i
] = op
;
910 } else if (!instr
->isVOP3() && can_swap_operands(instr
)) {
911 instr
->operands
[i
] = instr
->operands
[0];
912 instr
->operands
[0] = op
;
914 } else if (can_use_VOP3(ctx
, instr
)) {
916 instr
->operands
[i
] = op
;
922 /* MUBUF: propagate constants and combine additions */
923 else if (instr
->format
== Format::MUBUF
) {
924 MUBUF_instruction
*mubuf
= static_cast<MUBUF_instruction
*>(instr
.get());
927 while (info
.is_temp())
928 info
= ctx
.info
[info
.temp
.id()];
930 if (mubuf
->offen
&& i
== 1 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
931 assert(!mubuf
->idxen
);
932 instr
->operands
[1] = Operand(v1
);
933 mubuf
->offset
+= info
.val
;
934 mubuf
->offen
= false;
936 } else if (i
== 2 && info
.is_constant_or_literal(32) && mubuf
->offset
+ info
.val
< 4096) {
937 instr
->operands
[2] = Operand((uint32_t) 0);
938 mubuf
->offset
+= info
.val
;
940 } else if (mubuf
->offen
&& i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == v1
&& mubuf
->offset
+ offset
< 4096) {
941 assert(!mubuf
->idxen
);
942 instr
->operands
[1].setTemp(base
);
943 mubuf
->offset
+= offset
;
945 } else if (i
== 2 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& mubuf
->offset
+ offset
< 4096) {
946 instr
->operands
[i
].setTemp(base
);
947 mubuf
->offset
+= offset
;
952 /* DS: combine additions */
953 else if (instr
->format
== Format::DS
) {
955 DS_instruction
*ds
= static_cast<DS_instruction
*>(instr
.get());
958 bool has_usable_ds_offset
= ctx
.program
->chip_class
>= GFX7
;
959 if (has_usable_ds_offset
&&
960 i
== 0 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) &&
961 base
.regClass() == instr
->operands
[i
].regClass() &&
962 instr
->opcode
!= aco_opcode::ds_swizzle_b32
) {
963 if (instr
->opcode
== aco_opcode::ds_write2_b32
|| instr
->opcode
== aco_opcode::ds_read2_b32
||
964 instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) {
965 unsigned mask
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 0x7 : 0x3;
966 unsigned shifts
= (instr
->opcode
== aco_opcode::ds_write2_b64
|| instr
->opcode
== aco_opcode::ds_read2_b64
) ? 3 : 2;
968 if ((offset
& mask
) == 0 &&
969 ds
->offset0
+ (offset
>> shifts
) <= 255 &&
970 ds
->offset1
+ (offset
>> shifts
) <= 255) {
971 instr
->operands
[i
].setTemp(base
);
972 ds
->offset0
+= offset
>> shifts
;
973 ds
->offset1
+= offset
>> shifts
;
976 if (ds
->offset0
+ offset
<= 65535) {
977 instr
->operands
[i
].setTemp(base
);
978 ds
->offset0
+= offset
;
984 /* SMEM: propagate constants and combine additions */
985 else if (instr
->format
== Format::SMEM
) {
987 SMEM_instruction
*smem
= static_cast<SMEM_instruction
*>(instr
.get());
990 if (i
== 1 && info
.is_constant_or_literal(32) &&
991 ((ctx
.program
->chip_class
== GFX6
&& info
.val
<= 0x3FF) ||
992 (ctx
.program
->chip_class
== GFX7
&& info
.val
<= 0xFFFFFFFF) ||
993 (ctx
.program
->chip_class
>= GFX8
&& info
.val
<= 0xFFFFF))) {
994 instr
->operands
[i
] = Operand(info
.val
);
996 } else if (i
== 1 && parse_base_offset(ctx
, instr
.get(), i
, &base
, &offset
) && base
.regClass() == s1
&& offset
<= 0xFFFFF && ctx
.program
->chip_class
>= GFX9
) {
997 bool soe
= smem
->operands
.size() >= (!smem
->definitions
.empty() ? 3 : 4);
999 (!ctx
.info
[smem
->operands
.back().tempId()].is_constant_or_literal(32) ||
1000 ctx
.info
[smem
->operands
.back().tempId()].val
!= 0)) {
1004 smem
->operands
[1] = Operand(offset
);
1005 smem
->operands
.back() = Operand(base
);
1007 SMEM_instruction
*new_instr
= create_instruction
<SMEM_instruction
>(smem
->opcode
, Format::SMEM
, smem
->operands
.size() + 1, smem
->definitions
.size());
1008 new_instr
->operands
[0] = smem
->operands
[0];
1009 new_instr
->operands
[1] = Operand(offset
);
1010 if (smem
->definitions
.empty())
1011 new_instr
->operands
[2] = smem
->operands
[2];
1012 new_instr
->operands
.back() = Operand(base
);
1013 if (!smem
->definitions
.empty())
1014 new_instr
->definitions
[0] = smem
->definitions
[0];
1015 new_instr
->can_reorder
= smem
->can_reorder
;
1016 new_instr
->barrier
= smem
->barrier
;
1017 new_instr
->glc
= smem
->glc
;
1018 new_instr
->dlc
= smem
->dlc
;
1019 new_instr
->nv
= smem
->nv
;
1020 new_instr
->disable_wqm
= smem
->disable_wqm
;
1021 instr
.reset(new_instr
);
1022 smem
= static_cast<SMEM_instruction
*>(instr
.get());
1028 else if (instr
->format
== Format::PSEUDO_BRANCH
) {
1029 if (ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1030 /* Flip the branch instruction to get rid of the scc_invert instruction */
1031 instr
->opcode
= instr
->opcode
== aco_opcode::p_cbranch_z
? aco_opcode::p_cbranch_nz
: aco_opcode::p_cbranch_z
;
1032 instr
->operands
[0].setTemp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1037 /* if this instruction doesn't define anything, return */
1038 if (instr
->definitions
.empty())
1041 if ((uint16_t) instr
->format
& (uint16_t) Format::VOPC
) {
1042 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(instr
.get());
1046 switch (instr
->opcode
) {
1047 case aco_opcode::p_create_vector
: {
1048 bool copy_prop
= instr
->operands
.size() == 1 && instr
->operands
[0].isTemp() &&
1049 instr
->operands
[0].regClass() == instr
->definitions
[0].regClass();
1051 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1055 unsigned num_ops
= instr
->operands
.size();
1056 for (const Operand
& op
: instr
->operands
) {
1057 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_vec())
1058 num_ops
+= ctx
.info
[op
.tempId()].instr
->operands
.size() - 1;
1060 if (num_ops
!= instr
->operands
.size()) {
1061 aco_ptr
<Instruction
> old_vec
= std::move(instr
);
1062 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_ops
, 1));
1063 instr
->definitions
[0] = old_vec
->definitions
[0];
1065 for (Operand
& old_op
: old_vec
->operands
) {
1066 if (old_op
.isTemp() && ctx
.info
[old_op
.tempId()].is_vec()) {
1067 for (unsigned j
= 0; j
< ctx
.info
[old_op
.tempId()].instr
->operands
.size(); j
++) {
1068 Operand op
= ctx
.info
[old_op
.tempId()].instr
->operands
[j
];
1069 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_temp() &&
1070 ctx
.info
[op
.tempId()].temp
.type() == instr
->definitions
[0].regClass().type())
1071 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
1072 instr
->operands
[k
++] = op
;
1075 instr
->operands
[k
++] = old_op
;
1078 assert(k
== num_ops
);
1081 ctx
.info
[instr
->definitions
[0].tempId()].set_vec(instr
.get());
1084 case aco_opcode::p_split_vector
: {
1085 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1087 if (info
.is_constant_or_literal(32)) {
1088 uint32_t val
= info
.val
;
1089 for (Definition def
: instr
->definitions
) {
1090 uint32_t mask
= u_bit_consecutive(0, def
.bytes() * 8u);
1091 ctx
.info
[def
.tempId()].set_constant(ctx
.program
->chip_class
, val
& mask
);
1092 val
>>= def
.bytes() * 8u;
1095 } else if (!info
.is_vec()) {
1099 Instruction
* vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1100 unsigned split_offset
= 0;
1101 unsigned vec_offset
= 0;
1102 unsigned vec_index
= 0;
1103 for (unsigned i
= 0; i
< instr
->definitions
.size(); split_offset
+= instr
->definitions
[i
++].bytes()) {
1104 while (vec_offset
< split_offset
&& vec_index
< vec
->operands
.size())
1105 vec_offset
+= vec
->operands
[vec_index
++].bytes();
1107 if (vec_offset
!= split_offset
|| vec
->operands
[vec_index
].bytes() != instr
->definitions
[i
].bytes())
1110 Operand vec_op
= vec
->operands
[vec_index
];
1111 if (vec_op
.isConstant()) {
1112 ctx
.info
[instr
->definitions
[i
].tempId()].set_constant(ctx
.program
->chip_class
, vec_op
.constantValue64());
1113 } else if (vec_op
.isUndefined()) {
1114 ctx
.info
[instr
->definitions
[i
].tempId()].set_undefined();
1116 assert(vec_op
.isTemp());
1117 ctx
.info
[instr
->definitions
[i
].tempId()].set_temp(vec_op
.getTemp());
1122 case aco_opcode::p_extract_vector
: { /* mov */
1123 ssa_info
& info
= ctx
.info
[instr
->operands
[0].tempId()];
1124 const unsigned index
= instr
->operands
[1].constantValue();
1125 const unsigned dst_offset
= index
* instr
->definitions
[0].bytes();
1127 if (info
.is_constant_or_literal(32)) {
1128 uint32_t mask
= u_bit_consecutive(0, instr
->definitions
[0].bytes() * 8u);
1129 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, (info
.val
>> (dst_offset
* 8u)) & mask
);
1131 } else if (!info
.is_vec()) {
1135 /* check if we index directly into a vector element */
1136 Instruction
* vec
= info
.instr
;
1137 unsigned offset
= 0;
1139 for (const Operand
& op
: vec
->operands
) {
1140 if (offset
< dst_offset
) {
1141 offset
+= op
.bytes();
1143 } else if (offset
!= dst_offset
|| op
.bytes() != instr
->definitions
[0].bytes()) {
1147 /* convert this extract into a copy instruction */
1148 instr
->opcode
= aco_opcode::p_parallelcopy
;
1149 instr
->operands
.pop_back();
1150 instr
->operands
[0] = op
;
1152 if (op
.isConstant()) {
1153 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, op
.constantValue64());
1154 } else if (op
.isUndefined()) {
1155 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1157 assert(op
.isTemp());
1158 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(op
.getTemp());
1164 case aco_opcode::s_mov_b32
: /* propagate */
1165 case aco_opcode::s_mov_b64
:
1166 case aco_opcode::v_mov_b32
:
1167 case aco_opcode::p_as_uniform
:
1168 if (instr
->definitions
[0].isFixed()) {
1169 /* don't copy-propagate copies into fixed registers */
1170 } else if (instr
->usesModifiers()) {
1172 } else if (instr
->operands
[0].isConstant()) {
1173 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, instr
->operands
[0].constantValue64());
1174 } else if (instr
->operands
[0].isTemp()) {
1175 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1177 assert(instr
->operands
[0].isFixed());
1180 case aco_opcode::p_is_helper
:
1181 if (!ctx
.program
->needs_wqm
)
1182 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, 0u);
1184 case aco_opcode::s_movk_i32
: {
1185 uint32_t v
= static_cast<SOPK_instruction
*>(instr
.get())->imm
;
1186 v
= v
& 0x8000 ? (v
| 0xffff0000) : v
;
1187 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1190 case aco_opcode::v_bfrev_b32
:
1191 case aco_opcode::s_brev_b32
: {
1192 if (instr
->operands
[0].isConstant()) {
1193 uint32_t v
= util_bitreverse(instr
->operands
[0].constantValue());
1194 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1198 case aco_opcode::s_bfm_b32
: {
1199 if (instr
->operands
[0].isConstant() && instr
->operands
[1].isConstant()) {
1200 unsigned size
= instr
->operands
[0].constantValue() & 0x1f;
1201 unsigned start
= instr
->operands
[1].constantValue() & 0x1f;
1202 uint32_t v
= ((1u << size
) - 1u) << start
;
1203 ctx
.info
[instr
->definitions
[0].tempId()].set_constant(ctx
.program
->chip_class
, v
);
1207 case aco_opcode::v_mul_f16
:
1208 case aco_opcode::v_mul_f32
: { /* omod */
1209 /* TODO: try to move the negate/abs modifier to the consumer instead */
1210 if (instr
->usesModifiers())
1213 bool fp16
= instr
->opcode
== aco_opcode::v_mul_f16
;
1215 for (unsigned i
= 0; i
< 2; i
++) {
1216 if (instr
->operands
[!i
].isConstant() && instr
->operands
[i
].isTemp()) {
1217 if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4000 : 0x40000000)) { /* 2.0 */
1218 ctx
.info
[instr
->operands
[i
].tempId()].set_omod2(instr
->definitions
[0].getTemp());
1219 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x4400 : 0x40800000)) { /* 4.0 */
1220 ctx
.info
[instr
->operands
[i
].tempId()].set_omod4(instr
->definitions
[0].getTemp());
1221 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0xb800 : 0x3f000000)) { /* 0.5 */
1222 ctx
.info
[instr
->operands
[i
].tempId()].set_omod5(instr
->definitions
[0].getTemp());
1223 } else if (instr
->operands
[!i
].constantValue() == (fp16
? 0x3c00 : 0x3f800000) &&
1224 !(fp16
? block
.fp_mode
.must_flush_denorms16_64
: block
.fp_mode
.must_flush_denorms32
)) { /* 1.0 */
1225 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[i
].getTemp());
1234 case aco_opcode::v_and_b32
: { /* abs */
1235 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1236 instr
->operands
[1].getTemp().type() == RegType::vgpr
&&
1237 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x7FFFFFFFu
)) ||
1238 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x7FFFu
))))
1239 ctx
.info
[instr
->definitions
[0].tempId()].set_abs(instr
->operands
[1].getTemp());
1241 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1244 case aco_opcode::v_xor_b32
: { /* neg */
1245 if (!instr
->usesModifiers() && instr
->operands
[1].isTemp() &&
1246 ((instr
->definitions
[0].bytes() == 4 && instr
->operands
[0].constantEquals(0x80000000u
)) ||
1247 (instr
->definitions
[0].bytes() == 2 && instr
->operands
[0].constantEquals(0x8000u
)))) {
1248 if (ctx
.info
[instr
->operands
[1].tempId()].is_neg()) {
1249 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1250 } else if (instr
->operands
[1].getTemp().type() == RegType::vgpr
) {
1251 if (ctx
.info
[instr
->operands
[1].tempId()].is_abs()) { /* neg(abs(x)) */
1252 instr
->operands
[1].setTemp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1253 instr
->opcode
= aco_opcode::v_or_b32
;
1254 ctx
.info
[instr
->definitions
[0].tempId()].set_neg_abs(instr
->operands
[1].getTemp());
1256 ctx
.info
[instr
->definitions
[0].tempId()].set_neg(instr
->operands
[1].getTemp());
1260 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1264 case aco_opcode::v_med3_f16
:
1265 case aco_opcode::v_med3_f32
: { /* clamp */
1266 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(instr
.get());
1267 if (vop3
->abs
[0] || vop3
->abs
[1] || vop3
->abs
[2] ||
1268 vop3
->neg
[0] || vop3
->neg
[1] || vop3
->neg
[2] ||
1269 vop3
->omod
!= 0 || vop3
->opsel
!= 0)
1273 bool found_zero
= false, found_one
= false;
1274 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
1275 for (unsigned i
= 0; i
< 3; i
++)
1277 if (instr
->operands
[i
].constantEquals(0))
1279 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
1284 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp()) {
1285 ctx
.info
[instr
->operands
[idx
].tempId()].set_clamp(instr
->definitions
[0].getTemp());
1289 case aco_opcode::v_cndmask_b32
:
1290 if (instr
->operands
[0].constantEquals(0) &&
1291 instr
->operands
[1].constantEquals(0xFFFFFFFF))
1292 ctx
.info
[instr
->definitions
[0].tempId()].set_vcc(instr
->operands
[2].getTemp());
1293 else if (instr
->operands
[0].constantEquals(0) &&
1294 instr
->operands
[1].constantEquals(0x3f800000u
))
1295 ctx
.info
[instr
->definitions
[0].tempId()].set_b2f(instr
->operands
[2].getTemp());
1296 else if (instr
->operands
[0].constantEquals(0) &&
1297 instr
->operands
[1].constantEquals(1))
1298 ctx
.info
[instr
->definitions
[0].tempId()].set_b2i(instr
->operands
[2].getTemp());
1300 ctx
.info
[instr
->operands
[2].tempId()].set_vcc_hint();
1302 case aco_opcode::v_cmp_lg_u32
:
1303 if (instr
->format
== Format::VOPC
&& /* don't optimize VOP3 / SDWA / DPP */
1304 instr
->operands
[0].constantEquals(0) &&
1305 instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_vcc())
1306 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(ctx
.info
[instr
->operands
[1].tempId()].temp
);
1308 case aco_opcode::p_phi
:
1309 case aco_opcode::p_linear_phi
: {
1310 /* lower_bool_phis() can create phis like this */
1311 bool all_same_temp
= instr
->operands
[0].isTemp();
1312 /* this check is needed when moving uniform loop counters out of a divergent loop */
1314 all_same_temp
= instr
->definitions
[0].regClass() == instr
->operands
[0].regClass();
1315 for (unsigned i
= 1; all_same_temp
&& (i
< instr
->operands
.size()); i
++) {
1316 if (!instr
->operands
[i
].isTemp() || instr
->operands
[i
].tempId() != instr
->operands
[0].tempId())
1317 all_same_temp
= false;
1319 if (all_same_temp
) {
1320 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1322 bool all_undef
= instr
->operands
[0].isUndefined();
1323 for (unsigned i
= 1; all_undef
&& (i
< instr
->operands
.size()); i
++) {
1324 if (!instr
->operands
[i
].isUndefined())
1328 ctx
.info
[instr
->definitions
[0].tempId()].set_undefined();
1332 case aco_opcode::v_add_u32
:
1333 case aco_opcode::v_add_co_u32
:
1334 case aco_opcode::v_add_co_u32_e64
:
1335 case aco_opcode::s_add_i32
:
1336 case aco_opcode::s_add_u32
:
1337 ctx
.info
[instr
->definitions
[0].tempId()].set_add_sub(instr
.get());
1339 case aco_opcode::s_not_b32
:
1340 case aco_opcode::s_not_b64
:
1341 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1342 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1343 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1344 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1345 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1346 ctx
.info
[instr
->definitions
[1].tempId()].set_scc_invert(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1348 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1350 case aco_opcode::s_and_b32
:
1351 case aco_opcode::s_and_b64
:
1352 if (fixed_to_exec(instr
->operands
[1]) && instr
->operands
[0].isTemp()) {
1353 if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bool()) {
1354 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1355 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1356 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].temp
);
1358 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_uniform_bitwise()) {
1359 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1360 ctx
.info
[instr
->definitions
[1].tempId()].set_temp(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1361 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(ctx
.info
[instr
->operands
[0].tempId()].instr
->definitions
[1].getTemp());
1363 } else if (ctx
.info
[instr
->operands
[0].tempId()].is_vopc()) {
1364 Instruction
* vopc_instr
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
1365 /* Remove superfluous s_and when the VOPC instruction uses the same exec and thus already produces the same result */
1366 if (vopc_instr
->pass_flags
== instr
->pass_flags
) {
1367 assert(instr
->pass_flags
> 0);
1368 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(vopc_instr
->definitions
[0].getTemp());
1374 case aco_opcode::s_or_b32
:
1375 case aco_opcode::s_or_b64
:
1376 case aco_opcode::s_xor_b32
:
1377 case aco_opcode::s_xor_b64
:
1378 if (std::all_of(instr
->operands
.begin(), instr
->operands
.end(), [&ctx
](const Operand
& op
) {
1379 return op
.isTemp() && (ctx
.info
[op
.tempId()].is_uniform_bool() || ctx
.info
[op
.tempId()].is_uniform_bitwise());
1381 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bitwise();
1384 case aco_opcode::s_lshl_b32
:
1385 case aco_opcode::v_or_b32
:
1386 case aco_opcode::v_lshlrev_b32
:
1387 ctx
.info
[instr
->definitions
[0].tempId()].set_bitwise(instr
.get());
1389 case aco_opcode::v_min_f32
:
1390 case aco_opcode::v_min_f16
:
1391 case aco_opcode::v_min_u32
:
1392 case aco_opcode::v_min_i32
:
1393 case aco_opcode::v_min_u16
:
1394 case aco_opcode::v_min_i16
:
1395 case aco_opcode::v_max_f32
:
1396 case aco_opcode::v_max_f16
:
1397 case aco_opcode::v_max_u32
:
1398 case aco_opcode::v_max_i32
:
1399 case aco_opcode::v_max_u16
:
1400 case aco_opcode::v_max_i16
:
1401 ctx
.info
[instr
->definitions
[0].tempId()].set_minmax(instr
.get());
1403 case aco_opcode::s_cselect_b64
:
1404 case aco_opcode::s_cselect_b32
:
1405 if (instr
->operands
[0].constantEquals((unsigned) -1) &&
1406 instr
->operands
[1].constantEquals(0)) {
1407 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1408 ctx
.info
[instr
->definitions
[0].tempId()].set_uniform_bool(instr
->operands
[2].getTemp());
1410 if (instr
->operands
[2].isTemp() && ctx
.info
[instr
->operands
[2].tempId()].is_scc_invert()) {
1411 /* Flip the operands to get rid of the scc_invert instruction */
1412 std::swap(instr
->operands
[0], instr
->operands
[1]);
1413 instr
->operands
[2].setTemp(ctx
.info
[instr
->operands
[2].tempId()].temp
);
1416 case aco_opcode::p_wqm
:
1417 if (instr
->operands
[0].isTemp() &&
1418 ctx
.info
[instr
->operands
[0].tempId()].is_scc_invert()) {
1419 ctx
.info
[instr
->definitions
[0].tempId()].set_temp(instr
->operands
[0].getTemp());
1427 ALWAYS_INLINE
bool get_cmp_info(aco_opcode op
, CmpInfo
*info
)
1429 info
->ordered
= aco_opcode::num_opcodes
;
1430 info
->unordered
= aco_opcode::num_opcodes
;
1431 info
->ordered_swapped
= aco_opcode::num_opcodes
;
1432 info
->unordered_swapped
= aco_opcode::num_opcodes
;
1434 #define CMP2(ord, unord, ord_swap, unord_swap, sz) \
1435 case aco_opcode::v_cmp_##ord##_f##sz:\
1436 case aco_opcode::v_cmp_n##unord##_f##sz:\
1437 info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
1438 info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
1439 info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz;\
1440 info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz;\
1441 info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
1442 info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
1445 #define CMP(ord, unord, ord_swap, unord_swap) \
1446 CMP2(ord, unord, ord_swap, unord_swap, 16)\
1447 CMP2(ord, unord, ord_swap, unord_swap, 32)\
1448 CMP2(ord, unord, ord_swap, unord_swap, 64)
1449 CMP(lt
, /*n*/ge
, gt
, /*n*/le
)
1450 CMP(eq
, /*n*/lg
, eq
, /*n*/lg
)
1451 CMP(le
, /*n*/gt
, ge
, /*n*/lt
)
1452 CMP(gt
, /*n*/le
, lt
, /*n*/le
)
1453 CMP(lg
, /*n*/eq
, lg
, /*n*/eq
)
1454 CMP(ge
, /*n*/lt
, le
, /*n*/gt
)
1457 #define ORD_TEST(sz) \
1458 case aco_opcode::v_cmp_u_f##sz:\
1459 info->f32 = aco_opcode::v_cmp_u_f32;\
1460 info->inverse = aco_opcode::v_cmp_o_f##sz;\
1463 case aco_opcode::v_cmp_o_f##sz:\
1464 info->f32 = aco_opcode::v_cmp_o_f32;\
1465 info->inverse = aco_opcode::v_cmp_u_f##sz;\
1477 aco_opcode
get_ordered(aco_opcode op
)
1480 return get_cmp_info(op
, &info
) ? info
.ordered
: aco_opcode::num_opcodes
;
1483 aco_opcode
get_unordered(aco_opcode op
)
1486 return get_cmp_info(op
, &info
) ? info
.unordered
: aco_opcode::num_opcodes
;
1489 aco_opcode
get_inverse(aco_opcode op
)
1492 return get_cmp_info(op
, &info
) ? info
.inverse
: aco_opcode::num_opcodes
;
1495 aco_opcode
get_f32_cmp(aco_opcode op
)
1498 return get_cmp_info(op
, &info
) ? info
.f32
: aco_opcode::num_opcodes
;
1501 unsigned get_cmp_bitsize(aco_opcode op
)
1504 return get_cmp_info(op
, &info
) ? info
.size
: 0;
1507 bool is_cmp(aco_opcode op
)
1510 return get_cmp_info(op
, &info
) && info
.ordered
!= aco_opcode::num_opcodes
;
1513 unsigned original_temp_id(opt_ctx
&ctx
, Temp tmp
)
1515 if (ctx
.info
[tmp
.id()].is_temp())
1516 return ctx
.info
[tmp
.id()].temp
.id();
1521 void decrease_uses(opt_ctx
&ctx
, Instruction
* instr
)
1523 if (!--ctx
.uses
[instr
->definitions
[0].tempId()]) {
1524 for (const Operand
& op
: instr
->operands
) {
1526 ctx
.uses
[op
.tempId()]--;
1531 Instruction
*follow_operand(opt_ctx
&ctx
, Operand op
, bool ignore_uses
=false)
1533 if (!op
.isTemp() || !(ctx
.info
[op
.tempId()].label
& instr_labels
))
1535 if (!ignore_uses
&& ctx
.uses
[op
.tempId()] > 1)
1538 Instruction
*instr
= ctx
.info
[op
.tempId()].instr
;
1540 if (instr
->definitions
.size() == 2) {
1541 assert(instr
->definitions
[0].isTemp() && instr
->definitions
[0].tempId() == op
.tempId());
1542 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1549 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1550 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1551 bool combine_ordering_test(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1553 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1555 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1558 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1560 bool neg
[2] = {false, false};
1561 bool abs
[2] = {false, false};
1563 Instruction
*op_instr
[2];
1566 unsigned bitsize
= 0;
1567 for (unsigned i
= 0; i
< 2; i
++) {
1568 op_instr
[i
] = follow_operand(ctx
, instr
->operands
[i
], true);
1572 aco_opcode expected_cmp
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1573 unsigned op_bitsize
= get_cmp_bitsize(op_instr
[i
]->opcode
);
1575 if (get_f32_cmp(op_instr
[i
]->opcode
) != expected_cmp
)
1577 if (bitsize
&& op_bitsize
!= bitsize
)
1579 if (!op_instr
[i
]->operands
[0].isTemp() || !op_instr
[i
]->operands
[1].isTemp())
1582 if (op_instr
[i
]->isVOP3()) {
1583 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(op_instr
[i
]);
1584 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1586 neg
[i
] = vop3
->neg
[0];
1587 abs
[i
] = vop3
->abs
[0];
1588 opsel
|= (vop3
->opsel
& 1) << i
;
1591 Temp op0
= op_instr
[i
]->operands
[0].getTemp();
1592 Temp op1
= op_instr
[i
]->operands
[1].getTemp();
1593 if (original_temp_id(ctx
, op0
) != original_temp_id(ctx
, op1
))
1597 bitsize
= op_bitsize
;
1600 if (op
[1].type() == RegType::sgpr
)
1601 std::swap(op
[0], op
[1]);
1602 unsigned num_sgprs
= (op
[0].type() == RegType::sgpr
) + (op
[1].type() == RegType::sgpr
);
1603 if (num_sgprs
> (ctx
.program
->chip_class
>= GFX10
? 2 : 1))
1606 ctx
.uses
[op
[0].id()]++;
1607 ctx
.uses
[op
[1].id()]++;
1608 decrease_uses(ctx
, op_instr
[0]);
1609 decrease_uses(ctx
, op_instr
[1]);
1611 aco_opcode new_op
= aco_opcode::num_opcodes
;
1614 new_op
= is_or
? aco_opcode::v_cmp_u_f16
: aco_opcode::v_cmp_o_f16
;
1617 new_op
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1620 new_op
= is_or
? aco_opcode::v_cmp_u_f64
: aco_opcode::v_cmp_o_f64
;
1623 Instruction
*new_instr
;
1624 if (neg
[0] || neg
[1] || abs
[0] || abs
[1] || opsel
|| num_sgprs
> 1) {
1625 VOP3A_instruction
*vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1626 for (unsigned i
= 0; i
< 2; i
++) {
1627 vop3
->neg
[i
] = neg
[i
];
1628 vop3
->abs
[i
] = abs
[i
];
1630 vop3
->opsel
= opsel
;
1631 new_instr
= static_cast<Instruction
*>(vop3
);
1633 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1635 new_instr
->operands
[0] = Operand(op
[0]);
1636 new_instr
->operands
[1] = Operand(op
[1]);
1637 new_instr
->definitions
[0] = instr
->definitions
[0];
1639 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1640 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1642 instr
.reset(new_instr
);
1647 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1648 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1649 bool combine_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1651 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1653 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1656 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1657 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_u_f32
: aco_opcode::v_cmp_o_f32
;
1659 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1660 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1661 if (!nan_test
|| !cmp
)
1664 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1665 std::swap(nan_test
, cmp
);
1666 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1669 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1672 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1674 if (!cmp
->operands
[0].isTemp() || !cmp
->operands
[1].isTemp())
1677 unsigned prop_cmp0
= original_temp_id(ctx
, cmp
->operands
[0].getTemp());
1678 unsigned prop_cmp1
= original_temp_id(ctx
, cmp
->operands
[1].getTemp());
1679 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1680 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1681 if (prop_cmp0
!= prop_nan0
&& prop_cmp0
!= prop_nan1
)
1683 if (prop_cmp1
!= prop_nan0
&& prop_cmp1
!= prop_nan1
)
1686 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1687 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1688 decrease_uses(ctx
, nan_test
);
1689 decrease_uses(ctx
, cmp
);
1691 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1692 Instruction
*new_instr
;
1693 if (cmp
->isVOP3()) {
1694 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1695 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1696 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1697 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1698 new_vop3
->clamp
= cmp_vop3
->clamp
;
1699 new_vop3
->omod
= cmp_vop3
->omod
;
1700 new_vop3
->opsel
= cmp_vop3
->opsel
;
1701 new_instr
= new_vop3
;
1703 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1705 new_instr
->operands
[0] = cmp
->operands
[0];
1706 new_instr
->operands
[1] = cmp
->operands
[1];
1707 new_instr
->definitions
[0] = instr
->definitions
[0];
1709 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1710 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1712 instr
.reset(new_instr
);
1717 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1718 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1719 bool combine_constant_comparison_ordering(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1721 if (instr
->definitions
[0].regClass() != ctx
.program
->lane_mask
)
1723 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1726 bool is_or
= instr
->opcode
== aco_opcode::s_or_b64
|| instr
->opcode
== aco_opcode::s_or_b32
;
1728 Instruction
*nan_test
= follow_operand(ctx
, instr
->operands
[0], true);
1729 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[1], true);
1731 if (!nan_test
|| !cmp
)
1734 aco_opcode expected_nan_test
= is_or
? aco_opcode::v_cmp_neq_f32
: aco_opcode::v_cmp_eq_f32
;
1735 if (get_f32_cmp(cmp
->opcode
) == expected_nan_test
)
1736 std::swap(nan_test
, cmp
);
1737 else if (get_f32_cmp(nan_test
->opcode
) != expected_nan_test
)
1740 if (!is_cmp(cmp
->opcode
) || get_cmp_bitsize(cmp
->opcode
) != get_cmp_bitsize(nan_test
->opcode
))
1743 if (!nan_test
->operands
[0].isTemp() || !nan_test
->operands
[1].isTemp())
1745 if (!cmp
->operands
[0].isTemp() && !cmp
->operands
[1].isTemp())
1748 unsigned prop_nan0
= original_temp_id(ctx
, nan_test
->operands
[0].getTemp());
1749 unsigned prop_nan1
= original_temp_id(ctx
, nan_test
->operands
[1].getTemp());
1750 if (prop_nan0
!= prop_nan1
)
1753 if (nan_test
->isVOP3()) {
1754 VOP3A_instruction
*vop3
= static_cast<VOP3A_instruction
*>(nan_test
);
1755 if (vop3
->neg
[0] != vop3
->neg
[1] || vop3
->abs
[0] != vop3
->abs
[1] || vop3
->opsel
== 1 || vop3
->opsel
== 2)
1759 int constant_operand
= -1;
1760 for (unsigned i
= 0; i
< 2; i
++) {
1761 if (cmp
->operands
[i
].isTemp() && original_temp_id(ctx
, cmp
->operands
[i
].getTemp()) == prop_nan0
) {
1762 constant_operand
= !i
;
1766 if (constant_operand
== -1)
1770 if (cmp
->operands
[constant_operand
].isConstant()) {
1771 constant
= cmp
->operands
[constant_operand
].constantValue();
1772 } else if (cmp
->operands
[constant_operand
].isTemp()) {
1773 Temp tmp
= cmp
->operands
[constant_operand
].getTemp();
1774 unsigned id
= original_temp_id(ctx
, tmp
);
1775 if (!ctx
.info
[id
].is_constant_or_literal(32))
1777 constant
= ctx
.info
[id
].val
;
1783 memcpy(&constantf
, &constant
, 4);
1784 if (isnan(constantf
))
1787 if (cmp
->operands
[0].isTemp())
1788 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1789 if (cmp
->operands
[1].isTemp())
1790 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1791 decrease_uses(ctx
, nan_test
);
1792 decrease_uses(ctx
, cmp
);
1794 aco_opcode new_op
= is_or
? get_unordered(cmp
->opcode
) : get_ordered(cmp
->opcode
);
1795 Instruction
*new_instr
;
1796 if (cmp
->isVOP3()) {
1797 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOPC
), 2, 1);
1798 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1799 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1800 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1801 new_vop3
->clamp
= cmp_vop3
->clamp
;
1802 new_vop3
->omod
= cmp_vop3
->omod
;
1803 new_vop3
->opsel
= cmp_vop3
->opsel
;
1804 new_instr
= new_vop3
;
1806 new_instr
= create_instruction
<VOPC_instruction
>(new_op
, Format::VOPC
, 2, 1);
1808 new_instr
->operands
[0] = cmp
->operands
[0];
1809 new_instr
->operands
[1] = cmp
->operands
[1];
1810 new_instr
->definitions
[0] = instr
->definitions
[0];
1812 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1813 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1815 instr
.reset(new_instr
);
1820 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1821 bool combine_inverse_comparison(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
1823 if (instr
->opcode
!= aco_opcode::s_not_b64
)
1825 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
1827 if (!instr
->operands
[0].isTemp())
1830 Instruction
*cmp
= follow_operand(ctx
, instr
->operands
[0]);
1834 aco_opcode new_opcode
= get_inverse(cmp
->opcode
);
1835 if (new_opcode
== aco_opcode::num_opcodes
)
1838 if (cmp
->operands
[0].isTemp())
1839 ctx
.uses
[cmp
->operands
[0].tempId()]++;
1840 if (cmp
->operands
[1].isTemp())
1841 ctx
.uses
[cmp
->operands
[1].tempId()]++;
1842 decrease_uses(ctx
, cmp
);
1844 Instruction
*new_instr
;
1845 if (cmp
->isVOP3()) {
1846 VOP3A_instruction
*new_vop3
= create_instruction
<VOP3A_instruction
>(new_opcode
, asVOP3(Format::VOPC
), 2, 1);
1847 VOP3A_instruction
*cmp_vop3
= static_cast<VOP3A_instruction
*>(cmp
);
1848 memcpy(new_vop3
->abs
, cmp_vop3
->abs
, sizeof(new_vop3
->abs
));
1849 memcpy(new_vop3
->neg
, cmp_vop3
->neg
, sizeof(new_vop3
->neg
));
1850 new_vop3
->clamp
= cmp_vop3
->clamp
;
1851 new_vop3
->omod
= cmp_vop3
->omod
;
1852 new_vop3
->opsel
= cmp_vop3
->opsel
;
1853 new_instr
= new_vop3
;
1855 new_instr
= create_instruction
<VOPC_instruction
>(new_opcode
, Format::VOPC
, 2, 1);
1857 new_instr
->operands
[0] = cmp
->operands
[0];
1858 new_instr
->operands
[1] = cmp
->operands
[1];
1859 new_instr
->definitions
[0] = instr
->definitions
[0];
1861 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1862 ctx
.info
[instr
->definitions
[0].tempId()].set_vopc(new_instr
);
1864 instr
.reset(new_instr
);
1869 /* op1(op2(1, 2), 0) if swap = false
1870 * op1(0, op2(1, 2)) if swap = true */
1871 bool match_op3_for_vop3(opt_ctx
&ctx
, aco_opcode op1
, aco_opcode op2
,
1872 Instruction
* op1_instr
, bool swap
, const char *shuffle_str
,
1873 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t *opsel
,
1874 bool *op1_clamp
, uint8_t *op1_omod
,
1875 bool *inbetween_neg
, bool *inbetween_abs
, bool *inbetween_opsel
)
1878 if (op1_instr
->opcode
!= op1
)
1881 Instruction
*op2_instr
= follow_operand(ctx
, op1_instr
->operands
[swap
]);
1882 if (!op2_instr
|| op2_instr
->opcode
!= op2
)
1884 if (fixed_to_exec(op2_instr
->operands
[0]) || fixed_to_exec(op2_instr
->operands
[1]))
1887 VOP3A_instruction
*op1_vop3
= op1_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op1_instr
) : NULL
;
1888 VOP3A_instruction
*op2_vop3
= op2_instr
->isVOP3() ? static_cast<VOP3A_instruction
*>(op2_instr
) : NULL
;
1890 /* don't support inbetween clamp/omod */
1891 if (op2_vop3
&& (op2_vop3
->clamp
|| op2_vop3
->omod
))
1894 /* get operands and modifiers and check inbetween modifiers */
1895 *op1_clamp
= op1_vop3
? op1_vop3
->clamp
: false;
1896 *op1_omod
= op1_vop3
? op1_vop3
->omod
: 0u;
1899 *inbetween_neg
= op1_vop3
? op1_vop3
->neg
[swap
] : false;
1900 else if (op1_vop3
&& op1_vop3
->neg
[swap
])
1904 *inbetween_abs
= op1_vop3
? op1_vop3
->abs
[swap
] : false;
1905 else if (op1_vop3
&& op1_vop3
->abs
[swap
])
1908 if (inbetween_opsel
)
1909 *inbetween_opsel
= op1_vop3
? op1_vop3
->opsel
& (1 << swap
) : false;
1910 else if (op1_vop3
&& op1_vop3
->opsel
& (1 << swap
))
1914 shuffle
[shuffle_str
[0] - '0'] = 0;
1915 shuffle
[shuffle_str
[1] - '0'] = 1;
1916 shuffle
[shuffle_str
[2] - '0'] = 2;
1918 operands
[shuffle
[0]] = op1_instr
->operands
[!swap
];
1919 neg
[shuffle
[0]] = op1_vop3
? op1_vop3
->neg
[!swap
] : false;
1920 abs
[shuffle
[0]] = op1_vop3
? op1_vop3
->abs
[!swap
] : false;
1921 if (op1_vop3
&& op1_vop3
->opsel
& (1 << !swap
))
1922 *opsel
|= 1 << shuffle
[0];
1924 for (unsigned i
= 0; i
< 2; i
++) {
1925 operands
[shuffle
[i
+ 1]] = op2_instr
->operands
[i
];
1926 neg
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->neg
[i
] : false;
1927 abs
[shuffle
[i
+ 1]] = op2_vop3
? op2_vop3
->abs
[i
] : false;
1928 if (op2_vop3
&& op2_vop3
->opsel
& (1 << i
))
1929 *opsel
|= 1 << shuffle
[i
+ 1];
1932 /* check operands */
1933 if (!check_vop3_operands(ctx
, 3, operands
))
1939 void create_vop3_for_op3(opt_ctx
& ctx
, aco_opcode opcode
, aco_ptr
<Instruction
>& instr
,
1940 Operand operands
[3], bool neg
[3], bool abs
[3], uint8_t opsel
,
1941 bool clamp
, unsigned omod
)
1943 VOP3A_instruction
*new_instr
= create_instruction
<VOP3A_instruction
>(opcode
, Format::VOP3A
, 3, 1);
1944 memcpy(new_instr
->abs
, abs
, sizeof(bool[3]));
1945 memcpy(new_instr
->neg
, neg
, sizeof(bool[3]));
1946 new_instr
->clamp
= clamp
;
1947 new_instr
->omod
= omod
;
1948 new_instr
->opsel
= opsel
;
1949 new_instr
->operands
[0] = operands
[0];
1950 new_instr
->operands
[1] = operands
[1];
1951 new_instr
->operands
[2] = operands
[2];
1952 new_instr
->definitions
[0] = instr
->definitions
[0];
1953 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
1955 instr
.reset(new_instr
);
1958 bool combine_three_valu_op(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode op2
, aco_opcode new_op
, const char *shuffle
, uint8_t ops
)
1960 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1961 (label_omod_success
| label_clamp_success
);
1963 for (unsigned swap
= 0; swap
< 2; swap
++) {
1964 if (!((1 << swap
) & ops
))
1967 Operand operands
[3];
1968 bool neg
[3], abs
[3], clamp
;
1969 uint8_t opsel
= 0, omod
= 0;
1970 if (match_op3_for_vop3(ctx
, instr
->opcode
, op2
,
1971 instr
.get(), swap
, shuffle
,
1972 operands
, neg
, abs
, &opsel
,
1973 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
1974 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
1975 create_vop3_for_op3(ctx
, new_op
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
1976 if (omod_clamp
& label_omod_success
)
1977 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
1978 if (omod_clamp
& label_clamp_success
)
1979 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
1986 bool combine_minmax(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode opposite
, aco_opcode minmax3
)
1988 if (combine_three_valu_op(ctx
, instr
, instr
->opcode
, minmax3
, "012", 1 | 2))
1991 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
1992 (label_omod_success
| label_clamp_success
);
1994 /* min(-max(a, b), c) -> min3(-a, -b, c) *
1995 * max(-min(a, b), c) -> max3(-a, -b, c) */
1996 for (unsigned swap
= 0; swap
< 2; swap
++) {
1997 Operand operands
[3];
1998 bool neg
[3], abs
[3], clamp
;
1999 uint8_t opsel
= 0, omod
= 0;
2001 if (match_op3_for_vop3(ctx
, instr
->opcode
, opposite
,
2002 instr
.get(), swap
, "012",
2003 operands
, neg
, abs
, &opsel
,
2004 &clamp
, &omod
, &inbetween_neg
, NULL
, NULL
) &&
2006 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2009 create_vop3_for_op3(ctx
, minmax3
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2010 if (omod_clamp
& label_omod_success
)
2011 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2012 if (omod_clamp
& label_clamp_success
)
2013 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2020 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
2021 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
2022 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
2023 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
2024 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
2025 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
2026 bool combine_salu_not_bitwise(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2029 if (!instr
->operands
[0].isTemp())
2031 if (instr
->definitions
[1].isTemp() && ctx
.uses
[instr
->definitions
[1].tempId()])
2034 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[0]);
2037 switch (op2_instr
->opcode
) {
2038 case aco_opcode::s_and_b32
:
2039 case aco_opcode::s_or_b32
:
2040 case aco_opcode::s_xor_b32
:
2041 case aco_opcode::s_and_b64
:
2042 case aco_opcode::s_or_b64
:
2043 case aco_opcode::s_xor_b64
:
2049 /* create instruction */
2050 std::swap(instr
->definitions
[0], op2_instr
->definitions
[0]);
2051 std::swap(instr
->definitions
[1], op2_instr
->definitions
[1]);
2052 ctx
.uses
[instr
->operands
[0].tempId()]--;
2053 ctx
.info
[op2_instr
->definitions
[0].tempId()].label
= 0;
2055 switch (op2_instr
->opcode
) {
2056 case aco_opcode::s_and_b32
:
2057 op2_instr
->opcode
= aco_opcode::s_nand_b32
;
2059 case aco_opcode::s_or_b32
:
2060 op2_instr
->opcode
= aco_opcode::s_nor_b32
;
2062 case aco_opcode::s_xor_b32
:
2063 op2_instr
->opcode
= aco_opcode::s_xnor_b32
;
2065 case aco_opcode::s_and_b64
:
2066 op2_instr
->opcode
= aco_opcode::s_nand_b64
;
2068 case aco_opcode::s_or_b64
:
2069 op2_instr
->opcode
= aco_opcode::s_nor_b64
;
2071 case aco_opcode::s_xor_b64
:
2072 op2_instr
->opcode
= aco_opcode::s_xnor_b64
;
2081 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
2082 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
2083 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
2084 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
2085 bool combine_salu_n2(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2087 if (instr
->definitions
[0].isTemp() && ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bool())
2090 for (unsigned i
= 0; i
< 2; i
++) {
2091 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2092 if (!op2_instr
|| (op2_instr
->opcode
!= aco_opcode::s_not_b32
&& op2_instr
->opcode
!= aco_opcode::s_not_b64
))
2094 if (ctx
.uses
[op2_instr
->definitions
[1].tempId()] || fixed_to_exec(op2_instr
->operands
[0]))
2097 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2098 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2101 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2102 instr
->operands
[0] = instr
->operands
[!i
];
2103 instr
->operands
[1] = op2_instr
->operands
[0];
2104 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2106 switch (instr
->opcode
) {
2107 case aco_opcode::s_and_b32
:
2108 instr
->opcode
= aco_opcode::s_andn2_b32
;
2110 case aco_opcode::s_or_b32
:
2111 instr
->opcode
= aco_opcode::s_orn2_b32
;
2113 case aco_opcode::s_and_b64
:
2114 instr
->opcode
= aco_opcode::s_andn2_b64
;
2116 case aco_opcode::s_or_b64
:
2117 instr
->opcode
= aco_opcode::s_orn2_b64
;
2128 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2129 bool combine_salu_lshl_add(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
)
2131 if (instr
->opcode
== aco_opcode::s_add_i32
&& ctx
.uses
[instr
->definitions
[1].tempId()])
2134 for (unsigned i
= 0; i
< 2; i
++) {
2135 Instruction
*op2_instr
= follow_operand(ctx
, instr
->operands
[i
]);
2136 if (!op2_instr
|| op2_instr
->opcode
!= aco_opcode::s_lshl_b32
||
2137 ctx
.uses
[op2_instr
->definitions
[1].tempId()])
2139 if (!op2_instr
->operands
[1].isConstant() || fixed_to_exec(op2_instr
->operands
[0]))
2142 uint32_t shift
= op2_instr
->operands
[1].constantValue();
2143 if (shift
< 1 || shift
> 4)
2146 if (instr
->operands
[!i
].isLiteral() && op2_instr
->operands
[0].isLiteral() &&
2147 instr
->operands
[!i
].constantValue() != op2_instr
->operands
[0].constantValue())
2150 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2151 instr
->operands
[1] = instr
->operands
[!i
];
2152 instr
->operands
[0] = op2_instr
->operands
[0];
2153 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2155 instr
->opcode
= ((aco_opcode
[]){aco_opcode::s_lshl1_add_u32
,
2156 aco_opcode::s_lshl2_add_u32
,
2157 aco_opcode::s_lshl3_add_u32
,
2158 aco_opcode::s_lshl4_add_u32
})[shift
- 1];
2165 bool combine_add_sub_b2i(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
, aco_opcode new_op
, uint8_t ops
)
2167 if (instr
->usesModifiers())
2170 for (unsigned i
= 0; i
< 2; i
++) {
2171 if (!((1 << i
) & ops
))
2173 if (instr
->operands
[i
].isTemp() &&
2174 ctx
.info
[instr
->operands
[i
].tempId()].is_b2i() &&
2175 ctx
.uses
[instr
->operands
[i
].tempId()] == 1) {
2177 aco_ptr
<Instruction
> new_instr
;
2178 if (instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2179 new_instr
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 2));
2180 } else if (ctx
.program
->chip_class
>= GFX10
||
2181 (instr
->operands
[!i
].isConstant() && !instr
->operands
[!i
].isLiteral())) {
2182 new_instr
.reset(create_instruction
<VOP3A_instruction
>(new_op
, asVOP3(Format::VOP2
), 3, 2));
2186 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2187 new_instr
->definitions
[0] = instr
->definitions
[0];
2188 new_instr
->definitions
[1] = instr
->definitions
.size() == 2 ? instr
->definitions
[1] :
2189 Definition(ctx
.program
->allocateId(), ctx
.program
->lane_mask
);
2190 new_instr
->definitions
[1].setHint(vcc
);
2191 new_instr
->operands
[0] = Operand(0u);
2192 new_instr
->operands
[1] = instr
->operands
[!i
];
2193 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2194 instr
= std::move(new_instr
);
2195 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2203 bool get_minmax_info(aco_opcode op
, aco_opcode
*min
, aco_opcode
*max
, aco_opcode
*min3
, aco_opcode
*max3
, aco_opcode
*med3
, bool *some_gfx9_only
)
2206 #define MINMAX(type, gfx9) \
2207 case aco_opcode::v_min_##type:\
2208 case aco_opcode::v_max_##type:\
2209 case aco_opcode::v_med3_##type:\
2210 *min = aco_opcode::v_min_##type;\
2211 *max = aco_opcode::v_max_##type;\
2212 *med3 = aco_opcode::v_med3_##type;\
2213 *min3 = aco_opcode::v_min3_##type;\
2214 *max3 = aco_opcode::v_max3_##type;\
2215 *some_gfx9_only = gfx9;\
2229 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2230 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2231 bool combine_clamp(opt_ctx
& ctx
, aco_ptr
<Instruction
>& instr
,
2232 aco_opcode min
, aco_opcode max
, aco_opcode med
)
2234 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2235 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2236 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2237 aco_opcode other_op
;
2238 if (instr
->opcode
== min
)
2240 else if (instr
->opcode
== max
)
2245 uint64_t omod_clamp
= ctx
.info
[instr
->definitions
[0].tempId()].label
&
2246 (label_omod_success
| label_clamp_success
);
2248 for (unsigned swap
= 0; swap
< 2; swap
++) {
2249 Operand operands
[3];
2250 bool neg
[3], abs
[3], clamp
;
2251 uint8_t opsel
= 0, omod
= 0;
2252 if (match_op3_for_vop3(ctx
, instr
->opcode
, other_op
, instr
.get(), swap
,
2253 "012", operands
, neg
, abs
, &opsel
,
2254 &clamp
, &omod
, NULL
, NULL
, NULL
)) {
2255 int const0_idx
= -1, const1_idx
= -1;
2256 uint32_t const0
= 0, const1
= 0;
2257 for (int i
= 0; i
< 3; i
++) {
2259 if (operands
[i
].isConstant()) {
2260 val
= operands
[i
].constantValue();
2261 } else if (operands
[i
].isTemp() && ctx
.info
[operands
[i
].tempId()].is_constant_or_literal(32)) {
2262 val
= ctx
.info
[operands
[i
].tempId()].val
;
2266 if (const0_idx
>= 0) {
2274 if (const0_idx
< 0 || const1_idx
< 0)
2277 if (opsel
& (1 << const0_idx
))
2279 if (opsel
& (1 << const1_idx
))
2282 int lower_idx
= const0_idx
;
2284 case aco_opcode::v_min_f32
:
2285 case aco_opcode::v_min_f16
: {
2286 float const0_f
, const1_f
;
2287 if (min
== aco_opcode::v_min_f32
) {
2288 memcpy(&const0_f
, &const0
, 4);
2289 memcpy(&const1_f
, &const1
, 4);
2291 const0_f
= _mesa_half_to_float(const0
);
2292 const1_f
= _mesa_half_to_float(const1
);
2294 if (abs
[const0_idx
]) const0_f
= fabsf(const0_f
);
2295 if (abs
[const1_idx
]) const1_f
= fabsf(const1_f
);
2296 if (neg
[const0_idx
]) const0_f
= -const0_f
;
2297 if (neg
[const1_idx
]) const1_f
= -const1_f
;
2298 lower_idx
= const0_f
< const1_f
? const0_idx
: const1_idx
;
2301 case aco_opcode::v_min_u32
: {
2302 lower_idx
= const0
< const1
? const0_idx
: const1_idx
;
2305 case aco_opcode::v_min_u16
: {
2306 lower_idx
= (uint16_t)const0
< (uint16_t)const1
? const0_idx
: const1_idx
;
2309 case aco_opcode::v_min_i32
: {
2310 int32_t const0_i
= const0
& 0x80000000u
? -2147483648 + (int32_t)(const0
& 0x7fffffffu
) : const0
;
2311 int32_t const1_i
= const1
& 0x80000000u
? -2147483648 + (int32_t)(const1
& 0x7fffffffu
) : const1
;
2312 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2315 case aco_opcode::v_min_i16
: {
2316 int16_t const0_i
= const0
& 0x8000u
? -32768 + (int16_t)(const0
& 0x7fffu
) : const0
;
2317 int16_t const1_i
= const1
& 0x8000u
? -32768 + (int16_t)(const1
& 0x7fffu
) : const1
;
2318 lower_idx
= const0_i
< const1_i
? const0_idx
: const1_idx
;
2324 int upper_idx
= lower_idx
== const0_idx
? const1_idx
: const0_idx
;
2326 if (instr
->opcode
== min
) {
2327 if (upper_idx
!= 0 || lower_idx
== 0)
2330 if (upper_idx
== 0 || lower_idx
!= 0)
2334 ctx
.uses
[instr
->operands
[swap
].tempId()]--;
2335 create_vop3_for_op3(ctx
, med
, instr
, operands
, neg
, abs
, opsel
, clamp
, omod
);
2336 if (omod_clamp
& label_omod_success
)
2337 ctx
.info
[instr
->definitions
[0].tempId()].set_omod_success(instr
.get());
2338 if (omod_clamp
& label_clamp_success
)
2339 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(instr
.get());
2349 void apply_sgprs(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2351 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
2352 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
2353 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
2355 /* find candidates and create the set of sgprs already read */
2356 unsigned sgpr_ids
[2] = {0, 0};
2357 uint32_t operand_mask
= 0;
2358 bool has_literal
= false;
2359 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
2360 if (instr
->operands
[i
].isLiteral())
2362 if (!instr
->operands
[i
].isTemp())
2364 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
) {
2365 if (instr
->operands
[i
].tempId() != sgpr_ids
[0])
2366 sgpr_ids
[!!sgpr_ids
[0]] = instr
->operands
[i
].tempId();
2368 ssa_info
& info
= ctx
.info
[instr
->operands
[i
].tempId()];
2369 if (info
.is_temp() && info
.temp
.type() == RegType::sgpr
)
2370 operand_mask
|= 1u << i
;
2372 unsigned max_sgprs
= 1;
2373 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
2378 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
2380 /* keep on applying sgprs until there is nothing left to be done */
2381 while (operand_mask
) {
2382 uint32_t sgpr_idx
= 0;
2383 uint32_t sgpr_info_id
= 0;
2384 uint32_t mask
= operand_mask
;
2387 unsigned i
= u_bit_scan(&mask
);
2388 uint16_t uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2389 if (sgpr_info_id
== 0 || uses
< ctx
.uses
[sgpr_info_id
]) {
2391 sgpr_info_id
= instr
->operands
[i
].tempId();
2394 operand_mask
&= ~(1u << sgpr_idx
);
2396 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2397 * definitively beneficial.
2398 * TODO: this is too conservative because later the use count could be reduced to 1 */
2399 if (num_sgprs
&& ctx
.uses
[sgpr_info_id
] > 1 && !instr
->isVOP3())
2402 Temp sgpr
= ctx
.info
[sgpr_info_id
].temp
;
2403 bool new_sgpr
= sgpr
.id() != sgpr_ids
[0] && sgpr
.id() != sgpr_ids
[1];
2404 if (new_sgpr
&& num_sgprs
>= max_sgprs
)
2407 if (sgpr_idx
== 0 || instr
->isVOP3()) {
2408 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2409 } else if (can_swap_operands(instr
)) {
2410 instr
->operands
[sgpr_idx
] = instr
->operands
[0];
2411 instr
->operands
[0] = Operand(sgpr
);
2412 /* swap bits using a 4-entry LUT */
2413 uint32_t swapped
= (0x3120 >> (operand_mask
& 0x3)) & 0xf;
2414 operand_mask
= (operand_mask
& ~0x3) | swapped
;
2415 } else if (can_use_VOP3(ctx
, instr
)) {
2416 to_VOP3(ctx
, instr
);
2417 instr
->operands
[sgpr_idx
] = Operand(sgpr
);
2423 sgpr_ids
[num_sgprs
++] = sgpr
.id();
2424 ctx
.uses
[sgpr_info_id
]--;
2425 ctx
.uses
[sgpr
.id()]++;
2429 bool apply_omod_clamp(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2431 /* check if we could apply omod on predecessor */
2432 if (instr
->opcode
== aco_opcode::v_mul_f32
|| instr
->opcode
== aco_opcode::v_mul_f16
) {
2433 bool op0
= instr
->operands
[0].isTemp() && ctx
.info
[instr
->operands
[0].tempId()].is_omod_success();
2434 bool op1
= instr
->operands
[1].isTemp() && ctx
.info
[instr
->operands
[1].tempId()].is_omod_success();
2436 unsigned idx
= op0
? 0 : 1;
2437 /* omod was successfully applied */
2438 /* if the omod instruction is v_mad, we also have to change the original add */
2439 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2440 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2441 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp())
2442 static_cast<VOP3A_instruction
*>(add_instr
)->clamp
= true;
2443 add_instr
->definitions
[0] = instr
->definitions
[0];
2446 Instruction
* omod_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2447 /* check if we have an additional clamp modifier */
2448 if (ctx
.info
[instr
->definitions
[0].tempId()].is_clamp() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2449 ctx
.uses
[ctx
.info
[instr
->definitions
[0].tempId()].temp
.id()]) {
2450 static_cast<VOP3A_instruction
*>(omod_instr
)->clamp
= true;
2451 ctx
.info
[instr
->definitions
[0].tempId()].set_clamp_success(omod_instr
);
2453 /* change definition ssa-id of modified instruction */
2454 omod_instr
->definitions
[0] = instr
->definitions
[0];
2456 /* change the definition of instr to something unused, e.g. the original omod def */
2457 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2458 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2461 if (!ctx
.info
[instr
->definitions
[0].tempId()].label
) {
2462 /* in all other cases, label this instruction as option for multiply-add */
2463 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2467 /* check if we could apply clamp on predecessor */
2468 if (instr
->opcode
== aco_opcode::v_med3_f32
|| instr
->opcode
== aco_opcode::v_med3_f16
) {
2469 bool is_fp16
= instr
->opcode
== aco_opcode::v_med3_f16
;
2471 bool found_zero
= false, found_one
= false;
2472 for (unsigned i
= 0; i
< 3; i
++)
2474 if (instr
->operands
[i
].constantEquals(0))
2476 else if (instr
->operands
[i
].constantEquals(is_fp16
? 0x3c00 : 0x3f800000)) /* 1.0 */
2481 if (found_zero
&& found_one
&& instr
->operands
[idx
].isTemp() &&
2482 ctx
.info
[instr
->operands
[idx
].tempId()].is_clamp_success()) {
2483 /* clamp was successfully applied */
2484 /* if the clamp instruction is v_mad, we also have to change the original add */
2485 if (ctx
.info
[instr
->operands
[idx
].tempId()].is_mad()) {
2486 Instruction
* add_instr
= ctx
.mad_infos
[ctx
.info
[instr
->operands
[idx
].tempId()].instr
->pass_flags
].add_instr
.get();
2487 add_instr
->definitions
[0] = instr
->definitions
[0];
2489 Instruction
* clamp_instr
= ctx
.info
[instr
->operands
[idx
].tempId()].instr
;
2490 /* change definition ssa-id of modified instruction */
2491 clamp_instr
->definitions
[0] = instr
->definitions
[0];
2493 /* change the definition of instr to something unused, e.g. the original omod def */
2494 instr
->definitions
[0] = Definition(instr
->operands
[idx
].getTemp());
2495 ctx
.uses
[instr
->definitions
[0].tempId()] = 0;
2500 /* omod has no effect if denormals are enabled */
2501 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2502 if (!instr
->definitions
.empty() && ctx
.uses
[instr
->definitions
[0].tempId()] == 1 &&
2503 can_use_VOP3(ctx
, instr
) && instr_info
.can_use_output_modifiers
[(int)instr
->opcode
]) {
2504 bool can_use_omod
= (instr
->definitions
[0].bytes() == 4 ? block
.fp_mode
.denorm32
: block
.fp_mode
.denorm16_64
) == 0;
2505 ssa_info
& def_info
= ctx
.info
[instr
->definitions
[0].tempId()];
2506 if (can_use_omod
&& def_info
.is_omod2() && ctx
.uses
[def_info
.temp
.id()]) {
2507 to_VOP3(ctx
, instr
);
2508 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 1;
2509 def_info
.set_omod_success(instr
.get());
2510 } else if (can_use_omod
&& def_info
.is_omod4() && ctx
.uses
[def_info
.temp
.id()]) {
2511 to_VOP3(ctx
, instr
);
2512 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 2;
2513 def_info
.set_omod_success(instr
.get());
2514 } else if (can_use_omod
&& def_info
.is_omod5() && ctx
.uses
[def_info
.temp
.id()]) {
2515 to_VOP3(ctx
, instr
);
2516 static_cast<VOP3A_instruction
*>(instr
.get())->omod
= 3;
2517 def_info
.set_omod_success(instr
.get());
2518 } else if (def_info
.is_clamp() && ctx
.uses
[def_info
.temp
.id()]) {
2519 to_VOP3(ctx
, instr
);
2520 static_cast<VOP3A_instruction
*>(instr
.get())->clamp
= true;
2521 def_info
.set_clamp_success(instr
.get());
2528 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2529 // this would mean that we'd have to fix the instruction uses while value propagation
2531 void combine_instruction(opt_ctx
&ctx
, Block
& block
, aco_ptr
<Instruction
>& instr
)
2533 if (instr
->definitions
.empty() || is_dead(ctx
.uses
, instr
.get()))
2536 if (instr
->isVALU()) {
2537 if (can_apply_sgprs(instr
))
2538 apply_sgprs(ctx
, instr
);
2539 if (apply_omod_clamp(ctx
, block
, instr
))
2543 if (ctx
.info
[instr
->definitions
[0].tempId()].is_vcc_hint()) {
2544 instr
->definitions
[0].setHint(vcc
);
2547 /* TODO: There are still some peephole optimizations that could be done:
2548 * - abs(a - b) -> s_absdiff_i32
2549 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2550 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2551 * These aren't probably too interesting though.
2552 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2553 * probably more useful than the previously mentioned optimizations.
2554 * The various comparison optimizations also currently only work with 32-bit
2557 /* neg(mul(a, b)) -> mul(neg(a), b) */
2558 if (ctx
.info
[instr
->definitions
[0].tempId()].is_neg() && ctx
.uses
[instr
->operands
[1].tempId()] == 1) {
2559 Temp val
= ctx
.info
[instr
->definitions
[0].tempId()].temp
;
2561 if (!ctx
.info
[val
.id()].is_mul())
2564 Instruction
* mul_instr
= ctx
.info
[val
.id()].instr
;
2566 if (mul_instr
->operands
[0].isLiteral())
2568 if (mul_instr
->isVOP3() && static_cast<VOP3A_instruction
*>(mul_instr
)->clamp
)
2571 /* convert to mul(neg(a), b) */
2572 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2573 Definition def
= instr
->definitions
[0];
2574 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2575 bool is_abs
= ctx
.info
[instr
->definitions
[0].tempId()].is_abs();
2576 instr
.reset(create_instruction
<VOP3A_instruction
>(mul_instr
->opcode
, asVOP3(Format::VOP2
), 2, 1));
2577 instr
->operands
[0] = mul_instr
->operands
[0];
2578 instr
->operands
[1] = mul_instr
->operands
[1];
2579 instr
->definitions
[0] = def
;
2580 VOP3A_instruction
* new_mul
= static_cast<VOP3A_instruction
*>(instr
.get());
2581 if (mul_instr
->isVOP3()) {
2582 VOP3A_instruction
* mul
= static_cast<VOP3A_instruction
*>(mul_instr
);
2583 new_mul
->neg
[0] = mul
->neg
[0] && !is_abs
;
2584 new_mul
->neg
[1] = mul
->neg
[1] && !is_abs
;
2585 new_mul
->abs
[0] = mul
->abs
[0] || is_abs
;
2586 new_mul
->abs
[1] = mul
->abs
[1] || is_abs
;
2587 new_mul
->omod
= mul
->omod
;
2589 new_mul
->neg
[0] ^= true;
2590 new_mul
->clamp
= false;
2592 ctx
.info
[instr
->definitions
[0].tempId()].set_mul(instr
.get());
2596 /* combine mul+add -> mad */
2597 bool mad32
= instr
->opcode
== aco_opcode::v_add_f32
||
2598 instr
->opcode
== aco_opcode::v_sub_f32
||
2599 instr
->opcode
== aco_opcode::v_subrev_f32
;
2600 bool mad16
= instr
->opcode
== aco_opcode::v_add_f16
||
2601 instr
->opcode
== aco_opcode::v_sub_f16
||
2602 instr
->opcode
== aco_opcode::v_subrev_f16
;
2603 if (mad16
|| mad32
) {
2604 bool need_fma
= mad32
? block
.fp_mode
.denorm32
!= 0 :
2605 (block
.fp_mode
.denorm16_64
!= 0 || ctx
.program
->chip_class
>= GFX10
);
2606 if (need_fma
&& instr
->definitions
[0].isPrecise())
2608 if (need_fma
&& mad32
&& !ctx
.program
->has_fast_fma32
)
2611 uint32_t uses_src0
= UINT32_MAX
;
2612 uint32_t uses_src1
= UINT32_MAX
;
2613 Instruction
* mul_instr
= nullptr;
2614 unsigned add_op_idx
;
2615 /* check if any of the operands is a multiplication */
2616 ssa_info
*op0_info
= instr
->operands
[0].isTemp() ? &ctx
.info
[instr
->operands
[0].tempId()] : NULL
;
2617 ssa_info
*op1_info
= instr
->operands
[1].isTemp() ? &ctx
.info
[instr
->operands
[1].tempId()] : NULL
;
2618 if (op0_info
&& op0_info
->is_mul() && (!need_fma
|| !op0_info
->instr
->definitions
[0].isPrecise()))
2619 uses_src0
= ctx
.uses
[instr
->operands
[0].tempId()];
2620 if (op1_info
&& op1_info
->is_mul() && (!need_fma
|| !op1_info
->instr
->definitions
[0].isPrecise()))
2621 uses_src1
= ctx
.uses
[instr
->operands
[1].tempId()];
2623 /* find the 'best' mul instruction to combine with the add */
2624 if (uses_src0
< uses_src1
) {
2625 mul_instr
= op0_info
->instr
;
2627 } else if (uses_src1
< uses_src0
) {
2628 mul_instr
= op1_info
->instr
;
2630 } else if (uses_src0
!= UINT32_MAX
) {
2631 /* tiebreaker: quite random what to pick */
2632 if (op0_info
->instr
->operands
[0].isLiteral()) {
2633 mul_instr
= op1_info
->instr
;
2636 mul_instr
= op0_info
->instr
;
2641 Operand op
[3] = {Operand(v1
), Operand(v1
), Operand(v1
)};
2642 bool neg
[3] = {false, false, false};
2643 bool abs
[3] = {false, false, false};
2646 op
[0] = mul_instr
->operands
[0];
2647 op
[1] = mul_instr
->operands
[1];
2648 op
[2] = instr
->operands
[add_op_idx
];
2649 // TODO: would be better to check this before selecting a mul instr?
2650 if (!check_vop3_operands(ctx
, 3, op
))
2653 if (mul_instr
->isVOP3()) {
2654 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (mul_instr
);
2655 neg
[0] = vop3
->neg
[0];
2656 neg
[1] = vop3
->neg
[1];
2657 abs
[0] = vop3
->abs
[0];
2658 abs
[1] = vop3
->abs
[1];
2659 /* we cannot use these modifiers between mul and add */
2660 if (vop3
->clamp
|| vop3
->omod
)
2664 /* convert to mad */
2665 ctx
.uses
[mul_instr
->definitions
[0].tempId()]--;
2666 if (ctx
.uses
[mul_instr
->definitions
[0].tempId()]) {
2668 ctx
.uses
[op
[0].tempId()]++;
2670 ctx
.uses
[op
[1].tempId()]++;
2673 if (instr
->isVOP3()) {
2674 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*> (instr
.get());
2675 neg
[2] = vop3
->neg
[add_op_idx
];
2676 abs
[2] = vop3
->abs
[add_op_idx
];
2678 clamp
= vop3
->clamp
;
2679 /* abs of the multiplication result */
2680 if (vop3
->abs
[1 - add_op_idx
]) {
2686 /* neg of the multiplication result */
2687 neg
[1] = neg
[1] ^ vop3
->neg
[1 - add_op_idx
];
2689 if (instr
->opcode
== aco_opcode::v_sub_f32
|| instr
->opcode
== aco_opcode::v_sub_f16
)
2690 neg
[1 + add_op_idx
] = neg
[1 + add_op_idx
] ^ true;
2691 else if (instr
->opcode
== aco_opcode::v_subrev_f32
|| instr
->opcode
== aco_opcode::v_subrev_f16
)
2692 neg
[2 - add_op_idx
] = neg
[2 - add_op_idx
] ^ true;
2694 aco_opcode mad_op
= need_fma
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
2696 mad_op
= need_fma
? (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_fma_legacy_f16
: aco_opcode::v_fma_f16
) :
2697 (ctx
.program
->chip_class
== GFX8
? aco_opcode::v_mad_legacy_f16
: aco_opcode::v_mad_f16
);
2699 aco_ptr
<VOP3A_instruction
> mad
{create_instruction
<VOP3A_instruction
>(mad_op
, Format::VOP3A
, 3, 1)};
2700 for (unsigned i
= 0; i
< 3; i
++)
2702 mad
->operands
[i
] = op
[i
];
2703 mad
->neg
[i
] = neg
[i
];
2704 mad
->abs
[i
] = abs
[i
];
2708 mad
->definitions
[0] = instr
->definitions
[0];
2710 /* mark this ssa_def to be re-checked for profitability and literals */
2711 ctx
.mad_infos
.emplace_back(std::move(instr
), mul_instr
->definitions
[0].tempId());
2712 ctx
.info
[mad
->definitions
[0].tempId()].set_mad(mad
.get(), ctx
.mad_infos
.size() - 1);
2713 instr
.reset(mad
.release());
2717 /* v_mul_f32(v_cndmask_b32(0, 1.0, cond), a) -> v_cndmask_b32(0, a, cond) */
2718 else if (instr
->opcode
== aco_opcode::v_mul_f32
&& !instr
->isVOP3()) {
2719 for (unsigned i
= 0; i
< 2; i
++) {
2720 if (instr
->operands
[i
].isTemp() && ctx
.info
[instr
->operands
[i
].tempId()].is_b2f() &&
2721 ctx
.uses
[instr
->operands
[i
].tempId()] == 1 &&
2722 instr
->operands
[!i
].isTemp() && instr
->operands
[!i
].getTemp().type() == RegType::vgpr
) {
2723 ctx
.uses
[instr
->operands
[i
].tempId()]--;
2724 ctx
.uses
[ctx
.info
[instr
->operands
[i
].tempId()].temp
.id()]++;
2726 aco_ptr
<VOP2_instruction
> new_instr
{create_instruction
<VOP2_instruction
>(aco_opcode::v_cndmask_b32
, Format::VOP2
, 3, 1)};
2727 new_instr
->operands
[0] = Operand(0u);
2728 new_instr
->operands
[1] = instr
->operands
[!i
];
2729 new_instr
->operands
[2] = Operand(ctx
.info
[instr
->operands
[i
].tempId()].temp
);
2730 new_instr
->definitions
[0] = instr
->definitions
[0];
2731 instr
.reset(new_instr
.release());
2732 ctx
.info
[instr
->definitions
[0].tempId()].label
= 0;
2736 } else if (instr
->opcode
== aco_opcode::v_or_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2737 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2738 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_or_b32
, aco_opcode::v_or3_b32
, "012", 1 | 2)) ;
2739 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2740 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_and_b32
, aco_opcode::v_and_or_b32
, "120", 1 | 2)) ;
2741 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_or_b32
, "120", 1 | 2)) ;
2742 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_or_b32
, "210", 1 | 2);
2743 } else if (instr
->opcode
== aco_opcode::v_xor_b32
&& ctx
.program
->chip_class
>= GFX10
) {
2744 if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2)) ;
2745 else combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xor3_b32
, "012", 1 | 2);
2746 } else if (instr
->opcode
== aco_opcode::v_add_u32
) {
2747 if (combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2)) ;
2748 else if (ctx
.program
->chip_class
>= GFX9
) {
2749 if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2750 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_xor_b32
, aco_opcode::v_xad_u32
, "120", 1 | 2)) ;
2751 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_i32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2752 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2753 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add3_u32
, "012", 1 | 2)) ;
2754 else if (combine_three_valu_op(ctx
, instr
, aco_opcode::s_lshl_b32
, aco_opcode::v_lshl_add_u32
, "120", 1 | 2)) ;
2755 else combine_three_valu_op(ctx
, instr
, aco_opcode::v_lshlrev_b32
, aco_opcode::v_lshl_add_u32
, "210", 1 | 2);
2757 } else if (instr
->opcode
== aco_opcode::v_add_co_u32
||
2758 instr
->opcode
== aco_opcode::v_add_co_u32_e64
) {
2759 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_addc_co_u32
, 1 | 2);
2760 } else if (instr
->opcode
== aco_opcode::v_sub_u32
||
2761 instr
->opcode
== aco_opcode::v_sub_co_u32
||
2762 instr
->opcode
== aco_opcode::v_sub_co_u32_e64
) {
2763 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 2);
2764 } else if (instr
->opcode
== aco_opcode::v_subrev_u32
||
2765 instr
->opcode
== aco_opcode::v_subrev_co_u32
||
2766 instr
->opcode
== aco_opcode::v_subrev_co_u32_e64
) {
2767 combine_add_sub_b2i(ctx
, instr
, aco_opcode::v_subbrev_co_u32
, 1);
2768 } else if (instr
->opcode
== aco_opcode::v_lshlrev_b32
&& ctx
.program
->chip_class
>= GFX9
) {
2769 combine_three_valu_op(ctx
, instr
, aco_opcode::v_add_u32
, aco_opcode::v_add_lshl_u32
, "120", 2);
2770 } else if ((instr
->opcode
== aco_opcode::s_add_u32
|| instr
->opcode
== aco_opcode::s_add_i32
) && ctx
.program
->chip_class
>= GFX9
) {
2771 combine_salu_lshl_add(ctx
, instr
);
2772 } else if (instr
->opcode
== aco_opcode::s_not_b32
) {
2773 combine_salu_not_bitwise(ctx
, instr
);
2774 } else if (instr
->opcode
== aco_opcode::s_not_b64
) {
2775 if (combine_inverse_comparison(ctx
, instr
)) ;
2776 else combine_salu_not_bitwise(ctx
, instr
);
2777 } else if (instr
->opcode
== aco_opcode::s_and_b32
|| instr
->opcode
== aco_opcode::s_or_b32
||
2778 instr
->opcode
== aco_opcode::s_and_b64
|| instr
->opcode
== aco_opcode::s_or_b64
) {
2779 if (combine_ordering_test(ctx
, instr
)) ;
2780 else if (combine_comparison_ordering(ctx
, instr
)) ;
2781 else if (combine_constant_comparison_ordering(ctx
, instr
)) ;
2782 else combine_salu_n2(ctx
, instr
);
2784 aco_opcode min
, max
, min3
, max3
, med3
;
2785 bool some_gfx9_only
;
2786 if (get_minmax_info(instr
->opcode
, &min
, &max
, &min3
, &max3
, &med3
, &some_gfx9_only
) &&
2787 (!some_gfx9_only
|| ctx
.program
->chip_class
>= GFX9
)) {
2788 if (combine_minmax(ctx
, instr
, instr
->opcode
== min
? max
: min
, instr
->opcode
== min
? min3
: max3
)) ;
2789 else combine_clamp(ctx
, instr
, min
, max
, med3
);
2794 bool to_uniform_bool_instr(opt_ctx
&ctx
, aco_ptr
<Instruction
> &instr
)
2796 switch (instr
->opcode
) {
2797 case aco_opcode::s_and_b32
:
2798 case aco_opcode::s_and_b64
:
2799 instr
->opcode
= aco_opcode::s_and_b32
;
2801 case aco_opcode::s_or_b32
:
2802 case aco_opcode::s_or_b64
:
2803 instr
->opcode
= aco_opcode::s_or_b32
;
2805 case aco_opcode::s_xor_b32
:
2806 case aco_opcode::s_xor_b64
:
2807 instr
->opcode
= aco_opcode::s_absdiff_i32
;
2810 /* Don't transform other instructions. They are very unlikely to appear here. */
2814 for (Operand
&op
: instr
->operands
) {
2815 ctx
.uses
[op
.tempId()]--;
2817 if (ctx
.info
[op
.tempId()].is_uniform_bool()) {
2818 /* Just use the uniform boolean temp. */
2819 op
.setTemp(ctx
.info
[op
.tempId()].temp
);
2820 } else if (ctx
.info
[op
.tempId()].is_uniform_bitwise()) {
2821 /* Use the SCC definition of the predecessor instruction.
2822 * This allows the predecessor to get picked up by the same optimization (if it has no divergent users),
2823 * and it also makes sure that the current instruction will keep working even if the predecessor won't be transformed.
2825 Instruction
*pred_instr
= ctx
.info
[op
.tempId()].instr
;
2826 assert(pred_instr
->definitions
.size() >= 2);
2827 assert(pred_instr
->definitions
[1].isFixed() && pred_instr
->definitions
[1].physReg() == scc
);
2828 op
.setTemp(pred_instr
->definitions
[1].getTemp());
2830 unreachable("Invalid operand on uniform bitwise instruction.");
2833 ctx
.uses
[op
.tempId()]++;
2836 instr
->definitions
[0].setTemp(Temp(instr
->definitions
[0].tempId(), s1
));
2837 assert(instr
->operands
[0].regClass() == s1
);
2838 assert(instr
->operands
[1].regClass() == s1
);
2842 void select_instruction(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
2844 const uint32_t threshold
= 4;
2846 if (is_dead(ctx
.uses
, instr
.get())) {
2851 /* convert split_vector into a copy or extract_vector if only one definition is ever used */
2852 if (instr
->opcode
== aco_opcode::p_split_vector
) {
2853 unsigned num_used
= 0;
2855 unsigned split_offset
= 0;
2856 for (unsigned i
= 0, offset
= 0; i
< instr
->definitions
.size(); offset
+= instr
->definitions
[i
++].bytes()) {
2857 if (ctx
.uses
[instr
->definitions
[i
].tempId()]) {
2860 split_offset
= offset
;
2864 if (num_used
== 1 && ctx
.info
[instr
->operands
[0].tempId()].is_vec() &&
2865 ctx
.uses
[instr
->operands
[0].tempId()] == 1) {
2866 Instruction
*vec
= ctx
.info
[instr
->operands
[0].tempId()].instr
;
2870 for (Operand
& vec_op
: vec
->operands
) {
2871 if (off
== split_offset
) {
2875 off
+= vec_op
.bytes();
2877 if (off
!= instr
->operands
[0].bytes() && op
.bytes() == instr
->definitions
[idx
].bytes()) {
2878 ctx
.uses
[instr
->operands
[0].tempId()]--;
2879 for (Operand
& vec_op
: vec
->operands
) {
2880 if (vec_op
.isTemp())
2881 ctx
.uses
[vec_op
.tempId()]--;
2884 ctx
.uses
[op
.tempId()]++;
2886 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 1, 1)};
2887 extract
->operands
[0] = op
;
2888 extract
->definitions
[0] = instr
->definitions
[idx
];
2889 instr
.reset(extract
.release());
2895 if (!done
&& num_used
== 1 &&
2896 instr
->operands
[0].bytes() % instr
->definitions
[idx
].bytes() == 0 &&
2897 split_offset
% instr
->definitions
[idx
].bytes() == 0) {
2898 aco_ptr
<Pseudo_instruction
> extract
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_extract_vector
, Format::PSEUDO
, 2, 1)};
2899 extract
->operands
[0] = instr
->operands
[0];
2900 extract
->operands
[1] = Operand((uint32_t) split_offset
/ instr
->definitions
[idx
].bytes());
2901 extract
->definitions
[0] = instr
->definitions
[idx
];
2902 instr
.reset(extract
.release());
2906 mad_info
* mad_info
= NULL
;
2907 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
2908 mad_info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
2909 /* re-check mad instructions */
2910 if (ctx
.uses
[mad_info
->mul_temp_id
]) {
2911 ctx
.uses
[mad_info
->mul_temp_id
]++;
2912 if (instr
->operands
[0].isTemp())
2913 ctx
.uses
[instr
->operands
[0].tempId()]--;
2914 if (instr
->operands
[1].isTemp())
2915 ctx
.uses
[instr
->operands
[1].tempId()]--;
2916 instr
.swap(mad_info
->add_instr
);
2919 /* check literals */
2920 else if (!instr
->usesModifiers()) {
2921 /* FMA can only take literals on GFX10+ */
2922 if ((instr
->opcode
== aco_opcode::v_fma_f32
|| instr
->opcode
== aco_opcode::v_fma_f16
) &&
2923 ctx
.program
->chip_class
< GFX10
)
2926 bool sgpr_used
= false;
2927 uint32_t literal_idx
= 0;
2928 uint32_t literal_uses
= UINT32_MAX
;
2929 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++)
2931 if (instr
->operands
[i
].isConstant() && i
> 0) {
2932 literal_uses
= UINT32_MAX
;
2935 if (!instr
->operands
[i
].isTemp())
2937 unsigned bits
= get_operand_size(instr
, i
);
2938 /* if one of the operands is sgpr, we cannot add a literal somewhere else on pre-GFX10 or operands other than the 1st */
2939 if (instr
->operands
[i
].getTemp().type() == RegType::sgpr
&& (i
> 0 || ctx
.program
->chip_class
< GFX10
)) {
2940 if (!sgpr_used
&& ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
)) {
2941 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2944 literal_uses
= UINT32_MAX
;
2947 /* don't break because we still need to check constants */
2948 } else if (!sgpr_used
&&
2949 ctx
.info
[instr
->operands
[i
].tempId()].is_literal(bits
) &&
2950 ctx
.uses
[instr
->operands
[i
].tempId()] < literal_uses
) {
2951 literal_uses
= ctx
.uses
[instr
->operands
[i
].tempId()];
2956 /* Limit the number of literals to apply to not increase the code
2957 * size too much, but always apply literals for v_mad->v_madak
2958 * because both instructions are 64-bit and this doesn't increase
2960 * TODO: try to apply the literals earlier to lower the number of
2961 * uses below threshold
2963 if (literal_uses
< threshold
|| literal_idx
== 2) {
2964 ctx
.uses
[instr
->operands
[literal_idx
].tempId()]--;
2965 mad_info
->check_literal
= true;
2966 mad_info
->literal_idx
= literal_idx
;
2972 /* Mark SCC needed, so the uniform boolean transformation won't swap the definitions when it isn't beneficial */
2973 if (instr
->format
== Format::PSEUDO_BRANCH
&&
2974 instr
->operands
.size() &&
2975 instr
->operands
[0].isTemp()) {
2976 ctx
.info
[instr
->operands
[0].tempId()].set_scc_needed();
2978 } else if ((instr
->opcode
== aco_opcode::s_cselect_b64
||
2979 instr
->opcode
== aco_opcode::s_cselect_b32
) &&
2980 instr
->operands
[2].isTemp()) {
2981 ctx
.info
[instr
->operands
[2].tempId()].set_scc_needed();
2984 /* check for literals */
2985 if (!instr
->isSALU() && !instr
->isVALU())
2988 /* Transform uniform bitwise boolean operations to 32-bit when there are no divergent uses. */
2989 if (instr
->definitions
.size() &&
2990 ctx
.uses
[instr
->definitions
[0].tempId()] == 0 &&
2991 ctx
.info
[instr
->definitions
[0].tempId()].is_uniform_bitwise()) {
2992 bool transform_done
= to_uniform_bool_instr(ctx
, instr
);
2994 if (transform_done
&& !ctx
.info
[instr
->definitions
[1].tempId()].is_scc_needed()) {
2995 /* Swap the two definition IDs in order to avoid overusing the SCC. This reduces extra moves generated by RA. */
2996 uint32_t def0_id
= instr
->definitions
[0].getTemp().id();
2997 uint32_t def1_id
= instr
->definitions
[1].getTemp().id();
2998 instr
->definitions
[0].setTemp(Temp(def1_id
, s1
));
2999 instr
->definitions
[1].setTemp(Temp(def0_id
, s1
));
3005 if (instr
->isSDWA() || instr
->isDPP() || (instr
->isVOP3() && ctx
.program
->chip_class
< GFX10
))
3006 return; /* some encodings can't ever take literals */
3008 /* we do not apply the literals yet as we don't know if it is profitable */
3009 Operand
current_literal(s1
);
3011 unsigned literal_id
= 0;
3012 unsigned literal_uses
= UINT32_MAX
;
3013 Operand
literal(s1
);
3014 unsigned num_operands
= 1;
3015 if (instr
->isSALU() || (ctx
.program
->chip_class
>= GFX10
&& can_use_VOP3(ctx
, instr
)))
3016 num_operands
= instr
->operands
.size();
3017 /* catch VOP2 with a 3rd SGPR operand (e.g. v_cndmask_b32, v_addc_co_u32) */
3018 else if (instr
->isVALU() && instr
->operands
.size() >= 3)
3021 unsigned sgpr_ids
[2] = {0, 0};
3022 bool is_literal_sgpr
= false;
3025 /* choose a literal to apply */
3026 for (unsigned i
= 0; i
< num_operands
; i
++) {
3027 Operand op
= instr
->operands
[i
];
3028 unsigned bits
= get_operand_size(instr
, i
);
3030 if (instr
->isVALU() && op
.isTemp() && op
.getTemp().type() == RegType::sgpr
&&
3031 op
.tempId() != sgpr_ids
[0])
3032 sgpr_ids
[!!sgpr_ids
[0]] = op
.tempId();
3034 if (op
.isLiteral()) {
3035 current_literal
= op
;
3037 } else if (!op
.isTemp() || !ctx
.info
[op
.tempId()].is_literal(bits
)) {
3041 if (!alu_can_accept_constant(instr
->opcode
, i
))
3044 if (ctx
.uses
[op
.tempId()] < literal_uses
) {
3045 is_literal_sgpr
= op
.getTemp().type() == RegType::sgpr
;
3047 literal
= Operand(ctx
.info
[op
.tempId()].val
);
3048 literal_uses
= ctx
.uses
[op
.tempId()];
3049 literal_id
= op
.tempId();
3052 mask
|= (op
.tempId() == literal_id
) << i
;
3056 /* don't go over the constant bus limit */
3057 bool is_shift64
= instr
->opcode
== aco_opcode::v_lshlrev_b64
||
3058 instr
->opcode
== aco_opcode::v_lshrrev_b64
||
3059 instr
->opcode
== aco_opcode::v_ashrrev_i64
;
3060 unsigned const_bus_limit
= instr
->isVALU() ? 1 : UINT32_MAX
;
3061 if (ctx
.program
->chip_class
>= GFX10
&& !is_shift64
)
3062 const_bus_limit
= 2;
3064 unsigned num_sgprs
= !!sgpr_ids
[0] + !!sgpr_ids
[1];
3065 if (num_sgprs
== const_bus_limit
&& !is_literal_sgpr
)
3068 if (literal_id
&& literal_uses
< threshold
&&
3069 (current_literal
.isUndefined() ||
3070 (current_literal
.size() == literal
.size() &&
3071 current_literal
.constantValue() == literal
.constantValue()))) {
3072 /* mark the literal to be applied */
3074 unsigned i
= u_bit_scan(&mask
);
3075 if (instr
->operands
[i
].isTemp() && instr
->operands
[i
].tempId() == literal_id
)
3076 ctx
.uses
[instr
->operands
[i
].tempId()]--;
3082 void apply_literals(opt_ctx
&ctx
, aco_ptr
<Instruction
>& instr
)
3084 /* Cleanup Dead Instructions */
3088 /* apply literals on MAD */
3089 if (!instr
->definitions
.empty() && ctx
.info
[instr
->definitions
[0].tempId()].is_mad()) {
3090 mad_info
* info
= &ctx
.mad_infos
[ctx
.info
[instr
->definitions
[0].tempId()].instr
->pass_flags
];
3091 if (info
->check_literal
&&
3092 (ctx
.uses
[instr
->operands
[info
->literal_idx
].tempId()] == 0 || info
->literal_idx
== 2)) {
3093 aco_ptr
<Instruction
> new_mad
;
3095 aco_opcode new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f32
: aco_opcode::v_madmk_f32
;
3096 if (instr
->opcode
== aco_opcode::v_fma_f32
)
3097 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f32
: aco_opcode::v_fmamk_f32
;
3098 else if (instr
->opcode
== aco_opcode::v_mad_f16
|| instr
->opcode
== aco_opcode::v_mad_legacy_f16
)
3099 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_madak_f16
: aco_opcode::v_madmk_f16
;
3100 else if (instr
->opcode
== aco_opcode::v_fma_f16
)
3101 new_op
= info
->literal_idx
== 2 ? aco_opcode::v_fmaak_f16
: aco_opcode::v_fmamk_f16
;
3103 new_mad
.reset(create_instruction
<VOP2_instruction
>(new_op
, Format::VOP2
, 3, 1));
3104 if (info
->literal_idx
== 2) { /* add literal -> madak */
3105 new_mad
->operands
[0] = instr
->operands
[0];
3106 new_mad
->operands
[1] = instr
->operands
[1];
3107 } else { /* mul literal -> madmk */
3108 new_mad
->operands
[0] = instr
->operands
[1 - info
->literal_idx
];
3109 new_mad
->operands
[1] = instr
->operands
[2];
3111 new_mad
->operands
[2] = Operand(ctx
.info
[instr
->operands
[info
->literal_idx
].tempId()].val
);
3112 new_mad
->definitions
[0] = instr
->definitions
[0];
3113 ctx
.instructions
.emplace_back(std::move(new_mad
));
3118 /* apply literals on other SALU/VALU */
3119 if (instr
->isSALU() || instr
->isVALU()) {
3120 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
3121 Operand op
= instr
->operands
[i
];
3122 unsigned bits
= get_operand_size(instr
, i
);
3123 if (op
.isTemp() && ctx
.info
[op
.tempId()].is_literal(bits
) && ctx
.uses
[op
.tempId()] == 0) {
3124 Operand
literal(ctx
.info
[op
.tempId()].val
);
3125 if (instr
->isVALU() && i
> 0)
3126 to_VOP3(ctx
, instr
);
3127 instr
->operands
[i
] = literal
;
3132 ctx
.instructions
.emplace_back(std::move(instr
));
3136 void optimize(Program
* program
)
3139 ctx
.program
= program
;
3140 std::vector
<ssa_info
> info(program
->peekAllocationId());
3141 ctx
.info
= info
.data();
3143 /* 1. Bottom-Up DAG pass (forward) to label all ssa-defs */
3144 for (Block
& block
: program
->blocks
) {
3145 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3146 label_instruction(ctx
, block
, instr
);
3149 ctx
.uses
= dead_code_analysis(program
);
3151 /* 2. Combine v_mad, omod, clamp and propagate sgpr on VALU instructions */
3152 for (Block
& block
: program
->blocks
) {
3153 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3154 combine_instruction(ctx
, block
, instr
);
3157 /* 3. Top-Down DAG pass (backward) to select instructions (includes DCE) */
3158 for (std::vector
<Block
>::reverse_iterator it
= program
->blocks
.rbegin(); it
!= program
->blocks
.rend(); ++it
) {
3159 Block
* block
= &(*it
);
3160 for (std::vector
<aco_ptr
<Instruction
>>::reverse_iterator it
= block
->instructions
.rbegin(); it
!= block
->instructions
.rend(); ++it
)
3161 select_instruction(ctx
, *it
);
3164 /* 4. Add literals to instructions */
3165 for (Block
& block
: program
->blocks
) {
3166 ctx
.instructions
.clear();
3167 for (aco_ptr
<Instruction
>& instr
: block
.instructions
)
3168 apply_literals(ctx
, instr
);
3169 block
.instructions
.swap(ctx
.instructions
);