aco: be more careful combining additions that could wrap into loads/stores
[mesa.git] / src / amd / compiler / aco_optimizer.cpp
1 /*
2 * Copyright © 2018 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Daniel Schürmann (daniel.schuermann@campus.tu-berlin.de)
25 *
26 */
27
28 #include <algorithm>
29 #include <math.h>
30
31 #include "aco_ir.h"
32 #include "util/half_float.h"
33 #include "util/u_math.h"
34
35 namespace aco {
36
37 /**
38 * The optimizer works in 4 phases:
39 * (1) The first pass collects information for each ssa-def,
40 * propagates reg->reg operands of the same type, inline constants
41 * and neg/abs input modifiers.
42 * (2) The second pass combines instructions like mad, omod, clamp and
43 * propagates sgpr's on VALU instructions.
44 * This pass depends on information collected in the first pass.
45 * (3) The third pass goes backwards, and selects instructions,
46 * i.e. decides if a mad instruction is profitable and eliminates dead code.
47 * (4) The fourth pass cleans up the sequence: literals get applied and dead
48 * instructions are removed from the sequence.
49 */
50
51
52 struct mad_info {
53 aco_ptr<Instruction> add_instr;
54 uint32_t mul_temp_id;
55 uint16_t literal_idx;
56 bool check_literal;
57
58 mad_info(aco_ptr<Instruction> instr, uint32_t id)
59 : add_instr(std::move(instr)), mul_temp_id(id), check_literal(false) {}
60 };
61
62 enum Label {
63 label_vec = 1 << 0,
64 label_constant_32bit = 1 << 1,
65 /* label_{abs,neg,mul,omod2,omod4,omod5,clamp} are used for both 16 and
66 * 32-bit operations but this shouldn't cause any issues because we don't
67 * look through any conversions */
68 label_abs = 1 << 2,
69 label_neg = 1 << 3,
70 label_mul = 1 << 4,
71 label_temp = 1 << 5,
72 label_literal = 1 << 6,
73 label_mad = 1 << 7,
74 label_omod2 = 1 << 8,
75 label_omod4 = 1 << 9,
76 label_omod5 = 1 << 10,
77 label_omod_success = 1 << 11,
78 label_clamp = 1 << 12,
79 label_clamp_success = 1 << 13,
80 label_undefined = 1 << 14,
81 label_vcc = 1 << 15,
82 label_b2f = 1 << 16,
83 label_add_sub = 1 << 17,
84 label_bitwise = 1 << 18,
85 label_minmax = 1 << 19,
86 label_vopc = 1 << 20,
87 label_uniform_bool = 1 << 21,
88 label_constant_64bit = 1 << 22,
89 label_uniform_bitwise = 1 << 23,
90 label_scc_invert = 1 << 24,
91 label_vcc_hint = 1 << 25,
92 label_scc_needed = 1 << 26,
93 label_b2i = 1 << 27,
94 label_constant_16bit = 1 << 29,
95 };
96
97 static constexpr uint64_t instr_labels = label_vec | label_mul | label_mad | label_omod_success | label_clamp_success |
98 label_add_sub | label_bitwise | label_uniform_bitwise | label_minmax | label_vopc;
99 static constexpr uint64_t temp_labels = label_abs | label_neg | label_temp | label_vcc | label_b2f | label_uniform_bool |
100 label_omod2 | label_omod4 | label_omod5 | label_clamp | label_scc_invert | label_b2i;
101 static constexpr uint32_t val_labels = label_constant_32bit | label_constant_64bit | label_constant_16bit | label_literal;
102
103 struct ssa_info {
104 uint64_t label;
105 union {
106 uint32_t val;
107 Temp temp;
108 Instruction* instr;
109 };
110
111 ssa_info() : label(0) {}
112
113 void add_label(Label new_label)
114 {
115 /* Since all labels which use "instr" use it for the same thing
116 * (indicating the defining instruction), there is no need to clear
117 * any other instr labels. */
118 if (new_label & instr_labels)
119 label &= ~(temp_labels | val_labels); /* instr, temp and val alias */
120
121 if (new_label & temp_labels) {
122 label &= ~temp_labels;
123 label &= ~(instr_labels | val_labels); /* instr, temp and val alias */
124 }
125
126 uint32_t const_labels = label_literal | label_constant_32bit | label_constant_64bit | label_constant_16bit;
127 if (new_label & const_labels) {
128 label &= ~val_labels | const_labels;
129 label &= ~(instr_labels | temp_labels); /* instr, temp and val alias */
130 } else if (new_label & val_labels) {
131 label &= ~val_labels;
132 label &= ~(instr_labels | temp_labels); /* instr, temp and val alias */
133 }
134
135 label |= new_label;
136 }
137
138 void set_vec(Instruction* vec)
139 {
140 add_label(label_vec);
141 instr = vec;
142 }
143
144 bool is_vec()
145 {
146 return label & label_vec;
147 }
148
149 void set_constant(chip_class chip, uint64_t constant)
150 {
151 Operand op16((uint16_t)constant);
152 Operand op32((uint32_t)constant);
153 add_label(label_literal);
154 val = constant;
155
156 if (chip >= GFX8 && !op16.isLiteral())
157 add_label(label_constant_16bit);
158
159 if (!op32.isLiteral() || ((uint32_t)constant == 0x3e22f983 && chip >= GFX8))
160 add_label(label_constant_32bit);
161
162 if (constant <= 64) {
163 add_label(label_constant_64bit);
164 } else if (constant >= 0xFFFFFFFFFFFFFFF0) { /* [-16 .. -1] */
165 add_label(label_constant_64bit);
166 } else if (constant == 0x3FE0000000000000) { /* 0.5 */
167 add_label(label_constant_64bit);
168 } else if (constant == 0xBFE0000000000000) { /* -0.5 */
169 add_label(label_constant_64bit);
170 } else if (constant == 0x3FF0000000000000) { /* 1.0 */
171 add_label(label_constant_64bit);
172 } else if (constant == 0xBFF0000000000000) { /* -1.0 */
173 add_label(label_constant_64bit);
174 } else if (constant == 0x4000000000000000) { /* 2.0 */
175 add_label(label_constant_64bit);
176 } else if (constant == 0xC000000000000000) { /* -2.0 */
177 add_label(label_constant_64bit);
178 } else if (constant == 0x4010000000000000) { /* 4.0 */
179 add_label(label_constant_64bit);
180 } else if (constant == 0xC010000000000000) { /* -4.0 */
181 add_label(label_constant_64bit);
182 }
183
184 if (label & label_constant_64bit) {
185 val = Operand(constant).constantValue();
186 if (val != constant)
187 label &= ~(label_literal | label_constant_16bit | label_constant_32bit);
188 }
189 }
190
191 bool is_constant(unsigned bits)
192 {
193 switch (bits) {
194 case 8:
195 return label & label_literal;
196 case 16:
197 return label & label_constant_16bit;
198 case 32:
199 return label & label_constant_32bit;
200 case 64:
201 return label & label_constant_64bit;
202 }
203 return false;
204 }
205
206 bool is_literal(unsigned bits)
207 {
208 bool is_lit = label & label_literal;
209 switch (bits) {
210 case 8:
211 return false;
212 case 16:
213 return is_lit && ~(label & label_constant_16bit);
214 case 32:
215 return is_lit && ~(label & label_constant_32bit);
216 case 64:
217 return false;
218 }
219 return false;
220 }
221
222 bool is_constant_or_literal(unsigned bits)
223 {
224 if (bits == 64)
225 return label & label_constant_64bit;
226 else
227 return label & label_literal;
228 }
229
230 void set_abs(Temp abs_temp)
231 {
232 add_label(label_abs);
233 temp = abs_temp;
234 }
235
236 bool is_abs()
237 {
238 return label & label_abs;
239 }
240
241 void set_neg(Temp neg_temp)
242 {
243 add_label(label_neg);
244 temp = neg_temp;
245 }
246
247 bool is_neg()
248 {
249 return label & label_neg;
250 }
251
252 void set_neg_abs(Temp neg_abs_temp)
253 {
254 add_label((Label)((uint32_t)label_abs | (uint32_t)label_neg));
255 temp = neg_abs_temp;
256 }
257
258 void set_mul(Instruction* mul)
259 {
260 add_label(label_mul);
261 instr = mul;
262 }
263
264 bool is_mul()
265 {
266 return label & label_mul;
267 }
268
269 void set_temp(Temp tmp)
270 {
271 add_label(label_temp);
272 temp = tmp;
273 }
274
275 bool is_temp()
276 {
277 return label & label_temp;
278 }
279
280 void set_mad(Instruction* mad, uint32_t mad_info_idx)
281 {
282 add_label(label_mad);
283 mad->pass_flags = mad_info_idx;
284 instr = mad;
285 }
286
287 bool is_mad()
288 {
289 return label & label_mad;
290 }
291
292 void set_omod2(Temp def)
293 {
294 add_label(label_omod2);
295 temp = def;
296 }
297
298 bool is_omod2()
299 {
300 return label & label_omod2;
301 }
302
303 void set_omod4(Temp def)
304 {
305 add_label(label_omod4);
306 temp = def;
307 }
308
309 bool is_omod4()
310 {
311 return label & label_omod4;
312 }
313
314 void set_omod5(Temp def)
315 {
316 add_label(label_omod5);
317 temp = def;
318 }
319
320 bool is_omod5()
321 {
322 return label & label_omod5;
323 }
324
325 void set_omod_success(Instruction* omod_instr)
326 {
327 add_label(label_omod_success);
328 instr = omod_instr;
329 }
330
331 bool is_omod_success()
332 {
333 return label & label_omod_success;
334 }
335
336 void set_clamp(Temp def)
337 {
338 add_label(label_clamp);
339 temp = def;
340 }
341
342 bool is_clamp()
343 {
344 return label & label_clamp;
345 }
346
347 void set_clamp_success(Instruction* clamp_instr)
348 {
349 add_label(label_clamp_success);
350 instr = clamp_instr;
351 }
352
353 bool is_clamp_success()
354 {
355 return label & label_clamp_success;
356 }
357
358 void set_undefined()
359 {
360 add_label(label_undefined);
361 }
362
363 bool is_undefined()
364 {
365 return label & label_undefined;
366 }
367
368 void set_vcc(Temp vcc)
369 {
370 add_label(label_vcc);
371 temp = vcc;
372 }
373
374 bool is_vcc()
375 {
376 return label & label_vcc;
377 }
378
379 void set_b2f(Temp val)
380 {
381 add_label(label_b2f);
382 temp = val;
383 }
384
385 bool is_b2f()
386 {
387 return label & label_b2f;
388 }
389
390 void set_add_sub(Instruction *add_sub_instr)
391 {
392 add_label(label_add_sub);
393 instr = add_sub_instr;
394 }
395
396 bool is_add_sub()
397 {
398 return label & label_add_sub;
399 }
400
401 void set_bitwise(Instruction *bitwise_instr)
402 {
403 add_label(label_bitwise);
404 instr = bitwise_instr;
405 }
406
407 bool is_bitwise()
408 {
409 return label & label_bitwise;
410 }
411
412 void set_uniform_bitwise()
413 {
414 add_label(label_uniform_bitwise);
415 }
416
417 bool is_uniform_bitwise()
418 {
419 return label & label_uniform_bitwise;
420 }
421
422 void set_minmax(Instruction *minmax_instr)
423 {
424 add_label(label_minmax);
425 instr = minmax_instr;
426 }
427
428 bool is_minmax()
429 {
430 return label & label_minmax;
431 }
432
433 void set_vopc(Instruction *vopc_instr)
434 {
435 add_label(label_vopc);
436 instr = vopc_instr;
437 }
438
439 bool is_vopc()
440 {
441 return label & label_vopc;
442 }
443
444 void set_scc_needed()
445 {
446 add_label(label_scc_needed);
447 }
448
449 bool is_scc_needed()
450 {
451 return label & label_scc_needed;
452 }
453
454 void set_scc_invert(Temp scc_inv)
455 {
456 add_label(label_scc_invert);
457 temp = scc_inv;
458 }
459
460 bool is_scc_invert()
461 {
462 return label & label_scc_invert;
463 }
464
465 void set_uniform_bool(Temp uniform_bool)
466 {
467 add_label(label_uniform_bool);
468 temp = uniform_bool;
469 }
470
471 bool is_uniform_bool()
472 {
473 return label & label_uniform_bool;
474 }
475
476 void set_vcc_hint()
477 {
478 add_label(label_vcc_hint);
479 }
480
481 bool is_vcc_hint()
482 {
483 return label & label_vcc_hint;
484 }
485
486 void set_b2i(Temp val)
487 {
488 add_label(label_b2i);
489 temp = val;
490 }
491
492 bool is_b2i()
493 {
494 return label & label_b2i;
495 }
496
497 };
498
499 struct opt_ctx {
500 Program* program;
501 std::vector<aco_ptr<Instruction>> instructions;
502 ssa_info* info;
503 std::pair<uint32_t,Temp> last_literal;
504 std::vector<mad_info> mad_infos;
505 std::vector<uint16_t> uses;
506 };
507
508 struct CmpInfo {
509 aco_opcode ordered;
510 aco_opcode unordered;
511 aco_opcode ordered_swapped;
512 aco_opcode unordered_swapped;
513 aco_opcode inverse;
514 aco_opcode f32;
515 unsigned size;
516 };
517
518 ALWAYS_INLINE bool get_cmp_info(aco_opcode op, CmpInfo *info);
519
520 bool can_swap_operands(aco_ptr<Instruction>& instr)
521 {
522 if (instr->operands[0].isConstant() ||
523 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr))
524 return false;
525
526 switch (instr->opcode) {
527 case aco_opcode::v_add_u32:
528 case aco_opcode::v_add_co_u32:
529 case aco_opcode::v_add_co_u32_e64:
530 case aco_opcode::v_add_i32:
531 case aco_opcode::v_add_f16:
532 case aco_opcode::v_add_f32:
533 case aco_opcode::v_mul_f16:
534 case aco_opcode::v_mul_f32:
535 case aco_opcode::v_or_b32:
536 case aco_opcode::v_and_b32:
537 case aco_opcode::v_xor_b32:
538 case aco_opcode::v_max_f16:
539 case aco_opcode::v_max_f32:
540 case aco_opcode::v_min_f16:
541 case aco_opcode::v_min_f32:
542 case aco_opcode::v_max_i32:
543 case aco_opcode::v_min_i32:
544 case aco_opcode::v_max_u32:
545 case aco_opcode::v_min_u32:
546 case aco_opcode::v_max_i16:
547 case aco_opcode::v_min_i16:
548 case aco_opcode::v_max_u16:
549 case aco_opcode::v_min_u16:
550 case aco_opcode::v_max_i16_e64:
551 case aco_opcode::v_min_i16_e64:
552 case aco_opcode::v_max_u16_e64:
553 case aco_opcode::v_min_u16_e64:
554 return true;
555 case aco_opcode::v_sub_f16:
556 instr->opcode = aco_opcode::v_subrev_f16;
557 return true;
558 case aco_opcode::v_sub_f32:
559 instr->opcode = aco_opcode::v_subrev_f32;
560 return true;
561 case aco_opcode::v_sub_co_u32:
562 instr->opcode = aco_opcode::v_subrev_co_u32;
563 return true;
564 case aco_opcode::v_sub_u16:
565 instr->opcode = aco_opcode::v_subrev_u16;
566 return true;
567 case aco_opcode::v_sub_u32:
568 instr->opcode = aco_opcode::v_subrev_u32;
569 return true;
570 default: {
571 CmpInfo info;
572 get_cmp_info(instr->opcode, &info);
573 if (info.ordered == instr->opcode) {
574 instr->opcode = info.ordered_swapped;
575 return true;
576 }
577 if (info.unordered == instr->opcode) {
578 instr->opcode = info.unordered_swapped;
579 return true;
580 }
581 return false;
582 }
583 }
584 }
585
586 bool can_use_VOP3(opt_ctx& ctx, const aco_ptr<Instruction>& instr)
587 {
588 if (instr->isVOP3())
589 return true;
590
591 if (instr->operands.size() && instr->operands[0].isLiteral() && ctx.program->chip_class < GFX10)
592 return false;
593
594 if (instr->isDPP() || instr->isSDWA())
595 return false;
596
597 return instr->opcode != aco_opcode::v_madmk_f32 &&
598 instr->opcode != aco_opcode::v_madak_f32 &&
599 instr->opcode != aco_opcode::v_madmk_f16 &&
600 instr->opcode != aco_opcode::v_madak_f16 &&
601 instr->opcode != aco_opcode::v_fmamk_f32 &&
602 instr->opcode != aco_opcode::v_fmaak_f32 &&
603 instr->opcode != aco_opcode::v_fmamk_f16 &&
604 instr->opcode != aco_opcode::v_fmaak_f16 &&
605 instr->opcode != aco_opcode::v_readlane_b32 &&
606 instr->opcode != aco_opcode::v_writelane_b32 &&
607 instr->opcode != aco_opcode::v_readfirstlane_b32;
608 }
609
610 bool can_apply_sgprs(aco_ptr<Instruction>& instr)
611 {
612 return instr->opcode != aco_opcode::v_readfirstlane_b32 &&
613 instr->opcode != aco_opcode::v_readlane_b32 &&
614 instr->opcode != aco_opcode::v_readlane_b32_e64 &&
615 instr->opcode != aco_opcode::v_writelane_b32 &&
616 instr->opcode != aco_opcode::v_writelane_b32_e64;
617 }
618
619 void to_VOP3(opt_ctx& ctx, aco_ptr<Instruction>& instr)
620 {
621 if (instr->isVOP3())
622 return;
623
624 aco_ptr<Instruction> tmp = std::move(instr);
625 Format format = asVOP3(tmp->format);
626 instr.reset(create_instruction<VOP3A_instruction>(tmp->opcode, format, tmp->operands.size(), tmp->definitions.size()));
627 std::copy(tmp->operands.cbegin(), tmp->operands.cend(), instr->operands.begin());
628 for (unsigned i = 0; i < instr->definitions.size(); i++) {
629 instr->definitions[i] = tmp->definitions[i];
630 if (instr->definitions[i].isTemp()) {
631 ssa_info& info = ctx.info[instr->definitions[i].tempId()];
632 if (info.label & instr_labels && info.instr == tmp.get())
633 info.instr = instr.get();
634 }
635 }
636 }
637
638 /* only covers special cases */
639 bool alu_can_accept_constant(aco_opcode opcode, unsigned operand)
640 {
641 switch (opcode) {
642 case aco_opcode::v_interp_p2_f32:
643 case aco_opcode::v_mac_f32:
644 case aco_opcode::v_writelane_b32:
645 case aco_opcode::v_writelane_b32_e64:
646 case aco_opcode::v_cndmask_b32:
647 return operand != 2;
648 case aco_opcode::s_addk_i32:
649 case aco_opcode::s_mulk_i32:
650 case aco_opcode::p_wqm:
651 case aco_opcode::p_extract_vector:
652 case aco_opcode::p_split_vector:
653 case aco_opcode::v_readlane_b32:
654 case aco_opcode::v_readlane_b32_e64:
655 case aco_opcode::v_readfirstlane_b32:
656 return operand != 0;
657 default:
658 return true;
659 }
660 }
661
662 bool valu_can_accept_vgpr(aco_ptr<Instruction>& instr, unsigned operand)
663 {
664 if (instr->opcode == aco_opcode::v_readlane_b32 || instr->opcode == aco_opcode::v_readlane_b32_e64 ||
665 instr->opcode == aco_opcode::v_writelane_b32 || instr->opcode == aco_opcode::v_writelane_b32_e64)
666 return operand != 1;
667 return true;
668 }
669
670 /* check constant bus and literal limitations */
671 bool check_vop3_operands(opt_ctx& ctx, unsigned num_operands, Operand *operands)
672 {
673 int limit = ctx.program->chip_class >= GFX10 ? 2 : 1;
674 Operand literal32(s1);
675 Operand literal64(s2);
676 unsigned num_sgprs = 0;
677 unsigned sgpr[] = {0, 0};
678
679 for (unsigned i = 0; i < num_operands; i++) {
680 Operand op = operands[i];
681
682 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) {
683 /* two reads of the same SGPR count as 1 to the limit */
684 if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
685 if (num_sgprs < 2)
686 sgpr[num_sgprs++] = op.tempId();
687 limit--;
688 if (limit < 0)
689 return false;
690 }
691 } else if (op.isLiteral()) {
692 if (ctx.program->chip_class < GFX10)
693 return false;
694
695 if (!literal32.isUndefined() && literal32.constantValue() != op.constantValue())
696 return false;
697 if (!literal64.isUndefined() && literal64.constantValue() != op.constantValue())
698 return false;
699
700 /* Any number of 32-bit literals counts as only 1 to the limit. Same
701 * (but separately) for 64-bit literals. */
702 if (op.size() == 1 && literal32.isUndefined()) {
703 limit--;
704 literal32 = op;
705 } else if (op.size() == 2 && literal64.isUndefined()) {
706 limit--;
707 literal64 = op;
708 }
709
710 if (limit < 0)
711 return false;
712 }
713 }
714
715 return true;
716 }
717
718 bool parse_base_offset(opt_ctx &ctx, Instruction* instr, unsigned op_index, Temp *base, uint32_t *offset, bool prevent_overflow)
719 {
720 if (prevent_overflow)
721 return false; //TODO
722
723 Operand op = instr->operands[op_index];
724
725 if (!op.isTemp())
726 return false;
727 Temp tmp = op.getTemp();
728 if (!ctx.info[tmp.id()].is_add_sub())
729 return false;
730
731 Instruction *add_instr = ctx.info[tmp.id()].instr;
732
733 switch (add_instr->opcode) {
734 case aco_opcode::v_add_u32:
735 case aco_opcode::v_add_co_u32:
736 case aco_opcode::v_add_co_u32_e64:
737 case aco_opcode::s_add_i32:
738 case aco_opcode::s_add_u32:
739 break;
740 default:
741 return false;
742 }
743
744 if (add_instr->usesModifiers())
745 return false;
746
747 for (unsigned i = 0; i < 2; i++) {
748 if (add_instr->operands[i].isConstant()) {
749 *offset = add_instr->operands[i].constantValue();
750 } else if (add_instr->operands[i].isTemp() &&
751 ctx.info[add_instr->operands[i].tempId()].is_constant_or_literal(32)) {
752 *offset = ctx.info[add_instr->operands[i].tempId()].val;
753 } else {
754 continue;
755 }
756 if (!add_instr->operands[!i].isTemp())
757 continue;
758
759 uint32_t offset2 = 0;
760 if (parse_base_offset(ctx, add_instr, !i, base, &offset2, prevent_overflow)) {
761 *offset += offset2;
762 } else {
763 *base = add_instr->operands[!i].getTemp();
764 }
765 return true;
766 }
767
768 return false;
769 }
770
771 unsigned get_operand_size(aco_ptr<Instruction>& instr, unsigned index)
772 {
773 if (instr->format == Format::PSEUDO)
774 return instr->operands[index].bytes() * 8u;
775 else if (instr->opcode == aco_opcode::v_mad_u64_u32 || instr->opcode == aco_opcode::v_mad_i64_i32)
776 return index == 2 ? 64 : 32;
777 else if (instr->isVALU() || instr->isSALU())
778 return instr_info.operand_size[(int)instr->opcode];
779 else
780 return 0;
781 }
782
783 Operand get_constant_op(opt_ctx &ctx, ssa_info info, uint32_t bits)
784 {
785 if (bits == 8)
786 return Operand((uint8_t)info.val);
787 if (bits == 16)
788 return Operand((uint16_t)info.val);
789 // TODO: this functions shouldn't be needed if we store Operand instead of value.
790 Operand op(info.val, bits == 64);
791 if (info.is_literal(32) && info.val == 0x3e22f983 && ctx.program->chip_class >= GFX8)
792 op.setFixed(PhysReg{248}); /* 1/2 PI can be an inline constant on GFX8+ */
793 return op;
794 }
795
796 bool fixed_to_exec(Operand op)
797 {
798 return op.isFixed() && op.physReg() == exec;
799 }
800
801 void label_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
802 {
803 if (instr->isSALU() || instr->isVALU() || instr->format == Format::PSEUDO) {
804 ASSERTED bool all_const = false;
805 for (Operand& op : instr->operands)
806 all_const = all_const && (!op.isTemp() || ctx.info[op.tempId()].is_constant_or_literal(32));
807 perfwarn(all_const, "All instruction operands are constant", instr.get());
808 }
809
810 for (unsigned i = 0; i < instr->operands.size(); i++)
811 {
812 if (!instr->operands[i].isTemp())
813 continue;
814
815 ssa_info info = ctx.info[instr->operands[i].tempId()];
816 /* propagate undef */
817 if (info.is_undefined() && is_phi(instr))
818 instr->operands[i] = Operand(instr->operands[i].regClass());
819 /* propagate reg->reg of same type */
820 if (info.is_temp() && info.temp.regClass() == instr->operands[i].getTemp().regClass()) {
821 instr->operands[i].setTemp(ctx.info[instr->operands[i].tempId()].temp);
822 info = ctx.info[info.temp.id()];
823 }
824
825 /* SALU / PSEUDO: propagate inline constants */
826 if (instr->isSALU() || instr->format == Format::PSEUDO) {
827 bool is_subdword = false;
828 // TODO: optimize SGPR propagation for subdword pseudo instructions on gfx9+
829 if (instr->format == Format::PSEUDO) {
830 is_subdword = std::any_of(instr->definitions.begin(), instr->definitions.end(),
831 [] (const Definition& def) { return def.regClass().is_subdword();});
832 is_subdword = is_subdword || std::any_of(instr->operands.begin(), instr->operands.end(),
833 [] (const Operand& op) { return op.hasRegClass() && op.regClass().is_subdword();});
834 if (is_subdword && ctx.program->chip_class < GFX9)
835 continue;
836 }
837
838 if (info.is_temp() && info.temp.type() == RegType::sgpr) {
839 instr->operands[i].setTemp(info.temp);
840 info = ctx.info[info.temp.id()];
841 } else if (info.is_temp() && info.temp.type() == RegType::vgpr) {
842 /* propagate vgpr if it can take it */
843 switch (instr->opcode) {
844 case aco_opcode::p_create_vector:
845 case aco_opcode::p_split_vector:
846 case aco_opcode::p_extract_vector:
847 case aco_opcode::p_phi: {
848 const bool all_vgpr = std::none_of(instr->definitions.begin(), instr->definitions.end(),
849 [] (const Definition& def) { return def.getTemp().type() != RegType::vgpr;});
850 if (all_vgpr) {
851 instr->operands[i] = Operand(info.temp);
852 info = ctx.info[info.temp.id()];
853 }
854 break;
855 }
856 default:
857 break;
858 }
859 }
860 unsigned bits = get_operand_size(instr, i);
861 if ((info.is_constant(bits) || (!is_subdword && info.is_literal(bits) && instr->format == Format::PSEUDO)) &&
862 !instr->operands[i].isFixed() && alu_can_accept_constant(instr->opcode, i)) {
863 instr->operands[i] = get_constant_op(ctx, info, bits);
864 continue;
865 }
866 }
867
868 /* VALU: propagate neg, abs & inline constants */
869 else if (instr->isVALU()) {
870 if (info.is_temp() && info.temp.type() == RegType::vgpr && valu_can_accept_vgpr(instr, i)) {
871 instr->operands[i].setTemp(info.temp);
872 info = ctx.info[info.temp.id()];
873 }
874
875 /* for instructions other than v_cndmask_b32, the size of the instruction should match the operand size */
876 unsigned can_use_mod = instr->opcode != aco_opcode::v_cndmask_b32 || instr->operands[i].getTemp().bytes() == 4;
877 can_use_mod = can_use_mod && instr_info.can_use_input_modifiers[(int)instr->opcode];
878
879 if (info.is_abs() && (can_use_VOP3(ctx, instr) || instr->isDPP()) && can_use_mod) {
880 if (!instr->isDPP())
881 to_VOP3(ctx, instr);
882 instr->operands[i] = Operand(info.temp);
883 if (instr->isDPP())
884 static_cast<DPP_instruction*>(instr.get())->abs[i] = true;
885 else
886 static_cast<VOP3A_instruction*>(instr.get())->abs[i] = true;
887 }
888 if (info.is_neg() && instr->opcode == aco_opcode::v_add_f32) {
889 instr->opcode = i ? aco_opcode::v_sub_f32 : aco_opcode::v_subrev_f32;
890 instr->operands[i].setTemp(info.temp);
891 continue;
892 } else if (info.is_neg() && instr->opcode == aco_opcode::v_add_f16) {
893 instr->opcode = i ? aco_opcode::v_sub_f16 : aco_opcode::v_subrev_f16;
894 instr->operands[i].setTemp(info.temp);
895 continue;
896 } else if (info.is_neg() && (can_use_VOP3(ctx, instr) || instr->isDPP()) && can_use_mod) {
897 if (!instr->isDPP())
898 to_VOP3(ctx, instr);
899 instr->operands[i].setTemp(info.temp);
900 if (instr->isDPP())
901 static_cast<DPP_instruction*>(instr.get())->neg[i] = true;
902 else
903 static_cast<VOP3A_instruction*>(instr.get())->neg[i] = true;
904 continue;
905 }
906 unsigned bits = get_operand_size(instr, i);
907 if (info.is_constant(bits) && alu_can_accept_constant(instr->opcode, i)) {
908 Operand op = get_constant_op(ctx, info, bits);
909 perfwarn(instr->opcode == aco_opcode::v_cndmask_b32 && i == 2, "v_cndmask_b32 with a constant selector", instr.get());
910 if (i == 0 || instr->opcode == aco_opcode::v_readlane_b32 || instr->opcode == aco_opcode::v_writelane_b32) {
911 instr->operands[i] = op;
912 continue;
913 } else if (!instr->isVOP3() && can_swap_operands(instr)) {
914 instr->operands[i] = instr->operands[0];
915 instr->operands[0] = op;
916 continue;
917 } else if (can_use_VOP3(ctx, instr)) {
918 to_VOP3(ctx, instr);
919 instr->operands[i] = op;
920 continue;
921 }
922 }
923 }
924
925 /* MUBUF: propagate constants and combine additions */
926 else if (instr->format == Format::MUBUF) {
927 MUBUF_instruction *mubuf = static_cast<MUBUF_instruction *>(instr.get());
928 Temp base;
929 uint32_t offset;
930 while (info.is_temp())
931 info = ctx.info[info.temp.id()];
932
933 /* According to AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(), vaddr
934 * overflow for scratch accesses works only on GFX9+ and saddr overflow
935 * never works. Since swizzling is the only thing that separates
936 * scratch accesses and other accesses and swizzling changing how
937 * addressing works significantly, this probably applies to swizzled
938 * MUBUF accesses. */
939 bool vaddr_prevent_overflow = mubuf->swizzled && ctx.program->chip_class < GFX9;
940 bool saddr_prevent_overflow = mubuf->swizzled;
941
942 if (mubuf->offen && i == 1 && info.is_constant_or_literal(32) && mubuf->offset + info.val < 4096) {
943 assert(!mubuf->idxen);
944 instr->operands[1] = Operand(v1);
945 mubuf->offset += info.val;
946 mubuf->offen = false;
947 continue;
948 } else if (i == 2 && info.is_constant_or_literal(32) && mubuf->offset + info.val < 4096) {
949 instr->operands[2] = Operand((uint32_t) 0);
950 mubuf->offset += info.val;
951 continue;
952 } else if (mubuf->offen && i == 1 && parse_base_offset(ctx, instr.get(), i, &base, &offset, vaddr_prevent_overflow) &&
953 base.regClass() == v1 && mubuf->offset + offset < 4096) {
954 assert(!mubuf->idxen);
955 instr->operands[1].setTemp(base);
956 mubuf->offset += offset;
957 continue;
958 } else if (i == 2 && parse_base_offset(ctx, instr.get(), i, &base, &offset, saddr_prevent_overflow) &&
959 base.regClass() == s1 && mubuf->offset + offset < 4096) {
960 instr->operands[i].setTemp(base);
961 mubuf->offset += offset;
962 continue;
963 }
964 }
965
966 /* DS: combine additions */
967 else if (instr->format == Format::DS) {
968
969 DS_instruction *ds = static_cast<DS_instruction *>(instr.get());
970 Temp base;
971 uint32_t offset;
972 bool has_usable_ds_offset = ctx.program->chip_class >= GFX7;
973 if (has_usable_ds_offset &&
974 i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset, false) &&
975 base.regClass() == instr->operands[i].regClass() &&
976 instr->opcode != aco_opcode::ds_swizzle_b32) {
977 if (instr->opcode == aco_opcode::ds_write2_b32 || instr->opcode == aco_opcode::ds_read2_b32 ||
978 instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) {
979 unsigned mask = (instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) ? 0x7 : 0x3;
980 unsigned shifts = (instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) ? 3 : 2;
981
982 if ((offset & mask) == 0 &&
983 ds->offset0 + (offset >> shifts) <= 255 &&
984 ds->offset1 + (offset >> shifts) <= 255) {
985 instr->operands[i].setTemp(base);
986 ds->offset0 += offset >> shifts;
987 ds->offset1 += offset >> shifts;
988 }
989 } else {
990 if (ds->offset0 + offset <= 65535) {
991 instr->operands[i].setTemp(base);
992 ds->offset0 += offset;
993 }
994 }
995 }
996 }
997
998 /* SMEM: propagate constants and combine additions */
999 else if (instr->format == Format::SMEM) {
1000
1001 SMEM_instruction *smem = static_cast<SMEM_instruction *>(instr.get());
1002 Temp base;
1003 uint32_t offset;
1004 if (i == 1 && info.is_constant_or_literal(32) &&
1005 ((ctx.program->chip_class == GFX6 && info.val <= 0x3FF) ||
1006 (ctx.program->chip_class == GFX7 && info.val <= 0xFFFFFFFF) ||
1007 (ctx.program->chip_class >= GFX8 && info.val <= 0xFFFFF))) {
1008 instr->operands[i] = Operand(info.val);
1009 continue;
1010 } else if (i == 1 && parse_base_offset(ctx, instr.get(), i, &base, &offset, true) && base.regClass() == s1 && offset <= 0xFFFFF && ctx.program->chip_class >= GFX9) {
1011 bool soe = smem->operands.size() >= (!smem->definitions.empty() ? 3 : 4);
1012 if (soe &&
1013 (!ctx.info[smem->operands.back().tempId()].is_constant_or_literal(32) ||
1014 ctx.info[smem->operands.back().tempId()].val != 0)) {
1015 continue;
1016 }
1017 if (soe) {
1018 smem->operands[1] = Operand(offset);
1019 smem->operands.back() = Operand(base);
1020 } else {
1021 SMEM_instruction *new_instr = create_instruction<SMEM_instruction>(smem->opcode, Format::SMEM, smem->operands.size() + 1, smem->definitions.size());
1022 new_instr->operands[0] = smem->operands[0];
1023 new_instr->operands[1] = Operand(offset);
1024 if (smem->definitions.empty())
1025 new_instr->operands[2] = smem->operands[2];
1026 new_instr->operands.back() = Operand(base);
1027 if (!smem->definitions.empty())
1028 new_instr->definitions[0] = smem->definitions[0];
1029 new_instr->can_reorder = smem->can_reorder;
1030 new_instr->barrier = smem->barrier;
1031 new_instr->glc = smem->glc;
1032 new_instr->dlc = smem->dlc;
1033 new_instr->nv = smem->nv;
1034 new_instr->disable_wqm = smem->disable_wqm;
1035 instr.reset(new_instr);
1036 smem = static_cast<SMEM_instruction *>(instr.get());
1037 }
1038 continue;
1039 }
1040 }
1041
1042 else if (instr->format == Format::PSEUDO_BRANCH) {
1043 if (ctx.info[instr->operands[0].tempId()].is_scc_invert()) {
1044 /* Flip the branch instruction to get rid of the scc_invert instruction */
1045 instr->opcode = instr->opcode == aco_opcode::p_cbranch_z ? aco_opcode::p_cbranch_nz : aco_opcode::p_cbranch_z;
1046 instr->operands[0].setTemp(ctx.info[instr->operands[0].tempId()].temp);
1047 }
1048 }
1049 }
1050
1051 /* if this instruction doesn't define anything, return */
1052 if (instr->definitions.empty())
1053 return;
1054
1055 if ((uint16_t) instr->format & (uint16_t) Format::VOPC) {
1056 ctx.info[instr->definitions[0].tempId()].set_vopc(instr.get());
1057 return;
1058 }
1059
1060 switch (instr->opcode) {
1061 case aco_opcode::p_create_vector: {
1062 bool copy_prop = instr->operands.size() == 1 && instr->operands[0].isTemp() &&
1063 instr->operands[0].regClass() == instr->definitions[0].regClass();
1064 if (copy_prop) {
1065 ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
1066 break;
1067 }
1068
1069 unsigned num_ops = instr->operands.size();
1070 for (const Operand& op : instr->operands) {
1071 if (op.isTemp() && ctx.info[op.tempId()].is_vec())
1072 num_ops += ctx.info[op.tempId()].instr->operands.size() - 1;
1073 }
1074 if (num_ops != instr->operands.size()) {
1075 aco_ptr<Instruction> old_vec = std::move(instr);
1076 instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_ops, 1));
1077 instr->definitions[0] = old_vec->definitions[0];
1078 unsigned k = 0;
1079 for (Operand& old_op : old_vec->operands) {
1080 if (old_op.isTemp() && ctx.info[old_op.tempId()].is_vec()) {
1081 for (unsigned j = 0; j < ctx.info[old_op.tempId()].instr->operands.size(); j++) {
1082 Operand op = ctx.info[old_op.tempId()].instr->operands[j];
1083 if (op.isTemp() && ctx.info[op.tempId()].is_temp() &&
1084 ctx.info[op.tempId()].temp.type() == instr->definitions[0].regClass().type())
1085 op.setTemp(ctx.info[op.tempId()].temp);
1086 instr->operands[k++] = op;
1087 }
1088 } else {
1089 instr->operands[k++] = old_op;
1090 }
1091 }
1092 assert(k == num_ops);
1093 }
1094
1095 ctx.info[instr->definitions[0].tempId()].set_vec(instr.get());
1096 break;
1097 }
1098 case aco_opcode::p_split_vector: {
1099 ssa_info& info = ctx.info[instr->operands[0].tempId()];
1100
1101 if (info.is_constant_or_literal(32)) {
1102 uint32_t val = info.val;
1103 for (Definition def : instr->definitions) {
1104 uint32_t mask = u_bit_consecutive(0, def.bytes() * 8u);
1105 ctx.info[def.tempId()].set_constant(ctx.program->chip_class, val & mask);
1106 val >>= def.bytes() * 8u;
1107 }
1108 break;
1109 } else if (!info.is_vec()) {
1110 break;
1111 }
1112
1113 Instruction* vec = ctx.info[instr->operands[0].tempId()].instr;
1114 unsigned split_offset = 0;
1115 unsigned vec_offset = 0;
1116 unsigned vec_index = 0;
1117 for (unsigned i = 0; i < instr->definitions.size(); split_offset += instr->definitions[i++].bytes()) {
1118 while (vec_offset < split_offset && vec_index < vec->operands.size())
1119 vec_offset += vec->operands[vec_index++].bytes();
1120
1121 if (vec_offset != split_offset || vec->operands[vec_index].bytes() != instr->definitions[i].bytes())
1122 continue;
1123
1124 Operand vec_op = vec->operands[vec_index];
1125 if (vec_op.isConstant()) {
1126 ctx.info[instr->definitions[i].tempId()].set_constant(ctx.program->chip_class, vec_op.constantValue64());
1127 } else if (vec_op.isUndefined()) {
1128 ctx.info[instr->definitions[i].tempId()].set_undefined();
1129 } else {
1130 assert(vec_op.isTemp());
1131 ctx.info[instr->definitions[i].tempId()].set_temp(vec_op.getTemp());
1132 }
1133 }
1134 break;
1135 }
1136 case aco_opcode::p_extract_vector: { /* mov */
1137 ssa_info& info = ctx.info[instr->operands[0].tempId()];
1138 const unsigned index = instr->operands[1].constantValue();
1139 const unsigned dst_offset = index * instr->definitions[0].bytes();
1140
1141 if (info.is_constant_or_literal(32)) {
1142 uint32_t mask = u_bit_consecutive(0, instr->definitions[0].bytes() * 8u);
1143 ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, (info.val >> (dst_offset * 8u)) & mask);
1144 break;
1145 } else if (!info.is_vec()) {
1146 break;
1147 }
1148
1149 /* check if we index directly into a vector element */
1150 Instruction* vec = info.instr;
1151 unsigned offset = 0;
1152
1153 for (const Operand& op : vec->operands) {
1154 if (offset < dst_offset) {
1155 offset += op.bytes();
1156 continue;
1157 } else if (offset != dst_offset || op.bytes() != instr->definitions[0].bytes()) {
1158 break;
1159 }
1160
1161 /* convert this extract into a copy instruction */
1162 instr->opcode = aco_opcode::p_parallelcopy;
1163 instr->operands.pop_back();
1164 instr->operands[0] = op;
1165
1166 if (op.isConstant()) {
1167 ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, op.constantValue64());
1168 } else if (op.isUndefined()) {
1169 ctx.info[instr->definitions[0].tempId()].set_undefined();
1170 } else {
1171 assert(op.isTemp());
1172 ctx.info[instr->definitions[0].tempId()].set_temp(op.getTemp());
1173 }
1174 break;
1175 }
1176 break;
1177 }
1178 case aco_opcode::s_mov_b32: /* propagate */
1179 case aco_opcode::s_mov_b64:
1180 case aco_opcode::v_mov_b32:
1181 case aco_opcode::p_as_uniform:
1182 if (instr->definitions[0].isFixed()) {
1183 /* don't copy-propagate copies into fixed registers */
1184 } else if (instr->usesModifiers()) {
1185 // TODO
1186 } else if (instr->operands[0].isConstant()) {
1187 ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, instr->operands[0].constantValue64());
1188 } else if (instr->operands[0].isTemp()) {
1189 ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
1190 } else {
1191 assert(instr->operands[0].isFixed());
1192 }
1193 break;
1194 case aco_opcode::p_is_helper:
1195 if (!ctx.program->needs_wqm)
1196 ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, 0u);
1197 break;
1198 case aco_opcode::s_movk_i32: {
1199 uint32_t v = static_cast<SOPK_instruction*>(instr.get())->imm;
1200 v = v & 0x8000 ? (v | 0xffff0000) : v;
1201 ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, v);
1202 break;
1203 }
1204 case aco_opcode::v_bfrev_b32:
1205 case aco_opcode::s_brev_b32: {
1206 if (instr->operands[0].isConstant()) {
1207 uint32_t v = util_bitreverse(instr->operands[0].constantValue());
1208 ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, v);
1209 }
1210 break;
1211 }
1212 case aco_opcode::s_bfm_b32: {
1213 if (instr->operands[0].isConstant() && instr->operands[1].isConstant()) {
1214 unsigned size = instr->operands[0].constantValue() & 0x1f;
1215 unsigned start = instr->operands[1].constantValue() & 0x1f;
1216 uint32_t v = ((1u << size) - 1u) << start;
1217 ctx.info[instr->definitions[0].tempId()].set_constant(ctx.program->chip_class, v);
1218 }
1219 break;
1220 }
1221 case aco_opcode::v_mul_f16:
1222 case aco_opcode::v_mul_f32: { /* omod */
1223 /* TODO: try to move the negate/abs modifier to the consumer instead */
1224 if (instr->usesModifiers())
1225 break;
1226
1227 bool fp16 = instr->opcode == aco_opcode::v_mul_f16;
1228
1229 for (unsigned i = 0; i < 2; i++) {
1230 if (instr->operands[!i].isConstant() && instr->operands[i].isTemp()) {
1231 if (instr->operands[!i].constantValue() == (fp16 ? 0x4000 : 0x40000000)) { /* 2.0 */
1232 ctx.info[instr->operands[i].tempId()].set_omod2(instr->definitions[0].getTemp());
1233 } else if (instr->operands[!i].constantValue() == (fp16 ? 0x4400 : 0x40800000)) { /* 4.0 */
1234 ctx.info[instr->operands[i].tempId()].set_omod4(instr->definitions[0].getTemp());
1235 } else if (instr->operands[!i].constantValue() == (fp16 ? 0xb800 : 0x3f000000)) { /* 0.5 */
1236 ctx.info[instr->operands[i].tempId()].set_omod5(instr->definitions[0].getTemp());
1237 } else if (instr->operands[!i].constantValue() == (fp16 ? 0x3c00 : 0x3f800000) &&
1238 !(fp16 ? block.fp_mode.must_flush_denorms16_64 : block.fp_mode.must_flush_denorms32)) { /* 1.0 */
1239 ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[i].getTemp());
1240 } else {
1241 continue;
1242 }
1243 break;
1244 }
1245 }
1246 break;
1247 }
1248 case aco_opcode::v_and_b32: { /* abs */
1249 if (!instr->usesModifiers() && instr->operands[1].isTemp() &&
1250 instr->operands[1].getTemp().type() == RegType::vgpr &&
1251 ((instr->definitions[0].bytes() == 4 && instr->operands[0].constantEquals(0x7FFFFFFFu)) ||
1252 (instr->definitions[0].bytes() == 2 && instr->operands[0].constantEquals(0x7FFFu))))
1253 ctx.info[instr->definitions[0].tempId()].set_abs(instr->operands[1].getTemp());
1254 else
1255 ctx.info[instr->definitions[0].tempId()].set_bitwise(instr.get());
1256 break;
1257 }
1258 case aco_opcode::v_xor_b32: { /* neg */
1259 if (!instr->usesModifiers() && instr->operands[1].isTemp() &&
1260 ((instr->definitions[0].bytes() == 4 && instr->operands[0].constantEquals(0x80000000u)) ||
1261 (instr->definitions[0].bytes() == 2 && instr->operands[0].constantEquals(0x8000u)))) {
1262 if (ctx.info[instr->operands[1].tempId()].is_neg()) {
1263 ctx.info[instr->definitions[0].tempId()].set_temp(ctx.info[instr->operands[1].tempId()].temp);
1264 } else if (instr->operands[1].getTemp().type() == RegType::vgpr) {
1265 if (ctx.info[instr->operands[1].tempId()].is_abs()) { /* neg(abs(x)) */
1266 instr->operands[1].setTemp(ctx.info[instr->operands[1].tempId()].temp);
1267 instr->opcode = aco_opcode::v_or_b32;
1268 ctx.info[instr->definitions[0].tempId()].set_neg_abs(instr->operands[1].getTemp());
1269 } else {
1270 ctx.info[instr->definitions[0].tempId()].set_neg(instr->operands[1].getTemp());
1271 }
1272 }
1273 } else {
1274 ctx.info[instr->definitions[0].tempId()].set_bitwise(instr.get());
1275 }
1276 break;
1277 }
1278 case aco_opcode::v_med3_f16:
1279 case aco_opcode::v_med3_f32: { /* clamp */
1280 VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(instr.get());
1281 if (vop3->abs[0] || vop3->abs[1] || vop3->abs[2] ||
1282 vop3->neg[0] || vop3->neg[1] || vop3->neg[2] ||
1283 vop3->omod != 0 || vop3->opsel != 0)
1284 break;
1285
1286 unsigned idx = 0;
1287 bool found_zero = false, found_one = false;
1288 bool is_fp16 = instr->opcode == aco_opcode::v_med3_f16;
1289 for (unsigned i = 0; i < 3; i++)
1290 {
1291 if (instr->operands[i].constantEquals(0))
1292 found_zero = true;
1293 else if (instr->operands[i].constantEquals(is_fp16 ? 0x3c00 : 0x3f800000)) /* 1.0 */
1294 found_one = true;
1295 else
1296 idx = i;
1297 }
1298 if (found_zero && found_one && instr->operands[idx].isTemp()) {
1299 ctx.info[instr->operands[idx].tempId()].set_clamp(instr->definitions[0].getTemp());
1300 }
1301 break;
1302 }
1303 case aco_opcode::v_cndmask_b32:
1304 if (instr->operands[0].constantEquals(0) &&
1305 instr->operands[1].constantEquals(0xFFFFFFFF))
1306 ctx.info[instr->definitions[0].tempId()].set_vcc(instr->operands[2].getTemp());
1307 else if (instr->operands[0].constantEquals(0) &&
1308 instr->operands[1].constantEquals(0x3f800000u))
1309 ctx.info[instr->definitions[0].tempId()].set_b2f(instr->operands[2].getTemp());
1310 else if (instr->operands[0].constantEquals(0) &&
1311 instr->operands[1].constantEquals(1))
1312 ctx.info[instr->definitions[0].tempId()].set_b2i(instr->operands[2].getTemp());
1313
1314 ctx.info[instr->operands[2].tempId()].set_vcc_hint();
1315 break;
1316 case aco_opcode::v_cmp_lg_u32:
1317 if (instr->format == Format::VOPC && /* don't optimize VOP3 / SDWA / DPP */
1318 instr->operands[0].constantEquals(0) &&
1319 instr->operands[1].isTemp() && ctx.info[instr->operands[1].tempId()].is_vcc())
1320 ctx.info[instr->definitions[0].tempId()].set_temp(ctx.info[instr->operands[1].tempId()].temp);
1321 break;
1322 case aco_opcode::p_phi:
1323 case aco_opcode::p_linear_phi: {
1324 /* lower_bool_phis() can create phis like this */
1325 bool all_same_temp = instr->operands[0].isTemp();
1326 /* this check is needed when moving uniform loop counters out of a divergent loop */
1327 if (all_same_temp)
1328 all_same_temp = instr->definitions[0].regClass() == instr->operands[0].regClass();
1329 for (unsigned i = 1; all_same_temp && (i < instr->operands.size()); i++) {
1330 if (!instr->operands[i].isTemp() || instr->operands[i].tempId() != instr->operands[0].tempId())
1331 all_same_temp = false;
1332 }
1333 if (all_same_temp) {
1334 ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
1335 } else {
1336 bool all_undef = instr->operands[0].isUndefined();
1337 for (unsigned i = 1; all_undef && (i < instr->operands.size()); i++) {
1338 if (!instr->operands[i].isUndefined())
1339 all_undef = false;
1340 }
1341 if (all_undef)
1342 ctx.info[instr->definitions[0].tempId()].set_undefined();
1343 }
1344 break;
1345 }
1346 case aco_opcode::v_add_u32:
1347 case aco_opcode::v_add_co_u32:
1348 case aco_opcode::v_add_co_u32_e64:
1349 case aco_opcode::s_add_i32:
1350 case aco_opcode::s_add_u32:
1351 ctx.info[instr->definitions[0].tempId()].set_add_sub(instr.get());
1352 break;
1353 case aco_opcode::s_not_b32:
1354 case aco_opcode::s_not_b64:
1355 if (ctx.info[instr->operands[0].tempId()].is_uniform_bool()) {
1356 ctx.info[instr->definitions[0].tempId()].set_uniform_bitwise();
1357 ctx.info[instr->definitions[1].tempId()].set_scc_invert(ctx.info[instr->operands[0].tempId()].temp);
1358 } else if (ctx.info[instr->operands[0].tempId()].is_uniform_bitwise()) {
1359 ctx.info[instr->definitions[0].tempId()].set_uniform_bitwise();
1360 ctx.info[instr->definitions[1].tempId()].set_scc_invert(ctx.info[instr->operands[0].tempId()].instr->definitions[1].getTemp());
1361 }
1362 ctx.info[instr->definitions[0].tempId()].set_bitwise(instr.get());
1363 break;
1364 case aco_opcode::s_and_b32:
1365 case aco_opcode::s_and_b64:
1366 if (fixed_to_exec(instr->operands[1]) && instr->operands[0].isTemp()) {
1367 if (ctx.info[instr->operands[0].tempId()].is_uniform_bool()) {
1368 /* Try to get rid of the superfluous s_cselect + s_and_b64 that comes from turning a uniform bool into divergent */
1369 ctx.info[instr->definitions[1].tempId()].set_temp(ctx.info[instr->operands[0].tempId()].temp);
1370 ctx.info[instr->definitions[0].tempId()].set_uniform_bool(ctx.info[instr->operands[0].tempId()].temp);
1371 break;
1372 } else if (ctx.info[instr->operands[0].tempId()].is_uniform_bitwise()) {
1373 /* Try to get rid of the superfluous s_and_b64, since the uniform bitwise instruction already produces the same SCC */
1374 ctx.info[instr->definitions[1].tempId()].set_temp(ctx.info[instr->operands[0].tempId()].instr->definitions[1].getTemp());
1375 ctx.info[instr->definitions[0].tempId()].set_uniform_bool(ctx.info[instr->operands[0].tempId()].instr->definitions[1].getTemp());
1376 break;
1377 } else if (ctx.info[instr->operands[0].tempId()].is_vopc()) {
1378 Instruction* vopc_instr = ctx.info[instr->operands[0].tempId()].instr;
1379 /* Remove superfluous s_and when the VOPC instruction uses the same exec and thus already produces the same result */
1380 if (vopc_instr->pass_flags == instr->pass_flags) {
1381 assert(instr->pass_flags > 0);
1382 ctx.info[instr->definitions[0].tempId()].set_temp(vopc_instr->definitions[0].getTemp());
1383 break;
1384 }
1385 }
1386 }
1387 /* fallthrough */
1388 case aco_opcode::s_or_b32:
1389 case aco_opcode::s_or_b64:
1390 case aco_opcode::s_xor_b32:
1391 case aco_opcode::s_xor_b64:
1392 if (std::all_of(instr->operands.begin(), instr->operands.end(), [&ctx](const Operand& op) {
1393 return op.isTemp() && (ctx.info[op.tempId()].is_uniform_bool() || ctx.info[op.tempId()].is_uniform_bitwise());
1394 })) {
1395 ctx.info[instr->definitions[0].tempId()].set_uniform_bitwise();
1396 }
1397 /* fallthrough */
1398 case aco_opcode::s_lshl_b32:
1399 case aco_opcode::v_or_b32:
1400 case aco_opcode::v_lshlrev_b32:
1401 ctx.info[instr->definitions[0].tempId()].set_bitwise(instr.get());
1402 break;
1403 case aco_opcode::v_min_f32:
1404 case aco_opcode::v_min_f16:
1405 case aco_opcode::v_min_u32:
1406 case aco_opcode::v_min_i32:
1407 case aco_opcode::v_min_u16:
1408 case aco_opcode::v_min_i16:
1409 case aco_opcode::v_max_f32:
1410 case aco_opcode::v_max_f16:
1411 case aco_opcode::v_max_u32:
1412 case aco_opcode::v_max_i32:
1413 case aco_opcode::v_max_u16:
1414 case aco_opcode::v_max_i16:
1415 ctx.info[instr->definitions[0].tempId()].set_minmax(instr.get());
1416 break;
1417 case aco_opcode::s_cselect_b64:
1418 case aco_opcode::s_cselect_b32:
1419 if (instr->operands[0].constantEquals((unsigned) -1) &&
1420 instr->operands[1].constantEquals(0)) {
1421 /* Found a cselect that operates on a uniform bool that comes from eg. s_cmp */
1422 ctx.info[instr->definitions[0].tempId()].set_uniform_bool(instr->operands[2].getTemp());
1423 }
1424 if (instr->operands[2].isTemp() && ctx.info[instr->operands[2].tempId()].is_scc_invert()) {
1425 /* Flip the operands to get rid of the scc_invert instruction */
1426 std::swap(instr->operands[0], instr->operands[1]);
1427 instr->operands[2].setTemp(ctx.info[instr->operands[2].tempId()].temp);
1428 }
1429 break;
1430 case aco_opcode::p_wqm:
1431 if (instr->operands[0].isTemp() &&
1432 ctx.info[instr->operands[0].tempId()].is_scc_invert()) {
1433 ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
1434 }
1435 break;
1436 default:
1437 break;
1438 }
1439 }
1440
1441 ALWAYS_INLINE bool get_cmp_info(aco_opcode op, CmpInfo *info)
1442 {
1443 info->ordered = aco_opcode::num_opcodes;
1444 info->unordered = aco_opcode::num_opcodes;
1445 info->ordered_swapped = aco_opcode::num_opcodes;
1446 info->unordered_swapped = aco_opcode::num_opcodes;
1447 switch (op) {
1448 #define CMP2(ord, unord, ord_swap, unord_swap, sz) \
1449 case aco_opcode::v_cmp_##ord##_f##sz:\
1450 case aco_opcode::v_cmp_n##unord##_f##sz:\
1451 info->ordered = aco_opcode::v_cmp_##ord##_f##sz;\
1452 info->unordered = aco_opcode::v_cmp_n##unord##_f##sz;\
1453 info->ordered_swapped = aco_opcode::v_cmp_##ord_swap##_f##sz;\
1454 info->unordered_swapped = aco_opcode::v_cmp_n##unord_swap##_f##sz;\
1455 info->inverse = op == aco_opcode::v_cmp_n##unord##_f##sz ? aco_opcode::v_cmp_##unord##_f##sz : aco_opcode::v_cmp_n##ord##_f##sz;\
1456 info->f32 = op == aco_opcode::v_cmp_##ord##_f##sz ? aco_opcode::v_cmp_##ord##_f32 : aco_opcode::v_cmp_n##unord##_f32;\
1457 info->size = sz;\
1458 return true;
1459 #define CMP(ord, unord, ord_swap, unord_swap) \
1460 CMP2(ord, unord, ord_swap, unord_swap, 16)\
1461 CMP2(ord, unord, ord_swap, unord_swap, 32)\
1462 CMP2(ord, unord, ord_swap, unord_swap, 64)
1463 CMP(lt, /*n*/ge, gt, /*n*/le)
1464 CMP(eq, /*n*/lg, eq, /*n*/lg)
1465 CMP(le, /*n*/gt, ge, /*n*/lt)
1466 CMP(gt, /*n*/le, lt, /*n*/le)
1467 CMP(lg, /*n*/eq, lg, /*n*/eq)
1468 CMP(ge, /*n*/lt, le, /*n*/gt)
1469 #undef CMP
1470 #undef CMP2
1471 #define ORD_TEST(sz) \
1472 case aco_opcode::v_cmp_u_f##sz:\
1473 info->f32 = aco_opcode::v_cmp_u_f32;\
1474 info->inverse = aco_opcode::v_cmp_o_f##sz;\
1475 info->size = sz;\
1476 return true;\
1477 case aco_opcode::v_cmp_o_f##sz:\
1478 info->f32 = aco_opcode::v_cmp_o_f32;\
1479 info->inverse = aco_opcode::v_cmp_u_f##sz;\
1480 info->size = sz;\
1481 return true;
1482 ORD_TEST(16)
1483 ORD_TEST(32)
1484 ORD_TEST(64)
1485 #undef ORD_TEST
1486 default:
1487 return false;
1488 }
1489 }
1490
1491 aco_opcode get_ordered(aco_opcode op)
1492 {
1493 CmpInfo info;
1494 return get_cmp_info(op, &info) ? info.ordered : aco_opcode::num_opcodes;
1495 }
1496
1497 aco_opcode get_unordered(aco_opcode op)
1498 {
1499 CmpInfo info;
1500 return get_cmp_info(op, &info) ? info.unordered : aco_opcode::num_opcodes;
1501 }
1502
1503 aco_opcode get_inverse(aco_opcode op)
1504 {
1505 CmpInfo info;
1506 return get_cmp_info(op, &info) ? info.inverse : aco_opcode::num_opcodes;
1507 }
1508
1509 aco_opcode get_f32_cmp(aco_opcode op)
1510 {
1511 CmpInfo info;
1512 return get_cmp_info(op, &info) ? info.f32 : aco_opcode::num_opcodes;
1513 }
1514
1515 unsigned get_cmp_bitsize(aco_opcode op)
1516 {
1517 CmpInfo info;
1518 return get_cmp_info(op, &info) ? info.size : 0;
1519 }
1520
1521 bool is_cmp(aco_opcode op)
1522 {
1523 CmpInfo info;
1524 return get_cmp_info(op, &info) && info.ordered != aco_opcode::num_opcodes;
1525 }
1526
1527 unsigned original_temp_id(opt_ctx &ctx, Temp tmp)
1528 {
1529 if (ctx.info[tmp.id()].is_temp())
1530 return ctx.info[tmp.id()].temp.id();
1531 else
1532 return tmp.id();
1533 }
1534
1535 void decrease_uses(opt_ctx &ctx, Instruction* instr)
1536 {
1537 if (!--ctx.uses[instr->definitions[0].tempId()]) {
1538 for (const Operand& op : instr->operands) {
1539 if (op.isTemp())
1540 ctx.uses[op.tempId()]--;
1541 }
1542 }
1543 }
1544
1545 Instruction *follow_operand(opt_ctx &ctx, Operand op, bool ignore_uses=false)
1546 {
1547 if (!op.isTemp() || !(ctx.info[op.tempId()].label & instr_labels))
1548 return nullptr;
1549 if (!ignore_uses && ctx.uses[op.tempId()] > 1)
1550 return nullptr;
1551
1552 Instruction *instr = ctx.info[op.tempId()].instr;
1553
1554 if (instr->definitions.size() == 2) {
1555 assert(instr->definitions[0].isTemp() && instr->definitions[0].tempId() == op.tempId());
1556 if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
1557 return nullptr;
1558 }
1559
1560 return instr;
1561 }
1562
1563 /* s_or_b64(neq(a, a), neq(b, b)) -> v_cmp_u_f32(a, b)
1564 * s_and_b64(eq(a, a), eq(b, b)) -> v_cmp_o_f32(a, b) */
1565 bool combine_ordering_test(opt_ctx &ctx, aco_ptr<Instruction>& instr)
1566 {
1567 if (instr->definitions[0].regClass() != ctx.program->lane_mask)
1568 return false;
1569 if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
1570 return false;
1571
1572 bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32;
1573
1574 bool neg[2] = {false, false};
1575 bool abs[2] = {false, false};
1576 uint8_t opsel = 0;
1577 Instruction *op_instr[2];
1578 Temp op[2];
1579
1580 unsigned bitsize = 0;
1581 for (unsigned i = 0; i < 2; i++) {
1582 op_instr[i] = follow_operand(ctx, instr->operands[i], true);
1583 if (!op_instr[i])
1584 return false;
1585
1586 aco_opcode expected_cmp = is_or ? aco_opcode::v_cmp_neq_f32 : aco_opcode::v_cmp_eq_f32;
1587 unsigned op_bitsize = get_cmp_bitsize(op_instr[i]->opcode);
1588
1589 if (get_f32_cmp(op_instr[i]->opcode) != expected_cmp)
1590 return false;
1591 if (bitsize && op_bitsize != bitsize)
1592 return false;
1593 if (!op_instr[i]->operands[0].isTemp() || !op_instr[i]->operands[1].isTemp())
1594 return false;
1595
1596 if (op_instr[i]->isVOP3()) {
1597 VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(op_instr[i]);
1598 if (vop3->neg[0] != vop3->neg[1] || vop3->abs[0] != vop3->abs[1] || vop3->opsel == 1 || vop3->opsel == 2)
1599 return false;
1600 neg[i] = vop3->neg[0];
1601 abs[i] = vop3->abs[0];
1602 opsel |= (vop3->opsel & 1) << i;
1603 }
1604
1605 Temp op0 = op_instr[i]->operands[0].getTemp();
1606 Temp op1 = op_instr[i]->operands[1].getTemp();
1607 if (original_temp_id(ctx, op0) != original_temp_id(ctx, op1))
1608 return false;
1609
1610 op[i] = op1;
1611 bitsize = op_bitsize;
1612 }
1613
1614 if (op[1].type() == RegType::sgpr)
1615 std::swap(op[0], op[1]);
1616 unsigned num_sgprs = (op[0].type() == RegType::sgpr) + (op[1].type() == RegType::sgpr);
1617 if (num_sgprs > (ctx.program->chip_class >= GFX10 ? 2 : 1))
1618 return false;
1619
1620 ctx.uses[op[0].id()]++;
1621 ctx.uses[op[1].id()]++;
1622 decrease_uses(ctx, op_instr[0]);
1623 decrease_uses(ctx, op_instr[1]);
1624
1625 aco_opcode new_op = aco_opcode::num_opcodes;
1626 switch (bitsize) {
1627 case 16:
1628 new_op = is_or ? aco_opcode::v_cmp_u_f16 : aco_opcode::v_cmp_o_f16;
1629 break;
1630 case 32:
1631 new_op = is_or ? aco_opcode::v_cmp_u_f32 : aco_opcode::v_cmp_o_f32;
1632 break;
1633 case 64:
1634 new_op = is_or ? aco_opcode::v_cmp_u_f64 : aco_opcode::v_cmp_o_f64;
1635 break;
1636 }
1637 Instruction *new_instr;
1638 if (neg[0] || neg[1] || abs[0] || abs[1] || opsel || num_sgprs > 1) {
1639 VOP3A_instruction *vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1);
1640 for (unsigned i = 0; i < 2; i++) {
1641 vop3->neg[i] = neg[i];
1642 vop3->abs[i] = abs[i];
1643 }
1644 vop3->opsel = opsel;
1645 new_instr = static_cast<Instruction *>(vop3);
1646 } else {
1647 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1);
1648 }
1649 new_instr->operands[0] = Operand(op[0]);
1650 new_instr->operands[1] = Operand(op[1]);
1651 new_instr->definitions[0] = instr->definitions[0];
1652
1653 ctx.info[instr->definitions[0].tempId()].label = 0;
1654 ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
1655
1656 instr.reset(new_instr);
1657
1658 return true;
1659 }
1660
1661 /* s_or_b64(v_cmp_u_f32(a, b), cmp(a, b)) -> get_unordered(cmp)(a, b)
1662 * s_and_b64(v_cmp_o_f32(a, b), cmp(a, b)) -> get_ordered(cmp)(a, b) */
1663 bool combine_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& instr)
1664 {
1665 if (instr->definitions[0].regClass() != ctx.program->lane_mask)
1666 return false;
1667 if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
1668 return false;
1669
1670 bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32;
1671 aco_opcode expected_nan_test = is_or ? aco_opcode::v_cmp_u_f32 : aco_opcode::v_cmp_o_f32;
1672
1673 Instruction *nan_test = follow_operand(ctx, instr->operands[0], true);
1674 Instruction *cmp = follow_operand(ctx, instr->operands[1], true);
1675 if (!nan_test || !cmp)
1676 return false;
1677
1678 if (get_f32_cmp(cmp->opcode) == expected_nan_test)
1679 std::swap(nan_test, cmp);
1680 else if (get_f32_cmp(nan_test->opcode) != expected_nan_test)
1681 return false;
1682
1683 if (!is_cmp(cmp->opcode) || get_cmp_bitsize(cmp->opcode) != get_cmp_bitsize(nan_test->opcode))
1684 return false;
1685
1686 if (!nan_test->operands[0].isTemp() || !nan_test->operands[1].isTemp())
1687 return false;
1688 if (!cmp->operands[0].isTemp() || !cmp->operands[1].isTemp())
1689 return false;
1690
1691 unsigned prop_cmp0 = original_temp_id(ctx, cmp->operands[0].getTemp());
1692 unsigned prop_cmp1 = original_temp_id(ctx, cmp->operands[1].getTemp());
1693 unsigned prop_nan0 = original_temp_id(ctx, nan_test->operands[0].getTemp());
1694 unsigned prop_nan1 = original_temp_id(ctx, nan_test->operands[1].getTemp());
1695 if (prop_cmp0 != prop_nan0 && prop_cmp0 != prop_nan1)
1696 return false;
1697 if (prop_cmp1 != prop_nan0 && prop_cmp1 != prop_nan1)
1698 return false;
1699
1700 ctx.uses[cmp->operands[0].tempId()]++;
1701 ctx.uses[cmp->operands[1].tempId()]++;
1702 decrease_uses(ctx, nan_test);
1703 decrease_uses(ctx, cmp);
1704
1705 aco_opcode new_op = is_or ? get_unordered(cmp->opcode) : get_ordered(cmp->opcode);
1706 Instruction *new_instr;
1707 if (cmp->isVOP3()) {
1708 VOP3A_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1);
1709 VOP3A_instruction *cmp_vop3 = static_cast<VOP3A_instruction*>(cmp);
1710 memcpy(new_vop3->abs, cmp_vop3->abs, sizeof(new_vop3->abs));
1711 memcpy(new_vop3->neg, cmp_vop3->neg, sizeof(new_vop3->neg));
1712 new_vop3->clamp = cmp_vop3->clamp;
1713 new_vop3->omod = cmp_vop3->omod;
1714 new_vop3->opsel = cmp_vop3->opsel;
1715 new_instr = new_vop3;
1716 } else {
1717 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1);
1718 }
1719 new_instr->operands[0] = cmp->operands[0];
1720 new_instr->operands[1] = cmp->operands[1];
1721 new_instr->definitions[0] = instr->definitions[0];
1722
1723 ctx.info[instr->definitions[0].tempId()].label = 0;
1724 ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
1725
1726 instr.reset(new_instr);
1727
1728 return true;
1729 }
1730
1731 /* s_or_b64(v_cmp_neq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_unordered(cmp)(a, b)
1732 * s_and_b64(v_cmp_eq_f32(a, a), cmp(a, #b)) and b is not NaN -> get_ordered(cmp)(a, b) */
1733 bool combine_constant_comparison_ordering(opt_ctx &ctx, aco_ptr<Instruction>& instr)
1734 {
1735 if (instr->definitions[0].regClass() != ctx.program->lane_mask)
1736 return false;
1737 if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
1738 return false;
1739
1740 bool is_or = instr->opcode == aco_opcode::s_or_b64 || instr->opcode == aco_opcode::s_or_b32;
1741
1742 Instruction *nan_test = follow_operand(ctx, instr->operands[0], true);
1743 Instruction *cmp = follow_operand(ctx, instr->operands[1], true);
1744
1745 if (!nan_test || !cmp)
1746 return false;
1747
1748 aco_opcode expected_nan_test = is_or ? aco_opcode::v_cmp_neq_f32 : aco_opcode::v_cmp_eq_f32;
1749 if (get_f32_cmp(cmp->opcode) == expected_nan_test)
1750 std::swap(nan_test, cmp);
1751 else if (get_f32_cmp(nan_test->opcode) != expected_nan_test)
1752 return false;
1753
1754 if (!is_cmp(cmp->opcode) || get_cmp_bitsize(cmp->opcode) != get_cmp_bitsize(nan_test->opcode))
1755 return false;
1756
1757 if (!nan_test->operands[0].isTemp() || !nan_test->operands[1].isTemp())
1758 return false;
1759 if (!cmp->operands[0].isTemp() && !cmp->operands[1].isTemp())
1760 return false;
1761
1762 unsigned prop_nan0 = original_temp_id(ctx, nan_test->operands[0].getTemp());
1763 unsigned prop_nan1 = original_temp_id(ctx, nan_test->operands[1].getTemp());
1764 if (prop_nan0 != prop_nan1)
1765 return false;
1766
1767 if (nan_test->isVOP3()) {
1768 VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(nan_test);
1769 if (vop3->neg[0] != vop3->neg[1] || vop3->abs[0] != vop3->abs[1] || vop3->opsel == 1 || vop3->opsel == 2)
1770 return false;
1771 }
1772
1773 int constant_operand = -1;
1774 for (unsigned i = 0; i < 2; i++) {
1775 if (cmp->operands[i].isTemp() && original_temp_id(ctx, cmp->operands[i].getTemp()) == prop_nan0) {
1776 constant_operand = !i;
1777 break;
1778 }
1779 }
1780 if (constant_operand == -1)
1781 return false;
1782
1783 uint32_t constant;
1784 if (cmp->operands[constant_operand].isConstant()) {
1785 constant = cmp->operands[constant_operand].constantValue();
1786 } else if (cmp->operands[constant_operand].isTemp()) {
1787 Temp tmp = cmp->operands[constant_operand].getTemp();
1788 unsigned id = original_temp_id(ctx, tmp);
1789 if (!ctx.info[id].is_constant_or_literal(32))
1790 return false;
1791 constant = ctx.info[id].val;
1792 } else {
1793 return false;
1794 }
1795
1796 float constantf;
1797 memcpy(&constantf, &constant, 4);
1798 if (isnan(constantf))
1799 return false;
1800
1801 if (cmp->operands[0].isTemp())
1802 ctx.uses[cmp->operands[0].tempId()]++;
1803 if (cmp->operands[1].isTemp())
1804 ctx.uses[cmp->operands[1].tempId()]++;
1805 decrease_uses(ctx, nan_test);
1806 decrease_uses(ctx, cmp);
1807
1808 aco_opcode new_op = is_or ? get_unordered(cmp->opcode) : get_ordered(cmp->opcode);
1809 Instruction *new_instr;
1810 if (cmp->isVOP3()) {
1811 VOP3A_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOPC), 2, 1);
1812 VOP3A_instruction *cmp_vop3 = static_cast<VOP3A_instruction*>(cmp);
1813 memcpy(new_vop3->abs, cmp_vop3->abs, sizeof(new_vop3->abs));
1814 memcpy(new_vop3->neg, cmp_vop3->neg, sizeof(new_vop3->neg));
1815 new_vop3->clamp = cmp_vop3->clamp;
1816 new_vop3->omod = cmp_vop3->omod;
1817 new_vop3->opsel = cmp_vop3->opsel;
1818 new_instr = new_vop3;
1819 } else {
1820 new_instr = create_instruction<VOPC_instruction>(new_op, Format::VOPC, 2, 1);
1821 }
1822 new_instr->operands[0] = cmp->operands[0];
1823 new_instr->operands[1] = cmp->operands[1];
1824 new_instr->definitions[0] = instr->definitions[0];
1825
1826 ctx.info[instr->definitions[0].tempId()].label = 0;
1827 ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
1828
1829 instr.reset(new_instr);
1830
1831 return true;
1832 }
1833
1834 /* s_not_b64(cmp(a, b) -> get_inverse(cmp)(a, b) */
1835 bool combine_inverse_comparison(opt_ctx &ctx, aco_ptr<Instruction>& instr)
1836 {
1837 if (instr->opcode != aco_opcode::s_not_b64)
1838 return false;
1839 if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
1840 return false;
1841 if (!instr->operands[0].isTemp())
1842 return false;
1843
1844 Instruction *cmp = follow_operand(ctx, instr->operands[0]);
1845 if (!cmp)
1846 return false;
1847
1848 aco_opcode new_opcode = get_inverse(cmp->opcode);
1849 if (new_opcode == aco_opcode::num_opcodes)
1850 return false;
1851
1852 if (cmp->operands[0].isTemp())
1853 ctx.uses[cmp->operands[0].tempId()]++;
1854 if (cmp->operands[1].isTemp())
1855 ctx.uses[cmp->operands[1].tempId()]++;
1856 decrease_uses(ctx, cmp);
1857
1858 Instruction *new_instr;
1859 if (cmp->isVOP3()) {
1860 VOP3A_instruction *new_vop3 = create_instruction<VOP3A_instruction>(new_opcode, asVOP3(Format::VOPC), 2, 1);
1861 VOP3A_instruction *cmp_vop3 = static_cast<VOP3A_instruction*>(cmp);
1862 memcpy(new_vop3->abs, cmp_vop3->abs, sizeof(new_vop3->abs));
1863 memcpy(new_vop3->neg, cmp_vop3->neg, sizeof(new_vop3->neg));
1864 new_vop3->clamp = cmp_vop3->clamp;
1865 new_vop3->omod = cmp_vop3->omod;
1866 new_vop3->opsel = cmp_vop3->opsel;
1867 new_instr = new_vop3;
1868 } else {
1869 new_instr = create_instruction<VOPC_instruction>(new_opcode, Format::VOPC, 2, 1);
1870 }
1871 new_instr->operands[0] = cmp->operands[0];
1872 new_instr->operands[1] = cmp->operands[1];
1873 new_instr->definitions[0] = instr->definitions[0];
1874
1875 ctx.info[instr->definitions[0].tempId()].label = 0;
1876 ctx.info[instr->definitions[0].tempId()].set_vopc(new_instr);
1877
1878 instr.reset(new_instr);
1879
1880 return true;
1881 }
1882
1883 /* op1(op2(1, 2), 0) if swap = false
1884 * op1(0, op2(1, 2)) if swap = true */
1885 bool match_op3_for_vop3(opt_ctx &ctx, aco_opcode op1, aco_opcode op2,
1886 Instruction* op1_instr, bool swap, const char *shuffle_str,
1887 Operand operands[3], bool neg[3], bool abs[3], uint8_t *opsel,
1888 bool *op1_clamp, uint8_t *op1_omod,
1889 bool *inbetween_neg, bool *inbetween_abs, bool *inbetween_opsel)
1890 {
1891 /* checks */
1892 if (op1_instr->opcode != op1)
1893 return false;
1894
1895 Instruction *op2_instr = follow_operand(ctx, op1_instr->operands[swap]);
1896 if (!op2_instr || op2_instr->opcode != op2)
1897 return false;
1898 if (fixed_to_exec(op2_instr->operands[0]) || fixed_to_exec(op2_instr->operands[1]))
1899 return false;
1900
1901 VOP3A_instruction *op1_vop3 = op1_instr->isVOP3() ? static_cast<VOP3A_instruction *>(op1_instr) : NULL;
1902 VOP3A_instruction *op2_vop3 = op2_instr->isVOP3() ? static_cast<VOP3A_instruction *>(op2_instr) : NULL;
1903
1904 /* don't support inbetween clamp/omod */
1905 if (op2_vop3 && (op2_vop3->clamp || op2_vop3->omod))
1906 return false;
1907
1908 /* get operands and modifiers and check inbetween modifiers */
1909 *op1_clamp = op1_vop3 ? op1_vop3->clamp : false;
1910 *op1_omod = op1_vop3 ? op1_vop3->omod : 0u;
1911
1912 if (inbetween_neg)
1913 *inbetween_neg = op1_vop3 ? op1_vop3->neg[swap] : false;
1914 else if (op1_vop3 && op1_vop3->neg[swap])
1915 return false;
1916
1917 if (inbetween_abs)
1918 *inbetween_abs = op1_vop3 ? op1_vop3->abs[swap] : false;
1919 else if (op1_vop3 && op1_vop3->abs[swap])
1920 return false;
1921
1922 if (inbetween_opsel)
1923 *inbetween_opsel = op1_vop3 ? op1_vop3->opsel & (1 << swap) : false;
1924 else if (op1_vop3 && op1_vop3->opsel & (1 << swap))
1925 return false;
1926
1927 int shuffle[3];
1928 shuffle[shuffle_str[0] - '0'] = 0;
1929 shuffle[shuffle_str[1] - '0'] = 1;
1930 shuffle[shuffle_str[2] - '0'] = 2;
1931
1932 operands[shuffle[0]] = op1_instr->operands[!swap];
1933 neg[shuffle[0]] = op1_vop3 ? op1_vop3->neg[!swap] : false;
1934 abs[shuffle[0]] = op1_vop3 ? op1_vop3->abs[!swap] : false;
1935 if (op1_vop3 && op1_vop3->opsel & (1 << !swap))
1936 *opsel |= 1 << shuffle[0];
1937
1938 for (unsigned i = 0; i < 2; i++) {
1939 operands[shuffle[i + 1]] = op2_instr->operands[i];
1940 neg[shuffle[i + 1]] = op2_vop3 ? op2_vop3->neg[i] : false;
1941 abs[shuffle[i + 1]] = op2_vop3 ? op2_vop3->abs[i] : false;
1942 if (op2_vop3 && op2_vop3->opsel & (1 << i))
1943 *opsel |= 1 << shuffle[i + 1];
1944 }
1945
1946 /* check operands */
1947 if (!check_vop3_operands(ctx, 3, operands))
1948 return false;
1949
1950 return true;
1951 }
1952
1953 void create_vop3_for_op3(opt_ctx& ctx, aco_opcode opcode, aco_ptr<Instruction>& instr,
1954 Operand operands[3], bool neg[3], bool abs[3], uint8_t opsel,
1955 bool clamp, unsigned omod)
1956 {
1957 VOP3A_instruction *new_instr = create_instruction<VOP3A_instruction>(opcode, Format::VOP3A, 3, 1);
1958 memcpy(new_instr->abs, abs, sizeof(bool[3]));
1959 memcpy(new_instr->neg, neg, sizeof(bool[3]));
1960 new_instr->clamp = clamp;
1961 new_instr->omod = omod;
1962 new_instr->opsel = opsel;
1963 new_instr->operands[0] = operands[0];
1964 new_instr->operands[1] = operands[1];
1965 new_instr->operands[2] = operands[2];
1966 new_instr->definitions[0] = instr->definitions[0];
1967 ctx.info[instr->definitions[0].tempId()].label = 0;
1968
1969 instr.reset(new_instr);
1970 }
1971
1972 bool combine_three_valu_op(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode op2, aco_opcode new_op, const char *shuffle, uint8_t ops)
1973 {
1974 uint64_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
1975 (label_omod_success | label_clamp_success);
1976
1977 for (unsigned swap = 0; swap < 2; swap++) {
1978 if (!((1 << swap) & ops))
1979 continue;
1980
1981 Operand operands[3];
1982 bool neg[3], abs[3], clamp;
1983 uint8_t opsel = 0, omod = 0;
1984 if (match_op3_for_vop3(ctx, instr->opcode, op2,
1985 instr.get(), swap, shuffle,
1986 operands, neg, abs, &opsel,
1987 &clamp, &omod, NULL, NULL, NULL)) {
1988 ctx.uses[instr->operands[swap].tempId()]--;
1989 create_vop3_for_op3(ctx, new_op, instr, operands, neg, abs, opsel, clamp, omod);
1990 if (omod_clamp & label_omod_success)
1991 ctx.info[instr->definitions[0].tempId()].set_omod_success(instr.get());
1992 if (omod_clamp & label_clamp_success)
1993 ctx.info[instr->definitions[0].tempId()].set_clamp_success(instr.get());
1994 return true;
1995 }
1996 }
1997 return false;
1998 }
1999
2000 bool combine_minmax(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode opposite, aco_opcode minmax3)
2001 {
2002 if (combine_three_valu_op(ctx, instr, instr->opcode, minmax3, "012", 1 | 2))
2003 return true;
2004
2005 uint64_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
2006 (label_omod_success | label_clamp_success);
2007
2008 /* min(-max(a, b), c) -> min3(-a, -b, c) *
2009 * max(-min(a, b), c) -> max3(-a, -b, c) */
2010 for (unsigned swap = 0; swap < 2; swap++) {
2011 Operand operands[3];
2012 bool neg[3], abs[3], clamp;
2013 uint8_t opsel = 0, omod = 0;
2014 bool inbetween_neg;
2015 if (match_op3_for_vop3(ctx, instr->opcode, opposite,
2016 instr.get(), swap, "012",
2017 operands, neg, abs, &opsel,
2018 &clamp, &omod, &inbetween_neg, NULL, NULL) &&
2019 inbetween_neg) {
2020 ctx.uses[instr->operands[swap].tempId()]--;
2021 neg[1] = true;
2022 neg[2] = true;
2023 create_vop3_for_op3(ctx, minmax3, instr, operands, neg, abs, opsel, clamp, omod);
2024 if (omod_clamp & label_omod_success)
2025 ctx.info[instr->definitions[0].tempId()].set_omod_success(instr.get());
2026 if (omod_clamp & label_clamp_success)
2027 ctx.info[instr->definitions[0].tempId()].set_clamp_success(instr.get());
2028 return true;
2029 }
2030 }
2031 return false;
2032 }
2033
2034 /* s_not_b32(s_and_b32(a, b)) -> s_nand_b32(a, b)
2035 * s_not_b32(s_or_b32(a, b)) -> s_nor_b32(a, b)
2036 * s_not_b32(s_xor_b32(a, b)) -> s_xnor_b32(a, b)
2037 * s_not_b64(s_and_b64(a, b)) -> s_nand_b64(a, b)
2038 * s_not_b64(s_or_b64(a, b)) -> s_nor_b64(a, b)
2039 * s_not_b64(s_xor_b64(a, b)) -> s_xnor_b64(a, b) */
2040 bool combine_salu_not_bitwise(opt_ctx& ctx, aco_ptr<Instruction>& instr)
2041 {
2042 /* checks */
2043 if (!instr->operands[0].isTemp())
2044 return false;
2045 if (instr->definitions[1].isTemp() && ctx.uses[instr->definitions[1].tempId()])
2046 return false;
2047
2048 Instruction *op2_instr = follow_operand(ctx, instr->operands[0]);
2049 if (!op2_instr)
2050 return false;
2051 switch (op2_instr->opcode) {
2052 case aco_opcode::s_and_b32:
2053 case aco_opcode::s_or_b32:
2054 case aco_opcode::s_xor_b32:
2055 case aco_opcode::s_and_b64:
2056 case aco_opcode::s_or_b64:
2057 case aco_opcode::s_xor_b64:
2058 break;
2059 default:
2060 return false;
2061 }
2062
2063 /* create instruction */
2064 std::swap(instr->definitions[0], op2_instr->definitions[0]);
2065 std::swap(instr->definitions[1], op2_instr->definitions[1]);
2066 ctx.uses[instr->operands[0].tempId()]--;
2067 ctx.info[op2_instr->definitions[0].tempId()].label = 0;
2068
2069 switch (op2_instr->opcode) {
2070 case aco_opcode::s_and_b32:
2071 op2_instr->opcode = aco_opcode::s_nand_b32;
2072 break;
2073 case aco_opcode::s_or_b32:
2074 op2_instr->opcode = aco_opcode::s_nor_b32;
2075 break;
2076 case aco_opcode::s_xor_b32:
2077 op2_instr->opcode = aco_opcode::s_xnor_b32;
2078 break;
2079 case aco_opcode::s_and_b64:
2080 op2_instr->opcode = aco_opcode::s_nand_b64;
2081 break;
2082 case aco_opcode::s_or_b64:
2083 op2_instr->opcode = aco_opcode::s_nor_b64;
2084 break;
2085 case aco_opcode::s_xor_b64:
2086 op2_instr->opcode = aco_opcode::s_xnor_b64;
2087 break;
2088 default:
2089 break;
2090 }
2091
2092 return true;
2093 }
2094
2095 /* s_and_b32(a, s_not_b32(b)) -> s_andn2_b32(a, b)
2096 * s_or_b32(a, s_not_b32(b)) -> s_orn2_b32(a, b)
2097 * s_and_b64(a, s_not_b64(b)) -> s_andn2_b64(a, b)
2098 * s_or_b64(a, s_not_b64(b)) -> s_orn2_b64(a, b) */
2099 bool combine_salu_n2(opt_ctx& ctx, aco_ptr<Instruction>& instr)
2100 {
2101 if (instr->definitions[0].isTemp() && ctx.info[instr->definitions[0].tempId()].is_uniform_bool())
2102 return false;
2103
2104 for (unsigned i = 0; i < 2; i++) {
2105 Instruction *op2_instr = follow_operand(ctx, instr->operands[i]);
2106 if (!op2_instr || (op2_instr->opcode != aco_opcode::s_not_b32 && op2_instr->opcode != aco_opcode::s_not_b64))
2107 continue;
2108 if (ctx.uses[op2_instr->definitions[1].tempId()] || fixed_to_exec(op2_instr->operands[0]))
2109 continue;
2110
2111 if (instr->operands[!i].isLiteral() && op2_instr->operands[0].isLiteral() &&
2112 instr->operands[!i].constantValue() != op2_instr->operands[0].constantValue())
2113 continue;
2114
2115 ctx.uses[instr->operands[i].tempId()]--;
2116 instr->operands[0] = instr->operands[!i];
2117 instr->operands[1] = op2_instr->operands[0];
2118 ctx.info[instr->definitions[0].tempId()].label = 0;
2119
2120 switch (instr->opcode) {
2121 case aco_opcode::s_and_b32:
2122 instr->opcode = aco_opcode::s_andn2_b32;
2123 break;
2124 case aco_opcode::s_or_b32:
2125 instr->opcode = aco_opcode::s_orn2_b32;
2126 break;
2127 case aco_opcode::s_and_b64:
2128 instr->opcode = aco_opcode::s_andn2_b64;
2129 break;
2130 case aco_opcode::s_or_b64:
2131 instr->opcode = aco_opcode::s_orn2_b64;
2132 break;
2133 default:
2134 break;
2135 }
2136
2137 return true;
2138 }
2139 return false;
2140 }
2141
2142 /* s_add_{i32,u32}(a, s_lshl_b32(b, <n>)) -> s_lshl<n>_add_u32(a, b) */
2143 bool combine_salu_lshl_add(opt_ctx& ctx, aco_ptr<Instruction>& instr)
2144 {
2145 if (instr->opcode == aco_opcode::s_add_i32 && ctx.uses[instr->definitions[1].tempId()])
2146 return false;
2147
2148 for (unsigned i = 0; i < 2; i++) {
2149 Instruction *op2_instr = follow_operand(ctx, instr->operands[i]);
2150 if (!op2_instr || op2_instr->opcode != aco_opcode::s_lshl_b32 ||
2151 ctx.uses[op2_instr->definitions[1].tempId()])
2152 continue;
2153 if (!op2_instr->operands[1].isConstant() || fixed_to_exec(op2_instr->operands[0]))
2154 continue;
2155
2156 uint32_t shift = op2_instr->operands[1].constantValue();
2157 if (shift < 1 || shift > 4)
2158 continue;
2159
2160 if (instr->operands[!i].isLiteral() && op2_instr->operands[0].isLiteral() &&
2161 instr->operands[!i].constantValue() != op2_instr->operands[0].constantValue())
2162 continue;
2163
2164 ctx.uses[instr->operands[i].tempId()]--;
2165 instr->operands[1] = instr->operands[!i];
2166 instr->operands[0] = op2_instr->operands[0];
2167 ctx.info[instr->definitions[0].tempId()].label = 0;
2168
2169 instr->opcode = ((aco_opcode[]){aco_opcode::s_lshl1_add_u32,
2170 aco_opcode::s_lshl2_add_u32,
2171 aco_opcode::s_lshl3_add_u32,
2172 aco_opcode::s_lshl4_add_u32})[shift - 1];
2173
2174 return true;
2175 }
2176 return false;
2177 }
2178
2179 bool combine_add_sub_b2i(opt_ctx& ctx, aco_ptr<Instruction>& instr, aco_opcode new_op, uint8_t ops)
2180 {
2181 if (instr->usesModifiers())
2182 return false;
2183
2184 for (unsigned i = 0; i < 2; i++) {
2185 if (!((1 << i) & ops))
2186 continue;
2187 if (instr->operands[i].isTemp() &&
2188 ctx.info[instr->operands[i].tempId()].is_b2i() &&
2189 ctx.uses[instr->operands[i].tempId()] == 1) {
2190
2191 aco_ptr<Instruction> new_instr;
2192 if (instr->operands[!i].isTemp() && instr->operands[!i].getTemp().type() == RegType::vgpr) {
2193 new_instr.reset(create_instruction<VOP2_instruction>(new_op, Format::VOP2, 3, 2));
2194 } else if (ctx.program->chip_class >= GFX10 ||
2195 (instr->operands[!i].isConstant() && !instr->operands[!i].isLiteral())) {
2196 new_instr.reset(create_instruction<VOP3A_instruction>(new_op, asVOP3(Format::VOP2), 3, 2));
2197 } else {
2198 return false;
2199 }
2200 ctx.uses[instr->operands[i].tempId()]--;
2201 new_instr->definitions[0] = instr->definitions[0];
2202 new_instr->definitions[1] = instr->definitions.size() == 2 ? instr->definitions[1] :
2203 Definition(ctx.program->allocateId(), ctx.program->lane_mask);
2204 new_instr->definitions[1].setHint(vcc);
2205 new_instr->operands[0] = Operand(0u);
2206 new_instr->operands[1] = instr->operands[!i];
2207 new_instr->operands[2] = Operand(ctx.info[instr->operands[i].tempId()].temp);
2208 instr = std::move(new_instr);
2209 ctx.info[instr->definitions[0].tempId()].label = 0;
2210 return true;
2211 }
2212 }
2213
2214 return false;
2215 }
2216
2217 bool get_minmax_info(aco_opcode op, aco_opcode *min, aco_opcode *max, aco_opcode *min3, aco_opcode *max3, aco_opcode *med3, bool *some_gfx9_only)
2218 {
2219 switch (op) {
2220 #define MINMAX(type, gfx9) \
2221 case aco_opcode::v_min_##type:\
2222 case aco_opcode::v_max_##type:\
2223 case aco_opcode::v_med3_##type:\
2224 *min = aco_opcode::v_min_##type;\
2225 *max = aco_opcode::v_max_##type;\
2226 *med3 = aco_opcode::v_med3_##type;\
2227 *min3 = aco_opcode::v_min3_##type;\
2228 *max3 = aco_opcode::v_max3_##type;\
2229 *some_gfx9_only = gfx9;\
2230 return true;
2231 MINMAX(f32, false)
2232 MINMAX(u32, false)
2233 MINMAX(i32, false)
2234 MINMAX(f16, true)
2235 MINMAX(u16, true)
2236 MINMAX(i16, true)
2237 #undef MINMAX
2238 default:
2239 return false;
2240 }
2241 }
2242
2243 /* v_min_{f,u,i}{16,32}(v_max_{f,u,i}{16,32}(a, lb), ub) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb
2244 * v_max_{f,u,i}{16,32}(v_min_{f,u,i}{16,32}(a, ub), lb) -> v_med3_{f,u,i}{16,32}(a, lb, ub) when ub > lb */
2245 bool combine_clamp(opt_ctx& ctx, aco_ptr<Instruction>& instr,
2246 aco_opcode min, aco_opcode max, aco_opcode med)
2247 {
2248 /* TODO: GLSL's clamp(x, minVal, maxVal) and SPIR-V's
2249 * FClamp(x, minVal, maxVal)/NClamp(x, minVal, maxVal) are undefined if
2250 * minVal > maxVal, which means we can always select it to a v_med3_f32 */
2251 aco_opcode other_op;
2252 if (instr->opcode == min)
2253 other_op = max;
2254 else if (instr->opcode == max)
2255 other_op = min;
2256 else
2257 return false;
2258
2259 uint64_t omod_clamp = ctx.info[instr->definitions[0].tempId()].label &
2260 (label_omod_success | label_clamp_success);
2261
2262 for (unsigned swap = 0; swap < 2; swap++) {
2263 Operand operands[3];
2264 bool neg[3], abs[3], clamp;
2265 uint8_t opsel = 0, omod = 0;
2266 if (match_op3_for_vop3(ctx, instr->opcode, other_op, instr.get(), swap,
2267 "012", operands, neg, abs, &opsel,
2268 &clamp, &omod, NULL, NULL, NULL)) {
2269 int const0_idx = -1, const1_idx = -1;
2270 uint32_t const0 = 0, const1 = 0;
2271 for (int i = 0; i < 3; i++) {
2272 uint32_t val;
2273 if (operands[i].isConstant()) {
2274 val = operands[i].constantValue();
2275 } else if (operands[i].isTemp() && ctx.info[operands[i].tempId()].is_constant_or_literal(32)) {
2276 val = ctx.info[operands[i].tempId()].val;
2277 } else {
2278 continue;
2279 }
2280 if (const0_idx >= 0) {
2281 const1_idx = i;
2282 const1 = val;
2283 } else {
2284 const0_idx = i;
2285 const0 = val;
2286 }
2287 }
2288 if (const0_idx < 0 || const1_idx < 0)
2289 continue;
2290
2291 if (opsel & (1 << const0_idx))
2292 const0 >>= 16;
2293 if (opsel & (1 << const1_idx))
2294 const1 >>= 16;
2295
2296 int lower_idx = const0_idx;
2297 switch (min) {
2298 case aco_opcode::v_min_f32:
2299 case aco_opcode::v_min_f16: {
2300 float const0_f, const1_f;
2301 if (min == aco_opcode::v_min_f32) {
2302 memcpy(&const0_f, &const0, 4);
2303 memcpy(&const1_f, &const1, 4);
2304 } else {
2305 const0_f = _mesa_half_to_float(const0);
2306 const1_f = _mesa_half_to_float(const1);
2307 }
2308 if (abs[const0_idx]) const0_f = fabsf(const0_f);
2309 if (abs[const1_idx]) const1_f = fabsf(const1_f);
2310 if (neg[const0_idx]) const0_f = -const0_f;
2311 if (neg[const1_idx]) const1_f = -const1_f;
2312 lower_idx = const0_f < const1_f ? const0_idx : const1_idx;
2313 break;
2314 }
2315 case aco_opcode::v_min_u32: {
2316 lower_idx = const0 < const1 ? const0_idx : const1_idx;
2317 break;
2318 }
2319 case aco_opcode::v_min_u16: {
2320 lower_idx = (uint16_t)const0 < (uint16_t)const1 ? const0_idx : const1_idx;
2321 break;
2322 }
2323 case aco_opcode::v_min_i32: {
2324 int32_t const0_i = const0 & 0x80000000u ? -2147483648 + (int32_t)(const0 & 0x7fffffffu) : const0;
2325 int32_t const1_i = const1 & 0x80000000u ? -2147483648 + (int32_t)(const1 & 0x7fffffffu) : const1;
2326 lower_idx = const0_i < const1_i ? const0_idx : const1_idx;
2327 break;
2328 }
2329 case aco_opcode::v_min_i16: {
2330 int16_t const0_i = const0 & 0x8000u ? -32768 + (int16_t)(const0 & 0x7fffu) : const0;
2331 int16_t const1_i = const1 & 0x8000u ? -32768 + (int16_t)(const1 & 0x7fffu) : const1;
2332 lower_idx = const0_i < const1_i ? const0_idx : const1_idx;
2333 break;
2334 }
2335 default:
2336 break;
2337 }
2338 int upper_idx = lower_idx == const0_idx ? const1_idx : const0_idx;
2339
2340 if (instr->opcode == min) {
2341 if (upper_idx != 0 || lower_idx == 0)
2342 return false;
2343 } else {
2344 if (upper_idx == 0 || lower_idx != 0)
2345 return false;
2346 }
2347
2348 ctx.uses[instr->operands[swap].tempId()]--;
2349 create_vop3_for_op3(ctx, med, instr, operands, neg, abs, opsel, clamp, omod);
2350 if (omod_clamp & label_omod_success)
2351 ctx.info[instr->definitions[0].tempId()].set_omod_success(instr.get());
2352 if (omod_clamp & label_clamp_success)
2353 ctx.info[instr->definitions[0].tempId()].set_clamp_success(instr.get());
2354
2355 return true;
2356 }
2357 }
2358
2359 return false;
2360 }
2361
2362
2363 void apply_sgprs(opt_ctx &ctx, aco_ptr<Instruction>& instr)
2364 {
2365 bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
2366 instr->opcode == aco_opcode::v_lshrrev_b64 ||
2367 instr->opcode == aco_opcode::v_ashrrev_i64;
2368
2369 /* find candidates and create the set of sgprs already read */
2370 unsigned sgpr_ids[2] = {0, 0};
2371 uint32_t operand_mask = 0;
2372 bool has_literal = false;
2373 for (unsigned i = 0; i < instr->operands.size(); i++) {
2374 if (instr->operands[i].isLiteral())
2375 has_literal = true;
2376 if (!instr->operands[i].isTemp())
2377 continue;
2378 if (instr->operands[i].getTemp().type() == RegType::sgpr) {
2379 if (instr->operands[i].tempId() != sgpr_ids[0])
2380 sgpr_ids[!!sgpr_ids[0]] = instr->operands[i].tempId();
2381 }
2382 ssa_info& info = ctx.info[instr->operands[i].tempId()];
2383 if (info.is_temp() && info.temp.type() == RegType::sgpr)
2384 operand_mask |= 1u << i;
2385 }
2386 unsigned max_sgprs = 1;
2387 if (ctx.program->chip_class >= GFX10 && !is_shift64)
2388 max_sgprs = 2;
2389 if (has_literal)
2390 max_sgprs--;
2391
2392 unsigned num_sgprs = !!sgpr_ids[0] + !!sgpr_ids[1];
2393
2394 /* keep on applying sgprs until there is nothing left to be done */
2395 while (operand_mask) {
2396 uint32_t sgpr_idx = 0;
2397 uint32_t sgpr_info_id = 0;
2398 uint32_t mask = operand_mask;
2399 /* choose a sgpr */
2400 while (mask) {
2401 unsigned i = u_bit_scan(&mask);
2402 uint16_t uses = ctx.uses[instr->operands[i].tempId()];
2403 if (sgpr_info_id == 0 || uses < ctx.uses[sgpr_info_id]) {
2404 sgpr_idx = i;
2405 sgpr_info_id = instr->operands[i].tempId();
2406 }
2407 }
2408 operand_mask &= ~(1u << sgpr_idx);
2409
2410 /* Applying two sgprs require making it VOP3, so don't do it unless it's
2411 * definitively beneficial.
2412 * TODO: this is too conservative because later the use count could be reduced to 1 */
2413 if (num_sgprs && ctx.uses[sgpr_info_id] > 1 && !instr->isVOP3())
2414 break;
2415
2416 Temp sgpr = ctx.info[sgpr_info_id].temp;
2417 bool new_sgpr = sgpr.id() != sgpr_ids[0] && sgpr.id() != sgpr_ids[1];
2418 if (new_sgpr && num_sgprs >= max_sgprs)
2419 continue;
2420
2421 if (sgpr_idx == 0 || instr->isVOP3()) {
2422 instr->operands[sgpr_idx] = Operand(sgpr);
2423 } else if (can_swap_operands(instr)) {
2424 instr->operands[sgpr_idx] = instr->operands[0];
2425 instr->operands[0] = Operand(sgpr);
2426 /* swap bits using a 4-entry LUT */
2427 uint32_t swapped = (0x3120 >> (operand_mask & 0x3)) & 0xf;
2428 operand_mask = (operand_mask & ~0x3) | swapped;
2429 } else if (can_use_VOP3(ctx, instr)) {
2430 to_VOP3(ctx, instr);
2431 instr->operands[sgpr_idx] = Operand(sgpr);
2432 } else {
2433 continue;
2434 }
2435
2436 if (new_sgpr)
2437 sgpr_ids[num_sgprs++] = sgpr.id();
2438 ctx.uses[sgpr_info_id]--;
2439 ctx.uses[sgpr.id()]++;
2440 }
2441 }
2442
2443 bool apply_omod_clamp(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
2444 {
2445 /* check if we could apply omod on predecessor */
2446 if (instr->opcode == aco_opcode::v_mul_f32 || instr->opcode == aco_opcode::v_mul_f16) {
2447 bool op0 = instr->operands[0].isTemp() && ctx.info[instr->operands[0].tempId()].is_omod_success();
2448 bool op1 = instr->operands[1].isTemp() && ctx.info[instr->operands[1].tempId()].is_omod_success();
2449 if (op0 || op1) {
2450 unsigned idx = op0 ? 0 : 1;
2451 /* omod was successfully applied */
2452 /* if the omod instruction is v_mad, we also have to change the original add */
2453 if (ctx.info[instr->operands[idx].tempId()].is_mad()) {
2454 Instruction* add_instr = ctx.mad_infos[ctx.info[instr->operands[idx].tempId()].instr->pass_flags].add_instr.get();
2455 if (ctx.info[instr->definitions[0].tempId()].is_clamp())
2456 static_cast<VOP3A_instruction*>(add_instr)->clamp = true;
2457 add_instr->definitions[0] = instr->definitions[0];
2458 }
2459
2460 Instruction* omod_instr = ctx.info[instr->operands[idx].tempId()].instr;
2461 /* check if we have an additional clamp modifier */
2462 if (ctx.info[instr->definitions[0].tempId()].is_clamp() && ctx.uses[instr->definitions[0].tempId()] == 1 &&
2463 ctx.uses[ctx.info[instr->definitions[0].tempId()].temp.id()]) {
2464 static_cast<VOP3A_instruction*>(omod_instr)->clamp = true;
2465 ctx.info[instr->definitions[0].tempId()].set_clamp_success(omod_instr);
2466 }
2467 /* change definition ssa-id of modified instruction */
2468 omod_instr->definitions[0] = instr->definitions[0];
2469
2470 /* change the definition of instr to something unused, e.g. the original omod def */
2471 instr->definitions[0] = Definition(instr->operands[idx].getTemp());
2472 ctx.uses[instr->definitions[0].tempId()] = 0;
2473 return true;
2474 }
2475 if (!ctx.info[instr->definitions[0].tempId()].label) {
2476 /* in all other cases, label this instruction as option for multiply-add */
2477 ctx.info[instr->definitions[0].tempId()].set_mul(instr.get());
2478 }
2479 }
2480
2481 /* check if we could apply clamp on predecessor */
2482 if (instr->opcode == aco_opcode::v_med3_f32 || instr->opcode == aco_opcode::v_med3_f16) {
2483 bool is_fp16 = instr->opcode == aco_opcode::v_med3_f16;
2484 unsigned idx = 0;
2485 bool found_zero = false, found_one = false;
2486 for (unsigned i = 0; i < 3; i++)
2487 {
2488 if (instr->operands[i].constantEquals(0))
2489 found_zero = true;
2490 else if (instr->operands[i].constantEquals(is_fp16 ? 0x3c00 : 0x3f800000)) /* 1.0 */
2491 found_one = true;
2492 else
2493 idx = i;
2494 }
2495 if (found_zero && found_one && instr->operands[idx].isTemp() &&
2496 ctx.info[instr->operands[idx].tempId()].is_clamp_success()) {
2497 /* clamp was successfully applied */
2498 /* if the clamp instruction is v_mad, we also have to change the original add */
2499 if (ctx.info[instr->operands[idx].tempId()].is_mad()) {
2500 Instruction* add_instr = ctx.mad_infos[ctx.info[instr->operands[idx].tempId()].instr->pass_flags].add_instr.get();
2501 add_instr->definitions[0] = instr->definitions[0];
2502 }
2503 Instruction* clamp_instr = ctx.info[instr->operands[idx].tempId()].instr;
2504 /* change definition ssa-id of modified instruction */
2505 clamp_instr->definitions[0] = instr->definitions[0];
2506
2507 /* change the definition of instr to something unused, e.g. the original omod def */
2508 instr->definitions[0] = Definition(instr->operands[idx].getTemp());
2509 ctx.uses[instr->definitions[0].tempId()] = 0;
2510 return true;
2511 }
2512 }
2513
2514 /* omod has no effect if denormals are enabled */
2515 /* apply omod / clamp modifiers if the def is used only once and the instruction can have modifiers */
2516 if (!instr->definitions.empty() && ctx.uses[instr->definitions[0].tempId()] == 1 &&
2517 can_use_VOP3(ctx, instr) && instr_info.can_use_output_modifiers[(int)instr->opcode]) {
2518 bool can_use_omod = (instr->definitions[0].bytes() == 4 ? block.fp_mode.denorm32 : block.fp_mode.denorm16_64) == 0;
2519 ssa_info& def_info = ctx.info[instr->definitions[0].tempId()];
2520 if (can_use_omod && def_info.is_omod2() && ctx.uses[def_info.temp.id()]) {
2521 to_VOP3(ctx, instr);
2522 static_cast<VOP3A_instruction*>(instr.get())->omod = 1;
2523 def_info.set_omod_success(instr.get());
2524 } else if (can_use_omod && def_info.is_omod4() && ctx.uses[def_info.temp.id()]) {
2525 to_VOP3(ctx, instr);
2526 static_cast<VOP3A_instruction*>(instr.get())->omod = 2;
2527 def_info.set_omod_success(instr.get());
2528 } else if (can_use_omod && def_info.is_omod5() && ctx.uses[def_info.temp.id()]) {
2529 to_VOP3(ctx, instr);
2530 static_cast<VOP3A_instruction*>(instr.get())->omod = 3;
2531 def_info.set_omod_success(instr.get());
2532 } else if (def_info.is_clamp() && ctx.uses[def_info.temp.id()]) {
2533 to_VOP3(ctx, instr);
2534 static_cast<VOP3A_instruction*>(instr.get())->clamp = true;
2535 def_info.set_clamp_success(instr.get());
2536 }
2537 }
2538
2539 return false;
2540 }
2541
2542 // TODO: we could possibly move the whole label_instruction pass to combine_instruction:
2543 // this would mean that we'd have to fix the instruction uses while value propagation
2544
2545 void combine_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
2546 {
2547 if (instr->definitions.empty() || is_dead(ctx.uses, instr.get()))
2548 return;
2549
2550 if (instr->isVALU()) {
2551 if (can_apply_sgprs(instr))
2552 apply_sgprs(ctx, instr);
2553 if (apply_omod_clamp(ctx, block, instr))
2554 return;
2555 }
2556
2557 if (ctx.info[instr->definitions[0].tempId()].is_vcc_hint()) {
2558 instr->definitions[0].setHint(vcc);
2559 }
2560
2561 /* TODO: There are still some peephole optimizations that could be done:
2562 * - abs(a - b) -> s_absdiff_i32
2563 * - various patterns for s_bitcmp{0,1}_b32 and s_bitset{0,1}_b32
2564 * - patterns for v_alignbit_b32 and v_alignbyte_b32
2565 * These aren't probably too interesting though.
2566 * There are also patterns for v_cmp_class_f{16,32,64}. This is difficult but
2567 * probably more useful than the previously mentioned optimizations.
2568 * The various comparison optimizations also currently only work with 32-bit
2569 * floats. */
2570
2571 /* neg(mul(a, b)) -> mul(neg(a), b) */
2572 if (ctx.info[instr->definitions[0].tempId()].is_neg() && ctx.uses[instr->operands[1].tempId()] == 1) {
2573 Temp val = ctx.info[instr->definitions[0].tempId()].temp;
2574
2575 if (!ctx.info[val.id()].is_mul())
2576 return;
2577
2578 Instruction* mul_instr = ctx.info[val.id()].instr;
2579
2580 if (mul_instr->operands[0].isLiteral())
2581 return;
2582 if (mul_instr->isVOP3() && static_cast<VOP3A_instruction*>(mul_instr)->clamp)
2583 return;
2584
2585 /* convert to mul(neg(a), b) */
2586 ctx.uses[mul_instr->definitions[0].tempId()]--;
2587 Definition def = instr->definitions[0];
2588 /* neg(abs(mul(a, b))) -> mul(neg(abs(a)), abs(b)) */
2589 bool is_abs = ctx.info[instr->definitions[0].tempId()].is_abs();
2590 instr.reset(create_instruction<VOP3A_instruction>(mul_instr->opcode, asVOP3(Format::VOP2), 2, 1));
2591 instr->operands[0] = mul_instr->operands[0];
2592 instr->operands[1] = mul_instr->operands[1];
2593 instr->definitions[0] = def;
2594 VOP3A_instruction* new_mul = static_cast<VOP3A_instruction*>(instr.get());
2595 if (mul_instr->isVOP3()) {
2596 VOP3A_instruction* mul = static_cast<VOP3A_instruction*>(mul_instr);
2597 new_mul->neg[0] = mul->neg[0] && !is_abs;
2598 new_mul->neg[1] = mul->neg[1] && !is_abs;
2599 new_mul->abs[0] = mul->abs[0] || is_abs;
2600 new_mul->abs[1] = mul->abs[1] || is_abs;
2601 new_mul->omod = mul->omod;
2602 }
2603 new_mul->neg[0] ^= true;
2604 new_mul->clamp = false;
2605
2606 ctx.info[instr->definitions[0].tempId()].set_mul(instr.get());
2607 return;
2608 }
2609
2610 /* combine mul+add -> mad */
2611 bool mad32 = instr->opcode == aco_opcode::v_add_f32 ||
2612 instr->opcode == aco_opcode::v_sub_f32 ||
2613 instr->opcode == aco_opcode::v_subrev_f32;
2614 bool mad16 = instr->opcode == aco_opcode::v_add_f16 ||
2615 instr->opcode == aco_opcode::v_sub_f16 ||
2616 instr->opcode == aco_opcode::v_subrev_f16;
2617 if (mad16 || mad32) {
2618 bool need_fma = mad32 ? block.fp_mode.denorm32 != 0 :
2619 (block.fp_mode.denorm16_64 != 0 || ctx.program->chip_class >= GFX10);
2620 if (need_fma && instr->definitions[0].isPrecise())
2621 return;
2622 if (need_fma && mad32 && !ctx.program->has_fast_fma32)
2623 return;
2624
2625 uint32_t uses_src0 = UINT32_MAX;
2626 uint32_t uses_src1 = UINT32_MAX;
2627 Instruction* mul_instr = nullptr;
2628 unsigned add_op_idx;
2629 /* check if any of the operands is a multiplication */
2630 ssa_info *op0_info = instr->operands[0].isTemp() ? &ctx.info[instr->operands[0].tempId()] : NULL;
2631 ssa_info *op1_info = instr->operands[1].isTemp() ? &ctx.info[instr->operands[1].tempId()] : NULL;
2632 if (op0_info && op0_info->is_mul() && (!need_fma || !op0_info->instr->definitions[0].isPrecise()))
2633 uses_src0 = ctx.uses[instr->operands[0].tempId()];
2634 if (op1_info && op1_info->is_mul() && (!need_fma || !op1_info->instr->definitions[0].isPrecise()))
2635 uses_src1 = ctx.uses[instr->operands[1].tempId()];
2636
2637 /* find the 'best' mul instruction to combine with the add */
2638 if (uses_src0 < uses_src1) {
2639 mul_instr = op0_info->instr;
2640 add_op_idx = 1;
2641 } else if (uses_src1 < uses_src0) {
2642 mul_instr = op1_info->instr;
2643 add_op_idx = 0;
2644 } else if (uses_src0 != UINT32_MAX) {
2645 /* tiebreaker: quite random what to pick */
2646 if (op0_info->instr->operands[0].isLiteral()) {
2647 mul_instr = op1_info->instr;
2648 add_op_idx = 0;
2649 } else {
2650 mul_instr = op0_info->instr;
2651 add_op_idx = 1;
2652 }
2653 }
2654 if (mul_instr) {
2655 Operand op[3] = {Operand(v1), Operand(v1), Operand(v1)};
2656 bool neg[3] = {false, false, false};
2657 bool abs[3] = {false, false, false};
2658 unsigned omod = 0;
2659 bool clamp = false;
2660 op[0] = mul_instr->operands[0];
2661 op[1] = mul_instr->operands[1];
2662 op[2] = instr->operands[add_op_idx];
2663 // TODO: would be better to check this before selecting a mul instr?
2664 if (!check_vop3_operands(ctx, 3, op))
2665 return;
2666
2667 if (mul_instr->isVOP3()) {
2668 VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*> (mul_instr);
2669 neg[0] = vop3->neg[0];
2670 neg[1] = vop3->neg[1];
2671 abs[0] = vop3->abs[0];
2672 abs[1] = vop3->abs[1];
2673 /* we cannot use these modifiers between mul and add */
2674 if (vop3->clamp || vop3->omod)
2675 return;
2676 }
2677
2678 /* convert to mad */
2679 ctx.uses[mul_instr->definitions[0].tempId()]--;
2680 if (ctx.uses[mul_instr->definitions[0].tempId()]) {
2681 if (op[0].isTemp())
2682 ctx.uses[op[0].tempId()]++;
2683 if (op[1].isTemp())
2684 ctx.uses[op[1].tempId()]++;
2685 }
2686
2687 if (instr->isVOP3()) {
2688 VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*> (instr.get());
2689 neg[2] = vop3->neg[add_op_idx];
2690 abs[2] = vop3->abs[add_op_idx];
2691 omod = vop3->omod;
2692 clamp = vop3->clamp;
2693 /* abs of the multiplication result */
2694 if (vop3->abs[1 - add_op_idx]) {
2695 neg[0] = false;
2696 neg[1] = false;
2697 abs[0] = true;
2698 abs[1] = true;
2699 }
2700 /* neg of the multiplication result */
2701 neg[1] = neg[1] ^ vop3->neg[1 - add_op_idx];
2702 }
2703 if (instr->opcode == aco_opcode::v_sub_f32 || instr->opcode == aco_opcode::v_sub_f16)
2704 neg[1 + add_op_idx] = neg[1 + add_op_idx] ^ true;
2705 else if (instr->opcode == aco_opcode::v_subrev_f32 || instr->opcode == aco_opcode::v_subrev_f16)
2706 neg[2 - add_op_idx] = neg[2 - add_op_idx] ^ true;
2707
2708 aco_opcode mad_op = need_fma ? aco_opcode::v_fma_f32 : aco_opcode::v_mad_f32;
2709 if (mad16)
2710 mad_op = need_fma ? (ctx.program->chip_class == GFX8 ? aco_opcode::v_fma_legacy_f16 : aco_opcode::v_fma_f16) :
2711 (ctx.program->chip_class == GFX8 ? aco_opcode::v_mad_legacy_f16 : aco_opcode::v_mad_f16);
2712
2713 aco_ptr<VOP3A_instruction> mad{create_instruction<VOP3A_instruction>(mad_op, Format::VOP3A, 3, 1)};
2714 for (unsigned i = 0; i < 3; i++)
2715 {
2716 mad->operands[i] = op[i];
2717 mad->neg[i] = neg[i];
2718 mad->abs[i] = abs[i];
2719 }
2720 mad->omod = omod;
2721 mad->clamp = clamp;
2722 mad->definitions[0] = instr->definitions[0];
2723
2724 /* mark this ssa_def to be re-checked for profitability and literals */
2725 ctx.mad_infos.emplace_back(std::move(instr), mul_instr->definitions[0].tempId());