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27 #include "aco_builder.h"
35 * Implements the spilling algorithm on SSA-form from
36 * "Register Spilling and Live-Range Splitting for SSA-Form Programs"
37 * by Matthias Braun and Sebastian Hack.
49 RegisterDemand target_pressure
;
51 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
52 std::vector
<std::map
<Temp
, Temp
>> renames
;
53 std::vector
<std::map
<Temp
, uint32_t>> spills_entry
;
54 std::vector
<std::map
<Temp
, uint32_t>> spills_exit
;
55 std::vector
<bool> processed
;
56 std::stack
<Block
*> loop_header
;
57 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_start
;
58 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_end
;
59 std::vector
<std::pair
<RegClass
, std::set
<uint32_t>>> interferences
;
60 std::vector
<std::vector
<uint32_t>> affinities
;
61 std::vector
<bool> is_reloaded
;
62 std::map
<Temp
, remat_info
> remat
;
63 std::map
<Instruction
*, bool> remat_used
;
66 spill_ctx(const RegisterDemand target_pressure
, Program
* program
,
67 std::vector
<std::vector
<RegisterDemand
>> register_demand
)
68 : target_pressure(target_pressure
), program(program
),
69 register_demand(std::move(register_demand
)), renames(program
->blocks
.size()),
70 spills_entry(program
->blocks
.size()), spills_exit(program
->blocks
.size()),
71 processed(program
->blocks
.size(), false), wave_size(program
->wave_size
) {}
73 void add_affinity(uint32_t first
, uint32_t second
)
75 unsigned found_first
= affinities
.size();
76 unsigned found_second
= affinities
.size();
77 for (unsigned i
= 0; i
< affinities
.size(); i
++) {
78 std::vector
<uint32_t>& vec
= affinities
[i
];
79 for (uint32_t entry
: vec
) {
82 else if (entry
== second
)
86 if (found_first
== affinities
.size() && found_second
== affinities
.size()) {
87 affinities
.emplace_back(std::vector
<uint32_t>({first
, second
}));
88 } else if (found_first
< affinities
.size() && found_second
== affinities
.size()) {
89 affinities
[found_first
].push_back(second
);
90 } else if (found_second
< affinities
.size() && found_first
== affinities
.size()) {
91 affinities
[found_second
].push_back(first
);
92 } else if (found_first
!= found_second
) {
93 /* merge second into first */
94 affinities
[found_first
].insert(affinities
[found_first
].end(), affinities
[found_second
].begin(), affinities
[found_second
].end());
95 affinities
.erase(std::next(affinities
.begin(), found_second
));
97 assert(found_first
== found_second
);
101 uint32_t allocate_spill_id(RegClass rc
)
103 interferences
.emplace_back(rc
, std::set
<uint32_t>());
104 is_reloaded
.push_back(false);
105 return next_spill_id
++;
108 uint32_t next_spill_id
= 0;
111 int32_t get_dominator(int idx_a
, int idx_b
, Program
* program
, bool is_linear
)
119 while (idx_a
!= idx_b
) {
121 idx_a
= program
->blocks
[idx_a
].linear_idom
;
123 idx_b
= program
->blocks
[idx_b
].linear_idom
;
126 while (idx_a
!= idx_b
) {
128 idx_a
= program
->blocks
[idx_a
].logical_idom
;
130 idx_b
= program
->blocks
[idx_b
].logical_idom
;
137 void next_uses_per_block(spill_ctx
& ctx
, unsigned block_idx
, std::set
<uint32_t>& worklist
)
139 Block
* block
= &ctx
.program
->blocks
[block_idx
];
140 std::map
<Temp
, std::pair
<uint32_t, uint32_t>> next_uses
= ctx
.next_use_distances_end
[block_idx
];
142 /* to compute the next use distance at the beginning of the block, we have to add the block's size */
143 for (std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= next_uses
.begin(); it
!= next_uses
.end(); ++it
)
144 it
->second
.second
= it
->second
.second
+ block
->instructions
.size();
146 int idx
= block
->instructions
.size() - 1;
148 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
150 if (instr
->opcode
== aco_opcode::p_linear_phi
||
151 instr
->opcode
== aco_opcode::p_phi
)
154 for (const Definition
& def
: instr
->definitions
) {
156 next_uses
.erase(def
.getTemp());
159 for (const Operand
& op
: instr
->operands
) {
161 if (op
.isFixed() && op
.physReg() == exec
)
163 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
166 next_uses
[op
.getTemp()] = {block_idx
, idx
};
171 assert(block_idx
!= 0 || next_uses
.empty());
172 ctx
.next_use_distances_start
[block_idx
] = next_uses
;
174 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
175 assert(instr
->opcode
== aco_opcode::p_linear_phi
|| instr
->opcode
== aco_opcode::p_phi
);
177 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
178 unsigned pred_idx
= instr
->opcode
== aco_opcode::p_phi
?
179 block
->logical_preds
[i
] :
180 block
->linear_preds
[i
];
181 if (instr
->operands
[i
].isTemp()) {
182 if (instr
->operands
[i
].getTemp() == ctx
.program
->blocks
[pred_idx
].live_out_exec
)
184 if (ctx
.next_use_distances_end
[pred_idx
].find(instr
->operands
[i
].getTemp()) == ctx
.next_use_distances_end
[pred_idx
].end() ||
185 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] != std::pair
<uint32_t, uint32_t>{block_idx
, 0})
186 worklist
.insert(pred_idx
);
187 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] = {block_idx
, 0};
190 next_uses
.erase(instr
->definitions
[0].getTemp());
194 /* all remaining live vars must be live-out at the predecessors */
195 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: next_uses
) {
196 Temp temp
= pair
.first
;
197 uint32_t distance
= pair
.second
.second
;
198 uint32_t dom
= pair
.second
.first
;
199 std::vector
<unsigned>& preds
= temp
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
200 for (unsigned pred_idx
: preds
) {
201 if (temp
== ctx
.program
->blocks
[pred_idx
].live_out_exec
)
203 if (ctx
.program
->blocks
[pred_idx
].loop_nest_depth
> block
->loop_nest_depth
)
205 if (ctx
.next_use_distances_end
[pred_idx
].find(temp
) != ctx
.next_use_distances_end
[pred_idx
].end()) {
206 dom
= get_dominator(dom
, ctx
.next_use_distances_end
[pred_idx
][temp
].first
, ctx
.program
, temp
.is_linear());
207 distance
= std::min(ctx
.next_use_distances_end
[pred_idx
][temp
].second
, distance
);
209 if (ctx
.next_use_distances_end
[pred_idx
][temp
] != std::pair
<uint32_t, uint32_t>{dom
, distance
})
210 worklist
.insert(pred_idx
);
211 ctx
.next_use_distances_end
[pred_idx
][temp
] = {dom
, distance
};
217 void compute_global_next_uses(spill_ctx
& ctx
)
219 ctx
.next_use_distances_start
.resize(ctx
.program
->blocks
.size());
220 ctx
.next_use_distances_end
.resize(ctx
.program
->blocks
.size());
221 std::set
<uint32_t> worklist
;
222 for (Block
& block
: ctx
.program
->blocks
)
223 worklist
.insert(block
.index
);
225 while (!worklist
.empty()) {
226 std::set
<unsigned>::reverse_iterator b_it
= worklist
.rbegin();
227 unsigned block_idx
= *b_it
;
228 worklist
.erase(block_idx
);
229 next_uses_per_block(ctx
, block_idx
, worklist
);
233 bool should_rematerialize(aco_ptr
<Instruction
>& instr
)
235 /* TODO: rematerialization is only supported for VOP1, SOP1 and PSEUDO */
236 if (instr
->format
!= Format::VOP1
&& instr
->format
!= Format::SOP1
&& instr
->format
!= Format::PSEUDO
&& instr
->format
!= Format::SOPK
)
238 /* TODO: pseudo-instruction rematerialization is only supported for p_create_vector */
239 if (instr
->format
== Format::PSEUDO
&& instr
->opcode
!= aco_opcode::p_create_vector
)
241 if (instr
->format
== Format::SOPK
&& instr
->opcode
!= aco_opcode::s_movk_i32
)
244 for (const Operand
& op
: instr
->operands
) {
245 /* TODO: rematerialization using temporaries isn't yet supported */
250 /* TODO: rematerialization with multiple definitions isn't yet supported */
251 if (instr
->definitions
.size() > 1)
257 aco_ptr
<Instruction
> do_reload(spill_ctx
& ctx
, Temp tmp
, Temp new_name
, uint32_t spill_id
)
259 std::map
<Temp
, remat_info
>::iterator remat
= ctx
.remat
.find(tmp
);
260 if (remat
!= ctx
.remat
.end()) {
261 Instruction
*instr
= remat
->second
.instr
;
262 assert((instr
->format
== Format::VOP1
|| instr
->format
== Format::SOP1
|| instr
->format
== Format::PSEUDO
|| instr
->format
== Format::SOPK
) && "unsupported");
263 assert((instr
->format
!= Format::PSEUDO
|| instr
->opcode
== aco_opcode::p_create_vector
) && "unsupported");
264 assert(instr
->definitions
.size() == 1 && "unsupported");
266 aco_ptr
<Instruction
> res
;
267 if (instr
->format
== Format::VOP1
) {
268 res
.reset(create_instruction
<VOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
269 } else if (instr
->format
== Format::SOP1
) {
270 res
.reset(create_instruction
<SOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
271 } else if (instr
->format
== Format::PSEUDO
) {
272 res
.reset(create_instruction
<Pseudo_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
273 } else if (instr
->format
== Format::SOPK
) {
274 res
.reset(create_instruction
<SOPK_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
275 static_cast<SOPK_instruction
*>(res
.get())->imm
= static_cast<SOPK_instruction
*>(instr
)->imm
;
277 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
278 res
->operands
[i
] = instr
->operands
[i
];
279 if (instr
->operands
[i
].isTemp()) {
280 assert(false && "unsupported");
281 if (ctx
.remat
.count(instr
->operands
[i
].getTemp()))
282 ctx
.remat_used
[ctx
.remat
[instr
->operands
[i
].getTemp()].instr
] = true;
285 res
->definitions
[0] = Definition(new_name
);
288 aco_ptr
<Pseudo_instruction
> reload
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 1, 1)};
289 reload
->operands
[0] = Operand(spill_id
);
290 reload
->definitions
[0] = Definition(new_name
);
291 ctx
.is_reloaded
[spill_id
] = true;
296 void get_rematerialize_info(spill_ctx
& ctx
)
298 for (Block
& block
: ctx
.program
->blocks
) {
299 bool logical
= false;
300 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
301 if (instr
->opcode
== aco_opcode::p_logical_start
)
303 else if (instr
->opcode
== aco_opcode::p_logical_end
)
305 if (logical
&& should_rematerialize(instr
)) {
306 for (const Definition
& def
: instr
->definitions
) {
308 ctx
.remat
[def
.getTemp()] = (remat_info
){instr
.get()};
309 ctx
.remat_used
[instr
.get()] = false;
317 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(spill_ctx
& ctx
, Block
* block
)
319 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(block
->instructions
.size());
321 std::map
<Temp
, uint32_t> next_uses
;
322 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block
->index
])
323 next_uses
[pair
.first
] = pair
.second
.second
+ block
->instructions
.size();
325 for (int idx
= block
->instructions
.size() - 1; idx
>= 0; idx
--) {
326 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
329 if (instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
)
332 for (const Operand
& op
: instr
->operands
) {
333 if (op
.isFixed() && op
.physReg() == exec
)
335 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
338 next_uses
[op
.getTemp()] = idx
;
340 for (const Definition
& def
: instr
->definitions
) {
342 next_uses
.erase(def
.getTemp());
344 local_next_uses
[idx
] = next_uses
;
346 return local_next_uses
;
350 RegisterDemand
init_live_in_vars(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
352 RegisterDemand spilled_registers
;
354 /* first block, nothing was spilled before */
358 /* loop header block */
359 if (block
->loop_nest_depth
> ctx
.program
->blocks
[block_idx
- 1].loop_nest_depth
) {
360 assert(block
->linear_preds
[0] == block_idx
- 1);
361 assert(block
->logical_preds
[0] == block_idx
- 1);
363 /* create new loop_info */
364 ctx
.loop_header
.emplace(block
);
366 /* check how many live-through variables should be spilled */
367 RegisterDemand new_demand
;
368 unsigned i
= block_idx
;
369 while (ctx
.program
->blocks
[i
].loop_nest_depth
>= block
->loop_nest_depth
) {
370 assert(ctx
.program
->blocks
.size() > i
);
371 new_demand
.update(ctx
.program
->blocks
[i
].register_demand
);
374 unsigned loop_end
= i
;
376 /* select live-through vgpr variables */
377 while (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
378 unsigned distance
= 0;
380 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
381 if (pair
.first
.type() == RegType::vgpr
&&
382 pair
.second
.first
>= loop_end
&&
383 pair
.second
.second
> distance
&&
384 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
385 to_spill
= pair
.first
;
386 distance
= pair
.second
.second
;
393 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
394 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
396 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
399 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
400 spilled_registers
.vgpr
+= to_spill
.size();
403 /* select live-through sgpr variables */
404 while (new_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
405 unsigned distance
= 0;
407 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
408 if (pair
.first
.type() == RegType::sgpr
&&
409 pair
.second
.first
>= loop_end
&&
410 pair
.second
.second
> distance
&&
411 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
412 to_spill
= pair
.first
;
413 distance
= pair
.second
.second
;
420 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
421 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
423 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
426 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
427 spilled_registers
.sgpr
+= to_spill
.size();
433 if (!RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
))
434 return spilled_registers
;
436 /* if reg pressure is too high at beginning of loop, add variables with furthest use */
438 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
|| block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
)
441 assert(idx
!= 0 && "loop without phis: TODO");
443 RegisterDemand reg_pressure
= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
444 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
445 unsigned distance
= 0;
447 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
448 if (pair
.first
.type() == RegType::sgpr
&&
449 pair
.second
.second
> distance
&&
450 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
451 to_spill
= pair
.first
;
452 distance
= pair
.second
.second
;
455 assert(distance
!= 0);
457 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
458 spilled_registers
.sgpr
+= to_spill
.size();
459 reg_pressure
.sgpr
-= to_spill
.size();
461 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
462 unsigned distance
= 0;
464 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
465 if (pair
.first
.type() == RegType::vgpr
&&
466 pair
.second
.second
> distance
&&
467 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
468 to_spill
= pair
.first
;
469 distance
= pair
.second
.second
;
472 assert(distance
!= 0);
473 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
474 spilled_registers
.vgpr
+= to_spill
.size();
475 reg_pressure
.vgpr
-= to_spill
.size();
478 return spilled_registers
;
482 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
483 /* keep variables spilled if they are alive and not used in the current block */
484 unsigned pred_idx
= block
->linear_preds
[0];
485 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
486 if (pair
.first
.type() == RegType::sgpr
&&
487 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
488 ctx
.next_use_distances_start
[block_idx
][pair
.first
].second
> block_idx
) {
489 ctx
.spills_entry
[block_idx
].insert(pair
);
490 spilled_registers
.sgpr
+= pair
.first
.size();
493 if (block
->logical_preds
.size() == 1) {
494 pred_idx
= block
->logical_preds
[0];
495 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
496 if (pair
.first
.type() == RegType::vgpr
&&
497 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
498 ctx
.next_use_distances_start
[block_idx
][pair
.first
].second
> block_idx
) {
499 ctx
.spills_entry
[block_idx
].insert(pair
);
500 spilled_registers
.vgpr
+= pair
.first
.size();
505 /* if register demand is still too high, we just keep all spilled live vars and process the block */
506 if (block
->register_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
507 pred_idx
= block
->linear_preds
[0];
508 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
509 if (pair
.first
.type() == RegType::sgpr
&&
510 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
511 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
512 spilled_registers
.sgpr
+= pair
.first
.size();
516 if (block
->register_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
&& block
->logical_preds
.size() == 1) {
517 pred_idx
= block
->logical_preds
[0];
518 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
519 if (pair
.first
.type() == RegType::vgpr
&&
520 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
521 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
522 spilled_registers
.vgpr
+= pair
.first
.size();
527 return spilled_registers
;
530 /* else: merge block */
531 std::set
<Temp
> partial_spills
;
533 /* keep variables spilled on all incoming paths */
534 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
535 std::vector
<unsigned>& preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
536 /* If it can be rematerialized, keep the variable spilled if all predecessors do not reload it.
537 * Otherwise, if any predecessor reloads it, ensure it's reloaded on all other predecessors.
538 * The idea is that it's better in practice to rematerialize redundantly than to create lots of phis. */
539 /* TODO: test this idea with more than Dawn of War III shaders (the current pipeline-db doesn't seem to exercise this path much) */
540 bool remat
= ctx
.remat
.count(pair
.first
);
542 uint32_t spill_id
= 0;
543 for (unsigned pred_idx
: preds
) {
544 /* variable is not even live at the predecessor: probably from a phi */
545 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end()) {
549 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
553 partial_spills
.insert(pair
.first
);
554 /* it might be that on one incoming path, the variable has a different spill_id, but add_couple_code() will take care of that. */
555 spill_id
= ctx
.spills_exit
[pred_idx
][pair
.first
];
561 ctx
.spills_entry
[block_idx
][pair
.first
] = spill_id
;
562 partial_spills
.erase(pair
.first
);
563 spilled_registers
+= pair
.first
;
569 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
||
570 block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
) {
571 aco_ptr
<Instruction
>& phi
= block
->instructions
[idx
];
572 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
575 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
576 if (phi
->operands
[i
].isUndefined())
578 assert(phi
->operands
[i
].isTemp());
579 if (ctx
.spills_exit
[preds
[i
]].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[preds
[i
]].end())
582 partial_spills
.insert(phi
->definitions
[0].getTemp());
585 ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()] = ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
586 partial_spills
.erase(phi
->definitions
[0].getTemp());
587 spilled_registers
+= phi
->definitions
[0].getTemp();
593 /* if reg pressure at first instruction is still too high, add partially spilled variables */
594 RegisterDemand reg_pressure
;
596 for (const Definition
& def
: block
->instructions
[idx
]->definitions
) {
598 reg_pressure
-= def
.getTemp();
601 for (const Operand
& op
: block
->instructions
[idx
]->operands
) {
602 if (op
.isTemp() && op
.isFirstKill()) {
603 reg_pressure
+= op
.getTemp();
607 for (unsigned i
= 0; i
< idx
; i
++) {
608 aco_ptr
<Instruction
>& instr
= block
->instructions
[i
];
609 assert(is_phi(instr
));
610 /* Killed phi definitions increase pressure in the predecessor but not
611 * the block they're in. Since the loops below are both to control
612 * pressure of the start of this block and the ends of it's
613 * predecessors, we need to count killed unspilled phi definitions here. */
614 if (instr
->definitions
[0].isKill() &&
615 !ctx
.spills_entry
[block_idx
].count(instr
->definitions
[0].getTemp()))
616 reg_pressure
+= instr
->definitions
[0].getTemp();
620 reg_pressure
+= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
622 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
623 assert(!partial_spills
.empty());
625 std::set
<Temp
>::iterator it
= partial_spills
.begin();
627 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
628 while (it
!= partial_spills
.end()) {
629 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
631 if (it
->type() == RegType::sgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
632 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
637 assert(distance
!= 0);
639 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
640 partial_spills
.erase(to_spill
);
641 spilled_registers
.sgpr
+= to_spill
.size();
642 reg_pressure
.sgpr
-= to_spill
.size();
645 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
646 assert(!partial_spills
.empty());
648 std::set
<Temp
>::iterator it
= partial_spills
.begin();
650 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
651 while (it
!= partial_spills
.end()) {
652 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
654 if (it
->type() == RegType::vgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
655 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
660 assert(distance
!= 0);
662 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
663 partial_spills
.erase(to_spill
);
664 spilled_registers
.vgpr
+= to_spill
.size();
665 reg_pressure
.vgpr
-= to_spill
.size();
668 return spilled_registers
;
672 RegisterDemand
get_demand_before(spill_ctx
& ctx
, unsigned block_idx
, unsigned idx
)
675 RegisterDemand demand
= ctx
.register_demand
[block_idx
][idx
];
676 aco_ptr
<Instruction
>& instr
= ctx
.program
->blocks
[block_idx
].instructions
[idx
];
677 aco_ptr
<Instruction
> instr_before(nullptr);
678 return get_demand_before(demand
, instr
, instr_before
);
680 return ctx
.register_demand
[block_idx
][idx
- 1];
684 void add_coupling_code(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
686 /* no coupling code necessary */
687 if (block
->linear_preds
.size() == 0)
690 std::vector
<aco_ptr
<Instruction
>> instructions
;
691 /* branch block: TODO take other branch into consideration */
692 if (block
->linear_preds
.size() == 1 && !(block
->kind
& (block_kind_loop_exit
| block_kind_loop_header
))) {
693 assert(ctx
.processed
[block
->linear_preds
[0]]);
694 assert(ctx
.register_demand
[block_idx
].size() == block
->instructions
.size());
695 std::vector
<RegisterDemand
> reg_demand
;
696 unsigned insert_idx
= 0;
697 unsigned pred_idx
= block
->linear_preds
[0];
698 RegisterDemand demand_before
= get_demand_before(ctx
, block_idx
, 0);
700 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
701 if (!live
.first
.is_linear())
704 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
707 /* in register at end of predecessor */
708 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
709 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
710 if (it
!= ctx
.renames
[pred_idx
].end())
711 ctx
.renames
[block_idx
].insert(*it
);
715 /* variable is spilled at predecessor and live at current block: create reload instruction */
716 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
717 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
718 instructions
.emplace_back(std::move(reload
));
719 reg_demand
.push_back(demand_before
);
720 ctx
.renames
[block_idx
][live
.first
] = new_name
;
723 if (block
->logical_preds
.size() == 1) {
725 assert(insert_idx
< block
->instructions
.size());
726 instructions
.emplace_back(std::move(block
->instructions
[insert_idx
]));
727 reg_demand
.push_back(ctx
.register_demand
[block_idx
][insert_idx
]);
729 } while (instructions
.back()->opcode
!= aco_opcode::p_logical_start
);
731 unsigned pred_idx
= block
->logical_preds
[0];
732 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
733 if (live
.first
.is_linear())
736 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
739 /* in register at end of predecessor */
740 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
741 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
742 if (it
!= ctx
.renames
[pred_idx
].end())
743 ctx
.renames
[block_idx
].insert(*it
);
747 /* variable is spilled at predecessor and live at current block: create reload instruction */
748 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
749 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
750 instructions
.emplace_back(std::move(reload
));
751 reg_demand
.emplace_back(reg_demand
.back());
752 ctx
.renames
[block_idx
][live
.first
] = new_name
;
756 /* combine new reload instructions with original block */
757 if (!instructions
.empty()) {
758 reg_demand
.insert(reg_demand
.end(), std::next(ctx
.register_demand
[block
->index
].begin(), insert_idx
),
759 ctx
.register_demand
[block
->index
].end());
760 ctx
.register_demand
[block_idx
] = std::move(reg_demand
);
761 instructions
.insert(instructions
.end(),
762 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(std::next(block
->instructions
.begin(), insert_idx
)),
763 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
764 block
->instructions
= std::move(instructions
);
769 /* loop header and merge blocks: check if all (linear) predecessors have been processed */
770 for (ASSERTED
unsigned pred
: block
->linear_preds
)
771 assert(ctx
.processed
[pred
]);
773 /* iterate the phi nodes for which operands to spill at the predecessor */
774 for (aco_ptr
<Instruction
>& phi
: block
->instructions
) {
775 if (phi
->opcode
!= aco_opcode::p_phi
&&
776 phi
->opcode
!= aco_opcode::p_linear_phi
)
779 /* if the phi is not spilled, add to instructions */
780 if (ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end()) {
781 instructions
.emplace_back(std::move(phi
));
785 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
786 uint32_t def_spill_id
= ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()];
788 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
789 if (phi
->operands
[i
].isUndefined())
792 unsigned pred_idx
= preds
[i
];
793 assert(phi
->operands
[i
].isTemp() && phi
->operands
[i
].isKill());
794 Temp var
= phi
->operands
[i
].getTemp();
796 /* build interferences between the phi def and all spilled variables at the predecessor blocks */
797 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
798 if (var
== pair
.first
)
800 ctx
.interferences
[def_spill_id
].second
.emplace(pair
.second
);
801 ctx
.interferences
[pair
.second
].second
.emplace(def_spill_id
);
804 /* check if variable is already spilled at predecessor */
805 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(var
);
806 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
807 if (spilled
->second
!= def_spill_id
)
808 ctx
.add_affinity(def_spill_id
, spilled
->second
);
812 /* rename if necessary */
813 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
814 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
815 var
= rename_it
->second
;
816 ctx
.renames
[pred_idx
].erase(rename_it
);
819 uint32_t spill_id
= ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
820 ctx
.add_affinity(def_spill_id
, spill_id
);
821 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
822 spill
->operands
[0] = Operand(var
);
823 spill
->operands
[1] = Operand(spill_id
);
824 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
825 unsigned idx
= pred
.instructions
.size();
829 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
830 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
831 pred
.instructions
.insert(it
, std::move(spill
));
832 ctx
.spills_exit
[pred_idx
][phi
->operands
[i
].getTemp()] = spill_id
;
835 /* remove phi from instructions */
839 /* iterate all (other) spilled variables for which to spill at the predecessor */
840 // TODO: would be better to have them sorted: first vgprs and first with longest distance
841 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_entry
[block_idx
]) {
842 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
844 for (unsigned pred_idx
: preds
) {
845 /* variable is already spilled at predecessor */
846 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(pair
.first
);
847 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
848 if (spilled
->second
!= pair
.second
)
849 ctx
.add_affinity(pair
.second
, spilled
->second
);
853 /* variable is dead at predecessor, it must be from a phi: this works because of CSSA form */
854 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
857 /* add interferences between spilled variable and predecessors exit spills */
858 for (std::pair
<Temp
, uint32_t> exit_spill
: ctx
.spills_exit
[pred_idx
]) {
859 if (exit_spill
.first
== pair
.first
)
861 ctx
.interferences
[exit_spill
.second
].second
.emplace(pair
.second
);
862 ctx
.interferences
[pair
.second
].second
.emplace(exit_spill
.second
);
865 /* variable is in register at predecessor and has to be spilled */
866 /* rename if necessary */
867 Temp var
= pair
.first
;
868 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
869 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
870 var
= rename_it
->second
;
871 ctx
.renames
[pred_idx
].erase(rename_it
);
874 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
875 spill
->operands
[0] = Operand(var
);
876 spill
->operands
[1] = Operand(pair
.second
);
877 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
878 unsigned idx
= pred
.instructions
.size();
882 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
883 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
884 pred
.instructions
.insert(it
, std::move(spill
));
885 ctx
.spills_exit
[pred
.index
][pair
.first
] = pair
.second
;
889 /* iterate phis for which operands to reload */
890 for (aco_ptr
<Instruction
>& phi
: instructions
) {
891 assert(phi
->opcode
== aco_opcode::p_phi
|| phi
->opcode
== aco_opcode::p_linear_phi
);
892 assert(ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end());
894 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
895 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
896 if (!phi
->operands
[i
].isTemp())
898 unsigned pred_idx
= preds
[i
];
901 if (ctx
.spills_exit
[pred_idx
].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[pred_idx
].end()) {
902 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(phi
->operands
[i
].getTemp());
903 if (it
!= ctx
.renames
[pred_idx
].end())
904 phi
->operands
[i
].setTemp(it
->second
);
908 Temp tmp
= phi
->operands
[i
].getTemp();
910 /* reload phi operand at end of predecessor block */
911 Temp new_name
= {ctx
.program
->allocateId(), tmp
.regClass()};
912 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
913 unsigned idx
= pred
.instructions
.size();
917 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
918 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
920 aco_ptr
<Instruction
> reload
= do_reload(ctx
, tmp
, new_name
, ctx
.spills_exit
[pred_idx
][tmp
]);
921 pred
.instructions
.insert(it
, std::move(reload
));
923 ctx
.spills_exit
[pred_idx
].erase(tmp
);
924 ctx
.renames
[pred_idx
][tmp
] = new_name
;
925 phi
->operands
[i
].setTemp(new_name
);
929 /* iterate live variables for which to reload */
930 // TODO: reload at current block if variable is spilled on all predecessors
931 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
932 /* skip spilled variables */
933 if (ctx
.spills_entry
[block_idx
].find(pair
.first
) != ctx
.spills_entry
[block_idx
].end())
935 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
937 /* variable is dead at predecessor, it must be from a phi */
938 bool is_dead
= false;
939 for (unsigned pred_idx
: preds
) {
940 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
945 for (unsigned pred_idx
: preds
) {
946 /* the variable is not spilled at the predecessor */
947 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end())
950 /* variable is spilled at predecessor and has to be reloaded */
951 Temp new_name
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
952 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
953 unsigned idx
= pred
.instructions
.size();
957 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
958 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
960 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.first
, new_name
, ctx
.spills_exit
[pred
.index
][pair
.first
]);
961 pred
.instructions
.insert(it
, std::move(reload
));
963 ctx
.spills_exit
[pred
.index
].erase(pair
.first
);
964 ctx
.renames
[pred
.index
][pair
.first
] = new_name
;
967 /* check if we have to create a new phi for this variable */
968 Temp rename
= Temp();
970 for (unsigned pred_idx
: preds
) {
971 if (ctx
.renames
[pred_idx
].find(pair
.first
) == ctx
.renames
[pred_idx
].end()) {
972 if (rename
== Temp())
975 is_same
= rename
== pair
.first
;
977 if (rename
== Temp())
978 rename
= ctx
.renames
[pred_idx
][pair
.first
];
980 is_same
= rename
== ctx
.renames
[pred_idx
][pair
.first
];
988 /* the variable was renamed differently in the predecessors: we have to create a phi */
989 aco_opcode opcode
= pair
.first
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
990 aco_ptr
<Pseudo_instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
991 rename
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
992 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
994 if (ctx
.renames
[preds
[i
]].find(pair
.first
) != ctx
.renames
[preds
[i
]].end())
995 tmp
= ctx
.renames
[preds
[i
]][pair
.first
];
996 else if (preds
[i
] >= block_idx
)
1000 phi
->operands
[i
] = Operand(tmp
);
1002 phi
->definitions
[0] = Definition(rename
);
1003 instructions
.emplace_back(std::move(phi
));
1006 /* the variable was renamed: add new name to renames */
1007 if (!(rename
== Temp() || rename
== pair
.first
))
1008 ctx
.renames
[block_idx
][pair
.first
] = rename
;
1011 /* combine phis with instructions */
1013 while (!block
->instructions
[idx
]) {
1017 if (!ctx
.processed
[block_idx
]) {
1018 assert(!(block
->kind
& block_kind_loop_header
));
1019 RegisterDemand demand_before
= get_demand_before(ctx
, block_idx
, idx
);
1020 ctx
.register_demand
[block
->index
].erase(ctx
.register_demand
[block
->index
].begin(), ctx
.register_demand
[block
->index
].begin() + idx
);
1021 ctx
.register_demand
[block
->index
].insert(ctx
.register_demand
[block
->index
].begin(), instructions
.size(), demand_before
);
1024 std::vector
<aco_ptr
<Instruction
>>::iterator start
= std::next(block
->instructions
.begin(), idx
);
1025 instructions
.insert(instructions
.end(), std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(start
),
1026 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
1027 block
->instructions
= std::move(instructions
);
1030 void process_block(spill_ctx
& ctx
, unsigned block_idx
, Block
* block
,
1031 std::map
<Temp
, uint32_t> ¤t_spills
, RegisterDemand spilled_registers
)
1033 assert(!ctx
.processed
[block_idx
]);
1035 std::vector
<std::map
<Temp
, uint32_t>> local_next_use_distance
;
1036 std::vector
<aco_ptr
<Instruction
>> instructions
;
1039 /* phis are handled separetely */
1040 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
||
1041 block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
) {
1042 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1043 for (const Operand
& op
: instr
->operands
) {
1044 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1045 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1046 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1048 instructions
.emplace_back(std::move(instr
));
1052 if (block
->register_demand
.exceeds(ctx
.target_pressure
))
1053 local_next_use_distance
= local_next_uses(ctx
, block
);
1055 while (idx
< block
->instructions
.size()) {
1056 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1058 std::map
<Temp
, std::pair
<Temp
, uint32_t>> reloads
;
1059 std::map
<Temp
, uint32_t> spills
;
1060 /* rename and reload operands */
1061 for (Operand
& op
: instr
->operands
) {
1064 if (current_spills
.find(op
.getTemp()) == current_spills
.end()) {
1065 /* the Operand is in register: check if it was renamed */
1066 if (ctx
.renames
[block_idx
].find(op
.getTemp()) != ctx
.renames
[block_idx
].end())
1067 op
.setTemp(ctx
.renames
[block_idx
][op
.getTemp()]);
1068 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1069 if (ctx
.remat
.count(op
.getTemp()))
1070 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1073 /* the Operand is spilled: add it to reloads */
1074 Temp new_tmp
= {ctx
.program
->allocateId(), op
.regClass()};
1075 ctx
.renames
[block_idx
][op
.getTemp()] = new_tmp
;
1076 reloads
[new_tmp
] = std::make_pair(op
.getTemp(), current_spills
[op
.getTemp()]);
1077 current_spills
.erase(op
.getTemp());
1078 op
.setTemp(new_tmp
);
1079 spilled_registers
-= new_tmp
;
1082 /* check if register demand is low enough before and after the current instruction */
1083 if (block
->register_demand
.exceeds(ctx
.target_pressure
)) {
1085 RegisterDemand new_demand
= ctx
.register_demand
[block_idx
][idx
];
1086 new_demand
.update(get_demand_before(ctx
, block_idx
, idx
));
1088 assert(!local_next_use_distance
.empty());
1090 /* if reg pressure is too high, spill variable with furthest next use */
1091 while (RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
)) {
1092 unsigned distance
= 0;
1094 bool do_rematerialize
= false;
1095 if (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
1096 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1097 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1098 if (pair
.first
.type() == RegType::vgpr
&&
1099 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1100 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1101 current_spills
.find(pair
.first
) == current_spills
.end() &&
1102 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1103 to_spill
= pair
.first
;
1104 distance
= pair
.second
;
1105 do_rematerialize
= can_rematerialize
;
1109 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1110 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1111 if (pair
.first
.type() == RegType::sgpr
&&
1112 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1113 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1114 current_spills
.find(pair
.first
) == current_spills
.end() &&
1115 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1116 to_spill
= pair
.first
;
1117 distance
= pair
.second
;
1118 do_rematerialize
= can_rematerialize
;
1123 assert(distance
!= 0 && distance
> idx
);
1124 uint32_t spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
1126 /* add interferences with currently spilled variables */
1127 for (std::pair
<Temp
, uint32_t> pair
: current_spills
) {
1128 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
);
1129 ctx
.interferences
[pair
.second
].second
.emplace(spill_id
);
1131 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1132 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
.second
);
1133 ctx
.interferences
[pair
.second
.second
].second
.emplace(spill_id
);
1136 current_spills
[to_spill
] = spill_id
;
1137 spilled_registers
+= to_spill
;
1139 /* rename if necessary */
1140 if (ctx
.renames
[block_idx
].find(to_spill
) != ctx
.renames
[block_idx
].end()) {
1141 to_spill
= ctx
.renames
[block_idx
][to_spill
];
1144 /* add spill to new instructions */
1145 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
1146 spill
->operands
[0] = Operand(to_spill
);
1147 spill
->operands
[1] = Operand(spill_id
);
1148 instructions
.emplace_back(std::move(spill
));
1152 /* add reloads and instruction to new instructions */
1153 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1154 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.second
.first
, pair
.first
, pair
.second
.second
);
1155 instructions
.emplace_back(std::move(reload
));
1157 instructions
.emplace_back(std::move(instr
));
1161 block
->instructions
= std::move(instructions
);
1162 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1165 void spill_block(spill_ctx
& ctx
, unsigned block_idx
)
1167 Block
* block
= &ctx
.program
->blocks
[block_idx
];
1169 /* determine set of variables which are spilled at the beginning of the block */
1170 RegisterDemand spilled_registers
= init_live_in_vars(ctx
, block
, block_idx
);
1172 /* add interferences for spilled variables */
1173 for (std::pair
<Temp
, uint32_t> x
: ctx
.spills_entry
[block_idx
]) {
1174 for (std::pair
<Temp
, uint32_t> y
: ctx
.spills_entry
[block_idx
])
1175 if (x
.second
!= y
.second
)
1176 ctx
.interferences
[x
.second
].second
.emplace(y
.second
);
1179 bool is_loop_header
= block
->loop_nest_depth
&& ctx
.loop_header
.top()->index
== block_idx
;
1180 if (!is_loop_header
) {
1181 /* add spill/reload code on incoming control flow edges */
1182 add_coupling_code(ctx
, block
, block_idx
);
1185 std::map
<Temp
, uint32_t> current_spills
= ctx
.spills_entry
[block_idx
];
1187 /* check conditions to process this block */
1188 bool process
= RegisterDemand(block
->register_demand
- spilled_registers
).exceeds(ctx
.target_pressure
) ||
1189 !ctx
.renames
[block_idx
].empty() ||
1190 ctx
.remat_used
.size();
1192 std::map
<Temp
, uint32_t>::iterator it
= current_spills
.begin();
1193 while (!process
&& it
!= current_spills
.end()) {
1194 if (ctx
.next_use_distances_start
[block_idx
][it
->first
].first
== block_idx
)
1200 process_block(ctx
, block_idx
, block
, current_spills
, spilled_registers
);
1202 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1204 ctx
.processed
[block_idx
] = true;
1206 /* check if the next block leaves the current loop */
1207 if (block
->loop_nest_depth
== 0 || ctx
.program
->blocks
[block_idx
+ 1].loop_nest_depth
>= block
->loop_nest_depth
)
1210 Block
* loop_header
= ctx
.loop_header
.top();
1212 /* preserve original renames at end of loop header block */
1213 std::map
<Temp
, Temp
> renames
= std::move(ctx
.renames
[loop_header
->index
]);
1215 /* add coupling code to all loop header predecessors */
1216 add_coupling_code(ctx
, loop_header
, loop_header
->index
);
1218 /* update remat_used for phis added in add_coupling_code() */
1219 for (aco_ptr
<Instruction
>& instr
: loop_header
->instructions
) {
1222 for (const Operand
& op
: instr
->operands
) {
1223 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1224 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1228 /* propagate new renames through loop: i.e. repair the SSA */
1229 renames
.swap(ctx
.renames
[loop_header
->index
]);
1230 for (std::pair
<Temp
, Temp
> rename
: renames
) {
1231 for (unsigned idx
= loop_header
->index
; idx
<= block_idx
; idx
++) {
1232 Block
& current
= ctx
.program
->blocks
[idx
];
1233 std::vector
<aco_ptr
<Instruction
>>::iterator instr_it
= current
.instructions
.begin();
1235 /* first rename phis */
1236 while (instr_it
!= current
.instructions
.end()) {
1237 aco_ptr
<Instruction
>& phi
= *instr_it
;
1238 if (phi
->opcode
!= aco_opcode::p_phi
&& phi
->opcode
!= aco_opcode::p_linear_phi
)
1240 /* no need to rename the loop header phis once again. this happened in add_coupling_code() */
1241 if (idx
== loop_header
->index
) {
1246 for (Operand
& op
: phi
->operands
) {
1249 if (op
.getTemp() == rename
.first
)
1250 op
.setTemp(rename
.second
);
1255 std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= ctx
.next_use_distances_start
[idx
].find(rename
.first
);
1257 /* variable is not live at beginning of this block */
1258 if (it
== ctx
.next_use_distances_start
[idx
].end())
1261 /* if the variable is live at the block's exit, add rename */
1262 if (ctx
.next_use_distances_end
[idx
].find(rename
.first
) != ctx
.next_use_distances_end
[idx
].end())
1263 ctx
.renames
[idx
].insert(rename
);
1265 /* rename all uses in this block */
1266 bool renamed
= false;
1267 while (!renamed
&& instr_it
!= current
.instructions
.end()) {
1268 aco_ptr
<Instruction
>& instr
= *instr_it
;
1269 for (Operand
& op
: instr
->operands
) {
1272 if (op
.getTemp() == rename
.first
) {
1273 op
.setTemp(rename
.second
);
1274 /* we can stop with this block as soon as the variable is spilled */
1275 if (instr
->opcode
== aco_opcode::p_spill
)
1284 /* remove loop header info from stack */
1285 ctx
.loop_header
.pop();
1288 Temp
load_scratch_resource(spill_ctx
& ctx
, Temp
& scratch_offset
,
1289 std::vector
<aco_ptr
<Instruction
>>& instructions
,
1290 unsigned offset
, bool is_top_level
)
1292 Builder
bld(ctx
.program
);
1294 bld
.reset(&instructions
);
1296 /* find p_logical_end */
1297 unsigned idx
= instructions
.size() - 1;
1298 while (instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
)
1300 bld
.reset(&instructions
, std::next(instructions
.begin(), idx
));
1303 Temp private_segment_buffer
= ctx
.program
->private_segment_buffer
;
1304 if (ctx
.program
->stage
!= compute_cs
)
1305 private_segment_buffer
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, Operand(0u));
1308 scratch_offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), scratch_offset
, Operand(offset
));
1310 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
1311 S_008F0C_INDEX_STRIDE(ctx
.program
->wave_size
== 64 ? 3 : 2);
1313 if (ctx
.program
->chip_class
>= GFX10
) {
1314 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1315 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
1316 S_008F0C_RESOURCE_LEVEL(1);
1317 } else if (ctx
.program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
1318 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1319 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1321 /* older generations need element size = 4 bytes. element size removed in GFX9 */
1322 if (ctx
.program
->chip_class
<= GFX8
)
1323 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
1325 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
1326 private_segment_buffer
, Operand(-1u),
1327 Operand(rsrc_conf
));
1330 void assign_spill_slots(spill_ctx
& ctx
, unsigned spills_to_vgpr
) {
1331 std::map
<uint32_t, uint32_t> sgpr_slot
;
1332 std::map
<uint32_t, uint32_t> vgpr_slot
;
1333 std::vector
<bool> is_assigned(ctx
.interferences
.size());
1335 /* first, handle affinities: just merge all interferences into both spill ids */
1336 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1337 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1338 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1339 assert(vec
[i
] != vec
[j
]);
1340 for (uint32_t id
: ctx
.interferences
[vec
[i
]].second
)
1341 ctx
.interferences
[id
].second
.insert(vec
[j
]);
1342 for (uint32_t id
: ctx
.interferences
[vec
[j
]].second
)
1343 ctx
.interferences
[id
].second
.insert(vec
[i
]);
1344 ctx
.interferences
[vec
[i
]].second
.insert(ctx
.interferences
[vec
[j
]].second
.begin(), ctx
.interferences
[vec
[j
]].second
.end());
1345 ctx
.interferences
[vec
[j
]].second
.insert(ctx
.interferences
[vec
[i
]].second
.begin(), ctx
.interferences
[vec
[i
]].second
.end());
1347 bool reloaded
= ctx
.is_reloaded
[vec
[i
]] || ctx
.is_reloaded
[vec
[j
]];
1348 ctx
.is_reloaded
[vec
[i
]] = reloaded
;
1349 ctx
.is_reloaded
[vec
[j
]] = reloaded
;
1353 for (ASSERTED
uint32_t i
= 0; i
< ctx
.interferences
.size(); i
++)
1354 for (ASSERTED
uint32_t id
: ctx
.interferences
[i
].second
)
1357 /* for each spill slot, assign as many spill ids as possible */
1358 std::vector
<std::set
<uint32_t>> spill_slot_interferences
;
1359 unsigned slot_idx
= 0;
1362 /* assign sgpr spill slots */
1365 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1366 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1368 if (ctx
.interferences
[id
].first
.type() != RegType::sgpr
)
1371 /* check interferences */
1372 bool interferes
= false;
1373 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1374 if (i
== spill_slot_interferences
.size())
1375 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1376 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end() || i
/ ctx
.wave_size
!= slot_idx
/ ctx
.wave_size
) {
1386 /* we found a spill id which can be assigned to current spill slot */
1387 sgpr_slot
[id
] = slot_idx
;
1388 is_assigned
[id
] = true;
1389 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1390 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1392 /* add all affinities: there are no additional interferences */
1393 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1394 bool found_affinity
= false;
1395 for (uint32_t entry
: vec
) {
1397 found_affinity
= true;
1401 if (!found_affinity
)
1403 for (uint32_t entry
: vec
) {
1404 sgpr_slot
[entry
] = slot_idx
;
1405 is_assigned
[entry
] = true;
1412 unsigned sgpr_spill_slots
= spill_slot_interferences
.size();
1413 spill_slot_interferences
.clear();
1417 /* assign vgpr spill slots */
1420 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1421 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1423 if (ctx
.interferences
[id
].first
.type() != RegType::vgpr
)
1426 /* check interferences */
1427 bool interferes
= false;
1428 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1429 if (i
== spill_slot_interferences
.size())
1430 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1431 /* check for interference and ensure that vector regs are stored next to each other */
1432 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end()) {
1442 /* we found a spill id which can be assigned to current spill slot */
1443 vgpr_slot
[id
] = slot_idx
;
1444 is_assigned
[id
] = true;
1445 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1446 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1448 /* add all affinities: there are no additional interferences */
1449 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1450 bool found_affinity
= false;
1451 for (uint32_t entry
: vec
) {
1453 found_affinity
= true;
1457 if (!found_affinity
)
1459 for (uint32_t entry
: vec
) {
1460 vgpr_slot
[entry
] = slot_idx
;
1461 is_assigned
[entry
] = true;
1468 unsigned vgpr_spill_slots
= spill_slot_interferences
.size();
1470 for (unsigned id
= 0; id
< is_assigned
.size(); id
++)
1471 assert(is_assigned
[id
] || !ctx
.is_reloaded
[id
]);
1473 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1474 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1475 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1476 assert(is_assigned
[vec
[i
]] == is_assigned
[vec
[j
]]);
1477 if (!is_assigned
[vec
[i
]])
1479 assert(ctx
.is_reloaded
[vec
[i
]] == ctx
.is_reloaded
[vec
[j
]]);
1480 assert(ctx
.interferences
[vec
[i
]].first
.type() == ctx
.interferences
[vec
[j
]].first
.type());
1481 if (ctx
.interferences
[vec
[i
]].first
.type() == RegType::sgpr
)
1482 assert(sgpr_slot
[vec
[i
]] == sgpr_slot
[vec
[j
]]);
1484 assert(vgpr_slot
[vec
[i
]] == vgpr_slot
[vec
[j
]]);
1489 /* hope, we didn't mess up */
1490 std::vector
<Temp
> vgpr_spill_temps((sgpr_spill_slots
+ ctx
.wave_size
- 1) / ctx
.wave_size
);
1491 assert(vgpr_spill_temps
.size() <= spills_to_vgpr
);
1493 /* replace pseudo instructions with actual hardware instructions */
1494 Temp scratch_offset
= ctx
.program
->scratch_offset
, scratch_rsrc
= Temp();
1495 unsigned last_top_level_block_idx
= 0;
1496 std::vector
<bool> reload_in_loop(vgpr_spill_temps
.size());
1497 for (Block
& block
: ctx
.program
->blocks
) {
1499 /* after loops, we insert a user if there was a reload inside the loop */
1500 if (block
.loop_nest_depth
== 0) {
1502 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1503 if (reload_in_loop
[i
])
1507 if (end_vgprs
> 0) {
1508 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, end_vgprs
, 0)};
1510 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1511 if (reload_in_loop
[i
])
1512 destr
->operands
[k
++] = Operand(vgpr_spill_temps
[i
]);
1513 reload_in_loop
[i
] = false;
1515 /* find insertion point */
1516 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1517 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1519 block
.instructions
.insert(it
, std::move(destr
));
1523 if (block
.kind
& block_kind_top_level
&& !block
.linear_preds
.empty()) {
1524 last_top_level_block_idx
= block
.index
;
1526 /* check if any spilled variables use a created linear vgpr, otherwise destroy them */
1527 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1528 if (vgpr_spill_temps
[i
] == Temp())
1531 bool can_destroy
= true;
1532 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[block
.linear_preds
[0]]) {
1534 if (sgpr_slot
.find(pair
.second
) != sgpr_slot
.end() &&
1535 sgpr_slot
[pair
.second
] / ctx
.wave_size
== i
) {
1536 can_destroy
= false;
1541 vgpr_spill_temps
[i
] = Temp();
1545 std::vector
<aco_ptr
<Instruction
>>::iterator it
;
1546 std::vector
<aco_ptr
<Instruction
>> instructions
;
1547 instructions
.reserve(block
.instructions
.size());
1548 Builder
bld(ctx
.program
, &instructions
);
1549 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1551 if ((*it
)->opcode
== aco_opcode::p_spill
) {
1552 uint32_t spill_id
= (*it
)->operands
[1].constantValue();
1554 if (!ctx
.is_reloaded
[spill_id
]) {
1555 /* never reloaded, so don't spill */
1556 } else if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1558 ctx
.program
->config
->spilled_vgprs
+= (*it
)->operands
[0].size();
1559 uint32_t spill_slot
= vgpr_slot
[spill_id
];
1560 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1561 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1563 /* check if the scratch resource descriptor already exists */
1564 if (scratch_rsrc
== Temp()) {
1565 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1566 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1567 last_top_level_block_idx
== block
.index
?
1568 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1570 last_top_level_block_idx
== block
.index
);
1573 unsigned offset
= base_offset
+ spill_slot
* 4;
1574 aco_opcode opcode
= aco_opcode::buffer_store_dword
;
1575 assert((*it
)->operands
[0].isTemp());
1576 Temp temp
= (*it
)->operands
[0].getTemp();
1577 assert(temp
.type() == RegType::vgpr
&& !temp
.is_linear());
1578 if (temp
.size() > 1) {
1579 Instruction
* split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, temp
.size())};
1580 split
->operands
[0] = Operand(temp
);
1581 for (unsigned i
= 0; i
< temp
.size(); i
++)
1582 split
->definitions
[i
] = bld
.def(v1
);
1584 for (unsigned i
= 0; i
< temp
.size(); i
++)
1585 bld
.mubuf(opcode
, scratch_rsrc
, Operand(v1
), scratch_offset
, split
->definitions
[i
].getTemp(), offset
+ i
* 4, false);
1587 bld
.mubuf(opcode
, scratch_rsrc
, Operand(v1
), scratch_offset
, temp
, offset
, false);
1589 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1590 ctx
.program
->config
->spilled_sgprs
+= (*it
)->operands
[0].size();
1592 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1594 /* check if the linear vgpr already exists */
1595 if (vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] == Temp()) {
1596 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1597 vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] = linear_vgpr
;
1598 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1599 create
->definitions
[0] = Definition(linear_vgpr
);
1600 /* find the right place to insert this definition */
1601 if (last_top_level_block_idx
== block
.index
) {
1602 /* insert right before the current instruction */
1603 instructions
.emplace_back(std::move(create
));
1605 assert(last_top_level_block_idx
< block
.index
);
1606 /* insert before the branch at last top level block */
1607 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1608 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1612 /* spill sgpr: just add the vgpr temp to operands */
1613 Pseudo_instruction
* spill
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 3, 0);
1614 spill
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
]);
1615 spill
->operands
[1] = Operand(spill_slot
% ctx
.wave_size
);
1616 spill
->operands
[2] = (*it
)->operands
[0];
1617 instructions
.emplace_back(aco_ptr
<Instruction
>(spill
));
1619 unreachable("No spill slot assigned for spill id");
1622 } else if ((*it
)->opcode
== aco_opcode::p_reload
) {
1623 uint32_t spill_id
= (*it
)->operands
[0].constantValue();
1624 assert(ctx
.is_reloaded
[spill_id
]);
1626 if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1628 uint32_t spill_slot
= vgpr_slot
[spill_id
];
1629 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1630 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1632 /* check if the scratch resource descriptor already exists */
1633 if (scratch_rsrc
== Temp()) {
1634 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1635 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1636 last_top_level_block_idx
== block
.index
?
1637 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1639 last_top_level_block_idx
== block
.index
);
1642 unsigned offset
= base_offset
+ spill_slot
* 4;
1643 aco_opcode opcode
= aco_opcode::buffer_load_dword
;
1644 Definition def
= (*it
)->definitions
[0];
1645 if (def
.size() > 1) {
1646 Instruction
* vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, def
.size(), 1)};
1647 vec
->definitions
[0] = def
;
1648 for (unsigned i
= 0; i
< def
.size(); i
++) {
1649 Temp tmp
= bld
.tmp(v1
);
1650 vec
->operands
[i
] = Operand(tmp
);
1651 bld
.mubuf(opcode
, Definition(tmp
), scratch_rsrc
, Operand(v1
), scratch_offset
, offset
+ i
* 4, false);
1655 bld
.mubuf(opcode
, def
, scratch_rsrc
, Operand(v1
), scratch_offset
, offset
, false);
1657 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1658 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1659 reload_in_loop
[spill_slot
/ ctx
.wave_size
] = block
.loop_nest_depth
> 0;
1661 /* check if the linear vgpr already exists */
1662 if (vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] == Temp()) {
1663 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1664 vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] = linear_vgpr
;
1665 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1666 create
->definitions
[0] = Definition(linear_vgpr
);
1667 /* find the right place to insert this definition */
1668 if (last_top_level_block_idx
== block
.index
) {
1669 /* insert right before the current instruction */
1670 instructions
.emplace_back(std::move(create
));
1672 assert(last_top_level_block_idx
< block
.index
);
1673 /* insert before the branch at last top level block */
1674 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1675 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1679 /* reload sgpr: just add the vgpr temp to operands */
1680 Pseudo_instruction
* reload
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 2, 1);
1681 reload
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
]);
1682 reload
->operands
[1] = Operand(spill_slot
% ctx
.wave_size
);
1683 reload
->definitions
[0] = (*it
)->definitions
[0];
1684 instructions
.emplace_back(aco_ptr
<Instruction
>(reload
));
1686 unreachable("No spill slot assigned for spill id");
1688 } else if (!ctx
.remat_used
.count(it
->get()) || ctx
.remat_used
[it
->get()]) {
1689 instructions
.emplace_back(std::move(*it
));
1693 block
.instructions
= std::move(instructions
);
1696 /* update required scratch memory */
1697 ctx
.program
->config
->scratch_bytes_per_wave
+= align(vgpr_spill_slots
* 4 * ctx
.program
->wave_size
, 1024);
1699 /* SSA elimination inserts copies for logical phis right before p_logical_end
1700 * So if a linear vgpr is used between that p_logical_end and the branch,
1701 * we need to ensure logical phis don't choose a definition which aliases
1703 * TODO: Moving the spills and reloads to before p_logical_end might produce
1704 * slightly better code. */
1705 for (Block
& block
: ctx
.program
->blocks
) {
1706 /* loops exits are already handled */
1707 if (block
.logical_preds
.size() <= 1)
1710 bool has_logical_phis
= false;
1711 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
1712 if (instr
->opcode
== aco_opcode::p_phi
) {
1713 has_logical_phis
= true;
1715 } else if (instr
->opcode
!= aco_opcode::p_linear_phi
) {
1719 if (!has_logical_phis
)
1722 std::set
<Temp
> vgprs
;
1723 for (unsigned pred_idx
: block
.logical_preds
) {
1724 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
1725 for (int i
= pred
.instructions
.size() - 1; i
>= 0; i
--) {
1726 aco_ptr
<Instruction
>& pred_instr
= pred
.instructions
[i
];
1727 if (pred_instr
->opcode
== aco_opcode::p_logical_end
) {
1729 } else if (pred_instr
->opcode
== aco_opcode::p_spill
||
1730 pred_instr
->opcode
== aco_opcode::p_reload
) {
1731 vgprs
.insert(pred_instr
->operands
[0].getTemp());
1738 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, vgprs
.size(), 0)};
1740 for (Temp tmp
: vgprs
) {
1741 destr
->operands
[k
++] = Operand(tmp
);
1743 /* find insertion point */
1744 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1745 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1747 block
.instructions
.insert(it
, std::move(destr
));
1751 } /* end namespace */
1754 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
)
1756 program
->config
->spilled_vgprs
= 0;
1757 program
->config
->spilled_sgprs
= 0;
1759 /* no spilling when register pressure is low enough */
1760 if (program
->num_waves
> 0)
1763 /* lower to CSSA before spilling to ensure correctness w.r.t. phis */
1764 lower_to_cssa(program
, live_vars
, options
);
1766 /* calculate target register demand */
1767 RegisterDemand register_target
= program
->max_reg_demand
;
1768 if (register_target
.sgpr
> program
->sgpr_limit
)
1769 register_target
.vgpr
+= (register_target
.sgpr
- program
->sgpr_limit
+ program
->wave_size
- 1 + 32) / program
->wave_size
;
1770 register_target
.sgpr
= program
->sgpr_limit
;
1772 if (register_target
.vgpr
> program
->vgpr_limit
)
1773 register_target
.sgpr
= program
->sgpr_limit
- 5;
1774 int spills_to_vgpr
= (program
->max_reg_demand
.sgpr
- register_target
.sgpr
+ program
->wave_size
- 1 + 32) / program
->wave_size
;
1775 register_target
.vgpr
= program
->vgpr_limit
- spills_to_vgpr
;
1777 /* initialize ctx */
1778 spill_ctx
ctx(register_target
, program
, live_vars
.register_demand
);
1779 compute_global_next_uses(ctx
);
1780 get_rematerialize_info(ctx
);
1782 /* create spills and reloads */
1783 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++)
1784 spill_block(ctx
, i
);
1786 /* assign spill slots and DCE rematerialized code */
1787 assign_spill_slots(ctx
, spills_to_vgpr
);
1789 /* update live variable information */
1790 live_vars
= live_var_analysis(program
, options
);
1792 assert(program
->num_waves
> 0);