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27 #include "aco_builder.h"
35 * Implements the spilling algorithm on SSA-form from
36 * "Register Spilling and Live-Range Splitting for SSA-Form Programs"
37 * by Matthias Braun and Sebastian Hack.
49 RegisterDemand target_pressure
;
51 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
52 std::vector
<std::map
<Temp
, Temp
>> renames
;
53 std::vector
<std::map
<Temp
, uint32_t>> spills_entry
;
54 std::vector
<std::map
<Temp
, uint32_t>> spills_exit
;
55 std::vector
<bool> processed
;
56 std::stack
<Block
*> loop_header
;
57 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_start
;
58 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_end
;
59 std::vector
<std::pair
<RegClass
, std::unordered_set
<uint32_t>>> interferences
;
60 std::vector
<std::vector
<uint32_t>> affinities
;
61 std::vector
<bool> is_reloaded
;
62 std::map
<Temp
, remat_info
> remat
;
63 std::map
<Instruction
*, bool> remat_used
;
66 spill_ctx(const RegisterDemand target_pressure
, Program
* program
,
67 std::vector
<std::vector
<RegisterDemand
>> register_demand
)
68 : target_pressure(target_pressure
), program(program
),
69 register_demand(std::move(register_demand
)), renames(program
->blocks
.size()),
70 spills_entry(program
->blocks
.size()), spills_exit(program
->blocks
.size()),
71 processed(program
->blocks
.size(), false), wave_size(program
->wave_size
) {}
73 void add_affinity(uint32_t first
, uint32_t second
)
75 unsigned found_first
= affinities
.size();
76 unsigned found_second
= affinities
.size();
77 for (unsigned i
= 0; i
< affinities
.size(); i
++) {
78 std::vector
<uint32_t>& vec
= affinities
[i
];
79 for (uint32_t entry
: vec
) {
82 else if (entry
== second
)
86 if (found_first
== affinities
.size() && found_second
== affinities
.size()) {
87 affinities
.emplace_back(std::vector
<uint32_t>({first
, second
}));
88 } else if (found_first
< affinities
.size() && found_second
== affinities
.size()) {
89 affinities
[found_first
].push_back(second
);
90 } else if (found_second
< affinities
.size() && found_first
== affinities
.size()) {
91 affinities
[found_second
].push_back(first
);
92 } else if (found_first
!= found_second
) {
93 /* merge second into first */
94 affinities
[found_first
].insert(affinities
[found_first
].end(), affinities
[found_second
].begin(), affinities
[found_second
].end());
95 affinities
.erase(std::next(affinities
.begin(), found_second
));
97 assert(found_first
== found_second
);
101 void add_interference(uint32_t first
, uint32_t second
)
103 if (interferences
[first
].first
.type() != interferences
[second
].first
.type())
106 bool inserted
= interferences
[first
].second
.insert(second
).second
;
108 interferences
[second
].second
.insert(first
);
111 uint32_t allocate_spill_id(RegClass rc
)
113 interferences
.emplace_back(rc
, std::unordered_set
<uint32_t>());
114 is_reloaded
.push_back(false);
115 return next_spill_id
++;
118 uint32_t next_spill_id
= 0;
121 int32_t get_dominator(int idx_a
, int idx_b
, Program
* program
, bool is_linear
)
129 while (idx_a
!= idx_b
) {
131 idx_a
= program
->blocks
[idx_a
].linear_idom
;
133 idx_b
= program
->blocks
[idx_b
].linear_idom
;
136 while (idx_a
!= idx_b
) {
138 idx_a
= program
->blocks
[idx_a
].logical_idom
;
140 idx_b
= program
->blocks
[idx_b
].logical_idom
;
147 void next_uses_per_block(spill_ctx
& ctx
, unsigned block_idx
, std::set
<uint32_t>& worklist
)
149 Block
* block
= &ctx
.program
->blocks
[block_idx
];
150 std::map
<Temp
, std::pair
<uint32_t, uint32_t>> next_uses
= ctx
.next_use_distances_end
[block_idx
];
152 /* to compute the next use distance at the beginning of the block, we have to add the block's size */
153 for (std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= next_uses
.begin(); it
!= next_uses
.end(); ++it
)
154 it
->second
.second
= it
->second
.second
+ block
->instructions
.size();
156 int idx
= block
->instructions
.size() - 1;
158 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
160 if (instr
->opcode
== aco_opcode::p_linear_phi
||
161 instr
->opcode
== aco_opcode::p_phi
)
164 for (const Definition
& def
: instr
->definitions
) {
166 next_uses
.erase(def
.getTemp());
169 for (const Operand
& op
: instr
->operands
) {
171 if (op
.isFixed() && op
.physReg() == exec
)
173 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
176 next_uses
[op
.getTemp()] = {block_idx
, idx
};
181 assert(block_idx
!= 0 || next_uses
.empty());
182 ctx
.next_use_distances_start
[block_idx
] = next_uses
;
184 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
185 assert(instr
->opcode
== aco_opcode::p_linear_phi
|| instr
->opcode
== aco_opcode::p_phi
);
187 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
188 unsigned pred_idx
= instr
->opcode
== aco_opcode::p_phi
?
189 block
->logical_preds
[i
] :
190 block
->linear_preds
[i
];
191 if (instr
->operands
[i
].isTemp()) {
192 if (instr
->operands
[i
].getTemp() == ctx
.program
->blocks
[pred_idx
].live_out_exec
)
194 if (ctx
.next_use_distances_end
[pred_idx
].find(instr
->operands
[i
].getTemp()) == ctx
.next_use_distances_end
[pred_idx
].end() ||
195 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] != std::pair
<uint32_t, uint32_t>{block_idx
, 0})
196 worklist
.insert(pred_idx
);
197 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] = {block_idx
, 0};
200 next_uses
.erase(instr
->definitions
[0].getTemp());
204 /* all remaining live vars must be live-out at the predecessors */
205 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: next_uses
) {
206 Temp temp
= pair
.first
;
207 uint32_t distance
= pair
.second
.second
;
208 uint32_t dom
= pair
.second
.first
;
209 std::vector
<unsigned>& preds
= temp
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
210 for (unsigned pred_idx
: preds
) {
211 if (temp
== ctx
.program
->blocks
[pred_idx
].live_out_exec
)
213 if (ctx
.program
->blocks
[pred_idx
].loop_nest_depth
> block
->loop_nest_depth
)
215 if (ctx
.next_use_distances_end
[pred_idx
].find(temp
) != ctx
.next_use_distances_end
[pred_idx
].end()) {
216 dom
= get_dominator(dom
, ctx
.next_use_distances_end
[pred_idx
][temp
].first
, ctx
.program
, temp
.is_linear());
217 distance
= std::min(ctx
.next_use_distances_end
[pred_idx
][temp
].second
, distance
);
219 if (ctx
.next_use_distances_end
[pred_idx
][temp
] != std::pair
<uint32_t, uint32_t>{dom
, distance
})
220 worklist
.insert(pred_idx
);
221 ctx
.next_use_distances_end
[pred_idx
][temp
] = {dom
, distance
};
227 void compute_global_next_uses(spill_ctx
& ctx
)
229 ctx
.next_use_distances_start
.resize(ctx
.program
->blocks
.size());
230 ctx
.next_use_distances_end
.resize(ctx
.program
->blocks
.size());
231 std::set
<uint32_t> worklist
;
232 for (Block
& block
: ctx
.program
->blocks
)
233 worklist
.insert(block
.index
);
235 while (!worklist
.empty()) {
236 std::set
<unsigned>::reverse_iterator b_it
= worklist
.rbegin();
237 unsigned block_idx
= *b_it
;
238 worklist
.erase(block_idx
);
239 next_uses_per_block(ctx
, block_idx
, worklist
);
243 bool should_rematerialize(aco_ptr
<Instruction
>& instr
)
245 /* TODO: rematerialization is only supported for VOP1, SOP1 and PSEUDO */
246 if (instr
->format
!= Format::VOP1
&& instr
->format
!= Format::SOP1
&& instr
->format
!= Format::PSEUDO
&& instr
->format
!= Format::SOPK
)
248 /* TODO: pseudo-instruction rematerialization is only supported for p_create_vector */
249 if (instr
->format
== Format::PSEUDO
&& instr
->opcode
!= aco_opcode::p_create_vector
)
251 if (instr
->format
== Format::SOPK
&& instr
->opcode
!= aco_opcode::s_movk_i32
)
254 for (const Operand
& op
: instr
->operands
) {
255 /* TODO: rematerialization using temporaries isn't yet supported */
260 /* TODO: rematerialization with multiple definitions isn't yet supported */
261 if (instr
->definitions
.size() > 1)
267 aco_ptr
<Instruction
> do_reload(spill_ctx
& ctx
, Temp tmp
, Temp new_name
, uint32_t spill_id
)
269 std::map
<Temp
, remat_info
>::iterator remat
= ctx
.remat
.find(tmp
);
270 if (remat
!= ctx
.remat
.end()) {
271 Instruction
*instr
= remat
->second
.instr
;
272 assert((instr
->format
== Format::VOP1
|| instr
->format
== Format::SOP1
|| instr
->format
== Format::PSEUDO
|| instr
->format
== Format::SOPK
) && "unsupported");
273 assert((instr
->format
!= Format::PSEUDO
|| instr
->opcode
== aco_opcode::p_create_vector
) && "unsupported");
274 assert(instr
->definitions
.size() == 1 && "unsupported");
276 aco_ptr
<Instruction
> res
;
277 if (instr
->format
== Format::VOP1
) {
278 res
.reset(create_instruction
<VOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
279 } else if (instr
->format
== Format::SOP1
) {
280 res
.reset(create_instruction
<SOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
281 } else if (instr
->format
== Format::PSEUDO
) {
282 res
.reset(create_instruction
<Pseudo_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
283 } else if (instr
->format
== Format::SOPK
) {
284 res
.reset(create_instruction
<SOPK_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
285 static_cast<SOPK_instruction
*>(res
.get())->imm
= static_cast<SOPK_instruction
*>(instr
)->imm
;
287 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
288 res
->operands
[i
] = instr
->operands
[i
];
289 if (instr
->operands
[i
].isTemp()) {
290 assert(false && "unsupported");
291 if (ctx
.remat
.count(instr
->operands
[i
].getTemp()))
292 ctx
.remat_used
[ctx
.remat
[instr
->operands
[i
].getTemp()].instr
] = true;
295 res
->definitions
[0] = Definition(new_name
);
298 aco_ptr
<Pseudo_instruction
> reload
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 1, 1)};
299 reload
->operands
[0] = Operand(spill_id
);
300 reload
->definitions
[0] = Definition(new_name
);
301 ctx
.is_reloaded
[spill_id
] = true;
306 void get_rematerialize_info(spill_ctx
& ctx
)
308 for (Block
& block
: ctx
.program
->blocks
) {
309 bool logical
= false;
310 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
311 if (instr
->opcode
== aco_opcode::p_logical_start
)
313 else if (instr
->opcode
== aco_opcode::p_logical_end
)
315 if (logical
&& should_rematerialize(instr
)) {
316 for (const Definition
& def
: instr
->definitions
) {
318 ctx
.remat
[def
.getTemp()] = (remat_info
){instr
.get()};
319 ctx
.remat_used
[instr
.get()] = false;
327 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(spill_ctx
& ctx
, Block
* block
)
329 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(block
->instructions
.size());
331 std::map
<Temp
, uint32_t> next_uses
;
332 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block
->index
])
333 next_uses
[pair
.first
] = pair
.second
.second
+ block
->instructions
.size();
335 for (int idx
= block
->instructions
.size() - 1; idx
>= 0; idx
--) {
336 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
339 if (instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
)
342 for (const Operand
& op
: instr
->operands
) {
343 if (op
.isFixed() && op
.physReg() == exec
)
345 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
348 next_uses
[op
.getTemp()] = idx
;
350 for (const Definition
& def
: instr
->definitions
) {
352 next_uses
.erase(def
.getTemp());
354 local_next_uses
[idx
] = next_uses
;
356 return local_next_uses
;
360 RegisterDemand
init_live_in_vars(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
362 RegisterDemand spilled_registers
;
364 /* first block, nothing was spilled before */
368 /* loop header block */
369 if (block
->loop_nest_depth
> ctx
.program
->blocks
[block_idx
- 1].loop_nest_depth
) {
370 assert(block
->linear_preds
[0] == block_idx
- 1);
371 assert(block
->logical_preds
[0] == block_idx
- 1);
373 /* create new loop_info */
374 ctx
.loop_header
.emplace(block
);
376 /* check how many live-through variables should be spilled */
377 RegisterDemand new_demand
;
378 unsigned i
= block_idx
;
379 while (ctx
.program
->blocks
[i
].loop_nest_depth
>= block
->loop_nest_depth
) {
380 assert(ctx
.program
->blocks
.size() > i
);
381 new_demand
.update(ctx
.program
->blocks
[i
].register_demand
);
384 unsigned loop_end
= i
;
386 /* select live-through vgpr variables */
387 while (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
388 unsigned distance
= 0;
390 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
391 if (pair
.first
.type() == RegType::vgpr
&&
392 pair
.second
.first
>= loop_end
&&
393 pair
.second
.second
> distance
&&
394 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
395 to_spill
= pair
.first
;
396 distance
= pair
.second
.second
;
403 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
404 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
406 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
409 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
410 spilled_registers
.vgpr
+= to_spill
.size();
413 /* select live-through sgpr variables */
414 while (new_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
415 unsigned distance
= 0;
417 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
418 if (pair
.first
.type() == RegType::sgpr
&&
419 pair
.second
.first
>= loop_end
&&
420 pair
.second
.second
> distance
&&
421 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
422 to_spill
= pair
.first
;
423 distance
= pair
.second
.second
;
430 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
431 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
433 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
436 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
437 spilled_registers
.sgpr
+= to_spill
.size();
443 if (!RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
))
444 return spilled_registers
;
446 /* if reg pressure is too high at beginning of loop, add variables with furthest use */
448 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
|| block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
)
451 assert(idx
!= 0 && "loop without phis: TODO");
453 RegisterDemand reg_pressure
= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
454 /* Consider register pressure from linear predecessors. This can affect
455 * reg_pressure if the branch instructions define sgprs. */
456 for (unsigned pred
: block
->linear_preds
) {
457 reg_pressure
.sgpr
= std::max
<int16_t>(
458 reg_pressure
.sgpr
, ctx
.register_demand
[pred
].back().sgpr
- spilled_registers
.sgpr
);
461 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
462 unsigned distance
= 0;
464 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
465 if (pair
.first
.type() == RegType::sgpr
&&
466 pair
.second
.second
> distance
&&
467 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
468 to_spill
= pair
.first
;
469 distance
= pair
.second
.second
;
472 assert(distance
!= 0);
474 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
475 spilled_registers
.sgpr
+= to_spill
.size();
476 reg_pressure
.sgpr
-= to_spill
.size();
478 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
479 unsigned distance
= 0;
481 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
482 if (pair
.first
.type() == RegType::vgpr
&&
483 pair
.second
.second
> distance
&&
484 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
485 to_spill
= pair
.first
;
486 distance
= pair
.second
.second
;
489 assert(distance
!= 0);
490 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
491 spilled_registers
.vgpr
+= to_spill
.size();
492 reg_pressure
.vgpr
-= to_spill
.size();
495 return spilled_registers
;
499 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
500 /* keep variables spilled if they are alive and not used in the current block */
501 unsigned pred_idx
= block
->linear_preds
[0];
502 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
503 if (pair
.first
.type() == RegType::sgpr
&&
504 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
505 ctx
.next_use_distances_start
[block_idx
][pair
.first
].first
!= block_idx
) {
506 ctx
.spills_entry
[block_idx
].insert(pair
);
507 spilled_registers
.sgpr
+= pair
.first
.size();
510 if (block
->logical_preds
.size() == 1) {
511 pred_idx
= block
->logical_preds
[0];
512 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
513 if (pair
.first
.type() == RegType::vgpr
&&
514 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
515 ctx
.next_use_distances_start
[block_idx
][pair
.first
].first
!= block_idx
) {
516 ctx
.spills_entry
[block_idx
].insert(pair
);
517 spilled_registers
.vgpr
+= pair
.first
.size();
522 /* if register demand is still too high, we just keep all spilled live vars and process the block */
523 if (block
->register_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
524 pred_idx
= block
->linear_preds
[0];
525 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
526 if (pair
.first
.type() == RegType::sgpr
&&
527 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
528 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
529 spilled_registers
.sgpr
+= pair
.first
.size();
533 if (block
->register_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
&& block
->logical_preds
.size() == 1) {
534 pred_idx
= block
->logical_preds
[0];
535 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
536 if (pair
.first
.type() == RegType::vgpr
&&
537 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
538 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
539 spilled_registers
.vgpr
+= pair
.first
.size();
544 return spilled_registers
;
547 /* else: merge block */
548 std::set
<Temp
> partial_spills
;
550 /* keep variables spilled on all incoming paths */
551 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
552 std::vector
<unsigned>& preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
553 /* If it can be rematerialized, keep the variable spilled if all predecessors do not reload it.
554 * Otherwise, if any predecessor reloads it, ensure it's reloaded on all other predecessors.
555 * The idea is that it's better in practice to rematerialize redundantly than to create lots of phis. */
556 /* TODO: test this idea with more than Dawn of War III shaders (the current pipeline-db doesn't seem to exercise this path much) */
557 bool remat
= ctx
.remat
.count(pair
.first
);
559 uint32_t spill_id
= 0;
560 for (unsigned pred_idx
: preds
) {
561 /* variable is not even live at the predecessor: probably from a phi */
562 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end()) {
566 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
570 partial_spills
.insert(pair
.first
);
571 /* it might be that on one incoming path, the variable has a different spill_id, but add_couple_code() will take care of that. */
572 spill_id
= ctx
.spills_exit
[pred_idx
][pair
.first
];
578 ctx
.spills_entry
[block_idx
][pair
.first
] = spill_id
;
579 partial_spills
.erase(pair
.first
);
580 spilled_registers
+= pair
.first
;
586 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
||
587 block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
) {
588 aco_ptr
<Instruction
>& phi
= block
->instructions
[idx
];
589 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
592 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
593 if (phi
->operands
[i
].isUndefined())
595 assert(phi
->operands
[i
].isTemp());
596 if (ctx
.spills_exit
[preds
[i
]].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[preds
[i
]].end())
599 partial_spills
.insert(phi
->definitions
[0].getTemp());
602 ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()] = ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
603 partial_spills
.erase(phi
->definitions
[0].getTemp());
604 spilled_registers
+= phi
->definitions
[0].getTemp();
610 /* if reg pressure at first instruction is still too high, add partially spilled variables */
611 RegisterDemand reg_pressure
;
613 for (const Definition
& def
: block
->instructions
[idx
]->definitions
) {
615 reg_pressure
-= def
.getTemp();
618 for (const Operand
& op
: block
->instructions
[idx
]->operands
) {
619 if (op
.isTemp() && op
.isFirstKill()) {
620 reg_pressure
+= op
.getTemp();
624 for (unsigned i
= 0; i
< idx
; i
++) {
625 aco_ptr
<Instruction
>& instr
= block
->instructions
[i
];
626 assert(is_phi(instr
));
627 /* Killed phi definitions increase pressure in the predecessor but not
628 * the block they're in. Since the loops below are both to control
629 * pressure of the start of this block and the ends of it's
630 * predecessors, we need to count killed unspilled phi definitions here. */
631 if (instr
->definitions
[0].isKill() &&
632 !ctx
.spills_entry
[block_idx
].count(instr
->definitions
[0].getTemp()))
633 reg_pressure
+= instr
->definitions
[0].getTemp();
637 reg_pressure
+= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
639 /* Consider register pressure from linear predecessors. This can affect
640 * reg_pressure if the branch instructions define sgprs. */
641 for (unsigned pred
: block
->linear_preds
) {
642 reg_pressure
.sgpr
= std::max
<int16_t>(
643 reg_pressure
.sgpr
, ctx
.register_demand
[pred
].back().sgpr
- spilled_registers
.sgpr
);
646 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
647 assert(!partial_spills
.empty());
649 std::set
<Temp
>::iterator it
= partial_spills
.begin();
650 Temp to_spill
= Temp();
651 unsigned distance
= 0;
652 while (it
!= partial_spills
.end()) {
653 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
655 if (it
->type() == RegType::sgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
656 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
661 assert(distance
!= 0);
663 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
664 partial_spills
.erase(to_spill
);
665 spilled_registers
.sgpr
+= to_spill
.size();
666 reg_pressure
.sgpr
-= to_spill
.size();
669 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
670 assert(!partial_spills
.empty());
672 std::set
<Temp
>::iterator it
= partial_spills
.begin();
673 Temp to_spill
= Temp();
674 unsigned distance
= 0;
675 while (it
!= partial_spills
.end()) {
676 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
678 if (it
->type() == RegType::vgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
679 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
684 assert(distance
!= 0);
686 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
687 partial_spills
.erase(to_spill
);
688 spilled_registers
.vgpr
+= to_spill
.size();
689 reg_pressure
.vgpr
-= to_spill
.size();
692 return spilled_registers
;
696 RegisterDemand
get_demand_before(spill_ctx
& ctx
, unsigned block_idx
, unsigned idx
)
699 RegisterDemand demand
= ctx
.register_demand
[block_idx
][idx
];
700 aco_ptr
<Instruction
>& instr
= ctx
.program
->blocks
[block_idx
].instructions
[idx
];
701 aco_ptr
<Instruction
> instr_before(nullptr);
702 return get_demand_before(demand
, instr
, instr_before
);
704 return ctx
.register_demand
[block_idx
][idx
- 1];
708 void add_coupling_code(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
710 /* no coupling code necessary */
711 if (block
->linear_preds
.size() == 0)
714 std::vector
<aco_ptr
<Instruction
>> instructions
;
715 /* branch block: TODO take other branch into consideration */
716 if (block
->linear_preds
.size() == 1 && !(block
->kind
& (block_kind_loop_exit
| block_kind_loop_header
))) {
717 assert(ctx
.processed
[block
->linear_preds
[0]]);
718 assert(ctx
.register_demand
[block_idx
].size() == block
->instructions
.size());
719 std::vector
<RegisterDemand
> reg_demand
;
720 unsigned insert_idx
= 0;
721 unsigned pred_idx
= block
->linear_preds
[0];
722 RegisterDemand demand_before
= get_demand_before(ctx
, block_idx
, 0);
724 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
725 if (!live
.first
.is_linear())
728 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
731 /* in register at end of predecessor */
732 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
733 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
734 if (it
!= ctx
.renames
[pred_idx
].end())
735 ctx
.renames
[block_idx
].insert(*it
);
739 /* variable is spilled at predecessor and live at current block: create reload instruction */
740 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
741 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
742 instructions
.emplace_back(std::move(reload
));
743 reg_demand
.push_back(demand_before
);
744 ctx
.renames
[block_idx
][live
.first
] = new_name
;
747 if (block
->logical_preds
.size() == 1) {
749 assert(insert_idx
< block
->instructions
.size());
750 instructions
.emplace_back(std::move(block
->instructions
[insert_idx
]));
751 reg_demand
.push_back(ctx
.register_demand
[block_idx
][insert_idx
]);
753 } while (instructions
.back()->opcode
!= aco_opcode::p_logical_start
);
755 unsigned pred_idx
= block
->logical_preds
[0];
756 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
757 if (live
.first
.is_linear())
760 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
763 /* in register at end of predecessor */
764 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
765 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
766 if (it
!= ctx
.renames
[pred_idx
].end())
767 ctx
.renames
[block_idx
].insert(*it
);
771 /* variable is spilled at predecessor and live at current block: create reload instruction */
772 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
773 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
774 instructions
.emplace_back(std::move(reload
));
775 reg_demand
.emplace_back(reg_demand
.back());
776 ctx
.renames
[block_idx
][live
.first
] = new_name
;
780 /* combine new reload instructions with original block */
781 if (!instructions
.empty()) {
782 reg_demand
.insert(reg_demand
.end(), std::next(ctx
.register_demand
[block
->index
].begin(), insert_idx
),
783 ctx
.register_demand
[block
->index
].end());
784 ctx
.register_demand
[block_idx
] = std::move(reg_demand
);
785 instructions
.insert(instructions
.end(),
786 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(std::next(block
->instructions
.begin(), insert_idx
)),
787 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
788 block
->instructions
= std::move(instructions
);
793 /* loop header and merge blocks: check if all (linear) predecessors have been processed */
794 for (ASSERTED
unsigned pred
: block
->linear_preds
)
795 assert(ctx
.processed
[pred
]);
797 /* iterate the phi nodes for which operands to spill at the predecessor */
798 for (aco_ptr
<Instruction
>& phi
: block
->instructions
) {
799 if (phi
->opcode
!= aco_opcode::p_phi
&&
800 phi
->opcode
!= aco_opcode::p_linear_phi
)
803 /* if the phi is not spilled, add to instructions */
804 if (ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end()) {
805 instructions
.emplace_back(std::move(phi
));
809 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
810 uint32_t def_spill_id
= ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()];
812 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
813 if (phi
->operands
[i
].isUndefined())
816 unsigned pred_idx
= preds
[i
];
817 assert(phi
->operands
[i
].isTemp() && phi
->operands
[i
].isKill());
818 Temp var
= phi
->operands
[i
].getTemp();
820 /* build interferences between the phi def and all spilled variables at the predecessor blocks */
821 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
822 if (var
== pair
.first
)
824 ctx
.add_interference(def_spill_id
, pair
.second
);
827 /* check if variable is already spilled at predecessor */
828 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(var
);
829 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
830 if (spilled
->second
!= def_spill_id
)
831 ctx
.add_affinity(def_spill_id
, spilled
->second
);
835 /* rename if necessary */
836 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
837 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
838 var
= rename_it
->second
;
839 ctx
.renames
[pred_idx
].erase(rename_it
);
842 uint32_t spill_id
= ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
843 ctx
.add_affinity(def_spill_id
, spill_id
);
844 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
845 spill
->operands
[0] = Operand(var
);
846 spill
->operands
[1] = Operand(spill_id
);
847 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
848 unsigned idx
= pred
.instructions
.size();
852 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
853 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
854 pred
.instructions
.insert(it
, std::move(spill
));
855 ctx
.spills_exit
[pred_idx
][phi
->operands
[i
].getTemp()] = spill_id
;
858 /* remove phi from instructions */
862 /* iterate all (other) spilled variables for which to spill at the predecessor */
863 // TODO: would be better to have them sorted: first vgprs and first with longest distance
864 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_entry
[block_idx
]) {
865 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
867 for (unsigned pred_idx
: preds
) {
868 /* variable is already spilled at predecessor */
869 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(pair
.first
);
870 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
871 if (spilled
->second
!= pair
.second
)
872 ctx
.add_affinity(pair
.second
, spilled
->second
);
876 /* variable is dead at predecessor, it must be from a phi: this works because of CSSA form */
877 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
880 /* add interferences between spilled variable and predecessors exit spills */
881 for (std::pair
<Temp
, uint32_t> exit_spill
: ctx
.spills_exit
[pred_idx
]) {
882 if (exit_spill
.first
== pair
.first
)
884 ctx
.add_interference(exit_spill
.second
, pair
.second
);
887 /* variable is in register at predecessor and has to be spilled */
888 /* rename if necessary */
889 Temp var
= pair
.first
;
890 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
891 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
892 var
= rename_it
->second
;
893 ctx
.renames
[pred_idx
].erase(rename_it
);
896 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
897 spill
->operands
[0] = Operand(var
);
898 spill
->operands
[1] = Operand(pair
.second
);
899 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
900 unsigned idx
= pred
.instructions
.size();
904 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
905 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
906 pred
.instructions
.insert(it
, std::move(spill
));
907 ctx
.spills_exit
[pred
.index
][pair
.first
] = pair
.second
;
911 /* iterate phis for which operands to reload */
912 for (aco_ptr
<Instruction
>& phi
: instructions
) {
913 assert(phi
->opcode
== aco_opcode::p_phi
|| phi
->opcode
== aco_opcode::p_linear_phi
);
914 assert(ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end());
916 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
917 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
918 if (!phi
->operands
[i
].isTemp())
920 unsigned pred_idx
= preds
[i
];
923 if (ctx
.spills_exit
[pred_idx
].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[pred_idx
].end()) {
924 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(phi
->operands
[i
].getTemp());
925 if (it
!= ctx
.renames
[pred_idx
].end())
926 phi
->operands
[i
].setTemp(it
->second
);
930 Temp tmp
= phi
->operands
[i
].getTemp();
932 /* reload phi operand at end of predecessor block */
933 Temp new_name
= {ctx
.program
->allocateId(), tmp
.regClass()};
934 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
935 unsigned idx
= pred
.instructions
.size();
939 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
940 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
942 aco_ptr
<Instruction
> reload
= do_reload(ctx
, tmp
, new_name
, ctx
.spills_exit
[pred_idx
][tmp
]);
943 pred
.instructions
.insert(it
, std::move(reload
));
945 ctx
.spills_exit
[pred_idx
].erase(tmp
);
946 ctx
.renames
[pred_idx
][tmp
] = new_name
;
947 phi
->operands
[i
].setTemp(new_name
);
951 /* iterate live variables for which to reload */
952 // TODO: reload at current block if variable is spilled on all predecessors
953 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
954 /* skip spilled variables */
955 if (ctx
.spills_entry
[block_idx
].find(pair
.first
) != ctx
.spills_entry
[block_idx
].end())
957 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
959 /* variable is dead at predecessor, it must be from a phi */
960 bool is_dead
= false;
961 for (unsigned pred_idx
: preds
) {
962 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
967 for (unsigned pred_idx
: preds
) {
968 /* the variable is not spilled at the predecessor */
969 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end())
972 /* variable is spilled at predecessor and has to be reloaded */
973 Temp new_name
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
974 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
975 unsigned idx
= pred
.instructions
.size();
979 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
980 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
982 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.first
, new_name
, ctx
.spills_exit
[pred
.index
][pair
.first
]);
983 pred
.instructions
.insert(it
, std::move(reload
));
985 ctx
.spills_exit
[pred
.index
].erase(pair
.first
);
986 ctx
.renames
[pred
.index
][pair
.first
] = new_name
;
989 /* check if we have to create a new phi for this variable */
990 Temp rename
= Temp();
992 for (unsigned pred_idx
: preds
) {
993 if (ctx
.renames
[pred_idx
].find(pair
.first
) == ctx
.renames
[pred_idx
].end()) {
994 if (rename
== Temp())
997 is_same
= rename
== pair
.first
;
999 if (rename
== Temp())
1000 rename
= ctx
.renames
[pred_idx
][pair
.first
];
1002 is_same
= rename
== ctx
.renames
[pred_idx
][pair
.first
];
1010 /* the variable was renamed differently in the predecessors: we have to create a phi */
1011 aco_opcode opcode
= pair
.first
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
1012 aco_ptr
<Pseudo_instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
1013 rename
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
1014 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
1016 if (ctx
.renames
[preds
[i
]].find(pair
.first
) != ctx
.renames
[preds
[i
]].end())
1017 tmp
= ctx
.renames
[preds
[i
]][pair
.first
];
1018 else if (preds
[i
] >= block_idx
)
1022 phi
->operands
[i
] = Operand(tmp
);
1024 phi
->definitions
[0] = Definition(rename
);
1025 instructions
.emplace_back(std::move(phi
));
1028 /* the variable was renamed: add new name to renames */
1029 if (!(rename
== Temp() || rename
== pair
.first
))
1030 ctx
.renames
[block_idx
][pair
.first
] = rename
;
1033 /* combine phis with instructions */
1035 while (!block
->instructions
[idx
]) {
1039 if (!ctx
.processed
[block_idx
]) {
1040 assert(!(block
->kind
& block_kind_loop_header
));
1041 RegisterDemand demand_before
= get_demand_before(ctx
, block_idx
, idx
);
1042 ctx
.register_demand
[block
->index
].erase(ctx
.register_demand
[block
->index
].begin(), ctx
.register_demand
[block
->index
].begin() + idx
);
1043 ctx
.register_demand
[block
->index
].insert(ctx
.register_demand
[block
->index
].begin(), instructions
.size(), demand_before
);
1046 std::vector
<aco_ptr
<Instruction
>>::iterator start
= std::next(block
->instructions
.begin(), idx
);
1047 instructions
.insert(instructions
.end(), std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(start
),
1048 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
1049 block
->instructions
= std::move(instructions
);
1052 void process_block(spill_ctx
& ctx
, unsigned block_idx
, Block
* block
,
1053 std::map
<Temp
, uint32_t> ¤t_spills
, RegisterDemand spilled_registers
)
1055 assert(!ctx
.processed
[block_idx
]);
1057 std::vector
<std::map
<Temp
, uint32_t>> local_next_use_distance
;
1058 std::vector
<aco_ptr
<Instruction
>> instructions
;
1061 /* phis are handled separetely */
1062 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
||
1063 block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
) {
1064 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1065 for (const Operand
& op
: instr
->operands
) {
1066 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1067 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1068 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1070 instructions
.emplace_back(std::move(instr
));
1074 if (block
->register_demand
.exceeds(ctx
.target_pressure
))
1075 local_next_use_distance
= local_next_uses(ctx
, block
);
1077 while (idx
< block
->instructions
.size()) {
1078 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1080 std::map
<Temp
, std::pair
<Temp
, uint32_t>> reloads
;
1081 std::map
<Temp
, uint32_t> spills
;
1082 /* rename and reload operands */
1083 for (Operand
& op
: instr
->operands
) {
1086 if (current_spills
.find(op
.getTemp()) == current_spills
.end()) {
1087 /* the Operand is in register: check if it was renamed */
1088 if (ctx
.renames
[block_idx
].find(op
.getTemp()) != ctx
.renames
[block_idx
].end())
1089 op
.setTemp(ctx
.renames
[block_idx
][op
.getTemp()]);
1090 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1091 if (ctx
.remat
.count(op
.getTemp()))
1092 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1095 /* the Operand is spilled: add it to reloads */
1096 Temp new_tmp
= {ctx
.program
->allocateId(), op
.regClass()};
1097 ctx
.renames
[block_idx
][op
.getTemp()] = new_tmp
;
1098 reloads
[new_tmp
] = std::make_pair(op
.getTemp(), current_spills
[op
.getTemp()]);
1099 current_spills
.erase(op
.getTemp());
1100 op
.setTemp(new_tmp
);
1101 spilled_registers
-= new_tmp
;
1104 /* check if register demand is low enough before and after the current instruction */
1105 if (block
->register_demand
.exceeds(ctx
.target_pressure
)) {
1107 RegisterDemand new_demand
= ctx
.register_demand
[block_idx
][idx
];
1108 new_demand
.update(get_demand_before(ctx
, block_idx
, idx
));
1110 assert(!local_next_use_distance
.empty());
1112 /* if reg pressure is too high, spill variable with furthest next use */
1113 while (RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
)) {
1114 unsigned distance
= 0;
1116 bool do_rematerialize
= false;
1117 if (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
1118 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1119 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1120 if (pair
.first
.type() == RegType::vgpr
&&
1121 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1122 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1123 current_spills
.find(pair
.first
) == current_spills
.end() &&
1124 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1125 to_spill
= pair
.first
;
1126 distance
= pair
.second
;
1127 do_rematerialize
= can_rematerialize
;
1131 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1132 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1133 if (pair
.first
.type() == RegType::sgpr
&&
1134 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1135 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1136 current_spills
.find(pair
.first
) == current_spills
.end() &&
1137 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1138 to_spill
= pair
.first
;
1139 distance
= pair
.second
;
1140 do_rematerialize
= can_rematerialize
;
1145 assert(distance
!= 0 && distance
> idx
);
1146 uint32_t spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
1148 /* add interferences with currently spilled variables */
1149 for (std::pair
<Temp
, uint32_t> pair
: current_spills
)
1150 ctx
.add_interference(spill_id
, pair
.second
);
1151 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
)
1152 ctx
.add_interference(spill_id
, pair
.second
.second
);
1154 current_spills
[to_spill
] = spill_id
;
1155 spilled_registers
+= to_spill
;
1157 /* rename if necessary */
1158 if (ctx
.renames
[block_idx
].find(to_spill
) != ctx
.renames
[block_idx
].end()) {
1159 to_spill
= ctx
.renames
[block_idx
][to_spill
];
1162 /* add spill to new instructions */
1163 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
1164 spill
->operands
[0] = Operand(to_spill
);
1165 spill
->operands
[1] = Operand(spill_id
);
1166 instructions
.emplace_back(std::move(spill
));
1170 /* add reloads and instruction to new instructions */
1171 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1172 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.second
.first
, pair
.first
, pair
.second
.second
);
1173 instructions
.emplace_back(std::move(reload
));
1175 instructions
.emplace_back(std::move(instr
));
1179 block
->instructions
= std::move(instructions
);
1180 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1183 void spill_block(spill_ctx
& ctx
, unsigned block_idx
)
1185 Block
* block
= &ctx
.program
->blocks
[block_idx
];
1187 /* determine set of variables which are spilled at the beginning of the block */
1188 RegisterDemand spilled_registers
= init_live_in_vars(ctx
, block
, block_idx
);
1190 /* add interferences for spilled variables */
1191 for (auto it
= ctx
.spills_entry
[block_idx
].begin(); it
!= ctx
.spills_entry
[block_idx
].end(); ++it
) {
1192 for (auto it2
= std::next(it
); it2
!= ctx
.spills_entry
[block_idx
].end(); ++it2
)
1193 ctx
.add_interference(it
->second
, it2
->second
);
1196 bool is_loop_header
= block
->loop_nest_depth
&& ctx
.loop_header
.top()->index
== block_idx
;
1197 if (!is_loop_header
) {
1198 /* add spill/reload code on incoming control flow edges */
1199 add_coupling_code(ctx
, block
, block_idx
);
1202 std::map
<Temp
, uint32_t> current_spills
= ctx
.spills_entry
[block_idx
];
1204 /* check conditions to process this block */
1205 bool process
= RegisterDemand(block
->register_demand
- spilled_registers
).exceeds(ctx
.target_pressure
) ||
1206 !ctx
.renames
[block_idx
].empty() ||
1207 ctx
.remat_used
.size();
1209 std::map
<Temp
, uint32_t>::iterator it
= current_spills
.begin();
1210 while (!process
&& it
!= current_spills
.end()) {
1211 if (ctx
.next_use_distances_start
[block_idx
][it
->first
].first
== block_idx
)
1217 process_block(ctx
, block_idx
, block
, current_spills
, spilled_registers
);
1219 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1221 ctx
.processed
[block_idx
] = true;
1223 /* check if the next block leaves the current loop */
1224 if (block
->loop_nest_depth
== 0 || ctx
.program
->blocks
[block_idx
+ 1].loop_nest_depth
>= block
->loop_nest_depth
)
1227 Block
* loop_header
= ctx
.loop_header
.top();
1229 /* preserve original renames at end of loop header block */
1230 std::map
<Temp
, Temp
> renames
= std::move(ctx
.renames
[loop_header
->index
]);
1232 /* add coupling code to all loop header predecessors */
1233 add_coupling_code(ctx
, loop_header
, loop_header
->index
);
1235 /* update remat_used for phis added in add_coupling_code() */
1236 for (aco_ptr
<Instruction
>& instr
: loop_header
->instructions
) {
1239 for (const Operand
& op
: instr
->operands
) {
1240 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1241 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1245 /* propagate new renames through loop: i.e. repair the SSA */
1246 renames
.swap(ctx
.renames
[loop_header
->index
]);
1247 for (std::pair
<Temp
, Temp
> rename
: renames
) {
1248 for (unsigned idx
= loop_header
->index
; idx
<= block_idx
; idx
++) {
1249 Block
& current
= ctx
.program
->blocks
[idx
];
1250 std::vector
<aco_ptr
<Instruction
>>::iterator instr_it
= current
.instructions
.begin();
1252 /* first rename phis */
1253 while (instr_it
!= current
.instructions
.end()) {
1254 aco_ptr
<Instruction
>& phi
= *instr_it
;
1255 if (phi
->opcode
!= aco_opcode::p_phi
&& phi
->opcode
!= aco_opcode::p_linear_phi
)
1257 /* no need to rename the loop header phis once again. this happened in add_coupling_code() */
1258 if (idx
== loop_header
->index
) {
1263 for (Operand
& op
: phi
->operands
) {
1266 if (op
.getTemp() == rename
.first
)
1267 op
.setTemp(rename
.second
);
1272 std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= ctx
.next_use_distances_start
[idx
].find(rename
.first
);
1274 /* variable is not live at beginning of this block */
1275 if (it
== ctx
.next_use_distances_start
[idx
].end())
1278 /* if the variable is live at the block's exit, add rename */
1279 if (ctx
.next_use_distances_end
[idx
].find(rename
.first
) != ctx
.next_use_distances_end
[idx
].end())
1280 ctx
.renames
[idx
].insert(rename
);
1282 /* rename all uses in this block */
1283 bool renamed
= false;
1284 while (!renamed
&& instr_it
!= current
.instructions
.end()) {
1285 aco_ptr
<Instruction
>& instr
= *instr_it
;
1286 for (Operand
& op
: instr
->operands
) {
1289 if (op
.getTemp() == rename
.first
) {
1290 op
.setTemp(rename
.second
);
1291 /* we can stop with this block as soon as the variable is spilled */
1292 if (instr
->opcode
== aco_opcode::p_spill
)
1301 /* remove loop header info from stack */
1302 ctx
.loop_header
.pop();
1305 Temp
load_scratch_resource(spill_ctx
& ctx
, Temp
& scratch_offset
,
1306 std::vector
<aco_ptr
<Instruction
>>& instructions
,
1307 unsigned offset
, bool is_top_level
)
1309 Builder
bld(ctx
.program
);
1311 bld
.reset(&instructions
);
1313 /* find p_logical_end */
1314 unsigned idx
= instructions
.size() - 1;
1315 while (instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
)
1317 bld
.reset(&instructions
, std::next(instructions
.begin(), idx
));
1320 Temp private_segment_buffer
= ctx
.program
->private_segment_buffer
;
1321 if (ctx
.program
->stage
!= compute_cs
)
1322 private_segment_buffer
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, Operand(0u));
1325 scratch_offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), scratch_offset
, Operand(offset
));
1327 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
1328 S_008F0C_INDEX_STRIDE(ctx
.program
->wave_size
== 64 ? 3 : 2);
1330 if (ctx
.program
->chip_class
>= GFX10
) {
1331 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1332 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
1333 S_008F0C_RESOURCE_LEVEL(1);
1334 } else if (ctx
.program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
1335 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1336 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1338 /* older generations need element size = 4 bytes. element size removed in GFX9 */
1339 if (ctx
.program
->chip_class
<= GFX8
)
1340 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
1342 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
1343 private_segment_buffer
, Operand(-1u),
1344 Operand(rsrc_conf
));
1347 void add_interferences(spill_ctx
& ctx
, std::vector
<bool>& is_assigned
,
1348 std::vector
<uint32_t>& slots
, std::vector
<bool>& slots_used
,
1351 for (unsigned other
: ctx
.interferences
[id
].second
) {
1352 if (!is_assigned
[other
])
1355 RegClass other_rc
= ctx
.interferences
[other
].first
;
1356 unsigned slot
= slots
[other
];
1357 std::fill(slots_used
.begin() + slot
, slots_used
.begin() + slot
+ other_rc
.size(), true);
1361 unsigned find_available_slot(std::vector
<bool>& used
, unsigned wave_size
,
1362 unsigned size
, bool is_sgpr
, unsigned *num_slots
)
1364 unsigned wave_size_minus_one
= wave_size
- 1;
1368 bool available
= true;
1369 for (unsigned i
= 0; i
< size
; i
++) {
1370 if (slot
+ i
< used
.size() && used
[slot
+ i
]) {
1380 if (is_sgpr
&& ((slot
& wave_size_minus_one
) > wave_size
- size
)) {
1381 slot
= align(slot
, wave_size
);
1385 std::fill(used
.begin(), used
.end(), false);
1387 if (slot
+ size
> used
.size())
1388 used
.resize(slot
+ size
);
1394 void assign_spill_slots_helper(spill_ctx
& ctx
, RegType type
,
1395 std::vector
<bool>& is_assigned
,
1396 std::vector
<uint32_t>& slots
,
1397 unsigned *num_slots
)
1399 std::vector
<bool> slots_used(*num_slots
);
1401 /* assign slots for ids with affinities first */
1402 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1403 if (ctx
.interferences
[vec
[0]].first
.type() != type
)
1406 for (unsigned id
: vec
) {
1407 if (!ctx
.is_reloaded
[id
])
1410 add_interferences(ctx
, is_assigned
, slots
, slots_used
, id
);
1413 unsigned slot
= find_available_slot(slots_used
, ctx
.wave_size
,
1414 ctx
.interferences
[vec
[0]].first
.size(),
1415 type
== RegType::sgpr
, num_slots
);
1417 for (unsigned id
: vec
) {
1418 assert(!is_assigned
[id
]);
1420 if (ctx
.is_reloaded
[id
]) {
1422 is_assigned
[id
] = true;
1427 /* assign slots for ids without affinities */
1428 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1429 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
] || ctx
.interferences
[id
].first
.type() != type
)
1432 add_interferences(ctx
, is_assigned
, slots
, slots_used
, id
);
1434 unsigned slot
= find_available_slot(slots_used
, ctx
.wave_size
,
1435 ctx
.interferences
[id
].first
.size(),
1436 type
== RegType::sgpr
, num_slots
);
1439 is_assigned
[id
] = true;
1442 *num_slots
= slots_used
.size();
1445 void assign_spill_slots(spill_ctx
& ctx
, unsigned spills_to_vgpr
) {
1446 std::vector
<uint32_t> slots(ctx
.interferences
.size());
1447 std::vector
<bool> is_assigned(ctx
.interferences
.size());
1449 /* first, handle affinities: just merge all interferences into both spill ids */
1450 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1451 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1452 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1453 assert(vec
[i
] != vec
[j
]);
1454 bool reloaded
= ctx
.is_reloaded
[vec
[i
]] || ctx
.is_reloaded
[vec
[j
]];
1455 ctx
.is_reloaded
[vec
[i
]] = reloaded
;
1456 ctx
.is_reloaded
[vec
[j
]] = reloaded
;
1460 for (ASSERTED
uint32_t i
= 0; i
< ctx
.interferences
.size(); i
++)
1461 for (ASSERTED
uint32_t id
: ctx
.interferences
[i
].second
)
1464 /* for each spill slot, assign as many spill ids as possible */
1465 unsigned sgpr_spill_slots
= 0, vgpr_spill_slots
= 0;
1466 assign_spill_slots_helper(ctx
, RegType::sgpr
, is_assigned
, slots
, &sgpr_spill_slots
);
1467 assign_spill_slots_helper(ctx
, RegType::vgpr
, is_assigned
, slots
, &vgpr_spill_slots
);
1469 for (unsigned id
= 0; id
< is_assigned
.size(); id
++)
1470 assert(is_assigned
[id
] || !ctx
.is_reloaded
[id
]);
1472 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1473 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1474 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1475 assert(is_assigned
[vec
[i
]] == is_assigned
[vec
[j
]]);
1476 if (!is_assigned
[vec
[i
]])
1478 assert(ctx
.is_reloaded
[vec
[i
]] == ctx
.is_reloaded
[vec
[j
]]);
1479 assert(ctx
.interferences
[vec
[i
]].first
.type() == ctx
.interferences
[vec
[j
]].first
.type());
1480 assert(slots
[vec
[i
]] == slots
[vec
[j
]]);
1485 /* hope, we didn't mess up */
1486 std::vector
<Temp
> vgpr_spill_temps((sgpr_spill_slots
+ ctx
.wave_size
- 1) / ctx
.wave_size
);
1487 assert(vgpr_spill_temps
.size() <= spills_to_vgpr
);
1489 /* replace pseudo instructions with actual hardware instructions */
1490 Temp scratch_offset
= ctx
.program
->scratch_offset
, scratch_rsrc
= Temp();
1491 unsigned last_top_level_block_idx
= 0;
1492 std::vector
<bool> reload_in_loop(vgpr_spill_temps
.size());
1493 for (Block
& block
: ctx
.program
->blocks
) {
1495 /* after loops, we insert a user if there was a reload inside the loop */
1496 if (block
.loop_nest_depth
== 0) {
1498 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1499 if (reload_in_loop
[i
])
1503 if (end_vgprs
> 0) {
1504 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, end_vgprs
, 0)};
1506 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1507 if (reload_in_loop
[i
])
1508 destr
->operands
[k
++] = Operand(vgpr_spill_temps
[i
]);
1509 reload_in_loop
[i
] = false;
1511 /* find insertion point */
1512 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1513 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1515 block
.instructions
.insert(it
, std::move(destr
));
1519 if (block
.kind
& block_kind_top_level
&& !block
.linear_preds
.empty()) {
1520 last_top_level_block_idx
= block
.index
;
1522 /* check if any spilled variables use a created linear vgpr, otherwise destroy them */
1523 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1524 if (vgpr_spill_temps
[i
] == Temp())
1527 bool can_destroy
= true;
1528 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[block
.linear_preds
[0]]) {
1530 if (ctx
.interferences
[pair
.second
].first
.type() == RegType::sgpr
&&
1531 slots
[pair
.second
] / ctx
.wave_size
== i
) {
1532 can_destroy
= false;
1537 vgpr_spill_temps
[i
] = Temp();
1541 std::vector
<aco_ptr
<Instruction
>>::iterator it
;
1542 std::vector
<aco_ptr
<Instruction
>> instructions
;
1543 instructions
.reserve(block
.instructions
.size());
1544 Builder
bld(ctx
.program
, &instructions
);
1545 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1547 if ((*it
)->opcode
== aco_opcode::p_spill
) {
1548 uint32_t spill_id
= (*it
)->operands
[1].constantValue();
1550 if (!ctx
.is_reloaded
[spill_id
]) {
1551 /* never reloaded, so don't spill */
1552 } else if (!is_assigned
[spill_id
]) {
1553 unreachable("No spill slot assigned for spill id");
1554 } else if (ctx
.interferences
[spill_id
].first
.type() == RegType::vgpr
) {
1556 ctx
.program
->config
->spilled_vgprs
+= (*it
)->operands
[0].size();
1557 uint32_t spill_slot
= slots
[spill_id
];
1558 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1559 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1561 /* check if the scratch resource descriptor already exists */
1562 if (scratch_rsrc
== Temp()) {
1563 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1564 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1565 last_top_level_block_idx
== block
.index
?
1566 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1568 last_top_level_block_idx
== block
.index
);
1571 unsigned offset
= base_offset
+ spill_slot
* 4;
1572 aco_opcode opcode
= aco_opcode::buffer_store_dword
;
1573 assert((*it
)->operands
[0].isTemp());
1574 Temp temp
= (*it
)->operands
[0].getTemp();
1575 assert(temp
.type() == RegType::vgpr
&& !temp
.is_linear());
1576 if (temp
.size() > 1) {
1577 Instruction
* split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, temp
.size())};
1578 split
->operands
[0] = Operand(temp
);
1579 for (unsigned i
= 0; i
< temp
.size(); i
++)
1580 split
->definitions
[i
] = bld
.def(v1
);
1582 for (unsigned i
= 0; i
< temp
.size(); i
++) {
1583 Instruction
*instr
= bld
.mubuf(opcode
, scratch_rsrc
, Operand(v1
), scratch_offset
, split
->definitions
[i
].getTemp(), offset
+ i
* 4, false, true);
1584 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_vgpr_spill
, semantic_private
);
1587 Instruction
*instr
= bld
.mubuf(opcode
, scratch_rsrc
, Operand(v1
), scratch_offset
, temp
, offset
, false, true);
1588 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_vgpr_spill
, semantic_private
);
1591 ctx
.program
->config
->spilled_sgprs
+= (*it
)->operands
[0].size();
1593 uint32_t spill_slot
= slots
[spill_id
];
1595 /* check if the linear vgpr already exists */
1596 if (vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] == Temp()) {
1597 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1598 vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] = linear_vgpr
;
1599 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1600 create
->definitions
[0] = Definition(linear_vgpr
);
1601 /* find the right place to insert this definition */
1602 if (last_top_level_block_idx
== block
.index
) {
1603 /* insert right before the current instruction */
1604 instructions
.emplace_back(std::move(create
));
1606 assert(last_top_level_block_idx
< block
.index
);
1607 /* insert before the branch at last top level block */
1608 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1609 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1613 /* spill sgpr: just add the vgpr temp to operands */
1614 Pseudo_instruction
* spill
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 3, 0);
1615 spill
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
]);
1616 spill
->operands
[1] = Operand(spill_slot
% ctx
.wave_size
);
1617 spill
->operands
[2] = (*it
)->operands
[0];
1618 instructions
.emplace_back(aco_ptr
<Instruction
>(spill
));
1621 } else if ((*it
)->opcode
== aco_opcode::p_reload
) {
1622 uint32_t spill_id
= (*it
)->operands
[0].constantValue();
1623 assert(ctx
.is_reloaded
[spill_id
]);
1625 if (!is_assigned
[spill_id
]) {
1626 unreachable("No spill slot assigned for spill id");
1627 } else if (ctx
.interferences
[spill_id
].first
.type() == RegType::vgpr
) {
1629 uint32_t spill_slot
= slots
[spill_id
];
1630 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1631 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1633 /* check if the scratch resource descriptor already exists */
1634 if (scratch_rsrc
== Temp()) {
1635 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1636 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1637 last_top_level_block_idx
== block
.index
?
1638 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1640 last_top_level_block_idx
== block
.index
);
1643 unsigned offset
= base_offset
+ spill_slot
* 4;
1644 aco_opcode opcode
= aco_opcode::buffer_load_dword
;
1645 Definition def
= (*it
)->definitions
[0];
1646 if (def
.size() > 1) {
1647 Instruction
* vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, def
.size(), 1)};
1648 vec
->definitions
[0] = def
;
1649 for (unsigned i
= 0; i
< def
.size(); i
++) {
1650 Temp tmp
= bld
.tmp(v1
);
1651 vec
->operands
[i
] = Operand(tmp
);
1652 Instruction
*instr
= bld
.mubuf(opcode
, Definition(tmp
), scratch_rsrc
, Operand(v1
), scratch_offset
, offset
+ i
* 4, false, true);
1653 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_vgpr_spill
, semantic_private
);
1657 Instruction
*instr
= bld
.mubuf(opcode
, def
, scratch_rsrc
, Operand(v1
), scratch_offset
, offset
, false, true);
1658 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_vgpr_spill
, semantic_private
);
1661 uint32_t spill_slot
= slots
[spill_id
];
1662 reload_in_loop
[spill_slot
/ ctx
.wave_size
] = block
.loop_nest_depth
> 0;
1664 /* check if the linear vgpr already exists */
1665 if (vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] == Temp()) {
1666 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1667 vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] = linear_vgpr
;
1668 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1669 create
->definitions
[0] = Definition(linear_vgpr
);
1670 /* find the right place to insert this definition */
1671 if (last_top_level_block_idx
== block
.index
) {
1672 /* insert right before the current instruction */
1673 instructions
.emplace_back(std::move(create
));
1675 assert(last_top_level_block_idx
< block
.index
);
1676 /* insert before the branch at last top level block */
1677 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1678 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1682 /* reload sgpr: just add the vgpr temp to operands */
1683 Pseudo_instruction
* reload
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 2, 1);
1684 reload
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
]);
1685 reload
->operands
[1] = Operand(spill_slot
% ctx
.wave_size
);
1686 reload
->definitions
[0] = (*it
)->definitions
[0];
1687 instructions
.emplace_back(aco_ptr
<Instruction
>(reload
));
1689 } else if (!ctx
.remat_used
.count(it
->get()) || ctx
.remat_used
[it
->get()]) {
1690 instructions
.emplace_back(std::move(*it
));
1694 block
.instructions
= std::move(instructions
);
1697 /* update required scratch memory */
1698 ctx
.program
->config
->scratch_bytes_per_wave
+= align(vgpr_spill_slots
* 4 * ctx
.program
->wave_size
, 1024);
1700 /* SSA elimination inserts copies for logical phis right before p_logical_end
1701 * So if a linear vgpr is used between that p_logical_end and the branch,
1702 * we need to ensure logical phis don't choose a definition which aliases
1704 * TODO: Moving the spills and reloads to before p_logical_end might produce
1705 * slightly better code. */
1706 for (Block
& block
: ctx
.program
->blocks
) {
1707 /* loops exits are already handled */
1708 if (block
.logical_preds
.size() <= 1)
1711 bool has_logical_phis
= false;
1712 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
1713 if (instr
->opcode
== aco_opcode::p_phi
) {
1714 has_logical_phis
= true;
1716 } else if (instr
->opcode
!= aco_opcode::p_linear_phi
) {
1720 if (!has_logical_phis
)
1723 std::set
<Temp
> vgprs
;
1724 for (unsigned pred_idx
: block
.logical_preds
) {
1725 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
1726 for (int i
= pred
.instructions
.size() - 1; i
>= 0; i
--) {
1727 aco_ptr
<Instruction
>& pred_instr
= pred
.instructions
[i
];
1728 if (pred_instr
->opcode
== aco_opcode::p_logical_end
) {
1730 } else if (pred_instr
->opcode
== aco_opcode::p_spill
||
1731 pred_instr
->opcode
== aco_opcode::p_reload
) {
1732 vgprs
.insert(pred_instr
->operands
[0].getTemp());
1739 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, vgprs
.size(), 0)};
1741 for (Temp tmp
: vgprs
) {
1742 destr
->operands
[k
++] = Operand(tmp
);
1744 /* find insertion point */
1745 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1746 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1748 block
.instructions
.insert(it
, std::move(destr
));
1752 } /* end namespace */
1755 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
)
1757 program
->config
->spilled_vgprs
= 0;
1758 program
->config
->spilled_sgprs
= 0;
1760 /* no spilling when register pressure is low enough */
1761 if (program
->num_waves
> 0)
1764 /* lower to CSSA before spilling to ensure correctness w.r.t. phis */
1765 lower_to_cssa(program
, live_vars
, options
);
1767 /* calculate target register demand */
1768 RegisterDemand register_target
= program
->max_reg_demand
;
1769 if (register_target
.sgpr
> program
->sgpr_limit
)
1770 register_target
.vgpr
+= (register_target
.sgpr
- program
->sgpr_limit
+ program
->wave_size
- 1 + 32) / program
->wave_size
;
1771 register_target
.sgpr
= program
->sgpr_limit
;
1773 if (register_target
.vgpr
> program
->vgpr_limit
)
1774 register_target
.sgpr
= program
->sgpr_limit
- 5;
1775 int spills_to_vgpr
= (program
->max_reg_demand
.sgpr
- register_target
.sgpr
+ program
->wave_size
- 1 + 32) / program
->wave_size
;
1776 register_target
.vgpr
= program
->vgpr_limit
- spills_to_vgpr
;
1778 /* initialize ctx */
1779 spill_ctx
ctx(register_target
, program
, live_vars
.register_demand
);
1780 compute_global_next_uses(ctx
);
1781 get_rematerialize_info(ctx
);
1783 /* create spills and reloads */
1784 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++)
1785 spill_block(ctx
, i
);
1787 /* assign spill slots and DCE rematerialized code */
1788 assign_spill_slots(ctx
, spills_to_vgpr
);
1790 /* update live variable information */
1791 live_vars
= live_var_analysis(program
, options
);
1793 assert(program
->num_waves
> 0);