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27 #include "aco_builder.h"
34 * Implements the spilling algorithm on SSA-form from
35 * "Register Spilling and Live-Range Splitting for SSA-Form Programs"
36 * by Matthias Braun and Sebastian Hack.
48 RegisterDemand target_pressure
;
50 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
51 std::vector
<std::map
<Temp
, Temp
>> renames
;
52 std::vector
<std::map
<Temp
, uint32_t>> spills_entry
;
53 std::vector
<std::map
<Temp
, uint32_t>> spills_exit
;
54 std::vector
<bool> processed
;
55 std::stack
<Block
*> loop_header
;
56 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_start
;
57 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_end
;
58 std::vector
<std::pair
<RegClass
, std::set
<uint32_t>>> interferences
;
59 std::vector
<std::vector
<uint32_t>> affinities
;
60 std::vector
<bool> is_reloaded
;
61 std::map
<Temp
, remat_info
> remat
;
62 std::map
<Instruction
*, bool> remat_used
;
65 spill_ctx(const RegisterDemand target_pressure
, Program
* program
,
66 std::vector
<std::vector
<RegisterDemand
>> register_demand
)
67 : target_pressure(target_pressure
), program(program
),
68 register_demand(register_demand
), renames(program
->blocks
.size()),
69 spills_entry(program
->blocks
.size()), spills_exit(program
->blocks
.size()),
70 processed(program
->blocks
.size(), false), wave_size(program
->wave_size
) {}
72 void add_affinity(uint32_t first
, uint32_t second
)
74 unsigned found_first
= affinities
.size();
75 unsigned found_second
= affinities
.size();
76 for (unsigned i
= 0; i
< affinities
.size(); i
++) {
77 std::vector
<uint32_t>& vec
= affinities
[i
];
78 for (uint32_t entry
: vec
) {
81 else if (entry
== second
)
85 if (found_first
== affinities
.size() && found_second
== affinities
.size()) {
86 affinities
.emplace_back(std::vector
<uint32_t>({first
, second
}));
87 } else if (found_first
< affinities
.size() && found_second
== affinities
.size()) {
88 affinities
[found_first
].push_back(second
);
89 } else if (found_second
< affinities
.size() && found_first
== affinities
.size()) {
90 affinities
[found_second
].push_back(first
);
91 } else if (found_first
!= found_second
) {
92 /* merge second into first */
93 affinities
[found_first
].insert(affinities
[found_first
].end(), affinities
[found_second
].begin(), affinities
[found_second
].end());
94 affinities
.erase(std::next(affinities
.begin(), found_second
));
96 assert(found_first
== found_second
);
100 uint32_t allocate_spill_id(RegClass rc
)
102 interferences
.emplace_back(rc
, std::set
<uint32_t>());
103 is_reloaded
.push_back(false);
104 return next_spill_id
++;
107 uint32_t next_spill_id
= 0;
110 int32_t get_dominator(int idx_a
, int idx_b
, Program
* program
, bool is_linear
)
118 while (idx_a
!= idx_b
) {
120 idx_a
= program
->blocks
[idx_a
].linear_idom
;
122 idx_b
= program
->blocks
[idx_b
].linear_idom
;
125 while (idx_a
!= idx_b
) {
127 idx_a
= program
->blocks
[idx_a
].logical_idom
;
129 idx_b
= program
->blocks
[idx_b
].logical_idom
;
136 void next_uses_per_block(spill_ctx
& ctx
, unsigned block_idx
, std::set
<uint32_t>& worklist
)
138 Block
* block
= &ctx
.program
->blocks
[block_idx
];
139 std::map
<Temp
, std::pair
<uint32_t, uint32_t>> next_uses
= ctx
.next_use_distances_end
[block_idx
];
141 /* to compute the next use distance at the beginning of the block, we have to add the block's size */
142 for (std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= next_uses
.begin(); it
!= next_uses
.end(); ++it
)
143 it
->second
.second
= it
->second
.second
+ block
->instructions
.size();
145 int idx
= block
->instructions
.size() - 1;
147 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
149 if (instr
->opcode
== aco_opcode::p_linear_phi
||
150 instr
->opcode
== aco_opcode::p_phi
)
153 for (const Definition
& def
: instr
->definitions
) {
155 next_uses
.erase(def
.getTemp());
158 for (const Operand
& op
: instr
->operands
) {
160 if (op
.isFixed() && op
.physReg() == exec
)
162 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
165 next_uses
[op
.getTemp()] = {block_idx
, idx
};
170 assert(block_idx
!= 0 || next_uses
.empty());
171 ctx
.next_use_distances_start
[block_idx
] = next_uses
;
173 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
174 assert(instr
->opcode
== aco_opcode::p_linear_phi
|| instr
->opcode
== aco_opcode::p_phi
);
176 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
177 unsigned pred_idx
= instr
->opcode
== aco_opcode::p_phi
?
178 block
->logical_preds
[i
] :
179 block
->linear_preds
[i
];
180 if (instr
->operands
[i
].isTemp()) {
181 if (instr
->operands
[i
].getTemp() == ctx
.program
->blocks
[pred_idx
].live_out_exec
)
183 if (ctx
.next_use_distances_end
[pred_idx
].find(instr
->operands
[i
].getTemp()) == ctx
.next_use_distances_end
[pred_idx
].end() ||
184 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] != std::pair
<uint32_t, uint32_t>{block_idx
, 0})
185 worklist
.insert(pred_idx
);
186 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] = {block_idx
, 0};
189 next_uses
.erase(instr
->definitions
[0].getTemp());
193 /* all remaining live vars must be live-out at the predecessors */
194 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: next_uses
) {
195 Temp temp
= pair
.first
;
196 uint32_t distance
= pair
.second
.second
;
197 uint32_t dom
= pair
.second
.first
;
198 std::vector
<unsigned>& preds
= temp
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
199 for (unsigned pred_idx
: preds
) {
200 if (temp
== ctx
.program
->blocks
[pred_idx
].live_out_exec
)
202 if (ctx
.program
->blocks
[pred_idx
].loop_nest_depth
> block
->loop_nest_depth
)
204 if (ctx
.next_use_distances_end
[pred_idx
].find(temp
) != ctx
.next_use_distances_end
[pred_idx
].end()) {
205 dom
= get_dominator(dom
, ctx
.next_use_distances_end
[pred_idx
][temp
].first
, ctx
.program
, temp
.is_linear());
206 distance
= std::min(ctx
.next_use_distances_end
[pred_idx
][temp
].second
, distance
);
208 if (ctx
.next_use_distances_end
[pred_idx
][temp
] != std::pair
<uint32_t, uint32_t>{dom
, distance
})
209 worklist
.insert(pred_idx
);
210 ctx
.next_use_distances_end
[pred_idx
][temp
] = {dom
, distance
};
216 void compute_global_next_uses(spill_ctx
& ctx
, std::vector
<std::set
<Temp
>>& live_out
)
218 ctx
.next_use_distances_start
.resize(ctx
.program
->blocks
.size());
219 ctx
.next_use_distances_end
.resize(ctx
.program
->blocks
.size());
220 std::set
<uint32_t> worklist
;
221 for (Block
& block
: ctx
.program
->blocks
)
222 worklist
.insert(block
.index
);
224 while (!worklist
.empty()) {
225 std::set
<unsigned>::reverse_iterator b_it
= worklist
.rbegin();
226 unsigned block_idx
= *b_it
;
227 worklist
.erase(block_idx
);
228 next_uses_per_block(ctx
, block_idx
, worklist
);
232 bool should_rematerialize(aco_ptr
<Instruction
>& instr
)
234 /* TODO: rematerialization is only supported for VOP1, SOP1 and PSEUDO */
235 if (instr
->format
!= Format::VOP1
&& instr
->format
!= Format::SOP1
&& instr
->format
!= Format::PSEUDO
&& instr
->format
!= Format::SOPK
)
237 /* TODO: pseudo-instruction rematerialization is only supported for p_create_vector */
238 if (instr
->format
== Format::PSEUDO
&& instr
->opcode
!= aco_opcode::p_create_vector
)
240 if (instr
->format
== Format::SOPK
&& instr
->opcode
!= aco_opcode::s_movk_i32
)
243 for (const Operand
& op
: instr
->operands
) {
244 /* TODO: rematerialization using temporaries isn't yet supported */
249 /* TODO: rematerialization with multiple definitions isn't yet supported */
250 if (instr
->definitions
.size() > 1)
256 aco_ptr
<Instruction
> do_reload(spill_ctx
& ctx
, Temp tmp
, Temp new_name
, uint32_t spill_id
)
258 std::map
<Temp
, remat_info
>::iterator remat
= ctx
.remat
.find(tmp
);
259 if (remat
!= ctx
.remat
.end()) {
260 Instruction
*instr
= remat
->second
.instr
;
261 assert((instr
->format
== Format::VOP1
|| instr
->format
== Format::SOP1
|| instr
->format
== Format::PSEUDO
|| instr
->format
== Format::SOPK
) && "unsupported");
262 assert((instr
->format
!= Format::PSEUDO
|| instr
->opcode
== aco_opcode::p_create_vector
) && "unsupported");
263 assert(instr
->definitions
.size() == 1 && "unsupported");
265 aco_ptr
<Instruction
> res
;
266 if (instr
->format
== Format::VOP1
) {
267 res
.reset(create_instruction
<VOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
268 } else if (instr
->format
== Format::SOP1
) {
269 res
.reset(create_instruction
<SOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
270 } else if (instr
->format
== Format::PSEUDO
) {
271 res
.reset(create_instruction
<Pseudo_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
272 } else if (instr
->format
== Format::SOPK
) {
273 res
.reset(create_instruction
<SOPK_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
274 static_cast<SOPK_instruction
*>(res
.get())->imm
= static_cast<SOPK_instruction
*>(instr
)->imm
;
276 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
277 res
->operands
[i
] = instr
->operands
[i
];
278 if (instr
->operands
[i
].isTemp()) {
279 assert(false && "unsupported");
280 if (ctx
.remat
.count(instr
->operands
[i
].getTemp()))
281 ctx
.remat_used
[ctx
.remat
[instr
->operands
[i
].getTemp()].instr
] = true;
284 res
->definitions
[0] = Definition(new_name
);
287 aco_ptr
<Pseudo_instruction
> reload
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 1, 1)};
288 reload
->operands
[0] = Operand(spill_id
);
289 reload
->definitions
[0] = Definition(new_name
);
290 ctx
.is_reloaded
[spill_id
] = true;
295 void get_rematerialize_info(spill_ctx
& ctx
)
297 for (Block
& block
: ctx
.program
->blocks
) {
298 bool logical
= false;
299 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
300 if (instr
->opcode
== aco_opcode::p_logical_start
)
302 else if (instr
->opcode
== aco_opcode::p_logical_end
)
304 if (logical
&& should_rematerialize(instr
)) {
305 for (const Definition
& def
: instr
->definitions
) {
307 ctx
.remat
[def
.getTemp()] = (remat_info
){instr
.get()};
308 ctx
.remat_used
[instr
.get()] = false;
316 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(spill_ctx
& ctx
, Block
* block
)
318 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(block
->instructions
.size());
320 std::map
<Temp
, uint32_t> next_uses
;
321 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block
->index
])
322 next_uses
[pair
.first
] = pair
.second
.second
+ block
->instructions
.size();
324 for (int idx
= block
->instructions
.size() - 1; idx
>= 0; idx
--) {
325 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
328 if (instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
)
331 for (const Operand
& op
: instr
->operands
) {
332 if (op
.isFixed() && op
.physReg() == exec
)
334 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
337 next_uses
[op
.getTemp()] = idx
;
339 for (const Definition
& def
: instr
->definitions
) {
341 next_uses
.erase(def
.getTemp());
343 local_next_uses
[idx
] = next_uses
;
345 return local_next_uses
;
349 RegisterDemand
init_live_in_vars(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
351 RegisterDemand spilled_registers
;
353 /* first block, nothing was spilled before */
357 /* loop header block */
358 if (block
->loop_nest_depth
> ctx
.program
->blocks
[block_idx
- 1].loop_nest_depth
) {
359 assert(block
->linear_preds
[0] == block_idx
- 1);
360 assert(block
->logical_preds
[0] == block_idx
- 1);
362 /* create new loop_info */
363 ctx
.loop_header
.emplace(block
);
365 /* check how many live-through variables should be spilled */
366 RegisterDemand new_demand
;
367 unsigned i
= block_idx
;
368 while (ctx
.program
->blocks
[i
].loop_nest_depth
>= block
->loop_nest_depth
) {
369 assert(ctx
.program
->blocks
.size() > i
);
370 new_demand
.update(ctx
.program
->blocks
[i
].register_demand
);
373 unsigned loop_end
= i
;
375 /* select live-through vgpr variables */
376 while (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
377 unsigned distance
= 0;
379 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
380 if (pair
.first
.type() == RegType::vgpr
&&
381 pair
.second
.first
>= loop_end
&&
382 pair
.second
.second
> distance
&&
383 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
384 to_spill
= pair
.first
;
385 distance
= pair
.second
.second
;
392 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
393 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
395 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
398 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
399 spilled_registers
.vgpr
+= to_spill
.size();
402 /* select live-through sgpr variables */
403 while (new_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
404 unsigned distance
= 0;
406 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
407 if (pair
.first
.type() == RegType::sgpr
&&
408 pair
.second
.first
>= loop_end
&&
409 pair
.second
.second
> distance
&&
410 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
411 to_spill
= pair
.first
;
412 distance
= pair
.second
.second
;
419 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
420 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
422 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
425 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
426 spilled_registers
.sgpr
+= to_spill
.size();
432 if (!RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
))
433 return spilled_registers
;
435 /* if reg pressure is too high at beginning of loop, add variables with furthest use */
437 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
|| block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
)
440 assert(idx
!= 0 && "loop without phis: TODO");
442 RegisterDemand reg_pressure
= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
443 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
444 unsigned distance
= 0;
446 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
447 if (pair
.first
.type() == RegType::sgpr
&&
448 pair
.second
.second
> distance
&&
449 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
450 to_spill
= pair
.first
;
451 distance
= pair
.second
.second
;
454 assert(distance
!= 0);
456 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
457 spilled_registers
.sgpr
+= to_spill
.size();
458 reg_pressure
.sgpr
-= to_spill
.size();
460 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
461 unsigned distance
= 0;
463 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
464 if (pair
.first
.type() == RegType::vgpr
&&
465 pair
.second
.second
> distance
&&
466 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
467 to_spill
= pair
.first
;
468 distance
= pair
.second
.second
;
471 assert(distance
!= 0);
472 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
473 spilled_registers
.vgpr
+= to_spill
.size();
474 reg_pressure
.vgpr
-= to_spill
.size();
477 return spilled_registers
;
481 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
482 /* keep variables spilled if they are alive and not used in the current block */
483 unsigned pred_idx
= block
->linear_preds
[0];
484 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
485 if (pair
.first
.type() == RegType::sgpr
&&
486 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
487 ctx
.next_use_distances_start
[block_idx
][pair
.first
].second
> block_idx
) {
488 ctx
.spills_entry
[block_idx
].insert(pair
);
489 spilled_registers
.sgpr
+= pair
.first
.size();
492 if (block
->logical_preds
.size() == 1) {
493 pred_idx
= block
->logical_preds
[0];
494 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
495 if (pair
.first
.type() == RegType::vgpr
&&
496 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
497 ctx
.next_use_distances_start
[block_idx
][pair
.first
].second
> block_idx
) {
498 ctx
.spills_entry
[block_idx
].insert(pair
);
499 spilled_registers
.vgpr
+= pair
.first
.size();
504 /* if register demand is still too high, we just keep all spilled live vars and process the block */
505 if (block
->register_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
506 pred_idx
= block
->linear_preds
[0];
507 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
508 if (pair
.first
.type() == RegType::sgpr
&&
509 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
510 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
511 spilled_registers
.sgpr
+= pair
.first
.size();
515 if (block
->register_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
&& block
->logical_preds
.size() == 1) {
516 pred_idx
= block
->logical_preds
[0];
517 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
518 if (pair
.first
.type() == RegType::vgpr
&&
519 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
520 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
521 spilled_registers
.vgpr
+= pair
.first
.size();
526 return spilled_registers
;
529 /* else: merge block */
530 std::set
<Temp
> partial_spills
;
532 /* keep variables spilled on all incoming paths */
533 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
534 std::vector
<unsigned>& preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
535 /* If it can be rematerialized, keep the variable spilled if all predecessors do not reload it.
536 * Otherwise, if any predecessor reloads it, ensure it's reloaded on all other predecessors.
537 * The idea is that it's better in practice to rematerialize redundantly than to create lots of phis. */
538 /* TODO: test this idea with more than Dawn of War III shaders (the current pipeline-db doesn't seem to exercise this path much) */
539 bool remat
= ctx
.remat
.count(pair
.first
);
541 uint32_t spill_id
= 0;
542 for (unsigned pred_idx
: preds
) {
543 /* variable is not even live at the predecessor: probably from a phi */
544 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end()) {
548 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
552 partial_spills
.insert(pair
.first
);
553 /* it might be that on one incoming path, the variable has a different spill_id, but add_couple_code() will take care of that. */
554 spill_id
= ctx
.spills_exit
[pred_idx
][pair
.first
];
560 ctx
.spills_entry
[block_idx
][pair
.first
] = spill_id
;
561 partial_spills
.erase(pair
.first
);
562 spilled_registers
+= pair
.first
;
568 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
||
569 block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
) {
570 aco_ptr
<Instruction
>& phi
= block
->instructions
[idx
];
571 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
574 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
575 if (phi
->operands
[i
].isUndefined())
577 assert(phi
->operands
[i
].isTemp());
578 if (ctx
.spills_exit
[preds
[i
]].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[preds
[i
]].end())
581 partial_spills
.insert(phi
->definitions
[0].getTemp());
584 ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()] = ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
585 partial_spills
.erase(phi
->definitions
[0].getTemp());
586 spilled_registers
+= phi
->definitions
[0].getTemp();
592 /* if reg pressure at first instruction is still too high, add partially spilled variables */
593 RegisterDemand reg_pressure
;
595 for (const Definition
& def
: block
->instructions
[idx
]->definitions
) {
597 reg_pressure
-= def
.getTemp();
600 for (const Operand
& op
: block
->instructions
[idx
]->operands
) {
601 if (op
.isTemp() && op
.isFirstKill()) {
602 reg_pressure
+= op
.getTemp();
608 reg_pressure
+= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
610 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
611 assert(!partial_spills
.empty());
613 std::set
<Temp
>::iterator it
= partial_spills
.begin();
615 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
616 while (it
!= partial_spills
.end()) {
617 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
619 if (it
->type() == RegType::sgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
620 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
625 assert(distance
!= 0);
627 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
628 partial_spills
.erase(to_spill
);
629 spilled_registers
.sgpr
+= to_spill
.size();
630 reg_pressure
.sgpr
-= to_spill
.size();
633 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
634 assert(!partial_spills
.empty());
636 std::set
<Temp
>::iterator it
= partial_spills
.begin();
638 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
639 while (it
!= partial_spills
.end()) {
640 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
642 if (it
->type() == RegType::vgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
643 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
648 assert(distance
!= 0);
650 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
651 partial_spills
.erase(to_spill
);
652 spilled_registers
.vgpr
+= to_spill
.size();
653 reg_pressure
.vgpr
-= to_spill
.size();
656 return spilled_registers
;
660 void add_coupling_code(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
662 /* no coupling code necessary */
663 if (block
->linear_preds
.size() == 0)
666 std::vector
<aco_ptr
<Instruction
>> instructions
;
667 /* branch block: TODO take other branch into consideration */
668 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
669 assert(ctx
.processed
[block
->linear_preds
[0]]);
670 assert(ctx
.register_demand
[block_idx
].size() == block
->instructions
.size());
671 std::vector
<RegisterDemand
> reg_demand
;
672 unsigned insert_idx
= 0;
673 unsigned pred_idx
= block
->linear_preds
[0];
675 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
676 if (!live
.first
.is_linear())
679 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
682 /* in register at end of predecessor */
683 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
684 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
685 if (it
!= ctx
.renames
[pred_idx
].end())
686 ctx
.renames
[block_idx
].insert(*it
);
690 /* variable is spilled at predecessor and live at current block: create reload instruction */
691 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
692 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
693 instructions
.emplace_back(std::move(reload
));
694 reg_demand
.push_back(RegisterDemand());
695 ctx
.renames
[block_idx
][live
.first
] = new_name
;
698 if (block
->logical_preds
.size() == 1) {
700 assert(insert_idx
< block
->instructions
.size());
701 instructions
.emplace_back(std::move(block
->instructions
[insert_idx
]));
702 reg_demand
.push_back(ctx
.register_demand
[block_idx
][insert_idx
]);
704 } while (instructions
.back()->opcode
!= aco_opcode::p_logical_start
);
706 unsigned pred_idx
= block
->logical_preds
[0];
707 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
708 if (live
.first
.is_linear())
711 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
714 /* in register at end of predecessor */
715 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
716 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
717 if (it
!= ctx
.renames
[pred_idx
].end())
718 ctx
.renames
[block_idx
].insert(*it
);
722 /* variable is spilled at predecessor and live at current block: create reload instruction */
723 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
724 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
725 instructions
.emplace_back(std::move(reload
));
726 reg_demand
.emplace_back(reg_demand
.back());
727 ctx
.renames
[block_idx
][live
.first
] = new_name
;
731 /* combine new reload instructions with original block */
732 if (!instructions
.empty()) {
733 reg_demand
.insert(reg_demand
.end(), std::next(ctx
.register_demand
[block
->index
].begin(), insert_idx
),
734 ctx
.register_demand
[block
->index
].end());
735 ctx
.register_demand
[block_idx
] = std::move(reg_demand
);
736 instructions
.insert(instructions
.end(),
737 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(std::next(block
->instructions
.begin(), insert_idx
)),
738 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
739 block
->instructions
= std::move(instructions
);
744 /* loop header and merge blocks: check if all (linear) predecessors have been processed */
745 for (ASSERTED
unsigned pred
: block
->linear_preds
)
746 assert(ctx
.processed
[pred
]);
748 /* iterate the phi nodes for which operands to spill at the predecessor */
749 for (aco_ptr
<Instruction
>& phi
: block
->instructions
) {
750 if (phi
->opcode
!= aco_opcode::p_phi
&&
751 phi
->opcode
!= aco_opcode::p_linear_phi
)
754 /* if the phi is not spilled, add to instructions */
755 if (ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end()) {
756 instructions
.emplace_back(std::move(phi
));
760 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
761 uint32_t def_spill_id
= ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()];
763 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
764 if (phi
->operands
[i
].isUndefined())
767 unsigned pred_idx
= preds
[i
];
768 assert(phi
->operands
[i
].isTemp() && phi
->operands
[i
].isKill());
769 Temp var
= phi
->operands
[i
].getTemp();
771 /* build interferences between the phi def and all spilled variables at the predecessor blocks */
772 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
773 if (var
== pair
.first
)
775 ctx
.interferences
[def_spill_id
].second
.emplace(pair
.second
);
776 ctx
.interferences
[pair
.second
].second
.emplace(def_spill_id
);
779 /* check if variable is already spilled at predecessor */
780 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(var
);
781 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
782 if (spilled
->second
!= def_spill_id
)
783 ctx
.add_affinity(def_spill_id
, spilled
->second
);
787 /* rename if necessary */
788 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
789 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
790 var
= rename_it
->second
;
791 ctx
.renames
[pred_idx
].erase(rename_it
);
794 uint32_t spill_id
= ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
795 ctx
.add_affinity(def_spill_id
, spill_id
);
796 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
797 spill
->operands
[0] = Operand(var
);
798 spill
->operands
[1] = Operand(spill_id
);
799 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
800 unsigned idx
= pred
.instructions
.size();
804 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
805 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
806 pred
.instructions
.insert(it
, std::move(spill
));
807 ctx
.spills_exit
[pred_idx
][phi
->operands
[i
].getTemp()] = spill_id
;
810 /* remove phi from instructions */
814 /* iterate all (other) spilled variables for which to spill at the predecessor */
815 // TODO: would be better to have them sorted: first vgprs and first with longest distance
816 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_entry
[block_idx
]) {
817 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
819 for (unsigned pred_idx
: preds
) {
820 /* variable is already spilled at predecessor */
821 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(pair
.first
);
822 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
823 if (spilled
->second
!= pair
.second
)
824 ctx
.add_affinity(pair
.second
, spilled
->second
);
828 /* variable is dead at predecessor, it must be from a phi: this works because of CSSA form */
829 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
832 /* add interferences between spilled variable and predecessors exit spills */
833 for (std::pair
<Temp
, uint32_t> exit_spill
: ctx
.spills_exit
[pred_idx
]) {
834 if (exit_spill
.first
== pair
.first
)
836 ctx
.interferences
[exit_spill
.second
].second
.emplace(pair
.second
);
837 ctx
.interferences
[pair
.second
].second
.emplace(exit_spill
.second
);
840 /* variable is in register at predecessor and has to be spilled */
841 /* rename if necessary */
842 Temp var
= pair
.first
;
843 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
844 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
845 var
= rename_it
->second
;
846 ctx
.renames
[pred_idx
].erase(rename_it
);
849 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
850 spill
->operands
[0] = Operand(var
);
851 spill
->operands
[1] = Operand(pair
.second
);
852 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
853 unsigned idx
= pred
.instructions
.size();
857 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
858 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
859 pred
.instructions
.insert(it
, std::move(spill
));
860 ctx
.spills_exit
[pred
.index
][pair
.first
] = pair
.second
;
864 /* iterate phis for which operands to reload */
865 for (aco_ptr
<Instruction
>& phi
: instructions
) {
866 assert(phi
->opcode
== aco_opcode::p_phi
|| phi
->opcode
== aco_opcode::p_linear_phi
);
867 assert(ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end());
869 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
870 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
871 if (!phi
->operands
[i
].isTemp())
873 unsigned pred_idx
= preds
[i
];
876 if (ctx
.spills_exit
[pred_idx
].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[pred_idx
].end()) {
877 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(phi
->operands
[i
].getTemp());
878 if (it
!= ctx
.renames
[pred_idx
].end())
879 phi
->operands
[i
].setTemp(it
->second
);
883 Temp tmp
= phi
->operands
[i
].getTemp();
885 /* reload phi operand at end of predecessor block */
886 Temp new_name
= {ctx
.program
->allocateId(), tmp
.regClass()};
887 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
888 unsigned idx
= pred
.instructions
.size();
892 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
893 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
895 aco_ptr
<Instruction
> reload
= do_reload(ctx
, tmp
, new_name
, ctx
.spills_exit
[pred_idx
][tmp
]);
896 pred
.instructions
.insert(it
, std::move(reload
));
898 ctx
.spills_exit
[pred_idx
].erase(tmp
);
899 ctx
.renames
[pred_idx
][tmp
] = new_name
;
900 phi
->operands
[i
].setTemp(new_name
);
904 /* iterate live variables for which to reload */
905 // TODO: reload at current block if variable is spilled on all predecessors
906 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
907 /* skip spilled variables */
908 if (ctx
.spills_entry
[block_idx
].find(pair
.first
) != ctx
.spills_entry
[block_idx
].end())
910 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
912 /* variable is dead at predecessor, it must be from a phi */
913 bool is_dead
= false;
914 for (unsigned pred_idx
: preds
) {
915 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
920 for (unsigned pred_idx
: preds
) {
921 /* the variable is not spilled at the predecessor */
922 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end())
925 /* variable is spilled at predecessor and has to be reloaded */
926 Temp new_name
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
927 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
928 unsigned idx
= pred
.instructions
.size();
932 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
933 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
935 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.first
, new_name
, ctx
.spills_exit
[pred
.index
][pair
.first
]);
936 pred
.instructions
.insert(it
, std::move(reload
));
938 ctx
.spills_exit
[pred
.index
].erase(pair
.first
);
939 ctx
.renames
[pred
.index
][pair
.first
] = new_name
;
942 /* check if we have to create a new phi for this variable */
943 Temp rename
= Temp();
945 for (unsigned pred_idx
: preds
) {
946 if (ctx
.renames
[pred_idx
].find(pair
.first
) == ctx
.renames
[pred_idx
].end()) {
947 if (rename
== Temp())
950 is_same
= rename
== pair
.first
;
952 if (rename
== Temp())
953 rename
= ctx
.renames
[pred_idx
][pair
.first
];
955 is_same
= rename
== ctx
.renames
[pred_idx
][pair
.first
];
963 /* the variable was renamed differently in the predecessors: we have to create a phi */
964 aco_opcode opcode
= pair
.first
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
965 aco_ptr
<Pseudo_instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
966 rename
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
967 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
969 if (ctx
.renames
[preds
[i
]].find(pair
.first
) != ctx
.renames
[preds
[i
]].end())
970 tmp
= ctx
.renames
[preds
[i
]][pair
.first
];
971 else if (preds
[i
] >= block_idx
)
975 phi
->operands
[i
] = Operand(tmp
);
977 phi
->definitions
[0] = Definition(rename
);
978 instructions
.emplace_back(std::move(phi
));
981 /* the variable was renamed: add new name to renames */
982 if (!(rename
== Temp() || rename
== pair
.first
))
983 ctx
.renames
[block_idx
][pair
.first
] = rename
;
986 /* combine phis with instructions */
988 while (!block
->instructions
[idx
]) {
992 ctx
.register_demand
[block
->index
].erase(ctx
.register_demand
[block
->index
].begin(), ctx
.register_demand
[block
->index
].begin() + idx
);
993 ctx
.register_demand
[block
->index
].insert(ctx
.register_demand
[block
->index
].begin(), instructions
.size(), RegisterDemand());
995 std::vector
<aco_ptr
<Instruction
>>::iterator start
= std::next(block
->instructions
.begin(), idx
);
996 instructions
.insert(instructions
.end(), std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(start
),
997 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
998 block
->instructions
= std::move(instructions
);
1001 void process_block(spill_ctx
& ctx
, unsigned block_idx
, Block
* block
,
1002 std::map
<Temp
, uint32_t> ¤t_spills
, RegisterDemand spilled_registers
)
1004 std::vector
<std::map
<Temp
, uint32_t>> local_next_use_distance
;
1005 std::vector
<aco_ptr
<Instruction
>> instructions
;
1008 /* phis are handled separetely */
1009 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
||
1010 block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
) {
1011 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1012 for (const Operand
& op
: instr
->operands
) {
1013 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1014 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1015 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1017 instructions
.emplace_back(std::move(instr
));
1021 if (block
->register_demand
.exceeds(ctx
.target_pressure
))
1022 local_next_use_distance
= local_next_uses(ctx
, block
);
1024 while (idx
< block
->instructions
.size()) {
1025 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1027 std::map
<Temp
, std::pair
<Temp
, uint32_t>> reloads
;
1028 std::map
<Temp
, uint32_t> spills
;
1029 /* rename and reload operands */
1030 for (Operand
& op
: instr
->operands
) {
1033 if (current_spills
.find(op
.getTemp()) == current_spills
.end()) {
1034 /* the Operand is in register: check if it was renamed */
1035 if (ctx
.renames
[block_idx
].find(op
.getTemp()) != ctx
.renames
[block_idx
].end())
1036 op
.setTemp(ctx
.renames
[block_idx
][op
.getTemp()]);
1037 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1038 if (ctx
.remat
.count(op
.getTemp()))
1039 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1042 /* the Operand is spilled: add it to reloads */
1043 Temp new_tmp
= {ctx
.program
->allocateId(), op
.regClass()};
1044 ctx
.renames
[block_idx
][op
.getTemp()] = new_tmp
;
1045 reloads
[new_tmp
] = std::make_pair(op
.getTemp(), current_spills
[op
.getTemp()]);
1046 current_spills
.erase(op
.getTemp());
1047 op
.setTemp(new_tmp
);
1048 spilled_registers
-= new_tmp
;
1051 /* check if register demand is low enough before and after the current instruction */
1052 if (block
->register_demand
.exceeds(ctx
.target_pressure
)) {
1054 RegisterDemand new_demand
= ctx
.register_demand
[block_idx
][idx
];
1056 RegisterDemand demand_before
= new_demand
;
1057 for (const Definition
& def
: instr
->definitions
)
1058 demand_before
-= def
.getTemp();
1059 for (const Operand
& op
: instr
->operands
) {
1060 if (op
.isFirstKill())
1061 demand_before
+= op
.getTemp();
1063 new_demand
.update(demand_before
);
1065 new_demand
.update(ctx
.register_demand
[block_idx
][idx
- 1]);
1068 assert(!local_next_use_distance
.empty());
1070 /* if reg pressure is too high, spill variable with furthest next use */
1071 while (RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
)) {
1072 unsigned distance
= 0;
1074 bool do_rematerialize
= false;
1075 if (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
1076 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1077 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1078 if (pair
.first
.type() == RegType::vgpr
&&
1079 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1080 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1081 current_spills
.find(pair
.first
) == current_spills
.end() &&
1082 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1083 to_spill
= pair
.first
;
1084 distance
= pair
.second
;
1085 do_rematerialize
= can_rematerialize
;
1089 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1090 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1091 if (pair
.first
.type() == RegType::sgpr
&&
1092 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1093 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1094 current_spills
.find(pair
.first
) == current_spills
.end() &&
1095 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1096 to_spill
= pair
.first
;
1097 distance
= pair
.second
;
1098 do_rematerialize
= can_rematerialize
;
1103 assert(distance
!= 0 && distance
> idx
);
1104 uint32_t spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
1106 /* add interferences with currently spilled variables */
1107 for (std::pair
<Temp
, uint32_t> pair
: current_spills
) {
1108 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
);
1109 ctx
.interferences
[pair
.second
].second
.emplace(spill_id
);
1111 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1112 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
.second
);
1113 ctx
.interferences
[pair
.second
.second
].second
.emplace(spill_id
);
1116 current_spills
[to_spill
] = spill_id
;
1117 spilled_registers
+= to_spill
;
1119 /* rename if necessary */
1120 if (ctx
.renames
[block_idx
].find(to_spill
) != ctx
.renames
[block_idx
].end()) {
1121 to_spill
= ctx
.renames
[block_idx
][to_spill
];
1124 /* add spill to new instructions */
1125 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
1126 spill
->operands
[0] = Operand(to_spill
);
1127 spill
->operands
[1] = Operand(spill_id
);
1128 instructions
.emplace_back(std::move(spill
));
1132 /* add reloads and instruction to new instructions */
1133 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1134 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.second
.first
, pair
.first
, pair
.second
.second
);
1135 instructions
.emplace_back(std::move(reload
));
1137 instructions
.emplace_back(std::move(instr
));
1141 block
->instructions
= std::move(instructions
);
1142 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1145 void spill_block(spill_ctx
& ctx
, unsigned block_idx
)
1147 Block
* block
= &ctx
.program
->blocks
[block_idx
];
1148 ctx
.processed
[block_idx
] = true;
1150 /* determine set of variables which are spilled at the beginning of the block */
1151 RegisterDemand spilled_registers
= init_live_in_vars(ctx
, block
, block_idx
);
1153 /* add interferences for spilled variables */
1154 for (std::pair
<Temp
, uint32_t> x
: ctx
.spills_entry
[block_idx
]) {
1155 for (std::pair
<Temp
, uint32_t> y
: ctx
.spills_entry
[block_idx
])
1156 if (x
.second
!= y
.second
)
1157 ctx
.interferences
[x
.second
].second
.emplace(y
.second
);
1160 bool is_loop_header
= block
->loop_nest_depth
&& ctx
.loop_header
.top()->index
== block_idx
;
1161 if (!is_loop_header
) {
1162 /* add spill/reload code on incoming control flow edges */
1163 add_coupling_code(ctx
, block
, block_idx
);
1166 std::map
<Temp
, uint32_t> current_spills
= ctx
.spills_entry
[block_idx
];
1168 /* check conditions to process this block */
1169 bool process
= RegisterDemand(block
->register_demand
- spilled_registers
).exceeds(ctx
.target_pressure
) ||
1170 !ctx
.renames
[block_idx
].empty() ||
1171 ctx
.remat_used
.size();
1173 std::map
<Temp
, uint32_t>::iterator it
= current_spills
.begin();
1174 while (!process
&& it
!= current_spills
.end()) {
1175 if (ctx
.next_use_distances_start
[block_idx
][it
->first
].first
== block_idx
)
1181 process_block(ctx
, block_idx
, block
, current_spills
, spilled_registers
);
1183 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1185 /* check if the next block leaves the current loop */
1186 if (block
->loop_nest_depth
== 0 || ctx
.program
->blocks
[block_idx
+ 1].loop_nest_depth
>= block
->loop_nest_depth
)
1189 Block
* loop_header
= ctx
.loop_header
.top();
1191 /* preserve original renames at end of loop header block */
1192 std::map
<Temp
, Temp
> renames
= std::move(ctx
.renames
[loop_header
->index
]);
1194 /* add coupling code to all loop header predecessors */
1195 add_coupling_code(ctx
, loop_header
, loop_header
->index
);
1197 /* update remat_used for phis added in add_coupling_code() */
1198 for (aco_ptr
<Instruction
>& instr
: loop_header
->instructions
) {
1201 for (const Operand
& op
: instr
->operands
) {
1202 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1203 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1207 /* propagate new renames through loop: i.e. repair the SSA */
1208 renames
.swap(ctx
.renames
[loop_header
->index
]);
1209 for (std::pair
<Temp
, Temp
> rename
: renames
) {
1210 for (unsigned idx
= loop_header
->index
; idx
<= block_idx
; idx
++) {
1211 Block
& current
= ctx
.program
->blocks
[idx
];
1212 std::vector
<aco_ptr
<Instruction
>>::iterator instr_it
= current
.instructions
.begin();
1214 /* first rename phis */
1215 while (instr_it
!= current
.instructions
.end()) {
1216 aco_ptr
<Instruction
>& phi
= *instr_it
;
1217 if (phi
->opcode
!= aco_opcode::p_phi
&& phi
->opcode
!= aco_opcode::p_linear_phi
)
1219 /* no need to rename the loop header phis once again. this happened in add_coupling_code() */
1220 if (idx
== loop_header
->index
) {
1225 for (Operand
& op
: phi
->operands
) {
1228 if (op
.getTemp() == rename
.first
)
1229 op
.setTemp(rename
.second
);
1234 std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= ctx
.next_use_distances_start
[idx
].find(rename
.first
);
1236 /* variable is not live at beginning of this block */
1237 if (it
== ctx
.next_use_distances_start
[idx
].end())
1240 /* if the variable is live at the block's exit, add rename */
1241 if (ctx
.next_use_distances_end
[idx
].find(rename
.first
) != ctx
.next_use_distances_end
[idx
].end())
1242 ctx
.renames
[idx
].insert(rename
);
1244 /* rename all uses in this block */
1245 bool renamed
= false;
1246 while (!renamed
&& instr_it
!= current
.instructions
.end()) {
1247 aco_ptr
<Instruction
>& instr
= *instr_it
;
1248 for (Operand
& op
: instr
->operands
) {
1251 if (op
.getTemp() == rename
.first
) {
1252 op
.setTemp(rename
.second
);
1253 /* we can stop with this block as soon as the variable is spilled */
1254 if (instr
->opcode
== aco_opcode::p_spill
)
1263 /* remove loop header info from stack */
1264 ctx
.loop_header
.pop();
1267 Temp
load_scratch_resource(spill_ctx
& ctx
, Temp
& scratch_offset
,
1268 std::vector
<aco_ptr
<Instruction
>>& instructions
,
1269 unsigned offset
, bool is_top_level
)
1271 Builder
bld(ctx
.program
);
1273 bld
.reset(&instructions
);
1275 /* find p_logical_end */
1276 unsigned idx
= instructions
.size() - 1;
1277 while (instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
)
1279 bld
.reset(&instructions
, std::next(instructions
.begin(), idx
));
1282 Temp private_segment_buffer
= ctx
.program
->private_segment_buffer
;
1283 if (ctx
.program
->stage
!= compute_cs
)
1284 private_segment_buffer
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, Operand(0u));
1287 scratch_offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), scratch_offset
, Operand(offset
));
1289 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
1290 S_008F0C_INDEX_STRIDE(ctx
.program
->wave_size
== 64 ? 3 : 2);
1292 if (ctx
.program
->chip_class
>= GFX10
) {
1293 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1294 S_008F0C_OOB_SELECT(3) |
1295 S_008F0C_RESOURCE_LEVEL(1);
1296 } else if (ctx
.program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
1297 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1298 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1300 /* older generations need element size = 4 bytes. element size removed in GFX9 */
1301 if (ctx
.program
->chip_class
<= GFX8
)
1302 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
1304 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
1305 private_segment_buffer
, Operand(-1u),
1306 Operand(rsrc_conf
));
1309 void assign_spill_slots(spill_ctx
& ctx
, unsigned spills_to_vgpr
) {
1310 std::map
<uint32_t, uint32_t> sgpr_slot
;
1311 std::map
<uint32_t, uint32_t> vgpr_slot
;
1312 std::vector
<bool> is_assigned(ctx
.interferences
.size());
1314 /* first, handle affinities: just merge all interferences into both spill ids */
1315 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1316 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1317 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1318 assert(vec
[i
] != vec
[j
]);
1319 for (uint32_t id
: ctx
.interferences
[vec
[i
]].second
)
1320 ctx
.interferences
[id
].second
.insert(vec
[j
]);
1321 for (uint32_t id
: ctx
.interferences
[vec
[j
]].second
)
1322 ctx
.interferences
[id
].second
.insert(vec
[i
]);
1323 ctx
.interferences
[vec
[i
]].second
.insert(ctx
.interferences
[vec
[j
]].second
.begin(), ctx
.interferences
[vec
[j
]].second
.end());
1324 ctx
.interferences
[vec
[j
]].second
.insert(ctx
.interferences
[vec
[i
]].second
.begin(), ctx
.interferences
[vec
[i
]].second
.end());
1326 bool reloaded
= ctx
.is_reloaded
[vec
[i
]] || ctx
.is_reloaded
[vec
[j
]];
1327 ctx
.is_reloaded
[vec
[i
]] = reloaded
;
1328 ctx
.is_reloaded
[vec
[j
]] = reloaded
;
1332 for (ASSERTED
uint32_t i
= 0; i
< ctx
.interferences
.size(); i
++)
1333 for (ASSERTED
uint32_t id
: ctx
.interferences
[i
].second
)
1336 /* for each spill slot, assign as many spill ids as possible */
1337 std::vector
<std::set
<uint32_t>> spill_slot_interferences
;
1338 unsigned slot_idx
= 0;
1341 /* assign sgpr spill slots */
1344 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1345 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1347 if (ctx
.interferences
[id
].first
.type() != RegType::sgpr
)
1350 /* check interferences */
1351 bool interferes
= false;
1352 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1353 if (i
== spill_slot_interferences
.size())
1354 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1355 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end() || i
/ ctx
.wave_size
!= slot_idx
/ ctx
.wave_size
) {
1365 /* we found a spill id which can be assigned to current spill slot */
1366 sgpr_slot
[id
] = slot_idx
;
1367 is_assigned
[id
] = true;
1368 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1369 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1371 /* add all affinities: there are no additional interferences */
1372 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1373 bool found_affinity
= false;
1374 for (uint32_t entry
: vec
) {
1376 found_affinity
= true;
1380 if (!found_affinity
)
1382 for (uint32_t entry
: vec
) {
1383 sgpr_slot
[entry
] = slot_idx
;
1384 is_assigned
[entry
] = true;
1391 unsigned sgpr_spill_slots
= spill_slot_interferences
.size();
1392 spill_slot_interferences
.clear();
1396 /* assign vgpr spill slots */
1399 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1400 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1402 if (ctx
.interferences
[id
].first
.type() != RegType::vgpr
)
1405 /* check interferences */
1406 bool interferes
= false;
1407 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1408 if (i
== spill_slot_interferences
.size())
1409 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1410 /* check for interference and ensure that vector regs are stored next to each other */
1411 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end()) {
1421 /* we found a spill id which can be assigned to current spill slot */
1422 vgpr_slot
[id
] = slot_idx
;
1423 is_assigned
[id
] = true;
1424 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1425 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1427 /* add all affinities: there are no additional interferences */
1428 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1429 bool found_affinity
= false;
1430 for (uint32_t entry
: vec
) {
1432 found_affinity
= true;
1436 if (!found_affinity
)
1438 for (uint32_t entry
: vec
) {
1439 vgpr_slot
[entry
] = slot_idx
;
1440 is_assigned
[entry
] = true;
1447 unsigned vgpr_spill_slots
= spill_slot_interferences
.size();
1449 for (unsigned id
= 0; id
< is_assigned
.size(); id
++)
1450 assert(is_assigned
[id
] || !ctx
.is_reloaded
[id
]);
1452 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1453 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1454 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1455 assert(is_assigned
[vec
[i
]] == is_assigned
[vec
[j
]]);
1456 if (!is_assigned
[vec
[i
]])
1458 assert(ctx
.is_reloaded
[vec
[i
]] == ctx
.is_reloaded
[vec
[j
]]);
1459 assert(ctx
.interferences
[vec
[i
]].first
.type() == ctx
.interferences
[vec
[j
]].first
.type());
1460 if (ctx
.interferences
[vec
[i
]].first
.type() == RegType::sgpr
)
1461 assert(sgpr_slot
[vec
[i
]] == sgpr_slot
[vec
[j
]]);
1463 assert(vgpr_slot
[vec
[i
]] == vgpr_slot
[vec
[j
]]);
1468 /* hope, we didn't mess up */
1469 std::vector
<Temp
> vgpr_spill_temps((sgpr_spill_slots
+ ctx
.wave_size
- 1) / ctx
.wave_size
);
1470 assert(vgpr_spill_temps
.size() <= spills_to_vgpr
);
1472 /* replace pseudo instructions with actual hardware instructions */
1473 Temp scratch_offset
= ctx
.program
->scratch_offset
, scratch_rsrc
= Temp();
1474 unsigned last_top_level_block_idx
= 0;
1475 std::vector
<bool> reload_in_loop(vgpr_spill_temps
.size());
1476 for (Block
& block
: ctx
.program
->blocks
) {
1478 /* after loops, we insert a user if there was a reload inside the loop */
1479 if (block
.loop_nest_depth
== 0) {
1481 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1482 if (reload_in_loop
[i
])
1486 if (end_vgprs
> 0) {
1487 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, end_vgprs
, 0)};
1489 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1490 if (reload_in_loop
[i
])
1491 destr
->operands
[k
++] = Operand(vgpr_spill_temps
[i
]);
1492 reload_in_loop
[i
] = false;
1494 /* find insertion point */
1495 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1496 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1498 block
.instructions
.insert(it
, std::move(destr
));
1502 if (block
.kind
& block_kind_top_level
&& !block
.linear_preds
.empty()) {
1503 last_top_level_block_idx
= block
.index
;
1505 /* check if any spilled variables use a created linear vgpr, otherwise destroy them */
1506 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1507 if (vgpr_spill_temps
[i
] == Temp())
1510 bool can_destroy
= true;
1511 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[block
.linear_preds
[0]]) {
1513 if (sgpr_slot
.find(pair
.second
) != sgpr_slot
.end() &&
1514 sgpr_slot
[pair
.second
] / ctx
.wave_size
== i
) {
1515 can_destroy
= false;
1520 vgpr_spill_temps
[i
] = Temp();
1524 std::vector
<aco_ptr
<Instruction
>>::iterator it
;
1525 std::vector
<aco_ptr
<Instruction
>> instructions
;
1526 instructions
.reserve(block
.instructions
.size());
1527 Builder
bld(ctx
.program
, &instructions
);
1528 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1530 if ((*it
)->opcode
== aco_opcode::p_spill
) {
1531 uint32_t spill_id
= (*it
)->operands
[1].constantValue();
1533 if (!ctx
.is_reloaded
[spill_id
]) {
1534 /* never reloaded, so don't spill */
1535 } else if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1537 ctx
.program
->config
->spilled_vgprs
+= (*it
)->operands
[0].size();
1538 uint32_t spill_slot
= vgpr_slot
[spill_id
];
1539 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1540 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1542 /* check if the scratch resource descriptor already exists */
1543 if (scratch_rsrc
== Temp()) {
1544 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1545 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1546 last_top_level_block_idx
== block
.index
?
1547 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1549 last_top_level_block_idx
== block
.index
);
1552 unsigned offset
= base_offset
+ spill_slot
* 4;
1553 aco_opcode opcode
= aco_opcode::buffer_store_dword
;
1554 assert((*it
)->operands
[0].isTemp());
1555 Temp temp
= (*it
)->operands
[0].getTemp();
1556 assert(temp
.type() == RegType::vgpr
&& !temp
.is_linear());
1557 if (temp
.size() > 1) {
1558 Instruction
* split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, temp
.size())};
1559 split
->operands
[0] = Operand(temp
);
1560 for (unsigned i
= 0; i
< temp
.size(); i
++)
1561 split
->definitions
[i
] = bld
.def(v1
);
1563 for (unsigned i
= 0; i
< temp
.size(); i
++)
1564 bld
.mubuf(opcode
, Operand(), scratch_rsrc
, scratch_offset
, split
->definitions
[i
].getTemp(), offset
+ i
* 4, false);
1566 bld
.mubuf(opcode
, Operand(), scratch_rsrc
, scratch_offset
, temp
, offset
, false);
1568 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1569 ctx
.program
->config
->spilled_sgprs
+= (*it
)->operands
[0].size();
1571 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1573 /* check if the linear vgpr already exists */
1574 if (vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] == Temp()) {
1575 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1576 vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] = linear_vgpr
;
1577 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1578 create
->definitions
[0] = Definition(linear_vgpr
);
1579 /* find the right place to insert this definition */
1580 if (last_top_level_block_idx
== block
.index
) {
1581 /* insert right before the current instruction */
1582 instructions
.emplace_back(std::move(create
));
1584 assert(last_top_level_block_idx
< block
.index
);
1585 /* insert before the branch at last top level block */
1586 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1587 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1591 /* spill sgpr: just add the vgpr temp to operands */
1592 Pseudo_instruction
* spill
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 3, 0);
1593 spill
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
]);
1594 spill
->operands
[1] = Operand(spill_slot
% ctx
.wave_size
);
1595 spill
->operands
[2] = (*it
)->operands
[0];
1596 instructions
.emplace_back(aco_ptr
<Instruction
>(spill
));
1598 unreachable("No spill slot assigned for spill id");
1601 } else if ((*it
)->opcode
== aco_opcode::p_reload
) {
1602 uint32_t spill_id
= (*it
)->operands
[0].constantValue();
1603 assert(ctx
.is_reloaded
[spill_id
]);
1605 if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1607 uint32_t spill_slot
= vgpr_slot
[spill_id
];
1608 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1609 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1611 /* check if the scratch resource descriptor already exists */
1612 if (scratch_rsrc
== Temp()) {
1613 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1614 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1615 last_top_level_block_idx
== block
.index
?
1616 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1618 last_top_level_block_idx
== block
.index
);
1621 unsigned offset
= base_offset
+ spill_slot
* 4;
1622 aco_opcode opcode
= aco_opcode::buffer_load_dword
;
1623 Definition def
= (*it
)->definitions
[0];
1624 if (def
.size() > 1) {
1625 Instruction
* vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, def
.size(), 1)};
1626 vec
->definitions
[0] = def
;
1627 for (unsigned i
= 0; i
< def
.size(); i
++) {
1628 Temp tmp
= bld
.tmp(v1
);
1629 vec
->operands
[i
] = Operand(tmp
);
1630 bld
.mubuf(opcode
, Definition(tmp
), Operand(), scratch_rsrc
, scratch_offset
, offset
+ i
* 4, false);
1634 bld
.mubuf(opcode
, def
, Operand(), scratch_rsrc
, scratch_offset
, offset
, false);
1636 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1637 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1638 reload_in_loop
[spill_slot
/ ctx
.wave_size
] = block
.loop_nest_depth
> 0;
1640 /* check if the linear vgpr already exists */
1641 if (vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] == Temp()) {
1642 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1643 vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
] = linear_vgpr
;
1644 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1645 create
->definitions
[0] = Definition(linear_vgpr
);
1646 /* find the right place to insert this definition */
1647 if (last_top_level_block_idx
== block
.index
) {
1648 /* insert right before the current instruction */
1649 instructions
.emplace_back(std::move(create
));
1651 assert(last_top_level_block_idx
< block
.index
);
1652 /* insert before the branch at last top level block */
1653 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1654 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1658 /* reload sgpr: just add the vgpr temp to operands */
1659 Pseudo_instruction
* reload
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 2, 1);
1660 reload
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ ctx
.wave_size
]);
1661 reload
->operands
[1] = Operand(spill_slot
% ctx
.wave_size
);
1662 reload
->definitions
[0] = (*it
)->definitions
[0];
1663 instructions
.emplace_back(aco_ptr
<Instruction
>(reload
));
1665 unreachable("No spill slot assigned for spill id");
1667 } else if (!ctx
.remat_used
.count(it
->get()) || ctx
.remat_used
[it
->get()]) {
1668 instructions
.emplace_back(std::move(*it
));
1672 block
.instructions
= std::move(instructions
);
1675 /* update required scratch memory */
1676 ctx
.program
->config
->scratch_bytes_per_wave
+= align(vgpr_spill_slots
* 4 * ctx
.program
->wave_size
, 1024);
1678 /* SSA elimination inserts copies for logical phis right before p_logical_end
1679 * So if a linear vgpr is used between that p_logical_end and the branch,
1680 * we need to ensure logical phis don't choose a definition which aliases
1682 * TODO: Moving the spills and reloads to before p_logical_end might produce
1683 * slightly better code. */
1684 for (Block
& block
: ctx
.program
->blocks
) {
1685 /* loops exits are already handled */
1686 if (block
.logical_preds
.size() <= 1)
1689 bool has_logical_phis
= false;
1690 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
1691 if (instr
->opcode
== aco_opcode::p_phi
) {
1692 has_logical_phis
= true;
1694 } else if (instr
->opcode
!= aco_opcode::p_linear_phi
) {
1698 if (!has_logical_phis
)
1701 std::set
<Temp
> vgprs
;
1702 for (unsigned pred_idx
: block
.logical_preds
) {
1703 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
1704 for (int i
= pred
.instructions
.size() - 1; i
>= 0; i
--) {
1705 aco_ptr
<Instruction
>& pred_instr
= pred
.instructions
[i
];
1706 if (pred_instr
->opcode
== aco_opcode::p_logical_end
) {
1708 } else if (pred_instr
->opcode
== aco_opcode::p_spill
||
1709 pred_instr
->opcode
== aco_opcode::p_reload
) {
1710 vgprs
.insert(pred_instr
->operands
[0].getTemp());
1717 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, vgprs
.size(), 0)};
1719 for (Temp tmp
: vgprs
) {
1720 destr
->operands
[k
++] = Operand(tmp
);
1722 /* find insertion point */
1723 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1724 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1726 block
.instructions
.insert(it
, std::move(destr
));
1730 } /* end namespace */
1733 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
)
1735 program
->config
->spilled_vgprs
= 0;
1736 program
->config
->spilled_sgprs
= 0;
1738 /* no spilling when register pressure is low enough */
1739 if (program
->num_waves
> 0)
1742 /* lower to CSSA before spilling to ensure correctness w.r.t. phis */
1743 lower_to_cssa(program
, live_vars
, options
);
1745 /* calculate target register demand */
1746 RegisterDemand register_target
= program
->max_reg_demand
;
1747 if (register_target
.sgpr
> program
->sgpr_limit
)
1748 register_target
.vgpr
+= (register_target
.sgpr
- program
->sgpr_limit
+ program
->wave_size
- 1 + 32) / program
->wave_size
;
1749 register_target
.sgpr
= program
->sgpr_limit
;
1751 if (register_target
.vgpr
> program
->vgpr_limit
)
1752 register_target
.sgpr
= program
->sgpr_limit
- 5;
1753 register_target
.vgpr
= program
->vgpr_limit
- (register_target
.vgpr
- program
->max_reg_demand
.vgpr
);
1755 int spills_to_vgpr
= (program
->max_reg_demand
.sgpr
- register_target
.sgpr
+ program
->wave_size
- 1 + 32) / program
->wave_size
;
1757 /* initialize ctx */
1758 spill_ctx
ctx(register_target
, program
, live_vars
.register_demand
);
1759 compute_global_next_uses(ctx
, live_vars
.live_out
);
1760 get_rematerialize_info(ctx
);
1762 /* create spills and reloads */
1763 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++)
1764 spill_block(ctx
, i
);
1766 /* assign spill slots and DCE rematerialized code */
1767 assign_spill_slots(ctx
, spills_to_vgpr
);
1769 /* update live variable information */
1770 live_vars
= live_var_analysis(program
, options
);
1772 assert(program
->num_waves
>= 0);