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27 #include "aco_builder.h"
34 * Implements the spilling algorithm on SSA-form from
35 * "Register Spilling and Live-Range Splitting for SSA-Form Programs"
36 * by Matthias Braun and Sebastian Hack.
48 RegisterDemand target_pressure
;
50 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
51 std::vector
<std::map
<Temp
, Temp
>> renames
;
52 std::vector
<std::map
<Temp
, uint32_t>> spills_entry
;
53 std::vector
<std::map
<Temp
, uint32_t>> spills_exit
;
54 std::vector
<bool> processed
;
55 std::stack
<Block
*> loop_header
;
56 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_start
;
57 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_end
;
58 std::vector
<std::pair
<RegClass
, std::set
<uint32_t>>> interferences
;
59 std::vector
<std::vector
<uint32_t>> affinities
;
60 std::vector
<bool> is_reloaded
;
61 std::map
<Temp
, remat_info
> remat
;
62 std::map
<Instruction
*, bool> remat_used
;
64 spill_ctx(const RegisterDemand target_pressure
, Program
* program
,
65 std::vector
<std::vector
<RegisterDemand
>> register_demand
)
66 : target_pressure(target_pressure
), program(program
),
67 register_demand(register_demand
), renames(program
->blocks
.size()),
68 spills_entry(program
->blocks
.size()), spills_exit(program
->blocks
.size()),
69 processed(program
->blocks
.size(), false) {}
71 void add_affinity(uint32_t first
, uint32_t second
)
73 unsigned found_first
= affinities
.size();
74 unsigned found_second
= affinities
.size();
75 for (unsigned i
= 0; i
< affinities
.size(); i
++) {
76 std::vector
<uint32_t>& vec
= affinities
[i
];
77 for (uint32_t entry
: vec
) {
80 else if (entry
== second
)
84 if (found_first
== affinities
.size() && found_second
== affinities
.size()) {
85 affinities
.emplace_back(std::vector
<uint32_t>({first
, second
}));
86 } else if (found_first
< affinities
.size() && found_second
== affinities
.size()) {
87 affinities
[found_first
].push_back(second
);
88 } else if (found_second
< affinities
.size() && found_first
== affinities
.size()) {
89 affinities
[found_second
].push_back(first
);
90 } else if (found_first
!= found_second
) {
91 /* merge second into first */
92 affinities
[found_first
].insert(affinities
[found_first
].end(), affinities
[found_second
].begin(), affinities
[found_second
].end());
93 affinities
.erase(std::next(affinities
.begin(), found_second
));
95 assert(found_first
== found_second
);
99 uint32_t allocate_spill_id(RegClass rc
)
101 interferences
.emplace_back(rc
, std::set
<uint32_t>());
102 is_reloaded
.push_back(false);
103 return next_spill_id
++;
106 uint32_t next_spill_id
= 0;
109 int32_t get_dominator(int idx_a
, int idx_b
, Program
* program
, bool is_linear
)
117 while (idx_a
!= idx_b
) {
119 idx_a
= program
->blocks
[idx_a
].linear_idom
;
121 idx_b
= program
->blocks
[idx_b
].linear_idom
;
124 while (idx_a
!= idx_b
) {
126 idx_a
= program
->blocks
[idx_a
].logical_idom
;
128 idx_b
= program
->blocks
[idx_b
].logical_idom
;
135 void next_uses_per_block(spill_ctx
& ctx
, unsigned block_idx
, std::set
<uint32_t>& worklist
)
137 Block
* block
= &ctx
.program
->blocks
[block_idx
];
138 std::map
<Temp
, std::pair
<uint32_t, uint32_t>> next_uses
= ctx
.next_use_distances_end
[block_idx
];
140 /* to compute the next use distance at the beginning of the block, we have to add the block's size */
141 for (std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= next_uses
.begin(); it
!= next_uses
.end(); ++it
)
142 it
->second
.second
= it
->second
.second
+ block
->instructions
.size();
144 int idx
= block
->instructions
.size() - 1;
146 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
148 if (instr
->opcode
== aco_opcode::p_linear_phi
||
149 instr
->opcode
== aco_opcode::p_phi
)
152 for (const Definition
& def
: instr
->definitions
) {
154 next_uses
.erase(def
.getTemp());
157 for (const Operand
& op
: instr
->operands
) {
159 if (op
.isFixed() && op
.physReg() == exec
)
161 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
164 next_uses
[op
.getTemp()] = {block_idx
, idx
};
169 assert(block_idx
!= 0 || next_uses
.empty());
170 ctx
.next_use_distances_start
[block_idx
] = next_uses
;
172 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
173 assert(instr
->opcode
== aco_opcode::p_linear_phi
|| instr
->opcode
== aco_opcode::p_phi
);
175 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
176 unsigned pred_idx
= instr
->opcode
== aco_opcode::p_phi
?
177 block
->logical_preds
[i
] :
178 block
->linear_preds
[i
];
179 if (instr
->operands
[i
].isTemp()) {
180 if (instr
->operands
[i
].getTemp() == ctx
.program
->blocks
[pred_idx
].live_out_exec
)
182 if (ctx
.next_use_distances_end
[pred_idx
].find(instr
->operands
[i
].getTemp()) == ctx
.next_use_distances_end
[pred_idx
].end() ||
183 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] != std::pair
<uint32_t, uint32_t>{block_idx
, 0})
184 worklist
.insert(pred_idx
);
185 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] = {block_idx
, 0};
188 next_uses
.erase(instr
->definitions
[0].getTemp());
192 /* all remaining live vars must be live-out at the predecessors */
193 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: next_uses
) {
194 Temp temp
= pair
.first
;
195 uint32_t distance
= pair
.second
.second
;
196 uint32_t dom
= pair
.second
.first
;
197 std::vector
<unsigned>& preds
= temp
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
198 for (unsigned pred_idx
: preds
) {
199 if (temp
== ctx
.program
->blocks
[pred_idx
].live_out_exec
)
201 if (ctx
.program
->blocks
[pred_idx
].loop_nest_depth
> block
->loop_nest_depth
)
203 if (ctx
.next_use_distances_end
[pred_idx
].find(temp
) != ctx
.next_use_distances_end
[pred_idx
].end()) {
204 dom
= get_dominator(dom
, ctx
.next_use_distances_end
[pred_idx
][temp
].first
, ctx
.program
, temp
.is_linear());
205 distance
= std::min(ctx
.next_use_distances_end
[pred_idx
][temp
].second
, distance
);
207 if (ctx
.next_use_distances_end
[pred_idx
][temp
] != std::pair
<uint32_t, uint32_t>{dom
, distance
})
208 worklist
.insert(pred_idx
);
209 ctx
.next_use_distances_end
[pred_idx
][temp
] = {dom
, distance
};
215 void compute_global_next_uses(spill_ctx
& ctx
, std::vector
<std::set
<Temp
>>& live_out
)
217 ctx
.next_use_distances_start
.resize(ctx
.program
->blocks
.size());
218 ctx
.next_use_distances_end
.resize(ctx
.program
->blocks
.size());
219 std::set
<uint32_t> worklist
;
220 for (Block
& block
: ctx
.program
->blocks
)
221 worklist
.insert(block
.index
);
223 while (!worklist
.empty()) {
224 std::set
<unsigned>::reverse_iterator b_it
= worklist
.rbegin();
225 unsigned block_idx
= *b_it
;
226 worklist
.erase(block_idx
);
227 next_uses_per_block(ctx
, block_idx
, worklist
);
231 bool should_rematerialize(aco_ptr
<Instruction
>& instr
)
233 /* TODO: rematerialization is only supported for VOP1, SOP1 and PSEUDO */
234 if (instr
->format
!= Format::VOP1
&& instr
->format
!= Format::SOP1
&& instr
->format
!= Format::PSEUDO
)
236 /* TODO: pseudo-instruction rematerialization is only supported for p_create_vector */
237 if (instr
->format
== Format::PSEUDO
&& instr
->opcode
!= aco_opcode::p_create_vector
)
240 for (const Operand
& op
: instr
->operands
) {
241 /* TODO: rematerialization using temporaries isn't yet supported */
246 /* TODO: rematerialization with multiple definitions isn't yet supported */
247 if (instr
->definitions
.size() > 1)
253 aco_ptr
<Instruction
> do_reload(spill_ctx
& ctx
, Temp tmp
, Temp new_name
, uint32_t spill_id
)
255 std::map
<Temp
, remat_info
>::iterator remat
= ctx
.remat
.find(tmp
);
256 if (remat
!= ctx
.remat
.end()) {
257 Instruction
*instr
= remat
->second
.instr
;
258 assert((instr
->format
== Format::VOP1
|| instr
->format
== Format::SOP1
|| instr
->format
== Format::PSEUDO
) && "unsupported");
259 assert((instr
->format
!= Format::PSEUDO
|| instr
->opcode
== aco_opcode::p_create_vector
) && "unsupported");
260 assert(instr
->definitions
.size() == 1 && "unsupported");
262 aco_ptr
<Instruction
> res
;
263 if (instr
->format
== Format::VOP1
) {
264 res
.reset(create_instruction
<VOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
265 } else if (instr
->format
== Format::SOP1
) {
266 res
.reset(create_instruction
<SOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
267 } else if (instr
->format
== Format::PSEUDO
) {
268 res
.reset(create_instruction
<Instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
270 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
271 res
->operands
[i
] = instr
->operands
[i
];
272 if (instr
->operands
[i
].isTemp()) {
273 assert(false && "unsupported");
274 if (ctx
.remat
.count(instr
->operands
[i
].getTemp()))
275 ctx
.remat_used
[ctx
.remat
[instr
->operands
[i
].getTemp()].instr
] = true;
278 res
->definitions
[0] = Definition(new_name
);
281 aco_ptr
<Pseudo_instruction
> reload
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 1, 1)};
282 reload
->operands
[0] = Operand(spill_id
);
283 reload
->definitions
[0] = Definition(new_name
);
284 ctx
.is_reloaded
[spill_id
] = true;
289 void get_rematerialize_info(spill_ctx
& ctx
)
291 for (Block
& block
: ctx
.program
->blocks
) {
292 bool logical
= false;
293 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
294 if (instr
->opcode
== aco_opcode::p_logical_start
)
296 else if (instr
->opcode
== aco_opcode::p_logical_end
)
298 if (logical
&& should_rematerialize(instr
)) {
299 for (const Definition
& def
: instr
->definitions
) {
301 ctx
.remat
[def
.getTemp()] = (remat_info
){instr
.get()};
302 ctx
.remat_used
[instr
.get()] = false;
310 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(spill_ctx
& ctx
, Block
* block
)
312 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(block
->instructions
.size());
314 std::map
<Temp
, uint32_t> next_uses
;
315 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block
->index
])
316 next_uses
[pair
.first
] = pair
.second
.second
+ block
->instructions
.size();
318 for (int idx
= block
->instructions
.size() - 1; idx
>= 0; idx
--) {
319 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
322 if (instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
)
325 for (const Operand
& op
: instr
->operands
) {
326 if (op
.isFixed() && op
.physReg() == exec
)
328 if (op
.regClass().type() == RegType::vgpr
&& op
.regClass().is_linear())
331 next_uses
[op
.getTemp()] = idx
;
333 for (const Definition
& def
: instr
->definitions
) {
335 next_uses
.erase(def
.getTemp());
337 local_next_uses
[idx
] = next_uses
;
339 return local_next_uses
;
343 RegisterDemand
init_live_in_vars(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
345 RegisterDemand spilled_registers
;
347 /* first block, nothing was spilled before */
351 /* loop header block */
352 if (block
->loop_nest_depth
> ctx
.program
->blocks
[block_idx
- 1].loop_nest_depth
) {
353 assert(block
->linear_preds
[0] == block_idx
- 1);
354 assert(block
->logical_preds
[0] == block_idx
- 1);
356 /* create new loop_info */
357 ctx
.loop_header
.emplace(block
);
359 /* check how many live-through variables should be spilled */
360 RegisterDemand new_demand
;
361 unsigned i
= block_idx
;
362 while (ctx
.program
->blocks
[i
].loop_nest_depth
>= block
->loop_nest_depth
) {
363 assert(ctx
.program
->blocks
.size() > i
);
364 new_demand
.update(ctx
.program
->blocks
[i
].register_demand
);
367 unsigned loop_end
= i
;
369 /* select live-through vgpr variables */
370 while (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
371 unsigned distance
= 0;
373 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
374 if (pair
.first
.type() == RegType::vgpr
&&
375 pair
.second
.first
>= loop_end
&&
376 pair
.second
.second
> distance
&&
377 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
378 to_spill
= pair
.first
;
379 distance
= pair
.second
.second
;
386 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
387 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
389 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
392 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
393 spilled_registers
.vgpr
+= to_spill
.size();
396 /* select live-through sgpr variables */
397 while (new_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
398 unsigned distance
= 0;
400 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
401 if (pair
.first
.type() == RegType::sgpr
&&
402 pair
.second
.first
>= loop_end
&&
403 pair
.second
.second
> distance
&&
404 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
405 to_spill
= pair
.first
;
406 distance
= pair
.second
.second
;
413 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
414 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
416 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
419 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
420 spilled_registers
.sgpr
+= to_spill
.size();
426 if (!RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
))
427 return spilled_registers
;
429 /* if reg pressure is too high at beginning of loop, add variables with furthest use */
431 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
|| block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
)
434 assert(idx
!= 0 && "loop without phis: TODO");
436 RegisterDemand reg_pressure
= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
437 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
438 unsigned distance
= 0;
440 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
441 if (pair
.first
.type() == RegType::sgpr
&&
442 pair
.second
.second
> distance
&&
443 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
444 to_spill
= pair
.first
;
445 distance
= pair
.second
.second
;
448 assert(distance
!= 0);
450 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
451 spilled_registers
.sgpr
+= to_spill
.size();
452 reg_pressure
.sgpr
-= to_spill
.size();
454 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
455 unsigned distance
= 0;
457 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
458 if (pair
.first
.type() == RegType::vgpr
&&
459 pair
.second
.second
> distance
&&
460 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
461 to_spill
= pair
.first
;
462 distance
= pair
.second
.second
;
465 assert(distance
!= 0);
466 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
467 spilled_registers
.vgpr
+= to_spill
.size();
468 reg_pressure
.vgpr
-= to_spill
.size();
471 return spilled_registers
;
475 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
476 /* keep variables spilled if they are alive and not used in the current block */
477 unsigned pred_idx
= block
->linear_preds
[0];
478 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
479 if (pair
.first
.type() == RegType::sgpr
&&
480 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
481 ctx
.next_use_distances_start
[block_idx
][pair
.first
].second
> block_idx
) {
482 ctx
.spills_entry
[block_idx
].insert(pair
);
483 spilled_registers
.sgpr
+= pair
.first
.size();
486 if (block
->logical_preds
.size() == 1) {
487 pred_idx
= block
->logical_preds
[0];
488 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
489 if (pair
.first
.type() == RegType::vgpr
&&
490 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
491 ctx
.next_use_distances_start
[block_idx
][pair
.first
].second
> block_idx
) {
492 ctx
.spills_entry
[block_idx
].insert(pair
);
493 spilled_registers
.vgpr
+= pair
.first
.size();
498 /* if register demand is still too high, we just keep all spilled live vars and process the block */
499 if (block
->register_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
500 pred_idx
= block
->linear_preds
[0];
501 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
502 if (pair
.first
.type() == RegType::sgpr
&&
503 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
504 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
505 spilled_registers
.sgpr
+= pair
.first
.size();
509 if (block
->register_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
&& block
->logical_preds
.size() == 1) {
510 pred_idx
= block
->logical_preds
[0];
511 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
512 if (pair
.first
.type() == RegType::vgpr
&&
513 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
514 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
515 spilled_registers
.vgpr
+= pair
.first
.size();
520 return spilled_registers
;
523 /* else: merge block */
524 std::set
<Temp
> partial_spills
;
526 /* keep variables spilled on all incoming paths */
527 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
528 std::vector
<unsigned>& preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
529 /* If it can be rematerialized, keep the variable spilled if all predecessors do not reload it.
530 * Otherwise, if any predecessor reloads it, ensure it's reloaded on all other predecessors.
531 * The idea is that it's better in practice to rematerialize redundantly than to create lots of phis. */
532 /* TODO: test this idea with more than Dawn of War III shaders (the current pipeline-db doesn't seem to exercise this path much) */
533 bool remat
= ctx
.remat
.count(pair
.first
);
535 uint32_t spill_id
= 0;
536 for (unsigned pred_idx
: preds
) {
537 /* variable is not even live at the predecessor: probably from a phi */
538 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end()) {
542 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
546 partial_spills
.insert(pair
.first
);
547 /* it might be that on one incoming path, the variable has a different spill_id, but add_couple_code() will take care of that. */
548 spill_id
= ctx
.spills_exit
[pred_idx
][pair
.first
];
554 ctx
.spills_entry
[block_idx
][pair
.first
] = spill_id
;
555 partial_spills
.erase(pair
.first
);
556 spilled_registers
+= pair
.first
;
562 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
||
563 block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
) {
564 aco_ptr
<Instruction
>& phi
= block
->instructions
[idx
];
565 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
568 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
569 if (phi
->operands
[i
].isUndefined())
571 assert(phi
->operands
[i
].isTemp());
572 if (ctx
.spills_exit
[preds
[i
]].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[preds
[i
]].end())
575 partial_spills
.insert(phi
->definitions
[0].getTemp());
578 ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()] = ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
579 partial_spills
.erase(phi
->definitions
[0].getTemp());
580 spilled_registers
+= phi
->definitions
[0].getTemp();
586 /* if reg pressure at first instruction is still too high, add partially spilled variables */
587 RegisterDemand reg_pressure
;
589 for (const Definition
& def
: block
->instructions
[idx
]->definitions
) {
591 reg_pressure
-= def
.getTemp();
594 for (const Operand
& op
: block
->instructions
[idx
]->operands
) {
595 if (op
.isTemp() && op
.isFirstKill()) {
596 reg_pressure
+= op
.getTemp();
602 reg_pressure
+= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
604 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
605 assert(!partial_spills
.empty());
607 std::set
<Temp
>::iterator it
= partial_spills
.begin();
609 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
610 while (it
!= partial_spills
.end()) {
611 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
613 if (it
->type() == RegType::sgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
614 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
619 assert(distance
!= 0);
621 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
622 partial_spills
.erase(to_spill
);
623 spilled_registers
.sgpr
+= to_spill
.size();
624 reg_pressure
.sgpr
-= to_spill
.size();
627 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
628 assert(!partial_spills
.empty());
630 std::set
<Temp
>::iterator it
= partial_spills
.begin();
632 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
633 while (it
!= partial_spills
.end()) {
634 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
636 if (it
->type() == RegType::vgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
637 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
642 assert(distance
!= 0);
644 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
645 partial_spills
.erase(to_spill
);
646 spilled_registers
.vgpr
+= to_spill
.size();
647 reg_pressure
.vgpr
-= to_spill
.size();
650 return spilled_registers
;
654 void add_coupling_code(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
656 /* no coupling code necessary */
657 if (block
->linear_preds
.size() == 0)
660 std::vector
<aco_ptr
<Instruction
>> instructions
;
661 /* branch block: TODO take other branch into consideration */
662 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
663 assert(ctx
.processed
[block
->linear_preds
[0]]);
664 assert(ctx
.register_demand
[block_idx
].size() == block
->instructions
.size());
665 std::vector
<RegisterDemand
> reg_demand
;
666 unsigned insert_idx
= 0;
667 unsigned pred_idx
= block
->linear_preds
[0];
669 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
670 if (!live
.first
.is_linear())
673 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
676 /* in register at end of predecessor */
677 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
678 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
679 if (it
!= ctx
.renames
[pred_idx
].end())
680 ctx
.renames
[block_idx
].insert(*it
);
684 /* variable is spilled at predecessor and live at current block: create reload instruction */
685 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
686 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
687 instructions
.emplace_back(std::move(reload
));
688 reg_demand
.push_back(RegisterDemand());
689 ctx
.renames
[block_idx
][live
.first
] = new_name
;
692 if (block
->logical_preds
.size() == 1) {
694 assert(insert_idx
< block
->instructions
.size());
695 instructions
.emplace_back(std::move(block
->instructions
[insert_idx
]));
696 reg_demand
.push_back(ctx
.register_demand
[block_idx
][insert_idx
]);
698 } while (instructions
.back()->opcode
!= aco_opcode::p_logical_start
);
700 unsigned pred_idx
= block
->logical_preds
[0];
701 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
702 if (live
.first
.is_linear())
705 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
708 /* in register at end of predecessor */
709 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
710 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
711 if (it
!= ctx
.renames
[pred_idx
].end())
712 ctx
.renames
[block_idx
].insert(*it
);
716 /* variable is spilled at predecessor and live at current block: create reload instruction */
717 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
718 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
719 instructions
.emplace_back(std::move(reload
));
720 reg_demand
.emplace_back(reg_demand
.back());
721 ctx
.renames
[block_idx
][live
.first
] = new_name
;
725 /* combine new reload instructions with original block */
726 if (!instructions
.empty()) {
727 reg_demand
.insert(reg_demand
.end(), std::next(ctx
.register_demand
[block
->index
].begin(), insert_idx
),
728 ctx
.register_demand
[block
->index
].end());
729 ctx
.register_demand
[block_idx
] = std::move(reg_demand
);
730 instructions
.insert(instructions
.end(),
731 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(std::next(block
->instructions
.begin(), insert_idx
)),
732 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
733 block
->instructions
= std::move(instructions
);
738 /* loop header and merge blocks: check if all (linear) predecessors have been processed */
739 for (ASSERTED
unsigned pred
: block
->linear_preds
)
740 assert(ctx
.processed
[pred
]);
742 /* iterate the phi nodes for which operands to spill at the predecessor */
743 for (aco_ptr
<Instruction
>& phi
: block
->instructions
) {
744 if (phi
->opcode
!= aco_opcode::p_phi
&&
745 phi
->opcode
!= aco_opcode::p_linear_phi
)
748 /* if the phi is not spilled, add to instructions */
749 if (ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end()) {
750 instructions
.emplace_back(std::move(phi
));
754 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
755 uint32_t def_spill_id
= ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()];
757 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
758 if (phi
->operands
[i
].isUndefined())
761 unsigned pred_idx
= preds
[i
];
762 assert(phi
->operands
[i
].isTemp() && phi
->operands
[i
].isKill());
763 Temp var
= phi
->operands
[i
].getTemp();
765 /* build interferences between the phi def and all spilled variables at the predecessor blocks */
766 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
767 if (var
== pair
.first
)
769 ctx
.interferences
[def_spill_id
].second
.emplace(pair
.second
);
770 ctx
.interferences
[pair
.second
].second
.emplace(def_spill_id
);
773 /* check if variable is already spilled at predecessor */
774 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(var
);
775 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
776 if (spilled
->second
!= def_spill_id
)
777 ctx
.add_affinity(def_spill_id
, spilled
->second
);
781 /* rename if necessary */
782 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
783 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
784 var
= rename_it
->second
;
785 ctx
.renames
[pred_idx
].erase(rename_it
);
788 uint32_t spill_id
= ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
789 ctx
.add_affinity(def_spill_id
, spill_id
);
790 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
791 spill
->operands
[0] = Operand(var
);
792 spill
->operands
[1] = Operand(spill_id
);
793 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
794 unsigned idx
= pred
.instructions
.size();
798 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
799 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
800 pred
.instructions
.insert(it
, std::move(spill
));
801 ctx
.spills_exit
[pred_idx
][phi
->operands
[i
].getTemp()] = spill_id
;
804 /* remove phi from instructions */
808 /* iterate all (other) spilled variables for which to spill at the predecessor */
809 // TODO: would be better to have them sorted: first vgprs and first with longest distance
810 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_entry
[block_idx
]) {
811 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
813 for (unsigned pred_idx
: preds
) {
814 /* variable is already spilled at predecessor */
815 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(pair
.first
);
816 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
817 if (spilled
->second
!= pair
.second
)
818 ctx
.add_affinity(pair
.second
, spilled
->second
);
822 /* variable is dead at predecessor, it must be from a phi: this works because of CSSA form */
823 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
826 /* add interferences between spilled variable and predecessors exit spills */
827 for (std::pair
<Temp
, uint32_t> exit_spill
: ctx
.spills_exit
[pred_idx
]) {
828 if (exit_spill
.first
== pair
.first
)
830 ctx
.interferences
[exit_spill
.second
].second
.emplace(pair
.second
);
831 ctx
.interferences
[pair
.second
].second
.emplace(exit_spill
.second
);
834 /* variable is in register at predecessor and has to be spilled */
835 /* rename if necessary */
836 Temp var
= pair
.first
;
837 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
838 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
839 var
= rename_it
->second
;
840 ctx
.renames
[pred_idx
].erase(rename_it
);
843 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
844 spill
->operands
[0] = Operand(var
);
845 spill
->operands
[1] = Operand(pair
.second
);
846 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
847 unsigned idx
= pred
.instructions
.size();
851 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
852 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
853 pred
.instructions
.insert(it
, std::move(spill
));
854 ctx
.spills_exit
[pred
.index
][pair
.first
] = pair
.second
;
858 /* iterate phis for which operands to reload */
859 for (aco_ptr
<Instruction
>& phi
: instructions
) {
860 assert(phi
->opcode
== aco_opcode::p_phi
|| phi
->opcode
== aco_opcode::p_linear_phi
);
861 assert(ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end());
863 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
864 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
865 if (!phi
->operands
[i
].isTemp())
867 unsigned pred_idx
= preds
[i
];
870 if (ctx
.spills_exit
[pred_idx
].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[pred_idx
].end()) {
871 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(phi
->operands
[i
].getTemp());
872 if (it
!= ctx
.renames
[pred_idx
].end())
873 phi
->operands
[i
].setTemp(it
->second
);
877 Temp tmp
= phi
->operands
[i
].getTemp();
879 /* reload phi operand at end of predecessor block */
880 Temp new_name
= {ctx
.program
->allocateId(), tmp
.regClass()};
881 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
882 unsigned idx
= pred
.instructions
.size();
886 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
887 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
889 aco_ptr
<Instruction
> reload
= do_reload(ctx
, tmp
, new_name
, ctx
.spills_exit
[pred_idx
][tmp
]);
890 pred
.instructions
.insert(it
, std::move(reload
));
892 ctx
.spills_exit
[pred_idx
].erase(tmp
);
893 ctx
.renames
[pred_idx
][tmp
] = new_name
;
894 phi
->operands
[i
].setTemp(new_name
);
898 /* iterate live variables for which to reload */
899 // TODO: reload at current block if variable is spilled on all predecessors
900 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
901 /* skip spilled variables */
902 if (ctx
.spills_entry
[block_idx
].find(pair
.first
) != ctx
.spills_entry
[block_idx
].end())
904 std::vector
<unsigned> preds
= pair
.first
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
906 /* variable is dead at predecessor, it must be from a phi */
907 bool is_dead
= false;
908 for (unsigned pred_idx
: preds
) {
909 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
914 for (unsigned pred_idx
: preds
) {
915 /* the variable is not spilled at the predecessor */
916 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end())
919 /* variable is spilled at predecessor and has to be reloaded */
920 Temp new_name
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
921 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
922 unsigned idx
= pred
.instructions
.size();
926 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
927 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
929 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.first
, new_name
, ctx
.spills_exit
[pred
.index
][pair
.first
]);
930 pred
.instructions
.insert(it
, std::move(reload
));
932 ctx
.spills_exit
[pred
.index
].erase(pair
.first
);
933 ctx
.renames
[pred
.index
][pair
.first
] = new_name
;
936 /* check if we have to create a new phi for this variable */
937 Temp rename
= Temp();
939 for (unsigned pred_idx
: preds
) {
940 if (ctx
.renames
[pred_idx
].find(pair
.first
) == ctx
.renames
[pred_idx
].end()) {
941 if (rename
== Temp())
944 is_same
= rename
== pair
.first
;
946 if (rename
== Temp())
947 rename
= ctx
.renames
[pred_idx
][pair
.first
];
949 is_same
= rename
== ctx
.renames
[pred_idx
][pair
.first
];
957 /* the variable was renamed differently in the predecessors: we have to create a phi */
958 aco_opcode opcode
= pair
.first
.is_linear() ? aco_opcode::p_linear_phi
: aco_opcode::p_phi
;
959 aco_ptr
<Pseudo_instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
960 rename
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
961 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
963 if (ctx
.renames
[preds
[i
]].find(pair
.first
) != ctx
.renames
[preds
[i
]].end())
964 tmp
= ctx
.renames
[preds
[i
]][pair
.first
];
965 else if (preds
[i
] >= block_idx
)
969 phi
->operands
[i
] = Operand(tmp
);
971 phi
->definitions
[0] = Definition(rename
);
972 instructions
.emplace_back(std::move(phi
));
975 /* the variable was renamed: add new name to renames */
976 if (!(rename
== Temp() || rename
== pair
.first
))
977 ctx
.renames
[block_idx
][pair
.first
] = rename
;
980 /* combine phis with instructions */
982 while (!block
->instructions
[idx
]) {
986 ctx
.register_demand
[block
->index
].erase(ctx
.register_demand
[block
->index
].begin(), ctx
.register_demand
[block
->index
].begin() + idx
);
987 ctx
.register_demand
[block
->index
].insert(ctx
.register_demand
[block
->index
].begin(), instructions
.size(), RegisterDemand());
989 std::vector
<aco_ptr
<Instruction
>>::iterator start
= std::next(block
->instructions
.begin(), idx
);
990 instructions
.insert(instructions
.end(), std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(start
),
991 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
992 block
->instructions
= std::move(instructions
);
995 void process_block(spill_ctx
& ctx
, unsigned block_idx
, Block
* block
,
996 std::map
<Temp
, uint32_t> ¤t_spills
, RegisterDemand spilled_registers
)
998 std::vector
<std::map
<Temp
, uint32_t>> local_next_use_distance
;
999 std::vector
<aco_ptr
<Instruction
>> instructions
;
1002 /* phis are handled separetely */
1003 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
||
1004 block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
) {
1005 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1006 for (const Operand
& op
: instr
->operands
) {
1007 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1008 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1009 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1011 instructions
.emplace_back(std::move(instr
));
1015 if (block
->register_demand
.exceeds(ctx
.target_pressure
))
1016 local_next_use_distance
= local_next_uses(ctx
, block
);
1018 while (idx
< block
->instructions
.size()) {
1019 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1021 std::map
<Temp
, std::pair
<Temp
, uint32_t>> reloads
;
1022 std::map
<Temp
, uint32_t> spills
;
1023 /* rename and reload operands */
1024 for (Operand
& op
: instr
->operands
) {
1027 if (current_spills
.find(op
.getTemp()) == current_spills
.end()) {
1028 /* the Operand is in register: check if it was renamed */
1029 if (ctx
.renames
[block_idx
].find(op
.getTemp()) != ctx
.renames
[block_idx
].end())
1030 op
.setTemp(ctx
.renames
[block_idx
][op
.getTemp()]);
1031 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1032 if (ctx
.remat
.count(op
.getTemp()))
1033 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1036 /* the Operand is spilled: add it to reloads */
1037 Temp new_tmp
= {ctx
.program
->allocateId(), op
.regClass()};
1038 ctx
.renames
[block_idx
][op
.getTemp()] = new_tmp
;
1039 reloads
[new_tmp
] = std::make_pair(op
.getTemp(), current_spills
[op
.getTemp()]);
1040 current_spills
.erase(op
.getTemp());
1041 op
.setTemp(new_tmp
);
1042 spilled_registers
-= new_tmp
;
1045 /* check if register demand is low enough before and after the current instruction */
1046 if (block
->register_demand
.exceeds(ctx
.target_pressure
)) {
1048 RegisterDemand new_demand
= ctx
.register_demand
[block_idx
][idx
];
1050 RegisterDemand demand_before
= new_demand
;
1051 for (const Definition
& def
: instr
->definitions
)
1052 demand_before
-= def
.getTemp();
1053 for (const Operand
& op
: instr
->operands
) {
1054 if (op
.isFirstKill())
1055 demand_before
+= op
.getTemp();
1057 new_demand
.update(demand_before
);
1059 new_demand
.update(ctx
.register_demand
[block_idx
][idx
- 1]);
1062 assert(!local_next_use_distance
.empty());
1064 /* if reg pressure is too high, spill variable with furthest next use */
1065 while (RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
)) {
1066 unsigned distance
= 0;
1068 bool do_rematerialize
= false;
1069 if (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
1070 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1071 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1072 if (pair
.first
.type() == RegType::vgpr
&&
1073 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1074 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1075 current_spills
.find(pair
.first
) == current_spills
.end() &&
1076 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1077 to_spill
= pair
.first
;
1078 distance
= pair
.second
;
1079 do_rematerialize
= can_rematerialize
;
1083 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1084 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1085 if (pair
.first
.type() == RegType::sgpr
&&
1086 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1087 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1088 current_spills
.find(pair
.first
) == current_spills
.end() &&
1089 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1090 to_spill
= pair
.first
;
1091 distance
= pair
.second
;
1092 do_rematerialize
= can_rematerialize
;
1097 assert(distance
!= 0 && distance
> idx
);
1098 uint32_t spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
1100 /* add interferences with currently spilled variables */
1101 for (std::pair
<Temp
, uint32_t> pair
: current_spills
) {
1102 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
);
1103 ctx
.interferences
[pair
.second
].second
.emplace(spill_id
);
1105 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1106 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
.second
);
1107 ctx
.interferences
[pair
.second
.second
].second
.emplace(spill_id
);
1110 current_spills
[to_spill
] = spill_id
;
1111 spilled_registers
+= to_spill
;
1113 /* rename if necessary */
1114 if (ctx
.renames
[block_idx
].find(to_spill
) != ctx
.renames
[block_idx
].end()) {
1115 to_spill
= ctx
.renames
[block_idx
][to_spill
];
1118 /* add spill to new instructions */
1119 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
1120 spill
->operands
[0] = Operand(to_spill
);
1121 spill
->operands
[1] = Operand(spill_id
);
1122 instructions
.emplace_back(std::move(spill
));
1126 /* add reloads and instruction to new instructions */
1127 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1128 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.second
.first
, pair
.first
, pair
.second
.second
);
1129 instructions
.emplace_back(std::move(reload
));
1131 instructions
.emplace_back(std::move(instr
));
1135 block
->instructions
= std::move(instructions
);
1136 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1139 void spill_block(spill_ctx
& ctx
, unsigned block_idx
)
1141 Block
* block
= &ctx
.program
->blocks
[block_idx
];
1142 ctx
.processed
[block_idx
] = true;
1144 /* determine set of variables which are spilled at the beginning of the block */
1145 RegisterDemand spilled_registers
= init_live_in_vars(ctx
, block
, block_idx
);
1147 /* add interferences for spilled variables */
1148 for (std::pair
<Temp
, uint32_t> x
: ctx
.spills_entry
[block_idx
]) {
1149 for (std::pair
<Temp
, uint32_t> y
: ctx
.spills_entry
[block_idx
])
1150 if (x
.second
!= y
.second
)
1151 ctx
.interferences
[x
.second
].second
.emplace(y
.second
);
1154 bool is_loop_header
= block
->loop_nest_depth
&& ctx
.loop_header
.top()->index
== block_idx
;
1155 if (!is_loop_header
) {
1156 /* add spill/reload code on incoming control flow edges */
1157 add_coupling_code(ctx
, block
, block_idx
);
1160 std::map
<Temp
, uint32_t> current_spills
= ctx
.spills_entry
[block_idx
];
1162 /* check conditions to process this block */
1163 bool process
= RegisterDemand(block
->register_demand
- spilled_registers
).exceeds(ctx
.target_pressure
) ||
1164 !ctx
.renames
[block_idx
].empty() ||
1165 ctx
.remat_used
.size();
1167 std::map
<Temp
, uint32_t>::iterator it
= current_spills
.begin();
1168 while (!process
&& it
!= current_spills
.end()) {
1169 if (ctx
.next_use_distances_start
[block_idx
][it
->first
].first
== block_idx
)
1175 process_block(ctx
, block_idx
, block
, current_spills
, spilled_registers
);
1177 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1179 /* check if the next block leaves the current loop */
1180 if (block
->loop_nest_depth
== 0 || ctx
.program
->blocks
[block_idx
+ 1].loop_nest_depth
>= block
->loop_nest_depth
)
1183 Block
* loop_header
= ctx
.loop_header
.top();
1185 /* preserve original renames at end of loop header block */
1186 std::map
<Temp
, Temp
> renames
= std::move(ctx
.renames
[loop_header
->index
]);
1188 /* add coupling code to all loop header predecessors */
1189 add_coupling_code(ctx
, loop_header
, loop_header
->index
);
1191 /* update remat_used for phis added in add_coupling_code() */
1192 for (aco_ptr
<Instruction
>& instr
: loop_header
->instructions
) {
1195 for (const Operand
& op
: instr
->operands
) {
1196 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1197 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1201 /* propagate new renames through loop: i.e. repair the SSA */
1202 renames
.swap(ctx
.renames
[loop_header
->index
]);
1203 for (std::pair
<Temp
, Temp
> rename
: renames
) {
1204 for (unsigned idx
= loop_header
->index
; idx
<= block_idx
; idx
++) {
1205 Block
& current
= ctx
.program
->blocks
[idx
];
1206 std::vector
<aco_ptr
<Instruction
>>::iterator instr_it
= current
.instructions
.begin();
1208 /* first rename phis */
1209 while (instr_it
!= current
.instructions
.end()) {
1210 aco_ptr
<Instruction
>& phi
= *instr_it
;
1211 if (phi
->opcode
!= aco_opcode::p_phi
&& phi
->opcode
!= aco_opcode::p_linear_phi
)
1213 /* no need to rename the loop header phis once again. this happened in add_coupling_code() */
1214 if (idx
== loop_header
->index
) {
1219 for (Operand
& op
: phi
->operands
) {
1222 if (op
.getTemp() == rename
.first
)
1223 op
.setTemp(rename
.second
);
1228 std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= ctx
.next_use_distances_start
[idx
].find(rename
.first
);
1230 /* variable is not live at beginning of this block */
1231 if (it
== ctx
.next_use_distances_start
[idx
].end())
1234 /* if the variable is live at the block's exit, add rename */
1235 if (ctx
.next_use_distances_end
[idx
].find(rename
.first
) != ctx
.next_use_distances_end
[idx
].end())
1236 ctx
.renames
[idx
].insert(rename
);
1238 /* rename all uses in this block */
1239 bool renamed
= false;
1240 while (!renamed
&& instr_it
!= current
.instructions
.end()) {
1241 aco_ptr
<Instruction
>& instr
= *instr_it
;
1242 for (Operand
& op
: instr
->operands
) {
1245 if (op
.getTemp() == rename
.first
) {
1246 op
.setTemp(rename
.second
);
1247 /* we can stop with this block as soon as the variable is spilled */
1248 if (instr
->opcode
== aco_opcode::p_spill
)
1257 /* remove loop header info from stack */
1258 ctx
.loop_header
.pop();
1261 Temp
load_scratch_resource(spill_ctx
& ctx
, Temp
& scratch_offset
,
1262 std::vector
<aco_ptr
<Instruction
>>& instructions
,
1263 unsigned offset
, bool is_top_level
)
1265 Builder
bld(ctx
.program
);
1267 bld
.reset(&instructions
);
1269 /* find p_logical_end */
1270 unsigned idx
= instructions
.size() - 1;
1271 while (instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
)
1273 bld
.reset(&instructions
, std::next(instructions
.begin(), idx
));
1276 Temp private_segment_buffer
= ctx
.program
->private_segment_buffer
;
1277 if (ctx
.program
->stage
!= compute_cs
)
1278 private_segment_buffer
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, Operand(0u));
1281 scratch_offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), scratch_offset
, Operand(offset
));
1283 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
1284 S_008F0C_INDEX_STRIDE(ctx
.program
->wave_size
== 64 ? 3 : 2);
1286 if (ctx
.program
->chip_class
>= GFX10
) {
1287 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1288 S_008F0C_OOB_SELECT(3) |
1289 S_008F0C_RESOURCE_LEVEL(1);
1290 } else if (ctx
.program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
1291 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1292 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1294 /* older generations need element size = 4 bytes. element size removed in GFX9 */
1295 if (ctx
.program
->chip_class
<= GFX8
)
1296 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
1298 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
1299 private_segment_buffer
, Operand(-1u),
1300 Operand(rsrc_conf
));
1303 void assign_spill_slots(spill_ctx
& ctx
, unsigned spills_to_vgpr
) {
1304 std::map
<uint32_t, uint32_t> sgpr_slot
;
1305 std::map
<uint32_t, uint32_t> vgpr_slot
;
1306 std::vector
<bool> is_assigned(ctx
.interferences
.size());
1308 /* first, handle affinities: just merge all interferences into both spill ids */
1309 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1310 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1311 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1312 assert(vec
[i
] != vec
[j
]);
1313 for (uint32_t id
: ctx
.interferences
[vec
[i
]].second
)
1314 ctx
.interferences
[id
].second
.insert(vec
[j
]);
1315 for (uint32_t id
: ctx
.interferences
[vec
[j
]].second
)
1316 ctx
.interferences
[id
].second
.insert(vec
[i
]);
1317 ctx
.interferences
[vec
[i
]].second
.insert(ctx
.interferences
[vec
[j
]].second
.begin(), ctx
.interferences
[vec
[j
]].second
.end());
1318 ctx
.interferences
[vec
[j
]].second
.insert(ctx
.interferences
[vec
[i
]].second
.begin(), ctx
.interferences
[vec
[i
]].second
.end());
1320 bool reloaded
= ctx
.is_reloaded
[vec
[i
]] || ctx
.is_reloaded
[vec
[j
]];
1321 ctx
.is_reloaded
[vec
[i
]] = reloaded
;
1322 ctx
.is_reloaded
[vec
[j
]] = reloaded
;
1326 for (ASSERTED
uint32_t i
= 0; i
< ctx
.interferences
.size(); i
++)
1327 for (ASSERTED
uint32_t id
: ctx
.interferences
[i
].second
)
1330 /* for each spill slot, assign as many spill ids as possible */
1331 std::vector
<std::set
<uint32_t>> spill_slot_interferences
;
1332 unsigned slot_idx
= 0;
1335 /* assign sgpr spill slots */
1338 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1339 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1341 if (ctx
.interferences
[id
].first
.type() != RegType::sgpr
)
1344 /* check interferences */
1345 bool interferes
= false;
1346 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1347 if (i
== spill_slot_interferences
.size())
1348 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1349 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end() || i
/ 64 != slot_idx
/ 64) {
1359 /* we found a spill id which can be assigned to current spill slot */
1360 sgpr_slot
[id
] = slot_idx
;
1361 is_assigned
[id
] = true;
1362 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1363 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1365 /* add all affinities: there are no additional interferences */
1366 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1367 bool found_affinity
= false;
1368 for (uint32_t entry
: vec
) {
1370 found_affinity
= true;
1374 if (!found_affinity
)
1376 for (uint32_t entry
: vec
) {
1377 sgpr_slot
[entry
] = slot_idx
;
1378 is_assigned
[entry
] = true;
1385 unsigned sgpr_spill_slots
= spill_slot_interferences
.size();
1386 spill_slot_interferences
.clear();
1390 /* assign vgpr spill slots */
1393 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1394 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1396 if (ctx
.interferences
[id
].first
.type() != RegType::vgpr
)
1399 /* check interferences */
1400 bool interferes
= false;
1401 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1402 if (i
== spill_slot_interferences
.size())
1403 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1404 /* check for interference and ensure that vector regs are stored next to each other */
1405 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end()) {
1415 /* we found a spill id which can be assigned to current spill slot */
1416 vgpr_slot
[id
] = slot_idx
;
1417 is_assigned
[id
] = true;
1418 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1419 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1421 /* add all affinities: there are no additional interferences */
1422 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1423 bool found_affinity
= false;
1424 for (uint32_t entry
: vec
) {
1426 found_affinity
= true;
1430 if (!found_affinity
)
1432 for (uint32_t entry
: vec
) {
1433 vgpr_slot
[entry
] = slot_idx
;
1434 is_assigned
[entry
] = true;
1441 unsigned vgpr_spill_slots
= spill_slot_interferences
.size();
1443 for (unsigned id
= 0; id
< is_assigned
.size(); id
++)
1444 assert(is_assigned
[id
] || !ctx
.is_reloaded
[id
]);
1446 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1447 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1448 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1449 assert(is_assigned
[vec
[i
]] == is_assigned
[vec
[j
]]);
1450 if (!is_assigned
[vec
[i
]])
1452 assert(ctx
.is_reloaded
[vec
[i
]] == ctx
.is_reloaded
[vec
[j
]]);
1453 assert(ctx
.interferences
[vec
[i
]].first
.type() == ctx
.interferences
[vec
[j
]].first
.type());
1454 if (ctx
.interferences
[vec
[i
]].first
.type() == RegType::sgpr
)
1455 assert(sgpr_slot
[vec
[i
]] == sgpr_slot
[vec
[j
]]);
1457 assert(vgpr_slot
[vec
[i
]] == vgpr_slot
[vec
[j
]]);
1462 /* hope, we didn't mess up */
1463 std::vector
<Temp
> vgpr_spill_temps((sgpr_spill_slots
+ 63) / 64);
1464 assert(vgpr_spill_temps
.size() <= spills_to_vgpr
);
1466 /* replace pseudo instructions with actual hardware instructions */
1467 Temp scratch_offset
= ctx
.program
->scratch_offset
, scratch_rsrc
= Temp();
1468 unsigned last_top_level_block_idx
= 0;
1469 std::vector
<bool> reload_in_loop(vgpr_spill_temps
.size());
1470 for (Block
& block
: ctx
.program
->blocks
) {
1472 /* after loops, we insert a user if there was a reload inside the loop */
1473 if (block
.loop_nest_depth
== 0) {
1475 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1476 if (reload_in_loop
[i
])
1480 if (end_vgprs
> 0) {
1481 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, end_vgprs
, 0)};
1483 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1484 if (reload_in_loop
[i
])
1485 destr
->operands
[k
++] = Operand(vgpr_spill_temps
[i
]);
1486 reload_in_loop
[i
] = false;
1488 /* find insertion point */
1489 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1490 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1492 block
.instructions
.insert(it
, std::move(destr
));
1496 if (block
.kind
& block_kind_top_level
&& !block
.linear_preds
.empty()) {
1497 last_top_level_block_idx
= block
.index
;
1499 /* check if any spilled variables use a created linear vgpr, otherwise destroy them */
1500 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1501 if (vgpr_spill_temps
[i
] == Temp())
1504 bool can_destroy
= true;
1505 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[block
.linear_preds
[0]]) {
1507 if (sgpr_slot
.find(pair
.second
) != sgpr_slot
.end() &&
1508 sgpr_slot
[pair
.second
] / 64 == i
) {
1509 can_destroy
= false;
1514 vgpr_spill_temps
[i
] = Temp();
1518 std::vector
<aco_ptr
<Instruction
>>::iterator it
;
1519 std::vector
<aco_ptr
<Instruction
>> instructions
;
1520 instructions
.reserve(block
.instructions
.size());
1521 Builder
bld(ctx
.program
, &instructions
);
1522 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1524 if ((*it
)->opcode
== aco_opcode::p_spill
) {
1525 uint32_t spill_id
= (*it
)->operands
[1].constantValue();
1527 if (!ctx
.is_reloaded
[spill_id
]) {
1528 /* never reloaded, so don't spill */
1529 } else if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1531 ctx
.program
->config
->spilled_vgprs
+= (*it
)->operands
[0].size();
1532 uint32_t spill_slot
= vgpr_slot
[spill_id
];
1533 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1534 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1536 /* check if the scratch resource descriptor already exists */
1537 if (scratch_rsrc
== Temp()) {
1538 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1539 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1540 last_top_level_block_idx
== block
.index
?
1541 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1543 last_top_level_block_idx
== block
.index
);
1546 unsigned offset
= base_offset
+ spill_slot
* 4;
1547 aco_opcode opcode
= aco_opcode::buffer_store_dword
;
1548 assert((*it
)->operands
[0].isTemp());
1549 Temp temp
= (*it
)->operands
[0].getTemp();
1550 assert(temp
.type() == RegType::vgpr
&& !temp
.is_linear());
1551 if (temp
.size() > 1) {
1552 Instruction
* split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, temp
.size())};
1553 split
->operands
[0] = Operand(temp
);
1554 for (unsigned i
= 0; i
< temp
.size(); i
++)
1555 split
->definitions
[i
] = bld
.def(v1
);
1557 for (unsigned i
= 0; i
< temp
.size(); i
++)
1558 bld
.mubuf(opcode
, Operand(), scratch_rsrc
, scratch_offset
, split
->definitions
[i
].getTemp(), offset
+ i
* 4, false);
1560 bld
.mubuf(opcode
, Operand(), scratch_rsrc
, scratch_offset
, temp
, offset
, false);
1562 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1563 ctx
.program
->config
->spilled_sgprs
+= (*it
)->operands
[0].size();
1565 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1567 /* check if the linear vgpr already exists */
1568 if (vgpr_spill_temps
[spill_slot
/ 64] == Temp()) {
1569 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1570 vgpr_spill_temps
[spill_slot
/ 64] = linear_vgpr
;
1571 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1572 create
->definitions
[0] = Definition(linear_vgpr
);
1573 /* find the right place to insert this definition */
1574 if (last_top_level_block_idx
== block
.index
) {
1575 /* insert right before the current instruction */
1576 instructions
.emplace_back(std::move(create
));
1578 assert(last_top_level_block_idx
< block
.index
);
1579 /* insert before the branch at last top level block */
1580 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1581 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1585 /* spill sgpr: just add the vgpr temp to operands */
1586 Pseudo_instruction
* spill
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 3, 0);
1587 spill
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ 64]);
1588 spill
->operands
[1] = Operand(spill_slot
% 64);
1589 spill
->operands
[2] = (*it
)->operands
[0];
1590 instructions
.emplace_back(aco_ptr
<Instruction
>(spill
));
1592 unreachable("No spill slot assigned for spill id");
1595 } else if ((*it
)->opcode
== aco_opcode::p_reload
) {
1596 uint32_t spill_id
= (*it
)->operands
[0].constantValue();
1597 assert(ctx
.is_reloaded
[spill_id
]);
1599 if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1601 uint32_t spill_slot
= vgpr_slot
[spill_id
];
1602 bool add_offset_to_sgpr
= ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
+ vgpr_spill_slots
* 4 > 4096;
1603 unsigned base_offset
= add_offset_to_sgpr
? 0 : ctx
.program
->config
->scratch_bytes_per_wave
/ ctx
.program
->wave_size
;
1605 /* check if the scratch resource descriptor already exists */
1606 if (scratch_rsrc
== Temp()) {
1607 unsigned offset
= add_offset_to_sgpr
? ctx
.program
->config
->scratch_bytes_per_wave
: 0;
1608 scratch_rsrc
= load_scratch_resource(ctx
, scratch_offset
,
1609 last_top_level_block_idx
== block
.index
?
1610 instructions
: ctx
.program
->blocks
[last_top_level_block_idx
].instructions
,
1612 last_top_level_block_idx
== block
.index
);
1615 unsigned offset
= base_offset
+ spill_slot
* 4;
1616 aco_opcode opcode
= aco_opcode::buffer_load_dword
;
1617 Definition def
= (*it
)->definitions
[0];
1618 if (def
.size() > 1) {
1619 Instruction
* vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, def
.size(), 1)};
1620 vec
->definitions
[0] = def
;
1621 for (unsigned i
= 0; i
< def
.size(); i
++) {
1622 Temp tmp
= bld
.tmp(v1
);
1623 vec
->operands
[i
] = Operand(tmp
);
1624 bld
.mubuf(opcode
, Definition(tmp
), Operand(), scratch_rsrc
, scratch_offset
, offset
+ i
* 4, false);
1628 bld
.mubuf(opcode
, def
, Operand(), scratch_rsrc
, scratch_offset
, offset
, false);
1630 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1631 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1632 reload_in_loop
[spill_slot
/ 64] = block
.loop_nest_depth
> 0;
1634 /* check if the linear vgpr already exists */
1635 if (vgpr_spill_temps
[spill_slot
/ 64] == Temp()) {
1636 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1637 vgpr_spill_temps
[spill_slot
/ 64] = linear_vgpr
;
1638 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1639 create
->definitions
[0] = Definition(linear_vgpr
);
1640 /* find the right place to insert this definition */
1641 if (last_top_level_block_idx
== block
.index
) {
1642 /* insert right before the current instruction */
1643 instructions
.emplace_back(std::move(create
));
1645 assert(last_top_level_block_idx
< block
.index
);
1646 /* insert before the branch at last top level block */
1647 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1648 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1652 /* reload sgpr: just add the vgpr temp to operands */
1653 Pseudo_instruction
* reload
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 2, 1);
1654 reload
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ 64]);
1655 reload
->operands
[1] = Operand(spill_slot
% 64);
1656 reload
->definitions
[0] = (*it
)->definitions
[0];
1657 instructions
.emplace_back(aco_ptr
<Instruction
>(reload
));
1659 unreachable("No spill slot assigned for spill id");
1661 } else if (!ctx
.remat_used
.count(it
->get()) || ctx
.remat_used
[it
->get()]) {
1662 instructions
.emplace_back(std::move(*it
));
1666 block
.instructions
= std::move(instructions
);
1669 /* update required scratch memory */
1670 ctx
.program
->config
->scratch_bytes_per_wave
+= align(vgpr_spill_slots
* 4 * ctx
.program
->wave_size
, 1024);
1672 /* SSA elimination inserts copies for logical phis right before p_logical_end
1673 * So if a linear vgpr is used between that p_logical_end and the branch,
1674 * we need to ensure logical phis don't choose a definition which aliases
1676 * TODO: Moving the spills and reloads to before p_logical_end might produce
1677 * slightly better code. */
1678 for (Block
& block
: ctx
.program
->blocks
) {
1679 /* loops exits are already handled */
1680 if (block
.logical_preds
.size() <= 1)
1683 bool has_logical_phis
= false;
1684 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
1685 if (instr
->opcode
== aco_opcode::p_phi
) {
1686 has_logical_phis
= true;
1688 } else if (instr
->opcode
!= aco_opcode::p_linear_phi
) {
1692 if (!has_logical_phis
)
1695 std::set
<Temp
> vgprs
;
1696 for (unsigned pred_idx
: block
.logical_preds
) {
1697 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
1698 for (int i
= pred
.instructions
.size() - 1; i
>= 0; i
--) {
1699 aco_ptr
<Instruction
>& pred_instr
= pred
.instructions
[i
];
1700 if (pred_instr
->opcode
== aco_opcode::p_logical_end
) {
1702 } else if (pred_instr
->opcode
== aco_opcode::p_spill
||
1703 pred_instr
->opcode
== aco_opcode::p_reload
) {
1704 vgprs
.insert(pred_instr
->operands
[0].getTemp());
1711 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, vgprs
.size(), 0)};
1713 for (Temp tmp
: vgprs
) {
1714 destr
->operands
[k
++] = Operand(tmp
);
1716 /* find insertion point */
1717 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1718 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1720 block
.instructions
.insert(it
, std::move(destr
));
1724 } /* end namespace */
1727 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
)
1729 program
->config
->spilled_vgprs
= 0;
1730 program
->config
->spilled_sgprs
= 0;
1732 /* no spilling when register pressure is low enough */
1733 if (program
->num_waves
> 0)
1736 /* lower to CSSA before spilling to ensure correctness w.r.t. phis */
1737 lower_to_cssa(program
, live_vars
, options
);
1739 /* calculate target register demand */
1740 RegisterDemand register_target
= program
->max_reg_demand
;
1741 if (register_target
.sgpr
> program
->sgpr_limit
)
1742 register_target
.vgpr
+= (register_target
.sgpr
- program
->sgpr_limit
+ 63 + 32) / 64;
1743 register_target
.sgpr
= program
->sgpr_limit
;
1745 if (register_target
.vgpr
> program
->vgpr_limit
)
1746 register_target
.sgpr
= program
->sgpr_limit
- 5;
1747 register_target
.vgpr
= program
->vgpr_limit
- (register_target
.vgpr
- program
->max_reg_demand
.vgpr
);
1749 int spills_to_vgpr
= (program
->max_reg_demand
.sgpr
- register_target
.sgpr
+ 63 + 32) / 64;
1751 /* initialize ctx */
1752 spill_ctx
ctx(register_target
, program
, live_vars
.register_demand
);
1753 compute_global_next_uses(ctx
, live_vars
.live_out
);
1754 get_rematerialize_info(ctx
);
1756 /* create spills and reloads */
1757 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++)
1758 spill_block(ctx
, i
);
1760 /* assign spill slots and DCE rematerialized code */
1761 assign_spill_slots(ctx
, spills_to_vgpr
);
1763 /* update live variable information */
1764 live_vars
= live_var_analysis(program
, options
);
1766 assert(program
->num_waves
>= 0);