2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "vulkan/radv_shader.h"
33 * Implements the spilling algorithm on SSA-form from
34 * "Register Spilling and Live-Range Splitting for SSA-Form Programs"
35 * by Matthias Braun and Sebastian Hack.
47 RegisterDemand target_pressure
;
49 std::vector
<std::vector
<RegisterDemand
>> register_demand
;
50 std::vector
<std::map
<Temp
, Temp
>> renames
;
51 std::vector
<std::map
<Temp
, uint32_t>> spills_entry
;
52 std::vector
<std::map
<Temp
, uint32_t>> spills_exit
;
53 std::vector
<bool> processed
;
54 std::stack
<Block
*> loop_header
;
55 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_start
;
56 std::vector
<std::map
<Temp
, std::pair
<uint32_t, uint32_t>>> next_use_distances_end
;
57 std::vector
<std::pair
<RegClass
, std::set
<uint32_t>>> interferences
;
58 std::vector
<std::vector
<uint32_t>> affinities
;
59 std::vector
<bool> is_reloaded
;
60 std::map
<Temp
, remat_info
> remat
;
61 std::map
<Instruction
*, bool> remat_used
;
63 spill_ctx(const RegisterDemand target_pressure
, Program
* program
,
64 std::vector
<std::vector
<RegisterDemand
>> register_demand
)
65 : target_pressure(target_pressure
), program(program
),
66 register_demand(register_demand
), renames(program
->blocks
.size()),
67 spills_entry(program
->blocks
.size()), spills_exit(program
->blocks
.size()),
68 processed(program
->blocks
.size(), false) {}
70 void add_affinity(uint32_t first
, uint32_t second
)
72 unsigned found_first
= affinities
.size();
73 unsigned found_second
= affinities
.size();
74 for (unsigned i
= 0; i
< affinities
.size(); i
++) {
75 std::vector
<uint32_t>& vec
= affinities
[i
];
76 for (uint32_t entry
: vec
) {
79 else if (entry
== second
)
83 if (found_first
== affinities
.size() && found_second
== affinities
.size()) {
84 affinities
.emplace_back(std::vector
<uint32_t>({first
, second
}));
85 } else if (found_first
< affinities
.size() && found_second
== affinities
.size()) {
86 affinities
[found_first
].push_back(second
);
87 } else if (found_second
< affinities
.size() && found_first
== affinities
.size()) {
88 affinities
[found_second
].push_back(first
);
89 } else if (found_first
!= found_second
) {
90 /* merge second into first */
91 affinities
[found_first
].insert(affinities
[found_first
].end(), affinities
[found_second
].begin(), affinities
[found_second
].end());
92 affinities
.erase(std::next(affinities
.begin(), found_second
));
94 assert(found_first
== found_second
);
98 uint32_t allocate_spill_id(RegClass rc
)
100 interferences
.emplace_back(rc
, std::set
<uint32_t>());
101 is_reloaded
.push_back(false);
102 return next_spill_id
++;
105 uint32_t next_spill_id
= 0;
108 int32_t get_dominator(int idx_a
, int idx_b
, Program
* program
, bool is_linear
)
116 while (idx_a
!= idx_b
) {
118 idx_a
= program
->blocks
[idx_a
].linear_idom
;
120 idx_b
= program
->blocks
[idx_b
].linear_idom
;
123 while (idx_a
!= idx_b
) {
125 idx_a
= program
->blocks
[idx_a
].logical_idom
;
127 idx_b
= program
->blocks
[idx_b
].logical_idom
;
134 void next_uses_per_block(spill_ctx
& ctx
, unsigned block_idx
, std::set
<uint32_t>& worklist
)
136 Block
* block
= &ctx
.program
->blocks
[block_idx
];
137 std::map
<Temp
, std::pair
<uint32_t, uint32_t>> next_uses
= ctx
.next_use_distances_end
[block_idx
];
139 /* to compute the next use distance at the beginning of the block, we have to add the block's size */
140 for (std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= next_uses
.begin(); it
!= next_uses
.end(); ++it
)
141 it
->second
.second
= it
->second
.second
+ block
->instructions
.size();
143 int idx
= block
->instructions
.size() - 1;
145 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
147 if (instr
->opcode
== aco_opcode::p_linear_phi
||
148 instr
->opcode
== aco_opcode::p_phi
)
151 for (const Definition
& def
: instr
->definitions
) {
153 next_uses
.erase(def
.getTemp());
156 for (const Operand
& op
: instr
->operands
) {
158 if (op
.isFixed() && op
.physReg() == exec
)
161 next_uses
[op
.getTemp()] = {block_idx
, idx
};
166 assert(block_idx
!= 0 || next_uses
.empty());
167 ctx
.next_use_distances_start
[block_idx
] = next_uses
;
169 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
170 assert(instr
->opcode
== aco_opcode::p_linear_phi
|| instr
->opcode
== aco_opcode::p_phi
);
172 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
173 unsigned pred_idx
= instr
->opcode
== aco_opcode::p_phi
?
174 block
->logical_preds
[i
] :
175 block
->linear_preds
[i
];
176 if (instr
->operands
[i
].isTemp()) {
177 if (instr
->operands
[i
].getTemp() == ctx
.program
->blocks
[pred_idx
].live_out_exec
)
179 if (ctx
.next_use_distances_end
[pred_idx
].find(instr
->operands
[i
].getTemp()) == ctx
.next_use_distances_end
[pred_idx
].end() ||
180 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] != std::pair
<uint32_t, uint32_t>{block_idx
, 0})
181 worklist
.insert(pred_idx
);
182 ctx
.next_use_distances_end
[pred_idx
][instr
->operands
[i
].getTemp()] = {block_idx
, 0};
185 next_uses
.erase(instr
->definitions
[0].getTemp());
189 /* all remaining live vars must be live-out at the predecessors */
190 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: next_uses
) {
191 Temp temp
= pair
.first
;
192 uint32_t distance
= pair
.second
.second
;
193 uint32_t dom
= pair
.second
.first
;
194 std::vector
<unsigned>& preds
= temp
.is_linear() ? block
->linear_preds
: block
->logical_preds
;
195 for (unsigned pred_idx
: preds
) {
196 if (temp
== ctx
.program
->blocks
[pred_idx
].live_out_exec
)
198 if (ctx
.program
->blocks
[pred_idx
].loop_nest_depth
> block
->loop_nest_depth
)
200 if (ctx
.next_use_distances_end
[pred_idx
].find(temp
) != ctx
.next_use_distances_end
[pred_idx
].end()) {
201 dom
= get_dominator(dom
, ctx
.next_use_distances_end
[pred_idx
][temp
].first
, ctx
.program
, temp
.is_linear());
202 distance
= std::min(ctx
.next_use_distances_end
[pred_idx
][temp
].second
, distance
);
204 if (ctx
.next_use_distances_end
[pred_idx
][temp
] != std::pair
<uint32_t, uint32_t>{dom
, distance
})
205 worklist
.insert(pred_idx
);
206 ctx
.next_use_distances_end
[pred_idx
][temp
] = {dom
, distance
};
212 void compute_global_next_uses(spill_ctx
& ctx
, std::vector
<std::set
<Temp
>>& live_out
)
214 ctx
.next_use_distances_start
.resize(ctx
.program
->blocks
.size());
215 ctx
.next_use_distances_end
.resize(ctx
.program
->blocks
.size());
216 std::set
<uint32_t> worklist
;
217 for (Block
& block
: ctx
.program
->blocks
)
218 worklist
.insert(block
.index
);
220 while (!worklist
.empty()) {
221 std::set
<unsigned>::reverse_iterator b_it
= worklist
.rbegin();
222 unsigned block_idx
= *b_it
;
223 worklist
.erase(block_idx
);
224 next_uses_per_block(ctx
, block_idx
, worklist
);
228 bool should_rematerialize(aco_ptr
<Instruction
>& instr
)
230 /* TODO: rematerialization is only supported for VOP1, SOP1 and PSEUDO */
231 if (instr
->format
!= Format::VOP1
&& instr
->format
!= Format::SOP1
&& instr
->format
!= Format::PSEUDO
)
233 /* TODO: pseudo-instruction rematerialization is only supported for p_create_vector */
234 if (instr
->format
== Format::PSEUDO
&& instr
->opcode
!= aco_opcode::p_create_vector
)
237 for (const Operand
& op
: instr
->operands
) {
238 /* TODO: rematerialization using temporaries isn't yet supported */
243 /* TODO: rematerialization with multiple definitions isn't yet supported */
244 if (instr
->definitions
.size() > 1)
250 aco_ptr
<Instruction
> do_reload(spill_ctx
& ctx
, Temp tmp
, Temp new_name
, uint32_t spill_id
)
252 std::map
<Temp
, remat_info
>::iterator remat
= ctx
.remat
.find(tmp
);
253 if (remat
!= ctx
.remat
.end()) {
254 Instruction
*instr
= remat
->second
.instr
;
255 assert((instr
->format
== Format::VOP1
|| instr
->format
== Format::SOP1
|| instr
->format
== Format::PSEUDO
) && "unsupported");
256 assert((instr
->format
!= Format::PSEUDO
|| instr
->opcode
== aco_opcode::p_create_vector
) && "unsupported");
257 assert(instr
->definitions
.size() == 1 && "unsupported");
259 aco_ptr
<Instruction
> res
;
260 if (instr
->format
== Format::VOP1
) {
261 res
.reset(create_instruction
<VOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
262 } else if (instr
->format
== Format::SOP1
) {
263 res
.reset(create_instruction
<SOP1_instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
264 } else if (instr
->format
== Format::PSEUDO
) {
265 res
.reset(create_instruction
<Instruction
>(instr
->opcode
, instr
->format
, instr
->operands
.size(), instr
->definitions
.size()));
267 for (unsigned i
= 0; i
< instr
->operands
.size(); i
++) {
268 res
->operands
[i
] = instr
->operands
[i
];
269 if (instr
->operands
[i
].isTemp()) {
270 assert(false && "unsupported");
271 if (ctx
.remat
.count(instr
->operands
[i
].getTemp()))
272 ctx
.remat_used
[ctx
.remat
[instr
->operands
[i
].getTemp()].instr
] = true;
275 res
->definitions
[0] = Definition(new_name
);
278 aco_ptr
<Pseudo_instruction
> reload
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 1, 1)};
279 reload
->operands
[0] = Operand(spill_id
);
280 reload
->definitions
[0] = Definition(new_name
);
281 ctx
.is_reloaded
[spill_id
] = true;
286 void get_rematerialize_info(spill_ctx
& ctx
)
288 for (Block
& block
: ctx
.program
->blocks
) {
289 bool logical
= false;
290 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
291 if (instr
->opcode
== aco_opcode::p_logical_start
)
293 else if (instr
->opcode
== aco_opcode::p_logical_end
)
295 if (logical
&& should_rematerialize(instr
)) {
296 for (const Definition
& def
: instr
->definitions
) {
298 ctx
.remat
[def
.getTemp()] = (remat_info
){instr
.get()};
299 ctx
.remat_used
[instr
.get()] = false;
307 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(spill_ctx
& ctx
, Block
* block
)
309 std::vector
<std::map
<Temp
, uint32_t>> local_next_uses(block
->instructions
.size());
311 std::map
<Temp
, uint32_t> next_uses
;
312 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block
->index
])
313 next_uses
[pair
.first
] = pair
.second
.second
+ block
->instructions
.size();
315 for (int idx
= block
->instructions
.size() - 1; idx
>= 0; idx
--) {
316 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
319 if (instr
->opcode
== aco_opcode::p_phi
|| instr
->opcode
== aco_opcode::p_linear_phi
)
322 for (const Operand
& op
: instr
->operands
) {
323 if (op
.isFixed() && op
.physReg() == exec
)
326 next_uses
[op
.getTemp()] = idx
;
328 for (const Definition
& def
: instr
->definitions
) {
330 next_uses
.erase(def
.getTemp());
332 local_next_uses
[idx
] = next_uses
;
334 return local_next_uses
;
338 RegisterDemand
init_live_in_vars(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
340 RegisterDemand spilled_registers
;
342 /* first block, nothing was spilled before */
346 /* loop header block */
347 if (block
->loop_nest_depth
> ctx
.program
->blocks
[block_idx
- 1].loop_nest_depth
) {
348 assert(block
->linear_preds
[0] == block_idx
- 1);
349 assert(block
->logical_preds
[0] == block_idx
- 1);
351 /* create new loop_info */
352 ctx
.loop_header
.emplace(block
);
354 /* check how many live-through variables should be spilled */
355 RegisterDemand new_demand
;
356 unsigned i
= block_idx
;
357 while (ctx
.program
->blocks
[i
].loop_nest_depth
>= block
->loop_nest_depth
) {
358 assert(ctx
.program
->blocks
.size() > i
);
359 new_demand
.update(ctx
.program
->blocks
[i
].register_demand
);
362 unsigned loop_end
= i
;
364 /* select live-through vgpr variables */
365 while (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
366 unsigned distance
= 0;
368 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
369 if (pair
.first
.type() == RegType::vgpr
&&
370 pair
.second
.first
>= loop_end
&&
371 pair
.second
.second
> distance
&&
372 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
373 to_spill
= pair
.first
;
374 distance
= pair
.second
.second
;
381 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
382 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
384 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
387 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
388 spilled_registers
.vgpr
+= to_spill
.size();
391 /* select live-through sgpr variables */
392 while (new_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
393 unsigned distance
= 0;
395 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_end
[block_idx
- 1]) {
396 if (pair
.first
.type() == RegType::sgpr
&&
397 pair
.second
.first
>= loop_end
&&
398 pair
.second
.second
> distance
&&
399 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
400 to_spill
= pair
.first
;
401 distance
= pair
.second
.second
;
408 if (ctx
.spills_exit
[block_idx
- 1].find(to_spill
) == ctx
.spills_exit
[block_idx
- 1].end()) {
409 spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
411 spill_id
= ctx
.spills_exit
[block_idx
- 1][to_spill
];
414 ctx
.spills_entry
[block_idx
][to_spill
] = spill_id
;
415 spilled_registers
.sgpr
+= to_spill
.size();
421 if (!RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
))
422 return spilled_registers
;
424 /* if reg pressure is too high at beginning of loop, add variables with furthest use */
426 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
|| block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
)
429 assert(idx
!= 0 && "loop without phis: TODO");
431 RegisterDemand reg_pressure
= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
432 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
433 unsigned distance
= 0;
435 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
436 if (pair
.first
.type() == RegType::sgpr
&&
437 pair
.second
.second
> distance
&&
438 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
439 to_spill
= pair
.first
;
440 distance
= pair
.second
.second
;
443 assert(distance
!= 0);
445 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
446 spilled_registers
.sgpr
+= to_spill
.size();
447 reg_pressure
.sgpr
-= to_spill
.size();
449 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
450 unsigned distance
= 0;
452 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
453 if (pair
.first
.type() == RegType::vgpr
&&
454 pair
.second
.second
> distance
&&
455 ctx
.spills_entry
[block_idx
].find(pair
.first
) == ctx
.spills_entry
[block_idx
].end()) {
456 to_spill
= pair
.first
;
457 distance
= pair
.second
.second
;
460 assert(distance
!= 0);
461 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
462 spilled_registers
.vgpr
+= to_spill
.size();
463 reg_pressure
.vgpr
-= to_spill
.size();
466 return spilled_registers
;
470 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
471 /* keep variables spilled if they are alive and not used in the current block */
472 unsigned pred_idx
= block
->linear_preds
[0];
473 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
474 if (pair
.first
.type() == RegType::sgpr
&&
475 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
476 ctx
.next_use_distances_start
[block_idx
][pair
.first
].second
> block_idx
) {
477 ctx
.spills_entry
[block_idx
].insert(pair
);
478 spilled_registers
.sgpr
+= pair
.first
.size();
481 if (block
->logical_preds
.size() == 1) {
482 pred_idx
= block
->logical_preds
[0];
483 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
484 if (pair
.first
.type() == RegType::vgpr
&&
485 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
486 ctx
.next_use_distances_end
[pred_idx
][pair
.first
].second
> block_idx
) {
487 ctx
.spills_entry
[block_idx
].insert(pair
);
488 spilled_registers
.vgpr
+= pair
.first
.size();
493 /* if register demand is still too high, we just keep all spilled live vars and process the block */
494 if (block
->register_demand
.sgpr
- spilled_registers
.sgpr
> ctx
.target_pressure
.sgpr
) {
495 pred_idx
= block
->linear_preds
[0];
496 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
497 if (pair
.first
.type() == RegType::sgpr
&&
498 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
499 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
500 spilled_registers
.sgpr
+= pair
.first
.size();
504 if (block
->register_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
&& block
->logical_preds
.size() == 1) {
505 pred_idx
= block
->logical_preds
[0];
506 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
507 if (pair
.first
.type() == RegType::vgpr
&&
508 ctx
.next_use_distances_start
[block_idx
].find(pair
.first
) != ctx
.next_use_distances_start
[block_idx
].end() &&
509 ctx
.spills_entry
[block_idx
].insert(pair
).second
) {
510 spilled_registers
.vgpr
+= pair
.first
.size();
515 return spilled_registers
;
518 /* else: merge block */
519 std::set
<Temp
> partial_spills
;
521 /* keep variables spilled on all incoming paths */
522 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
523 std::vector
<unsigned>& preds
= pair
.first
.type() == RegType::vgpr
? block
->logical_preds
: block
->linear_preds
;
524 /* If it can be rematerialized, keep the variable spilled if all predecessors do not reload it.
525 * Otherwise, if any predecessor reloads it, ensure it's reloaded on all other predecessors.
526 * The idea is that it's better in practice to rematerialize redundantly than to create lots of phis. */
527 /* TODO: test this idea with more than Dawn of War III shaders (the current pipeline-db doesn't seem to exercise this path much) */
528 bool remat
= ctx
.remat
.count(pair
.first
);
530 uint32_t spill_id
= 0;
531 for (unsigned pred_idx
: preds
) {
532 /* variable is not even live at the predecessor: probably from a phi */
533 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end()) {
537 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
541 partial_spills
.insert(pair
.first
);
542 /* it might be that on one incoming path, the variable has a different spill_id, but add_couple_code() will take care of that. */
543 spill_id
= ctx
.spills_exit
[pred_idx
][pair
.first
];
549 ctx
.spills_entry
[block_idx
][pair
.first
] = spill_id
;
550 partial_spills
.erase(pair
.first
);
551 spilled_registers
+= pair
.first
;
557 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
||
558 block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
) {
559 aco_ptr
<Instruction
>& phi
= block
->instructions
[idx
];
560 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
563 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
564 if (phi
->operands
[i
].isUndefined())
566 assert(phi
->operands
[i
].isTemp());
567 if (ctx
.spills_exit
[preds
[i
]].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[preds
[i
]].end())
570 partial_spills
.insert(phi
->definitions
[0].getTemp());
573 ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()] = ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
574 partial_spills
.erase(phi
->definitions
[0].getTemp());
575 spilled_registers
+= phi
->definitions
[0].getTemp();
581 /* if reg pressure at first instruction is still too high, add partially spilled variables */
582 RegisterDemand reg_pressure
;
584 for (const Definition
& def
: block
->instructions
[idx
]->definitions
) {
586 reg_pressure
-= def
.getTemp();
589 for (const Operand
& op
: block
->instructions
[idx
]->operands
) {
590 if (op
.isTemp() && op
.isFirstKill()) {
591 reg_pressure
+= op
.getTemp();
597 reg_pressure
+= ctx
.register_demand
[block_idx
][idx
] - spilled_registers
;
599 while (reg_pressure
.sgpr
> ctx
.target_pressure
.sgpr
) {
600 assert(!partial_spills
.empty());
602 std::set
<Temp
>::iterator it
= partial_spills
.begin();
604 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
605 while (it
!= partial_spills
.end()) {
606 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
608 if (it
->type() == RegType::sgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
609 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
614 assert(distance
!= 0);
616 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
617 partial_spills
.erase(to_spill
);
618 spilled_registers
.sgpr
+= to_spill
.size();
619 reg_pressure
.sgpr
-= to_spill
.size();
622 while (reg_pressure
.vgpr
> ctx
.target_pressure
.vgpr
) {
623 assert(!partial_spills
.empty());
625 std::set
<Temp
>::iterator it
= partial_spills
.begin();
627 unsigned distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
628 while (it
!= partial_spills
.end()) {
629 assert(ctx
.spills_entry
[block_idx
].find(*it
) == ctx
.spills_entry
[block_idx
].end());
631 if (it
->type() == RegType::vgpr
&& ctx
.next_use_distances_start
[block_idx
][*it
].second
> distance
) {
632 distance
= ctx
.next_use_distances_start
[block_idx
][*it
].second
;
637 assert(distance
!= 0);
639 ctx
.spills_entry
[block_idx
][to_spill
] = ctx
.allocate_spill_id(to_spill
.regClass());
640 partial_spills
.erase(to_spill
);
641 spilled_registers
.vgpr
+= to_spill
.size();
642 reg_pressure
.vgpr
-= to_spill
.size();
645 return spilled_registers
;
649 void add_coupling_code(spill_ctx
& ctx
, Block
* block
, unsigned block_idx
)
651 /* no coupling code necessary */
652 if (block
->linear_preds
.size() == 0)
655 std::vector
<aco_ptr
<Instruction
>> instructions
;
656 /* branch block: TODO take other branch into consideration */
657 if (block
->linear_preds
.size() == 1 && !(block
->kind
& block_kind_loop_exit
)) {
658 assert(ctx
.processed
[block
->linear_preds
[0]]);
660 if (block
->logical_preds
.size() == 1) {
661 unsigned pred_idx
= block
->logical_preds
[0];
662 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
663 if (live
.first
.type() == RegType::sgpr
)
666 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
669 /* in register at end of predecessor */
670 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
671 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
672 if (it
!= ctx
.renames
[pred_idx
].end())
673 ctx
.renames
[block_idx
].insert(*it
);
677 /* variable is spilled at predecessor and live at current block: create reload instruction */
678 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
679 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
680 instructions
.emplace_back(std::move(reload
));
681 ctx
.renames
[block_idx
][live
.first
] = new_name
;
685 unsigned pred_idx
= block
->linear_preds
[0];
686 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> live
: ctx
.next_use_distances_start
[block_idx
]) {
687 if (live
.first
.type() == RegType::vgpr
)
690 if (ctx
.spills_entry
[block_idx
].find(live
.first
) != ctx
.spills_entry
[block_idx
].end())
693 /* in register at end of predecessor */
694 if (ctx
.spills_exit
[pred_idx
].find(live
.first
) == ctx
.spills_exit
[pred_idx
].end()) {
695 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(live
.first
);
696 if (it
!= ctx
.renames
[pred_idx
].end())
697 ctx
.renames
[block_idx
].insert(*it
);
701 /* variable is spilled at predecessor and live at current block: create reload instruction */
702 Temp new_name
= {ctx
.program
->allocateId(), live
.first
.regClass()};
703 aco_ptr
<Instruction
> reload
= do_reload(ctx
, live
.first
, new_name
, ctx
.spills_exit
[pred_idx
][live
.first
]);
704 instructions
.emplace_back(std::move(reload
));
705 ctx
.renames
[block_idx
][live
.first
] = new_name
;
708 /* combine new reload instructions with original block */
709 if (!instructions
.empty()) {
710 unsigned insert_idx
= 0;
711 while (block
->instructions
[insert_idx
]->opcode
== aco_opcode::p_phi
||
712 block
->instructions
[insert_idx
]->opcode
== aco_opcode::p_linear_phi
) {
715 ctx
.register_demand
[block
->index
].insert(std::next(ctx
.register_demand
[block
->index
].begin(), insert_idx
),
716 instructions
.size(), RegisterDemand());
717 block
->instructions
.insert(std::next(block
->instructions
.begin(), insert_idx
),
718 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(instructions
.begin()),
719 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(instructions
.end()));
724 /* loop header and merge blocks: check if all (linear) predecessors have been processed */
725 for (ASSERTED
unsigned pred
: block
->linear_preds
)
726 assert(ctx
.processed
[pred
]);
728 /* iterate the phi nodes for which operands to spill at the predecessor */
729 for (aco_ptr
<Instruction
>& phi
: block
->instructions
) {
730 if (phi
->opcode
!= aco_opcode::p_phi
&&
731 phi
->opcode
!= aco_opcode::p_linear_phi
)
734 /* if the phi is not spilled, add to instructions */
735 if (ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end()) {
736 instructions
.emplace_back(std::move(phi
));
740 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
741 uint32_t def_spill_id
= ctx
.spills_entry
[block_idx
][phi
->definitions
[0].getTemp()];
743 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
744 if (phi
->operands
[i
].isUndefined())
747 unsigned pred_idx
= preds
[i
];
748 assert(phi
->operands
[i
].isTemp() && phi
->operands
[i
].isKill());
749 Temp var
= phi
->operands
[i
].getTemp();
751 /* build interferences between the phi def and all spilled variables at the predecessor blocks */
752 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[pred_idx
]) {
753 if (var
== pair
.first
)
755 ctx
.interferences
[def_spill_id
].second
.emplace(pair
.second
);
756 ctx
.interferences
[pair
.second
].second
.emplace(def_spill_id
);
759 /* check if variable is already spilled at predecessor */
760 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(var
);
761 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
762 if (spilled
->second
!= def_spill_id
)
763 ctx
.add_affinity(def_spill_id
, spilled
->second
);
767 /* rename if necessary */
768 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
769 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
770 var
= rename_it
->second
;
771 ctx
.renames
[pred_idx
].erase(rename_it
);
774 uint32_t spill_id
= ctx
.allocate_spill_id(phi
->definitions
[0].regClass());
775 ctx
.add_affinity(def_spill_id
, spill_id
);
776 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
777 spill
->operands
[0] = Operand(var
);
778 spill
->operands
[1] = Operand(spill_id
);
779 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
780 unsigned idx
= pred
.instructions
.size();
784 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
785 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
786 pred
.instructions
.insert(it
, std::move(spill
));
787 ctx
.spills_exit
[pred_idx
][phi
->operands
[i
].getTemp()] = spill_id
;
790 /* remove phi from instructions */
794 /* iterate all (other) spilled variables for which to spill at the predecessor */
795 // TODO: would be better to have them sorted: first vgprs and first with longest distance
796 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_entry
[block_idx
]) {
797 std::vector
<unsigned> preds
= pair
.first
.type() == RegType::vgpr
? block
->logical_preds
: block
->linear_preds
;
799 for (unsigned pred_idx
: preds
) {
800 /* variable is already spilled at predecessor */
801 std::map
<Temp
, uint32_t>::iterator spilled
= ctx
.spills_exit
[pred_idx
].find(pair
.first
);
802 if (spilled
!= ctx
.spills_exit
[pred_idx
].end()) {
803 if (spilled
->second
!= pair
.second
)
804 ctx
.add_affinity(pair
.second
, spilled
->second
);
808 /* variable is dead at predecessor, it must be from a phi: this works because of CSSA form */
809 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
812 /* add interferences between spilled variable and predecessors exit spills */
813 for (std::pair
<Temp
, uint32_t> exit_spill
: ctx
.spills_exit
[pred_idx
]) {
814 if (exit_spill
.first
== pair
.first
)
816 ctx
.interferences
[exit_spill
.second
].second
.emplace(pair
.second
);
817 ctx
.interferences
[pair
.second
].second
.emplace(exit_spill
.second
);
820 /* variable is in register at predecessor and has to be spilled */
821 /* rename if necessary */
822 Temp var
= pair
.first
;
823 std::map
<Temp
, Temp
>::iterator rename_it
= ctx
.renames
[pred_idx
].find(var
);
824 if (rename_it
!= ctx
.renames
[pred_idx
].end()) {
825 var
= rename_it
->second
;
826 ctx
.renames
[pred_idx
].erase(rename_it
);
829 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
830 spill
->operands
[0] = Operand(var
);
831 spill
->operands
[1] = Operand(pair
.second
);
832 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
833 unsigned idx
= pred
.instructions
.size();
837 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
838 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
839 pred
.instructions
.insert(it
, std::move(spill
));
840 ctx
.spills_exit
[pred
.index
][pair
.first
] = pair
.second
;
844 /* iterate phis for which operands to reload */
845 for (aco_ptr
<Instruction
>& phi
: instructions
) {
846 assert(phi
->opcode
== aco_opcode::p_phi
|| phi
->opcode
== aco_opcode::p_linear_phi
);
847 assert(ctx
.spills_entry
[block_idx
].find(phi
->definitions
[0].getTemp()) == ctx
.spills_entry
[block_idx
].end());
849 std::vector
<unsigned>& preds
= phi
->opcode
== aco_opcode::p_phi
? block
->logical_preds
: block
->linear_preds
;
850 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
851 if (!phi
->operands
[i
].isTemp())
853 unsigned pred_idx
= preds
[i
];
856 if (ctx
.spills_exit
[pred_idx
].find(phi
->operands
[i
].getTemp()) == ctx
.spills_exit
[pred_idx
].end()) {
857 std::map
<Temp
, Temp
>::iterator it
= ctx
.renames
[pred_idx
].find(phi
->operands
[i
].getTemp());
858 if (it
!= ctx
.renames
[pred_idx
].end())
859 phi
->operands
[i
].setTemp(it
->second
);
863 Temp tmp
= phi
->operands
[i
].getTemp();
865 /* reload phi operand at end of predecessor block */
866 Temp new_name
= {ctx
.program
->allocateId(), tmp
.regClass()};
867 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
868 unsigned idx
= pred
.instructions
.size();
872 } while (phi
->opcode
== aco_opcode::p_phi
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
873 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
875 aco_ptr
<Instruction
> reload
= do_reload(ctx
, tmp
, new_name
, ctx
.spills_exit
[pred_idx
][tmp
]);
876 pred
.instructions
.insert(it
, std::move(reload
));
878 ctx
.spills_exit
[pred_idx
].erase(tmp
);
879 ctx
.renames
[pred_idx
][tmp
] = new_name
;
880 phi
->operands
[i
].setTemp(new_name
);
884 /* iterate live variables for which to reload */
885 // TODO: reload at current block if variable is spilled on all predecessors
886 for (std::pair
<Temp
, std::pair
<uint32_t, uint32_t>> pair
: ctx
.next_use_distances_start
[block_idx
]) {
887 /* skip spilled variables */
888 if (ctx
.spills_entry
[block_idx
].find(pair
.first
) != ctx
.spills_entry
[block_idx
].end())
890 std::vector
<unsigned> preds
= pair
.first
.type() == RegType::vgpr
? block
->logical_preds
: block
->linear_preds
;
892 /* variable is dead at predecessor, it must be from a phi */
893 bool is_dead
= false;
894 for (unsigned pred_idx
: preds
) {
895 if (ctx
.next_use_distances_end
[pred_idx
].find(pair
.first
) == ctx
.next_use_distances_end
[pred_idx
].end())
900 for (unsigned pred_idx
: preds
) {
901 /* the variable is not spilled at the predecessor */
902 if (ctx
.spills_exit
[pred_idx
].find(pair
.first
) == ctx
.spills_exit
[pred_idx
].end())
905 /* variable is spilled at predecessor and has to be reloaded */
906 Temp new_name
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
907 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
908 unsigned idx
= pred
.instructions
.size();
912 } while (pair
.first
.type() == RegType::vgpr
&& pred
.instructions
[idx
]->opcode
!= aco_opcode::p_logical_end
);
913 std::vector
<aco_ptr
<Instruction
>>::iterator it
= std::next(pred
.instructions
.begin(), idx
);
915 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.first
, new_name
, ctx
.spills_exit
[pred
.index
][pair
.first
]);
916 pred
.instructions
.insert(it
, std::move(reload
));
918 ctx
.spills_exit
[pred
.index
].erase(pair
.first
);
919 ctx
.renames
[pred
.index
][pair
.first
] = new_name
;
922 /* check if we have to create a new phi for this variable */
923 Temp rename
= Temp();
925 for (unsigned pred_idx
: preds
) {
926 if (ctx
.renames
[pred_idx
].find(pair
.first
) == ctx
.renames
[pred_idx
].end()) {
927 if (rename
== Temp())
930 is_same
= rename
== pair
.first
;
932 if (rename
== Temp())
933 rename
= ctx
.renames
[pred_idx
][pair
.first
];
935 is_same
= rename
== ctx
.renames
[pred_idx
][pair
.first
];
943 /* the variable was renamed differently in the predecessors: we have to create a phi */
944 aco_opcode opcode
= pair
.first
.type() == RegType::vgpr
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
945 aco_ptr
<Pseudo_instruction
> phi
{create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, preds
.size(), 1)};
946 rename
= {ctx
.program
->allocateId(), pair
.first
.regClass()};
947 for (unsigned i
= 0; i
< phi
->operands
.size(); i
++) {
949 if (ctx
.renames
[preds
[i
]].find(pair
.first
) != ctx
.renames
[preds
[i
]].end())
950 tmp
= ctx
.renames
[preds
[i
]][pair
.first
];
951 else if (preds
[i
] >= block_idx
)
955 phi
->operands
[i
] = Operand(tmp
);
957 phi
->definitions
[0] = Definition(rename
);
958 instructions
.emplace_back(std::move(phi
));
961 /* the variable was renamed: add new name to renames */
962 if (!(rename
== Temp() || rename
== pair
.first
))
963 ctx
.renames
[block_idx
][pair
.first
] = rename
;
966 /* combine phis with instructions */
968 while (!block
->instructions
[idx
]) {
972 ctx
.register_demand
[block
->index
].erase(ctx
.register_demand
[block
->index
].begin(), ctx
.register_demand
[block
->index
].begin() + idx
);
973 ctx
.register_demand
[block
->index
].insert(ctx
.register_demand
[block
->index
].begin(), instructions
.size(), RegisterDemand());
975 std::vector
<aco_ptr
<Instruction
>>::iterator start
= std::next(block
->instructions
.begin(), idx
);
976 instructions
.insert(instructions
.end(), std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(start
),
977 std::move_iterator
<std::vector
<aco_ptr
<Instruction
>>::iterator
>(block
->instructions
.end()));
978 block
->instructions
= std::move(instructions
);
981 void process_block(spill_ctx
& ctx
, unsigned block_idx
, Block
* block
,
982 std::map
<Temp
, uint32_t> ¤t_spills
, RegisterDemand spilled_registers
)
984 std::vector
<std::map
<Temp
, uint32_t>> local_next_use_distance
;
985 std::vector
<aco_ptr
<Instruction
>> instructions
;
988 /* phis are handled separetely */
989 while (block
->instructions
[idx
]->opcode
== aco_opcode::p_phi
||
990 block
->instructions
[idx
]->opcode
== aco_opcode::p_linear_phi
) {
991 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
992 for (const Operand
& op
: instr
->operands
) {
993 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
994 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
995 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
997 instructions
.emplace_back(std::move(instr
));
1001 if (block
->register_demand
.exceeds(ctx
.target_pressure
))
1002 local_next_use_distance
= local_next_uses(ctx
, block
);
1004 while (idx
< block
->instructions
.size()) {
1005 aco_ptr
<Instruction
>& instr
= block
->instructions
[idx
];
1007 std::map
<Temp
, std::pair
<Temp
, uint32_t>> reloads
;
1008 std::map
<Temp
, uint32_t> spills
;
1009 /* rename and reload operands */
1010 for (Operand
& op
: instr
->operands
) {
1013 if (current_spills
.find(op
.getTemp()) == current_spills
.end()) {
1014 /* the Operand is in register: check if it was renamed */
1015 if (ctx
.renames
[block_idx
].find(op
.getTemp()) != ctx
.renames
[block_idx
].end())
1016 op
.setTemp(ctx
.renames
[block_idx
][op
.getTemp()]);
1017 /* prevent it's definining instruction from being DCE'd if it could be rematerialized */
1018 if (ctx
.remat
.count(op
.getTemp()))
1019 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1022 /* the Operand is spilled: add it to reloads */
1023 Temp new_tmp
= {ctx
.program
->allocateId(), op
.regClass()};
1024 ctx
.renames
[block_idx
][op
.getTemp()] = new_tmp
;
1025 reloads
[new_tmp
] = std::make_pair(op
.getTemp(), current_spills
[op
.getTemp()]);
1026 current_spills
.erase(op
.getTemp());
1027 op
.setTemp(new_tmp
);
1028 spilled_registers
-= new_tmp
;
1031 /* check if register demand is low enough before and after the current instruction */
1032 if (block
->register_demand
.exceeds(ctx
.target_pressure
)) {
1034 RegisterDemand new_demand
= ctx
.register_demand
[block_idx
][idx
];
1036 RegisterDemand demand_before
= new_demand
;
1037 for (const Definition
& def
: instr
->definitions
)
1038 demand_before
-= def
.getTemp();
1039 for (const Operand
& op
: instr
->operands
) {
1040 if (op
.isFirstKill())
1041 demand_before
+= op
.getTemp();
1043 new_demand
.update(demand_before
);
1045 new_demand
.update(ctx
.register_demand
[block_idx
][idx
- 1]);
1048 assert(!local_next_use_distance
.empty());
1050 /* if reg pressure is too high, spill variable with furthest next use */
1051 while (RegisterDemand(new_demand
- spilled_registers
).exceeds(ctx
.target_pressure
)) {
1052 unsigned distance
= 0;
1054 bool do_rematerialize
= false;
1055 if (new_demand
.vgpr
- spilled_registers
.vgpr
> ctx
.target_pressure
.vgpr
) {
1056 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1057 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1058 if (pair
.first
.type() == RegType::vgpr
&&
1059 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1060 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1061 current_spills
.find(pair
.first
) == current_spills
.end() &&
1062 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1063 to_spill
= pair
.first
;
1064 distance
= pair
.second
;
1065 do_rematerialize
= can_rematerialize
;
1069 for (std::pair
<Temp
, uint32_t> pair
: local_next_use_distance
[idx
]) {
1070 bool can_rematerialize
= ctx
.remat
.count(pair
.first
);
1071 if (pair
.first
.type() == RegType::sgpr
&&
1072 ((pair
.second
> distance
&& can_rematerialize
== do_rematerialize
) ||
1073 (can_rematerialize
&& !do_rematerialize
&& pair
.second
> idx
)) &&
1074 current_spills
.find(pair
.first
) == current_spills
.end() &&
1075 ctx
.spills_exit
[block_idx
].find(pair
.first
) == ctx
.spills_exit
[block_idx
].end()) {
1076 to_spill
= pair
.first
;
1077 distance
= pair
.second
;
1078 do_rematerialize
= can_rematerialize
;
1083 assert(distance
!= 0 && distance
> idx
);
1084 uint32_t spill_id
= ctx
.allocate_spill_id(to_spill
.regClass());
1086 /* add interferences with currently spilled variables */
1087 for (std::pair
<Temp
, uint32_t> pair
: current_spills
) {
1088 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
);
1089 ctx
.interferences
[pair
.second
].second
.emplace(spill_id
);
1091 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1092 ctx
.interferences
[spill_id
].second
.emplace(pair
.second
.second
);
1093 ctx
.interferences
[pair
.second
.second
].second
.emplace(spill_id
);
1096 current_spills
[to_spill
] = spill_id
;
1097 spilled_registers
+= to_spill
;
1099 /* rename if necessary */
1100 if (ctx
.renames
[block_idx
].find(to_spill
) != ctx
.renames
[block_idx
].end()) {
1101 to_spill
= ctx
.renames
[block_idx
][to_spill
];
1104 /* add spill to new instructions */
1105 aco_ptr
<Pseudo_instruction
> spill
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 2, 0)};
1106 spill
->operands
[0] = Operand(to_spill
);
1107 spill
->operands
[1] = Operand(spill_id
);
1108 instructions
.emplace_back(std::move(spill
));
1112 /* add reloads and instruction to new instructions */
1113 for (std::pair
<Temp
, std::pair
<Temp
, uint32_t>> pair
: reloads
) {
1114 aco_ptr
<Instruction
> reload
= do_reload(ctx
, pair
.second
.first
, pair
.first
, pair
.second
.second
);
1115 instructions
.emplace_back(std::move(reload
));
1117 instructions
.emplace_back(std::move(instr
));
1121 block
->instructions
= std::move(instructions
);
1122 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1125 void spill_block(spill_ctx
& ctx
, unsigned block_idx
)
1127 Block
* block
= &ctx
.program
->blocks
[block_idx
];
1128 ctx
.processed
[block_idx
] = true;
1130 /* determine set of variables which are spilled at the beginning of the block */
1131 RegisterDemand spilled_registers
= init_live_in_vars(ctx
, block
, block_idx
);
1133 /* add interferences for spilled variables */
1134 for (std::pair
<Temp
, uint32_t> x
: ctx
.spills_entry
[block_idx
]) {
1135 for (std::pair
<Temp
, uint32_t> y
: ctx
.spills_entry
[block_idx
])
1136 if (x
.second
!= y
.second
)
1137 ctx
.interferences
[x
.second
].second
.emplace(y
.second
);
1140 bool is_loop_header
= block
->loop_nest_depth
&& ctx
.loop_header
.top()->index
== block_idx
;
1141 if (!is_loop_header
) {
1142 /* add spill/reload code on incoming control flow edges */
1143 add_coupling_code(ctx
, block
, block_idx
);
1146 std::map
<Temp
, uint32_t> current_spills
= ctx
.spills_entry
[block_idx
];
1148 /* check conditions to process this block */
1149 bool process
= RegisterDemand(block
->register_demand
- spilled_registers
).exceeds(ctx
.target_pressure
) ||
1150 !ctx
.renames
[block_idx
].empty() ||
1151 ctx
.remat_used
.size();
1153 std::map
<Temp
, uint32_t>::iterator it
= current_spills
.begin();
1154 while (!process
&& it
!= current_spills
.end()) {
1155 if (ctx
.next_use_distances_start
[block_idx
][it
->first
].first
== block_idx
)
1161 process_block(ctx
, block_idx
, block
, current_spills
, spilled_registers
);
1163 ctx
.spills_exit
[block_idx
].insert(current_spills
.begin(), current_spills
.end());
1165 /* check if the next block leaves the current loop */
1166 if (block
->loop_nest_depth
== 0 || ctx
.program
->blocks
[block_idx
+ 1].loop_nest_depth
>= block
->loop_nest_depth
)
1169 Block
* loop_header
= ctx
.loop_header
.top();
1171 /* preserve original renames at end of loop header block */
1172 std::map
<Temp
, Temp
> renames
= std::move(ctx
.renames
[loop_header
->index
]);
1174 /* add coupling code to all loop header predecessors */
1175 add_coupling_code(ctx
, loop_header
, loop_header
->index
);
1177 /* update remat_used for phis added in add_coupling_code() */
1178 for (aco_ptr
<Instruction
>& instr
: loop_header
->instructions
) {
1181 for (const Operand
& op
: instr
->operands
) {
1182 if (op
.isTemp() && ctx
.remat
.count(op
.getTemp()))
1183 ctx
.remat_used
[ctx
.remat
[op
.getTemp()].instr
] = true;
1187 /* propagate new renames through loop: i.e. repair the SSA */
1188 renames
.swap(ctx
.renames
[loop_header
->index
]);
1189 for (std::pair
<Temp
, Temp
> rename
: renames
) {
1190 for (unsigned idx
= loop_header
->index
; idx
<= block_idx
; idx
++) {
1191 Block
& current
= ctx
.program
->blocks
[idx
];
1192 std::vector
<aco_ptr
<Instruction
>>::iterator instr_it
= current
.instructions
.begin();
1194 /* first rename phis */
1195 while (instr_it
!= current
.instructions
.end()) {
1196 aco_ptr
<Instruction
>& phi
= *instr_it
;
1197 if (phi
->opcode
!= aco_opcode::p_phi
&& phi
->opcode
!= aco_opcode::p_linear_phi
)
1199 /* no need to rename the loop header phis once again. this happened in add_coupling_code() */
1200 if (idx
== loop_header
->index
) {
1205 for (Operand
& op
: phi
->operands
) {
1208 if (op
.getTemp() == rename
.first
)
1209 op
.setTemp(rename
.second
);
1214 std::map
<Temp
, std::pair
<uint32_t, uint32_t>>::iterator it
= ctx
.next_use_distances_start
[idx
].find(rename
.first
);
1216 /* variable is not live at beginning of this block */
1217 if (it
== ctx
.next_use_distances_start
[idx
].end())
1220 /* if the variable is live at the block's exit, add rename */
1221 if (ctx
.next_use_distances_end
[idx
].find(rename
.first
) != ctx
.next_use_distances_end
[idx
].end())
1222 ctx
.renames
[idx
].insert(rename
);
1224 /* rename all uses in this block */
1225 bool renamed
= false;
1226 while (!renamed
&& instr_it
!= current
.instructions
.end()) {
1227 aco_ptr
<Instruction
>& instr
= *instr_it
;
1228 for (Operand
& op
: instr
->operands
) {
1231 if (op
.getTemp() == rename
.first
) {
1232 op
.setTemp(rename
.second
);
1233 /* we can stop with this block as soon as the variable is spilled */
1234 if (instr
->opcode
== aco_opcode::p_spill
)
1243 /* remove loop header info from stack */
1244 ctx
.loop_header
.pop();
1247 void assign_spill_slots(spill_ctx
& ctx
, unsigned spills_to_vgpr
) {
1248 std::map
<uint32_t, uint32_t> sgpr_slot
;
1249 std::map
<uint32_t, uint32_t> vgpr_slot
;
1250 std::vector
<bool> is_assigned(ctx
.interferences
.size());
1252 /* first, handle affinities: just merge all interferences into both spill ids */
1253 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1254 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1255 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1256 assert(vec
[i
] != vec
[j
]);
1257 for (uint32_t id
: ctx
.interferences
[vec
[i
]].second
)
1258 ctx
.interferences
[id
].second
.insert(vec
[j
]);
1259 for (uint32_t id
: ctx
.interferences
[vec
[j
]].second
)
1260 ctx
.interferences
[id
].second
.insert(vec
[i
]);
1261 ctx
.interferences
[vec
[i
]].second
.insert(ctx
.interferences
[vec
[j
]].second
.begin(), ctx
.interferences
[vec
[j
]].second
.end());
1262 ctx
.interferences
[vec
[j
]].second
.insert(ctx
.interferences
[vec
[i
]].second
.begin(), ctx
.interferences
[vec
[i
]].second
.end());
1264 bool reloaded
= ctx
.is_reloaded
[vec
[i
]] || ctx
.is_reloaded
[vec
[j
]];
1265 ctx
.is_reloaded
[vec
[i
]] = reloaded
;
1266 ctx
.is_reloaded
[vec
[j
]] = reloaded
;
1270 for (ASSERTED
uint32_t i
= 0; i
< ctx
.interferences
.size(); i
++)
1271 for (ASSERTED
uint32_t id
: ctx
.interferences
[i
].second
)
1274 /* for each spill slot, assign as many spill ids as possible */
1275 std::vector
<std::set
<uint32_t>> spill_slot_interferences
;
1276 unsigned slot_idx
= 0;
1279 /* assign sgpr spill slots */
1282 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1283 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1285 if (ctx
.interferences
[id
].first
.type() != RegType::sgpr
)
1288 /* check interferences */
1289 bool interferes
= false;
1290 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1291 if (i
== spill_slot_interferences
.size())
1292 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1293 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end() || i
/ 64 != slot_idx
/ 64) {
1303 /* we found a spill id which can be assigned to current spill slot */
1304 sgpr_slot
[id
] = slot_idx
;
1305 is_assigned
[id
] = true;
1306 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1307 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1309 /* add all affinities: there are no additional interferences */
1310 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1311 bool found_affinity
= false;
1312 for (uint32_t entry
: vec
) {
1314 found_affinity
= true;
1318 if (!found_affinity
)
1320 for (uint32_t entry
: vec
) {
1321 sgpr_slot
[entry
] = slot_idx
;
1322 is_assigned
[entry
] = true;
1332 /* assign vgpr spill slots */
1335 for (unsigned id
= 0; id
< ctx
.interferences
.size(); id
++) {
1336 if (is_assigned
[id
] || !ctx
.is_reloaded
[id
])
1338 if (ctx
.interferences
[id
].first
.type() != RegType::vgpr
)
1341 /* check interferences */
1342 bool interferes
= false;
1343 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++) {
1344 if (i
== spill_slot_interferences
.size())
1345 spill_slot_interferences
.emplace_back(std::set
<uint32_t>());
1346 /* check for interference and ensure that vector regs are stored next to each other */
1347 if (spill_slot_interferences
[i
].find(id
) != spill_slot_interferences
[i
].end() || i
/ 64 != slot_idx
/ 64) {
1357 /* we found a spill id which can be assigned to current spill slot */
1358 vgpr_slot
[id
] = slot_idx
;
1359 is_assigned
[id
] = true;
1360 for (unsigned i
= slot_idx
; i
< slot_idx
+ ctx
.interferences
[id
].first
.size(); i
++)
1361 spill_slot_interferences
[i
].insert(ctx
.interferences
[id
].second
.begin(), ctx
.interferences
[id
].second
.end());
1366 for (unsigned id
= 0; id
< is_assigned
.size(); id
++)
1367 assert(is_assigned
[id
] || !ctx
.is_reloaded
[id
]);
1369 for (std::vector
<uint32_t>& vec
: ctx
.affinities
) {
1370 for (unsigned i
= 0; i
< vec
.size(); i
++) {
1371 for (unsigned j
= i
+ 1; j
< vec
.size(); j
++) {
1372 assert(is_assigned
[vec
[i
]] == is_assigned
[vec
[j
]]);
1373 if (!is_assigned
[vec
[i
]])
1375 assert(ctx
.is_reloaded
[vec
[i
]] == ctx
.is_reloaded
[vec
[j
]]);
1376 assert(ctx
.interferences
[vec
[i
]].first
.type() == ctx
.interferences
[vec
[j
]].first
.type());
1377 if (ctx
.interferences
[vec
[i
]].first
.type() == RegType::sgpr
)
1378 assert(sgpr_slot
[vec
[i
]] == sgpr_slot
[vec
[j
]]);
1380 assert(vgpr_slot
[vec
[i
]] == vgpr_slot
[vec
[j
]]);
1385 /* hope, we didn't mess up */
1386 std::vector
<Temp
> vgpr_spill_temps((spill_slot_interferences
.size() + 63) / 64);
1387 assert(vgpr_spill_temps
.size() <= spills_to_vgpr
);
1389 /* replace pseudo instructions with actual hardware instructions */
1390 unsigned last_top_level_block_idx
= 0;
1391 std::vector
<bool> reload_in_loop(vgpr_spill_temps
.size());
1392 for (Block
& block
: ctx
.program
->blocks
) {
1394 /* after loops, we insert a user if there was a reload inside the loop */
1395 if (block
.loop_nest_depth
== 0) {
1397 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1398 if (reload_in_loop
[i
])
1402 if (end_vgprs
> 0) {
1403 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, end_vgprs
, 0)};
1405 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1406 if (reload_in_loop
[i
])
1407 destr
->operands
[k
++] = Operand(vgpr_spill_temps
[i
]);
1408 reload_in_loop
[i
] = false;
1410 /* find insertion point */
1411 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1412 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1414 block
.instructions
.insert(it
, std::move(destr
));
1418 if (block
.kind
& block_kind_top_level
&& !block
.linear_preds
.empty()) {
1419 last_top_level_block_idx
= block
.index
;
1421 /* check if any spilled variables use a created linear vgpr, otherwise destroy them */
1422 for (unsigned i
= 0; i
< vgpr_spill_temps
.size(); i
++) {
1423 if (vgpr_spill_temps
[i
] == Temp())
1426 bool can_destroy
= true;
1427 for (std::pair
<Temp
, uint32_t> pair
: ctx
.spills_exit
[block
.linear_preds
[0]]) {
1429 if (sgpr_slot
.find(pair
.second
) != sgpr_slot
.end() &&
1430 sgpr_slot
[pair
.second
] / 64 == i
) {
1431 can_destroy
= false;
1436 vgpr_spill_temps
[i
] = Temp();
1440 std::vector
<aco_ptr
<Instruction
>>::iterator it
;
1441 std::vector
<aco_ptr
<Instruction
>> instructions
;
1442 instructions
.reserve(block
.instructions
.size());
1443 for (it
= block
.instructions
.begin(); it
!= block
.instructions
.end(); ++it
) {
1445 if ((*it
)->opcode
== aco_opcode::p_spill
) {
1446 uint32_t spill_id
= (*it
)->operands
[1].constantValue();
1448 if (!ctx
.is_reloaded
[spill_id
]) {
1449 /* never reloaded, so don't spill */
1450 } else if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1452 ctx
.program
->config
->spilled_vgprs
+= (*it
)->operands
[0].size();
1454 assert(false && "vgpr spilling not yet implemented.");
1455 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1456 ctx
.program
->config
->spilled_sgprs
+= (*it
)->operands
[0].size();
1458 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1460 /* check if the linear vgpr already exists */
1461 if (vgpr_spill_temps
[spill_slot
/ 64] == Temp()) {
1462 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1463 vgpr_spill_temps
[spill_slot
/ 64] = linear_vgpr
;
1464 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1465 create
->definitions
[0] = Definition(linear_vgpr
);
1466 /* find the right place to insert this definition */
1467 if (last_top_level_block_idx
== block
.index
) {
1468 /* insert right before the current instruction */
1469 instructions
.emplace_back(std::move(create
));
1471 assert(last_top_level_block_idx
< block
.index
);
1472 /* insert before the branch at last top level block */
1473 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1474 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1478 /* spill sgpr: just add the vgpr temp to operands */
1479 Pseudo_instruction
* spill
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_spill
, Format::PSEUDO
, 3, 0);
1480 spill
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ 64]);
1481 spill
->operands
[1] = Operand(spill_slot
% 64);
1482 spill
->operands
[2] = (*it
)->operands
[0];
1483 instructions
.emplace_back(aco_ptr
<Instruction
>(spill
));
1485 unreachable("No spill slot assigned for spill id");
1488 } else if ((*it
)->opcode
== aco_opcode::p_reload
) {
1489 uint32_t spill_id
= (*it
)->operands
[0].constantValue();
1490 assert(ctx
.is_reloaded
[spill_id
]);
1492 if (vgpr_slot
.find(spill_id
) != vgpr_slot
.end()) {
1494 assert(false && "vgpr spilling not yet implemented.");
1496 } else if (sgpr_slot
.find(spill_id
) != sgpr_slot
.end()) {
1497 uint32_t spill_slot
= sgpr_slot
[spill_id
];
1498 reload_in_loop
[spill_slot
/ 64] = block
.loop_nest_depth
> 0;
1500 /* check if the linear vgpr already exists */
1501 if (vgpr_spill_temps
[spill_slot
/ 64] == Temp()) {
1502 Temp linear_vgpr
= {ctx
.program
->allocateId(), v1
.as_linear()};
1503 vgpr_spill_temps
[spill_slot
/ 64] = linear_vgpr
;
1504 aco_ptr
<Pseudo_instruction
> create
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_start_linear_vgpr
, Format::PSEUDO
, 0, 1)};
1505 create
->definitions
[0] = Definition(linear_vgpr
);
1506 /* find the right place to insert this definition */
1507 if (last_top_level_block_idx
== block
.index
) {
1508 /* insert right before the current instruction */
1509 instructions
.emplace_back(std::move(create
));
1511 assert(last_top_level_block_idx
< block
.index
);
1512 /* insert before the branch at last top level block */
1513 std::vector
<aco_ptr
<Instruction
>>& instructions
= ctx
.program
->blocks
[last_top_level_block_idx
].instructions
;
1514 instructions
.insert(std::next(instructions
.begin(), instructions
.size() - 1), std::move(create
));
1518 /* reload sgpr: just add the vgpr temp to operands */
1519 Pseudo_instruction
* reload
= create_instruction
<Pseudo_instruction
>(aco_opcode::p_reload
, Format::PSEUDO
, 2, 1);
1520 reload
->operands
[0] = Operand(vgpr_spill_temps
[spill_slot
/ 64]);
1521 reload
->operands
[1] = Operand(spill_slot
% 64);
1522 reload
->definitions
[0] = (*it
)->definitions
[0];
1523 instructions
.emplace_back(aco_ptr
<Instruction
>(reload
));
1525 unreachable("No spill slot assigned for spill id");
1527 } else if (!ctx
.remat_used
.count(it
->get()) || ctx
.remat_used
[it
->get()]) {
1528 instructions
.emplace_back(std::move(*it
));
1532 block
.instructions
= std::move(instructions
);
1535 /* SSA elimination inserts copies for logical phis right before p_logical_end
1536 * So if a linear vgpr is used between that p_logical_end and the branch,
1537 * we need to ensure logical phis don't choose a definition which aliases
1539 * TODO: Moving the spills and reloads to before p_logical_end might produce
1540 * slightly better code. */
1541 for (Block
& block
: ctx
.program
->blocks
) {
1542 /* loops exits are already handled */
1543 if (block
.logical_preds
.size() <= 1)
1546 bool has_logical_phis
= false;
1547 for (aco_ptr
<Instruction
>& instr
: block
.instructions
) {
1548 if (instr
->opcode
== aco_opcode::p_phi
) {
1549 has_logical_phis
= true;
1551 } else if (instr
->opcode
!= aco_opcode::p_linear_phi
) {
1555 if (!has_logical_phis
)
1558 std::set
<Temp
> vgprs
;
1559 for (unsigned pred_idx
: block
.logical_preds
) {
1560 Block
& pred
= ctx
.program
->blocks
[pred_idx
];
1561 for (int i
= pred
.instructions
.size() - 1; i
>= 0; i
--) {
1562 aco_ptr
<Instruction
>& pred_instr
= pred
.instructions
[i
];
1563 if (pred_instr
->opcode
== aco_opcode::p_logical_end
) {
1565 } else if (pred_instr
->opcode
== aco_opcode::p_spill
||
1566 pred_instr
->opcode
== aco_opcode::p_reload
) {
1567 vgprs
.insert(pred_instr
->operands
[0].getTemp());
1574 aco_ptr
<Instruction
> destr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_end_linear_vgpr
, Format::PSEUDO
, vgprs
.size(), 0)};
1576 for (Temp tmp
: vgprs
) {
1577 destr
->operands
[k
++] = Operand(tmp
);
1579 /* find insertion point */
1580 std::vector
<aco_ptr
<Instruction
>>::iterator it
= block
.instructions
.begin();
1581 while ((*it
)->opcode
== aco_opcode::p_linear_phi
|| (*it
)->opcode
== aco_opcode::p_phi
)
1583 block
.instructions
.insert(it
, std::move(destr
));
1587 } /* end namespace */
1590 void spill(Program
* program
, live
& live_vars
, const struct radv_nir_compiler_options
*options
)
1592 program
->config
->spilled_vgprs
= 0;
1593 program
->config
->spilled_sgprs
= 0;
1595 /* no spilling when register pressure is low enough */
1596 if (program
->num_waves
> 0)
1599 /* lower to CSSA before spilling to ensure correctness w.r.t. phis */
1600 lower_to_cssa(program
, live_vars
, options
);
1602 /* calculate target register demand */
1603 RegisterDemand register_target
= program
->max_reg_demand
;
1604 if (register_target
.sgpr
> program
->sgpr_limit
)
1605 register_target
.vgpr
+= (register_target
.sgpr
- program
->sgpr_limit
+ 63 + 32) / 64;
1606 register_target
.sgpr
= program
->sgpr_limit
;
1608 if (register_target
.vgpr
> program
->vgpr_limit
)
1609 register_target
.sgpr
= program
->sgpr_limit
- 5;
1610 register_target
.vgpr
= program
->vgpr_limit
- (register_target
.vgpr
- program
->max_reg_demand
.vgpr
);
1612 int spills_to_vgpr
= (program
->max_reg_demand
.sgpr
- register_target
.sgpr
+ 63 + 32) / 64;
1614 /* initialize ctx */
1615 spill_ctx
ctx(register_target
, program
, live_vars
.register_demand
);
1616 compute_global_next_uses(ctx
, live_vars
.live_out
);
1617 get_rematerialize_info(ctx
);
1619 /* create spills and reloads */
1620 for (unsigned i
= 0; i
< program
->blocks
.size(); i
++)
1621 spill_block(ctx
, i
);
1623 /* assign spill slots and DCE rematerialized code */
1624 assign_spill_slots(ctx
, spills_to_vgpr
);
1626 /* update live variable information */
1627 live_vars
= live_var_analysis(program
, options
);
1629 assert(program
->num_waves
>= 0);