src/amd/compiler/aco_validate.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "aco_ir.h"
  26
  27 #include <array>
  28 #include <map>
  29
  30 namespace aco {
  31
  32 #ifndef NDEBUG
  33 void perfwarn(bool cond, const char *msg, Instruction *instr)
  34 {
  35    if (cond) {
  36       fprintf(stderr, "ACO performance warning: %s\n", msg);
  37       if (instr) {
  38          fprintf(stderr, "instruction: ");
  39          aco_print_instr(instr, stderr);
  40          fprintf(stderr, "\n");
  41       }
  42
  43       if (debug_flags & DEBUG_PERFWARN)
  44          exit(1);
  45    }
  46 }
  47 #endif
  48
  49 void validate(Program* program, FILE * output)
  50 {
  51    if (!(debug_flags & DEBUG_VALIDATE))
  52       return;
  53
  54    bool is_valid = true;
  55    auto check = [&output, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void {
  56       if (!check) {
  57          fprintf(output, "%s: ", msg);
  58          aco_print_instr(instr, output);
  59          fprintf(output, "\n");
  60          is_valid = false;
  61       }
  62    };
  63    auto check_block = [&output, &is_valid](bool check, const char * msg, aco::Block * block) -> void {
  64       if (!check) {
  65          fprintf(output, "%s: BB%u\n", msg, block->index);
  66          is_valid = false;
  67       }
  68    };
  69
  70    for (Block& block : program->blocks) {
  71       for (aco_ptr<Instruction>& instr : block.instructions) {
  72
  73          /* check base format */
  74          Format base_format = instr->format;
  75          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::SDWA);
  76          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::DPP);
  77          if ((uint32_t)base_format & (uint32_t)Format::VOP1)
  78             base_format = Format::VOP1;
  79          else if ((uint32_t)base_format & (uint32_t)Format::VOP2)
  80             base_format = Format::VOP2;
  81          else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
  82             base_format = Format::VOPC;
  83          else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) {
  84             if (instr->opcode == aco_opcode::v_interp_p1ll_f16 ||
  85                 instr->opcode == aco_opcode::v_interp_p1lv_f16 ||
  86                 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
  87                 instr->opcode == aco_opcode::v_interp_p2_f16) {
  88                /* v_interp_*_fp16 are considered VINTRP by the compiler but
  89                 * they are emitted as VOP3.
  90                 */
  91                base_format = Format::VOP3;
  92             } else {
  93                base_format = Format::VINTRP;
  94             }
  95          }
  96          check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
  97
  98          /* check VOP3 modifiers */
  99          if (((uint32_t)instr->format & (uint32_t)Format::VOP3) && instr->format != Format::VOP3) {
 100             check(base_format == Format::VOP2 ||
 101                   base_format == Format::VOP1 ||
 102                   base_format == Format::VOPC ||
 103                   base_format == Format::VINTRP,
 104                   "Format cannot have VOP3A/VOP3B applied", instr.get());
 105          }
 106
 107          /* check SDWA */
 108          if (instr->isSDWA()) {
 109             check(base_format == Format::VOP2 ||
 110                   base_format == Format::VOP1 ||
 111                   base_format == Format::VOPC,
 112                   "Format cannot have SDWA applied", instr.get());
 113
 114             check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
 115
 116             SDWA_instruction *sdwa = static_cast<SDWA_instruction*>(instr.get());
 117             check(sdwa->omod == 0 || program->chip_class >= GFX9, "SDWA omod only supported on GFX9+", instr.get());
 118             if (base_format == Format::VOPC) {
 119                check(sdwa->clamp == false || program->chip_class == GFX8, "SDWA VOPC clamp only supported on GFX8", instr.get());
 120                check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
 121                      program->chip_class >= GFX9,
 122                      "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
 123             }
 124
 125             if (instr->operands.size() >= 3) {
 126                check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
 127                      "3rd operand must be fixed to vcc with SDWA", instr.get());
 128             }
 129             if (instr->definitions.size() >= 2) {
 130                check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
 131                      "2nd definition must be fixed to vcc with SDWA", instr.get());
 132             }
 133
 134             check(instr->opcode != aco_opcode::v_madmk_f32 &&
 135                   instr->opcode != aco_opcode::v_madak_f32 &&
 136                   instr->opcode != aco_opcode::v_madmk_f16 &&
 137                   instr->opcode != aco_opcode::v_madak_f16 &&
 138                   instr->opcode != aco_opcode::v_readfirstlane_b32 &&
 139                   instr->opcode != aco_opcode::v_clrexcp &&
 140                   instr->opcode != aco_opcode::v_swap_b32,
 141                   "SDWA can't be used with this opcode", instr.get());
 142             if (program->chip_class != GFX8) {
 143                check(instr->opcode != aco_opcode::v_mac_f32 &&
 144                      instr->opcode != aco_opcode::v_mac_f16 &&
 145                      instr->opcode != aco_opcode::v_fmac_f32 &&
 146                      instr->opcode != aco_opcode::v_fmac_f16,
 147                      "SDWA can't be used with this opcode", instr.get());
 148             }
 149
 150             for (unsigned i = 0; i < MIN2(instr->operands.size(), 2); i++) {
 151                if (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword())
 152                   check((sdwa->sel[i] & sdwa_asuint) == (sdwa_isra | instr->operands[i].bytes()), "Unexpected SDWA sel for sub-dword operand", instr.get());
 153             }
 154             if (instr->definitions[0].regClass().is_subdword())
 155                check((sdwa->dst_sel & sdwa_asuint) == (sdwa_isra | instr->definitions[0].bytes()), "Unexpected SDWA sel for sub-dword definition", instr.get());
 156          }
 157
 158          /* check opsel */
 159          if (instr->isVOP3()) {
 160             VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
 161             check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
 162
 163             for (unsigned i = 0; i < 3; i++) {
 164                if (i >= instr->operands.size() ||
 165                    (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()))
 166                   check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get());
 167             }
 168             if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed())
 169                check((vop3->opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr.get());
 170          }
 171
 172          /* check for undefs */
 173          for (unsigned i = 0; i < instr->operands.size(); i++) {
 174             if (instr->operands[i].isUndefined()) {
 175                bool flat = instr->format == Format::FLAT || instr->format == Format::SCRATCH || instr->format == Format::GLOBAL;
 176                bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
 177                                    instr->format == Format::PSEUDO_REDUCTION ||
 178                                    instr->opcode == aco_opcode::p_create_vector ||
 179                                    (flat && i == 1) || (instr->format == Format::MIMG && i == 1) ||
 180                                    ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1);
 181                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
 182             } else {
 183                check(instr->operands[i].isFixed() || instr->operands[i].isTemp() || instr->operands[i].isConstant(), "Uninitialized Operand", instr.get());
 184             }
 185          }
 186
 187          /* check subdword definitions */
 188          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 189             if (instr->definitions[i].regClass().is_subdword())
 190                check(instr->format == Format::PSEUDO || instr->definitions[i].bytes() <= 4, "Only Pseudo instructions can write subdword registers larger than 4 bytes", instr.get());
 191          }
 192
 193          if (instr->isSALU() || instr->isVALU()) {
 194             /* check literals */
 195             Operand literal(s1);
 196             for (unsigned i = 0; i < instr->operands.size(); i++)
 197             {
 198                Operand op = instr->operands[i];
 199                if (!op.isLiteral())
 200                   continue;
 201
 202                check(instr->format == Format::SOP1 ||
 203                      instr->format == Format::SOP2 ||
 204                      instr->format == Format::SOPC ||
 205                      instr->format == Format::VOP1 ||
 206                      instr->format == Format::VOP2 ||
 207                      instr->format == Format::VOPC ||
 208                      (instr->isVOP3() && program->chip_class >= GFX10),
 209                      "Literal applied on wrong instruction format", instr.get());
 210
 211                check(literal.isUndefined() || (literal.size() == op.size() && literal.constantValue() == op.constantValue()), "Only 1 Literal allowed", instr.get());
 212                literal = op;
 213                check(!instr->isVALU() || instr->isVOP3() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
 214             }
 215
 216             /* check num sgprs for VALU */
 217             if (instr->isVALU()) {
 218                bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
 219                                  instr->opcode == aco_opcode::v_lshrrev_b64 ||
 220                                  instr->opcode == aco_opcode::v_ashrrev_i64;
 221                unsigned const_bus_limit = 1;
 222                if (program->chip_class >= GFX10 && !is_shift64)
 223                   const_bus_limit = 2;
 224
 225                uint32_t scalar_mask = instr->isVOP3() ? 0x7 : 0x5;
 226                if (instr->isSDWA())
 227                   scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
 228
 229                if ((int) instr->format & (int) Format::VOPC ||
 230                    instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 231                    instr->opcode == aco_opcode::v_readlane_b32 ||
 232                    instr->opcode == aco_opcode::v_readlane_b32_e64) {
 233                   check(instr->definitions[0].getTemp().type() == RegType::sgpr,
 234                         "Wrong Definition type for VALU instruction", instr.get());
 235                } else {
 236                   check(instr->definitions[0].getTemp().type() == RegType::vgpr,
 237                         "Wrong Definition type for VALU instruction", instr.get());
 238                }
 239
 240                unsigned num_sgprs = 0;
 241                unsigned sgpr[] = {0, 0};
 242                for (unsigned i = 0; i < instr->operands.size(); i++)
 243                {
 244                   Operand op = instr->operands[i];
 245                   if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 246                       instr->opcode == aco_opcode::v_readlane_b32 ||
 247                       instr->opcode == aco_opcode::v_readlane_b32_e64) {
 248                      check(i != 1 ||
 249                            (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
 250                            op.isConstant(),
 251                            "Must be a SGPR or a constant", instr.get());
 252                      check(i == 1 ||
 253                            (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
 254                            "Wrong Operand type for VALU instruction", instr.get());
 255                      continue;
 256                   }
 257
 258                   if (instr->opcode == aco_opcode::v_writelane_b32 ||
 259                       instr->opcode == aco_opcode::v_writelane_b32_e64) {
 260                      check(i != 2 ||
 261                            (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
 262                            "Wrong Operand type for VALU instruction", instr.get());
 263                      check(i == 2 ||
 264                            (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
 265                            op.isConstant(),
 266                            "Must be a SGPR or a constant", instr.get());
 267                      continue;
 268                   }
 269                   if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
 270                      check(scalar_mask & (1 << i), "Wrong source position for SGPR argument", instr.get());
 271
 272                      if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
 273                         if (num_sgprs < 2)
 274                            sgpr[num_sgprs++] = op.tempId();
 275                      }
 276                   }
 277
 278                   if (op.isConstant() && !op.isLiteral())
 279                      check(scalar_mask & (1 << i), "Wrong source position for constant argument", instr.get());
 280                }
 281                check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, "Too many SGPRs/literals", instr.get());
 282             }
 283
 284             if (instr->format == Format::SOP1 || instr->format == Format::SOP2) {
 285                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "Wrong Definition type for SALU instruction", instr.get());
 286                for (const Operand& op : instr->operands) {
 287                  check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
 288                        "Wrong Operand type for SALU instruction", instr.get());
 289             }
 290          }
 291          }
 292
 293          switch (instr->format) {
 294          case Format::PSEUDO: {
 295             bool is_subdword = false;
 296             bool has_const_sgpr = false;
 297             bool has_literal = false;
 298             for (Definition def : instr->definitions)
 299                is_subdword |= def.regClass().is_subdword();
 300             for (unsigned i = 0; i < instr->operands.size(); i++) {
 301                if (instr->opcode == aco_opcode::p_extract_vector && i == 1)
 302                   continue;
 303                Operand op = instr->operands[i];
 304                is_subdword |= op.hasRegClass() && op.regClass().is_subdword();
 305                has_const_sgpr |= op.isConstant() || (op.hasRegClass() && op.regClass().type() == RegType::sgpr);
 306                has_literal |= op.isLiteral();
 307             }
 308
 309             check(!is_subdword || !has_const_sgpr || program->chip_class >= GFX9,
 310                   "Sub-dword pseudo instructions can only take constants or SGPRs on GFX9+", instr.get());
 311             check(!is_subdword || !has_literal, "Sub-dword pseudo instructions cannot take literals", instr.get());
 312
 313             if (instr->opcode == aco_opcode::p_create_vector) {
 314                unsigned size = 0;
 315                for (const Operand& op : instr->operands) {
 316                   size += op.bytes();
 317                }
 318                check(size == instr->definitions[0].bytes(), "Definition size does not match operand sizes", instr.get());
 319                if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
 320                   for (const Operand& op : instr->operands) {
 321                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
 322                            "Wrong Operand type for scalar vector", instr.get());
 323                   }
 324                }
 325             } else if (instr->opcode == aco_opcode::p_extract_vector) {
 326                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
 327                check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <= instr->operands[0].bytes(), "Index out of range", instr.get());
 328                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
 329                      "Cannot extract SGPR value from VGPR vector", instr.get());
 330             } else if (instr->opcode == aco_opcode::p_parallelcopy) {
 331                check(instr->definitions.size() == instr->operands.size(), "Number of Operands does not match number of Definitions", instr.get());
 332                for (unsigned i = 0; i < instr->operands.size(); i++) {
 333                   if (instr->operands[i].isTemp())
 334                      check((instr->definitions[i].getTemp().type() == instr->operands[i].regClass().type()) ||
 335                            (instr->definitions[i].getTemp().type() == RegType::vgpr && instr->operands[i].regClass().type() == RegType::sgpr),
 336                            "Operand and Definition types do not match", instr.get());
 337                }
 338             } else if (instr->opcode == aco_opcode::p_phi) {
 339                check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 340                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "Logical Phi Definition must be vgpr", instr.get());
 341             } else if (instr->opcode == aco_opcode::p_linear_phi) {
 342                for (const Operand& op : instr->operands)
 343                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get());
 344                check(instr->operands.size() == block.linear_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 345             }
 346             break;
 347          }
 348          case Format::SMEM: {
 349             if (instr->operands.size() >= 1)
 350                check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "SMEM operands must be sgpr", instr.get());
 351             if (instr->operands.size() >= 2)
 352                check(instr->operands[1].isConstant() || (instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr),
 353                      "SMEM offset must be constant or sgpr", instr.get());
 354             if (!instr->definitions.empty())
 355                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "SMEM result must be sgpr", instr.get());
 356             break;
 357          }
 358          case Format::MTBUF:
 359          case Format::MUBUF: {
 360             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand", instr.get());
 361             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr,
 362                   "VADDR must be in vgpr for VMEM instructions", instr.get());
 363             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
 364             check(instr->operands.size() < 4 || (instr->operands[3].isTemp() && instr->operands[3].regClass().type() == RegType::vgpr), "VMEM write data must be vgpr", instr.get());
 365             break;
 366          }
 367          case Format::MIMG: {
 368             check(instr->operands.size() == 3, "MIMG instructions must have exactly 3 operands", instr.get());
 369             check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
 370                   "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
 371             if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr)
 372                check(instr->operands[1].regClass() == s4, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
 373             else if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr)
 374                check((instr->definitions.empty() || instr->definitions[0].regClass() == instr->operands[1].regClass() ||
 375                      instr->opcode == aco_opcode::image_atomic_cmpswap || instr->opcode == aco_opcode::image_atomic_fcmpswap),
 376                      "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr.get());
 377             check(instr->operands[2].hasRegClass() && instr->operands[2].regClass().type() == RegType::vgpr,
 378                   "MIMG operands[2] (VADDR) must be VGPR", instr.get());
 379             check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
 380                   "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
 381             break;
 382          }
 383          case Format::DS: {
 384             for (const Operand& op : instr->operands) {
 385                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
 386                      "Only VGPRs are valid DS instruction operands", instr.get());
 387             }
 388             if (!instr->definitions.empty())
 389                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "DS instruction must return VGPR", instr.get());
 390             break;
 391          }
 392          case Format::EXP: {
 393             for (unsigned i = 0; i < 4; i++)
 394                check(instr->operands[i].hasRegClass() && instr->operands[i].regClass().type() == RegType::vgpr,
 395                      "Only VGPRs are valid Export arguments", instr.get());
 396             break;
 397          }
 398          case Format::FLAT:
 399             check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR", instr.get());
 400             /* fallthrough */
 401          case Format::GLOBAL:
 402          case Format::SCRATCH: {
 403             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr.get());
 404             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr,
 405                   "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr.get());
 406             if (!instr->definitions.empty())
 407                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr.get());
 408             else
 409                check(instr->operands[2].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr.get());
 410             break;
 411          }
 412          default:
 413             break;
 414          }
 415       }
 416    }
 417
 418    /* validate CFG */
 419    for (unsigned i = 0; i < program->blocks.size(); i++) {
 420       Block& block = program->blocks[i];
 421       check_block(block.index == i, "block.index must match actual index", &block);
 422
 423       /* predecessors/successors should be sorted */
 424       for (unsigned j = 0; j + 1 < block.linear_preds.size(); j++)
 425          check_block(block.linear_preds[j] < block.linear_preds[j + 1], "linear predecessors must be sorted", &block);
 426       for (unsigned j = 0; j + 1 < block.logical_preds.size(); j++)
 427          check_block(block.logical_preds[j] < block.logical_preds[j + 1], "logical predecessors must be sorted", &block);
 428       for (unsigned j = 0; j + 1 < block.linear_succs.size(); j++)
 429          check_block(block.linear_succs[j] < block.linear_succs[j + 1], "linear successors must be sorted", &block);
 430       for (unsigned j = 0; j + 1 < block.logical_succs.size(); j++)
 431          check_block(block.logical_succs[j] < block.logical_succs[j + 1], "logical successors must be sorted", &block);
 432
 433       /* critical edges are not allowed */
 434       if (block.linear_preds.size() > 1) {
 435          for (unsigned pred : block.linear_preds)
 436             check_block(program->blocks[pred].linear_succs.size() == 1, "linear critical edges are not allowed", &program->blocks[pred]);
 437          for (unsigned pred : block.logical_preds)
 438             check_block(program->blocks[pred].logical_succs.size() == 1, "logical critical edges are not allowed", &program->blocks[pred]);
 439       }
 440    }
 441
 442    assert(is_valid);
 443 }
 444
 445 /* RA validation */
 446 namespace {
 447
 448 struct Location {
 449    Location() : block(NULL), instr(NULL) {}
 450
 451    Block *block;
 452    Instruction *instr; //NULL if it's the block's live-in
 453 };
 454
 455 struct Assignment {
 456    Location defloc;
 457    Location firstloc;
 458    PhysReg reg;
 459 };
 460
 461 bool ra_fail(FILE *output, Location loc, Location loc2, const char *fmt, ...) {
 462    va_list args;
 463    va_start(args, fmt);
 464    char msg[1024];
 465    vsprintf(msg, fmt, args);
 466    va_end(args);
 467
 468    fprintf(stderr, "RA error found at instruction in BB%d:\n", loc.block->index);
 469    if (loc.instr) {
 470       aco_print_instr(loc.instr, stderr);
 471       fprintf(stderr, "\n%s", msg);
 472    } else {
 473       fprintf(stderr, "%s", msg);
 474    }
 475    if (loc2.block) {
 476       fprintf(stderr, " in BB%d:\n", loc2.block->index);
 477       aco_print_instr(loc2.instr, stderr);
 478    }
 479    fprintf(stderr, "\n\n");
 480
 481    return true;
 482 }
 483
 484 bool validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, unsigned index)
 485 {
 486    Operand op = instr->operands[index];
 487    unsigned byte = op.physReg().byte();
 488
 489    if (instr->format == Format::PSEUDO && chip >= GFX8)
 490       return true;
 491    if (instr->isSDWA() && (static_cast<SDWA_instruction *>(instr.get())->sel[index] & sdwa_asuint) == (sdwa_isra | op.bytes()))
 492       return true;
 493    if (byte == 2 && can_use_opsel(chip, instr->opcode, index, 1))
 494       return true;
 495
 496    switch (instr->opcode) {
 497    case aco_opcode::v_cvt_f32_ubyte1:
 498       if (byte == 1)
 499          return true;
 500       break;
 501    case aco_opcode::v_cvt_f32_ubyte2:
 502       if (byte == 2)
 503          return true;
 504       break;
 505    case aco_opcode::v_cvt_f32_ubyte3:
 506       if (byte == 3)
 507          return true;
 508       break;
 509    case aco_opcode::ds_write_b8_d16_hi:
 510    case aco_opcode::ds_write_b16_d16_hi:
 511       if (byte == 2 && index == 1)
 512          return true;
 513       break;
 514    case aco_opcode::buffer_store_byte_d16_hi:
 515    case aco_opcode::buffer_store_short_d16_hi:
 516       if (byte == 2 && index == 3)
 517          return true;
 518       break;
 519    case aco_opcode::flat_store_byte_d16_hi:
 520    case aco_opcode::flat_store_short_d16_hi:
 521    case aco_opcode::scratch_store_byte_d16_hi:
 522    case aco_opcode::scratch_store_short_d16_hi:
 523    case aco_opcode::global_store_byte_d16_hi:
 524    case aco_opcode::global_store_short_d16_hi:
 525       if (byte == 2 && index == 2)
 526          return true;
 527    default:
 528       break;
 529    }
 530
 531    return byte == 0;
 532 }
 533
 534 bool validate_subdword_definition(chip_class chip, const aco_ptr<Instruction>& instr)
 535 {
 536    Definition def = instr->definitions[0];
 537    unsigned byte = def.physReg().byte();
 538
 539    if (instr->format == Format::PSEUDO && chip >= GFX8)
 540       return true;
 541    if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
 542       return true;
 543    if (byte == 2 && can_use_opsel(chip, instr->opcode, -1, 1))
 544       return true;
 545
 546    switch (instr->opcode) {
 547    case aco_opcode::buffer_load_ubyte_d16_hi:
 548    case aco_opcode::buffer_load_short_d16_hi:
 549    case aco_opcode::flat_load_ubyte_d16_hi:
 550    case aco_opcode::flat_load_short_d16_hi:
 551    case aco_opcode::scratch_load_ubyte_d16_hi:
 552    case aco_opcode::scratch_load_short_d16_hi:
 553    case aco_opcode::global_load_ubyte_d16_hi:
 554    case aco_opcode::global_load_short_d16_hi:
 555    case aco_opcode::ds_read_u8_d16_hi:
 556    case aco_opcode::ds_read_u16_d16_hi:
 557       return byte == 2;
 558    default:
 559       break;
 560    }
 561
 562    return byte == 0;
 563 }
 564
 565 unsigned get_subdword_bytes_written(Program *program, const aco_ptr<Instruction>& instr, unsigned index)
 566 {
 567    chip_class chip = program->chip_class;
 568    Definition def = instr->definitions[index];
 569
 570    if (instr->format == Format::PSEUDO)
 571       return chip >= GFX8 ? def.bytes() : def.size() * 4u;
 572    if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
 573       return def.bytes();
 574
 575    switch (instr->opcode) {
 576    case aco_opcode::buffer_load_ubyte_d16:
 577    case aco_opcode::buffer_load_short_d16:
 578    case aco_opcode::flat_load_ubyte_d16:
 579    case aco_opcode::flat_load_short_d16:
 580    case aco_opcode::scratch_load_ubyte_d16:
 581    case aco_opcode::scratch_load_short_d16:
 582    case aco_opcode::global_load_ubyte_d16:
 583    case aco_opcode::global_load_short_d16:
 584    case aco_opcode::ds_read_u8_d16:
 585    case aco_opcode::ds_read_u16_d16:
 586    case aco_opcode::buffer_load_ubyte_d16_hi:
 587    case aco_opcode::buffer_load_short_d16_hi:
 588    case aco_opcode::flat_load_ubyte_d16_hi:
 589    case aco_opcode::flat_load_short_d16_hi:
 590    case aco_opcode::scratch_load_ubyte_d16_hi:
 591    case aco_opcode::scratch_load_short_d16_hi:
 592    case aco_opcode::global_load_ubyte_d16_hi:
 593    case aco_opcode::global_load_short_d16_hi:
 594    case aco_opcode::ds_read_u8_d16_hi:
 595    case aco_opcode::ds_read_u16_d16_hi:
 596       return program->sram_ecc_enabled ? 4 : 2;
 597    case aco_opcode::v_mad_f16:
 598    case aco_opcode::v_mad_u16:
 599    case aco_opcode::v_mad_i16:
 600    case aco_opcode::v_fma_f16:
 601    case aco_opcode::v_div_fixup_f16:
 602    case aco_opcode::v_interp_p2_f16:
 603       if (chip >= GFX9)
 604          return 2;
 605    default:
 606       break;
 607    }
 608
 609    return MAX2(chip >= GFX10 ? def.bytes() : 4, instr_info.definition_size[(int)instr->opcode] / 8u);
 610 }
 611
 612 } /* end namespace */
 613
 614 bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) {
 615    if (!(debug_flags & DEBUG_VALIDATE_RA))
 616       return false;
 617
 618    bool err = false;
 619    aco::live live_vars = aco::live_var_analysis(program, options);
 620    std::vector<std::vector<Temp>> phi_sgpr_ops(program->blocks.size());
 621
 622    std::map<unsigned, Assignment> assignments;
 623    for (Block& block : program->blocks) {
 624       Location loc;
 625       loc.block = &block;
 626       for (aco_ptr<Instruction>& instr : block.instructions) {
 627          if (instr->opcode == aco_opcode::p_phi) {
 628             for (unsigned i = 0; i < instr->operands.size(); i++) {
 629                if (instr->operands[i].isTemp() &&
 630                    instr->operands[i].getTemp().type() == RegType::sgpr &&
 631                    instr->operands[i].isFirstKill())
 632                   phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
 633             }
 634          }
 635
 636          loc.instr = instr.get();
 637          for (unsigned i = 0; i < instr->operands.size(); i++) {
 638             Operand& op = instr->operands[i];
 639             if (!op.isTemp())
 640                continue;
 641             if (!op.isFixed())
 642                err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i);
 643             if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
 644                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
 645             if ((op.getTemp().type() == RegType::vgpr && op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) ||
 646                 (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
 647                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
 648             if (op.physReg() == vcc && !program->needs_vcc)
 649                err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i);
 650             if (op.regClass().is_subdword() && !validate_subdword_operand(program->chip_class, instr, i))
 651                err |= ra_fail(output, loc, Location(), "Operand %d not aligned correctly", i);
 652             if (!assignments[op.tempId()].firstloc.block)
 653                assignments[op.tempId()].firstloc = loc;
 654             if (!assignments[op.tempId()].defloc.block)
 655                assignments[op.tempId()].reg = op.physReg();
 656          }
 657
 658          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 659             Definition& def = instr->definitions[i];
 660             if (!def.isTemp())
 661                continue;
 662             if (!def.isFixed())
 663                err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i);
 664             if (assignments[def.tempId()].defloc.block)
 665                err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
 666             if ((def.getTemp().type() == RegType::vgpr && def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) ||
 667                 (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
 668                err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
 669             if (def.physReg() == vcc && !program->needs_vcc)
 670                err |= ra_fail(output, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i);
 671             if (def.regClass().is_subdword() && !validate_subdword_definition(program->chip_class, instr))
 672                err |= ra_fail(output, loc, Location(), "Definition %d not aligned correctly", i);
 673             if (!assignments[def.tempId()].firstloc.block)
 674                assignments[def.tempId()].firstloc = loc;
 675             assignments[def.tempId()].defloc = loc;
 676             assignments[def.tempId()].reg = def.physReg();
 677          }
 678       }
 679    }
 680
 681    for (Block& block : program->blocks) {
 682       Location loc;
 683       loc.block = &block;
 684
 685       std::array<unsigned, 2048> regs; /* register file in bytes */
 686       regs.fill(0);
 687
 688       std::set<Temp> live;
 689       live.insert(live_vars.live_out[block.index].begin(), live_vars.live_out[block.index].end());
 690       /* remove killed p_phi sgpr operands */
 691       for (Temp tmp : phi_sgpr_ops[block.index])
 692          live.erase(tmp);
 693
 694       /* check live out */
 695       for (Temp tmp : live) {
 696          PhysReg reg = assignments.at(tmp.id()).reg;
 697          for (unsigned i = 0; i < tmp.bytes(); i++) {
 698             if (regs[reg.reg_b + i]) {
 699                err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 700             }
 701             regs[reg.reg_b + i] = tmp.id();
 702          }
 703       }
 704       regs.fill(0);
 705
 706       for (auto it = block.instructions.rbegin(); it != block.instructions.rend(); ++it) {
 707          aco_ptr<Instruction>& instr = *it;
 708
 709          /* check killed p_phi sgpr operands */
 710          if (instr->opcode == aco_opcode::p_logical_end) {
 711             for (Temp tmp : phi_sgpr_ops[block.index]) {
 712                PhysReg reg = assignments.at(tmp.id()).reg;
 713                for (unsigned i = 0; i < tmp.bytes(); i++) {
 714                   if (regs[reg.reg_b + i])
 715                      err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 716                }
 717                live.emplace(tmp);
 718             }
 719          }
 720
 721          for (const Definition& def : instr->definitions) {
 722             if (!def.isTemp())
 723                continue;
 724             live.erase(def.getTemp());
 725          }
 726
 727          /* don't count phi operands as live-in, since they are actually
 728           * killed when they are copied at the predecessor */
 729          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 730             for (const Operand& op : instr->operands) {
 731                if (!op.isTemp())
 732                   continue;
 733                live.insert(op.getTemp());
 734             }
 735          }
 736       }
 737
 738       for (Temp tmp : live) {
 739          PhysReg reg = assignments.at(tmp.id()).reg;
 740          for (unsigned i = 0; i < tmp.bytes(); i++)
 741             regs[reg.reg_b + i] = tmp.id();
 742       }
 743
 744       for (aco_ptr<Instruction>& instr : block.instructions) {
 745          loc.instr = instr.get();
 746
 747          /* remove killed p_phi operands from regs */
 748          if (instr->opcode == aco_opcode::p_logical_end) {
 749             for (Temp tmp : phi_sgpr_ops[block.index]) {
 750                PhysReg reg = assignments.at(tmp.id()).reg;
 751                for (unsigned i = 0; i < tmp.bytes(); i++)
 752                   regs[reg.reg_b + i] = 0;
 753             }
 754          }
 755
 756          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 757             for (const Operand& op : instr->operands) {
 758                if (!op.isTemp())
 759                   continue;
 760                if (op.isFirstKillBeforeDef()) {
 761                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 762                      regs[op.physReg().reg_b + j] = 0;
 763                }
 764             }
 765          }
 766
 767          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 768             Definition& def = instr->definitions[i];
 769             if (!def.isTemp())
 770                continue;
 771             Temp tmp = def.getTemp();
 772             PhysReg reg = assignments.at(tmp.id()).reg;
 773             for (unsigned j = 0; j < tmp.bytes(); j++) {
 774                if (regs[reg.reg_b + j])
 775                   err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
 776                regs[reg.reg_b + j] = tmp.id();
 777             }
 778             if (def.regClass().is_subdword() && def.bytes() < 4) {
 779                unsigned written = get_subdword_bytes_written(program, instr, i);
 780                /* If written=4, the instruction still might write the upper half. In that case, it's the lower half that isn't preserved */
 781                for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) {
 782                   unsigned written_reg = reg.reg() * 4u + j;
 783                   if (regs[written_reg] && regs[written_reg] != def.tempId())
 784                      err |= ra_fail(output, loc, assignments.at(regs[written_reg]).defloc, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i, tmp.id(), regs[written_reg]);
 785                }
 786             }
 787          }
 788
 789          for (const Definition& def : instr->definitions) {
 790             if (!def.isTemp())
 791                continue;
 792             if (def.isKill()) {
 793                for (unsigned j = 0; j < def.getTemp().bytes(); j++)
 794                   regs[def.physReg().reg_b + j] = 0;
 795             }
 796          }
 797
 798          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 799             for (const Operand& op : instr->operands) {
 800                if (!op.isTemp())
 801                   continue;
 802                if (op.isLateKill() && op.isFirstKill()) {
 803                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 804                      regs[op.physReg().reg_b + j] = 0;
 805                }
 806             }
 807          }
 808       }
 809    }
 810
 811    return err;
 812 }
 813 }