src/amd/compiler/aco_validate.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "aco_ir.h"
  26
  27 #include <array>
  28 #include <map>
  29
  30 namespace aco {
  31
  32 #ifndef NDEBUG
  33 void perfwarn(bool cond, const char *msg, Instruction *instr)
  34 {
  35    if (cond) {
  36       fprintf(stderr, "ACO performance warning: %s\n", msg);
  37       if (instr) {
  38          fprintf(stderr, "instruction: ");
  39          aco_print_instr(instr, stderr);
  40          fprintf(stderr, "\n");
  41       }
  42
  43       if (debug_flags & DEBUG_PERFWARN)
  44          exit(1);
  45    }
  46 }
  47 #endif
  48
  49 void validate(Program* program, FILE * output)
  50 {
  51    if (!(debug_flags & DEBUG_VALIDATE))
  52       return;
  53
  54    bool is_valid = true;
  55    auto check = [&output, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void {
  56       if (!check) {
  57          fprintf(output, "%s: ", msg);
  58          aco_print_instr(instr, output);
  59          fprintf(output, "\n");
  60          is_valid = false;
  61       }
  62    };
  63    auto check_block = [&output, &is_valid](bool check, const char * msg, aco::Block * block) -> void {
  64       if (!check) {
  65          fprintf(output, "%s: BB%u\n", msg, block->index);
  66          is_valid = false;
  67       }
  68    };
  69
  70    for (Block& block : program->blocks) {
  71       for (aco_ptr<Instruction>& instr : block.instructions) {
  72
  73          /* check base format */
  74          Format base_format = instr->format;
  75          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::SDWA);
  76          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::DPP);
  77          if ((uint32_t)base_format & (uint32_t)Format::VOP1)
  78             base_format = Format::VOP1;
  79          else if ((uint32_t)base_format & (uint32_t)Format::VOP2)
  80             base_format = Format::VOP2;
  81          else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
  82             base_format = Format::VOPC;
  83          else if ((uint32_t)base_format & (uint32_t)Format::VINTRP)
  84             base_format = Format::VINTRP;
  85          check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
  86
  87          /* check VOP3 modifiers */
  88          if (((uint32_t)instr->format & (uint32_t)Format::VOP3) && instr->format != Format::VOP3) {
  89             check(base_format == Format::VOP2 ||
  90                   base_format == Format::VOP1 ||
  91                   base_format == Format::VOPC ||
  92                   base_format == Format::VINTRP,
  93                   "Format cannot have VOP3A/VOP3B applied", instr.get());
  94          }
  95
  96          /* check SDWA */
  97          if (instr->isSDWA()) {
  98             check(base_format == Format::VOP2 ||
  99                   base_format == Format::VOP1 ||
 100                   base_format == Format::VOPC,
 101                   "Format cannot have SDWA applied", instr.get());
 102
 103             check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
 104
 105             SDWA_instruction *sdwa = static_cast<SDWA_instruction*>(instr.get());
 106             check(sdwa->omod == 0 || program->chip_class >= GFX9, "SDWA omod only supported on GFX9+", instr.get());
 107             if (base_format == Format::VOPC) {
 108                check(sdwa->clamp == false || program->chip_class == GFX8, "SDWA VOPC clamp only supported on GFX8", instr.get());
 109                check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
 110                      program->chip_class >= GFX9,
 111                      "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
 112             }
 113
 114             if (instr->operands.size() >= 3) {
 115                check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
 116                      "3rd operand must be fixed to vcc with SDWA", instr.get());
 117             }
 118             if (instr->definitions.size() >= 2) {
 119                check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
 120                      "2nd definition must be fixed to vcc with SDWA", instr.get());
 121             }
 122
 123             check(instr->opcode != aco_opcode::v_madmk_f32 &&
 124                   instr->opcode != aco_opcode::v_madak_f32 &&
 125                   instr->opcode != aco_opcode::v_madmk_f16 &&
 126                   instr->opcode != aco_opcode::v_madak_f16 &&
 127                   instr->opcode != aco_opcode::v_readfirstlane_b32 &&
 128                   instr->opcode != aco_opcode::v_clrexcp &&
 129                   instr->opcode != aco_opcode::v_swap_b32,
 130                   "SDWA can't be used with this opcode", instr.get());
 131             if (program->chip_class != GFX8) {
 132                check(instr->opcode != aco_opcode::v_mac_f32 &&
 133                      instr->opcode != aco_opcode::v_mac_f16 &&
 134                      instr->opcode != aco_opcode::v_fmac_f32 &&
 135                      instr->opcode != aco_opcode::v_fmac_f16,
 136                      "SDWA can't be used with this opcode", instr.get());
 137             }
 138          }
 139
 140          /* check opsel */
 141          if (instr->isVOP3()) {
 142             VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
 143             check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
 144             check((vop3->opsel & ~(0x10 | ((1 << instr->operands.size()) - 1))) == 0, "Unused bits in opsel must be zeroed out", instr.get());
 145          }
 146
 147          /* check for undefs */
 148          for (unsigned i = 0; i < instr->operands.size(); i++) {
 149             if (instr->operands[i].isUndefined()) {
 150                bool flat = instr->format == Format::FLAT || instr->format == Format::SCRATCH || instr->format == Format::GLOBAL;
 151                bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
 152                                    instr->format == Format::PSEUDO_REDUCTION ||
 153                                    instr->opcode == aco_opcode::p_create_vector ||
 154                                    (flat && i == 1) || (instr->format == Format::MIMG && i == 1) ||
 155                                    ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1);
 156                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
 157             } else {
 158                check(instr->operands[i].isFixed() || instr->operands[i].isTemp() || instr->operands[i].isConstant(), "Uninitialized Operand", instr.get());
 159             }
 160          }
 161
 162          /* check subdword definitions */
 163          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 164             if (instr->definitions[i].regClass().is_subdword())
 165                check(instr->isSDWA() || instr->format == Format::PSEUDO, "Only SDWA and Pseudo instructions can write subdword registers", instr.get());
 166          }
 167
 168          if (instr->isSALU() || instr->isVALU()) {
 169             /* check literals */
 170             Operand literal(s1);
 171             for (unsigned i = 0; i < instr->operands.size(); i++)
 172             {
 173                Operand op = instr->operands[i];
 174                if (!op.isLiteral())
 175                   continue;
 176
 177                check(instr->format == Format::SOP1 ||
 178                      instr->format == Format::SOP2 ||
 179                      instr->format == Format::SOPC ||
 180                      instr->format == Format::VOP1 ||
 181                      instr->format == Format::VOP2 ||
 182                      instr->format == Format::VOPC ||
 183                      (instr->isVOP3() && program->chip_class >= GFX10),
 184                      "Literal applied on wrong instruction format", instr.get());
 185
 186                check(literal.isUndefined() || (literal.size() == op.size() && literal.constantValue() == op.constantValue()), "Only 1 Literal allowed", instr.get());
 187                literal = op;
 188                check(!instr->isVALU() || instr->isVOP3() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
 189             }
 190
 191             /* check num sgprs for VALU */
 192             if (instr->isVALU()) {
 193                bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
 194                                  instr->opcode == aco_opcode::v_lshrrev_b64 ||
 195                                  instr->opcode == aco_opcode::v_ashrrev_i64;
 196                unsigned const_bus_limit = 1;
 197                if (program->chip_class >= GFX10 && !is_shift64)
 198                   const_bus_limit = 2;
 199
 200                uint32_t scalar_mask = instr->isVOP3() ? 0x7 : 0x5;
 201                if (instr->isSDWA())
 202                   scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
 203
 204                check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
 205                      (int) instr->format & (int) Format::VOPC ||
 206                      instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 207                      instr->opcode == aco_opcode::v_readlane_b32 ||
 208                      instr->opcode == aco_opcode::v_readlane_b32_e64,
 209                      "Wrong Definition type for VALU instruction", instr.get());
 210                unsigned num_sgprs = 0;
 211                unsigned sgpr[] = {0, 0};
 212                for (unsigned i = 0; i < instr->operands.size(); i++)
 213                {
 214                   Operand op = instr->operands[i];
 215                   if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 216                       instr->opcode == aco_opcode::v_readlane_b32 ||
 217                       instr->opcode == aco_opcode::v_readlane_b32_e64 ||
 218                       instr->opcode == aco_opcode::v_writelane_b32 ||
 219                       instr->opcode == aco_opcode::v_writelane_b32_e64) {
 220                      check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get());
 221                      check(i == 1 || (op.isTemp() && op.regClass() == v1), "Wrong Operand type for VALU instruction", instr.get());
 222                      continue;
 223                   }
 224                   if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
 225                      check(scalar_mask & (1 << i), "Wrong source position for SGPR argument", instr.get());
 226
 227                      if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
 228                         if (num_sgprs < 2)
 229                            sgpr[num_sgprs++] = op.tempId();
 230                      }
 231                   }
 232
 233                   if (op.isConstant() && !op.isLiteral())
 234                      check(scalar_mask & (1 << i), "Wrong source position for constant argument", instr.get());
 235                }
 236                check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, "Too many SGPRs/literals", instr.get());
 237             }
 238
 239             if (instr->format == Format::SOP1 || instr->format == Format::SOP2) {
 240                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "Wrong Definition type for SALU instruction", instr.get());
 241                for (const Operand& op : instr->operands) {
 242                  check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
 243                        "Wrong Operand type for SALU instruction", instr.get());
 244             }
 245          }
 246          }
 247
 248          switch (instr->format) {
 249          case Format::PSEUDO: {
 250             if (instr->opcode == aco_opcode::p_create_vector) {
 251                unsigned size = 0;
 252                for (const Operand& op : instr->operands) {
 253                   size += op.bytes();
 254                }
 255                check(size == instr->definitions[0].bytes(), "Definition size does not match operand sizes", instr.get());
 256                if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
 257                   for (const Operand& op : instr->operands) {
 258                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
 259                            "Wrong Operand type for scalar vector", instr.get());
 260                   }
 261                }
 262             } else if (instr->opcode == aco_opcode::p_extract_vector) {
 263                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
 264                check(instr->operands[1].constantValue() < instr->operands[0].size(), "Index out of range", instr.get());
 265                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
 266                      "Cannot extract SGPR value from VGPR vector", instr.get());
 267             } else if (instr->opcode == aco_opcode::p_parallelcopy) {
 268                check(instr->definitions.size() == instr->operands.size(), "Number of Operands does not match number of Definitions", instr.get());
 269                for (unsigned i = 0; i < instr->operands.size(); i++) {
 270                   if (instr->operands[i].isTemp())
 271                      check((instr->definitions[i].getTemp().type() == instr->operands[i].regClass().type()) ||
 272                            (instr->definitions[i].getTemp().type() == RegType::vgpr && instr->operands[i].regClass().type() == RegType::sgpr),
 273                            "Operand and Definition types do not match", instr.get());
 274                }
 275             } else if (instr->opcode == aco_opcode::p_phi) {
 276                check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 277                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->definitions[0].getTemp().regClass() == program->lane_mask, "Logical Phi Definition must be vgpr or divergent boolean", instr.get());
 278             } else if (instr->opcode == aco_opcode::p_linear_phi) {
 279                for (const Operand& op : instr->operands)
 280                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get());
 281                check(instr->operands.size() == block.linear_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 282             }
 283             break;
 284          }
 285          case Format::SMEM: {
 286             if (instr->operands.size() >= 1)
 287                check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "SMEM operands must be sgpr", instr.get());
 288             if (instr->operands.size() >= 2)
 289                check(instr->operands[1].isConstant() || (instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr),
 290                      "SMEM offset must be constant or sgpr", instr.get());
 291             if (!instr->definitions.empty())
 292                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "SMEM result must be sgpr", instr.get());
 293             break;
 294          }
 295          case Format::MTBUF:
 296          case Format::MUBUF: {
 297             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand", instr.get());
 298             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr,
 299                   "VADDR must be in vgpr for VMEM instructions", instr.get());
 300             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
 301             check(instr->operands.size() < 4 || (instr->operands[3].isTemp() && instr->operands[3].regClass().type() == RegType::vgpr), "VMEM write data must be vgpr", instr.get());
 302             break;
 303          }
 304          case Format::MIMG: {
 305             check(instr->operands.size() == 3, "MIMG instructions must have exactly 3 operands", instr.get());
 306             check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
 307                   "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
 308             if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr)
 309                check(instr->operands[1].regClass() == s4, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
 310             else if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr)
 311                check((instr->definitions.empty() || instr->definitions[0].regClass() == instr->operands[1].regClass() ||
 312                      instr->opcode == aco_opcode::image_atomic_cmpswap || instr->opcode == aco_opcode::image_atomic_fcmpswap),
 313                      "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr.get());
 314             check(instr->operands[2].hasRegClass() && instr->operands[2].regClass().type() == RegType::vgpr,
 315                   "MIMG operands[2] (VADDR) must be VGPR", instr.get());
 316             check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
 317                   "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
 318             break;
 319          }
 320          case Format::DS: {
 321             for (const Operand& op : instr->operands) {
 322                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
 323                      "Only VGPRs are valid DS instruction operands", instr.get());
 324             }
 325             if (!instr->definitions.empty())
 326                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "DS instruction must return VGPR", instr.get());
 327             break;
 328          }
 329          case Format::EXP: {
 330             for (unsigned i = 0; i < 4; i++)
 331                check(instr->operands[i].hasRegClass() && instr->operands[i].regClass().type() == RegType::vgpr,
 332                      "Only VGPRs are valid Export arguments", instr.get());
 333             break;
 334          }
 335          case Format::FLAT:
 336             check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR", instr.get());
 337             /* fallthrough */
 338          case Format::GLOBAL:
 339          case Format::SCRATCH: {
 340             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr.get());
 341             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr,
 342                   "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr.get());
 343             if (!instr->definitions.empty())
 344                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr.get());
 345             else
 346                check(instr->operands[2].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr.get());
 347             break;
 348          }
 349          default:
 350             break;
 351          }
 352       }
 353    }
 354
 355    /* validate CFG */
 356    for (unsigned i = 0; i < program->blocks.size(); i++) {
 357       Block& block = program->blocks[i];
 358       check_block(block.index == i, "block.index must match actual index", &block);
 359
 360       /* predecessors/successors should be sorted */
 361       for (unsigned j = 0; j + 1 < block.linear_preds.size(); j++)
 362          check_block(block.linear_preds[j] < block.linear_preds[j + 1], "linear predecessors must be sorted", &block);
 363       for (unsigned j = 0; j + 1 < block.logical_preds.size(); j++)
 364          check_block(block.logical_preds[j] < block.logical_preds[j + 1], "logical predecessors must be sorted", &block);
 365       for (unsigned j = 0; j + 1 < block.linear_succs.size(); j++)
 366          check_block(block.linear_succs[j] < block.linear_succs[j + 1], "linear successors must be sorted", &block);
 367       for (unsigned j = 0; j + 1 < block.logical_succs.size(); j++)
 368          check_block(block.logical_succs[j] < block.logical_succs[j + 1], "logical successors must be sorted", &block);
 369
 370       /* critical edges are not allowed */
 371       if (block.linear_preds.size() > 1) {
 372          for (unsigned pred : block.linear_preds)
 373             check_block(program->blocks[pred].linear_succs.size() == 1, "linear critical edges are not allowed", &program->blocks[pred]);
 374          for (unsigned pred : block.logical_preds)
 375             check_block(program->blocks[pred].logical_succs.size() == 1, "logical critical edges are not allowed", &program->blocks[pred]);
 376       }
 377    }
 378
 379    assert(is_valid);
 380 }
 381
 382 /* RA validation */
 383 namespace {
 384
 385 struct Location {
 386    Location() : block(NULL), instr(NULL) {}
 387
 388    Block *block;
 389    Instruction *instr; //NULL if it's the block's live-in
 390 };
 391
 392 struct Assignment {
 393    Location defloc;
 394    Location firstloc;
 395    PhysReg reg;
 396 };
 397
 398 bool ra_fail(FILE *output, Location loc, Location loc2, const char *fmt, ...) {
 399    va_list args;
 400    va_start(args, fmt);
 401    char msg[1024];
 402    vsprintf(msg, fmt, args);
 403    va_end(args);
 404
 405    fprintf(stderr, "RA error found at instruction in BB%d:\n", loc.block->index);
 406    if (loc.instr) {
 407       aco_print_instr(loc.instr, stderr);
 408       fprintf(stderr, "\n%s", msg);
 409    } else {
 410       fprintf(stderr, "%s", msg);
 411    }
 412    if (loc2.block) {
 413       fprintf(stderr, " in BB%d:\n", loc2.block->index);
 414       aco_print_instr(loc2.instr, stderr);
 415    }
 416    fprintf(stderr, "\n\n");
 417
 418    return true;
 419 }
 420
 421 } /* end namespace */
 422
 423 bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) {
 424    if (!(debug_flags & DEBUG_VALIDATE_RA))
 425       return false;
 426
 427    bool err = false;
 428    aco::live live_vars = aco::live_var_analysis(program, options);
 429    std::vector<std::vector<Temp>> phi_sgpr_ops(program->blocks.size());
 430
 431    std::map<unsigned, Assignment> assignments;
 432    for (Block& block : program->blocks) {
 433       Location loc;
 434       loc.block = &block;
 435       for (aco_ptr<Instruction>& instr : block.instructions) {
 436          if (instr->opcode == aco_opcode::p_phi) {
 437             for (unsigned i = 0; i < instr->operands.size(); i++) {
 438                if (instr->operands[i].isTemp() &&
 439                    instr->operands[i].getTemp().type() == RegType::sgpr &&
 440                    instr->operands[i].isFirstKill())
 441                   phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
 442             }
 443          }
 444
 445          loc.instr = instr.get();
 446          for (unsigned i = 0; i < instr->operands.size(); i++) {
 447             Operand& op = instr->operands[i];
 448             if (!op.isTemp())
 449                continue;
 450             if (!op.isFixed())
 451                err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i);
 452             if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
 453                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
 454             if ((op.getTemp().type() == RegType::vgpr && op.physReg() + op.size() > 256 + program->config->num_vgprs) ||
 455                 (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
 456                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
 457             if (op.physReg() == vcc && !program->needs_vcc)
 458                err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i);
 459             if (!(instr->isSDWA() || instr->format == Format::PSEUDO) && op.regClass().is_subdword() && op.physReg().byte())
 460                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d must be aligned to a full register", i);
 461             if (!assignments[op.tempId()].firstloc.block)
 462                assignments[op.tempId()].firstloc = loc;
 463             if (!assignments[op.tempId()].defloc.block)
 464                assignments[op.tempId()].reg = op.physReg();
 465          }
 466
 467          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 468             Definition& def = instr->definitions[i];
 469             if (!def.isTemp())
 470                continue;
 471             if (!def.isFixed())
 472                err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i);
 473             if (assignments[def.tempId()].defloc.block)
 474                err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
 475             if ((def.getTemp().type() == RegType::vgpr && def.physReg() + def.size() > 256 + program->config->num_vgprs) ||
 476                 (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
 477                err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
 478             if (def.physReg() == vcc && !program->needs_vcc)
 479                err |= ra_fail(output, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i);
 480             if (!assignments[def.tempId()].firstloc.block)
 481                assignments[def.tempId()].firstloc = loc;
 482             assignments[def.tempId()].defloc = loc;
 483             assignments[def.tempId()].reg = def.physReg();
 484          }
 485       }
 486    }
 487
 488    for (Block& block : program->blocks) {
 489       Location loc;
 490       loc.block = &block;
 491
 492       std::array<unsigned, 2048> regs; /* register file in bytes */
 493       regs.fill(0);
 494
 495       std::set<Temp> live;
 496       live.insert(live_vars.live_out[block.index].begin(), live_vars.live_out[block.index].end());
 497       /* remove killed p_phi sgpr operands */
 498       for (Temp tmp : phi_sgpr_ops[block.index])
 499          live.erase(tmp);
 500
 501       /* check live out */
 502       for (Temp tmp : live) {
 503          PhysReg reg = assignments.at(tmp.id()).reg;
 504          for (unsigned i = 0; i < tmp.bytes(); i++) {
 505             if (regs[reg.reg_b + i]) {
 506                err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 507             }
 508             regs[reg.reg_b + i] = tmp.id();
 509          }
 510       }
 511       regs.fill(0);
 512
 513       for (auto it = block.instructions.rbegin(); it != block.instructions.rend(); ++it) {
 514          aco_ptr<Instruction>& instr = *it;
 515
 516          /* check killed p_phi sgpr operands */
 517          if (instr->opcode == aco_opcode::p_logical_end) {
 518             for (Temp tmp : phi_sgpr_ops[block.index]) {
 519                PhysReg reg = assignments.at(tmp.id()).reg;
 520                for (unsigned i = 0; i < tmp.bytes(); i++) {
 521                   if (regs[reg.reg_b + i])
 522                      err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
 523                }
 524                live.emplace(tmp);
 525             }
 526          }
 527
 528          for (const Definition& def : instr->definitions) {
 529             if (!def.isTemp())
 530                continue;
 531             live.erase(def.getTemp());
 532          }
 533
 534          /* don't count phi operands as live-in, since they are actually
 535           * killed when they are copied at the predecessor */
 536          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 537             for (const Operand& op : instr->operands) {
 538                if (!op.isTemp())
 539                   continue;
 540                live.insert(op.getTemp());
 541             }
 542          }
 543       }
 544
 545       for (Temp tmp : live) {
 546          PhysReg reg = assignments.at(tmp.id()).reg;
 547          for (unsigned i = 0; i < tmp.bytes(); i++)
 548             regs[reg.reg_b + i] = tmp.id();
 549       }
 550
 551       for (aco_ptr<Instruction>& instr : block.instructions) {
 552          loc.instr = instr.get();
 553
 554          /* remove killed p_phi operands from regs */
 555          if (instr->opcode == aco_opcode::p_logical_end) {
 556             for (Temp tmp : phi_sgpr_ops[block.index]) {
 557                PhysReg reg = assignments.at(tmp.id()).reg;
 558                for (unsigned i = 0; i < tmp.bytes(); i++)
 559                   regs[reg.reg_b + i] = 0;
 560             }
 561          }
 562
 563          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 564             for (const Operand& op : instr->operands) {
 565                if (!op.isTemp())
 566                   continue;
 567                if (op.isFirstKillBeforeDef()) {
 568                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 569                      regs[op.physReg().reg_b + j] = 0;
 570                }
 571             }
 572          }
 573
 574          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 575             Definition& def = instr->definitions[i];
 576             if (!def.isTemp())
 577                continue;
 578             Temp tmp = def.getTemp();
 579             PhysReg reg = assignments.at(tmp.id()).reg;
 580             for (unsigned j = 0; j < tmp.bytes(); j++) {
 581                if (regs[reg.reg_b + j])
 582                   err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + i]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
 583                regs[reg.reg_b + j] = tmp.id();
 584             }
 585          }
 586
 587          for (const Definition& def : instr->definitions) {
 588             if (!def.isTemp())
 589                continue;
 590             if (def.isKill()) {
 591                for (unsigned j = 0; j < def.getTemp().bytes(); j++)
 592                   regs[def.physReg().reg_b + j] = 0;
 593             }
 594          }
 595
 596          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 597             for (const Operand& op : instr->operands) {
 598                if (!op.isTemp())
 599                   continue;
 600                if (op.isLateKill() && op.isFirstKill()) {
 601                   for (unsigned j = 0; j < op.getTemp().bytes(); j++)
 602                      regs[op.physReg().reg_b + j] = 0;
 603                }
 604             }
 605          }
 606       }
 607    }
 608
 609    return err;
 610 }
 611 }