src/amd/compiler/aco_validate.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "aco_ir.h"
  26
  27 #include <array>
  28 #include <map>
  29
  30 namespace aco {
  31
  32 #ifndef NDEBUG
  33 void perfwarn(bool cond, const char *msg, Instruction *instr)
  34 {
  35    if (cond) {
  36       fprintf(stderr, "ACO performance warning: %s\n", msg);
  37       if (instr) {
  38          fprintf(stderr, "instruction: ");
  39          aco_print_instr(instr, stderr);
  40          fprintf(stderr, "\n");
  41       }
  42
  43       if (debug_flags & DEBUG_PERFWARN)
  44          exit(1);
  45    }
  46 }
  47 #endif
  48
  49 void validate(Program* program, FILE * output)
  50 {
  51    if (!(debug_flags & DEBUG_VALIDATE))
  52       return;
  53
  54    bool is_valid = true;
  55    auto check = [&output, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void {
  56       if (!check) {
  57          fprintf(output, "%s: ", msg);
  58          aco_print_instr(instr, output);
  59          fprintf(output, "\n");
  60          is_valid = false;
  61       }
  62    };
  63    auto check_block = [&output, &is_valid](bool check, const char * msg, aco::Block * block) -> void {
  64       if (!check) {
  65          fprintf(output, "%s: BB%u\n", msg, block->index);
  66          is_valid = false;
  67       }
  68    };
  69
  70    for (Block& block : program->blocks) {
  71       for (aco_ptr<Instruction>& instr : block.instructions) {
  72
  73          /* check base format */
  74          Format base_format = instr->format;
  75          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::SDWA);
  76          base_format = (Format)((uint32_t)base_format & ~(uint32_t)Format::DPP);
  77          if ((uint32_t)base_format & (uint32_t)Format::VOP1)
  78             base_format = Format::VOP1;
  79          else if ((uint32_t)base_format & (uint32_t)Format::VOP2)
  80             base_format = Format::VOP2;
  81          else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
  82             base_format = Format::VOPC;
  83          else if ((uint32_t)base_format & (uint32_t)Format::VINTRP)
  84             base_format = Format::VINTRP;
  85          check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
  86
  87          /* check VOP3 modifiers */
  88          if (((uint32_t)instr->format & (uint32_t)Format::VOP3) && instr->format != Format::VOP3) {
  89             check(base_format == Format::VOP2 ||
  90                   base_format == Format::VOP1 ||
  91                   base_format == Format::VOPC ||
  92                   base_format == Format::VINTRP,
  93                   "Format cannot have VOP3A/VOP3B applied", instr.get());
  94          }
  95
  96          /* check for undefs */
  97          for (unsigned i = 0; i < instr->operands.size(); i++) {
  98             if (instr->operands[i].isUndefined()) {
  99                bool flat = instr->format == Format::FLAT || instr->format == Format::SCRATCH || instr->format == Format::GLOBAL;
 100                bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
 101                                    instr->format == Format::PSEUDO_REDUCTION ||
 102                                    (flat && i == 1) || (instr->format == Format::MIMG && i == 2) ||
 103                                    ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 0);
 104                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
 105             }
 106          }
 107
 108          /* check num literals */
 109          if (instr->isSALU() || instr->isVALU()) {
 110             unsigned num_literals = 0;
 111             for (unsigned i = 0; i < instr->operands.size(); i++)
 112             {
 113                if (instr->operands[i].isLiteral() && instr->isVOP3() && program->chip_class >= GFX10) {
 114                   num_literals++;
 115                } else if (instr->operands[i].isLiteral()) {
 116                   check(instr->format == Format::SOP1 ||
 117                         instr->format == Format::SOP2 ||
 118                         instr->format == Format::SOPC ||
 119                         instr->format == Format::VOP1 ||
 120                         instr->format == Format::VOP2 ||
 121                         instr->format == Format::VOPC,
 122                         "Literal applied on wrong instruction format", instr.get());
 123
 124                   num_literals++;
 125                   check(!instr->isVALU() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
 126                }
 127             }
 128             check(num_literals <= 1, "Only 1 Literal allowed", instr.get());
 129
 130             /* check num sgprs for VALU */
 131             if (instr->isVALU()) {
 132                check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
 133                      (int) instr->format & (int) Format::VOPC ||
 134                      instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 135                      instr->opcode == aco_opcode::v_readlane_b32 ||
 136                      instr->opcode == aco_opcode::v_readlane_b32_e64,
 137                      "Wrong Definition type for VALU instruction", instr.get());
 138                unsigned num_sgpr = 0;
 139                unsigned sgpr_idx = instr->operands.size();
 140                for (unsigned i = 0; i < instr->operands.size(); i++) {
 141                   if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
 142                       instr->opcode == aco_opcode::v_readlane_b32 ||
 143                       instr->opcode == aco_opcode::v_readlane_b32_e64 ||
 144                       instr->opcode == aco_opcode::v_writelane_b32 ||
 145                       instr->opcode == aco_opcode::v_writelane_b32_e64) {
 146                      check(!instr->operands[i].isLiteral(), "No literal allowed on VALU instruction", instr.get());
 147                      check(i == 1 || (instr->operands[i].isTemp() && instr->operands[i].regClass() == v1), "Wrong Operand type for VALU instruction", instr.get());
 148                      continue;
 149                   }
 150                   if (instr->operands[i].isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
 151                      check(i != 1 || (int) instr->format & (int) Format::VOP3A, "Wrong source position for SGPR argument", instr.get());
 152
 153                      if (sgpr_idx == instr->operands.size() || instr->operands[sgpr_idx].tempId() != instr->operands[i].tempId())
 154                         num_sgpr++;
 155                      sgpr_idx = i;
 156                   }
 157
 158                   if (instr->operands[i].isConstant() && !instr->operands[i].isLiteral())
 159                      check(i == 0 || (int) instr->format & (int) Format::VOP3A, "Wrong source position for constant argument", instr.get());
 160                }
 161                check(num_sgpr + num_literals <= 1, "Only 1 Literal OR 1 SGPR allowed", instr.get());
 162             }
 163
 164             if (instr->format == Format::SOP1 || instr->format == Format::SOP2) {
 165                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "Wrong Definition type for SALU instruction", instr.get());
 166                for (const Operand& op : instr->operands) {
 167                  check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
 168                        "Wrong Operand type for SALU instruction", instr.get());
 169             }
 170          }
 171          }
 172
 173          switch (instr->format) {
 174          case Format::PSEUDO: {
 175             if (instr->opcode == aco_opcode::p_create_vector) {
 176                unsigned size = 0;
 177                for (const Operand& op : instr->operands) {
 178                   size += op.size();
 179                }
 180                check(size == instr->definitions[0].size(), "Definition size does not match operand sizes", instr.get());
 181                if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
 182                   for (const Operand& op : instr->operands) {
 183                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
 184                            "Wrong Operand type for scalar vector", instr.get());
 185                   }
 186                }
 187             } else if (instr->opcode == aco_opcode::p_extract_vector) {
 188                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
 189                check(instr->operands[1].constantValue() < instr->operands[0].size(), "Index out of range", instr.get());
 190                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
 191                      "Cannot extract SGPR value from VGPR vector", instr.get());
 192             } else if (instr->opcode == aco_opcode::p_parallelcopy) {
 193                check(instr->definitions.size() == instr->operands.size(), "Number of Operands does not match number of Definitions", instr.get());
 194                for (unsigned i = 0; i < instr->operands.size(); i++) {
 195                   if (instr->operands[i].isTemp())
 196                      check((instr->definitions[i].getTemp().type() == instr->operands[i].regClass().type()) ||
 197                            (instr->definitions[i].getTemp().type() == RegType::vgpr && instr->operands[i].regClass().type() == RegType::sgpr),
 198                            "Operand and Definition types do not match", instr.get());
 199                }
 200             } else if (instr->opcode == aco_opcode::p_phi) {
 201                check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 202                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->definitions[0].getTemp().regClass() == program->lane_mask, "Logical Phi Definition must be vgpr or divergent boolean", instr.get());
 203             } else if (instr->opcode == aco_opcode::p_linear_phi) {
 204                for (const Operand& op : instr->operands)
 205                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get());
 206                check(instr->operands.size() == block.linear_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
 207             }
 208             break;
 209          }
 210          case Format::SMEM: {
 211             if (instr->operands.size() >= 1)
 212                check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "SMEM operands must be sgpr", instr.get());
 213             if (instr->operands.size() >= 2)
 214                check(instr->operands[1].isConstant() || (instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr),
 215                      "SMEM offset must be constant or sgpr", instr.get());
 216             if (!instr->definitions.empty())
 217                check(instr->definitions[0].getTemp().type() == RegType::sgpr, "SMEM result must be sgpr", instr.get());
 218             break;
 219          }
 220          case Format::MTBUF:
 221          case Format::MUBUF:
 222          case Format::MIMG: {
 223             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand", instr.get());
 224             check(instr->operands[0].hasRegClass() && instr->operands[0].regClass().type() == RegType::vgpr,
 225                   "VADDR must be in vgpr for VMEM instructions", instr.get());
 226             check(instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
 227             check(instr->operands.size() < 4 || (instr->operands[3].isTemp() && instr->operands[3].regClass().type() == RegType::vgpr), "VMEM write data must be vgpr", instr.get());
 228             break;
 229          }
 230          case Format::DS: {
 231             for (const Operand& op : instr->operands) {
 232                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
 233                      "Only VGPRs are valid DS instruction operands", instr.get());
 234             }
 235             if (!instr->definitions.empty())
 236                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "DS instruction must return VGPR", instr.get());
 237             break;
 238          }
 239          case Format::EXP: {
 240             for (unsigned i = 0; i < 4; i++)
 241                check(instr->operands[i].hasRegClass() && instr->operands[i].regClass().type() == RegType::vgpr,
 242                      "Only VGPRs are valid Export arguments", instr.get());
 243             break;
 244          }
 245          case Format::FLAT:
 246             check(instr->operands[1].isUndefined(), "Flat instructions don't support SADDR", instr.get());
 247             /* fallthrough */
 248          case Format::GLOBAL:
 249          case Format::SCRATCH: {
 250             check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH address must be vgpr", instr.get());
 251             check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr,
 252                   "FLAT/GLOBAL/SCRATCH sgpr address must be undefined or sgpr", instr.get());
 253             if (!instr->definitions.empty())
 254                check(instr->definitions[0].getTemp().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH result must be vgpr", instr.get());
 255             else
 256                check(instr->operands[2].regClass().type() == RegType::vgpr, "FLAT/GLOBAL/SCRATCH data must be vgpr", instr.get());
 257             break;
 258          }
 259          default:
 260             break;
 261          }
 262       }
 263    }
 264
 265    /* validate CFG */
 266    for (unsigned i = 0; i < program->blocks.size(); i++) {
 267       Block& block = program->blocks[i];
 268       check_block(block.index == i, "block.index must match actual index", &block);
 269
 270       /* predecessors/successors should be sorted */
 271       for (unsigned j = 0; j + 1 < block.linear_preds.size(); j++)
 272          check_block(block.linear_preds[j] < block.linear_preds[j + 1], "linear predecessors must be sorted", &block);
 273       for (unsigned j = 0; j + 1 < block.logical_preds.size(); j++)
 274          check_block(block.logical_preds[j] < block.logical_preds[j + 1], "logical predecessors must be sorted", &block);
 275       for (unsigned j = 0; j + 1 < block.linear_succs.size(); j++)
 276          check_block(block.linear_succs[j] < block.linear_succs[j + 1], "linear successors must be sorted", &block);
 277       for (unsigned j = 0; j + 1 < block.logical_succs.size(); j++)
 278          check_block(block.logical_succs[j] < block.logical_succs[j + 1], "logical successors must be sorted", &block);
 279
 280       /* critical edges are not allowed */
 281       if (block.linear_preds.size() > 1) {
 282          for (unsigned pred : block.linear_preds)
 283             check_block(program->blocks[pred].linear_succs.size() == 1, "linear critical edges are not allowed", &program->blocks[pred]);
 284          for (unsigned pred : block.logical_preds)
 285             check_block(program->blocks[pred].logical_succs.size() == 1, "logical critical edges are not allowed", &program->blocks[pred]);
 286       }
 287    }
 288
 289    assert(is_valid);
 290 }
 291
 292 /* RA validation */
 293 namespace {
 294
 295 struct Location {
 296    Location() : block(NULL), instr(NULL) {}
 297
 298    Block *block;
 299    Instruction *instr; //NULL if it's the block's live-in
 300 };
 301
 302 struct Assignment {
 303    Location defloc;
 304    Location firstloc;
 305    PhysReg reg;
 306 };
 307
 308 bool ra_fail(FILE *output, Location loc, Location loc2, const char *fmt, ...) {
 309    va_list args;
 310    va_start(args, fmt);
 311    char msg[1024];
 312    vsprintf(msg, fmt, args);
 313    va_end(args);
 314
 315    fprintf(stderr, "RA error found at instruction in BB%d:\n", loc.block->index);
 316    if (loc.instr) {
 317       aco_print_instr(loc.instr, stderr);
 318       fprintf(stderr, "\n%s", msg);
 319    } else {
 320       fprintf(stderr, "%s", msg);
 321    }
 322    if (loc2.block) {
 323       fprintf(stderr, " in BB%d:\n", loc2.block->index);
 324       aco_print_instr(loc2.instr, stderr);
 325    }
 326    fprintf(stderr, "\n\n");
 327
 328    return true;
 329 }
 330
 331 } /* end namespace */
 332
 333 bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) {
 334    if (!(debug_flags & DEBUG_VALIDATE_RA))
 335       return false;
 336
 337    bool err = false;
 338    aco::live live_vars = aco::live_var_analysis(program, options);
 339    std::vector<std::vector<Temp>> phi_sgpr_ops(program->blocks.size());
 340
 341    std::map<unsigned, Assignment> assignments;
 342    for (Block& block : program->blocks) {
 343       Location loc;
 344       loc.block = &block;
 345       for (aco_ptr<Instruction>& instr : block.instructions) {
 346          if (instr->opcode == aco_opcode::p_phi) {
 347             for (unsigned i = 0; i < instr->operands.size(); i++) {
 348                if (instr->operands[i].isTemp() &&
 349                    instr->operands[i].getTemp().type() == RegType::sgpr &&
 350                    instr->operands[i].isFirstKill())
 351                   phi_sgpr_ops[block.logical_preds[i]].emplace_back(instr->operands[i].getTemp());
 352             }
 353          }
 354
 355          loc.instr = instr.get();
 356          for (unsigned i = 0; i < instr->operands.size(); i++) {
 357             Operand& op = instr->operands[i];
 358             if (!op.isTemp())
 359                continue;
 360             if (!op.isFixed())
 361                err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i);
 362             if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
 363                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
 364             if ((op.getTemp().type() == RegType::vgpr && op.physReg() + op.size() > 256 + program->config->num_vgprs) ||
 365                 (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
 366                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
 367             if (!assignments[op.tempId()].firstloc.block)
 368                assignments[op.tempId()].firstloc = loc;
 369             if (!assignments[op.tempId()].defloc.block)
 370                assignments[op.tempId()].reg = op.physReg();
 371          }
 372
 373          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 374             Definition& def = instr->definitions[i];
 375             if (!def.isTemp())
 376                continue;
 377             if (!def.isFixed())
 378                err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i);
 379             if (assignments[def.tempId()].defloc.block)
 380                err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
 381             if ((def.getTemp().type() == RegType::vgpr && def.physReg() + def.size() > 256 + program->config->num_vgprs) ||
 382                 (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
 383                err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
 384             if (!assignments[def.tempId()].firstloc.block)
 385                assignments[def.tempId()].firstloc = loc;
 386             assignments[def.tempId()].defloc = loc;
 387             assignments[def.tempId()].reg = def.physReg();
 388          }
 389       }
 390    }
 391
 392    for (Block& block : program->blocks) {
 393       Location loc;
 394       loc.block = &block;
 395
 396       std::array<unsigned, 512> regs;
 397       regs.fill(0);
 398
 399       std::set<Temp> live;
 400       live.insert(live_vars.live_out[block.index].begin(), live_vars.live_out[block.index].end());
 401       /* remove killed p_phi sgpr operands */
 402       for (Temp tmp : phi_sgpr_ops[block.index])
 403          live.erase(tmp);
 404
 405       /* check live out */
 406       for (Temp tmp : live) {
 407          PhysReg reg = assignments.at(tmp.id()).reg;
 408          for (unsigned i = 0; i < tmp.size(); i++) {
 409             if (regs[reg + i]) {
 410                err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg + i]);
 411             }
 412             regs[reg + i] = tmp.id();
 413          }
 414       }
 415       regs.fill(0);
 416
 417       for (auto it = block.instructions.rbegin(); it != block.instructions.rend(); ++it) {
 418          aco_ptr<Instruction>& instr = *it;
 419
 420          /* check killed p_phi sgpr operands */
 421          if (instr->opcode == aco_opcode::p_logical_end) {
 422             for (Temp tmp : phi_sgpr_ops[block.index]) {
 423                PhysReg reg = assignments.at(tmp.id()).reg;
 424                for (unsigned i = 0; i < tmp.size(); i++) {
 425                   if (regs[reg + i])
 426                      err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg + i]);
 427                }
 428                live.emplace(tmp);
 429             }
 430          }
 431
 432          for (const Definition& def : instr->definitions) {
 433             if (!def.isTemp())
 434                continue;
 435             live.erase(def.getTemp());
 436          }
 437
 438          /* don't count phi operands as live-in, since they are actually
 439           * killed when they are copied at the predecessor */
 440          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 441             for (const Operand& op : instr->operands) {
 442                if (!op.isTemp())
 443                   continue;
 444                live.insert(op.getTemp());
 445             }
 446          }
 447       }
 448
 449       for (Temp tmp : live) {
 450          PhysReg reg = assignments.at(tmp.id()).reg;
 451          for (unsigned i = 0; i < tmp.size(); i++)
 452             regs[reg + i] = tmp.id();
 453       }
 454
 455       for (aco_ptr<Instruction>& instr : block.instructions) {
 456          loc.instr = instr.get();
 457
 458          /* remove killed p_phi operands from regs */
 459          if (instr->opcode == aco_opcode::p_logical_end) {
 460             for (Temp tmp : phi_sgpr_ops[block.index]) {
 461                PhysReg reg = assignments.at(tmp.id()).reg;
 462                regs[reg] = 0;
 463             }
 464          }
 465
 466          if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
 467             for (const Operand& op : instr->operands) {
 468                if (!op.isTemp())
 469                   continue;
 470                if (op.isFirstKill()) {
 471                   for (unsigned j = 0; j < op.getTemp().size(); j++)
 472                      regs[op.physReg() + j] = 0;
 473                }
 474             }
 475          }
 476
 477          for (unsigned i = 0; i < instr->definitions.size(); i++) {
 478             Definition& def = instr->definitions[i];
 479             if (!def.isTemp())
 480                continue;
 481             Temp tmp = def.getTemp();
 482             PhysReg reg = assignments.at(tmp.id()).reg;
 483             for (unsigned j = 0; j < tmp.size(); j++) {
 484                if (regs[reg + j])
 485                   err |= ra_fail(output, loc, assignments.at(regs[reg + i]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg + j]);
 486                regs[reg + j] = tmp.id();
 487             }
 488          }
 489
 490          for (const Definition& def : instr->definitions) {
 491             if (!def.isTemp())
 492                continue;
 493             if (def.isKill()) {
 494                for (unsigned j = 0; j < def.getTemp().size(); j++)
 495                   regs[def.physReg() + j] = 0;
 496             }
 497          }
 498       }
 499    }
 500
 501    return err;
 502 }
 503 }