src/amd/llvm/ac_llvm_util.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial portions
  22  * of the Software.
  23  *
  24  */
  25 /* based on pieces from si_pipe.c and radeon_llvm_emit.c */
  26 #include "ac_llvm_util.h"
  27 #include "ac_llvm_build.h"
  28 #include "util/bitscan.h"
  29 #include <llvm-c/Core.h>
  30 #include <llvm-c/Support.h>
  31 #include <llvm-c/Transforms/IPO.h>
  32 #include <llvm-c/Transforms/Scalar.h>
  33 #include <llvm-c/Transforms/Utils.h>
  34 #include "c11/threads.h"
  35 #include "gallivm/lp_bld_misc.h"
  36 #include "util/u_math.h"
  37
  38 #include <assert.h>
  39 #include <stdio.h>
  40 #include <string.h>
  41
  42 static void ac_init_llvm_target()
  43 {
  44         LLVMInitializeAMDGPUTargetInfo();
  45         LLVMInitializeAMDGPUTarget();
  46         LLVMInitializeAMDGPUTargetMC();
  47         LLVMInitializeAMDGPUAsmPrinter();
  48
  49         /* For inline assembly. */
  50         LLVMInitializeAMDGPUAsmParser();
  51
  52         /* For ACO disassembly. */
  53         LLVMInitializeAMDGPUDisassembler();
  54
  55         /* Workaround for bug in llvm 4.0 that causes image intrinsics
  56          * to disappear.
  57          * https://reviews.llvm.org/D26348
  58          *
  59          * "mesa" is the prefix for error messages.
  60          *
  61          * -global-isel-abort=2 is a no-op unless global isel has been enabled.
  62          * This option tells the backend to fall-back to SelectionDAG and print
  63          * a diagnostic message if global isel fails.
  64          */
  65         const char *argv[] = {
  66                 "mesa",
  67                 "-simplifycfg-sink-common=false",
  68                 "-global-isel-abort=2",
  69 #if LLVM_VERSION_MAJOR >= 10
  70                 /* Atomic optimizations require LLVM 10.0 for gfx10 support. */
  71                 "-amdgpu-atomic-optimizations=true",
  72 #endif
  73         };
  74         LLVMParseCommandLineOptions(ARRAY_SIZE(argv), argv, NULL);
  75 }
  76
  77 static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
  78
  79 void ac_init_llvm_once(void)
  80 {
  81         call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
  82 }
  83
  84 static LLVMTargetRef ac_get_llvm_target(const char *triple)
  85 {
  86         LLVMTargetRef target = NULL;
  87         char *err_message = NULL;
  88
  89         if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
  90                 fprintf(stderr, "Cannot find target for triple %s ", triple);
  91                 if (err_message) {
  92                         fprintf(stderr, "%s\n", err_message);
  93                 }
  94                 LLVMDisposeMessage(err_message);
  95                 return NULL;
  96         }
  97         return target;
  98 }
  99
 100 const char *ac_get_llvm_processor_name(enum radeon_family family)
 101 {
 102         switch (family) {
 103         case CHIP_TAHITI:
 104                 return "tahiti";
 105         case CHIP_PITCAIRN:
 106                 return "pitcairn";
 107         case CHIP_VERDE:
 108                 return "verde";
 109         case CHIP_OLAND:
 110                 return "oland";
 111         case CHIP_HAINAN:
 112                 return "hainan";
 113         case CHIP_BONAIRE:
 114                 return "bonaire";
 115         case CHIP_KABINI:
 116                 return "kabini";
 117         case CHIP_KAVERI:
 118                 return "kaveri";
 119         case CHIP_HAWAII:
 120                 return "hawaii";
 121         case CHIP_TONGA:
 122                 return "tonga";
 123         case CHIP_ICELAND:
 124                 return "iceland";
 125         case CHIP_CARRIZO:
 126                 return "carrizo";
 127         case CHIP_FIJI:
 128                 return "fiji";
 129         case CHIP_STONEY:
 130                 return "stoney";
 131         case CHIP_POLARIS10:
 132                 return "polaris10";
 133         case CHIP_POLARIS11:
 134         case CHIP_POLARIS12:
 135         case CHIP_VEGAM:
 136                 return "polaris11";
 137         case CHIP_VEGA10:
 138                 return "gfx900";
 139         case CHIP_RAVEN:
 140                 return "gfx902";
 141         case CHIP_VEGA12:
 142                 return "gfx904";
 143         case CHIP_VEGA20:
 144                 return "gfx906";
 145         case CHIP_RAVEN2:
 146         case CHIP_RENOIR:
 147                 return "gfx909";
 148         case CHIP_ARCTURUS:
 149                 return "gfx908";
 150         case CHIP_NAVI10:
 151                 return "gfx1010";
 152         case CHIP_NAVI12:
 153                 return "gfx1011";
 154         case CHIP_NAVI14:
 155                 return "gfx1012";
 156         default:
 157                 return "";
 158         }
 159 }
 160
 161 static LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
 162                                                      enum ac_target_machine_options tm_options,
 163                                                      LLVMCodeGenOptLevel level,
 164                                                      const char **out_triple)
 165 {
 166         assert(family >= CHIP_TAHITI);
 167         char features[256];
 168         const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
 169         LLVMTargetRef target = ac_get_llvm_target(triple);
 170
 171         snprintf(features, sizeof(features),
 172                  "+DumpCode,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
 173                  family >= CHIP_NAVI10 && !(tm_options & AC_TM_WAVE32) ?
 174                          ",+wavefrontsize64,-wavefrontsize32" : "",
 175                  tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
 176                  tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
 177                  tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
 178                  tm_options & AC_TM_NO_LOAD_STORE_OPT ? ",-load-store-opt" : "");
 179
 180         LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
 181                                      target,
 182                                      triple,
 183                                      ac_get_llvm_processor_name(family),
 184                                      features,
 185                                      level,
 186                                      LLVMRelocDefault,
 187                                      LLVMCodeModelDefault);
 188
 189         if (out_triple)
 190                 *out_triple = triple;
 191         if (tm_options & AC_TM_ENABLE_GLOBAL_ISEL)
 192                 ac_enable_global_isel(tm);
 193         return tm;
 194 }
 195
 196 static LLVMPassManagerRef ac_create_passmgr(LLVMTargetLibraryInfoRef target_library_info,
 197                                             bool check_ir)
 198 {
 199         LLVMPassManagerRef passmgr = LLVMCreatePassManager();
 200         if (!passmgr)
 201                 return NULL;
 202
 203         if (target_library_info)
 204                 LLVMAddTargetLibraryInfo(target_library_info,
 205                                          passmgr);
 206
 207         if (check_ir)
 208                 LLVMAddVerifierPass(passmgr);
 209         LLVMAddAlwaysInlinerPass(passmgr);
 210         /* Normally, the pass manager runs all passes on one function before
 211          * moving onto another. Adding a barrier no-op pass forces the pass
 212          * manager to run the inliner on all functions first, which makes sure
 213          * that the following passes are only run on the remaining non-inline
 214          * function, so it removes useless work done on dead inline functions.
 215          */
 216         ac_llvm_add_barrier_noop_pass(passmgr);
 217         /* This pass should eliminate all the load and store instructions. */
 218         LLVMAddPromoteMemoryToRegisterPass(passmgr);
 219         LLVMAddScalarReplAggregatesPass(passmgr);
 220         LLVMAddLICMPass(passmgr);
 221         LLVMAddAggressiveDCEPass(passmgr);
 222         LLVMAddCFGSimplificationPass(passmgr);
 223         /* This is recommended by the instruction combining pass. */
 224         LLVMAddEarlyCSEMemSSAPass(passmgr);
 225         LLVMAddInstructionCombiningPass(passmgr);
 226         return passmgr;
 227 }
 228
 229 static const char *attr_to_str(enum ac_func_attr attr)
 230 {
 231    switch (attr) {
 232    case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
 233    case AC_FUNC_ATTR_INREG: return "inreg";
 234    case AC_FUNC_ATTR_NOALIAS: return "noalias";
 235    case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
 236    case AC_FUNC_ATTR_READNONE: return "readnone";
 237    case AC_FUNC_ATTR_READONLY: return "readonly";
 238    case AC_FUNC_ATTR_WRITEONLY: return "writeonly";
 239    case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";
 240    case AC_FUNC_ATTR_CONVERGENT: return "convergent";
 241    default:
 242            fprintf(stderr, "Unhandled function attribute: %x\n", attr);
 243            return 0;
 244    }
 245 }
 246
 247 void
 248 ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
 249                      int attr_idx, enum ac_func_attr attr)
 250 {
 251    const char *attr_name = attr_to_str(attr);
 252    unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
 253                                                       strlen(attr_name));
 254    LLVMAttributeRef llvm_attr = LLVMCreateEnumAttribute(ctx, kind_id, 0);
 255
 256    if (LLVMIsAFunction(function))
 257       LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
 258    else
 259       LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
 260 }
 261
 262 void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
 263                             unsigned attrib_mask)
 264 {
 265         attrib_mask |= AC_FUNC_ATTR_NOUNWIND;
 266         attrib_mask &= ~AC_FUNC_ATTR_LEGACY;
 267
 268         while (attrib_mask) {
 269                 enum ac_func_attr attr = 1u << u_bit_scan(&attrib_mask);
 270                 ac_add_function_attr(ctx, function, -1, attr);
 271         }
 272 }
 273
 274 void
 275 ac_dump_module(LLVMModuleRef module)
 276 {
 277         char *str = LLVMPrintModuleToString(module);
 278         fprintf(stderr, "%s", str);
 279         LLVMDisposeMessage(str);
 280 }
 281
 282 void
 283 ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
 284                                      const char *name, unsigned value)
 285 {
 286         char str[16];
 287
 288         snprintf(str, sizeof(str), "0x%x", value);
 289         LLVMAddTargetDependentFunctionAttr(F, name, str);
 290 }
 291
 292 void ac_llvm_set_workgroup_size(LLVMValueRef F, unsigned size)
 293 {
 294         if (!size)
 295                 return;
 296
 297         char str[32];
 298         snprintf(str, sizeof(str), "%u,%u", size, size);
 299         LLVMAddTargetDependentFunctionAttr(F, "amdgpu-flat-work-group-size", str);
 300 }
 301
 302 unsigned
 303 ac_count_scratch_private_memory(LLVMValueRef function)
 304 {
 305         unsigned private_mem_vgprs = 0;
 306
 307         /* Process all LLVM instructions. */
 308         LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(function);
 309         while (bb) {
 310                 LLVMValueRef next = LLVMGetFirstInstruction(bb);
 311
 312                 while (next) {
 313                         LLVMValueRef inst = next;
 314                         next = LLVMGetNextInstruction(next);
 315
 316                         if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
 317                                 continue;
 318
 319                         LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
 320                         /* No idea why LLVM aligns allocas to 4 elements. */
 321                         unsigned alignment = LLVMGetAlignment(inst);
 322                         unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
 323                         private_mem_vgprs += dw_size;
 324                 }
 325                 bb = LLVMGetNextBasicBlock(bb);
 326         }
 327
 328         return private_mem_vgprs;
 329 }
 330
 331 bool
 332 ac_init_llvm_compiler(struct ac_llvm_compiler *compiler,
 333                       enum radeon_family family,
 334                       enum ac_target_machine_options tm_options)
 335 {
 336         const char *triple;
 337         memset(compiler, 0, sizeof(*compiler));
 338
 339         compiler->tm = ac_create_target_machine(family, tm_options,
 340                                                 LLVMCodeGenLevelDefault,
 341                                                 &triple);
 342         if (!compiler->tm)
 343                 return false;
 344
 345         if (tm_options & AC_TM_CREATE_LOW_OPT) {
 346                 compiler->low_opt_tm =
 347                         ac_create_target_machine(family, tm_options,
 348                                                  LLVMCodeGenLevelLess, NULL);
 349                 if (!compiler->low_opt_tm)
 350                         goto fail;
 351         }
 352
 353         if (family >= CHIP_NAVI10) {
 354                 assert(!(tm_options & AC_TM_CREATE_LOW_OPT));
 355                 compiler->tm_wave32 = ac_create_target_machine(family,
 356                                                                tm_options | AC_TM_WAVE32,
 357                                                                LLVMCodeGenLevelDefault,
 358                                                                NULL);
 359                 if (!compiler->tm_wave32)
 360                         goto fail;
 361         }
 362
 363         compiler->target_library_info =
 364                 ac_create_target_library_info(triple);
 365         if (!compiler->target_library_info)
 366                 goto fail;
 367
 368         compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
 369                                               tm_options & AC_TM_CHECK_IR);
 370         if (!compiler->passmgr)
 371                 goto fail;
 372
 373         return true;
 374 fail:
 375         ac_destroy_llvm_compiler(compiler);
 376         return false;
 377 }
 378
 379 void
 380 ac_destroy_llvm_compiler(struct ac_llvm_compiler *compiler)
 381 {
 382         ac_destroy_llvm_passes(compiler->passes);
 383         ac_destroy_llvm_passes(compiler->passes_wave32);
 384         ac_destroy_llvm_passes(compiler->low_opt_passes);
 385
 386         if (compiler->passmgr)
 387                 LLVMDisposePassManager(compiler->passmgr);
 388         if (compiler->target_library_info)
 389                 ac_dispose_target_library_info(compiler->target_library_info);
 390         if (compiler->low_opt_tm)
 391                 LLVMDisposeTargetMachine(compiler->low_opt_tm);
 392         if (compiler->tm)
 393                 LLVMDisposeTargetMachine(compiler->tm);
 394         if (compiler->tm_wave32)
 395                 LLVMDisposeTargetMachine(compiler->tm_wave32);
 396 }