5 {"name": "ARRAY_LINEAR_GENERAL", "value": 0},
6 {"name": "ARRAY_LINEAR_ALIGNED", "value": 1},
7 {"name": "ARRAY_1D_TILED_THIN1", "value": 2},
8 {"name": "ARRAY_1D_TILED_THICK", "value": 3},
9 {"name": "ARRAY_2D_TILED_THIN1", "value": 4},
10 {"name": "ARRAY_PRT_TILED_THIN1", "value": 5},
11 {"name": "ARRAY_PRT_2D_TILED_THIN1", "value": 6},
12 {"name": "ARRAY_2D_TILED_THICK", "value": 7},
13 {"name": "ARRAY_2D_TILED_XTHICK", "value": 8},
14 {"name": "ARRAY_PRT_TILED_THICK", "value": 9},
15 {"name": "ARRAY_PRT_2D_TILED_THICK", "value": 10},
16 {"name": "ARRAY_PRT_3D_TILED_THIN1", "value": 11},
17 {"name": "ARRAY_3D_TILED_THIN1", "value": 12},
18 {"name": "ARRAY_3D_TILED_THICK", "value": 13},
19 {"name": "ARRAY_3D_TILED_XTHICK", "value": 14},
20 {"name": "ARRAY_PRT_3D_TILED_THICK", "value": 15}
25 {"name": "BUF_DATA_FORMAT_INVALID", "value": 0},
26 {"name": "BUF_DATA_FORMAT_8", "value": 1},
27 {"name": "BUF_DATA_FORMAT_16", "value": 2},
28 {"name": "BUF_DATA_FORMAT_8_8", "value": 3},
29 {"name": "BUF_DATA_FORMAT_32", "value": 4},
30 {"name": "BUF_DATA_FORMAT_16_16", "value": 5},
31 {"name": "BUF_DATA_FORMAT_10_11_11", "value": 6},
32 {"name": "BUF_DATA_FORMAT_11_11_10", "value": 7},
33 {"name": "BUF_DATA_FORMAT_10_10_10_2", "value": 8},
34 {"name": "BUF_DATA_FORMAT_2_10_10_10", "value": 9},
35 {"name": "BUF_DATA_FORMAT_8_8_8_8", "value": 10},
36 {"name": "BUF_DATA_FORMAT_32_32", "value": 11},
37 {"name": "BUF_DATA_FORMAT_16_16_16_16", "value": 12},
38 {"name": "BUF_DATA_FORMAT_32_32_32", "value": 13},
39 {"name": "BUF_DATA_FORMAT_32_32_32_32", "value": 14},
40 {"name": "BUF_DATA_FORMAT_RESERVED_15", "value": 15}
45 {"name": "BUF_NUM_FORMAT_UNORM", "value": 0},
46 {"name": "BUF_NUM_FORMAT_SNORM", "value": 1},
47 {"name": "BUF_NUM_FORMAT_USCALED", "value": 2},
48 {"name": "BUF_NUM_FORMAT_SSCALED", "value": 3},
49 {"name": "BUF_NUM_FORMAT_UINT", "value": 4},
50 {"name": "BUF_NUM_FORMAT_SINT", "value": 5},
51 {"name": "BUF_NUM_FORMAT_SNORM_OGL", "value": 6},
52 {"name": "BUF_NUM_FORMAT_FLOAT", "value": 7}
57 {"name": "ADDR_SURF_BANK_HEIGHT_1", "value": 0},
58 {"name": "ADDR_SURF_BANK_HEIGHT_2", "value": 1},
59 {"name": "ADDR_SURF_BANK_HEIGHT_4", "value": 2},
60 {"name": "ADDR_SURF_BANK_HEIGHT_8", "value": 3}
65 {"name": "ADDR_SURF_BANK_WIDTH_1", "value": 0},
66 {"name": "ADDR_SURF_BANK_WIDTH_2", "value": 1},
67 {"name": "ADDR_SURF_BANK_WIDTH_4", "value": 2},
68 {"name": "ADDR_SURF_BANK_WIDTH_8", "value": 3}
73 {"name": "BLEND_ZERO", "value": 0},
74 {"name": "BLEND_ONE", "value": 1},
75 {"name": "BLEND_SRC_COLOR", "value": 2},
76 {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
77 {"name": "BLEND_SRC_ALPHA", "value": 4},
78 {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
79 {"name": "BLEND_DST_ALPHA", "value": 6},
80 {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
81 {"name": "BLEND_DST_COLOR", "value": 8},
82 {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
83 {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
84 {"name": "BLEND_BOTH_SRC_ALPHA", "value": 11},
85 {"name": "BLEND_BOTH_INV_SRC_ALPHA", "value": 12},
86 {"name": "BLEND_CONSTANT_COLOR", "value": 13},
87 {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 14},
88 {"name": "BLEND_SRC1_COLOR", "value": 15},
89 {"name": "BLEND_INV_SRC1_COLOR", "value": 16},
90 {"name": "BLEND_SRC1_ALPHA", "value": 17},
91 {"name": "BLEND_INV_SRC1_ALPHA", "value": 18},
92 {"name": "BLEND_CONSTANT_ALPHA", "value": 19},
93 {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 20}
98 {"name": "FORCE_OPT_AUTO", "value": 0},
99 {"name": "FORCE_OPT_DISABLE", "value": 1},
100 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
101 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
102 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
103 {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
104 {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
105 {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
110 {"name": "CB_DISABLE", "value": 0},
111 {"name": "CB_NORMAL", "value": 1},
112 {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
113 {"name": "CB_RESOLVE", "value": 3},
114 {"name": "CB_DECOMPRESS", "value": 4},
115 {"name": "CB_FMASK_DECOMPRESS", "value": 5}
120 {"name": "OUT", "value": 1},
121 {"name": "IN_0", "value": 2},
122 {"name": "IN_1", "value": 4},
123 {"name": "IN_10", "value": 8},
124 {"name": "IN_2", "value": 16},
125 {"name": "IN_20", "value": 32},
126 {"name": "IN_21", "value": 64},
127 {"name": "IN_210", "value": 128},
128 {"name": "IN_3", "value": 256},
129 {"name": "IN_30", "value": 512},
130 {"name": "IN_31", "value": 1024},
131 {"name": "IN_310", "value": 2048},
132 {"name": "IN_32", "value": 4096},
133 {"name": "IN_320", "value": 8192},
134 {"name": "IN_321", "value": 16384},
135 {"name": "IN_3210", "value": 32768}
138 "CP_PERFMON_ENABLE_MODE": {
140 {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
141 {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
142 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
143 {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
146 "CP_PERFMON_STATE": {
148 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
149 {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
150 {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
151 {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
152 {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
153 {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
158 {"name": "COLOR_INVALID", "value": 0},
159 {"name": "COLOR_8", "value": 1},
160 {"name": "COLOR_16", "value": 2},
161 {"name": "COLOR_8_8", "value": 3},
162 {"name": "COLOR_32", "value": 4},
163 {"name": "COLOR_16_16", "value": 5},
164 {"name": "COLOR_10_11_11", "value": 6},
165 {"name": "COLOR_11_11_10", "value": 7},
166 {"name": "COLOR_10_10_10_2", "value": 8},
167 {"name": "COLOR_2_10_10_10", "value": 9},
168 {"name": "COLOR_8_8_8_8", "value": 10},
169 {"name": "COLOR_32_32", "value": 11},
170 {"name": "COLOR_16_16_16_16", "value": 12},
171 {"name": "COLOR_RESERVED_13", "value": 13},
172 {"name": "COLOR_32_32_32_32", "value": 14},
173 {"name": "COLOR_RESERVED_15", "value": 15},
174 {"name": "COLOR_5_6_5", "value": 16},
175 {"name": "COLOR_1_5_5_5", "value": 17},
176 {"name": "COLOR_5_5_5_1", "value": 18},
177 {"name": "COLOR_4_4_4_4", "value": 19},
178 {"name": "COLOR_8_24", "value": 20},
179 {"name": "COLOR_24_8", "value": 21},
180 {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
181 {"name": "COLOR_RESERVED_23", "value": 23}
186 {"name": "COMB_DST_PLUS_SRC", "value": 0},
187 {"name": "COMB_SRC_MINUS_DST", "value": 1},
188 {"name": "COMB_MIN_DST_SRC", "value": 2},
189 {"name": "COMB_MAX_DST_SRC", "value": 3},
190 {"name": "COMB_DST_MINUS_SRC", "value": 4}
195 {"name": "FRAG_NEVER", "value": 0},
196 {"name": "FRAG_LESS", "value": 1},
197 {"name": "FRAG_EQUAL", "value": 2},
198 {"name": "FRAG_LEQUAL", "value": 3},
199 {"name": "FRAG_GREATER", "value": 4},
200 {"name": "FRAG_NOTEQUAL", "value": 5},
201 {"name": "FRAG_GEQUAL", "value": 6},
202 {"name": "FRAG_ALWAYS", "value": 7}
205 "ConservativeZExport": {
207 {"name": "EXPORT_ANY_Z", "value": 0},
208 {"name": "EXPORT_LESS_THAN_Z", "value": 1},
209 {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
210 {"name": "EXPORT_RESERVED", "value": 3}
215 {"name": "PSLC_AUTO", "value": 0},
216 {"name": "PSLC_ON_HANG_ONLY", "value": 1},
217 {"name": "PSLC_ASAP", "value": 2},
218 {"name": "PSLC_COUNTDOWN", "value": 3}
223 {"name": "INVALID", "value": 1},
224 {"name": "INPUT_DENORMAL", "value": 2},
225 {"name": "DIVIDE_BY_ZERO", "value": 4},
226 {"name": "OVERFLOW", "value": 8},
227 {"name": "UNDERFLOW", "value": 16},
228 {"name": "INEXACT", "value": 32},
229 {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
230 {"name": "ADDRESS_WATCH", "value": 128},
231 {"name": "MEMORY_VIOLATION", "value": 256}
236 {"name": "FP_32_DENORMS", "value": 48},
237 {"name": "FP_64_DENORMS", "value": 192},
238 {"name": "FP_ALL_DENORMS", "value": 240}
243 {"name": "FORCE_OFF", "value": 0},
244 {"name": "FORCE_ENABLE", "value": 1},
245 {"name": "FORCE_DISABLE", "value": 2},
246 {"name": "FORCE_RESERVED", "value": 3}
249 "GB_TILE_MODE0__MICRO_TILE_MODE": {
251 {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
252 {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
253 {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
254 {"name": "ADDR_SURF_THICK_MICRO_TILING_GFX6", "value": 3}
259 {"name": "IMG_DATA_FORMAT_INVALID", "value": 0},
260 {"name": "IMG_DATA_FORMAT_8", "value": 1},
261 {"name": "IMG_DATA_FORMAT_16", "value": 2},
262 {"name": "IMG_DATA_FORMAT_8_8", "value": 3},
263 {"name": "IMG_DATA_FORMAT_32", "value": 4},
264 {"name": "IMG_DATA_FORMAT_16_16", "value": 5},
265 {"name": "IMG_DATA_FORMAT_10_11_11", "value": 6},
266 {"name": "IMG_DATA_FORMAT_11_11_10", "value": 7},
267 {"name": "IMG_DATA_FORMAT_10_10_10_2", "value": 8},
268 {"name": "IMG_DATA_FORMAT_2_10_10_10", "value": 9},
269 {"name": "IMG_DATA_FORMAT_8_8_8_8", "value": 10},
270 {"name": "IMG_DATA_FORMAT_32_32", "value": 11},
271 {"name": "IMG_DATA_FORMAT_16_16_16_16", "value": 12},
272 {"name": "IMG_DATA_FORMAT_32_32_32", "value": 13},
273 {"name": "IMG_DATA_FORMAT_32_32_32_32", "value": 14},
274 {"name": "IMG_DATA_FORMAT_RESERVED_15", "value": 15},
275 {"name": "IMG_DATA_FORMAT_5_6_5", "value": 16},
276 {"name": "IMG_DATA_FORMAT_1_5_5_5", "value": 17},
277 {"name": "IMG_DATA_FORMAT_5_5_5_1", "value": 18},
278 {"name": "IMG_DATA_FORMAT_4_4_4_4", "value": 19},
279 {"name": "IMG_DATA_FORMAT_8_24", "value": 20},
280 {"name": "IMG_DATA_FORMAT_24_8", "value": 21},
281 {"name": "IMG_DATA_FORMAT_X24_8_32", "value": 22},
282 {"name": "IMG_DATA_FORMAT_RESERVED_23", "value": 23},
283 {"name": "IMG_DATA_FORMAT_RESERVED_24", "value": 24},
284 {"name": "IMG_DATA_FORMAT_RESERVED_25", "value": 25},
285 {"name": "IMG_DATA_FORMAT_RESERVED_26", "value": 26},
286 {"name": "IMG_DATA_FORMAT_RESERVED_27", "value": 27},
287 {"name": "IMG_DATA_FORMAT_RESERVED_28", "value": 28},
288 {"name": "IMG_DATA_FORMAT_RESERVED_29", "value": 29},
289 {"name": "IMG_DATA_FORMAT_RESERVED_30", "value": 30},
290 {"name": "IMG_DATA_FORMAT_RESERVED_31", "value": 31},
291 {"name": "IMG_DATA_FORMAT_GB_GR", "value": 32},
292 {"name": "IMG_DATA_FORMAT_BG_RG", "value": 33},
293 {"name": "IMG_DATA_FORMAT_5_9_9_9", "value": 34},
294 {"name": "IMG_DATA_FORMAT_BC1", "value": 35},
295 {"name": "IMG_DATA_FORMAT_BC2", "value": 36},
296 {"name": "IMG_DATA_FORMAT_BC3", "value": 37},
297 {"name": "IMG_DATA_FORMAT_BC4", "value": 38},
298 {"name": "IMG_DATA_FORMAT_BC5", "value": 39},
299 {"name": "IMG_DATA_FORMAT_BC6", "value": 40},
300 {"name": "IMG_DATA_FORMAT_BC7", "value": 41},
301 {"name": "IMG_DATA_FORMAT_RESERVED_42", "value": 42},
302 {"name": "IMG_DATA_FORMAT_RESERVED_43", "value": 43},
303 {"name": "IMG_DATA_FORMAT_FMASK8_S2_F1", "value": 44},
304 {"name": "IMG_DATA_FORMAT_FMASK8_S4_F1", "value": 45},
305 {"name": "IMG_DATA_FORMAT_FMASK8_S8_F1", "value": 46},
306 {"name": "IMG_DATA_FORMAT_FMASK8_S2_F2", "value": 47},
307 {"name": "IMG_DATA_FORMAT_FMASK8_S4_F2", "value": 48},
308 {"name": "IMG_DATA_FORMAT_FMASK8_S4_F4", "value": 49},
309 {"name": "IMG_DATA_FORMAT_FMASK16_S16_F1", "value": 50},
310 {"name": "IMG_DATA_FORMAT_FMASK16_S8_F2", "value": 51},
311 {"name": "IMG_DATA_FORMAT_FMASK32_S16_F2", "value": 52},
312 {"name": "IMG_DATA_FORMAT_FMASK32_S8_F4", "value": 53},
313 {"name": "IMG_DATA_FORMAT_FMASK32_S8_F8", "value": 54},
314 {"name": "IMG_DATA_FORMAT_FMASK64_S16_F4", "value": 55},
315 {"name": "IMG_DATA_FORMAT_FMASK64_S16_F8", "value": 56},
316 {"name": "IMG_DATA_FORMAT_4_4", "value": 57},
317 {"name": "IMG_DATA_FORMAT_6_5_5", "value": 58},
318 {"name": "IMG_DATA_FORMAT_1", "value": 59},
319 {"name": "IMG_DATA_FORMAT_1_REVERSED", "value": 60},
320 {"name": "IMG_DATA_FORMAT_32_AS_8", "value": 61},
321 {"name": "IMG_DATA_FORMAT_32_AS_8_8", "value": 62},
322 {"name": "IMG_DATA_FORMAT_32_AS_32_32_32_32", "value": 63}
327 {"name": "IMG_NUM_FORMAT_UNORM", "value": 0},
328 {"name": "IMG_NUM_FORMAT_SNORM", "value": 1},
329 {"name": "IMG_NUM_FORMAT_USCALED", "value": 2},
330 {"name": "IMG_NUM_FORMAT_SSCALED", "value": 3},
331 {"name": "IMG_NUM_FORMAT_UINT", "value": 4},
332 {"name": "IMG_NUM_FORMAT_SINT", "value": 5},
333 {"name": "IMG_NUM_FORMAT_SNORM_OGL", "value": 6},
334 {"name": "IMG_NUM_FORMAT_FLOAT", "value": 7},
335 {"name": "IMG_NUM_FORMAT_RESERVED_8", "value": 8},
336 {"name": "IMG_NUM_FORMAT_SRGB", "value": 9},
337 {"name": "IMG_NUM_FORMAT_UBNORM", "value": 10},
338 {"name": "IMG_NUM_FORMAT_UBNORM_OGL", "value": 11},
339 {"name": "IMG_NUM_FORMAT_UBINT", "value": 12},
340 {"name": "IMG_NUM_FORMAT_UBSCALED", "value": 13},
341 {"name": "IMG_NUM_FORMAT_RESERVED_14", "value": 14},
342 {"name": "IMG_NUM_FORMAT_RESERVED_15", "value": 15}
347 {"name": "ADDR_SURF_MACRO_ASPECT_1", "value": 0},
348 {"name": "ADDR_SURF_MACRO_ASPECT_2", "value": 1},
349 {"name": "ADDR_SURF_MACRO_ASPECT_4", "value": 2},
350 {"name": "ADDR_SURF_MACRO_ASPECT_8", "value": 3}
355 {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0},
356 {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1},
357 {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2},
358 {"name": "ADDR_SURF_ROTATED_MICRO_TILING", "value": 3},
359 {"name": "ADDR_SURF_THICK_MICRO_TILING", "value": 4}
364 {"name": "ADDR_SURF_2_BANK", "value": 0},
365 {"name": "ADDR_SURF_4_BANK", "value": 1},
366 {"name": "ADDR_SURF_8_BANK", "value": 2},
367 {"name": "ADDR_SURF_16_BANK", "value": 3}
370 "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
372 {"name": "X_DRAW_POINTS", "value": 0},
373 {"name": "X_DRAW_LINES", "value": 1},
374 {"name": "X_DRAW_TRIANGLES", "value": 2}
377 "PA_SU_SC_MODE_CNTL__POLY_MODE": {
379 {"name": "X_DISABLE_POLY_MODE", "value": 0},
380 {"name": "X_DUAL_MODE", "value": 1}
383 "PA_SU_VTX_CNTL__ROUND_MODE": {
385 {"name": "X_TRUNCATE", "value": 0},
386 {"name": "X_ROUND", "value": 1},
387 {"name": "X_ROUND_TO_EVEN", "value": 2},
388 {"name": "X_ROUND_TO_ODD", "value": 3}
393 {"name": "ADDR_SURF_P2", "value": 0},
394 {"name": "ADDR_SURF_P2_RESERVED0", "value": 1},
395 {"name": "ADDR_SURF_P2_RESERVED1", "value": 2},
396 {"name": "ADDR_SURF_P2_RESERVED2", "value": 3},
397 {"name": "ADDR_SURF_P4_8x16", "value": 4},
398 {"name": "ADDR_SURF_P4_16x16", "value": 5},
399 {"name": "ADDR_SURF_P4_16x32", "value": 6},
400 {"name": "ADDR_SURF_P4_32x32", "value": 7},
401 {"name": "ADDR_SURF_P8_16x16_8x16", "value": 8},
402 {"name": "ADDR_SURF_P8_16x32_8x16", "value": 9},
403 {"name": "ADDR_SURF_P8_32x32_8x16", "value": 10},
404 {"name": "ADDR_SURF_P8_16x32_16x16", "value": 11},
405 {"name": "ADDR_SURF_P8_32x32_16x16", "value": 12},
406 {"name": "ADDR_SURF_P8_32x32_16x32", "value": 13},
407 {"name": "ADDR_SURF_P8_32x64_32x32", "value": 14},
408 {"name": "ADDR_SURF_P8_RESERVED0", "value": 15},
409 {"name": "ADDR_SURF_P16_32x32_8x16", "value": 16},
410 {"name": "ADDR_SURF_P16_32x32_16x16", "value": 17}
415 {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
416 {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
417 {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
418 {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
423 {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
424 {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
425 {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
426 {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
431 {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
432 {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
433 {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
434 {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
439 {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
440 {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
441 {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
442 {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
447 {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
448 {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
449 {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
450 {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
451 {"name": "X_16_8_FIXED_POINT_1", "value": 4},
452 {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
453 {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
454 {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
459 {"name": "ROP3_CLEAR", "value": 0},
460 {"name": "X_0X05", "value": 5},
461 {"name": "X_0X0A", "value": 10},
462 {"name": "X_0X0F", "value": 15},
463 {"name": "ROP3_NOR", "value": 17},
464 {"name": "ROP3_AND_INVERTED", "value": 34},
465 {"name": "ROP3_COPY_INVERTED", "value": 51},
466 {"name": "ROP3_AND_REVERSE", "value": 68},
467 {"name": "X_0X50", "value": 80},
468 {"name": "ROP3_INVERT", "value": 85},
469 {"name": "X_0X5A", "value": 90},
470 {"name": "X_0X5F", "value": 95},
471 {"name": "ROP3_XOR", "value": 102},
472 {"name": "ROP3_NAND", "value": 119},
473 {"name": "ROP3_AND", "value": 136},
474 {"name": "ROP3_EQUIVALENT", "value": 153},
475 {"name": "X_0XA0", "value": 160},
476 {"name": "X_0XA5", "value": 165},
477 {"name": "ROP3_NO_OP", "value": 170},
478 {"name": "X_0XAF", "value": 175},
479 {"name": "ROP3_OR_INVERTED", "value": 187},
480 {"name": "ROP3_COPY", "value": 204},
481 {"name": "ROP3_OR_REVERSE", "value": 221},
482 {"name": "ROP3_OR", "value": 238},
483 {"name": "X_0XF0", "value": 240},
484 {"name": "X_0XF5", "value": 245},
485 {"name": "X_0XFA", "value": 250},
486 {"name": "ROP3_SET", "value": 255}
491 {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
492 {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
493 {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
494 {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
499 {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
500 {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
505 {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
506 {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
507 {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
508 {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
513 {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
514 {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
517 "SPI_PNT_SPRITE_OVERRIDE": {
519 {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
520 {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
521 {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
522 {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
523 {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
526 "SPI_SHADER_EX_FORMAT": {
528 {"name": "SPI_SHADER_ZERO", "value": 0},
529 {"name": "SPI_SHADER_32_R", "value": 1},
530 {"name": "SPI_SHADER_32_GR", "value": 2},
531 {"name": "SPI_SHADER_32_AR", "value": 3},
532 {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
533 {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
534 {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
535 {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
536 {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
537 {"name": "SPI_SHADER_32_ABGR", "value": 9}
540 "SPI_SHADER_FORMAT": {
542 {"name": "SPI_SHADER_NONE", "value": 0},
543 {"name": "SPI_SHADER_1COMP", "value": 1},
544 {"name": "SPI_SHADER_2COMP", "value": 2},
545 {"name": "SPI_SHADER_4COMPRESS", "value": 3},
546 {"name": "SPI_SHADER_4COMP", "value": 4}
549 "SPM_PERFMON_STATE": {
551 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
552 {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
553 {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
554 {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
555 {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
556 {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
559 "SQ_IMG_FILTER_TYPE": {
561 {"name": "SQ_IMG_FILTER_MODE_BLEND", "value": 0},
562 {"name": "SQ_IMG_FILTER_MODE_MIN", "value": 1},
563 {"name": "SQ_IMG_FILTER_MODE_MAX", "value": 2}
566 "SQ_RSRC_BUF_TYPE": {
568 {"name": "SQ_RSRC_BUF", "value": 0},
569 {"name": "SQ_RSRC_BUF_RSVD_1", "value": 1},
570 {"name": "SQ_RSRC_BUF_RSVD_2", "value": 2},
571 {"name": "SQ_RSRC_BUF_RSVD_3", "value": 3}
574 "SQ_RSRC_IMG_TYPE": {
576 {"name": "SQ_RSRC_IMG_RSVD_0", "value": 0},
577 {"name": "SQ_RSRC_IMG_RSVD_1", "value": 1},
578 {"name": "SQ_RSRC_IMG_RSVD_2", "value": 2},
579 {"name": "SQ_RSRC_IMG_RSVD_3", "value": 3},
580 {"name": "SQ_RSRC_IMG_RSVD_4", "value": 4},
581 {"name": "SQ_RSRC_IMG_RSVD_5", "value": 5},
582 {"name": "SQ_RSRC_IMG_RSVD_6", "value": 6},
583 {"name": "SQ_RSRC_IMG_RSVD_7", "value": 7},
584 {"name": "SQ_RSRC_IMG_1D", "value": 8},
585 {"name": "SQ_RSRC_IMG_2D", "value": 9},
586 {"name": "SQ_RSRC_IMG_3D", "value": 10},
587 {"name": "SQ_RSRC_IMG_CUBE", "value": 11},
588 {"name": "SQ_RSRC_IMG_1D_ARRAY", "value": 12},
589 {"name": "SQ_RSRC_IMG_2D_ARRAY", "value": 13},
590 {"name": "SQ_RSRC_IMG_2D_MSAA", "value": 14},
591 {"name": "SQ_RSRC_IMG_2D_MSAA_ARRAY", "value": 15}
596 {"name": "SQ_SEL_0", "value": 0},
597 {"name": "SQ_SEL_1", "value": 1},
598 {"name": "SQ_SEL_RESERVED_0", "value": 2},
599 {"name": "SQ_SEL_RESERVED_1", "value": 3},
600 {"name": "SQ_SEL_X", "value": 4},
601 {"name": "SQ_SEL_Y", "value": 5},
602 {"name": "SQ_SEL_Z", "value": 6},
603 {"name": "SQ_SEL_W", "value": 7}
606 "SQ_TEX_BORDER_COLOR": {
608 {"name": "SQ_TEX_BORDER_COLOR_TRANS_BLACK", "value": 0},
609 {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_BLACK", "value": 1},
610 {"name": "SQ_TEX_BORDER_COLOR_OPAQUE_WHITE", "value": 2},
611 {"name": "SQ_TEX_BORDER_COLOR_REGISTER", "value": 3}
616 {"name": "SQ_TEX_WRAP", "value": 0},
617 {"name": "SQ_TEX_MIRROR", "value": 1},
618 {"name": "SQ_TEX_CLAMP_LAST_TEXEL", "value": 2},
619 {"name": "SQ_TEX_MIRROR_ONCE_LAST_TEXEL", "value": 3},
620 {"name": "SQ_TEX_CLAMP_HALF_BORDER", "value": 4},
621 {"name": "SQ_TEX_MIRROR_ONCE_HALF_BORDER", "value": 5},
622 {"name": "SQ_TEX_CLAMP_BORDER", "value": 6},
623 {"name": "SQ_TEX_MIRROR_ONCE_BORDER", "value": 7}
626 "SQ_TEX_DEPTH_COMPARE": {
628 {"name": "SQ_TEX_DEPTH_COMPARE_NEVER", "value": 0},
629 {"name": "SQ_TEX_DEPTH_COMPARE_LESS", "value": 1},
630 {"name": "SQ_TEX_DEPTH_COMPARE_EQUAL", "value": 2},
631 {"name": "SQ_TEX_DEPTH_COMPARE_LESSEQUAL", "value": 3},
632 {"name": "SQ_TEX_DEPTH_COMPARE_GREATER", "value": 4},
633 {"name": "SQ_TEX_DEPTH_COMPARE_NOTEQUAL", "value": 5},
634 {"name": "SQ_TEX_DEPTH_COMPARE_GREATEREQUAL", "value": 6},
635 {"name": "SQ_TEX_DEPTH_COMPARE_ALWAYS", "value": 7}
638 "SQ_TEX_MIP_FILTER": {
640 {"name": "SQ_TEX_MIP_FILTER_NONE", "value": 0},
641 {"name": "SQ_TEX_MIP_FILTER_POINT", "value": 1},
642 {"name": "SQ_TEX_MIP_FILTER_LINEAR", "value": 2}
645 "SQ_TEX_XY_FILTER": {
647 {"name": "SQ_TEX_XY_FILTER_POINT", "value": 0},
648 {"name": "SQ_TEX_XY_FILTER_BILINEAR", "value": 1},
649 {"name": "SQ_TEX_XY_FILTER_ANISO_POINT", "value": 2},
650 {"name": "SQ_TEX_XY_FILTER_ANISO_BILINEAR", "value": 3}
655 {"name": "SQ_TEX_Z_FILTER_NONE", "value": 0},
656 {"name": "SQ_TEX_Z_FILTER_POINT", "value": 1},
657 {"name": "SQ_TEX_Z_FILTER_LINEAR", "value": 2}
662 {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
663 {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
664 {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
665 {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
670 {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
671 {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
672 {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
673 {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
678 {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
679 {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
680 {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
681 {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
686 {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
687 {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
688 {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
689 {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
694 {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
695 {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
696 {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
697 {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
702 {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
703 {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
704 {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
705 {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
710 {"name": "STENCIL_INVALID", "value": 0},
711 {"name": "STENCIL_8", "value": 1}
716 {"name": "STENCIL_KEEP", "value": 0},
717 {"name": "STENCIL_ZERO", "value": 1},
718 {"name": "STENCIL_ONES", "value": 2},
719 {"name": "STENCIL_REPLACE_TEST", "value": 3},
720 {"name": "STENCIL_REPLACE_OP", "value": 4},
721 {"name": "STENCIL_ADD_CLAMP", "value": 5},
722 {"name": "STENCIL_SUB_CLAMP", "value": 6},
723 {"name": "STENCIL_INVERT", "value": 7},
724 {"name": "STENCIL_ADD_WRAP", "value": 8},
725 {"name": "STENCIL_SUB_WRAP", "value": 9},
726 {"name": "STENCIL_AND", "value": 10},
727 {"name": "STENCIL_OR", "value": 11},
728 {"name": "STENCIL_XOR", "value": 12},
729 {"name": "STENCIL_NAND", "value": 13},
730 {"name": "STENCIL_NOR", "value": 14},
731 {"name": "STENCIL_XNOR", "value": 15}
736 {"name": "ENDIAN_NONE", "value": 0},
737 {"name": "ENDIAN_8IN16", "value": 1},
738 {"name": "ENDIAN_8IN32", "value": 2},
739 {"name": "ENDIAN_8IN64", "value": 3}
744 {"name": "NUMBER_UNORM", "value": 0},
745 {"name": "NUMBER_SNORM", "value": 1},
746 {"name": "NUMBER_USCALED", "value": 2},
747 {"name": "NUMBER_SSCALED", "value": 3},
748 {"name": "NUMBER_UINT", "value": 4},
749 {"name": "NUMBER_SINT", "value": 5},
750 {"name": "NUMBER_SRGB", "value": 6},
751 {"name": "NUMBER_FLOAT", "value": 7}
756 {"name": "SWAP_STD", "value": 0},
757 {"name": "SWAP_ALT", "value": 1},
758 {"name": "SWAP_STD_REV", "value": 2},
759 {"name": "SWAP_ALT_REV", "value": 3}
764 {"name": "ADDR_SURF_TILE_SPLIT_64B", "value": 0},
765 {"name": "ADDR_SURF_TILE_SPLIT_128B", "value": 1},
766 {"name": "ADDR_SURF_TILE_SPLIT_256B", "value": 2},
767 {"name": "ADDR_SURF_TILE_SPLIT_512B", "value": 3},
768 {"name": "ADDR_SURF_TILE_SPLIT_1KB", "value": 4},
769 {"name": "ADDR_SURF_TILE_SPLIT_2KB", "value": 5},
770 {"name": "ADDR_SURF_TILE_SPLIT_4KB", "value": 6}
773 "VGT_DI_MAJOR_MODE_SELECT": {
775 {"name": "DI_MAJOR_MODE_0", "value": 0},
776 {"name": "DI_MAJOR_MODE_1", "value": 1}
779 "VGT_DI_PRIM_TYPE": {
781 {"name": "DI_PT_NONE", "value": 0},
782 {"name": "DI_PT_POINTLIST", "value": 1},
783 {"name": "DI_PT_LINELIST", "value": 2},
784 {"name": "DI_PT_LINESTRIP", "value": 3},
785 {"name": "DI_PT_TRILIST", "value": 4},
786 {"name": "DI_PT_TRIFAN", "value": 5},
787 {"name": "DI_PT_TRISTRIP", "value": 6},
788 {"name": "DI_PT_UNUSED_0", "value": 7},
789 {"name": "DI_PT_UNUSED_1", "value": 8},
790 {"name": "DI_PT_PATCH", "value": 9},
791 {"name": "DI_PT_LINELIST_ADJ", "value": 10},
792 {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
793 {"name": "DI_PT_TRILIST_ADJ", "value": 12},
794 {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
795 {"name": "DI_PT_UNUSED_3", "value": 14},
796 {"name": "DI_PT_UNUSED_4", "value": 15},
797 {"name": "DI_PT_TRI_WITH_WFLAGS", "value": 16},
798 {"name": "DI_PT_RECTLIST", "value": 17},
799 {"name": "DI_PT_LINELOOP", "value": 18},
800 {"name": "DI_PT_QUADLIST", "value": 19},
801 {"name": "DI_PT_QUADSTRIP", "value": 20},
802 {"name": "DI_PT_POLYGON", "value": 21},
803 {"name": "DI_PT_2D_COPY_RECT_LIST_V0", "value": 22},
804 {"name": "DI_PT_2D_COPY_RECT_LIST_V1", "value": 23},
805 {"name": "DI_PT_2D_COPY_RECT_LIST_V2", "value": 24},
806 {"name": "DI_PT_2D_COPY_RECT_LIST_V3", "value": 25},
807 {"name": "DI_PT_2D_FILL_RECT_LIST", "value": 26},
808 {"name": "DI_PT_2D_LINE_STRIP", "value": 27},
809 {"name": "DI_PT_2D_TRI_STRIP", "value": 28}
812 "VGT_DI_SOURCE_SELECT": {
814 {"name": "DI_SRC_SEL_DMA", "value": 0},
815 {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
816 {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
817 {"name": "DI_SRC_SEL_RESERVED", "value": 3}
820 "VGT_DMA_BUF_TYPE": {
822 {"name": "VGT_DMA_BUF_MEM", "value": 0},
823 {"name": "VGT_DMA_BUF_RING", "value": 1},
824 {"name": "VGT_DMA_BUF_SETUP", "value": 2}
827 "VGT_DMA_SWAP_MODE": {
829 {"name": "VGT_DMA_SWAP_NONE", "value": 0},
830 {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
831 {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
832 {"name": "VGT_DMA_SWAP_WORD", "value": 3}
837 {"name": "Reserved_0x00", "value": 0},
838 {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
839 {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
840 {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
841 {"name": "CACHE_FLUSH_TS", "value": 4},
842 {"name": "CONTEXT_DONE", "value": 5},
843 {"name": "CACHE_FLUSH", "value": 6},
844 {"name": "CS_PARTIAL_FLUSH", "value": 7},
845 {"name": "VGT_STREAMOUT_SYNC", "value": 8},
846 {"name": "Reserved_0x09", "value": 9},
847 {"name": "VGT_STREAMOUT_RESET", "value": 10},
848 {"name": "END_OF_PIPE_INCR_DE", "value": 11},
849 {"name": "END_OF_PIPE_IB_END", "value": 12},
850 {"name": "RST_PIX_CNT", "value": 13},
851 {"name": "Reserved_0x0E", "value": 14},
852 {"name": "VS_PARTIAL_FLUSH", "value": 15},
853 {"name": "PS_PARTIAL_FLUSH", "value": 16},
854 {"name": "FLUSH_HS_OUTPUT", "value": 17},
855 {"name": "FLUSH_LS_OUTPUT", "value": 18},
856 {"name": "Reserved_0x13", "value": 19},
857 {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
858 {"name": "ZPASS_DONE", "value": 21},
859 {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
860 {"name": "PERFCOUNTER_START", "value": 23},
861 {"name": "PERFCOUNTER_STOP", "value": 24},
862 {"name": "PIPELINESTAT_START", "value": 25},
863 {"name": "PIPELINESTAT_STOP", "value": 26},
864 {"name": "PERFCOUNTER_SAMPLE", "value": 27},
865 {"name": "FLUSH_ES_OUTPUT", "value": 28},
866 {"name": "FLUSH_GS_OUTPUT", "value": 29},
867 {"name": "SAMPLE_PIPELINESTAT", "value": 30},
868 {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
869 {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
870 {"name": "RESET_VTX_CNT", "value": 33},
871 {"name": "BLOCK_CONTEXT_DONE", "value": 34},
872 {"name": "CS_CONTEXT_DONE", "value": 35},
873 {"name": "VGT_FLUSH", "value": 36},
874 {"name": "Reserved_0x25", "value": 37},
875 {"name": "SQ_NON_EVENT", "value": 38},
876 {"name": "SC_SEND_DB_VPZ", "value": 39},
877 {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
878 {"name": "FLUSH_SX_TS", "value": 41},
879 {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
880 {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
881 {"name": "FLUSH_AND_INV_DB_META", "value": 44},
882 {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
883 {"name": "FLUSH_AND_INV_CB_META", "value": 46},
884 {"name": "CS_DONE", "value": 47},
885 {"name": "PS_DONE", "value": 48},
886 {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
887 {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
888 {"name": "THREAD_TRACE_START", "value": 51},
889 {"name": "THREAD_TRACE_STOP", "value": 52},
890 {"name": "THREAD_TRACE_MARKER", "value": 53},
891 {"name": "THREAD_TRACE_FLUSH", "value": 54},
892 {"name": "THREAD_TRACE_FINISH", "value": 55},
893 {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
894 {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
895 {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
896 {"name": "CONTEXT_SUSPEND", "value": 59}
901 {"name": "GS_CUT_1024", "value": 0},
902 {"name": "GS_CUT_512", "value": 1},
903 {"name": "GS_CUT_256", "value": 2},
904 {"name": "GS_CUT_128", "value": 3}
907 "VGT_GS_MODE_TYPE": {
909 {"name": "GS_OFF", "value": 0},
910 {"name": "GS_SCENARIO_A", "value": 1},
911 {"name": "GS_SCENARIO_B", "value": 2},
912 {"name": "GS_SCENARIO_G", "value": 3},
913 {"name": "GS_SCENARIO_C", "value": 4},
914 {"name": "SPRITE_EN", "value": 5}
917 "VGT_GS_OUTPRIM_TYPE": {
919 {"name": "POINTLIST", "value": 0},
920 {"name": "LINESTRIP", "value": 1},
921 {"name": "TRISTRIP", "value": 2}
924 "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
926 {"name": "X_8K_DWORDS", "value": 0},
927 {"name": "X_4K_DWORDS", "value": 1},
928 {"name": "X_2K_DWORDS", "value": 2},
929 {"name": "X_1K_DWORDS", "value": 3}
932 "VGT_INDEX_TYPE_MODE": {
934 {"name": "VGT_INDEX_16", "value": 0},
935 {"name": "VGT_INDEX_32", "value": 1}
938 "VGT_RDREQ_POLICY": {
940 {"name": "VGT_POLICY_LRU", "value": 0},
941 {"name": "VGT_POLICY_STREAM", "value": 1},
942 {"name": "VGT_POLICY_BYPASS", "value": 2},
943 {"name": "VGT_POLICY_RESERVED", "value": 3}
946 "VGT_STAGES_ES_EN": {
948 {"name": "ES_STAGE_OFF", "value": 0},
949 {"name": "ES_STAGE_DS", "value": 1},
950 {"name": "ES_STAGE_REAL", "value": 2},
951 {"name": "RESERVED_ES", "value": 3}
954 "VGT_STAGES_GS_EN": {
956 {"name": "GS_STAGE_OFF", "value": 0},
957 {"name": "GS_STAGE_ON", "value": 1}
960 "VGT_STAGES_HS_EN": {
962 {"name": "HS_STAGE_OFF", "value": 0},
963 {"name": "HS_STAGE_ON", "value": 1}
966 "VGT_STAGES_LS_EN": {
968 {"name": "LS_STAGE_OFF", "value": 0},
969 {"name": "LS_STAGE_ON", "value": 1},
970 {"name": "CS_STAGE_ON", "value": 2},
971 {"name": "RESERVED_LS", "value": 3}
974 "VGT_STAGES_VS_EN": {
976 {"name": "VS_STAGE_REAL", "value": 0},
977 {"name": "VS_STAGE_DS", "value": 1},
978 {"name": "VS_STAGE_COPY_SHADER", "value": 2},
979 {"name": "RESERVED_VS", "value": 3}
982 "VGT_TESS_PARTITION": {
984 {"name": "PART_INTEGER", "value": 0},
985 {"name": "PART_POW2", "value": 1},
986 {"name": "PART_FRAC_ODD", "value": 2},
987 {"name": "PART_FRAC_EVEN", "value": 3}
990 "VGT_TESS_TOPOLOGY": {
992 {"name": "OUTPUT_POINT", "value": 0},
993 {"name": "OUTPUT_LINE", "value": 1},
994 {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
995 {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
1000 {"name": "TESS_ISOLINE", "value": 0},
1001 {"name": "TESS_TRIANGLE", "value": 1},
1002 {"name": "TESS_QUAD", "value": 2}
1007 {"name": "Z_INVALID", "value": 0},
1008 {"name": "Z_16", "value": 1},
1009 {"name": "Z_24", "value": 2},
1010 {"name": "Z_32_FLOAT", "value": 3}
1015 {"name": "FORCE_SUMM_OFF", "value": 0},
1016 {"name": "FORCE_SUMM_MINZ", "value": 1},
1017 {"name": "FORCE_SUMM_MAXZ", "value": 2},
1018 {"name": "FORCE_SUMM_BOTH", "value": 3}
1023 {"name": "LATE_Z", "value": 0},
1024 {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
1025 {"name": "RE_Z", "value": 2},
1026 {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
1030 "register_mappings": [
1033 "map": {"at": 68, "to": "mm"},
1034 "name": "SQ_WAVE_MODE",
1035 "type_ref": "SQ_WAVE_MODE"
1039 "map": {"at": 72, "to": "mm"},
1040 "name": "SQ_WAVE_STATUS",
1041 "type_ref": "SQ_WAVE_STATUS"
1045 "map": {"at": 76, "to": "mm"},
1046 "name": "SQ_WAVE_TRAPSTS",
1047 "type_ref": "SQ_WAVE_TRAPSTS"
1051 "map": {"at": 80, "to": "mm"},
1052 "name": "SQ_WAVE_HW_ID",
1053 "type_ref": "SQ_WAVE_HW_ID"
1057 "map": {"at": 84, "to": "mm"},
1058 "name": "SQ_WAVE_GPR_ALLOC",
1059 "type_ref": "SQ_WAVE_GPR_ALLOC"
1063 "map": {"at": 88, "to": "mm"},
1064 "name": "SQ_WAVE_LDS_ALLOC",
1065 "type_ref": "SQ_WAVE_LDS_ALLOC"
1069 "map": {"at": 92, "to": "mm"},
1070 "name": "SQ_WAVE_IB_STS",
1071 "type_ref": "SQ_WAVE_IB_STS"
1075 "map": {"at": 96, "to": "mm"},
1076 "name": "SQ_WAVE_PC_LO",
1077 "type_ref": "SQ_WAVE_PC_LO"
1081 "map": {"at": 100, "to": "mm"},
1082 "name": "SQ_WAVE_PC_HI",
1083 "type_ref": "SQ_WAVE_PC_HI"
1087 "map": {"at": 104, "to": "mm"},
1088 "name": "SQ_WAVE_INST_DW0",
1089 "type_ref": "SQ_WAVE_INST_DW0"
1093 "map": {"at": 108, "to": "mm"},
1094 "name": "SQ_WAVE_INST_DW1",
1095 "type_ref": "SQ_WAVE_INST_DW1"
1099 "map": {"at": 112, "to": "mm"},
1100 "name": "SQ_WAVE_IB_DBG0",
1101 "type_ref": "SQ_WAVE_IB_DBG0"
1105 "map": {"at": 2480, "to": "mm"},
1106 "name": "SQ_WAVE_TBA_LO",
1107 "type_ref": "SQ_WAVE_TBA_LO"
1111 "map": {"at": 2484, "to": "mm"},
1112 "name": "SQ_WAVE_TBA_HI",
1113 "type_ref": "SQ_WAVE_TBA_HI"
1117 "map": {"at": 2488, "to": "mm"},
1118 "name": "SQ_WAVE_TMA_LO",
1119 "type_ref": "SQ_WAVE_TBA_LO"
1123 "map": {"at": 2492, "to": "mm"},
1124 "name": "SQ_WAVE_TMA_HI",
1125 "type_ref": "SQ_WAVE_TBA_HI"
1129 "map": {"at": 2496, "to": "mm"},
1130 "name": "SQ_WAVE_TTMP0",
1131 "type_ref": "SQ_WAVE_TTMP0"
1135 "map": {"at": 2500, "to": "mm"},
1136 "name": "SQ_WAVE_TTMP1",
1137 "type_ref": "SQ_WAVE_TTMP0"
1141 "map": {"at": 2504, "to": "mm"},
1142 "name": "SQ_WAVE_TTMP2",
1143 "type_ref": "SQ_WAVE_TTMP0"
1147 "map": {"at": 2508, "to": "mm"},
1148 "name": "SQ_WAVE_TTMP3",
1149 "type_ref": "SQ_WAVE_TTMP0"
1153 "map": {"at": 2512, "to": "mm"},
1154 "name": "SQ_WAVE_TTMP4",
1155 "type_ref": "SQ_WAVE_TTMP0"
1159 "map": {"at": 2516, "to": "mm"},
1160 "name": "SQ_WAVE_TTMP5",
1161 "type_ref": "SQ_WAVE_TTMP0"
1165 "map": {"at": 2520, "to": "mm"},
1166 "name": "SQ_WAVE_TTMP6",
1167 "type_ref": "SQ_WAVE_TTMP0"
1171 "map": {"at": 2524, "to": "mm"},
1172 "name": "SQ_WAVE_TTMP7",
1173 "type_ref": "SQ_WAVE_TTMP0"
1177 "map": {"at": 2528, "to": "mm"},
1178 "name": "SQ_WAVE_TTMP8",
1179 "type_ref": "SQ_WAVE_TTMP0"
1183 "map": {"at": 2532, "to": "mm"},
1184 "name": "SQ_WAVE_TTMP9",
1185 "type_ref": "SQ_WAVE_TTMP0"
1189 "map": {"at": 2536, "to": "mm"},
1190 "name": "SQ_WAVE_TTMP10",
1191 "type_ref": "SQ_WAVE_TTMP0"
1195 "map": {"at": 2540, "to": "mm"},
1196 "name": "SQ_WAVE_TTMP11",
1197 "type_ref": "SQ_WAVE_TTMP0"
1201 "map": {"at": 2544, "to": "mm"},
1202 "name": "SQ_WAVE_M0",
1203 "type_ref": "SQ_WAVE_M0"
1207 "map": {"at": 2552, "to": "mm"},
1208 "name": "SQ_WAVE_EXEC_LO",
1209 "type_ref": "SQ_WAVE_EXEC_LO"
1213 "map": {"at": 2556, "to": "mm"},
1214 "name": "SQ_WAVE_EXEC_HI",
1215 "type_ref": "SQ_WAVE_EXEC_HI"
1219 "map": {"at": 32768, "to": "mm"},
1220 "name": "GRBM_CNTL",
1221 "type_ref": "GRBM_CNTL"
1225 "map": {"at": 32772, "to": "mm"},
1226 "name": "GRBM_SKEW_CNTL",
1227 "type_ref": "GRBM_SKEW_CNTL"
1231 "map": {"at": 32776, "to": "mm"},
1232 "name": "GRBM_STATUS2",
1233 "type_ref": "GRBM_STATUS2"
1237 "map": {"at": 32780, "to": "mm"},
1238 "name": "GRBM_PWR_CNTL",
1239 "type_ref": "GRBM_PWR_CNTL"
1243 "map": {"at": 32784, "to": "mm"},
1244 "name": "GRBM_STATUS",
1245 "type_ref": "GRBM_STATUS"
1249 "map": {"at": 32788, "to": "mm"},
1250 "name": "GRBM_STATUS_SE0",
1251 "type_ref": "GRBM_STATUS_SE0"
1255 "map": {"at": 32792, "to": "mm"},
1256 "name": "GRBM_STATUS_SE1",
1257 "type_ref": "GRBM_STATUS_SE0"
1261 "map": {"at": 32800, "to": "mm"},
1262 "name": "GRBM_SOFT_RESET",
1263 "type_ref": "GRBM_SOFT_RESET"
1267 "map": {"at": 32804, "to": "mm"},
1268 "name": "GRBM_DEBUG_CNTL",
1269 "type_ref": "GRBM_DEBUG_CNTL"
1273 "map": {"at": 32808, "to": "mm"},
1274 "name": "GRBM_DEBUG_DATA",
1275 "type_ref": "SQ_WAVE_TTMP0"
1279 "map": {"at": 32812, "to": "mm"},
1280 "name": "GRBM_GFX_INDEX",
1281 "type_ref": "GRBM_GFX_INDEX"
1285 "map": {"at": 32816, "to": "mm"},
1286 "name": "GRBM_GFX_CLKEN_CNTL",
1287 "type_ref": "GRBM_GFX_CLKEN_CNTL"
1291 "map": {"at": 32820, "to": "mm"},
1292 "name": "GRBM_WAIT_IDLE_CLOCKS",
1293 "type_ref": "GRBM_WAIT_IDLE_CLOCKS"
1297 "map": {"at": 32848, "to": "mm"},
1298 "name": "GRBM_DEBUG",
1299 "type_ref": "GRBM_DEBUG"
1303 "map": {"at": 32852, "to": "mm"},
1304 "name": "GRBM_DEBUG_SNAPSHOT",
1305 "type_ref": "GRBM_DEBUG_SNAPSHOT"
1309 "map": {"at": 32856, "to": "mm"},
1310 "name": "GRBM_READ_ERROR",
1311 "type_ref": "GRBM_READ_ERROR"
1315 "map": {"at": 32864, "to": "mm"},
1316 "name": "GRBM_INT_CNTL",
1317 "type_ref": "GRBM_INT_CNTL"
1321 "map": {"at": 32880, "to": "mm"},
1322 "name": "GRBM_PERFCOUNTER0_SELECT",
1323 "type_ref": "GRBM_PERFCOUNTER0_SELECT"
1327 "map": {"at": 32884, "to": "mm"},
1328 "name": "GRBM_PERFCOUNTER1_SELECT",
1329 "type_ref": "GRBM_PERFCOUNTER0_SELECT"
1333 "map": {"at": 32888, "to": "mm"},
1334 "name": "GRBM_PERFCOUNTER0_LO",
1335 "type_ref": "GRBM_PERFCOUNTER0_LO"
1339 "map": {"at": 32892, "to": "mm"},
1340 "name": "GRBM_PERFCOUNTER0_HI",
1341 "type_ref": "GRBM_PERFCOUNTER0_HI"
1345 "map": {"at": 32896, "to": "mm"},
1346 "name": "GRBM_PERFCOUNTER1_LO",
1347 "type_ref": "GRBM_PERFCOUNTER0_LO"
1351 "map": {"at": 32900, "to": "mm"},
1352 "name": "GRBM_PERFCOUNTER1_HI",
1353 "type_ref": "GRBM_PERFCOUNTER0_HI"
1357 "map": {"at": 32920, "to": "mm"},
1358 "name": "GRBM_SE0_PERFCOUNTER_SELECT",
1359 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
1363 "map": {"at": 32924, "to": "mm"},
1364 "name": "GRBM_SE1_PERFCOUNTER_SELECT",
1365 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
1369 "map": {"at": 32936, "to": "mm"},
1370 "name": "GRBM_SE0_PERFCOUNTER_LO",
1371 "type_ref": "GRBM_PERFCOUNTER0_LO"
1375 "map": {"at": 32940, "to": "mm"},
1376 "name": "GRBM_SE0_PERFCOUNTER_HI",
1377 "type_ref": "GRBM_PERFCOUNTER0_HI"
1381 "map": {"at": 32944, "to": "mm"},
1382 "name": "GRBM_SE1_PERFCOUNTER_LO",
1383 "type_ref": "GRBM_PERFCOUNTER0_LO"
1387 "map": {"at": 32948, "to": "mm"},
1388 "name": "GRBM_SE1_PERFCOUNTER_HI",
1389 "type_ref": "GRBM_PERFCOUNTER0_HI"
1393 "map": {"at": 33008, "to": "mm"},
1394 "name": "DEBUG_INDEX",
1395 "type_ref": "DEBUG_INDEX"
1399 "map": {"at": 33012, "to": "mm"},
1400 "name": "DEBUG_DATA",
1401 "type_ref": "DEBUG_DATA"
1405 "map": {"at": 33020, "to": "mm"},
1406 "name": "GRBM_NOWHERE",
1407 "type_ref": "SQ_WAVE_TTMP0"
1411 "map": {"at": 33024, "to": "mm"},
1412 "name": "GRBM_SCRATCH_REG0",
1413 "type_ref": "GRBM_SCRATCH_REG0"
1417 "map": {"at": 33028, "to": "mm"},
1418 "name": "GRBM_SCRATCH_REG1",
1419 "type_ref": "GRBM_SCRATCH_REG1"
1423 "map": {"at": 33032, "to": "mm"},
1424 "name": "GRBM_SCRATCH_REG2",
1425 "type_ref": "GRBM_SCRATCH_REG2"
1429 "map": {"at": 33036, "to": "mm"},
1430 "name": "GRBM_SCRATCH_REG3",
1431 "type_ref": "GRBM_SCRATCH_REG3"
1435 "map": {"at": 33040, "to": "mm"},
1436 "name": "GRBM_SCRATCH_REG4",
1437 "type_ref": "GRBM_SCRATCH_REG4"
1441 "map": {"at": 33044, "to": "mm"},
1442 "name": "GRBM_SCRATCH_REG5",
1443 "type_ref": "GRBM_SCRATCH_REG5"
1447 "map": {"at": 33048, "to": "mm"},
1448 "name": "GRBM_SCRATCH_REG6",
1449 "type_ref": "GRBM_SCRATCH_REG6"
1453 "map": {"at": 33052, "to": "mm"},
1454 "name": "GRBM_SCRATCH_REG7",
1455 "type_ref": "GRBM_SCRATCH_REG7"
1459 "map": {"at": 33536, "to": "mm"},
1460 "name": "SQ_INTERRUPT_WORD_AUTO",
1461 "type_ref": "SQ_INTERRUPT_WORD_AUTO"
1465 "map": {"at": 33792, "to": "mm"},
1466 "name": "CP_EOP_DONE_ADDR_LO",
1467 "type_ref": "CP_EOP_DONE_ADDR_LO"
1471 "map": {"at": 33796, "to": "mm"},
1472 "name": "CP_EOP_DONE_ADDR_HI",
1473 "type_ref": "CP_EOP_DONE_ADDR_HI"
1477 "map": {"at": 33800, "to": "mm"},
1478 "name": "CP_EOP_DONE_DATA_LO",
1479 "type_ref": "CP_EOP_DONE_DATA_LO"
1483 "map": {"at": 33804, "to": "mm"},
1484 "name": "CP_EOP_DONE_DATA_HI",
1485 "type_ref": "CP_EOP_DONE_DATA_HI"
1489 "map": {"at": 33808, "to": "mm"},
1490 "name": "CP_EOP_LAST_FENCE_LO",
1491 "type_ref": "CP_EOP_LAST_FENCE_LO"
1495 "map": {"at": 33812, "to": "mm"},
1496 "name": "CP_EOP_LAST_FENCE_HI",
1497 "type_ref": "CP_EOP_LAST_FENCE_HI"
1501 "map": {"at": 33816, "to": "mm"},
1502 "name": "CP_STREAM_OUT_ADDR_LO",
1503 "type_ref": "CP_STREAM_OUT_ADDR_LO"
1507 "map": {"at": 33820, "to": "mm"},
1508 "name": "CP_STREAM_OUT_ADDR_HI",
1509 "type_ref": "CP_STREAM_OUT_ADDR_HI"
1513 "map": {"at": 33824, "to": "mm"},
1514 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO",
1515 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_LO"
1519 "map": {"at": 33828, "to": "mm"},
1520 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI",
1521 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT0_HI"
1525 "map": {"at": 33832, "to": "mm"},
1526 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO",
1527 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_LO"
1531 "map": {"at": 33836, "to": "mm"},
1532 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI",
1533 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_HI"
1537 "map": {"at": 33840, "to": "mm"},
1538 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO",
1539 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_LO"
1543 "map": {"at": 33844, "to": "mm"},
1544 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI",
1545 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_HI"
1549 "map": {"at": 33848, "to": "mm"},
1550 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO",
1551 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_LO"
1555 "map": {"at": 33852, "to": "mm"},
1556 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI",
1557 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_HI"
1561 "map": {"at": 33856, "to": "mm"},
1562 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO",
1563 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_LO"
1567 "map": {"at": 33860, "to": "mm"},
1568 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI",
1569 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_HI"
1573 "map": {"at": 33864, "to": "mm"},
1574 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO",
1575 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_LO"
1579 "map": {"at": 33868, "to": "mm"},
1580 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI",
1581 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_HI"
1585 "map": {"at": 33872, "to": "mm"},
1586 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO",
1587 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_LO"
1591 "map": {"at": 33876, "to": "mm"},
1592 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI",
1593 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_HI"
1597 "map": {"at": 33880, "to": "mm"},
1598 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO",
1599 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_LO"
1603 "map": {"at": 33884, "to": "mm"},
1604 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI",
1605 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_HI"
1609 "map": {"at": 33888, "to": "mm"},
1610 "name": "CP_PIPE_STATS_ADDR_LO",
1611 "type_ref": "CP_PIPE_STATS_ADDR_LO"
1615 "map": {"at": 33892, "to": "mm"},
1616 "name": "CP_PIPE_STATS_ADDR_HI",
1617 "type_ref": "CP_PIPE_STATS_ADDR_HI"
1621 "map": {"at": 33896, "to": "mm"},
1622 "name": "CP_VGT_IAVERT_COUNT_LO",
1623 "type_ref": "CP_VGT_IAVERT_COUNT_LO"
1627 "map": {"at": 33900, "to": "mm"},
1628 "name": "CP_VGT_IAVERT_COUNT_HI",
1629 "type_ref": "CP_VGT_IAVERT_COUNT_HI"
1633 "map": {"at": 33904, "to": "mm"},
1634 "name": "CP_VGT_IAPRIM_COUNT_LO",
1635 "type_ref": "CP_VGT_IAPRIM_COUNT_LO"
1639 "map": {"at": 33908, "to": "mm"},
1640 "name": "CP_VGT_IAPRIM_COUNT_HI",
1641 "type_ref": "CP_VGT_IAPRIM_COUNT_HI"
1645 "map": {"at": 33912, "to": "mm"},
1646 "name": "CP_VGT_GSPRIM_COUNT_LO",
1647 "type_ref": "CP_VGT_GSPRIM_COUNT_LO"
1651 "map": {"at": 33916, "to": "mm"},
1652 "name": "CP_VGT_GSPRIM_COUNT_HI",
1653 "type_ref": "CP_VGT_GSPRIM_COUNT_HI"
1657 "map": {"at": 33920, "to": "mm"},
1658 "name": "CP_VGT_VSINVOC_COUNT_LO",
1659 "type_ref": "CP_VGT_VSINVOC_COUNT_LO"
1663 "map": {"at": 33924, "to": "mm"},
1664 "name": "CP_VGT_VSINVOC_COUNT_HI",
1665 "type_ref": "CP_VGT_VSINVOC_COUNT_HI"
1669 "map": {"at": 33928, "to": "mm"},
1670 "name": "CP_VGT_GSINVOC_COUNT_LO",
1671 "type_ref": "CP_VGT_GSINVOC_COUNT_LO"
1675 "map": {"at": 33932, "to": "mm"},
1676 "name": "CP_VGT_GSINVOC_COUNT_HI",
1677 "type_ref": "CP_VGT_GSINVOC_COUNT_HI"
1681 "map": {"at": 33936, "to": "mm"},
1682 "name": "CP_VGT_HSINVOC_COUNT_LO",
1683 "type_ref": "CP_VGT_HSINVOC_COUNT_LO"
1687 "map": {"at": 33940, "to": "mm"},
1688 "name": "CP_VGT_HSINVOC_COUNT_HI",
1689 "type_ref": "CP_VGT_HSINVOC_COUNT_HI"
1693 "map": {"at": 33944, "to": "mm"},
1694 "name": "CP_VGT_DSINVOC_COUNT_LO",
1695 "type_ref": "CP_VGT_DSINVOC_COUNT_LO"
1699 "map": {"at": 33948, "to": "mm"},
1700 "name": "CP_VGT_DSINVOC_COUNT_HI",
1701 "type_ref": "CP_VGT_DSINVOC_COUNT_HI"
1705 "map": {"at": 33952, "to": "mm"},
1706 "name": "CP_PA_CINVOC_COUNT_LO",
1707 "type_ref": "CP_PA_CINVOC_COUNT_LO"
1711 "map": {"at": 33956, "to": "mm"},
1712 "name": "CP_PA_CINVOC_COUNT_HI",
1713 "type_ref": "CP_PA_CINVOC_COUNT_HI"
1717 "map": {"at": 33960, "to": "mm"},
1718 "name": "CP_PA_CPRIM_COUNT_LO",
1719 "type_ref": "CP_PA_CPRIM_COUNT_LO"
1723 "map": {"at": 33964, "to": "mm"},
1724 "name": "CP_PA_CPRIM_COUNT_HI",
1725 "type_ref": "CP_PA_CPRIM_COUNT_HI"
1729 "map": {"at": 33968, "to": "mm"},
1730 "name": "CP_SC_PSINVOC_COUNT0_LO",
1731 "type_ref": "CP_SC_PSINVOC_COUNT0_LO"
1735 "map": {"at": 33972, "to": "mm"},
1736 "name": "CP_SC_PSINVOC_COUNT0_HI",
1737 "type_ref": "CP_SC_PSINVOC_COUNT0_HI"
1741 "map": {"at": 33976, "to": "mm"},
1742 "name": "CP_SC_PSINVOC_COUNT1_LO",
1743 "type_ref": "CP_SC_PSINVOC_COUNT1_HI"
1747 "map": {"at": 33980, "to": "mm"},
1748 "name": "CP_SC_PSINVOC_COUNT1_HI",
1749 "type_ref": "CP_SC_PSINVOC_COUNT1_HI"
1753 "map": {"at": 33984, "to": "mm"},
1754 "name": "CP_VGT_CSINVOC_COUNT_LO",
1755 "type_ref": "CP_VGT_CSINVOC_COUNT_LO"
1759 "map": {"at": 33988, "to": "mm"},
1760 "name": "CP_VGT_CSINVOC_COUNT_HI",
1761 "type_ref": "CP_VGT_CSINVOC_COUNT_HI"
1765 "map": {"at": 34044, "to": "mm"},
1766 "name": "CP_STRMOUT_CNTL",
1767 "type_ref": "CP_STRMOUT_CNTL"
1771 "map": {"at": 34048, "to": "mm"},
1772 "name": "SCRATCH_REG0",
1773 "type_ref": "GRBM_SCRATCH_REG0"
1777 "map": {"at": 34052, "to": "mm"},
1778 "name": "SCRATCH_REG1",
1779 "type_ref": "GRBM_SCRATCH_REG1"
1783 "map": {"at": 34056, "to": "mm"},
1784 "name": "SCRATCH_REG2",
1785 "type_ref": "GRBM_SCRATCH_REG2"
1789 "map": {"at": 34060, "to": "mm"},
1790 "name": "SCRATCH_REG3",
1791 "type_ref": "GRBM_SCRATCH_REG3"
1795 "map": {"at": 34064, "to": "mm"},
1796 "name": "SCRATCH_REG4",
1797 "type_ref": "GRBM_SCRATCH_REG4"
1801 "map": {"at": 34068, "to": "mm"},
1802 "name": "SCRATCH_REG5",
1803 "type_ref": "GRBM_SCRATCH_REG5"
1807 "map": {"at": 34072, "to": "mm"},
1808 "name": "SCRATCH_REG6",
1809 "type_ref": "GRBM_SCRATCH_REG6"
1813 "map": {"at": 34076, "to": "mm"},
1814 "name": "SCRATCH_REG7",
1815 "type_ref": "GRBM_SCRATCH_REG7"
1819 "map": {"at": 34112, "to": "mm"},
1820 "name": "SCRATCH_UMSK",
1821 "type_ref": "SCRATCH_UMSK"
1825 "map": {"at": 34116, "to": "mm"},
1826 "name": "SCRATCH_ADDR",
1827 "type_ref": "SCRATCH_ADDR"
1831 "map": {"at": 34144, "to": "mm"},
1832 "name": "CP_APPEND_ADDR_LO",
1833 "type_ref": "CP_APPEND_ADDR_LO"
1837 "map": {"at": 34148, "to": "mm"},
1838 "name": "CP_APPEND_ADDR_HI",
1839 "type_ref": "CP_APPEND_ADDR_HI"
1843 "map": {"at": 34152, "to": "mm"},
1844 "name": "CP_APPEND_DATA",
1845 "type_ref": "SQ_WAVE_TTMP0"
1849 "map": {"at": 34156, "to": "mm"},
1850 "name": "CP_APPEND_LAST_CS_FENCE",
1851 "type_ref": "CP_APPEND_LAST_CS_FENCE"
1855 "map": {"at": 34160, "to": "mm"},
1856 "name": "CP_APPEND_LAST_PS_FENCE",
1857 "type_ref": "CP_APPEND_LAST_CS_FENCE"
1861 "map": {"at": 34164, "to": "mm"},
1862 "name": "CP_ATOMIC_PREOP_LO",
1863 "type_ref": "CP_ATOMIC_PREOP_LO"
1867 "map": {"at": 34168, "to": "mm"},
1868 "name": "CP_ATOMIC_PREOP_HI",
1869 "type_ref": "CP_ATOMIC_PREOP_HI"
1873 "map": {"at": 34172, "to": "mm"},
1874 "name": "CP_GDS_ATOMIC0_PREOP_LO",
1875 "type_ref": "CP_GDS_ATOMIC0_PREOP_LO"
1879 "map": {"at": 34176, "to": "mm"},
1880 "name": "CP_GDS_ATOMIC0_PREOP_HI",
1881 "type_ref": "CP_GDS_ATOMIC0_PREOP_HI"
1885 "map": {"at": 34180, "to": "mm"},
1886 "name": "CP_GDS_ATOMIC1_PREOP_LO",
1887 "type_ref": "CP_GDS_ATOMIC1_PREOP_LO"
1891 "map": {"at": 34184, "to": "mm"},
1892 "name": "CP_GDS_ATOMIC1_PREOP_HI",
1893 "type_ref": "CP_GDS_ATOMIC1_PREOP_HI"
1897 "map": {"at": 34212, "to": "mm"},
1898 "name": "CP_ME_MC_WADDR_LO",
1899 "type_ref": "CP_ME_MC_WADDR_LO"
1903 "map": {"at": 34216, "to": "mm"},
1904 "name": "CP_ME_MC_WADDR_HI",
1905 "type_ref": "CP_ME_MC_WADDR_HI"
1909 "map": {"at": 34220, "to": "mm"},
1910 "name": "CP_ME_MC_WDATA_LO",
1911 "type_ref": "CP_ME_MC_WDATA_LO"
1915 "map": {"at": 34224, "to": "mm"},
1916 "name": "CP_ME_MC_WDATA_HI",
1917 "type_ref": "CP_ME_MC_WDATA_HI"
1921 "map": {"at": 34228, "to": "mm"},
1922 "name": "CP_ME_MC_RADDR_LO",
1923 "type_ref": "CP_ME_MC_RADDR_LO"
1927 "map": {"at": 34232, "to": "mm"},
1928 "name": "CP_ME_MC_RADDR_HI",
1929 "type_ref": "CP_ME_MC_RADDR_HI"
1933 "map": {"at": 34236, "to": "mm"},
1934 "name": "CP_SEM_WAIT_TIMER",
1935 "type_ref": "CP_SEM_WAIT_TIMER"
1939 "map": {"at": 34240, "to": "mm"},
1940 "name": "CP_SIG_SEM_ADDR_LO",
1941 "type_ref": "CP_SIG_SEM_ADDR_LO"
1945 "map": {"at": 34244, "to": "mm"},
1946 "name": "CP_SIG_SEM_ADDR_HI",
1947 "type_ref": "CP_SIG_SEM_ADDR_HI"
1951 "map": {"at": 34256, "to": "mm"},
1952 "name": "CP_WAIT_REG_MEM_TIMEOUT",
1953 "type_ref": "CP_WAIT_REG_MEM_TIMEOUT"
1957 "map": {"at": 34260, "to": "mm"},
1958 "name": "CP_WAIT_SEM_ADDR_LO",
1959 "type_ref": "CP_SIG_SEM_ADDR_LO"
1963 "map": {"at": 34264, "to": "mm"},
1964 "name": "CP_WAIT_SEM_ADDR_HI",
1965 "type_ref": "CP_SIG_SEM_ADDR_HI"
1969 "map": {"at": 34284, "to": "mm"},
1970 "name": "CP_COHER_START_DELAY",
1971 "type_ref": "CP_COHER_START_DELAY"
1975 "map": {"at": 34288, "to": "mm"},
1976 "name": "CP_COHER_CNTL",
1977 "type_ref": "CP_COHER_CNTL"
1981 "map": {"at": 34292, "to": "mm"},
1982 "name": "CP_COHER_SIZE",
1983 "type_ref": "CP_COHER_SIZE"
1987 "map": {"at": 34296, "to": "mm"},
1988 "name": "CP_COHER_BASE",
1989 "type_ref": "CP_COHER_BASE"
1993 "map": {"at": 34300, "to": "mm"},
1994 "name": "CP_COHER_STATUS",
1995 "type_ref": "CP_COHER_STATUS"
1999 "map": {"at": 34304, "to": "mm"},
2000 "name": "CP_DMA_ME_SRC_ADDR",
2001 "type_ref": "CP_DMA_ME_SRC_ADDR"
2005 "map": {"at": 34308, "to": "mm"},
2006 "name": "CP_DMA_ME_SRC_ADDR_HI",
2007 "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
2011 "map": {"at": 34312, "to": "mm"},
2012 "name": "CP_DMA_ME_DST_ADDR",
2013 "type_ref": "CP_DMA_ME_DST_ADDR"
2017 "map": {"at": 34316, "to": "mm"},
2018 "name": "CP_DMA_ME_DST_ADDR_HI",
2019 "type_ref": "CP_DMA_ME_DST_ADDR_HI"
2023 "map": {"at": 34320, "to": "mm"},
2024 "name": "CP_DMA_ME_COMMAND",
2025 "type_ref": "CP_DMA_ME_COMMAND"
2029 "map": {"at": 34324, "to": "mm"},
2030 "name": "CP_DMA_PFP_SRC_ADDR",
2031 "type_ref": "CP_DMA_ME_SRC_ADDR"
2035 "map": {"at": 34328, "to": "mm"},
2036 "name": "CP_DMA_PFP_SRC_ADDR_HI",
2037 "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
2041 "map": {"at": 34332, "to": "mm"},
2042 "name": "CP_DMA_PFP_DST_ADDR",
2043 "type_ref": "CP_DMA_ME_DST_ADDR"
2047 "map": {"at": 34336, "to": "mm"},
2048 "name": "CP_DMA_PFP_DST_ADDR_HI",
2049 "type_ref": "CP_DMA_ME_DST_ADDR_HI"
2053 "map": {"at": 34340, "to": "mm"},
2054 "name": "CP_DMA_PFP_COMMAND",
2055 "type_ref": "CP_DMA_ME_COMMAND"
2059 "map": {"at": 34344, "to": "mm"},
2060 "name": "CP_DMA_CNTL",
2061 "type_ref": "CP_DMA_CNTL"
2065 "map": {"at": 34348, "to": "mm"},
2066 "name": "CP_DMA_READ_TAGS",
2067 "type_ref": "CP_DMA_READ_TAGS"
2071 "map": {"at": 34356, "to": "mm"},
2072 "name": "CP_PFP_IB_CONTROL",
2073 "type_ref": "CP_PFP_IB_CONTROL"
2077 "map": {"at": 34360, "to": "mm"},
2078 "name": "CP_PFP_LOAD_CONTROL",
2079 "type_ref": "CP_PFP_LOAD_CONTROL"
2083 "map": {"at": 34364, "to": "mm"},
2084 "name": "CP_SCRATCH_INDEX",
2085 "type_ref": "CP_SCRATCH_INDEX"
2089 "map": {"at": 34368, "to": "mm"},
2090 "name": "CP_SCRATCH_DATA",
2091 "type_ref": "CP_SCRATCH_DATA"
2095 "map": {"at": 34372, "to": "mm"},
2096 "name": "CP_RB_OFFSET",
2097 "type_ref": "CP_RB_OFFSET"
2101 "map": {"at": 34376, "to": "mm"},
2102 "name": "CP_IB1_OFFSET",
2103 "type_ref": "CP_IB1_OFFSET"
2107 "map": {"at": 34380, "to": "mm"},
2108 "name": "CP_IB2_OFFSET",
2109 "type_ref": "CP_IB2_OFFSET"
2113 "map": {"at": 34384, "to": "mm"},
2114 "name": "CP_IB1_PREAMBLE_BEGIN",
2115 "type_ref": "CP_IB1_PREAMBLE_BEGIN"
2119 "map": {"at": 34388, "to": "mm"},
2120 "name": "CP_IB1_PREAMBLE_END",
2121 "type_ref": "CP_IB1_PREAMBLE_END"
2125 "map": {"at": 34392, "to": "mm"},
2126 "name": "CP_IB2_PREAMBLE_BEGIN",
2127 "type_ref": "CP_IB2_PREAMBLE_BEGIN"
2131 "map": {"at": 34396, "to": "mm"},
2132 "name": "CP_IB2_PREAMBLE_END",
2133 "type_ref": "CP_IB2_PREAMBLE_END"
2137 "map": {"at": 34416, "to": "mm"},
2138 "name": "CP_STALLED_STAT3",
2139 "type_ref": "CP_STALLED_STAT3"
2143 "map": {"at": 34420, "to": "mm"},
2144 "name": "CP_STALLED_STAT1",
2145 "type_ref": "CP_STALLED_STAT1"
2149 "map": {"at": 34424, "to": "mm"},
2150 "name": "CP_STALLED_STAT2",
2151 "type_ref": "CP_STALLED_STAT2"
2155 "map": {"at": 34428, "to": "mm"},
2156 "name": "CP_BUSY_STAT",
2157 "type_ref": "CP_BUSY_STAT"
2161 "map": {"at": 34432, "to": "mm"},
2163 "type_ref": "CP_STAT"
2167 "map": {"at": 34436, "to": "mm"},
2168 "name": "CP_ME_HEADER_DUMP",
2169 "type_ref": "CP_ME_HEADER_DUMP"
2173 "map": {"at": 34440, "to": "mm"},
2174 "name": "CP_PFP_HEADER_DUMP",
2175 "type_ref": "CP_PFP_HEADER_DUMP"
2179 "map": {"at": 34444, "to": "mm"},
2180 "name": "CP_GRBM_FREE_COUNT",
2181 "type_ref": "CP_GRBM_FREE_COUNT"
2185 "map": {"at": 34448, "to": "mm"},
2186 "name": "CP_CE_HEADER_DUMP",
2187 "type_ref": "CP_CE_HEADER_DUMP"
2191 "map": {"at": 34460, "to": "mm"},
2192 "name": "CP_MC_PACK_DELAY_CNT",
2193 "type_ref": "CP_MC_PACK_DELAY_CNT"
2197 "map": {"at": 34512, "to": "mm"},
2198 "name": "CP_CSF_STAT",
2199 "type_ref": "CP_CSF_STAT"
2203 "map": {"at": 34516, "to": "mm"},
2204 "name": "CP_CSF_CNTL",
2205 "type_ref": "CP_CSF_CNTL"
2209 "map": {"at": 34520, "to": "mm"},
2210 "name": "CP_ME_CNTL",
2211 "type_ref": "CP_ME_CNTL"
2215 "map": {"at": 34528, "to": "mm"},
2216 "name": "CP_CNTX_STAT",
2217 "type_ref": "CP_CNTX_STAT"
2221 "map": {"at": 34532, "to": "mm"},
2222 "name": "CP_ME_PREEMPTION",
2223 "type_ref": "CP_ME_PREEMPTION"
2227 "map": {"at": 34552, "to": "mm"},
2228 "name": "CP_RB2_RPTR",
2229 "type_ref": "CP_RB0_RPTR"
2233 "map": {"at": 34556, "to": "mm"},
2234 "name": "CP_RB1_RPTR",
2235 "type_ref": "CP_RB0_RPTR"
2239 "map": {"at": 34560, "to": "mm"},
2240 "name": "CP_RB0_RPTR",
2241 "type_ref": "CP_RB0_RPTR"
2245 "map": {"at": 34564, "to": "mm"},
2246 "name": "CP_RB_WPTR_DELAY",
2247 "type_ref": "CP_RB_WPTR_DELAY"
2251 "map": {"at": 34568, "to": "mm"},
2252 "name": "CP_RB_WPTR_POLL_CNTL",
2253 "type_ref": "CP_RB_WPTR_POLL_CNTL"
2257 "map": {"at": 34572, "to": "mm"},
2258 "name": "CP_CE_INIT_BASE_LO",
2259 "type_ref": "CP_CE_INIT_BASE_LO"
2263 "map": {"at": 34576, "to": "mm"},
2264 "name": "CP_CE_INIT_BASE_HI",
2265 "type_ref": "CP_CE_INIT_BASE_HI"
2269 "map": {"at": 34580, "to": "mm"},
2270 "name": "CP_CE_INIT_BUFSZ",
2271 "type_ref": "CP_CE_INIT_BUFSZ"
2275 "map": {"at": 34584, "to": "mm"},
2276 "name": "CP_CE_IB1_BASE_LO",
2277 "type_ref": "CP_CE_IB1_BASE_LO"
2281 "map": {"at": 34588, "to": "mm"},
2282 "name": "CP_CE_IB1_BASE_HI",
2283 "type_ref": "CP_CE_IB1_BASE_HI"
2287 "map": {"at": 34592, "to": "mm"},
2288 "name": "CP_CE_IB1_BUFSZ",
2289 "type_ref": "CP_CE_IB1_BUFSZ"
2293 "map": {"at": 34596, "to": "mm"},
2294 "name": "CP_CE_IB2_BASE_LO",
2295 "type_ref": "CP_CE_IB2_BASE_LO"
2299 "map": {"at": 34600, "to": "mm"},
2300 "name": "CP_CE_IB2_BASE_HI",
2301 "type_ref": "CP_CE_IB2_BASE_HI"
2305 "map": {"at": 34604, "to": "mm"},
2306 "name": "CP_CE_IB2_BUFSZ",
2307 "type_ref": "CP_CE_IB2_BUFSZ"
2311 "map": {"at": 34608, "to": "mm"},
2312 "name": "CP_IB1_BASE_LO",
2313 "type_ref": "CP_CE_IB1_BASE_LO"
2317 "map": {"at": 34612, "to": "mm"},
2318 "name": "CP_IB1_BASE_HI",
2319 "type_ref": "CP_CE_IB1_BASE_HI"
2323 "map": {"at": 34616, "to": "mm"},
2324 "name": "CP_IB1_BUFSZ",
2325 "type_ref": "CP_CE_IB1_BUFSZ"
2329 "map": {"at": 34620, "to": "mm"},
2330 "name": "CP_IB2_BASE_LO",
2331 "type_ref": "CP_CE_IB2_BASE_LO"
2335 "map": {"at": 34624, "to": "mm"},
2336 "name": "CP_IB2_BASE_HI",
2337 "type_ref": "CP_CE_IB2_BASE_HI"
2341 "map": {"at": 34628, "to": "mm"},
2342 "name": "CP_IB2_BUFSZ",
2343 "type_ref": "CP_CE_IB2_BUFSZ"
2347 "map": {"at": 34632, "to": "mm"},
2348 "name": "CP_ST_BASE_LO",
2349 "type_ref": "CP_ST_BASE_LO"
2353 "map": {"at": 34636, "to": "mm"},
2354 "name": "CP_ST_BASE_HI",
2355 "type_ref": "CP_ST_BASE_HI"
2359 "map": {"at": 34640, "to": "mm"},
2360 "name": "CP_ST_BUFSZ",
2361 "type_ref": "CP_ST_BUFSZ"
2365 "map": {"at": 34644, "to": "mm"},
2366 "name": "CP_ROQ1_THRESHOLDS",
2367 "type_ref": "CP_ROQ1_THRESHOLDS"
2371 "map": {"at": 34648, "to": "mm"},
2372 "name": "CP_ROQ2_THRESHOLDS",
2373 "type_ref": "CP_ROQ2_THRESHOLDS"
2377 "map": {"at": 34652, "to": "mm"},
2378 "name": "CP_STQ_THRESHOLDS",
2379 "type_ref": "CP_STQ_THRESHOLDS"
2383 "map": {"at": 34656, "to": "mm"},
2384 "name": "CP_QUEUE_THRESHOLDS",
2385 "type_ref": "CP_QUEUE_THRESHOLDS"
2389 "map": {"at": 34660, "to": "mm"},
2390 "name": "CP_MEQ_THRESHOLDS",
2391 "type_ref": "CP_MEQ_THRESHOLDS"
2395 "map": {"at": 34664, "to": "mm"},
2396 "name": "CP_ROQ_AVAIL",
2397 "type_ref": "CP_ROQ_AVAIL"
2401 "map": {"at": 34668, "to": "mm"},
2402 "name": "CP_STQ_AVAIL",
2403 "type_ref": "CP_STQ_AVAIL"
2407 "map": {"at": 34672, "to": "mm"},
2408 "name": "CP_ROQ2_AVAIL",
2409 "type_ref": "CP_ROQ2_AVAIL"
2413 "map": {"at": 34676, "to": "mm"},
2414 "name": "CP_MEQ_AVAIL",
2415 "type_ref": "CP_MEQ_AVAIL"
2419 "map": {"at": 34680, "to": "mm"},
2420 "name": "CP_CMD_INDEX",
2421 "type_ref": "CP_CMD_INDEX"
2425 "map": {"at": 34684, "to": "mm"},
2426 "name": "CP_CMD_DATA",
2427 "type_ref": "CP_CMD_DATA"
2431 "map": {"at": 34688, "to": "mm"},
2432 "name": "CP_ROQ_RB_STAT",
2433 "type_ref": "CP_ROQ_RB_STAT"
2437 "map": {"at": 34692, "to": "mm"},
2438 "name": "CP_ROQ_IB1_STAT",
2439 "type_ref": "CP_ROQ_IB1_STAT"
2443 "map": {"at": 34696, "to": "mm"},
2444 "name": "CP_ROQ_IB2_STAT",
2445 "type_ref": "CP_ROQ_IB2_STAT"
2449 "map": {"at": 34700, "to": "mm"},
2450 "name": "CP_STQ_STAT",
2451 "type_ref": "CP_STQ_STAT"
2455 "map": {"at": 34708, "to": "mm"},
2456 "name": "CP_MEQ_STAT",
2457 "type_ref": "CP_MEQ_STAT"
2461 "map": {"at": 34712, "to": "mm"},
2462 "name": "CP_CEQ1_AVAIL",
2463 "type_ref": "CP_CEQ1_AVAIL"
2467 "map": {"at": 34716, "to": "mm"},
2468 "name": "CP_CEQ2_AVAIL",
2469 "type_ref": "CP_CEQ2_AVAIL"
2473 "map": {"at": 34720, "to": "mm"},
2474 "name": "CP_CE_ROQ_RB_STAT",
2475 "type_ref": "CP_CE_ROQ_RB_STAT"
2479 "map": {"at": 34724, "to": "mm"},
2480 "name": "CP_CE_ROQ_IB1_STAT",
2481 "type_ref": "CP_CE_ROQ_IB1_STAT"
2485 "map": {"at": 34728, "to": "mm"},
2486 "name": "CP_CE_ROQ_IB2_STAT",
2487 "type_ref": "CP_CE_ROQ_IB2_STAT"
2491 "map": {"at": 34780, "to": "mm"},
2492 "name": "CP_INT_STAT_DEBUG",
2493 "type_ref": "CP_INT_STAT_DEBUG"
2497 "map": {"at": 34812, "to": "mm"},
2498 "name": "CP_PERFMON_CNTL",
2499 "type_ref": "CP_PERFMON_CNTL"
2503 "map": {"at": 34944, "to": "mm"},
2504 "name": "IA_PERFCOUNTER0_SELECT",
2505 "type_ref": "IA_PERFCOUNTER0_SELECT"
2509 "map": {"at": 34948, "to": "mm"},
2510 "name": "IA_PERFCOUNTER1_SELECT",
2511 "type_ref": "IA_PERFCOUNTER1_SELECT"
2515 "map": {"at": 34952, "to": "mm"},
2516 "name": "IA_PERFCOUNTER2_SELECT",
2517 "type_ref": "IA_PERFCOUNTER1_SELECT"
2521 "map": {"at": 34956, "to": "mm"},
2522 "name": "IA_PERFCOUNTER3_SELECT",
2523 "type_ref": "IA_PERFCOUNTER1_SELECT"
2527 "map": {"at": 34960, "to": "mm"},
2528 "name": "IA_PERFCOUNTER0_LO",
2529 "type_ref": "GRBM_PERFCOUNTER0_LO"
2533 "map": {"at": 34964, "to": "mm"},
2534 "name": "IA_PERFCOUNTER0_HI",
2535 "type_ref": "GRBM_PERFCOUNTER0_HI"
2539 "map": {"at": 34968, "to": "mm"},
2540 "name": "IA_PERFCOUNTER1_LO",
2541 "type_ref": "GRBM_PERFCOUNTER0_LO"
2545 "map": {"at": 34972, "to": "mm"},
2546 "name": "IA_PERFCOUNTER1_HI",
2547 "type_ref": "GRBM_PERFCOUNTER0_HI"
2551 "map": {"at": 34976, "to": "mm"},
2552 "name": "IA_PERFCOUNTER2_LO",
2553 "type_ref": "GRBM_PERFCOUNTER0_LO"
2557 "map": {"at": 34980, "to": "mm"},
2558 "name": "IA_PERFCOUNTER2_HI",
2559 "type_ref": "GRBM_PERFCOUNTER0_HI"
2563 "map": {"at": 34984, "to": "mm"},
2564 "name": "IA_PERFCOUNTER3_LO",
2565 "type_ref": "GRBM_PERFCOUNTER0_LO"
2569 "map": {"at": 34988, "to": "mm"},
2570 "name": "IA_PERFCOUNTER3_HI",
2571 "type_ref": "GRBM_PERFCOUNTER0_HI"
2575 "map": {"at": 34992, "to": "mm"},
2576 "name": "VGT_VTX_VECT_EJECT_REG",
2577 "type_ref": "VGT_VTX_VECT_EJECT_REG"
2581 "map": {"at": 34996, "to": "mm"},
2582 "name": "VGT_DMA_DATA_FIFO_DEPTH",
2583 "type_ref": "VGT_DMA_DATA_FIFO_DEPTH"
2587 "map": {"at": 35000, "to": "mm"},
2588 "name": "VGT_DMA_REQ_FIFO_DEPTH",
2589 "type_ref": "VGT_DMA_REQ_FIFO_DEPTH"
2593 "map": {"at": 35004, "to": "mm"},
2594 "name": "VGT_DRAW_INIT_FIFO_DEPTH",
2595 "type_ref": "VGT_DRAW_INIT_FIFO_DEPTH"
2599 "map": {"at": 35008, "to": "mm"},
2600 "name": "VGT_LAST_COPY_STATE",
2601 "type_ref": "VGT_LAST_COPY_STATE"
2605 "map": {"at": 35012, "to": "mm"},
2606 "name": "VGT_CACHE_INVALIDATION",
2607 "type_ref": "VGT_CACHE_INVALIDATION"
2611 "map": {"at": 35016, "to": "mm"},
2612 "name": "VGT_ESGS_RING_SIZE",
2613 "type_ref": "VGT_ESGS_RING_SIZE"
2617 "map": {"at": 35020, "to": "mm"},
2618 "name": "VGT_GSVS_RING_SIZE",
2619 "type_ref": "VGT_ESGS_RING_SIZE"
2623 "map": {"at": 35024, "to": "mm"},
2624 "name": "VGT_FIFO_DEPTHS",
2625 "type_ref": "VGT_FIFO_DEPTHS"
2629 "map": {"at": 35028, "to": "mm"},
2630 "name": "VGT_GS_VERTEX_REUSE",
2631 "type_ref": "VGT_GS_VERTEX_REUSE"
2635 "map": {"at": 35032, "to": "mm"},
2636 "name": "VGT_MC_LAT_CNTL",
2637 "type_ref": "VGT_MC_LAT_CNTL"
2641 "map": {"at": 35036, "to": "mm"},
2642 "name": "IA_CNTL_STATUS",
2643 "type_ref": "IA_CNTL_STATUS"
2647 "map": {"at": 35040, "to": "mm"},
2648 "name": "VGT_DEBUG_CNTL",
2649 "type_ref": "VGT_DEBUG_CNTL"
2653 "map": {"at": 35044, "to": "mm"},
2654 "name": "VGT_DEBUG_DATA",
2655 "type_ref": "SQ_WAVE_TTMP0"
2659 "map": {"at": 35048, "to": "mm"},
2660 "name": "IA_DEBUG_CNTL",
2661 "type_ref": "IA_DEBUG_CNTL"
2665 "map": {"at": 35052, "to": "mm"},
2666 "name": "IA_DEBUG_DATA",
2667 "type_ref": "SQ_WAVE_TTMP0"
2671 "map": {"at": 35056, "to": "mm"},
2672 "name": "VGT_CNTL_STATUS",
2673 "type_ref": "VGT_CNTL_STATUS"
2677 "map": {"at": 35100, "to": "mm"},
2678 "name": "VGT_PERFCOUNTER_SEID_MASK",
2679 "type_ref": "VGT_PERFCOUNTER_SEID_MASK"
2683 "map": {"at": 35104, "to": "mm"},
2684 "name": "VGT_PERFCOUNTER0_SELECT",
2685 "type_ref": "IA_PERFCOUNTER0_SELECT"
2689 "map": {"at": 35108, "to": "mm"},
2690 "name": "VGT_PERFCOUNTER1_SELECT",
2691 "type_ref": "IA_PERFCOUNTER0_SELECT"
2695 "map": {"at": 35112, "to": "mm"},
2696 "name": "VGT_PERFCOUNTER2_SELECT",
2697 "type_ref": "IA_PERFCOUNTER1_SELECT"
2701 "map": {"at": 35116, "to": "mm"},
2702 "name": "VGT_PERFCOUNTER3_SELECT",
2703 "type_ref": "IA_PERFCOUNTER1_SELECT"
2707 "map": {"at": 35120, "to": "mm"},
2708 "name": "VGT_PERFCOUNTER0_LO",
2709 "type_ref": "GRBM_PERFCOUNTER0_LO"
2713 "map": {"at": 35124, "to": "mm"},
2714 "name": "VGT_PERFCOUNTER0_HI",
2715 "type_ref": "GRBM_PERFCOUNTER0_HI"
2719 "map": {"at": 35128, "to": "mm"},
2720 "name": "VGT_PERFCOUNTER1_LO",
2721 "type_ref": "GRBM_PERFCOUNTER0_LO"
2725 "map": {"at": 35132, "to": "mm"},
2726 "name": "VGT_PERFCOUNTER1_HI",
2727 "type_ref": "GRBM_PERFCOUNTER0_HI"
2731 "map": {"at": 35136, "to": "mm"},
2732 "name": "VGT_PERFCOUNTER2_LO",
2733 "type_ref": "GRBM_PERFCOUNTER0_LO"
2737 "map": {"at": 35140, "to": "mm"},
2738 "name": "VGT_PERFCOUNTER2_HI",
2739 "type_ref": "GRBM_PERFCOUNTER0_HI"
2743 "map": {"at": 35144, "to": "mm"},
2744 "name": "VGT_PERFCOUNTER3_LO",
2745 "type_ref": "GRBM_PERFCOUNTER0_LO"
2749 "map": {"at": 35148, "to": "mm"},
2750 "name": "VGT_PERFCOUNTER3_HI",
2751 "type_ref": "GRBM_PERFCOUNTER0_HI"
2755 "map": {"at": 35160, "to": "mm"},
2756 "name": "VGT_PRIMITIVE_TYPE",
2757 "type_ref": "VGT_PRIMITIVE_TYPE"
2761 "map": {"at": 35164, "to": "mm"},
2762 "name": "VGT_INDEX_TYPE",
2763 "type_ref": "VGT_INDEX_TYPE"
2767 "map": {"at": 35168, "to": "mm"},
2768 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0",
2769 "type_ref": "COMPUTE_DIM_X"
2773 "map": {"at": 35172, "to": "mm"},
2774 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1",
2775 "type_ref": "COMPUTE_DIM_X"
2779 "map": {"at": 35176, "to": "mm"},
2780 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2",
2781 "type_ref": "COMPUTE_DIM_X"
2785 "map": {"at": 35180, "to": "mm"},
2786 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3",
2787 "type_ref": "COMPUTE_DIM_X"
2791 "map": {"at": 35184, "to": "mm"},
2792 "name": "VGT_NUM_INDICES",
2793 "type_ref": "VGT_DMA_SIZE"
2797 "map": {"at": 35188, "to": "mm"},
2798 "name": "VGT_NUM_INSTANCES",
2799 "type_ref": "VGT_DMA_NUM_INSTANCES"
2803 "map": {"at": 35196, "to": "mm"},
2804 "name": "CGTT_VGT_CLK_CTRL",
2805 "type_ref": "CGTT_VGT_CLK_CTRL"
2809 "map": {"at": 35200, "to": "mm"},
2810 "name": "IA_VMID_OVERRIDE",
2811 "type_ref": "IA_VMID_OVERRIDE"
2815 "map": {"at": 35204, "to": "mm"},
2816 "name": "CGTT_IA_CLK_CTRL",
2817 "type_ref": "CGTT_IA_CLK_CTRL"
2821 "map": {"at": 35208, "to": "mm"},
2822 "name": "VGT_TF_RING_SIZE",
2823 "type_ref": "VGT_TF_RING_SIZE"
2827 "map": {"at": 35212, "to": "mm"},
2828 "name": "VGT_SYS_CONFIG",
2829 "type_ref": "VGT_SYS_CONFIG"
2833 "map": {"at": 35248, "to": "mm"},
2834 "name": "VGT_HS_OFFCHIP_PARAM",
2835 "type_ref": "VGT_HS_OFFCHIP_PARAM"
2839 "map": {"at": 35256, "to": "mm"},
2840 "name": "VGT_TF_MEMORY_BASE",
2841 "type_ref": "VGT_TF_MEMORY_BASE"
2845 "map": {"at": 35260, "to": "mm"},
2846 "name": "CC_GC_SHADER_ARRAY_CONFIG",
2847 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG"
2851 "map": {"at": 35264, "to": "mm"},
2852 "name": "GC_USER_SHADER_ARRAY_CONFIG",
2853 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG"
2857 "map": {"at": 35328, "to": "mm"},
2858 "name": "PA_SU_DEBUG_CNTL",
2859 "type_ref": "PA_SU_DEBUG_CNTL"
2863 "map": {"at": 35332, "to": "mm"},
2864 "name": "PA_SU_DEBUG_DATA",
2865 "type_ref": "SQ_WAVE_TTMP0"
2869 "map": {"at": 35344, "to": "mm"},
2870 "name": "PA_CL_CNTL_STATUS",
2871 "type_ref": "PA_CL_CNTL_STATUS"
2875 "map": {"at": 35348, "to": "mm"},
2876 "name": "PA_CL_ENHANCE",
2877 "type_ref": "PA_CL_ENHANCE"
2881 "map": {"at": 35352, "to": "mm"},
2882 "name": "CGTT_PA_CLK_CTRL",
2883 "type_ref": "CGTT_PA_CLK_CTRL"
2887 "map": {"at": 35360, "to": "mm"},
2888 "name": "PA_SU_PERFCOUNTER0_SELECT",
2889 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
2893 "map": {"at": 35364, "to": "mm"},
2894 "name": "PA_SU_PERFCOUNTER1_SELECT",
2895 "type_ref": "PA_SU_PERFCOUNTER0_SELECT"
2899 "map": {"at": 35368, "to": "mm"},
2900 "name": "PA_SU_PERFCOUNTER2_SELECT",
2901 "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
2905 "map": {"at": 35372, "to": "mm"},
2906 "name": "PA_SU_PERFCOUNTER3_SELECT",
2907 "type_ref": "PA_SU_PERFCOUNTER2_SELECT"
2911 "map": {"at": 35376, "to": "mm"},
2912 "name": "PA_SU_PERFCOUNTER0_LO",
2913 "type_ref": "GRBM_PERFCOUNTER0_LO"
2917 "map": {"at": 35380, "to": "mm"},
2918 "name": "PA_SU_PERFCOUNTER0_HI",
2919 "type_ref": "PA_SU_PERFCOUNTER0_HI"
2923 "map": {"at": 35384, "to": "mm"},
2924 "name": "PA_SU_PERFCOUNTER1_LO",
2925 "type_ref": "GRBM_PERFCOUNTER0_LO"
2929 "map": {"at": 35388, "to": "mm"},
2930 "name": "PA_SU_PERFCOUNTER1_HI",
2931 "type_ref": "PA_SU_PERFCOUNTER0_HI"
2935 "map": {"at": 35392, "to": "mm"},
2936 "name": "PA_SU_PERFCOUNTER2_LO",
2937 "type_ref": "GRBM_PERFCOUNTER0_LO"
2941 "map": {"at": 35396, "to": "mm"},
2942 "name": "PA_SU_PERFCOUNTER2_HI",
2943 "type_ref": "PA_SU_PERFCOUNTER0_HI"
2947 "map": {"at": 35400, "to": "mm"},
2948 "name": "PA_SU_PERFCOUNTER3_LO",
2949 "type_ref": "GRBM_PERFCOUNTER0_LO"
2953 "map": {"at": 35404, "to": "mm"},
2954 "name": "PA_SU_PERFCOUNTER3_HI",
2955 "type_ref": "PA_SU_PERFCOUNTER0_HI"
2959 "map": {"at": 35408, "to": "mm"},
2960 "name": "PA_SU_CNTL_STATUS",
2961 "type_ref": "PA_SU_CNTL_STATUS"
2965 "map": {"at": 35412, "to": "mm"},
2966 "name": "PA_SC_FIFO_DEPTH_CNTL",
2967 "type_ref": "PA_SC_FIFO_DEPTH_CNTL"
2971 "map": {"at": 35424, "to": "mm"},
2972 "name": "PA_SU_LINE_STIPPLE_VALUE",
2973 "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
2977 "map": {"at": 35456, "to": "mm"},
2978 "name": "PA_SC_PERFCOUNTER0_SELECT",
2979 "type_ref": "PA_SC_PERFCOUNTER0_SELECT"
2983 "map": {"at": 35460, "to": "mm"},
2984 "name": "PA_SC_PERFCOUNTER1_SELECT",
2985 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
2989 "map": {"at": 35464, "to": "mm"},
2990 "name": "PA_SC_PERFCOUNTER2_SELECT",
2991 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
2995 "map": {"at": 35468, "to": "mm"},
2996 "name": "PA_SC_PERFCOUNTER3_SELECT",
2997 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
3001 "map": {"at": 35472, "to": "mm"},
3002 "name": "PA_SC_PERFCOUNTER4_SELECT",
3003 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
3007 "map": {"at": 35476, "to": "mm"},
3008 "name": "PA_SC_PERFCOUNTER5_SELECT",
3009 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
3013 "map": {"at": 35480, "to": "mm"},
3014 "name": "PA_SC_PERFCOUNTER6_SELECT",
3015 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
3019 "map": {"at": 35484, "to": "mm"},
3020 "name": "PA_SC_PERFCOUNTER7_SELECT",
3021 "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
3025 "map": {"at": 35488, "to": "mm"},
3026 "name": "PA_SC_PERFCOUNTER0_LO",
3027 "type_ref": "GRBM_PERFCOUNTER0_LO"
3031 "map": {"at": 35492, "to": "mm"},
3032 "name": "PA_SC_PERFCOUNTER0_HI",
3033 "type_ref": "GRBM_PERFCOUNTER0_HI"
3037 "map": {"at": 35496, "to": "mm"},
3038 "name": "PA_SC_PERFCOUNTER1_LO",
3039 "type_ref": "GRBM_PERFCOUNTER0_LO"
3043 "map": {"at": 35500, "to": "mm"},
3044 "name": "PA_SC_PERFCOUNTER1_HI",
3045 "type_ref": "GRBM_PERFCOUNTER0_HI"
3049 "map": {"at": 35504, "to": "mm"},
3050 "name": "PA_SC_PERFCOUNTER2_LO",
3051 "type_ref": "GRBM_PERFCOUNTER0_LO"
3055 "map": {"at": 35508, "to": "mm"},
3056 "name": "PA_SC_PERFCOUNTER2_HI",
3057 "type_ref": "GRBM_PERFCOUNTER0_HI"
3061 "map": {"at": 35512, "to": "mm"},
3062 "name": "PA_SC_PERFCOUNTER3_LO",
3063 "type_ref": "GRBM_PERFCOUNTER0_LO"
3067 "map": {"at": 35516, "to": "mm"},
3068 "name": "PA_SC_PERFCOUNTER3_HI",
3069 "type_ref": "GRBM_PERFCOUNTER0_HI"
3073 "map": {"at": 35520, "to": "mm"},
3074 "name": "PA_SC_PERFCOUNTER4_LO",
3075 "type_ref": "GRBM_PERFCOUNTER0_LO"
3079 "map": {"at": 35524, "to": "mm"},
3080 "name": "PA_SC_PERFCOUNTER4_HI",
3081 "type_ref": "GRBM_PERFCOUNTER0_HI"
3085 "map": {"at": 35528, "to": "mm"},
3086 "name": "PA_SC_PERFCOUNTER5_LO",
3087 "type_ref": "GRBM_PERFCOUNTER0_LO"
3091 "map": {"at": 35532, "to": "mm"},
3092 "name": "PA_SC_PERFCOUNTER5_HI",
3093 "type_ref": "GRBM_PERFCOUNTER0_HI"
3097 "map": {"at": 35536, "to": "mm"},
3098 "name": "PA_SC_PERFCOUNTER6_LO",
3099 "type_ref": "GRBM_PERFCOUNTER0_LO"
3103 "map": {"at": 35540, "to": "mm"},
3104 "name": "PA_SC_PERFCOUNTER6_HI",
3105 "type_ref": "GRBM_PERFCOUNTER0_HI"
3109 "map": {"at": 35544, "to": "mm"},
3110 "name": "PA_SC_PERFCOUNTER7_LO",
3111 "type_ref": "GRBM_PERFCOUNTER0_LO"
3115 "map": {"at": 35548, "to": "mm"},
3116 "name": "PA_SC_PERFCOUNTER7_HI",
3117 "type_ref": "GRBM_PERFCOUNTER0_HI"
3121 "map": {"at": 35600, "to": "mm"},
3122 "name": "PA_SC_LINE_STIPPLE_STATE",
3123 "type_ref": "PA_SC_LINE_STIPPLE_STATE"
3127 "map": {"at": 35620, "to": "mm"},
3128 "name": "PA_SC_FORCE_EOV_MAX_CNTS",
3129 "type_ref": "PA_SC_FORCE_EOV_MAX_CNTS"
3133 "map": {"at": 35624, "to": "mm"},
3134 "name": "CGTT_SC_CLK_CTRL",
3135 "type_ref": "CGTT_SC_CLK_CTRL"
3139 "map": {"at": 35788, "to": "mm"},
3140 "name": "PA_SC_FIFO_SIZE",
3141 "type_ref": "PA_SC_FIFO_SIZE"
3145 "map": {"at": 35796, "to": "mm"},
3146 "name": "PA_SC_IF_FIFO_SIZE",
3147 "type_ref": "PA_SC_IF_FIFO_SIZE"
3151 "map": {"at": 35800, "to": "mm"},
3152 "name": "PA_SC_DEBUG_CNTL",
3153 "type_ref": "PA_SC_DEBUG_CNTL"
3157 "map": {"at": 35804, "to": "mm"},
3158 "name": "PA_SC_DEBUG_DATA",
3159 "type_ref": "SQ_WAVE_TTMP0"
3163 "map": {"at": 35824, "to": "mm"},
3164 "name": "PA_SC_ENHANCE",
3165 "type_ref": "PA_SC_ENHANCE"
3169 "map": {"at": 35840, "to": "mm"},
3170 "name": "SQ_CONFIG",
3171 "type_ref": "SQ_CONFIG"
3175 "map": {"at": 35844, "to": "mm"},
3176 "name": "SQC_CONFIG",
3177 "type_ref": "SQC_CONFIG"
3181 "map": {"at": 35848, "to": "mm"},
3182 "name": "SQC_CACHES",
3183 "type_ref": "SQC_CACHES"
3187 "map": {"at": 35852, "to": "mm"},
3188 "name": "SQ_RANDOM_WAVE_PRI",
3189 "type_ref": "SQ_RANDOM_WAVE_PRI"
3193 "map": {"at": 35856, "to": "mm"},
3194 "name": "SQ_REG_CREDITS",
3195 "type_ref": "SQ_REG_CREDITS"
3199 "map": {"at": 35860, "to": "mm"},
3200 "name": "SQ_FIFO_SIZES",
3201 "type_ref": "SQ_FIFO_SIZES"
3205 "map": {"at": 35864, "to": "mm"},
3206 "name": "SQ_PERFCOUNTER_CTRL",
3207 "type_ref": "SQ_PERFCOUNTER_CTRL"
3211 "map": {"at": 35868, "to": "mm"},
3212 "name": "CC_SQC_BANK_DISABLE",
3213 "type_ref": "CC_SQC_BANK_DISABLE"
3217 "map": {"at": 35872, "to": "mm"},
3218 "name": "USER_SQC_BANK_DISABLE",
3219 "type_ref": "CC_SQC_BANK_DISABLE"
3223 "map": {"at": 35876, "to": "mm"},
3224 "name": "SQ_DEBUG_STS_GLOBAL",
3225 "type_ref": "SQ_DEBUG_STS_GLOBAL"
3229 "map": {"at": 35968, "to": "mm"},
3230 "name": "SQ_PERFCOUNTER0_LO",
3231 "type_ref": "GRBM_PERFCOUNTER0_LO"
3235 "map": {"at": 35972, "to": "mm"},
3236 "name": "SQ_PERFCOUNTER0_HI",
3237 "type_ref": "GRBM_PERFCOUNTER0_HI"
3241 "map": {"at": 35976, "to": "mm"},
3242 "name": "SQ_PERFCOUNTER1_LO",
3243 "type_ref": "GRBM_PERFCOUNTER0_LO"
3247 "map": {"at": 35980, "to": "mm"},
3248 "name": "SQ_PERFCOUNTER1_HI",
3249 "type_ref": "GRBM_PERFCOUNTER0_HI"
3253 "map": {"at": 35984, "to": "mm"},
3254 "name": "SQ_PERFCOUNTER2_LO",
3255 "type_ref": "GRBM_PERFCOUNTER0_LO"
3259 "map": {"at": 35988, "to": "mm"},
3260 "name": "SQ_PERFCOUNTER2_HI",
3261 "type_ref": "GRBM_PERFCOUNTER0_HI"
3265 "map": {"at": 35992, "to": "mm"},
3266 "name": "SQ_PERFCOUNTER3_LO",
3267 "type_ref": "GRBM_PERFCOUNTER0_LO"
3271 "map": {"at": 35996, "to": "mm"},
3272 "name": "SQ_PERFCOUNTER3_HI",
3273 "type_ref": "GRBM_PERFCOUNTER0_HI"
3277 "map": {"at": 36000, "to": "mm"},
3278 "name": "SQ_PERFCOUNTER4_LO",
3279 "type_ref": "GRBM_PERFCOUNTER0_LO"
3283 "map": {"at": 36004, "to": "mm"},
3284 "name": "SQ_PERFCOUNTER4_HI",
3285 "type_ref": "GRBM_PERFCOUNTER0_HI"
3289 "map": {"at": 36008, "to": "mm"},
3290 "name": "SQ_PERFCOUNTER5_LO",
3291 "type_ref": "GRBM_PERFCOUNTER0_LO"
3295 "map": {"at": 36012, "to": "mm"},
3296 "name": "SQ_PERFCOUNTER5_HI",
3297 "type_ref": "GRBM_PERFCOUNTER0_HI"
3301 "map": {"at": 36016, "to": "mm"},
3302 "name": "SQ_PERFCOUNTER6_LO",
3303 "type_ref": "GRBM_PERFCOUNTER0_LO"
3307 "map": {"at": 36020, "to": "mm"},
3308 "name": "SQ_PERFCOUNTER6_HI",
3309 "type_ref": "GRBM_PERFCOUNTER0_HI"
3313 "map": {"at": 36024, "to": "mm"},
3314 "name": "SQ_PERFCOUNTER7_LO",
3315 "type_ref": "GRBM_PERFCOUNTER0_LO"
3319 "map": {"at": 36028, "to": "mm"},
3320 "name": "SQ_PERFCOUNTER7_HI",
3321 "type_ref": "GRBM_PERFCOUNTER0_HI"
3325 "map": {"at": 36032, "to": "mm"},
3326 "name": "SQ_PERFCOUNTER8_LO",
3327 "type_ref": "GRBM_PERFCOUNTER0_LO"
3331 "map": {"at": 36036, "to": "mm"},
3332 "name": "SQ_PERFCOUNTER8_HI",
3333 "type_ref": "GRBM_PERFCOUNTER0_HI"
3337 "map": {"at": 36040, "to": "mm"},
3338 "name": "SQ_PERFCOUNTER9_LO",
3339 "type_ref": "GRBM_PERFCOUNTER0_LO"
3343 "map": {"at": 36044, "to": "mm"},
3344 "name": "SQ_PERFCOUNTER9_HI",
3345 "type_ref": "GRBM_PERFCOUNTER0_HI"
3349 "map": {"at": 36048, "to": "mm"},
3350 "name": "SQ_PERFCOUNTER10_LO",
3351 "type_ref": "GRBM_PERFCOUNTER0_LO"
3355 "map": {"at": 36052, "to": "mm"},
3356 "name": "SQ_PERFCOUNTER10_HI",
3357 "type_ref": "GRBM_PERFCOUNTER0_HI"
3361 "map": {"at": 36056, "to": "mm"},
3362 "name": "SQ_PERFCOUNTER11_LO",
3363 "type_ref": "GRBM_PERFCOUNTER0_LO"
3367 "map": {"at": 36060, "to": "mm"},
3368 "name": "SQ_PERFCOUNTER11_HI",
3369 "type_ref": "GRBM_PERFCOUNTER0_HI"
3373 "map": {"at": 36064, "to": "mm"},
3374 "name": "SQ_PERFCOUNTER12_LO",
3375 "type_ref": "GRBM_PERFCOUNTER0_LO"
3379 "map": {"at": 36068, "to": "mm"},
3380 "name": "SQ_PERFCOUNTER12_HI",
3381 "type_ref": "GRBM_PERFCOUNTER0_HI"
3385 "map": {"at": 36072, "to": "mm"},
3386 "name": "SQ_PERFCOUNTER13_LO",
3387 "type_ref": "GRBM_PERFCOUNTER0_LO"
3391 "map": {"at": 36076, "to": "mm"},
3392 "name": "SQ_PERFCOUNTER13_HI",
3393 "type_ref": "GRBM_PERFCOUNTER0_HI"
3397 "map": {"at": 36080, "to": "mm"},
3398 "name": "SQ_PERFCOUNTER14_LO",
3399 "type_ref": "GRBM_PERFCOUNTER0_LO"
3403 "map": {"at": 36084, "to": "mm"},
3404 "name": "SQ_PERFCOUNTER14_HI",
3405 "type_ref": "GRBM_PERFCOUNTER0_HI"
3409 "map": {"at": 36088, "to": "mm"},
3410 "name": "SQ_PERFCOUNTER15_LO",
3411 "type_ref": "GRBM_PERFCOUNTER0_LO"
3415 "map": {"at": 36092, "to": "mm"},
3416 "name": "SQ_PERFCOUNTER15_HI",
3417 "type_ref": "GRBM_PERFCOUNTER0_HI"
3421 "map": {"at": 36096, "to": "mm"},
3422 "name": "SQ_PERFCOUNTER0_SELECT",
3423 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3427 "map": {"at": 36100, "to": "mm"},
3428 "name": "SQ_PERFCOUNTER1_SELECT",
3429 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3433 "map": {"at": 36104, "to": "mm"},
3434 "name": "SQ_PERFCOUNTER2_SELECT",
3435 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3439 "map": {"at": 36108, "to": "mm"},
3440 "name": "SQ_PERFCOUNTER3_SELECT",
3441 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3445 "map": {"at": 36112, "to": "mm"},
3446 "name": "SQ_PERFCOUNTER4_SELECT",
3447 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3451 "map": {"at": 36116, "to": "mm"},
3452 "name": "SQ_PERFCOUNTER5_SELECT",
3453 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3457 "map": {"at": 36120, "to": "mm"},
3458 "name": "SQ_PERFCOUNTER6_SELECT",
3459 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3463 "map": {"at": 36124, "to": "mm"},
3464 "name": "SQ_PERFCOUNTER7_SELECT",
3465 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3469 "map": {"at": 36128, "to": "mm"},
3470 "name": "SQ_PERFCOUNTER8_SELECT",
3471 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3475 "map": {"at": 36132, "to": "mm"},
3476 "name": "SQ_PERFCOUNTER9_SELECT",
3477 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3481 "map": {"at": 36136, "to": "mm"},
3482 "name": "SQ_PERFCOUNTER10_SELECT",
3483 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3487 "map": {"at": 36140, "to": "mm"},
3488 "name": "SQ_PERFCOUNTER11_SELECT",
3489 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3493 "map": {"at": 36144, "to": "mm"},
3494 "name": "SQ_PERFCOUNTER12_SELECT",
3495 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3499 "map": {"at": 36148, "to": "mm"},
3500 "name": "SQ_PERFCOUNTER13_SELECT",
3501 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3505 "map": {"at": 36152, "to": "mm"},
3506 "name": "SQ_PERFCOUNTER14_SELECT",
3507 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3511 "map": {"at": 36156, "to": "mm"},
3512 "name": "SQ_PERFCOUNTER15_SELECT",
3513 "type_ref": "SQ_PERFCOUNTER0_SELECT"
3517 "map": {"at": 36224, "to": "mm"},
3518 "name": "SQ_ALU_CLK_CTRL",
3519 "type_ref": "SQ_ALU_CLK_CTRL"
3523 "map": {"at": 36228, "to": "mm"},
3524 "name": "SQ_TEX_CLK_CTRL",
3525 "type_ref": "SQ_ALU_CLK_CTRL"
3529 "map": {"at": 36232, "to": "mm"},
3530 "name": "CGTT_SQ_CLK_CTRL",
3531 "type_ref": "CGTT_SQ_CLK_CTRL"
3535 "map": {"at": 36236, "to": "mm"},
3536 "name": "CGTT_SQG_CLK_CTRL",
3537 "type_ref": "CGTT_SQ_CLK_CTRL"
3541 "map": {"at": 36320, "to": "mm"},
3542 "name": "SQ_IND_INDEX",
3543 "type_ref": "SQ_IND_INDEX"
3547 "map": {"at": 36324, "to": "mm"},
3548 "name": "SQ_IND_DATA",
3549 "type_ref": "SQ_WAVE_TTMP0"
3553 "map": {"at": 36336, "to": "mm"},
3554 "name": "SQ_TIME_HI",
3555 "type_ref": "SQ_TIME_HI"
3559 "map": {"at": 36340, "to": "mm"},
3560 "name": "SQ_TIME_LO",
3561 "type_ref": "SQ_TIME_HI"
3565 "map": {"at": 36352, "to": "mm"},
3566 "name": "SQ_THREAD_TRACE_BASE",
3567 "type_ref": "SQ_THREAD_TRACE_BASE"
3571 "map": {"at": 36356, "to": "mm"},
3572 "name": "SQ_THREAD_TRACE_SIZE",
3573 "type_ref": "SQ_THREAD_TRACE_SIZE"
3577 "map": {"at": 36360, "to": "mm"},
3578 "name": "SQ_THREAD_TRACE_MASK",
3579 "type_ref": "SQ_THREAD_TRACE_MASK"
3583 "map": {"at": 36364, "to": "mm"},
3584 "name": "SQ_THREAD_TRACE_TOKEN_MASK",
3585 "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
3589 "map": {"at": 36368, "to": "mm"},
3590 "name": "SQ_THREAD_TRACE_PERF_MASK",
3591 "type_ref": "SQ_THREAD_TRACE_PERF_MASK"
3595 "map": {"at": 36384, "to": "mm"},
3596 "name": "SQ_THREAD_TRACE_USERDATA_0",
3597 "type_ref": "SQ_WAVE_TTMP0"
3601 "map": {"at": 36388, "to": "mm"},
3602 "name": "SQ_THREAD_TRACE_USERDATA_1",
3603 "type_ref": "SQ_WAVE_TTMP0"
3607 "map": {"at": 36392, "to": "mm"},
3608 "name": "SQ_THREAD_TRACE_USERDATA_2",
3609 "type_ref": "SQ_WAVE_TTMP0"
3613 "map": {"at": 36396, "to": "mm"},
3614 "name": "SQ_THREAD_TRACE_USERDATA_3",
3615 "type_ref": "SQ_WAVE_TTMP0"
3619 "map": {"at": 36400, "to": "mm"},
3620 "name": "SQ_THREAD_TRACE_WPTR",
3621 "type_ref": "SQ_THREAD_TRACE_WPTR"
3625 "map": {"at": 36404, "to": "mm"},
3626 "name": "SQ_THREAD_TRACE_STATUS",
3627 "type_ref": "SQ_THREAD_TRACE_STATUS"
3631 "map": {"at": 36408, "to": "mm"},
3632 "name": "SQ_THREAD_TRACE_MODE",
3633 "type_ref": "SQ_THREAD_TRACE_MODE"
3637 "map": {"at": 36412, "to": "mm"},
3638 "name": "SQ_THREAD_TRACE_CTRL",
3639 "type_ref": "SQ_THREAD_TRACE_CTRL"
3643 "map": {"at": 36416, "to": "mm"},
3644 "name": "SQ_THREAD_TRACE_CNTR",
3645 "type_ref": "SQ_THREAD_TRACE_CNTR"
3649 "map": {"at": 36424, "to": "mm"},
3650 "name": "SQ_THREAD_TRACE_HIWATER",
3651 "type_ref": "SQ_THREAD_TRACE_HIWATER"
3655 "map": {"at": 36440, "to": "mm"},
3656 "name": "SQ_POWER_THROTTLE",
3657 "type_ref": "SQ_POWER_THROTTLE"
3661 "map": {"at": 36444, "to": "mm"},
3662 "name": "SQ_POWER_THROTTLE2",
3663 "type_ref": "SQ_POWER_THROTTLE2"
3667 "map": {"at": 36448, "to": "mm"},
3668 "name": "SQ_LB_CTR_CTRL",
3669 "type_ref": "SQ_LB_CTR_CTRL"
3673 "map": {"at": 36452, "to": "mm"},
3674 "name": "SQ_LB_DATA_ALU_CYCLES",
3675 "type_ref": "SQ_WAVE_TTMP0"
3679 "map": {"at": 36456, "to": "mm"},
3680 "name": "SQ_LB_DATA_TEX_CYCLES",
3681 "type_ref": "SQ_WAVE_TTMP0"
3685 "map": {"at": 36460, "to": "mm"},
3686 "name": "SQ_LB_DATA_ALU_STALLS",
3687 "type_ref": "SQ_WAVE_TTMP0"
3691 "map": {"at": 36464, "to": "mm"},
3692 "name": "SQ_LB_DATA_TEX_STALLS",
3693 "type_ref": "SQ_WAVE_TTMP0"
3697 "map": {"at": 36480, "to": "mm"},
3698 "name": "SQC_SECDED_CNT",
3699 "type_ref": "SQC_SECDED_CNT"
3703 "map": {"at": 36484, "to": "mm"},
3704 "name": "SQ_SEC_CNT",
3705 "type_ref": "SQ_SEC_CNT"
3709 "map": {"at": 36488, "to": "mm"},
3710 "name": "SQ_DED_CNT",
3711 "type_ref": "SQ_DED_CNT"
3715 "map": {"at": 36492, "to": "mm"},
3716 "name": "SQ_DED_INFO",
3717 "type_ref": "SQ_DED_INFO"
3721 "map": {"at": 36608, "to": "mm"},
3722 "name": "SQ_BUF_RSRC_WORD0",
3723 "type_ref": "SQ_BUF_RSRC_WORD0"
3727 "map": {"at": 36612, "to": "mm"},
3728 "name": "SQ_BUF_RSRC_WORD1",
3729 "type_ref": "SQ_BUF_RSRC_WORD1"
3733 "map": {"at": 36616, "to": "mm"},
3734 "name": "SQ_BUF_RSRC_WORD2",
3735 "type_ref": "SQ_BUF_RSRC_WORD2"
3739 "map": {"at": 36620, "to": "mm"},
3740 "name": "SQ_BUF_RSRC_WORD3",
3741 "type_ref": "SQ_BUF_RSRC_WORD3"
3745 "map": {"at": 36624, "to": "mm"},
3746 "name": "SQ_IMG_RSRC_WORD0",
3747 "type_ref": "SQ_BUF_RSRC_WORD0"
3751 "map": {"at": 36628, "to": "mm"},
3752 "name": "SQ_IMG_RSRC_WORD1",
3753 "type_ref": "SQ_IMG_RSRC_WORD1"
3757 "map": {"at": 36632, "to": "mm"},
3758 "name": "SQ_IMG_RSRC_WORD2",
3759 "type_ref": "SQ_IMG_RSRC_WORD2"
3763 "map": {"at": 36636, "to": "mm"},
3764 "name": "SQ_IMG_RSRC_WORD3",
3765 "type_ref": "SQ_IMG_RSRC_WORD3"
3769 "map": {"at": 36640, "to": "mm"},
3770 "name": "SQ_IMG_RSRC_WORD4",
3771 "type_ref": "SQ_IMG_RSRC_WORD4"
3775 "map": {"at": 36644, "to": "mm"},
3776 "name": "SQ_IMG_RSRC_WORD5",
3777 "type_ref": "SQ_IMG_RSRC_WORD5"
3781 "map": {"at": 36648, "to": "mm"},
3782 "name": "SQ_IMG_RSRC_WORD6",
3783 "type_ref": "SQ_IMG_RSRC_WORD6"
3787 "map": {"at": 36652, "to": "mm"},
3788 "name": "SQ_IMG_RSRC_WORD7",
3789 "type_ref": "SQ_IMG_RSRC_WORD7"
3793 "map": {"at": 36656, "to": "mm"},
3794 "name": "SQ_IMG_SAMP_WORD0",
3795 "type_ref": "SQ_IMG_SAMP_WORD0"
3799 "map": {"at": 36660, "to": "mm"},
3800 "name": "SQ_IMG_SAMP_WORD1",
3801 "type_ref": "SQ_IMG_SAMP_WORD1"
3805 "map": {"at": 36664, "to": "mm"},
3806 "name": "SQ_IMG_SAMP_WORD2",
3807 "type_ref": "SQ_IMG_SAMP_WORD2"
3811 "map": {"at": 36668, "to": "mm"},
3812 "name": "SQ_IMG_SAMP_WORD3",
3813 "type_ref": "SQ_IMG_SAMP_WORD3"
3817 "map": {"at": 37120, "to": "mm"},
3818 "name": "SPI_CONFIG_CNTL",
3819 "type_ref": "SPI_CONFIG_CNTL"
3823 "map": {"at": 38156, "to": "mm"},
3824 "name": "TA_CS_BC_BASE_ADDR",
3825 "type_ref": "TA_BC_BASE_ADDR"
3829 "map": {"at": 39160, "to": "mm"},
3830 "name": "GB_ADDR_CONFIG",
3831 "type_ref": "GB_ADDR_CONFIG"
3835 "map": {"at": 39184, "to": "mm"},
3836 "name": "GB_TILE_MODE0",
3837 "type_ref": "GB_TILE_MODE0"
3841 "map": {"at": 39188, "to": "mm"},
3842 "name": "GB_TILE_MODE1",
3843 "type_ref": "GB_TILE_MODE10"
3847 "map": {"at": 39192, "to": "mm"},
3848 "name": "GB_TILE_MODE2",
3849 "type_ref": "GB_TILE_MODE10"
3853 "map": {"at": 39196, "to": "mm"},
3854 "name": "GB_TILE_MODE3",
3855 "type_ref": "GB_TILE_MODE10"
3859 "map": {"at": 39200, "to": "mm"},
3860 "name": "GB_TILE_MODE4",
3861 "type_ref": "GB_TILE_MODE10"
3865 "map": {"at": 39204, "to": "mm"},
3866 "name": "GB_TILE_MODE5",
3867 "type_ref": "GB_TILE_MODE10"
3871 "map": {"at": 39208, "to": "mm"},
3872 "name": "GB_TILE_MODE6",
3873 "type_ref": "GB_TILE_MODE10"
3877 "map": {"at": 39212, "to": "mm"},
3878 "name": "GB_TILE_MODE7",
3879 "type_ref": "GB_TILE_MODE10"
3883 "map": {"at": 39216, "to": "mm"},
3884 "name": "GB_TILE_MODE8",
3885 "type_ref": "GB_TILE_MODE10"
3889 "map": {"at": 39220, "to": "mm"},
3890 "name": "GB_TILE_MODE9",
3891 "type_ref": "GB_TILE_MODE10"
3895 "map": {"at": 39224, "to": "mm"},
3896 "name": "GB_TILE_MODE10",
3897 "type_ref": "GB_TILE_MODE10"
3901 "map": {"at": 39228, "to": "mm"},
3902 "name": "GB_TILE_MODE11",
3903 "type_ref": "GB_TILE_MODE10"
3907 "map": {"at": 39232, "to": "mm"},
3908 "name": "GB_TILE_MODE12",
3909 "type_ref": "GB_TILE_MODE10"
3913 "map": {"at": 39236, "to": "mm"},
3914 "name": "GB_TILE_MODE13",
3915 "type_ref": "GB_TILE_MODE10"
3919 "map": {"at": 39240, "to": "mm"},
3920 "name": "GB_TILE_MODE14",
3921 "type_ref": "GB_TILE_MODE10"
3925 "map": {"at": 39244, "to": "mm"},
3926 "name": "GB_TILE_MODE15",
3927 "type_ref": "GB_TILE_MODE10"
3931 "map": {"at": 39248, "to": "mm"},
3932 "name": "GB_TILE_MODE16",
3933 "type_ref": "GB_TILE_MODE10"
3937 "map": {"at": 39252, "to": "mm"},
3938 "name": "GB_TILE_MODE17",
3939 "type_ref": "GB_TILE_MODE10"
3943 "map": {"at": 39256, "to": "mm"},
3944 "name": "GB_TILE_MODE18",
3945 "type_ref": "GB_TILE_MODE10"
3949 "map": {"at": 39260, "to": "mm"},
3950 "name": "GB_TILE_MODE19",
3951 "type_ref": "GB_TILE_MODE10"
3955 "map": {"at": 39264, "to": "mm"},
3956 "name": "GB_TILE_MODE20",
3957 "type_ref": "GB_TILE_MODE10"
3961 "map": {"at": 39268, "to": "mm"},
3962 "name": "GB_TILE_MODE21",
3963 "type_ref": "GB_TILE_MODE10"
3967 "map": {"at": 39272, "to": "mm"},
3968 "name": "GB_TILE_MODE22",
3969 "type_ref": "GB_TILE_MODE10"
3973 "map": {"at": 39276, "to": "mm"},
3974 "name": "GB_TILE_MODE23",
3975 "type_ref": "GB_TILE_MODE10"
3979 "map": {"at": 39280, "to": "mm"},
3980 "name": "GB_TILE_MODE24",
3981 "type_ref": "GB_TILE_MODE10"
3985 "map": {"at": 39284, "to": "mm"},
3986 "name": "GB_TILE_MODE25",
3987 "type_ref": "GB_TILE_MODE10"
3991 "map": {"at": 39288, "to": "mm"},
3992 "name": "GB_TILE_MODE26",
3993 "type_ref": "GB_TILE_MODE10"
3997 "map": {"at": 39292, "to": "mm"},
3998 "name": "GB_TILE_MODE27",
3999 "type_ref": "GB_TILE_MODE10"
4003 "map": {"at": 39296, "to": "mm"},
4004 "name": "GB_TILE_MODE28",
4005 "type_ref": "GB_TILE_MODE10"
4009 "map": {"at": 39300, "to": "mm"},
4010 "name": "GB_TILE_MODE29",
4011 "type_ref": "GB_TILE_MODE10"
4015 "map": {"at": 39304, "to": "mm"},
4016 "name": "GB_TILE_MODE30",
4017 "type_ref": "GB_TILE_MODE10"
4021 "map": {"at": 39308, "to": "mm"},
4022 "name": "GB_TILE_MODE31",
4023 "type_ref": "GB_TILE_MODE10"
4027 "map": {"at": 45056, "to": "mm"},
4028 "name": "SPI_SHADER_TBA_LO_PS",
4029 "type_ref": "SPI_SHADER_PGM_LO_ES"
4033 "map": {"at": 45060, "to": "mm"},
4034 "name": "SPI_SHADER_TBA_HI_PS",
4035 "type_ref": "SPI_SHADER_PGM_HI_ES"
4039 "map": {"at": 45064, "to": "mm"},
4040 "name": "SPI_SHADER_TMA_LO_PS",
4041 "type_ref": "SPI_SHADER_PGM_LO_ES"
4045 "map": {"at": 45068, "to": "mm"},
4046 "name": "SPI_SHADER_TMA_HI_PS",
4047 "type_ref": "SPI_SHADER_PGM_HI_ES"
4051 "map": {"at": 45088, "to": "mm"},
4052 "name": "SPI_SHADER_PGM_LO_PS",
4053 "type_ref": "SPI_SHADER_PGM_LO_ES"
4057 "map": {"at": 45092, "to": "mm"},
4058 "name": "SPI_SHADER_PGM_HI_PS",
4059 "type_ref": "SPI_SHADER_PGM_HI_ES"
4063 "map": {"at": 45096, "to": "mm"},
4064 "name": "SPI_SHADER_PGM_RSRC1_PS",
4065 "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
4069 "map": {"at": 45100, "to": "mm"},
4070 "name": "SPI_SHADER_PGM_RSRC2_PS",
4071 "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
4075 "map": {"at": 45104, "to": "mm"},
4076 "name": "SPI_SHADER_USER_DATA_PS_0",
4077 "type_ref": "SQ_WAVE_TTMP0"
4081 "map": {"at": 45108, "to": "mm"},
4082 "name": "SPI_SHADER_USER_DATA_PS_1",
4083 "type_ref": "SQ_WAVE_TTMP0"
4087 "map": {"at": 45112, "to": "mm"},
4088 "name": "SPI_SHADER_USER_DATA_PS_2",
4089 "type_ref": "SQ_WAVE_TTMP0"
4093 "map": {"at": 45116, "to": "mm"},
4094 "name": "SPI_SHADER_USER_DATA_PS_3",
4095 "type_ref": "SQ_WAVE_TTMP0"
4099 "map": {"at": 45120, "to": "mm"},
4100 "name": "SPI_SHADER_USER_DATA_PS_4",
4101 "type_ref": "SQ_WAVE_TTMP0"
4105 "map": {"at": 45124, "to": "mm"},
4106 "name": "SPI_SHADER_USER_DATA_PS_5",
4107 "type_ref": "SQ_WAVE_TTMP0"
4111 "map": {"at": 45128, "to": "mm"},
4112 "name": "SPI_SHADER_USER_DATA_PS_6",
4113 "type_ref": "SQ_WAVE_TTMP0"
4117 "map": {"at": 45132, "to": "mm"},
4118 "name": "SPI_SHADER_USER_DATA_PS_7",
4119 "type_ref": "SQ_WAVE_TTMP0"
4123 "map": {"at": 45136, "to": "mm"},
4124 "name": "SPI_SHADER_USER_DATA_PS_8",
4125 "type_ref": "SQ_WAVE_TTMP0"
4129 "map": {"at": 45140, "to": "mm"},
4130 "name": "SPI_SHADER_USER_DATA_PS_9",
4131 "type_ref": "SQ_WAVE_TTMP0"
4135 "map": {"at": 45144, "to": "mm"},
4136 "name": "SPI_SHADER_USER_DATA_PS_10",
4137 "type_ref": "SQ_WAVE_TTMP0"
4141 "map": {"at": 45148, "to": "mm"},
4142 "name": "SPI_SHADER_USER_DATA_PS_11",
4143 "type_ref": "SQ_WAVE_TTMP0"
4147 "map": {"at": 45152, "to": "mm"},
4148 "name": "SPI_SHADER_USER_DATA_PS_12",
4149 "type_ref": "SQ_WAVE_TTMP0"
4153 "map": {"at": 45156, "to": "mm"},
4154 "name": "SPI_SHADER_USER_DATA_PS_13",
4155 "type_ref": "SQ_WAVE_TTMP0"
4159 "map": {"at": 45160, "to": "mm"},
4160 "name": "SPI_SHADER_USER_DATA_PS_14",
4161 "type_ref": "SQ_WAVE_TTMP0"
4165 "map": {"at": 45164, "to": "mm"},
4166 "name": "SPI_SHADER_USER_DATA_PS_15",
4167 "type_ref": "SQ_WAVE_TTMP0"
4171 "map": {"at": 45312, "to": "mm"},
4172 "name": "SPI_SHADER_TBA_LO_VS",
4173 "type_ref": "SPI_SHADER_PGM_LO_ES"
4177 "map": {"at": 45316, "to": "mm"},
4178 "name": "SPI_SHADER_TBA_HI_VS",
4179 "type_ref": "SPI_SHADER_PGM_HI_ES"
4183 "map": {"at": 45320, "to": "mm"},
4184 "name": "SPI_SHADER_TMA_LO_VS",
4185 "type_ref": "SPI_SHADER_PGM_LO_ES"
4189 "map": {"at": 45324, "to": "mm"},
4190 "name": "SPI_SHADER_TMA_HI_VS",
4191 "type_ref": "SPI_SHADER_PGM_HI_ES"
4195 "map": {"at": 45344, "to": "mm"},
4196 "name": "SPI_SHADER_PGM_LO_VS",
4197 "type_ref": "SPI_SHADER_PGM_LO_ES"
4201 "map": {"at": 45348, "to": "mm"},
4202 "name": "SPI_SHADER_PGM_HI_VS",
4203 "type_ref": "SPI_SHADER_PGM_HI_ES"
4207 "map": {"at": 45352, "to": "mm"},
4208 "name": "SPI_SHADER_PGM_RSRC1_VS",
4209 "type_ref": "SPI_SHADER_PGM_RSRC1_ES"
4213 "map": {"at": 45356, "to": "mm"},
4214 "name": "SPI_SHADER_PGM_RSRC2_VS",
4215 "type_ref": "SPI_SHADER_PGM_RSRC2_VS"
4219 "map": {"at": 45360, "to": "mm"},
4220 "name": "SPI_SHADER_USER_DATA_VS_0",
4221 "type_ref": "SQ_WAVE_TTMP0"
4225 "map": {"at": 45364, "to": "mm"},
4226 "name": "SPI_SHADER_USER_DATA_VS_1",
4227 "type_ref": "SQ_WAVE_TTMP0"
4231 "map": {"at": 45368, "to": "mm"},
4232 "name": "SPI_SHADER_USER_DATA_VS_2",
4233 "type_ref": "SQ_WAVE_TTMP0"
4237 "map": {"at": 45372, "to": "mm"},
4238 "name": "SPI_SHADER_USER_DATA_VS_3",
4239 "type_ref": "SQ_WAVE_TTMP0"
4243 "map": {"at": 45376, "to": "mm"},
4244 "name": "SPI_SHADER_USER_DATA_VS_4",
4245 "type_ref": "SQ_WAVE_TTMP0"
4249 "map": {"at": 45380, "to": "mm"},
4250 "name": "SPI_SHADER_USER_DATA_VS_5",
4251 "type_ref": "SQ_WAVE_TTMP0"
4255 "map": {"at": 45384, "to": "mm"},
4256 "name": "SPI_SHADER_USER_DATA_VS_6",
4257 "type_ref": "SQ_WAVE_TTMP0"
4261 "map": {"at": 45388, "to": "mm"},
4262 "name": "SPI_SHADER_USER_DATA_VS_7",
4263 "type_ref": "SQ_WAVE_TTMP0"
4267 "map": {"at": 45392, "to": "mm"},
4268 "name": "SPI_SHADER_USER_DATA_VS_8",
4269 "type_ref": "SQ_WAVE_TTMP0"
4273 "map": {"at": 45396, "to": "mm"},
4274 "name": "SPI_SHADER_USER_DATA_VS_9",
4275 "type_ref": "SQ_WAVE_TTMP0"
4279 "map": {"at": 45400, "to": "mm"},
4280 "name": "SPI_SHADER_USER_DATA_VS_10",
4281 "type_ref": "SQ_WAVE_TTMP0"
4285 "map": {"at": 45404, "to": "mm"},
4286 "name": "SPI_SHADER_USER_DATA_VS_11",
4287 "type_ref": "SQ_WAVE_TTMP0"
4291 "map": {"at": 45408, "to": "mm"},
4292 "name": "SPI_SHADER_USER_DATA_VS_12",
4293 "type_ref": "SQ_WAVE_TTMP0"
4297 "map": {"at": 45412, "to": "mm"},
4298 "name": "SPI_SHADER_USER_DATA_VS_13",
4299 "type_ref": "SQ_WAVE_TTMP0"
4303 "map": {"at": 45416, "to": "mm"},
4304 "name": "SPI_SHADER_USER_DATA_VS_14",
4305 "type_ref": "SQ_WAVE_TTMP0"
4309 "map": {"at": 45420, "to": "mm"},
4310 "name": "SPI_SHADER_USER_DATA_VS_15",
4311 "type_ref": "SQ_WAVE_TTMP0"
4315 "map": {"at": 45568, "to": "mm"},
4316 "name": "SPI_SHADER_TBA_LO_GS",
4317 "type_ref": "SPI_SHADER_PGM_LO_ES"
4321 "map": {"at": 45572, "to": "mm"},
4322 "name": "SPI_SHADER_TBA_HI_GS",
4323 "type_ref": "SPI_SHADER_PGM_HI_ES"
4327 "map": {"at": 45576, "to": "mm"},
4328 "name": "SPI_SHADER_TMA_LO_GS",
4329 "type_ref": "SPI_SHADER_PGM_LO_ES"
4333 "map": {"at": 45580, "to": "mm"},
4334 "name": "SPI_SHADER_TMA_HI_GS",
4335 "type_ref": "SPI_SHADER_PGM_HI_ES"
4339 "map": {"at": 45600, "to": "mm"},
4340 "name": "SPI_SHADER_PGM_LO_GS",
4341 "type_ref": "SPI_SHADER_PGM_LO_ES"
4345 "map": {"at": 45604, "to": "mm"},
4346 "name": "SPI_SHADER_PGM_HI_GS",
4347 "type_ref": "SPI_SHADER_PGM_HI_ES"
4351 "map": {"at": 45608, "to": "mm"},
4352 "name": "SPI_SHADER_PGM_RSRC1_GS",
4353 "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
4357 "map": {"at": 45612, "to": "mm"},
4358 "name": "SPI_SHADER_PGM_RSRC2_GS",
4359 "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
4363 "map": {"at": 45616, "to": "mm"},
4364 "name": "SPI_SHADER_USER_DATA_GS_0",
4365 "type_ref": "SQ_WAVE_TTMP0"
4369 "map": {"at": 45620, "to": "mm"},
4370 "name": "SPI_SHADER_USER_DATA_GS_1",
4371 "type_ref": "SQ_WAVE_TTMP0"
4375 "map": {"at": 45624, "to": "mm"},
4376 "name": "SPI_SHADER_USER_DATA_GS_2",
4377 "type_ref": "SQ_WAVE_TTMP0"
4381 "map": {"at": 45628, "to": "mm"},
4382 "name": "SPI_SHADER_USER_DATA_GS_3",
4383 "type_ref": "SQ_WAVE_TTMP0"
4387 "map": {"at": 45632, "to": "mm"},
4388 "name": "SPI_SHADER_USER_DATA_GS_4",
4389 "type_ref": "SQ_WAVE_TTMP0"
4393 "map": {"at": 45636, "to": "mm"},
4394 "name": "SPI_SHADER_USER_DATA_GS_5",
4395 "type_ref": "SQ_WAVE_TTMP0"
4399 "map": {"at": 45640, "to": "mm"},
4400 "name": "SPI_SHADER_USER_DATA_GS_6",
4401 "type_ref": "SQ_WAVE_TTMP0"
4405 "map": {"at": 45644, "to": "mm"},
4406 "name": "SPI_SHADER_USER_DATA_GS_7",
4407 "type_ref": "SQ_WAVE_TTMP0"
4411 "map": {"at": 45648, "to": "mm"},
4412 "name": "SPI_SHADER_USER_DATA_GS_8",
4413 "type_ref": "SQ_WAVE_TTMP0"
4417 "map": {"at": 45652, "to": "mm"},
4418 "name": "SPI_SHADER_USER_DATA_GS_9",
4419 "type_ref": "SQ_WAVE_TTMP0"
4423 "map": {"at": 45656, "to": "mm"},
4424 "name": "SPI_SHADER_USER_DATA_GS_10",
4425 "type_ref": "SQ_WAVE_TTMP0"
4429 "map": {"at": 45660, "to": "mm"},
4430 "name": "SPI_SHADER_USER_DATA_GS_11",
4431 "type_ref": "SQ_WAVE_TTMP0"
4435 "map": {"at": 45664, "to": "mm"},
4436 "name": "SPI_SHADER_USER_DATA_GS_12",
4437 "type_ref": "SQ_WAVE_TTMP0"
4441 "map": {"at": 45668, "to": "mm"},
4442 "name": "SPI_SHADER_USER_DATA_GS_13",
4443 "type_ref": "SQ_WAVE_TTMP0"
4447 "map": {"at": 45672, "to": "mm"},
4448 "name": "SPI_SHADER_USER_DATA_GS_14",
4449 "type_ref": "SQ_WAVE_TTMP0"
4453 "map": {"at": 45676, "to": "mm"},
4454 "name": "SPI_SHADER_USER_DATA_GS_15",
4455 "type_ref": "SQ_WAVE_TTMP0"
4459 "map": {"at": 45824, "to": "mm"},
4460 "name": "SPI_SHADER_TBA_LO_ES",
4461 "type_ref": "SPI_SHADER_PGM_LO_ES"
4465 "map": {"at": 45828, "to": "mm"},
4466 "name": "SPI_SHADER_TBA_HI_ES",
4467 "type_ref": "SPI_SHADER_PGM_HI_ES"
4471 "map": {"at": 45832, "to": "mm"},
4472 "name": "SPI_SHADER_TMA_LO_ES",
4473 "type_ref": "SPI_SHADER_PGM_LO_ES"
4477 "map": {"at": 45836, "to": "mm"},
4478 "name": "SPI_SHADER_TMA_HI_ES",
4479 "type_ref": "SPI_SHADER_PGM_HI_ES"
4483 "map": {"at": 45856, "to": "mm"},
4484 "name": "SPI_SHADER_PGM_LO_ES",
4485 "type_ref": "SPI_SHADER_PGM_LO_ES"
4489 "map": {"at": 45860, "to": "mm"},
4490 "name": "SPI_SHADER_PGM_HI_ES",
4491 "type_ref": "SPI_SHADER_PGM_HI_ES"
4495 "map": {"at": 45864, "to": "mm"},
4496 "name": "SPI_SHADER_PGM_RSRC1_ES",
4497 "type_ref": "SPI_SHADER_PGM_RSRC1_ES"
4501 "map": {"at": 45868, "to": "mm"},
4502 "name": "SPI_SHADER_PGM_RSRC2_ES",
4503 "type_ref": "SPI_SHADER_PGM_RSRC2_ES"
4507 "map": {"at": 45872, "to": "mm"},
4508 "name": "SPI_SHADER_USER_DATA_ES_0",
4509 "type_ref": "SQ_WAVE_TTMP0"
4513 "map": {"at": 45876, "to": "mm"},
4514 "name": "SPI_SHADER_USER_DATA_ES_1",
4515 "type_ref": "SQ_WAVE_TTMP0"
4519 "map": {"at": 45880, "to": "mm"},
4520 "name": "SPI_SHADER_USER_DATA_ES_2",
4521 "type_ref": "SQ_WAVE_TTMP0"
4525 "map": {"at": 45884, "to": "mm"},
4526 "name": "SPI_SHADER_USER_DATA_ES_3",
4527 "type_ref": "SQ_WAVE_TTMP0"
4531 "map": {"at": 45888, "to": "mm"},
4532 "name": "SPI_SHADER_USER_DATA_ES_4",
4533 "type_ref": "SQ_WAVE_TTMP0"
4537 "map": {"at": 45892, "to": "mm"},
4538 "name": "SPI_SHADER_USER_DATA_ES_5",
4539 "type_ref": "SQ_WAVE_TTMP0"
4543 "map": {"at": 45896, "to": "mm"},
4544 "name": "SPI_SHADER_USER_DATA_ES_6",
4545 "type_ref": "SQ_WAVE_TTMP0"
4549 "map": {"at": 45900, "to": "mm"},
4550 "name": "SPI_SHADER_USER_DATA_ES_7",
4551 "type_ref": "SQ_WAVE_TTMP0"
4555 "map": {"at": 45904, "to": "mm"},
4556 "name": "SPI_SHADER_USER_DATA_ES_8",
4557 "type_ref": "SQ_WAVE_TTMP0"
4561 "map": {"at": 45908, "to": "mm"},
4562 "name": "SPI_SHADER_USER_DATA_ES_9",
4563 "type_ref": "SQ_WAVE_TTMP0"
4567 "map": {"at": 45912, "to": "mm"},
4568 "name": "SPI_SHADER_USER_DATA_ES_10",
4569 "type_ref": "SQ_WAVE_TTMP0"
4573 "map": {"at": 45916, "to": "mm"},
4574 "name": "SPI_SHADER_USER_DATA_ES_11",
4575 "type_ref": "SQ_WAVE_TTMP0"
4579 "map": {"at": 45920, "to": "mm"},
4580 "name": "SPI_SHADER_USER_DATA_ES_12",
4581 "type_ref": "SQ_WAVE_TTMP0"
4585 "map": {"at": 45924, "to": "mm"},
4586 "name": "SPI_SHADER_USER_DATA_ES_13",
4587 "type_ref": "SQ_WAVE_TTMP0"
4591 "map": {"at": 45928, "to": "mm"},
4592 "name": "SPI_SHADER_USER_DATA_ES_14",
4593 "type_ref": "SQ_WAVE_TTMP0"
4597 "map": {"at": 45932, "to": "mm"},
4598 "name": "SPI_SHADER_USER_DATA_ES_15",
4599 "type_ref": "SQ_WAVE_TTMP0"
4603 "map": {"at": 46080, "to": "mm"},
4604 "name": "SPI_SHADER_TBA_LO_HS",
4605 "type_ref": "SPI_SHADER_PGM_LO_ES"
4609 "map": {"at": 46084, "to": "mm"},
4610 "name": "SPI_SHADER_TBA_HI_HS",
4611 "type_ref": "SPI_SHADER_PGM_HI_ES"
4615 "map": {"at": 46088, "to": "mm"},
4616 "name": "SPI_SHADER_TMA_LO_HS",
4617 "type_ref": "SPI_SHADER_PGM_LO_ES"
4621 "map": {"at": 46092, "to": "mm"},
4622 "name": "SPI_SHADER_TMA_HI_HS",
4623 "type_ref": "SPI_SHADER_PGM_HI_ES"
4627 "map": {"at": 46112, "to": "mm"},
4628 "name": "SPI_SHADER_PGM_LO_HS",
4629 "type_ref": "SPI_SHADER_PGM_LO_ES"
4633 "map": {"at": 46116, "to": "mm"},
4634 "name": "SPI_SHADER_PGM_HI_HS",
4635 "type_ref": "SPI_SHADER_PGM_HI_ES"
4639 "map": {"at": 46120, "to": "mm"},
4640 "name": "SPI_SHADER_PGM_RSRC1_HS",
4641 "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
4645 "map": {"at": 46124, "to": "mm"},
4646 "name": "SPI_SHADER_PGM_RSRC2_HS",
4647 "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
4651 "map": {"at": 46128, "to": "mm"},
4652 "name": "SPI_SHADER_USER_DATA_HS_0",
4653 "type_ref": "SQ_WAVE_TTMP0"
4657 "map": {"at": 46132, "to": "mm"},
4658 "name": "SPI_SHADER_USER_DATA_HS_1",
4659 "type_ref": "SQ_WAVE_TTMP0"
4663 "map": {"at": 46136, "to": "mm"},
4664 "name": "SPI_SHADER_USER_DATA_HS_2",
4665 "type_ref": "SQ_WAVE_TTMP0"
4669 "map": {"at": 46140, "to": "mm"},
4670 "name": "SPI_SHADER_USER_DATA_HS_3",
4671 "type_ref": "SQ_WAVE_TTMP0"
4675 "map": {"at": 46144, "to": "mm"},
4676 "name": "SPI_SHADER_USER_DATA_HS_4",
4677 "type_ref": "SQ_WAVE_TTMP0"
4681 "map": {"at": 46148, "to": "mm"},
4682 "name": "SPI_SHADER_USER_DATA_HS_5",
4683 "type_ref": "SQ_WAVE_TTMP0"
4687 "map": {"at": 46152, "to": "mm"},
4688 "name": "SPI_SHADER_USER_DATA_HS_6",
4689 "type_ref": "SQ_WAVE_TTMP0"
4693 "map": {"at": 46156, "to": "mm"},
4694 "name": "SPI_SHADER_USER_DATA_HS_7",
4695 "type_ref": "SQ_WAVE_TTMP0"
4699 "map": {"at": 46160, "to": "mm"},
4700 "name": "SPI_SHADER_USER_DATA_HS_8",
4701 "type_ref": "SQ_WAVE_TTMP0"
4705 "map": {"at": 46164, "to": "mm"},
4706 "name": "SPI_SHADER_USER_DATA_HS_9",
4707 "type_ref": "SQ_WAVE_TTMP0"
4711 "map": {"at": 46168, "to": "mm"},
4712 "name": "SPI_SHADER_USER_DATA_HS_10",
4713 "type_ref": "SQ_WAVE_TTMP0"
4717 "map": {"at": 46172, "to": "mm"},
4718 "name": "SPI_SHADER_USER_DATA_HS_11",
4719 "type_ref": "SQ_WAVE_TTMP0"
4723 "map": {"at": 46176, "to": "mm"},
4724 "name": "SPI_SHADER_USER_DATA_HS_12",
4725 "type_ref": "SQ_WAVE_TTMP0"
4729 "map": {"at": 46180, "to": "mm"},
4730 "name": "SPI_SHADER_USER_DATA_HS_13",
4731 "type_ref": "SQ_WAVE_TTMP0"
4735 "map": {"at": 46184, "to": "mm"},
4736 "name": "SPI_SHADER_USER_DATA_HS_14",
4737 "type_ref": "SQ_WAVE_TTMP0"
4741 "map": {"at": 46188, "to": "mm"},
4742 "name": "SPI_SHADER_USER_DATA_HS_15",
4743 "type_ref": "SQ_WAVE_TTMP0"
4747 "map": {"at": 46336, "to": "mm"},
4748 "name": "SPI_SHADER_TBA_LO_LS",
4749 "type_ref": "SPI_SHADER_PGM_LO_ES"
4753 "map": {"at": 46340, "to": "mm"},
4754 "name": "SPI_SHADER_TBA_HI_LS",
4755 "type_ref": "SPI_SHADER_PGM_HI_ES"
4759 "map": {"at": 46344, "to": "mm"},
4760 "name": "SPI_SHADER_TMA_LO_LS",
4761 "type_ref": "SPI_SHADER_PGM_LO_ES"
4765 "map": {"at": 46348, "to": "mm"},
4766 "name": "SPI_SHADER_TMA_HI_LS",
4767 "type_ref": "SPI_SHADER_PGM_HI_ES"
4771 "map": {"at": 46368, "to": "mm"},
4772 "name": "SPI_SHADER_PGM_LO_LS",
4773 "type_ref": "SPI_SHADER_PGM_LO_ES"
4777 "map": {"at": 46372, "to": "mm"},
4778 "name": "SPI_SHADER_PGM_HI_LS",
4779 "type_ref": "SPI_SHADER_PGM_HI_ES"
4783 "map": {"at": 46376, "to": "mm"},
4784 "name": "SPI_SHADER_PGM_RSRC1_LS",
4785 "type_ref": "SPI_SHADER_PGM_RSRC1_LS"
4789 "map": {"at": 46380, "to": "mm"},
4790 "name": "SPI_SHADER_PGM_RSRC2_LS",
4791 "type_ref": "SPI_SHADER_PGM_RSRC2_LS"
4795 "map": {"at": 46384, "to": "mm"},
4796 "name": "SPI_SHADER_USER_DATA_LS_0",
4797 "type_ref": "SQ_WAVE_TTMP0"
4801 "map": {"at": 46388, "to": "mm"},
4802 "name": "SPI_SHADER_USER_DATA_LS_1",
4803 "type_ref": "SQ_WAVE_TTMP0"
4807 "map": {"at": 46392, "to": "mm"},
4808 "name": "SPI_SHADER_USER_DATA_LS_2",
4809 "type_ref": "SQ_WAVE_TTMP0"
4813 "map": {"at": 46396, "to": "mm"},
4814 "name": "SPI_SHADER_USER_DATA_LS_3",
4815 "type_ref": "SQ_WAVE_TTMP0"
4819 "map": {"at": 46400, "to": "mm"},
4820 "name": "SPI_SHADER_USER_DATA_LS_4",
4821 "type_ref": "SQ_WAVE_TTMP0"
4825 "map": {"at": 46404, "to": "mm"},
4826 "name": "SPI_SHADER_USER_DATA_LS_5",
4827 "type_ref": "SQ_WAVE_TTMP0"
4831 "map": {"at": 46408, "to": "mm"},
4832 "name": "SPI_SHADER_USER_DATA_LS_6",
4833 "type_ref": "SQ_WAVE_TTMP0"
4837 "map": {"at": 46412, "to": "mm"},
4838 "name": "SPI_SHADER_USER_DATA_LS_7",
4839 "type_ref": "SQ_WAVE_TTMP0"
4843 "map": {"at": 46416, "to": "mm"},
4844 "name": "SPI_SHADER_USER_DATA_LS_8",
4845 "type_ref": "SQ_WAVE_TTMP0"
4849 "map": {"at": 46420, "to": "mm"},
4850 "name": "SPI_SHADER_USER_DATA_LS_9",
4851 "type_ref": "SQ_WAVE_TTMP0"
4855 "map": {"at": 46424, "to": "mm"},
4856 "name": "SPI_SHADER_USER_DATA_LS_10",
4857 "type_ref": "SQ_WAVE_TTMP0"
4861 "map": {"at": 46428, "to": "mm"},
4862 "name": "SPI_SHADER_USER_DATA_LS_11",
4863 "type_ref": "SQ_WAVE_TTMP0"
4867 "map": {"at": 46432, "to": "mm"},
4868 "name": "SPI_SHADER_USER_DATA_LS_12",
4869 "type_ref": "SQ_WAVE_TTMP0"
4873 "map": {"at": 46436, "to": "mm"},
4874 "name": "SPI_SHADER_USER_DATA_LS_13",
4875 "type_ref": "SQ_WAVE_TTMP0"
4879 "map": {"at": 46440, "to": "mm"},
4880 "name": "SPI_SHADER_USER_DATA_LS_14",
4881 "type_ref": "SQ_WAVE_TTMP0"
4885 "map": {"at": 46444, "to": "mm"},
4886 "name": "SPI_SHADER_USER_DATA_LS_15",
4887 "type_ref": "SQ_WAVE_TTMP0"
4891 "map": {"at": 47104, "to": "mm"},
4892 "name": "COMPUTE_DISPATCH_INITIATOR",
4893 "type_ref": "COMPUTE_DISPATCH_INITIATOR"
4897 "map": {"at": 47108, "to": "mm"},
4898 "name": "COMPUTE_DIM_X",
4899 "type_ref": "COMPUTE_DIM_X"
4903 "map": {"at": 47112, "to": "mm"},
4904 "name": "COMPUTE_DIM_Y",
4905 "type_ref": "COMPUTE_DIM_X"
4909 "map": {"at": 47116, "to": "mm"},
4910 "name": "COMPUTE_DIM_Z",
4911 "type_ref": "COMPUTE_DIM_X"
4915 "map": {"at": 47120, "to": "mm"},
4916 "name": "COMPUTE_START_X",
4917 "type_ref": "COMPUTE_START_X"
4921 "map": {"at": 47124, "to": "mm"},
4922 "name": "COMPUTE_START_Y",
4923 "type_ref": "COMPUTE_START_X"
4927 "map": {"at": 47128, "to": "mm"},
4928 "name": "COMPUTE_START_Z",
4929 "type_ref": "COMPUTE_START_X"
4933 "map": {"at": 47132, "to": "mm"},
4934 "name": "COMPUTE_NUM_THREAD_X",
4935 "type_ref": "COMPUTE_NUM_THREAD_X"
4939 "map": {"at": 47136, "to": "mm"},
4940 "name": "COMPUTE_NUM_THREAD_Y",
4941 "type_ref": "COMPUTE_NUM_THREAD_X"
4945 "map": {"at": 47140, "to": "mm"},
4946 "name": "COMPUTE_NUM_THREAD_Z",
4947 "type_ref": "COMPUTE_NUM_THREAD_X"
4951 "map": {"at": 47152, "to": "mm"},
4952 "name": "COMPUTE_PGM_LO",
4953 "type_ref": "SQ_WAVE_TTMP0"
4957 "map": {"at": 47156, "to": "mm"},
4958 "name": "COMPUTE_PGM_HI",
4959 "type_ref": "COMPUTE_PGM_HI"
4963 "map": {"at": 47160, "to": "mm"},
4964 "name": "COMPUTE_TBA_LO",
4965 "type_ref": "SQ_WAVE_TTMP0"
4969 "map": {"at": 47164, "to": "mm"},
4970 "name": "COMPUTE_TBA_HI",
4971 "type_ref": "COMPUTE_TBA_HI"
4975 "map": {"at": 47168, "to": "mm"},
4976 "name": "COMPUTE_TMA_LO",
4977 "type_ref": "SQ_WAVE_TTMP0"
4981 "map": {"at": 47172, "to": "mm"},
4982 "name": "COMPUTE_TMA_HI",
4983 "type_ref": "COMPUTE_TBA_HI"
4987 "map": {"at": 47176, "to": "mm"},
4988 "name": "COMPUTE_PGM_RSRC1",
4989 "type_ref": "COMPUTE_PGM_RSRC1"
4993 "map": {"at": 47180, "to": "mm"},
4994 "name": "COMPUTE_PGM_RSRC2",
4995 "type_ref": "COMPUTE_PGM_RSRC2"
4999 "map": {"at": 47184, "to": "mm"},
5000 "name": "COMPUTE_VMID",
5001 "type_ref": "COMPUTE_VMID"
5005 "map": {"at": 47188, "to": "mm"},
5006 "name": "COMPUTE_RESOURCE_LIMITS",
5007 "type_ref": "COMPUTE_RESOURCE_LIMITS"
5011 "map": {"at": 47192, "to": "mm"},
5012 "name": "COMPUTE_STATIC_THREAD_MGMT_SE0",
5013 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
5017 "map": {"at": 47196, "to": "mm"},
5018 "name": "COMPUTE_STATIC_THREAD_MGMT_SE1",
5019 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0"
5023 "map": {"at": 47200, "to": "mm"},
5024 "name": "COMPUTE_TMPRING_SIZE",
5025 "type_ref": "COMPUTE_TMPRING_SIZE"
5029 "map": {"at": 47360, "to": "mm"},
5030 "name": "COMPUTE_USER_DATA_0",
5031 "type_ref": "SQ_WAVE_TTMP0"
5035 "map": {"at": 47364, "to": "mm"},
5036 "name": "COMPUTE_USER_DATA_1",
5037 "type_ref": "SQ_WAVE_TTMP0"
5041 "map": {"at": 47368, "to": "mm"},
5042 "name": "COMPUTE_USER_DATA_2",
5043 "type_ref": "SQ_WAVE_TTMP0"
5047 "map": {"at": 47372, "to": "mm"},
5048 "name": "COMPUTE_USER_DATA_3",
5049 "type_ref": "SQ_WAVE_TTMP0"
5053 "map": {"at": 47376, "to": "mm"},
5054 "name": "COMPUTE_USER_DATA_4",
5055 "type_ref": "SQ_WAVE_TTMP0"
5059 "map": {"at": 47380, "to": "mm"},
5060 "name": "COMPUTE_USER_DATA_5",
5061 "type_ref": "SQ_WAVE_TTMP0"
5065 "map": {"at": 47384, "to": "mm"},
5066 "name": "COMPUTE_USER_DATA_6",
5067 "type_ref": "SQ_WAVE_TTMP0"
5071 "map": {"at": 47388, "to": "mm"},
5072 "name": "COMPUTE_USER_DATA_7",
5073 "type_ref": "SQ_WAVE_TTMP0"
5077 "map": {"at": 47392, "to": "mm"},
5078 "name": "COMPUTE_USER_DATA_8",
5079 "type_ref": "SQ_WAVE_TTMP0"
5083 "map": {"at": 47396, "to": "mm"},
5084 "name": "COMPUTE_USER_DATA_9",
5085 "type_ref": "SQ_WAVE_TTMP0"
5089 "map": {"at": 47400, "to": "mm"},
5090 "name": "COMPUTE_USER_DATA_10",
5091 "type_ref": "SQ_WAVE_TTMP0"
5095 "map": {"at": 47404, "to": "mm"},
5096 "name": "COMPUTE_USER_DATA_11",
5097 "type_ref": "SQ_WAVE_TTMP0"
5101 "map": {"at": 47408, "to": "mm"},
5102 "name": "COMPUTE_USER_DATA_12",
5103 "type_ref": "SQ_WAVE_TTMP0"
5107 "map": {"at": 47412, "to": "mm"},
5108 "name": "COMPUTE_USER_DATA_13",
5109 "type_ref": "SQ_WAVE_TTMP0"
5113 "map": {"at": 47416, "to": "mm"},
5114 "name": "COMPUTE_USER_DATA_14",
5115 "type_ref": "SQ_WAVE_TTMP0"
5119 "map": {"at": 47420, "to": "mm"},
5120 "name": "COMPUTE_USER_DATA_15",
5121 "type_ref": "SQ_WAVE_TTMP0"
5125 "map": {"at": 163840, "to": "mm"},
5126 "name": "DB_RENDER_CONTROL",
5127 "type_ref": "DB_RENDER_CONTROL"
5131 "map": {"at": 163844, "to": "mm"},
5132 "name": "DB_COUNT_CONTROL",
5133 "type_ref": "DB_COUNT_CONTROL"
5137 "map": {"at": 163848, "to": "mm"},
5138 "name": "DB_DEPTH_VIEW",
5139 "type_ref": "DB_DEPTH_VIEW"
5143 "map": {"at": 163852, "to": "mm"},
5144 "name": "DB_RENDER_OVERRIDE",
5145 "type_ref": "DB_RENDER_OVERRIDE"
5149 "map": {"at": 163856, "to": "mm"},
5150 "name": "DB_RENDER_OVERRIDE2",
5151 "type_ref": "DB_RENDER_OVERRIDE2"
5155 "map": {"at": 163860, "to": "mm"},
5156 "name": "DB_HTILE_DATA_BASE",
5157 "type_ref": "CB_COLOR0_BASE"
5161 "map": {"at": 163872, "to": "mm"},
5162 "name": "DB_DEPTH_BOUNDS_MIN",
5163 "type_ref": "DB_DEPTH_BOUNDS_MIN"
5167 "map": {"at": 163876, "to": "mm"},
5168 "name": "DB_DEPTH_BOUNDS_MAX",
5169 "type_ref": "DB_DEPTH_BOUNDS_MAX"
5173 "map": {"at": 163880, "to": "mm"},
5174 "name": "DB_STENCIL_CLEAR",
5175 "type_ref": "DB_STENCIL_CLEAR"
5179 "map": {"at": 163884, "to": "mm"},
5180 "name": "DB_DEPTH_CLEAR",
5181 "type_ref": "DB_DEPTH_CLEAR"
5185 "map": {"at": 163888, "to": "mm"},
5186 "name": "PA_SC_SCREEN_SCISSOR_TL",
5187 "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
5191 "map": {"at": 163892, "to": "mm"},
5192 "name": "PA_SC_SCREEN_SCISSOR_BR",
5193 "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
5197 "map": {"at": 163900, "to": "mm"},
5198 "name": "DB_DEPTH_INFO",
5199 "type_ref": "DB_DEPTH_INFO"
5203 "map": {"at": 163904, "to": "mm"},
5204 "name": "DB_Z_INFO",
5205 "type_ref": "DB_Z_INFO"
5209 "map": {"at": 163908, "to": "mm"},
5210 "name": "DB_STENCIL_INFO",
5211 "type_ref": "DB_STENCIL_INFO"
5215 "map": {"at": 163912, "to": "mm"},
5216 "name": "DB_Z_READ_BASE",
5217 "type_ref": "CB_COLOR0_BASE"
5221 "map": {"at": 163916, "to": "mm"},
5222 "name": "DB_STENCIL_READ_BASE",
5223 "type_ref": "CB_COLOR0_BASE"
5227 "map": {"at": 163920, "to": "mm"},
5228 "name": "DB_Z_WRITE_BASE",
5229 "type_ref": "CB_COLOR0_BASE"
5233 "map": {"at": 163924, "to": "mm"},
5234 "name": "DB_STENCIL_WRITE_BASE",
5235 "type_ref": "CB_COLOR0_BASE"
5239 "map": {"at": 163928, "to": "mm"},
5240 "name": "DB_DEPTH_SIZE",
5241 "type_ref": "DB_DEPTH_SIZE"
5245 "map": {"at": 163932, "to": "mm"},
5246 "name": "DB_DEPTH_SLICE",
5247 "type_ref": "DB_DEPTH_SLICE"
5251 "map": {"at": 163968, "to": "mm"},
5252 "name": "TA_BC_BASE_ADDR",
5253 "type_ref": "TA_BC_BASE_ADDR"
5257 "map": {"at": 164344, "to": "mm"},
5258 "name": "COHER_DEST_BASE_2",
5259 "type_ref": "COHER_DEST_BASE_0"
5263 "map": {"at": 164348, "to": "mm"},
5264 "name": "COHER_DEST_BASE_3",
5265 "type_ref": "COHER_DEST_BASE_0"
5269 "map": {"at": 164352, "to": "mm"},
5270 "name": "PA_SC_WINDOW_OFFSET",
5271 "type_ref": "PA_SC_WINDOW_OFFSET"
5275 "map": {"at": 164356, "to": "mm"},
5276 "name": "PA_SC_WINDOW_SCISSOR_TL",
5277 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5281 "map": {"at": 164360, "to": "mm"},
5282 "name": "PA_SC_WINDOW_SCISSOR_BR",
5283 "type_ref": "PA_SC_CLIPRECT_0_BR"
5287 "map": {"at": 164364, "to": "mm"},
5288 "name": "PA_SC_CLIPRECT_RULE",
5289 "type_ref": "PA_SC_CLIPRECT_RULE"
5293 "map": {"at": 164368, "to": "mm"},
5294 "name": "PA_SC_CLIPRECT_0_TL",
5295 "type_ref": "PA_SC_CLIPRECT_0_TL"
5299 "map": {"at": 164372, "to": "mm"},
5300 "name": "PA_SC_CLIPRECT_0_BR",
5301 "type_ref": "PA_SC_CLIPRECT_0_BR"
5305 "map": {"at": 164376, "to": "mm"},
5306 "name": "PA_SC_CLIPRECT_1_TL",
5307 "type_ref": "PA_SC_CLIPRECT_0_TL"
5311 "map": {"at": 164380, "to": "mm"},
5312 "name": "PA_SC_CLIPRECT_1_BR",
5313 "type_ref": "PA_SC_CLIPRECT_0_BR"
5317 "map": {"at": 164384, "to": "mm"},
5318 "name": "PA_SC_CLIPRECT_2_TL",
5319 "type_ref": "PA_SC_CLIPRECT_0_TL"
5323 "map": {"at": 164388, "to": "mm"},
5324 "name": "PA_SC_CLIPRECT_2_BR",
5325 "type_ref": "PA_SC_CLIPRECT_0_BR"
5329 "map": {"at": 164392, "to": "mm"},
5330 "name": "PA_SC_CLIPRECT_3_TL",
5331 "type_ref": "PA_SC_CLIPRECT_0_TL"
5335 "map": {"at": 164396, "to": "mm"},
5336 "name": "PA_SC_CLIPRECT_3_BR",
5337 "type_ref": "PA_SC_CLIPRECT_0_BR"
5341 "map": {"at": 164400, "to": "mm"},
5342 "name": "PA_SC_EDGERULE",
5343 "type_ref": "PA_SC_EDGERULE"
5347 "map": {"at": 164404, "to": "mm"},
5348 "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
5349 "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
5353 "map": {"at": 164408, "to": "mm"},
5354 "name": "CB_TARGET_MASK",
5355 "type_ref": "CB_TARGET_MASK"
5359 "map": {"at": 164412, "to": "mm"},
5360 "name": "CB_SHADER_MASK",
5361 "type_ref": "CB_SHADER_MASK"
5365 "map": {"at": 164416, "to": "mm"},
5366 "name": "PA_SC_GENERIC_SCISSOR_TL",
5367 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5371 "map": {"at": 164420, "to": "mm"},
5372 "name": "PA_SC_GENERIC_SCISSOR_BR",
5373 "type_ref": "PA_SC_CLIPRECT_0_BR"
5377 "map": {"at": 164424, "to": "mm"},
5378 "name": "COHER_DEST_BASE_0",
5379 "type_ref": "COHER_DEST_BASE_0"
5383 "map": {"at": 164428, "to": "mm"},
5384 "name": "COHER_DEST_BASE_1",
5385 "type_ref": "COHER_DEST_BASE_0"
5389 "map": {"at": 164432, "to": "mm"},
5390 "name": "PA_SC_VPORT_SCISSOR_0_TL",
5391 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5395 "map": {"at": 164436, "to": "mm"},
5396 "name": "PA_SC_VPORT_SCISSOR_0_BR",
5397 "type_ref": "PA_SC_CLIPRECT_0_BR"
5401 "map": {"at": 164440, "to": "mm"},
5402 "name": "PA_SC_VPORT_SCISSOR_1_TL",
5403 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5407 "map": {"at": 164444, "to": "mm"},
5408 "name": "PA_SC_VPORT_SCISSOR_1_BR",
5409 "type_ref": "PA_SC_CLIPRECT_0_BR"
5413 "map": {"at": 164448, "to": "mm"},
5414 "name": "PA_SC_VPORT_SCISSOR_2_TL",
5415 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5419 "map": {"at": 164452, "to": "mm"},
5420 "name": "PA_SC_VPORT_SCISSOR_2_BR",
5421 "type_ref": "PA_SC_CLIPRECT_0_BR"
5425 "map": {"at": 164456, "to": "mm"},
5426 "name": "PA_SC_VPORT_SCISSOR_3_TL",
5427 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5431 "map": {"at": 164460, "to": "mm"},
5432 "name": "PA_SC_VPORT_SCISSOR_3_BR",
5433 "type_ref": "PA_SC_CLIPRECT_0_BR"
5437 "map": {"at": 164464, "to": "mm"},
5438 "name": "PA_SC_VPORT_SCISSOR_4_TL",
5439 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5443 "map": {"at": 164468, "to": "mm"},
5444 "name": "PA_SC_VPORT_SCISSOR_4_BR",
5445 "type_ref": "PA_SC_CLIPRECT_0_BR"
5449 "map": {"at": 164472, "to": "mm"},
5450 "name": "PA_SC_VPORT_SCISSOR_5_TL",
5451 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5455 "map": {"at": 164476, "to": "mm"},
5456 "name": "PA_SC_VPORT_SCISSOR_5_BR",
5457 "type_ref": "PA_SC_CLIPRECT_0_BR"
5461 "map": {"at": 164480, "to": "mm"},
5462 "name": "PA_SC_VPORT_SCISSOR_6_TL",
5463 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5467 "map": {"at": 164484, "to": "mm"},
5468 "name": "PA_SC_VPORT_SCISSOR_6_BR",
5469 "type_ref": "PA_SC_CLIPRECT_0_BR"
5473 "map": {"at": 164488, "to": "mm"},
5474 "name": "PA_SC_VPORT_SCISSOR_7_TL",
5475 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5479 "map": {"at": 164492, "to": "mm"},
5480 "name": "PA_SC_VPORT_SCISSOR_7_BR",
5481 "type_ref": "PA_SC_CLIPRECT_0_BR"
5485 "map": {"at": 164496, "to": "mm"},
5486 "name": "PA_SC_VPORT_SCISSOR_8_TL",
5487 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5491 "map": {"at": 164500, "to": "mm"},
5492 "name": "PA_SC_VPORT_SCISSOR_8_BR",
5493 "type_ref": "PA_SC_CLIPRECT_0_BR"
5497 "map": {"at": 164504, "to": "mm"},
5498 "name": "PA_SC_VPORT_SCISSOR_9_TL",
5499 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5503 "map": {"at": 164508, "to": "mm"},
5504 "name": "PA_SC_VPORT_SCISSOR_9_BR",
5505 "type_ref": "PA_SC_CLIPRECT_0_BR"
5509 "map": {"at": 164512, "to": "mm"},
5510 "name": "PA_SC_VPORT_SCISSOR_10_TL",
5511 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5515 "map": {"at": 164516, "to": "mm"},
5516 "name": "PA_SC_VPORT_SCISSOR_10_BR",
5517 "type_ref": "PA_SC_CLIPRECT_0_BR"
5521 "map": {"at": 164520, "to": "mm"},
5522 "name": "PA_SC_VPORT_SCISSOR_11_TL",
5523 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5527 "map": {"at": 164524, "to": "mm"},
5528 "name": "PA_SC_VPORT_SCISSOR_11_BR",
5529 "type_ref": "PA_SC_CLIPRECT_0_BR"
5533 "map": {"at": 164528, "to": "mm"},
5534 "name": "PA_SC_VPORT_SCISSOR_12_TL",
5535 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5539 "map": {"at": 164532, "to": "mm"},
5540 "name": "PA_SC_VPORT_SCISSOR_12_BR",
5541 "type_ref": "PA_SC_CLIPRECT_0_BR"
5545 "map": {"at": 164536, "to": "mm"},
5546 "name": "PA_SC_VPORT_SCISSOR_13_TL",
5547 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5551 "map": {"at": 164540, "to": "mm"},
5552 "name": "PA_SC_VPORT_SCISSOR_13_BR",
5553 "type_ref": "PA_SC_CLIPRECT_0_BR"
5557 "map": {"at": 164544, "to": "mm"},
5558 "name": "PA_SC_VPORT_SCISSOR_14_TL",
5559 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5563 "map": {"at": 164548, "to": "mm"},
5564 "name": "PA_SC_VPORT_SCISSOR_14_BR",
5565 "type_ref": "PA_SC_CLIPRECT_0_BR"
5569 "map": {"at": 164552, "to": "mm"},
5570 "name": "PA_SC_VPORT_SCISSOR_15_TL",
5571 "type_ref": "PA_SC_GENERIC_SCISSOR_TL"
5575 "map": {"at": 164556, "to": "mm"},
5576 "name": "PA_SC_VPORT_SCISSOR_15_BR",
5577 "type_ref": "PA_SC_CLIPRECT_0_BR"
5581 "map": {"at": 164560, "to": "mm"},
5582 "name": "PA_SC_VPORT_ZMIN_0",
5583 "type_ref": "PA_SC_VPORT_ZMIN_0"
5587 "map": {"at": 164564, "to": "mm"},
5588 "name": "PA_SC_VPORT_ZMAX_0",
5589 "type_ref": "PA_SC_VPORT_ZMAX_0"
5593 "map": {"at": 164568, "to": "mm"},
5594 "name": "PA_SC_VPORT_ZMIN_1",
5595 "type_ref": "PA_SC_VPORT_ZMIN_0"
5599 "map": {"at": 164572, "to": "mm"},
5600 "name": "PA_SC_VPORT_ZMAX_1",
5601 "type_ref": "PA_SC_VPORT_ZMAX_0"
5605 "map": {"at": 164576, "to": "mm"},
5606 "name": "PA_SC_VPORT_ZMIN_2",
5607 "type_ref": "PA_SC_VPORT_ZMIN_0"
5611 "map": {"at": 164580, "to": "mm"},
5612 "name": "PA_SC_VPORT_ZMAX_2",
5613 "type_ref": "PA_SC_VPORT_ZMAX_0"
5617 "map": {"at": 164584, "to": "mm"},
5618 "name": "PA_SC_VPORT_ZMIN_3",
5619 "type_ref": "PA_SC_VPORT_ZMIN_0"
5623 "map": {"at": 164588, "to": "mm"},
5624 "name": "PA_SC_VPORT_ZMAX_3",
5625 "type_ref": "PA_SC_VPORT_ZMAX_0"
5629 "map": {"at": 164592, "to": "mm"},
5630 "name": "PA_SC_VPORT_ZMIN_4",
5631 "type_ref": "PA_SC_VPORT_ZMIN_0"
5635 "map": {"at": 164596, "to": "mm"},
5636 "name": "PA_SC_VPORT_ZMAX_4",
5637 "type_ref": "PA_SC_VPORT_ZMAX_0"
5641 "map": {"at": 164600, "to": "mm"},
5642 "name": "PA_SC_VPORT_ZMIN_5",
5643 "type_ref": "PA_SC_VPORT_ZMIN_0"
5647 "map": {"at": 164604, "to": "mm"},
5648 "name": "PA_SC_VPORT_ZMAX_5",
5649 "type_ref": "PA_SC_VPORT_ZMAX_0"
5653 "map": {"at": 164608, "to": "mm"},
5654 "name": "PA_SC_VPORT_ZMIN_6",
5655 "type_ref": "PA_SC_VPORT_ZMIN_0"
5659 "map": {"at": 164612, "to": "mm"},
5660 "name": "PA_SC_VPORT_ZMAX_6",
5661 "type_ref": "PA_SC_VPORT_ZMAX_0"
5665 "map": {"at": 164616, "to": "mm"},
5666 "name": "PA_SC_VPORT_ZMIN_7",
5667 "type_ref": "PA_SC_VPORT_ZMIN_0"
5671 "map": {"at": 164620, "to": "mm"},
5672 "name": "PA_SC_VPORT_ZMAX_7",
5673 "type_ref": "PA_SC_VPORT_ZMAX_0"
5677 "map": {"at": 164624, "to": "mm"},
5678 "name": "PA_SC_VPORT_ZMIN_8",
5679 "type_ref": "PA_SC_VPORT_ZMIN_0"
5683 "map": {"at": 164628, "to": "mm"},
5684 "name": "PA_SC_VPORT_ZMAX_8",
5685 "type_ref": "PA_SC_VPORT_ZMAX_0"
5689 "map": {"at": 164632, "to": "mm"},
5690 "name": "PA_SC_VPORT_ZMIN_9",
5691 "type_ref": "PA_SC_VPORT_ZMIN_0"
5695 "map": {"at": 164636, "to": "mm"},
5696 "name": "PA_SC_VPORT_ZMAX_9",
5697 "type_ref": "PA_SC_VPORT_ZMAX_0"
5701 "map": {"at": 164640, "to": "mm"},
5702 "name": "PA_SC_VPORT_ZMIN_10",
5703 "type_ref": "PA_SC_VPORT_ZMIN_0"
5707 "map": {"at": 164644, "to": "mm"},
5708 "name": "PA_SC_VPORT_ZMAX_10",
5709 "type_ref": "PA_SC_VPORT_ZMAX_0"
5713 "map": {"at": 164648, "to": "mm"},
5714 "name": "PA_SC_VPORT_ZMIN_11",
5715 "type_ref": "PA_SC_VPORT_ZMIN_0"
5719 "map": {"at": 164652, "to": "mm"},
5720 "name": "PA_SC_VPORT_ZMAX_11",
5721 "type_ref": "PA_SC_VPORT_ZMAX_0"
5725 "map": {"at": 164656, "to": "mm"},
5726 "name": "PA_SC_VPORT_ZMIN_12",
5727 "type_ref": "PA_SC_VPORT_ZMIN_0"
5731 "map": {"at": 164660, "to": "mm"},
5732 "name": "PA_SC_VPORT_ZMAX_12",
5733 "type_ref": "PA_SC_VPORT_ZMAX_0"
5737 "map": {"at": 164664, "to": "mm"},
5738 "name": "PA_SC_VPORT_ZMIN_13",
5739 "type_ref": "PA_SC_VPORT_ZMIN_0"
5743 "map": {"at": 164668, "to": "mm"},
5744 "name": "PA_SC_VPORT_ZMAX_13",
5745 "type_ref": "PA_SC_VPORT_ZMAX_0"
5749 "map": {"at": 164672, "to": "mm"},
5750 "name": "PA_SC_VPORT_ZMIN_14",
5751 "type_ref": "PA_SC_VPORT_ZMIN_0"
5755 "map": {"at": 164676, "to": "mm"},
5756 "name": "PA_SC_VPORT_ZMAX_14",
5757 "type_ref": "PA_SC_VPORT_ZMAX_0"
5761 "map": {"at": 164680, "to": "mm"},
5762 "name": "PA_SC_VPORT_ZMIN_15",
5763 "type_ref": "PA_SC_VPORT_ZMIN_0"
5767 "map": {"at": 164684, "to": "mm"},
5768 "name": "PA_SC_VPORT_ZMAX_15",
5769 "type_ref": "PA_SC_VPORT_ZMAX_0"
5773 "map": {"at": 164688, "to": "mm"},
5774 "name": "PA_SC_RASTER_CONFIG",
5775 "type_ref": "PA_SC_RASTER_CONFIG"
5779 "map": {"at": 164704, "to": "mm"},
5780 "name": "CP_PERFMON_CNTX_CNTL",
5781 "type_ref": "CP_PERFMON_CNTX_CNTL"
5785 "map": {"at": 164708, "to": "mm"},
5786 "name": "CP_RINGID",
5787 "type_ref": "CP_RINGID"
5791 "map": {"at": 164712, "to": "mm"},
5793 "type_ref": "CP_VMID"
5797 "map": {"at": 164864, "to": "mm"},
5798 "name": "VGT_MAX_VTX_INDX",
5799 "type_ref": "VGT_MAX_VTX_INDX"
5803 "map": {"at": 164868, "to": "mm"},
5804 "name": "VGT_MIN_VTX_INDX",
5805 "type_ref": "VGT_MIN_VTX_INDX"
5809 "map": {"at": 164872, "to": "mm"},
5810 "name": "VGT_INDX_OFFSET",
5811 "type_ref": "VGT_INDX_OFFSET"
5815 "map": {"at": 164876, "to": "mm"},
5816 "name": "VGT_MULTI_PRIM_IB_RESET_INDX",
5817 "type_ref": "VGT_MULTI_PRIM_IB_RESET_INDX"
5821 "map": {"at": 164884, "to": "mm"},
5822 "name": "CB_BLEND_RED",
5823 "type_ref": "CB_BLEND_RED"
5827 "map": {"at": 164888, "to": "mm"},
5828 "name": "CB_BLEND_GREEN",
5829 "type_ref": "CB_BLEND_GREEN"
5833 "map": {"at": 164892, "to": "mm"},
5834 "name": "CB_BLEND_BLUE",
5835 "type_ref": "CB_BLEND_BLUE"
5839 "map": {"at": 164896, "to": "mm"},
5840 "name": "CB_BLEND_ALPHA",
5841 "type_ref": "CB_BLEND_ALPHA"
5845 "map": {"at": 164908, "to": "mm"},
5846 "name": "DB_STENCIL_CONTROL",
5847 "type_ref": "DB_STENCIL_CONTROL"
5851 "map": {"at": 164912, "to": "mm"},
5852 "name": "DB_STENCILREFMASK",
5853 "type_ref": "DB_STENCILREFMASK"
5857 "map": {"at": 164916, "to": "mm"},
5858 "name": "DB_STENCILREFMASK_BF",
5859 "type_ref": "DB_STENCILREFMASK_BF"
5863 "map": {"at": 164924, "to": "mm"},
5864 "name": "PA_CL_VPORT_XSCALE",
5865 "type_ref": "PA_CL_VPORT_XSCALE"
5869 "map": {"at": 164928, "to": "mm"},
5870 "name": "PA_CL_VPORT_XOFFSET",
5871 "type_ref": "PA_CL_VPORT_XOFFSET"
5875 "map": {"at": 164932, "to": "mm"},
5876 "name": "PA_CL_VPORT_YSCALE",
5877 "type_ref": "PA_CL_VPORT_YSCALE"
5881 "map": {"at": 164936, "to": "mm"},
5882 "name": "PA_CL_VPORT_YOFFSET",
5883 "type_ref": "PA_CL_VPORT_YOFFSET"
5887 "map": {"at": 164940, "to": "mm"},
5888 "name": "PA_CL_VPORT_ZSCALE",
5889 "type_ref": "PA_CL_VPORT_ZSCALE"
5893 "map": {"at": 164944, "to": "mm"},
5894 "name": "PA_CL_VPORT_ZOFFSET",
5895 "type_ref": "PA_CL_VPORT_ZOFFSET"
5899 "map": {"at": 164948, "to": "mm"},
5900 "name": "PA_CL_VPORT_XSCALE_1",
5901 "type_ref": "PA_CL_VPORT_XSCALE"
5905 "map": {"at": 164952, "to": "mm"},
5906 "name": "PA_CL_VPORT_XOFFSET_1",
5907 "type_ref": "PA_CL_VPORT_XOFFSET"
5911 "map": {"at": 164956, "to": "mm"},
5912 "name": "PA_CL_VPORT_YSCALE_1",
5913 "type_ref": "PA_CL_VPORT_YSCALE"
5917 "map": {"at": 164960, "to": "mm"},
5918 "name": "PA_CL_VPORT_YOFFSET_1",
5919 "type_ref": "PA_CL_VPORT_YOFFSET"
5923 "map": {"at": 164964, "to": "mm"},
5924 "name": "PA_CL_VPORT_ZSCALE_1",
5925 "type_ref": "PA_CL_VPORT_ZSCALE"
5929 "map": {"at": 164968, "to": "mm"},
5930 "name": "PA_CL_VPORT_ZOFFSET_1",
5931 "type_ref": "PA_CL_VPORT_ZOFFSET"
5935 "map": {"at": 164972, "to": "mm"},
5936 "name": "PA_CL_VPORT_XSCALE_2",
5937 "type_ref": "PA_CL_VPORT_XSCALE"
5941 "map": {"at": 164976, "to": "mm"},
5942 "name": "PA_CL_VPORT_XOFFSET_2",
5943 "type_ref": "PA_CL_VPORT_XOFFSET"
5947 "map": {"at": 164980, "to": "mm"},
5948 "name": "PA_CL_VPORT_YSCALE_2",
5949 "type_ref": "PA_CL_VPORT_YSCALE"
5953 "map": {"at": 164984, "to": "mm"},
5954 "name": "PA_CL_VPORT_YOFFSET_2",
5955 "type_ref": "PA_CL_VPORT_YOFFSET"
5959 "map": {"at": 164988, "to": "mm"},
5960 "name": "PA_CL_VPORT_ZSCALE_2",
5961 "type_ref": "PA_CL_VPORT_ZSCALE"
5965 "map": {"at": 164992, "to": "mm"},
5966 "name": "PA_CL_VPORT_ZOFFSET_2",
5967 "type_ref": "PA_CL_VPORT_ZOFFSET"
5971 "map": {"at": 164996, "to": "mm"},
5972 "name": "PA_CL_VPORT_XSCALE_3",
5973 "type_ref": "PA_CL_VPORT_XSCALE"
5977 "map": {"at": 165000, "to": "mm"},
5978 "name": "PA_CL_VPORT_XOFFSET_3",
5979 "type_ref": "PA_CL_VPORT_XOFFSET"
5983 "map": {"at": 165004, "to": "mm"},
5984 "name": "PA_CL_VPORT_YSCALE_3",
5985 "type_ref": "PA_CL_VPORT_YSCALE"
5989 "map": {"at": 165008, "to": "mm"},
5990 "name": "PA_CL_VPORT_YOFFSET_3",
5991 "type_ref": "PA_CL_VPORT_YOFFSET"
5995 "map": {"at": 165012, "to": "mm"},
5996 "name": "PA_CL_VPORT_ZSCALE_3",
5997 "type_ref": "PA_CL_VPORT_ZSCALE"
6001 "map": {"at": 165016, "to": "mm"},
6002 "name": "PA_CL_VPORT_ZOFFSET_3",
6003 "type_ref": "PA_CL_VPORT_ZOFFSET"
6007 "map": {"at": 165020, "to": "mm"},
6008 "name": "PA_CL_VPORT_XSCALE_4",
6009 "type_ref": "PA_CL_VPORT_XSCALE"
6013 "map": {"at": 165024, "to": "mm"},
6014 "name": "PA_CL_VPORT_XOFFSET_4",
6015 "type_ref": "PA_CL_VPORT_XOFFSET"
6019 "map": {"at": 165028, "to": "mm"},
6020 "name": "PA_CL_VPORT_YSCALE_4",
6021 "type_ref": "PA_CL_VPORT_YSCALE"
6025 "map": {"at": 165032, "to": "mm"},
6026 "name": "PA_CL_VPORT_YOFFSET_4",
6027 "type_ref": "PA_CL_VPORT_YOFFSET"
6031 "map": {"at": 165036, "to": "mm"},
6032 "name": "PA_CL_VPORT_ZSCALE_4",
6033 "type_ref": "PA_CL_VPORT_ZSCALE"
6037 "map": {"at": 165040, "to": "mm"},
6038 "name": "PA_CL_VPORT_ZOFFSET_4",
6039 "type_ref": "PA_CL_VPORT_ZOFFSET"
6043 "map": {"at": 165044, "to": "mm"},
6044 "name": "PA_CL_VPORT_XSCALE_5",
6045 "type_ref": "PA_CL_VPORT_XSCALE"
6049 "map": {"at": 165048, "to": "mm"},
6050 "name": "PA_CL_VPORT_XOFFSET_5",
6051 "type_ref": "PA_CL_VPORT_XOFFSET"
6055 "map": {"at": 165052, "to": "mm"},
6056 "name": "PA_CL_VPORT_YSCALE_5",
6057 "type_ref": "PA_CL_VPORT_YSCALE"
6061 "map": {"at": 165056, "to": "mm"},
6062 "name": "PA_CL_VPORT_YOFFSET_5",
6063 "type_ref": "PA_CL_VPORT_YOFFSET"
6067 "map": {"at": 165060, "to": "mm"},
6068 "name": "PA_CL_VPORT_ZSCALE_5",
6069 "type_ref": "PA_CL_VPORT_ZSCALE"
6073 "map": {"at": 165064, "to": "mm"},
6074 "name": "PA_CL_VPORT_ZOFFSET_5",
6075 "type_ref": "PA_CL_VPORT_ZOFFSET"
6079 "map": {"at": 165068, "to": "mm"},
6080 "name": "PA_CL_VPORT_XSCALE_6",
6081 "type_ref": "PA_CL_VPORT_XSCALE"
6085 "map": {"at": 165072, "to": "mm"},
6086 "name": "PA_CL_VPORT_XOFFSET_6",
6087 "type_ref": "PA_CL_VPORT_XOFFSET"
6091 "map": {"at": 165076, "to": "mm"},
6092 "name": "PA_CL_VPORT_YSCALE_6",
6093 "type_ref": "PA_CL_VPORT_YSCALE"
6097 "map": {"at": 165080, "to": "mm"},
6098 "name": "PA_CL_VPORT_YOFFSET_6",
6099 "type_ref": "PA_CL_VPORT_YOFFSET"
6103 "map": {"at": 165084, "to": "mm"},
6104 "name": "PA_CL_VPORT_ZSCALE_6",
6105 "type_ref": "PA_CL_VPORT_ZSCALE"
6109 "map": {"at": 165088, "to": "mm"},
6110 "name": "PA_CL_VPORT_ZOFFSET_6",
6111 "type_ref": "PA_CL_VPORT_ZOFFSET"
6115 "map": {"at": 165092, "to": "mm"},
6116 "name": "PA_CL_VPORT_XSCALE_7",
6117 "type_ref": "PA_CL_VPORT_XSCALE"
6121 "map": {"at": 165096, "to": "mm"},
6122 "name": "PA_CL_VPORT_XOFFSET_7",
6123 "type_ref": "PA_CL_VPORT_XOFFSET"
6127 "map": {"at": 165100, "to": "mm"},
6128 "name": "PA_CL_VPORT_YSCALE_7",
6129 "type_ref": "PA_CL_VPORT_YSCALE"
6133 "map": {"at": 165104, "to": "mm"},
6134 "name": "PA_CL_VPORT_YOFFSET_7",
6135 "type_ref": "PA_CL_VPORT_YOFFSET"
6139 "map": {"at": 165108, "to": "mm"},
6140 "name": "PA_CL_VPORT_ZSCALE_7",
6141 "type_ref": "PA_CL_VPORT_ZSCALE"
6145 "map": {"at": 165112, "to": "mm"},
6146 "name": "PA_CL_VPORT_ZOFFSET_7",
6147 "type_ref": "PA_CL_VPORT_ZOFFSET"
6151 "map": {"at": 165116, "to": "mm"},
6152 "name": "PA_CL_VPORT_XSCALE_8",
6153 "type_ref": "PA_CL_VPORT_XSCALE"
6157 "map": {"at": 165120, "to": "mm"},
6158 "name": "PA_CL_VPORT_XOFFSET_8",
6159 "type_ref": "PA_CL_VPORT_XOFFSET"
6163 "map": {"at": 165124, "to": "mm"},
6164 "name": "PA_CL_VPORT_YSCALE_8",
6165 "type_ref": "PA_CL_VPORT_YSCALE"
6169 "map": {"at": 165128, "to": "mm"},
6170 "name": "PA_CL_VPORT_YOFFSET_8",
6171 "type_ref": "PA_CL_VPORT_YOFFSET"
6175 "map": {"at": 165132, "to": "mm"},
6176 "name": "PA_CL_VPORT_ZSCALE_8",
6177 "type_ref": "PA_CL_VPORT_ZSCALE"
6181 "map": {"at": 165136, "to": "mm"},
6182 "name": "PA_CL_VPORT_ZOFFSET_8",
6183 "type_ref": "PA_CL_VPORT_ZOFFSET"
6187 "map": {"at": 165140, "to": "mm"},
6188 "name": "PA_CL_VPORT_XSCALE_9",
6189 "type_ref": "PA_CL_VPORT_XSCALE"
6193 "map": {"at": 165144, "to": "mm"},
6194 "name": "PA_CL_VPORT_XOFFSET_9",
6195 "type_ref": "PA_CL_VPORT_XOFFSET"
6199 "map": {"at": 165148, "to": "mm"},
6200 "name": "PA_CL_VPORT_YSCALE_9",
6201 "type_ref": "PA_CL_VPORT_YSCALE"
6205 "map": {"at": 165152, "to": "mm"},
6206 "name": "PA_CL_VPORT_YOFFSET_9",
6207 "type_ref": "PA_CL_VPORT_YOFFSET"
6211 "map": {"at": 165156, "to": "mm"},
6212 "name": "PA_CL_VPORT_ZSCALE_9",
6213 "type_ref": "PA_CL_VPORT_ZSCALE"
6217 "map": {"at": 165160, "to": "mm"},
6218 "name": "PA_CL_VPORT_ZOFFSET_9",
6219 "type_ref": "PA_CL_VPORT_ZOFFSET"
6223 "map": {"at": 165164, "to": "mm"},
6224 "name": "PA_CL_VPORT_XSCALE_10",
6225 "type_ref": "PA_CL_VPORT_XSCALE"
6229 "map": {"at": 165168, "to": "mm"},
6230 "name": "PA_CL_VPORT_XOFFSET_10",
6231 "type_ref": "PA_CL_VPORT_XOFFSET"
6235 "map": {"at": 165172, "to": "mm"},
6236 "name": "PA_CL_VPORT_YSCALE_10",
6237 "type_ref": "PA_CL_VPORT_YSCALE"
6241 "map": {"at": 165176, "to": "mm"},
6242 "name": "PA_CL_VPORT_YOFFSET_10",
6243 "type_ref": "PA_CL_VPORT_YOFFSET"
6247 "map": {"at": 165180, "to": "mm"},
6248 "name": "PA_CL_VPORT_ZSCALE_10",
6249 "type_ref": "PA_CL_VPORT_ZSCALE"
6253 "map": {"at": 165184, "to": "mm"},
6254 "name": "PA_CL_VPORT_ZOFFSET_10",
6255 "type_ref": "PA_CL_VPORT_ZOFFSET"
6259 "map": {"at": 165188, "to": "mm"},
6260 "name": "PA_CL_VPORT_XSCALE_11",
6261 "type_ref": "PA_CL_VPORT_XSCALE"
6265 "map": {"at": 165192, "to": "mm"},
6266 "name": "PA_CL_VPORT_XOFFSET_11",
6267 "type_ref": "PA_CL_VPORT_XOFFSET"
6271 "map": {"at": 165196, "to": "mm"},
6272 "name": "PA_CL_VPORT_YSCALE_11",
6273 "type_ref": "PA_CL_VPORT_YSCALE"
6277 "map": {"at": 165200, "to": "mm"},
6278 "name": "PA_CL_VPORT_YOFFSET_11",
6279 "type_ref": "PA_CL_VPORT_YOFFSET"
6283 "map": {"at": 165204, "to": "mm"},
6284 "name": "PA_CL_VPORT_ZSCALE_11",
6285 "type_ref": "PA_CL_VPORT_ZSCALE"
6289 "map": {"at": 165208, "to": "mm"},
6290 "name": "PA_CL_VPORT_ZOFFSET_11",
6291 "type_ref": "PA_CL_VPORT_ZOFFSET"
6295 "map": {"at": 165212, "to": "mm"},
6296 "name": "PA_CL_VPORT_XSCALE_12",
6297 "type_ref": "PA_CL_VPORT_XSCALE"
6301 "map": {"at": 165216, "to": "mm"},
6302 "name": "PA_CL_VPORT_XOFFSET_12",
6303 "type_ref": "PA_CL_VPORT_XOFFSET"
6307 "map": {"at": 165220, "to": "mm"},
6308 "name": "PA_CL_VPORT_YSCALE_12",
6309 "type_ref": "PA_CL_VPORT_YSCALE"
6313 "map": {"at": 165224, "to": "mm"},
6314 "name": "PA_CL_VPORT_YOFFSET_12",
6315 "type_ref": "PA_CL_VPORT_YOFFSET"
6319 "map": {"at": 165228, "to": "mm"},
6320 "name": "PA_CL_VPORT_ZSCALE_12",
6321 "type_ref": "PA_CL_VPORT_ZSCALE"
6325 "map": {"at": 165232, "to": "mm"},
6326 "name": "PA_CL_VPORT_ZOFFSET_12",
6327 "type_ref": "PA_CL_VPORT_ZOFFSET"
6331 "map": {"at": 165236, "to": "mm"},
6332 "name": "PA_CL_VPORT_XSCALE_13",
6333 "type_ref": "PA_CL_VPORT_XSCALE"
6337 "map": {"at": 165240, "to": "mm"},
6338 "name": "PA_CL_VPORT_XOFFSET_13",
6339 "type_ref": "PA_CL_VPORT_XOFFSET"
6343 "map": {"at": 165244, "to": "mm"},
6344 "name": "PA_CL_VPORT_YSCALE_13",
6345 "type_ref": "PA_CL_VPORT_YSCALE"
6349 "map": {"at": 165248, "to": "mm"},
6350 "name": "PA_CL_VPORT_YOFFSET_13",
6351 "type_ref": "PA_CL_VPORT_YOFFSET"
6355 "map": {"at": 165252, "to": "mm"},
6356 "name": "PA_CL_VPORT_ZSCALE_13",
6357 "type_ref": "PA_CL_VPORT_ZSCALE"
6361 "map": {"at": 165256, "to": "mm"},
6362 "name": "PA_CL_VPORT_ZOFFSET_13",
6363 "type_ref": "PA_CL_VPORT_ZOFFSET"
6367 "map": {"at": 165260, "to": "mm"},
6368 "name": "PA_CL_VPORT_XSCALE_14",
6369 "type_ref": "PA_CL_VPORT_XSCALE"
6373 "map": {"at": 165264, "to": "mm"},
6374 "name": "PA_CL_VPORT_XOFFSET_14",
6375 "type_ref": "PA_CL_VPORT_XOFFSET"
6379 "map": {"at": 165268, "to": "mm"},
6380 "name": "PA_CL_VPORT_YSCALE_14",
6381 "type_ref": "PA_CL_VPORT_YSCALE"
6385 "map": {"at": 165272, "to": "mm"},
6386 "name": "PA_CL_VPORT_YOFFSET_14",
6387 "type_ref": "PA_CL_VPORT_YOFFSET"
6391 "map": {"at": 165276, "to": "mm"},
6392 "name": "PA_CL_VPORT_ZSCALE_14",
6393 "type_ref": "PA_CL_VPORT_ZSCALE"
6397 "map": {"at": 165280, "to": "mm"},
6398 "name": "PA_CL_VPORT_ZOFFSET_14",
6399 "type_ref": "PA_CL_VPORT_ZOFFSET"
6403 "map": {"at": 165284, "to": "mm"},
6404 "name": "PA_CL_VPORT_XSCALE_15",
6405 "type_ref": "PA_CL_VPORT_XSCALE"
6409 "map": {"at": 165288, "to": "mm"},
6410 "name": "PA_CL_VPORT_XOFFSET_15",
6411 "type_ref": "PA_CL_VPORT_XOFFSET"
6415 "map": {"at": 165292, "to": "mm"},
6416 "name": "PA_CL_VPORT_YSCALE_15",
6417 "type_ref": "PA_CL_VPORT_YSCALE"
6421 "map": {"at": 165296, "to": "mm"},
6422 "name": "PA_CL_VPORT_YOFFSET_15",
6423 "type_ref": "PA_CL_VPORT_YOFFSET"
6427 "map": {"at": 165300, "to": "mm"},
6428 "name": "PA_CL_VPORT_ZSCALE_15",
6429 "type_ref": "PA_CL_VPORT_ZSCALE"
6433 "map": {"at": 165304, "to": "mm"},
6434 "name": "PA_CL_VPORT_ZOFFSET_15",
6435 "type_ref": "PA_CL_VPORT_ZOFFSET"
6439 "map": {"at": 165308, "to": "mm"},
6440 "name": "PA_CL_UCP_0_X",
6441 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6445 "map": {"at": 165312, "to": "mm"},
6446 "name": "PA_CL_UCP_0_Y",
6447 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6451 "map": {"at": 165316, "to": "mm"},
6452 "name": "PA_CL_UCP_0_Z",
6453 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6457 "map": {"at": 165320, "to": "mm"},
6458 "name": "PA_CL_UCP_0_W",
6459 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6463 "map": {"at": 165324, "to": "mm"},
6464 "name": "PA_CL_UCP_1_X",
6465 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6469 "map": {"at": 165328, "to": "mm"},
6470 "name": "PA_CL_UCP_1_Y",
6471 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6475 "map": {"at": 165332, "to": "mm"},
6476 "name": "PA_CL_UCP_1_Z",
6477 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6481 "map": {"at": 165336, "to": "mm"},
6482 "name": "PA_CL_UCP_1_W",
6483 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6487 "map": {"at": 165340, "to": "mm"},
6488 "name": "PA_CL_UCP_2_X",
6489 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6493 "map": {"at": 165344, "to": "mm"},
6494 "name": "PA_CL_UCP_2_Y",
6495 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6499 "map": {"at": 165348, "to": "mm"},
6500 "name": "PA_CL_UCP_2_Z",
6501 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6505 "map": {"at": 165352, "to": "mm"},
6506 "name": "PA_CL_UCP_2_W",
6507 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6511 "map": {"at": 165356, "to": "mm"},
6512 "name": "PA_CL_UCP_3_X",
6513 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6517 "map": {"at": 165360, "to": "mm"},
6518 "name": "PA_CL_UCP_3_Y",
6519 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6523 "map": {"at": 165364, "to": "mm"},
6524 "name": "PA_CL_UCP_3_Z",
6525 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6529 "map": {"at": 165368, "to": "mm"},
6530 "name": "PA_CL_UCP_3_W",
6531 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6535 "map": {"at": 165372, "to": "mm"},
6536 "name": "PA_CL_UCP_4_X",
6537 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6541 "map": {"at": 165376, "to": "mm"},
6542 "name": "PA_CL_UCP_4_Y",
6543 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6547 "map": {"at": 165380, "to": "mm"},
6548 "name": "PA_CL_UCP_4_Z",
6549 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6553 "map": {"at": 165384, "to": "mm"},
6554 "name": "PA_CL_UCP_4_W",
6555 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6559 "map": {"at": 165388, "to": "mm"},
6560 "name": "PA_CL_UCP_5_X",
6561 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6565 "map": {"at": 165392, "to": "mm"},
6566 "name": "PA_CL_UCP_5_Y",
6567 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6571 "map": {"at": 165396, "to": "mm"},
6572 "name": "PA_CL_UCP_5_Z",
6573 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6577 "map": {"at": 165400, "to": "mm"},
6578 "name": "PA_CL_UCP_5_W",
6579 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6583 "map": {"at": 165444, "to": "mm"},
6584 "name": "SPI_PS_INPUT_CNTL_0",
6585 "type_ref": "SPI_PS_INPUT_CNTL_0"
6589 "map": {"at": 165448, "to": "mm"},
6590 "name": "SPI_PS_INPUT_CNTL_1",
6591 "type_ref": "SPI_PS_INPUT_CNTL_0"
6595 "map": {"at": 165452, "to": "mm"},
6596 "name": "SPI_PS_INPUT_CNTL_2",
6597 "type_ref": "SPI_PS_INPUT_CNTL_0"
6601 "map": {"at": 165456, "to": "mm"},
6602 "name": "SPI_PS_INPUT_CNTL_3",
6603 "type_ref": "SPI_PS_INPUT_CNTL_0"
6607 "map": {"at": 165460, "to": "mm"},
6608 "name": "SPI_PS_INPUT_CNTL_4",
6609 "type_ref": "SPI_PS_INPUT_CNTL_0"
6613 "map": {"at": 165464, "to": "mm"},
6614 "name": "SPI_PS_INPUT_CNTL_5",
6615 "type_ref": "SPI_PS_INPUT_CNTL_0"
6619 "map": {"at": 165468, "to": "mm"},
6620 "name": "SPI_PS_INPUT_CNTL_6",
6621 "type_ref": "SPI_PS_INPUT_CNTL_0"
6625 "map": {"at": 165472, "to": "mm"},
6626 "name": "SPI_PS_INPUT_CNTL_7",
6627 "type_ref": "SPI_PS_INPUT_CNTL_0"
6631 "map": {"at": 165476, "to": "mm"},
6632 "name": "SPI_PS_INPUT_CNTL_8",
6633 "type_ref": "SPI_PS_INPUT_CNTL_0"
6637 "map": {"at": 165480, "to": "mm"},
6638 "name": "SPI_PS_INPUT_CNTL_9",
6639 "type_ref": "SPI_PS_INPUT_CNTL_0"
6643 "map": {"at": 165484, "to": "mm"},
6644 "name": "SPI_PS_INPUT_CNTL_10",
6645 "type_ref": "SPI_PS_INPUT_CNTL_0"
6649 "map": {"at": 165488, "to": "mm"},
6650 "name": "SPI_PS_INPUT_CNTL_11",
6651 "type_ref": "SPI_PS_INPUT_CNTL_0"
6655 "map": {"at": 165492, "to": "mm"},
6656 "name": "SPI_PS_INPUT_CNTL_12",
6657 "type_ref": "SPI_PS_INPUT_CNTL_0"
6661 "map": {"at": 165496, "to": "mm"},
6662 "name": "SPI_PS_INPUT_CNTL_13",
6663 "type_ref": "SPI_PS_INPUT_CNTL_0"
6667 "map": {"at": 165500, "to": "mm"},
6668 "name": "SPI_PS_INPUT_CNTL_14",
6669 "type_ref": "SPI_PS_INPUT_CNTL_0"
6673 "map": {"at": 165504, "to": "mm"},
6674 "name": "SPI_PS_INPUT_CNTL_15",
6675 "type_ref": "SPI_PS_INPUT_CNTL_0"
6679 "map": {"at": 165508, "to": "mm"},
6680 "name": "SPI_PS_INPUT_CNTL_16",
6681 "type_ref": "SPI_PS_INPUT_CNTL_0"
6685 "map": {"at": 165512, "to": "mm"},
6686 "name": "SPI_PS_INPUT_CNTL_17",
6687 "type_ref": "SPI_PS_INPUT_CNTL_0"
6691 "map": {"at": 165516, "to": "mm"},
6692 "name": "SPI_PS_INPUT_CNTL_18",
6693 "type_ref": "SPI_PS_INPUT_CNTL_0"
6697 "map": {"at": 165520, "to": "mm"},
6698 "name": "SPI_PS_INPUT_CNTL_19",
6699 "type_ref": "SPI_PS_INPUT_CNTL_0"
6703 "map": {"at": 165524, "to": "mm"},
6704 "name": "SPI_PS_INPUT_CNTL_20",
6705 "type_ref": "SPI_PS_INPUT_CNTL_20"
6709 "map": {"at": 165528, "to": "mm"},
6710 "name": "SPI_PS_INPUT_CNTL_21",
6711 "type_ref": "SPI_PS_INPUT_CNTL_20"
6715 "map": {"at": 165532, "to": "mm"},
6716 "name": "SPI_PS_INPUT_CNTL_22",
6717 "type_ref": "SPI_PS_INPUT_CNTL_20"
6721 "map": {"at": 165536, "to": "mm"},
6722 "name": "SPI_PS_INPUT_CNTL_23",
6723 "type_ref": "SPI_PS_INPUT_CNTL_20"
6727 "map": {"at": 165540, "to": "mm"},
6728 "name": "SPI_PS_INPUT_CNTL_24",
6729 "type_ref": "SPI_PS_INPUT_CNTL_20"
6733 "map": {"at": 165544, "to": "mm"},
6734 "name": "SPI_PS_INPUT_CNTL_25",
6735 "type_ref": "SPI_PS_INPUT_CNTL_20"
6739 "map": {"at": 165548, "to": "mm"},
6740 "name": "SPI_PS_INPUT_CNTL_26",
6741 "type_ref": "SPI_PS_INPUT_CNTL_20"
6745 "map": {"at": 165552, "to": "mm"},
6746 "name": "SPI_PS_INPUT_CNTL_27",
6747 "type_ref": "SPI_PS_INPUT_CNTL_20"
6751 "map": {"at": 165556, "to": "mm"},
6752 "name": "SPI_PS_INPUT_CNTL_28",
6753 "type_ref": "SPI_PS_INPUT_CNTL_20"
6757 "map": {"at": 165560, "to": "mm"},
6758 "name": "SPI_PS_INPUT_CNTL_29",
6759 "type_ref": "SPI_PS_INPUT_CNTL_20"
6763 "map": {"at": 165564, "to": "mm"},
6764 "name": "SPI_PS_INPUT_CNTL_30",
6765 "type_ref": "SPI_PS_INPUT_CNTL_20"
6769 "map": {"at": 165568, "to": "mm"},
6770 "name": "SPI_PS_INPUT_CNTL_31",
6771 "type_ref": "SPI_PS_INPUT_CNTL_20"
6775 "map": {"at": 165572, "to": "mm"},
6776 "name": "SPI_VS_OUT_CONFIG",
6777 "type_ref": "SPI_VS_OUT_CONFIG"
6781 "map": {"at": 165580, "to": "mm"},
6782 "name": "SPI_PS_INPUT_ENA",
6783 "type_ref": "SPI_PS_INPUT_ADDR"
6787 "map": {"at": 165584, "to": "mm"},
6788 "name": "SPI_PS_INPUT_ADDR",
6789 "type_ref": "SPI_PS_INPUT_ADDR"
6793 "map": {"at": 165588, "to": "mm"},
6794 "name": "SPI_INTERP_CONTROL_0",
6795 "type_ref": "SPI_INTERP_CONTROL_0"
6799 "map": {"at": 165592, "to": "mm"},
6800 "name": "SPI_PS_IN_CONTROL",
6801 "type_ref": "SPI_PS_IN_CONTROL"
6805 "map": {"at": 165600, "to": "mm"},
6806 "name": "SPI_BARYC_CNTL",
6807 "type_ref": "SPI_BARYC_CNTL"
6811 "map": {"at": 165608, "to": "mm"},
6812 "name": "SPI_TMPRING_SIZE",
6813 "type_ref": "COMPUTE_TMPRING_SIZE"
6817 "map": {"at": 165644, "to": "mm"},
6818 "name": "SPI_SHADER_POS_FORMAT",
6819 "type_ref": "SPI_SHADER_POS_FORMAT"
6823 "map": {"at": 165648, "to": "mm"},
6824 "name": "SPI_SHADER_Z_FORMAT",
6825 "type_ref": "SPI_SHADER_Z_FORMAT"
6829 "map": {"at": 165652, "to": "mm"},
6830 "name": "SPI_SHADER_COL_FORMAT",
6831 "type_ref": "SPI_SHADER_COL_FORMAT"
6835 "map": {"at": 165760, "to": "mm"},
6836 "name": "CB_BLEND0_CONTROL",
6837 "type_ref": "CB_BLEND0_CONTROL"
6841 "map": {"at": 165764, "to": "mm"},
6842 "name": "CB_BLEND1_CONTROL",
6843 "type_ref": "CB_BLEND0_CONTROL"
6847 "map": {"at": 165768, "to": "mm"},
6848 "name": "CB_BLEND2_CONTROL",
6849 "type_ref": "CB_BLEND0_CONTROL"
6853 "map": {"at": 165772, "to": "mm"},
6854 "name": "CB_BLEND3_CONTROL",
6855 "type_ref": "CB_BLEND0_CONTROL"
6859 "map": {"at": 165776, "to": "mm"},
6860 "name": "CB_BLEND4_CONTROL",
6861 "type_ref": "CB_BLEND0_CONTROL"
6865 "map": {"at": 165780, "to": "mm"},
6866 "name": "CB_BLEND5_CONTROL",
6867 "type_ref": "CB_BLEND0_CONTROL"
6871 "map": {"at": 165784, "to": "mm"},
6872 "name": "CB_BLEND6_CONTROL",
6873 "type_ref": "CB_BLEND0_CONTROL"
6877 "map": {"at": 165788, "to": "mm"},
6878 "name": "CB_BLEND7_CONTROL",
6879 "type_ref": "CB_BLEND0_CONTROL"
6883 "map": {"at": 165836, "to": "mm"},
6884 "name": "CS_COPY_STATE",
6885 "type_ref": "CS_COPY_STATE"
6889 "map": {"at": 165840, "to": "mm"},
6890 "name": "GFX_COPY_STATE",
6891 "type_ref": "CS_COPY_STATE"
6895 "map": {"at": 165844, "to": "mm"},
6896 "name": "PA_CL_POINT_X_RAD",
6897 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6901 "map": {"at": 165848, "to": "mm"},
6902 "name": "PA_CL_POINT_Y_RAD",
6903 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6907 "map": {"at": 165852, "to": "mm"},
6908 "name": "PA_CL_POINT_SIZE",
6909 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6913 "map": {"at": 165856, "to": "mm"},
6914 "name": "PA_CL_POINT_CULL_RAD",
6915 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
6919 "map": {"at": 165860, "to": "mm"},
6920 "name": "VGT_DMA_BASE_HI",
6921 "type_ref": "VGT_DMA_BASE_HI"
6925 "map": {"at": 165864, "to": "mm"},
6926 "name": "VGT_DMA_BASE",
6927 "type_ref": "VGT_DMA_BASE"
6931 "map": {"at": 165872, "to": "mm"},
6932 "name": "VGT_DRAW_INITIATOR",
6933 "type_ref": "VGT_DRAW_INITIATOR"
6937 "map": {"at": 165876, "to": "mm"},
6938 "name": "VGT_IMMED_DATA",
6939 "type_ref": "SQ_WAVE_TTMP0"
6943 "map": {"at": 165880, "to": "mm"},
6944 "name": "VGT_EVENT_ADDRESS_REG",
6945 "type_ref": "VGT_EVENT_ADDRESS_REG"
6949 "map": {"at": 165888, "to": "mm"},
6950 "name": "DB_DEPTH_CONTROL",
6951 "type_ref": "DB_DEPTH_CONTROL"
6955 "map": {"at": 165892, "to": "mm"},
6957 "type_ref": "DB_EQAA"
6961 "map": {"at": 165896, "to": "mm"},
6962 "name": "CB_COLOR_CONTROL",
6963 "type_ref": "CB_COLOR_CONTROL"
6967 "map": {"at": 165900, "to": "mm"},
6968 "name": "DB_SHADER_CONTROL",
6969 "type_ref": "DB_SHADER_CONTROL"
6973 "map": {"at": 165904, "to": "mm"},
6974 "name": "PA_CL_CLIP_CNTL",
6975 "type_ref": "PA_CL_CLIP_CNTL"
6979 "map": {"at": 165908, "to": "mm"},
6980 "name": "PA_SU_SC_MODE_CNTL",
6981 "type_ref": "PA_SU_SC_MODE_CNTL"
6985 "map": {"at": 165912, "to": "mm"},
6986 "name": "PA_CL_VTE_CNTL",
6987 "type_ref": "PA_CL_VTE_CNTL"
6991 "map": {"at": 165916, "to": "mm"},
6992 "name": "PA_CL_VS_OUT_CNTL",
6993 "type_ref": "PA_CL_VS_OUT_CNTL"
6997 "map": {"at": 165920, "to": "mm"},
6998 "name": "PA_CL_NANINF_CNTL",
6999 "type_ref": "PA_CL_NANINF_CNTL"
7003 "map": {"at": 165924, "to": "mm"},
7004 "name": "PA_SU_LINE_STIPPLE_CNTL",
7005 "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
7009 "map": {"at": 165928, "to": "mm"},
7010 "name": "PA_SU_LINE_STIPPLE_SCALE",
7011 "type_ref": "PA_SU_LINE_STIPPLE_SCALE"
7015 "map": {"at": 165932, "to": "mm"},
7016 "name": "PA_SU_PRIM_FILTER_CNTL",
7017 "type_ref": "PA_SU_PRIM_FILTER_CNTL"
7021 "map": {"at": 166400, "to": "mm"},
7022 "name": "PA_SU_POINT_SIZE",
7023 "type_ref": "PA_SU_POINT_SIZE"
7027 "map": {"at": 166404, "to": "mm"},
7028 "name": "PA_SU_POINT_MINMAX",
7029 "type_ref": "PA_SU_POINT_MINMAX"
7033 "map": {"at": 166408, "to": "mm"},
7034 "name": "PA_SU_LINE_CNTL",
7035 "type_ref": "PA_SU_LINE_CNTL"
7039 "map": {"at": 166412, "to": "mm"},
7040 "name": "PA_SC_LINE_STIPPLE",
7041 "type_ref": "PA_SC_LINE_STIPPLE"
7045 "map": {"at": 166416, "to": "mm"},
7046 "name": "VGT_OUTPUT_PATH_CNTL",
7047 "type_ref": "VGT_OUTPUT_PATH_CNTL"
7051 "map": {"at": 166420, "to": "mm"},
7052 "name": "VGT_HOS_CNTL",
7053 "type_ref": "VGT_HOS_CNTL"
7057 "map": {"at": 166424, "to": "mm"},
7058 "name": "VGT_HOS_MAX_TESS_LEVEL",
7059 "type_ref": "VGT_HOS_MAX_TESS_LEVEL"
7063 "map": {"at": 166428, "to": "mm"},
7064 "name": "VGT_HOS_MIN_TESS_LEVEL",
7065 "type_ref": "VGT_HOS_MIN_TESS_LEVEL"
7069 "map": {"at": 166432, "to": "mm"},
7070 "name": "VGT_HOS_REUSE_DEPTH",
7071 "type_ref": "VGT_HOS_REUSE_DEPTH"
7075 "map": {"at": 166436, "to": "mm"},
7076 "name": "VGT_GROUP_PRIM_TYPE",
7077 "type_ref": "VGT_GROUP_PRIM_TYPE"
7081 "map": {"at": 166440, "to": "mm"},
7082 "name": "VGT_GROUP_FIRST_DECR",
7083 "type_ref": "VGT_GROUP_FIRST_DECR"
7087 "map": {"at": 166444, "to": "mm"},
7088 "name": "VGT_GROUP_DECR",
7089 "type_ref": "VGT_GROUP_DECR"
7093 "map": {"at": 166448, "to": "mm"},
7094 "name": "VGT_GROUP_VECT_0_CNTL",
7095 "type_ref": "VGT_GROUP_VECT_0_CNTL"
7099 "map": {"at": 166452, "to": "mm"},
7100 "name": "VGT_GROUP_VECT_1_CNTL",
7101 "type_ref": "VGT_GROUP_VECT_0_CNTL"
7105 "map": {"at": 166456, "to": "mm"},
7106 "name": "VGT_GROUP_VECT_0_FMT_CNTL",
7107 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
7111 "map": {"at": 166460, "to": "mm"},
7112 "name": "VGT_GROUP_VECT_1_FMT_CNTL",
7113 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL"
7117 "map": {"at": 166464, "to": "mm"},
7118 "name": "VGT_GS_MODE",
7119 "type_ref": "VGT_GS_MODE"
7123 "map": {"at": 166472, "to": "mm"},
7124 "name": "PA_SC_MODE_CNTL_0",
7125 "type_ref": "PA_SC_MODE_CNTL_0"
7129 "map": {"at": 166476, "to": "mm"},
7130 "name": "PA_SC_MODE_CNTL_1",
7131 "type_ref": "PA_SC_MODE_CNTL_1"
7135 "map": {"at": 166480, "to": "mm"},
7136 "name": "VGT_ENHANCE",
7137 "type_ref": "IA_ENHANCE"
7141 "map": {"at": 166484, "to": "mm"},
7142 "name": "VGT_GS_PER_ES",
7143 "type_ref": "VGT_GS_PER_ES"
7147 "map": {"at": 166488, "to": "mm"},
7148 "name": "VGT_ES_PER_GS",
7149 "type_ref": "VGT_ES_PER_GS"
7153 "map": {"at": 166492, "to": "mm"},
7154 "name": "VGT_GS_PER_VS",
7155 "type_ref": "VGT_GS_PER_VS"
7159 "map": {"at": 166496, "to": "mm"},
7160 "name": "VGT_GSVS_RING_OFFSET_1",
7161 "type_ref": "VGT_GSVS_RING_OFFSET_1"
7165 "map": {"at": 166500, "to": "mm"},
7166 "name": "VGT_GSVS_RING_OFFSET_2",
7167 "type_ref": "VGT_GSVS_RING_OFFSET_1"
7171 "map": {"at": 166504, "to": "mm"},
7172 "name": "VGT_GSVS_RING_OFFSET_3",
7173 "type_ref": "VGT_GSVS_RING_OFFSET_1"
7177 "map": {"at": 166508, "to": "mm"},
7178 "name": "VGT_GS_OUT_PRIM_TYPE",
7179 "type_ref": "VGT_GS_OUT_PRIM_TYPE"
7183 "map": {"at": 166512, "to": "mm"},
7184 "name": "IA_ENHANCE",
7185 "type_ref": "IA_ENHANCE"
7189 "map": {"at": 166516, "to": "mm"},
7190 "name": "VGT_DMA_SIZE",
7191 "type_ref": "VGT_DMA_SIZE"
7195 "map": {"at": 166520, "to": "mm"},
7196 "name": "VGT_DMA_MAX_SIZE",
7197 "type_ref": "VGT_DMA_MAX_SIZE"
7201 "map": {"at": 166524, "to": "mm"},
7202 "name": "VGT_DMA_INDEX_TYPE",
7203 "type_ref": "VGT_DMA_INDEX_TYPE"
7207 "map": {"at": 166532, "to": "mm"},
7208 "name": "VGT_PRIMITIVEID_EN",
7209 "type_ref": "VGT_PRIMITIVEID_EN"
7213 "map": {"at": 166536, "to": "mm"},
7214 "name": "VGT_DMA_NUM_INSTANCES",
7215 "type_ref": "VGT_DMA_NUM_INSTANCES"
7219 "map": {"at": 166540, "to": "mm"},
7220 "name": "VGT_PRIMITIVEID_RESET",
7221 "type_ref": "VGT_PRIMITIVEID_RESET"
7225 "map": {"at": 166544, "to": "mm"},
7226 "name": "VGT_EVENT_INITIATOR",
7227 "type_ref": "VGT_EVENT_INITIATOR"
7231 "map": {"at": 166548, "to": "mm"},
7232 "name": "VGT_MULTI_PRIM_IB_RESET_EN",
7233 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN"
7237 "map": {"at": 166560, "to": "mm"},
7238 "name": "VGT_INSTANCE_STEP_RATE_0",
7239 "type_ref": "VGT_INSTANCE_STEP_RATE_0"
7243 "map": {"at": 166564, "to": "mm"},
7244 "name": "VGT_INSTANCE_STEP_RATE_1",
7245 "type_ref": "VGT_INSTANCE_STEP_RATE_0"
7249 "map": {"at": 166568, "to": "mm"},
7250 "name": "IA_MULTI_VGT_PARAM",
7251 "type_ref": "IA_MULTI_VGT_PARAM"
7255 "map": {"at": 166572, "to": "mm"},
7256 "name": "VGT_ESGS_RING_ITEMSIZE",
7257 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
7261 "map": {"at": 166576, "to": "mm"},
7262 "name": "VGT_GSVS_RING_ITEMSIZE",
7263 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
7267 "map": {"at": 166580, "to": "mm"},
7268 "name": "VGT_REUSE_OFF",
7269 "type_ref": "VGT_REUSE_OFF"
7273 "map": {"at": 166584, "to": "mm"},
7274 "name": "VGT_VTX_CNT_EN",
7275 "type_ref": "VGT_VTX_CNT_EN"
7279 "map": {"at": 166588, "to": "mm"},
7280 "name": "DB_HTILE_SURFACE",
7281 "type_ref": "DB_HTILE_SURFACE"
7285 "map": {"at": 166592, "to": "mm"},
7286 "name": "DB_SRESULTS_COMPARE_STATE0",
7287 "type_ref": "DB_SRESULTS_COMPARE_STATE0"
7291 "map": {"at": 166596, "to": "mm"},
7292 "name": "DB_SRESULTS_COMPARE_STATE1",
7293 "type_ref": "DB_SRESULTS_COMPARE_STATE1"
7297 "map": {"at": 166600, "to": "mm"},
7298 "name": "DB_PRELOAD_CONTROL",
7299 "type_ref": "DB_PRELOAD_CONTROL"
7303 "map": {"at": 166608, "to": "mm"},
7304 "name": "VGT_STRMOUT_BUFFER_SIZE_0",
7305 "type_ref": "COMPUTE_DIM_X"
7309 "map": {"at": 166612, "to": "mm"},
7310 "name": "VGT_STRMOUT_VTX_STRIDE_0",
7311 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
7315 "map": {"at": 166620, "to": "mm"},
7316 "name": "VGT_STRMOUT_BUFFER_OFFSET_0",
7317 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET"
7321 "map": {"at": 166624, "to": "mm"},
7322 "name": "VGT_STRMOUT_BUFFER_SIZE_1",
7323 "type_ref": "COMPUTE_DIM_X"
7327 "map": {"at": 166628, "to": "mm"},
7328 "name": "VGT_STRMOUT_VTX_STRIDE_1",
7329 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
7333 "map": {"at": 166636, "to": "mm"},
7334 "name": "VGT_STRMOUT_BUFFER_OFFSET_1",
7335 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET"
7339 "map": {"at": 166640, "to": "mm"},
7340 "name": "VGT_STRMOUT_BUFFER_SIZE_2",
7341 "type_ref": "COMPUTE_DIM_X"
7345 "map": {"at": 166644, "to": "mm"},
7346 "name": "VGT_STRMOUT_VTX_STRIDE_2",
7347 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
7351 "map": {"at": 166652, "to": "mm"},
7352 "name": "VGT_STRMOUT_BUFFER_OFFSET_2",
7353 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET"
7357 "map": {"at": 166656, "to": "mm"},
7358 "name": "VGT_STRMOUT_BUFFER_SIZE_3",
7359 "type_ref": "COMPUTE_DIM_X"
7363 "map": {"at": 166660, "to": "mm"},
7364 "name": "VGT_STRMOUT_VTX_STRIDE_3",
7365 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0"
7369 "map": {"at": 166668, "to": "mm"},
7370 "name": "VGT_STRMOUT_BUFFER_OFFSET_3",
7371 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET"
7375 "map": {"at": 166696, "to": "mm"},
7376 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET",
7377 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET"
7381 "map": {"at": 166700, "to": "mm"},
7382 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE",
7383 "type_ref": "COMPUTE_DIM_X"
7387 "map": {"at": 166704, "to": "mm"},
7388 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
7389 "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
7393 "map": {"at": 166712, "to": "mm"},
7394 "name": "VGT_GS_MAX_VERT_OUT",
7395 "type_ref": "VGT_GS_MAX_VERT_OUT"
7399 "map": {"at": 166740, "to": "mm"},
7400 "name": "VGT_SHADER_STAGES_EN",
7401 "type_ref": "VGT_SHADER_STAGES_EN"
7405 "map": {"at": 166744, "to": "mm"},
7406 "name": "VGT_LS_HS_CONFIG",
7407 "type_ref": "VGT_LS_HS_CONFIG"
7411 "map": {"at": 166748, "to": "mm"},
7412 "name": "VGT_GS_VERT_ITEMSIZE",
7413 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
7417 "map": {"at": 166752, "to": "mm"},
7418 "name": "VGT_GS_VERT_ITEMSIZE_1",
7419 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
7423 "map": {"at": 166756, "to": "mm"},
7424 "name": "VGT_GS_VERT_ITEMSIZE_2",
7425 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
7429 "map": {"at": 166760, "to": "mm"},
7430 "name": "VGT_GS_VERT_ITEMSIZE_3",
7431 "type_ref": "VGT_ESGS_RING_ITEMSIZE"
7435 "map": {"at": 166764, "to": "mm"},
7436 "name": "VGT_TF_PARAM",
7437 "type_ref": "VGT_TF_PARAM"
7441 "map": {"at": 166768, "to": "mm"},
7442 "name": "DB_ALPHA_TO_MASK",
7443 "type_ref": "DB_ALPHA_TO_MASK"
7447 "map": {"at": 166776, "to": "mm"},
7448 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
7449 "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
7453 "map": {"at": 166780, "to": "mm"},
7454 "name": "PA_SU_POLY_OFFSET_CLAMP",
7455 "type_ref": "PA_SU_POLY_OFFSET_CLAMP"
7459 "map": {"at": 166784, "to": "mm"},
7460 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE",
7461 "type_ref": "PA_SU_POLY_OFFSET_BACK_SCALE"
7465 "map": {"at": 166788, "to": "mm"},
7466 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET",
7467 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET"
7471 "map": {"at": 166792, "to": "mm"},
7472 "name": "PA_SU_POLY_OFFSET_BACK_SCALE",
7473 "type_ref": "PA_SU_POLY_OFFSET_BACK_SCALE"
7477 "map": {"at": 166796, "to": "mm"},
7478 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET",
7479 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET"
7483 "map": {"at": 166800, "to": "mm"},
7484 "name": "VGT_GS_INSTANCE_CNT",
7485 "type_ref": "VGT_GS_INSTANCE_CNT"
7489 "map": {"at": 166804, "to": "mm"},
7490 "name": "VGT_STRMOUT_CONFIG",
7491 "type_ref": "VGT_STRMOUT_CONFIG"
7495 "map": {"at": 166808, "to": "mm"},
7496 "name": "VGT_STRMOUT_BUFFER_CONFIG",
7497 "type_ref": "VGT_STRMOUT_BUFFER_CONFIG"
7501 "map": {"at": 166868, "to": "mm"},
7502 "name": "PA_SC_CENTROID_PRIORITY_0",
7503 "type_ref": "PA_SC_CENTROID_PRIORITY_0"
7507 "map": {"at": 166872, "to": "mm"},
7508 "name": "PA_SC_CENTROID_PRIORITY_1",
7509 "type_ref": "PA_SC_CENTROID_PRIORITY_1"
7513 "map": {"at": 166876, "to": "mm"},
7514 "name": "PA_SC_LINE_CNTL",
7515 "type_ref": "PA_SC_LINE_CNTL"
7519 "map": {"at": 166880, "to": "mm"},
7520 "name": "PA_SC_AA_CONFIG",
7521 "type_ref": "PA_SC_AA_CONFIG"
7525 "map": {"at": 166884, "to": "mm"},
7526 "name": "PA_SU_VTX_CNTL",
7527 "type_ref": "PA_SU_VTX_CNTL"
7531 "map": {"at": 166888, "to": "mm"},
7532 "name": "PA_CL_GB_VERT_CLIP_ADJ",
7533 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
7537 "map": {"at": 166892, "to": "mm"},
7538 "name": "PA_CL_GB_VERT_DISC_ADJ",
7539 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
7543 "map": {"at": 166896, "to": "mm"},
7544 "name": "PA_CL_GB_HORZ_CLIP_ADJ",
7545 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
7549 "map": {"at": 166900, "to": "mm"},
7550 "name": "PA_CL_GB_HORZ_DISC_ADJ",
7551 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ"
7555 "map": {"at": 166904, "to": "mm"},
7556 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
7557 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
7561 "map": {"at": 166908, "to": "mm"},
7562 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
7563 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
7567 "map": {"at": 166912, "to": "mm"},
7568 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
7569 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
7573 "map": {"at": 166916, "to": "mm"},
7574 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
7575 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
7579 "map": {"at": 166920, "to": "mm"},
7580 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
7581 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
7585 "map": {"at": 166924, "to": "mm"},
7586 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
7587 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
7591 "map": {"at": 166928, "to": "mm"},
7592 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
7593 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
7597 "map": {"at": 166932, "to": "mm"},
7598 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
7599 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
7603 "map": {"at": 166936, "to": "mm"},
7604 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
7605 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
7609 "map": {"at": 166940, "to": "mm"},
7610 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
7611 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
7615 "map": {"at": 166944, "to": "mm"},
7616 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
7617 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
7621 "map": {"at": 166948, "to": "mm"},
7622 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
7623 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
7627 "map": {"at": 166952, "to": "mm"},
7628 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
7629 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
7633 "map": {"at": 166956, "to": "mm"},
7634 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
7635 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
7639 "map": {"at": 166960, "to": "mm"},
7640 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
7641 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
7645 "map": {"at": 166964, "to": "mm"},
7646 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
7647 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
7651 "map": {"at": 166968, "to": "mm"},
7652 "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
7653 "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
7657 "map": {"at": 166972, "to": "mm"},
7658 "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
7659 "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
7663 "map": {"at": 167000, "to": "mm"},
7664 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL",
7665 "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL"
7669 "map": {"at": 167004, "to": "mm"},
7670 "name": "VGT_OUT_DEALLOC_CNTL",
7671 "type_ref": "VGT_OUT_DEALLOC_CNTL"
7675 "map": {"at": 167008, "to": "mm"},
7676 "name": "CB_COLOR0_BASE",
7677 "type_ref": "CB_COLOR0_BASE"
7681 "map": {"at": 167012, "to": "mm"},
7682 "name": "CB_COLOR0_PITCH",
7683 "type_ref": "CB_COLOR0_PITCH"
7687 "map": {"at": 167016, "to": "mm"},
7688 "name": "CB_COLOR0_SLICE",
7689 "type_ref": "CB_COLOR0_FMASK_SLICE"
7693 "map": {"at": 167020, "to": "mm"},
7694 "name": "CB_COLOR0_VIEW",
7695 "type_ref": "CB_COLOR0_VIEW"
7699 "map": {"at": 167024, "to": "mm"},
7700 "name": "CB_COLOR0_INFO",
7701 "type_ref": "CB_COLOR0_INFO"
7705 "map": {"at": 167028, "to": "mm"},
7706 "name": "CB_COLOR0_ATTRIB",
7707 "type_ref": "CB_COLOR0_ATTRIB"
7711 "map": {"at": 167036, "to": "mm"},
7712 "name": "CB_COLOR0_CMASK",
7713 "type_ref": "CB_COLOR0_BASE"
7717 "map": {"at": 167040, "to": "mm"},
7718 "name": "CB_COLOR0_CMASK_SLICE",
7719 "type_ref": "CB_COLOR0_CMASK_SLICE"
7723 "map": {"at": 167044, "to": "mm"},
7724 "name": "CB_COLOR0_FMASK",
7725 "type_ref": "CB_COLOR0_BASE"
7729 "map": {"at": 167048, "to": "mm"},
7730 "name": "CB_COLOR0_FMASK_SLICE",
7731 "type_ref": "CB_COLOR0_FMASK_SLICE"
7735 "map": {"at": 167052, "to": "mm"},
7736 "name": "CB_COLOR0_CLEAR_WORD0",
7737 "type_ref": "CB_COLOR0_CLEAR_WORD0"
7741 "map": {"at": 167056, "to": "mm"},
7742 "name": "CB_COLOR0_CLEAR_WORD1",
7743 "type_ref": "CB_COLOR0_CLEAR_WORD1"
7747 "map": {"at": 167068, "to": "mm"},
7748 "name": "CB_COLOR1_BASE",
7749 "type_ref": "CB_COLOR0_BASE"
7753 "map": {"at": 167072, "to": "mm"},
7754 "name": "CB_COLOR1_PITCH",
7755 "type_ref": "CB_COLOR0_PITCH"
7759 "map": {"at": 167076, "to": "mm"},
7760 "name": "CB_COLOR1_SLICE",
7761 "type_ref": "CB_COLOR0_FMASK_SLICE"
7765 "map": {"at": 167080, "to": "mm"},
7766 "name": "CB_COLOR1_VIEW",
7767 "type_ref": "CB_COLOR0_VIEW"
7771 "map": {"at": 167084, "to": "mm"},
7772 "name": "CB_COLOR1_INFO",
7773 "type_ref": "CB_COLOR0_INFO"
7777 "map": {"at": 167088, "to": "mm"},
7778 "name": "CB_COLOR1_ATTRIB",
7779 "type_ref": "CB_COLOR0_ATTRIB"
7783 "map": {"at": 167096, "to": "mm"},
7784 "name": "CB_COLOR1_CMASK",
7785 "type_ref": "CB_COLOR0_BASE"
7789 "map": {"at": 167100, "to": "mm"},
7790 "name": "CB_COLOR1_CMASK_SLICE",
7791 "type_ref": "CB_COLOR0_CMASK_SLICE"
7795 "map": {"at": 167104, "to": "mm"},
7796 "name": "CB_COLOR1_FMASK",
7797 "type_ref": "CB_COLOR0_BASE"
7801 "map": {"at": 167108, "to": "mm"},
7802 "name": "CB_COLOR1_FMASK_SLICE",
7803 "type_ref": "CB_COLOR0_FMASK_SLICE"
7807 "map": {"at": 167112, "to": "mm"},
7808 "name": "CB_COLOR1_CLEAR_WORD0",
7809 "type_ref": "CB_COLOR0_CLEAR_WORD0"
7813 "map": {"at": 167116, "to": "mm"},
7814 "name": "CB_COLOR1_CLEAR_WORD1",
7815 "type_ref": "CB_COLOR0_CLEAR_WORD1"
7819 "map": {"at": 167128, "to": "mm"},
7820 "name": "CB_COLOR2_BASE",
7821 "type_ref": "CB_COLOR0_BASE"
7825 "map": {"at": 167132, "to": "mm"},
7826 "name": "CB_COLOR2_PITCH",
7827 "type_ref": "CB_COLOR0_PITCH"
7831 "map": {"at": 167136, "to": "mm"},
7832 "name": "CB_COLOR2_SLICE",
7833 "type_ref": "CB_COLOR0_FMASK_SLICE"
7837 "map": {"at": 167140, "to": "mm"},
7838 "name": "CB_COLOR2_VIEW",
7839 "type_ref": "CB_COLOR0_VIEW"
7843 "map": {"at": 167144, "to": "mm"},
7844 "name": "CB_COLOR2_INFO",
7845 "type_ref": "CB_COLOR0_INFO"
7849 "map": {"at": 167148, "to": "mm"},
7850 "name": "CB_COLOR2_ATTRIB",
7851 "type_ref": "CB_COLOR0_ATTRIB"
7855 "map": {"at": 167156, "to": "mm"},
7856 "name": "CB_COLOR2_CMASK",
7857 "type_ref": "CB_COLOR0_BASE"
7861 "map": {"at": 167160, "to": "mm"},
7862 "name": "CB_COLOR2_CMASK_SLICE",
7863 "type_ref": "CB_COLOR0_CMASK_SLICE"
7867 "map": {"at": 167164, "to": "mm"},
7868 "name": "CB_COLOR2_FMASK",
7869 "type_ref": "CB_COLOR0_BASE"
7873 "map": {"at": 167168, "to": "mm"},
7874 "name": "CB_COLOR2_FMASK_SLICE",
7875 "type_ref": "CB_COLOR0_FMASK_SLICE"
7879 "map": {"at": 167172, "to": "mm"},
7880 "name": "CB_COLOR2_CLEAR_WORD0",
7881 "type_ref": "CB_COLOR0_CLEAR_WORD0"
7885 "map": {"at": 167176, "to": "mm"},
7886 "name": "CB_COLOR2_CLEAR_WORD1",
7887 "type_ref": "CB_COLOR0_CLEAR_WORD1"
7891 "map": {"at": 167188, "to": "mm"},
7892 "name": "CB_COLOR3_BASE",
7893 "type_ref": "CB_COLOR0_BASE"
7897 "map": {"at": 167192, "to": "mm"},
7898 "name": "CB_COLOR3_PITCH",
7899 "type_ref": "CB_COLOR0_PITCH"
7903 "map": {"at": 167196, "to": "mm"},
7904 "name": "CB_COLOR3_SLICE",
7905 "type_ref": "CB_COLOR0_FMASK_SLICE"
7909 "map": {"at": 167200, "to": "mm"},
7910 "name": "CB_COLOR3_VIEW",
7911 "type_ref": "CB_COLOR0_VIEW"
7915 "map": {"at": 167204, "to": "mm"},
7916 "name": "CB_COLOR3_INFO",
7917 "type_ref": "CB_COLOR0_INFO"
7921 "map": {"at": 167208, "to": "mm"},
7922 "name": "CB_COLOR3_ATTRIB",
7923 "type_ref": "CB_COLOR0_ATTRIB"
7927 "map": {"at": 167216, "to": "mm"},
7928 "name": "CB_COLOR3_CMASK",
7929 "type_ref": "CB_COLOR0_BASE"
7933 "map": {"at": 167220, "to": "mm"},
7934 "name": "CB_COLOR3_CMASK_SLICE",
7935 "type_ref": "CB_COLOR0_CMASK_SLICE"
7939 "map": {"at": 167224, "to": "mm"},
7940 "name": "CB_COLOR3_FMASK",
7941 "type_ref": "CB_COLOR0_BASE"
7945 "map": {"at": 167228, "to": "mm"},
7946 "name": "CB_COLOR3_FMASK_SLICE",
7947 "type_ref": "CB_COLOR0_FMASK_SLICE"
7951 "map": {"at": 167232, "to": "mm"},
7952 "name": "CB_COLOR3_CLEAR_WORD0",
7953 "type_ref": "CB_COLOR0_CLEAR_WORD0"
7957 "map": {"at": 167236, "to": "mm"},
7958 "name": "CB_COLOR3_CLEAR_WORD1",
7959 "type_ref": "CB_COLOR0_CLEAR_WORD1"
7963 "map": {"at": 167248, "to": "mm"},
7964 "name": "CB_COLOR4_BASE",
7965 "type_ref": "CB_COLOR0_BASE"
7969 "map": {"at": 167252, "to": "mm"},
7970 "name": "CB_COLOR4_PITCH",
7971 "type_ref": "CB_COLOR0_PITCH"
7975 "map": {"at": 167256, "to": "mm"},
7976 "name": "CB_COLOR4_SLICE",
7977 "type_ref": "CB_COLOR0_FMASK_SLICE"
7981 "map": {"at": 167260, "to": "mm"},
7982 "name": "CB_COLOR4_VIEW",
7983 "type_ref": "CB_COLOR0_VIEW"
7987 "map": {"at": 167264, "to": "mm"},
7988 "name": "CB_COLOR4_INFO",
7989 "type_ref": "CB_COLOR0_INFO"
7993 "map": {"at": 167268, "to": "mm"},
7994 "name": "CB_COLOR4_ATTRIB",
7995 "type_ref": "CB_COLOR0_ATTRIB"
7999 "map": {"at": 167276, "to": "mm"},
8000 "name": "CB_COLOR4_CMASK",
8001 "type_ref": "CB_COLOR0_BASE"
8005 "map": {"at": 167280, "to": "mm"},
8006 "name": "CB_COLOR4_CMASK_SLICE",
8007 "type_ref": "CB_COLOR0_CMASK_SLICE"
8011 "map": {"at": 167284, "to": "mm"},
8012 "name": "CB_COLOR4_FMASK",
8013 "type_ref": "CB_COLOR0_BASE"
8017 "map": {"at": 167288, "to": "mm"},
8018 "name": "CB_COLOR4_FMASK_SLICE",
8019 "type_ref": "CB_COLOR0_FMASK_SLICE"
8023 "map": {"at": 167292, "to": "mm"},
8024 "name": "CB_COLOR4_CLEAR_WORD0",
8025 "type_ref": "CB_COLOR0_CLEAR_WORD0"
8029 "map": {"at": 167296, "to": "mm"},
8030 "name": "CB_COLOR4_CLEAR_WORD1",
8031 "type_ref": "CB_COLOR0_CLEAR_WORD1"
8035 "map": {"at": 167308, "to": "mm"},
8036 "name": "CB_COLOR5_BASE",
8037 "type_ref": "CB_COLOR0_BASE"
8041 "map": {"at": 167312, "to": "mm"},
8042 "name": "CB_COLOR5_PITCH",
8043 "type_ref": "CB_COLOR0_PITCH"
8047 "map": {"at": 167316, "to": "mm"},
8048 "name": "CB_COLOR5_SLICE",
8049 "type_ref": "CB_COLOR0_FMASK_SLICE"
8053 "map": {"at": 167320, "to": "mm"},
8054 "name": "CB_COLOR5_VIEW",
8055 "type_ref": "CB_COLOR0_VIEW"
8059 "map": {"at": 167324, "to": "mm"},
8060 "name": "CB_COLOR5_INFO",
8061 "type_ref": "CB_COLOR0_INFO"
8065 "map": {"at": 167328, "to": "mm"},
8066 "name": "CB_COLOR5_ATTRIB",
8067 "type_ref": "CB_COLOR0_ATTRIB"
8071 "map": {"at": 167336, "to": "mm"},
8072 "name": "CB_COLOR5_CMASK",
8073 "type_ref": "CB_COLOR0_BASE"
8077 "map": {"at": 167340, "to": "mm"},
8078 "name": "CB_COLOR5_CMASK_SLICE",
8079 "type_ref": "CB_COLOR0_CMASK_SLICE"
8083 "map": {"at": 167344, "to": "mm"},
8084 "name": "CB_COLOR5_FMASK",
8085 "type_ref": "CB_COLOR0_BASE"
8089 "map": {"at": 167348, "to": "mm"},
8090 "name": "CB_COLOR5_FMASK_SLICE",
8091 "type_ref": "CB_COLOR0_FMASK_SLICE"
8095 "map": {"at": 167352, "to": "mm"},
8096 "name": "CB_COLOR5_CLEAR_WORD0",
8097 "type_ref": "CB_COLOR0_CLEAR_WORD0"
8101 "map": {"at": 167356, "to": "mm"},
8102 "name": "CB_COLOR5_CLEAR_WORD1",
8103 "type_ref": "CB_COLOR0_CLEAR_WORD1"
8107 "map": {"at": 167368, "to": "mm"},
8108 "name": "CB_COLOR6_BASE",
8109 "type_ref": "CB_COLOR0_BASE"
8113 "map": {"at": 167372, "to": "mm"},
8114 "name": "CB_COLOR6_PITCH",
8115 "type_ref": "CB_COLOR0_PITCH"
8119 "map": {"at": 167376, "to": "mm"},
8120 "name": "CB_COLOR6_SLICE",
8121 "type_ref": "CB_COLOR0_FMASK_SLICE"
8125 "map": {"at": 167380, "to": "mm"},
8126 "name": "CB_COLOR6_VIEW",
8127 "type_ref": "CB_COLOR0_VIEW"
8131 "map": {"at": 167384, "to": "mm"},
8132 "name": "CB_COLOR6_INFO",
8133 "type_ref": "CB_COLOR0_INFO"
8137 "map": {"at": 167388, "to": "mm"},
8138 "name": "CB_COLOR6_ATTRIB",
8139 "type_ref": "CB_COLOR0_ATTRIB"
8143 "map": {"at": 167396, "to": "mm"},
8144 "name": "CB_COLOR6_CMASK",
8145 "type_ref": "CB_COLOR0_BASE"
8149 "map": {"at": 167400, "to": "mm"},
8150 "name": "CB_COLOR6_CMASK_SLICE",
8151 "type_ref": "CB_COLOR0_CMASK_SLICE"
8155 "map": {"at": 167404, "to": "mm"},
8156 "name": "CB_COLOR6_FMASK",
8157 "type_ref": "CB_COLOR0_BASE"
8161 "map": {"at": 167408, "to": "mm"},
8162 "name": "CB_COLOR6_FMASK_SLICE",
8163 "type_ref": "CB_COLOR0_FMASK_SLICE"
8167 "map": {"at": 167412, "to": "mm"},
8168 "name": "CB_COLOR6_CLEAR_WORD0",
8169 "type_ref": "CB_COLOR0_CLEAR_WORD0"
8173 "map": {"at": 167416, "to": "mm"},
8174 "name": "CB_COLOR6_CLEAR_WORD1",
8175 "type_ref": "CB_COLOR0_CLEAR_WORD1"
8179 "map": {"at": 167428, "to": "mm"},
8180 "name": "CB_COLOR7_BASE",
8181 "type_ref": "CB_COLOR0_BASE"
8185 "map": {"at": 167432, "to": "mm"},
8186 "name": "CB_COLOR7_PITCH",
8187 "type_ref": "CB_COLOR0_PITCH"
8191 "map": {"at": 167436, "to": "mm"},
8192 "name": "CB_COLOR7_SLICE",
8193 "type_ref": "CB_COLOR0_FMASK_SLICE"
8197 "map": {"at": 167440, "to": "mm"},
8198 "name": "CB_COLOR7_VIEW",
8199 "type_ref": "CB_COLOR0_VIEW"
8203 "map": {"at": 167444, "to": "mm"},
8204 "name": "CB_COLOR7_INFO",
8205 "type_ref": "CB_COLOR0_INFO"
8209 "map": {"at": 167448, "to": "mm"},
8210 "name": "CB_COLOR7_ATTRIB",
8211 "type_ref": "CB_COLOR0_ATTRIB"
8215 "map": {"at": 167456, "to": "mm"},
8216 "name": "CB_COLOR7_CMASK",
8217 "type_ref": "CB_COLOR0_BASE"
8221 "map": {"at": 167460, "to": "mm"},
8222 "name": "CB_COLOR7_CMASK_SLICE",
8223 "type_ref": "CB_COLOR0_CMASK_SLICE"
8227 "map": {"at": 167464, "to": "mm"},
8228 "name": "CB_COLOR7_FMASK",
8229 "type_ref": "CB_COLOR0_BASE"
8233 "map": {"at": 167468, "to": "mm"},
8234 "name": "CB_COLOR7_FMASK_SLICE",
8235 "type_ref": "CB_COLOR0_FMASK_SLICE"
8239 "map": {"at": 167472, "to": "mm"},
8240 "name": "CB_COLOR7_CLEAR_WORD0",
8241 "type_ref": "CB_COLOR0_CLEAR_WORD0"
8245 "map": {"at": 167476, "to": "mm"},
8246 "name": "CB_COLOR7_CLEAR_WORD1",
8247 "type_ref": "CB_COLOR0_CLEAR_WORD1"
8251 "CB_BLEND0_CONTROL": {
8253 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
8254 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
8255 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
8256 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
8257 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
8258 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
8259 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
8260 {"bits": [30, 30], "name": "ENABLE"},
8261 {"bits": [31, 31], "name": "DISABLE_ROP3"}
8266 {"bits": [0, 31], "name": "BLEND_ALPHA"}
8271 {"bits": [0, 31], "name": "BLEND_BLUE"}
8276 {"bits": [0, 31], "name": "BLEND_GREEN"}
8281 {"bits": [0, 31], "name": "BLEND_RED"}
8284 "CB_COLOR0_ATTRIB": {
8286 {"bits": [0, 4], "name": "TILE_MODE_INDEX"},
8287 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"},
8288 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"},
8289 {"bits": [12, 14], "name": "NUM_SAMPLES"},
8290 {"bits": [15, 16], "name": "NUM_FRAGMENTS"},
8291 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}
8296 {"bits": [0, 31], "name": "BASE_256B"}
8299 "CB_COLOR0_CLEAR_WORD0": {
8301 {"bits": [0, 31], "name": "CLEAR_WORD0"}
8304 "CB_COLOR0_CLEAR_WORD1": {
8306 {"bits": [0, 31], "name": "CLEAR_WORD1"}
8309 "CB_COLOR0_CMASK_SLICE": {
8311 {"bits": [0, 13], "name": "TILE_MAX"}
8314 "CB_COLOR0_FMASK_SLICE": {
8316 {"bits": [0, 21], "name": "TILE_MAX"}
8321 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"},
8322 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"},
8323 {"bits": [7, 7], "name": "LINEAR_GENERAL"},
8324 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
8325 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
8326 {"bits": [13, 13], "name": "FAST_CLEAR"},
8327 {"bits": [14, 14], "name": "COMPRESSION"},
8328 {"bits": [15, 15], "name": "BLEND_CLAMP"},
8329 {"bits": [16, 16], "name": "BLEND_BYPASS"},
8330 {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
8331 {"bits": [18, 18], "name": "ROUND_MODE"},
8332 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"},
8333 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
8334 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"},
8335 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}
8338 "CB_COLOR0_PITCH": {
8340 {"bits": [0, 10], "name": "TILE_MAX"},
8341 {"bits": [20, 30], "name": "FMASK_TILE_MAX"}
8346 {"bits": [0, 10], "name": "SLICE_START"},
8347 {"bits": [13, 23], "name": "SLICE_MAX"}
8350 "CB_COLOR_CONTROL": {
8352 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
8353 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
8354 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
8359 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
8360 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
8361 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
8362 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
8363 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
8364 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
8365 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
8366 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
8371 {"bits": [0, 3], "name": "TARGET0_ENABLE"},
8372 {"bits": [4, 7], "name": "TARGET1_ENABLE"},
8373 {"bits": [8, 11], "name": "TARGET2_ENABLE"},
8374 {"bits": [12, 15], "name": "TARGET3_ENABLE"},
8375 {"bits": [16, 19], "name": "TARGET4_ENABLE"},
8376 {"bits": [20, 23], "name": "TARGET5_ENABLE"},
8377 {"bits": [24, 27], "name": "TARGET6_ENABLE"},
8378 {"bits": [28, 31], "name": "TARGET7_ENABLE"}
8381 "CC_GC_SHADER_ARRAY_CONFIG": {
8383 {"bits": [1, 2], "name": "DPFP_RATE"},
8384 {"bits": [3, 3], "name": "SQC_BALANCE_DISABLE"},
8385 {"bits": [4, 4], "name": "HALF_LDS"},
8386 {"bits": [16, 31], "name": "INACTIVE_CUS"}
8389 "CC_SQC_BANK_DISABLE": {
8391 {"bits": [16, 19], "name": "SQC0_BANK_DISABLE"},
8392 {"bits": [20, 23], "name": "SQC1_BANK_DISABLE"},
8393 {"bits": [24, 27], "name": "SQC2_BANK_DISABLE"},
8394 {"bits": [28, 31], "name": "SQC3_BANK_DISABLE"}
8397 "CGTT_IA_CLK_CTRL": {
8399 {"bits": [0, 3], "name": "ON_DELAY"},
8400 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
8401 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
8402 {"bits": [25, 25], "name": "PERF_ENABLE"},
8403 {"bits": [26, 26], "name": "DBG_ENABLE"},
8404 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
8405 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
8406 {"bits": [29, 29], "name": "CORE_OVERRIDE"},
8407 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"},
8408 {"bits": [31, 31], "name": "REG_OVERRIDE"}
8411 "CGTT_PA_CLK_CTRL": {
8413 {"bits": [0, 3], "name": "ON_DELAY"},
8414 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
8415 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
8416 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"},
8417 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"},
8418 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
8419 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
8420 {"bits": [29, 29], "name": "SU_CLK_OVERRIDE"},
8421 {"bits": [30, 30], "name": "CL_CLK_OVERRIDE"},
8422 {"bits": [31, 31], "name": "REG_CLK_OVERRIDE"}
8425 "CGTT_SC_CLK_CTRL": {
8427 {"bits": [0, 3], "name": "ON_DELAY"},
8428 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
8429 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
8430 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"},
8431 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"},
8432 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
8433 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
8434 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"},
8435 {"bits": [30, 30], "name": "SOFT_OVERRIDE1"},
8436 {"bits": [31, 31], "name": "SOFT_OVERRIDE0"}
8439 "CGTT_SQ_CLK_CTRL": {
8441 {"bits": [0, 3], "name": "ON_DELAY"},
8442 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
8443 {"bits": [30, 30], "name": "CORE_OVERRIDE"},
8444 {"bits": [31, 31], "name": "REG_OVERRIDE"}
8447 "CGTT_VGT_CLK_CTRL": {
8449 {"bits": [0, 3], "name": "ON_DELAY"},
8450 {"bits": [4, 11], "name": "OFF_HYSTERESIS"},
8451 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"},
8452 {"bits": [25, 25], "name": "PERF_ENABLE"},
8453 {"bits": [26, 26], "name": "DBG_ENABLE"},
8454 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"},
8455 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"},
8456 {"bits": [29, 29], "name": "GS_OVERRIDE"},
8457 {"bits": [30, 30], "name": "CORE_OVERRIDE"},
8458 {"bits": [31, 31], "name": "REG_OVERRIDE"}
8461 "COHER_DEST_BASE_0": {
8463 {"bits": [0, 31], "name": "DEST_BASE_256B"}
8468 {"bits": [0, 31], "name": "SIZE"}
8471 "COMPUTE_DISPATCH_INITIATOR": {
8473 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
8474 {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
8475 {"bits": [2, 2], "name": "FORCE_START_AT_000"},
8476 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
8477 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
8478 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
8479 {"bits": [6, 6], "name": "ORDER_MODE"},
8480 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"},
8481 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
8482 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
8483 {"bits": [12, 12], "name": "DATA_ATC"},
8484 {"bits": [14, 14], "name": "RESTORE"}
8487 "COMPUTE_NUM_THREAD_X": {
8489 {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
8490 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
8495 {"bits": [0, 7], "name": "DATA"},
8496 {"bits": [8, 8], "name": "INST_ATC"}
8499 "COMPUTE_PGM_RSRC1": {
8501 {"bits": [0, 5], "name": "VGPRS"},
8502 {"bits": [6, 9], "name": "SGPRS"},
8503 {"bits": [10, 11], "name": "PRIORITY"},
8504 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
8505 {"bits": [20, 20], "name": "PRIV"},
8506 {"bits": [21, 21], "name": "DX10_CLAMP"},
8507 {"bits": [22, 22], "name": "DEBUG_MODE"},
8508 {"bits": [23, 23], "name": "IEEE_MODE"},
8509 {"bits": [24, 24], "name": "BULKY"},
8510 {"bits": [25, 25], "name": "CDBG_USER"}
8513 "COMPUTE_PGM_RSRC2": {
8515 {"bits": [0, 0], "name": "SCRATCH_EN"},
8516 {"bits": [1, 5], "name": "USER_SGPR"},
8517 {"bits": [6, 6], "name": "TRAP_PRESENT"},
8518 {"bits": [7, 7], "name": "TGID_X_EN"},
8519 {"bits": [8, 8], "name": "TGID_Y_EN"},
8520 {"bits": [9, 9], "name": "TGID_Z_EN"},
8521 {"bits": [10, 10], "name": "TG_SIZE_EN"},
8522 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
8523 {"bits": [13, 14], "name": "EXCP_EN_MSB"},
8524 {"bits": [15, 23], "name": "LDS_SIZE"},
8525 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
8528 "COMPUTE_RESOURCE_LIMITS": {
8530 {"bits": [0, 5], "name": "WAVES_PER_SH"},
8531 {"bits": [0, 5], "name": "WAVES_PER_SH_GFX6"},
8532 {"bits": [12, 15], "name": "TG_PER_CU"},
8533 {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
8534 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
8535 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
8536 {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
8539 "COMPUTE_START_X": {
8541 {"bits": [0, 31], "name": "START"}
8544 "COMPUTE_STATIC_THREAD_MGMT_SE0": {
8546 {"bits": [0, 15], "name": "SH0_CU_EN"},
8547 {"bits": [16, 31], "name": "SH1_CU_EN"}
8552 {"bits": [0, 7], "name": "DATA"}
8555 "COMPUTE_TMPRING_SIZE": {
8557 {"bits": [0, 11], "name": "WAVES"},
8558 {"bits": [12, 24], "name": "WAVESIZE"}
8563 {"bits": [0, 3], "name": "DATA"}
8566 "CP_APPEND_ADDR_HI": {
8568 {"bits": [0, 7], "name": "MEM_ADDR_HI"},
8569 {"bits": [16, 17], "name": "CS_PS_SEL"},
8570 {"bits": [29, 31], "name": "COMMAND"}
8573 "CP_APPEND_ADDR_LO": {
8575 {"bits": [2, 31], "name": "MEM_ADDR_LO"}
8578 "CP_APPEND_LAST_CS_FENCE": {
8580 {"bits": [0, 31], "name": "LAST_FENCE"}
8583 "CP_ATOMIC_PREOP_HI": {
8585 {"bits": [0, 31], "name": "ATOMIC_PREOP_HI"}
8588 "CP_ATOMIC_PREOP_LO": {
8590 {"bits": [0, 31], "name": "ATOMIC_PREOP_LO"}
8595 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
8596 {"bits": [6, 6], "name": "COHER_CNT_NEQ_ZERO"},
8597 {"bits": [7, 7], "name": "PFP_PARSING_PACKETS"},
8598 {"bits": [8, 8], "name": "ME_PARSING_PACKETS"},
8599 {"bits": [9, 9], "name": "RCIU_PFP_BUSY"},
8600 {"bits": [10, 10], "name": "RCIU_ME_BUSY"},
8601 {"bits": [12, 12], "name": "SEM_CMDFIFO_NOT_EMPTY"},
8602 {"bits": [13, 13], "name": "SEM_FAILED_AND_HOLDING"},
8603 {"bits": [14, 14], "name": "SEM_POLLING_FOR_PASS"},
8604 {"bits": [15, 15], "name": "GFX_CONTEXT_BUSY"},
8605 {"bits": [17, 17], "name": "ME_PARSER_BUSY"},
8606 {"bits": [18, 18], "name": "EOP_DONE_BUSY"},
8607 {"bits": [19, 19], "name": "STRM_OUT_BUSY"},
8608 {"bits": [20, 20], "name": "PIPE_STATS_BUSY"},
8609 {"bits": [21, 21], "name": "RCIU_CE_BUSY"},
8610 {"bits": [22, 22], "name": "CE_PARSING_PACKETS"}
8615 {"bits": [0, 10], "name": "CEQ_CNT_RING"},
8616 {"bits": [16, 26], "name": "CEQ_CNT_IB1"}
8621 {"bits": [0, 10], "name": "CEQ_CNT_IB2"}
8624 "CP_CE_HEADER_DUMP": {
8626 {"bits": [0, 31], "name": "CE_HEADER_DUMP"}
8629 "CP_CE_IB1_BASE_HI": {
8631 {"bits": [0, 7], "name": "IB1_BASE_HI"}
8634 "CP_CE_IB1_BASE_LO": {
8636 {"bits": [2, 31], "name": "IB1_BASE_LO"}
8639 "CP_CE_IB1_BUFSZ": {
8641 {"bits": [0, 19], "name": "IB1_BUFSZ"}
8644 "CP_CE_IB2_BASE_HI": {
8646 {"bits": [0, 7], "name": "IB2_BASE_HI"}
8649 "CP_CE_IB2_BASE_LO": {
8651 {"bits": [2, 31], "name": "IB2_BASE_LO"}
8654 "CP_CE_IB2_BUFSZ": {
8656 {"bits": [0, 19], "name": "IB2_BUFSZ"}
8659 "CP_CE_INIT_BASE_HI": {
8661 {"bits": [0, 7], "name": "INIT_BASE_HI"}
8664 "CP_CE_INIT_BASE_LO": {
8666 {"bits": [5, 31], "name": "INIT_BASE_LO"}
8669 "CP_CE_INIT_BUFSZ": {
8671 {"bits": [0, 11], "name": "INIT_BUFSZ"}
8674 "CP_CE_ROQ_IB1_STAT": {
8676 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT1"},
8677 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT1"}
8680 "CP_CE_ROQ_IB2_STAT": {
8682 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT2"},
8683 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT2"}
8686 "CP_CE_ROQ_RB_STAT": {
8688 {"bits": [0, 9], "name": "CEQ_RPTR_PRIMARY"},
8689 {"bits": [16, 25], "name": "CEQ_WPTR_PRIMARY"}
8694 {"bits": [0, 31], "name": "CMD_DATA"}
8699 {"bits": [0, 10], "name": "CMD_INDEX"},
8700 {"bits": [12, 13], "name": "CMD_ME_SEL"},
8701 {"bits": [16, 17], "name": "CMD_QUEUE_SEL"}
8706 {"bits": [0, 7], "name": "ACTIVE_HP3D_CONTEXTS"},
8707 {"bits": [8, 10], "name": "CURRENT_HP3D_CONTEXT"},
8708 {"bits": [20, 27], "name": "ACTIVE_GFX_CONTEXTS"},
8709 {"bits": [28, 30], "name": "CURRENT_GFX_CONTEXT"}
8714 {"bits": [0, 31], "name": "COHER_BASE_256B"}
8719 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
8720 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
8721 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
8722 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
8723 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
8724 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
8725 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
8726 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
8727 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
8728 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
8729 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
8730 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"},
8731 {"bits": [16, 16], "name": "TC_VOL_ACTION_ENA"},
8732 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"},
8733 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
8734 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"},
8735 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"},
8736 {"bits": [23, 23], "name": "TC_ACTION_ENA"},
8737 {"bits": [25, 25], "name": "CB_ACTION_ENA"},
8738 {"bits": [26, 26], "name": "DB_ACTION_ENA"},
8739 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"},
8740 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"},
8741 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}
8746 {"bits": [0, 31], "name": "COHER_SIZE_256B"}
8749 "CP_COHER_START_DELAY": {
8751 {"bits": [0, 5], "name": "START_DELAY_COUNT"}
8754 "CP_COHER_STATUS": {
8756 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
8757 {"bits": [24, 25], "name": "MEID"},
8758 {"bits": [30, 30], "name": "PHASE1_STATUS"},
8759 {"bits": [31, 31], "name": "STATUS"}
8764 {"bits": [0, 3], "name": "FETCH_BUFFER_DEPTH"}
8769 {"bits": [0, 3], "name": "BUFFER_SLOTS_ALLOCATED"},
8770 {"bits": [8, 13], "name": "BUFFER_REQUEST_COUNT"}
8775 {"bits": [4, 5], "name": "MIN_AVAILSZ"},
8776 {"bits": [16, 19], "name": "BUFFER_DEPTH"},
8777 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
8778 {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
8779 {"bits": [30, 31], "name": "PIO_COUNT"}
8782 "CP_DMA_ME_COMMAND": {
8784 {"bits": [0, 20], "name": "BYTE_COUNT"},
8785 {"bits": [21, 21], "name": "DIS_WC"},
8786 {"bits": [22, 23], "name": "SRC_SWAP"},
8787 {"bits": [24, 25], "name": "DST_SWAP"},
8788 {"bits": [26, 26], "name": "SAS"},
8789 {"bits": [27, 27], "name": "DAS"},
8790 {"bits": [28, 28], "name": "SAIC"},
8791 {"bits": [29, 29], "name": "DAIC"},
8792 {"bits": [30, 30], "name": "RAW_WAIT"}
8795 "CP_DMA_ME_DST_ADDR": {
8797 {"bits": [0, 31], "name": "DST_ADDR"}
8800 "CP_DMA_ME_DST_ADDR_HI": {
8802 {"bits": [0, 7], "name": "DST_ADDR_HI"}
8805 "CP_DMA_ME_SRC_ADDR": {
8807 {"bits": [0, 31], "name": "SRC_ADDR"}
8810 "CP_DMA_ME_SRC_ADDR_HI": {
8812 {"bits": [0, 7], "name": "SRC_ADDR_HI"}
8815 "CP_DMA_READ_TAGS": {
8817 {"bits": [0, 25], "name": "DMA_READ_TAG"},
8818 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
8821 "CP_EOP_DONE_ADDR_HI": {
8823 {"bits": [0, 15], "name": "ADDR_HI"}
8826 "CP_EOP_DONE_ADDR_LO": {
8828 {"bits": [0, 1], "name": "ADDR_SWAP"},
8829 {"bits": [2, 31], "name": "ADDR_LO"}
8832 "CP_EOP_DONE_DATA_HI": {
8834 {"bits": [0, 31], "name": "DATA_HI"}
8837 "CP_EOP_DONE_DATA_LO": {
8839 {"bits": [0, 31], "name": "DATA_LO"}
8842 "CP_EOP_LAST_FENCE_HI": {
8844 {"bits": [0, 31], "name": "LAST_FENCE_HI"}
8847 "CP_EOP_LAST_FENCE_LO": {
8849 {"bits": [0, 31], "name": "LAST_FENCE_LO"}
8852 "CP_GDS_ATOMIC0_PREOP_HI": {
8854 {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_HI"}
8857 "CP_GDS_ATOMIC0_PREOP_LO": {
8859 {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_LO"}
8862 "CP_GDS_ATOMIC1_PREOP_HI": {
8864 {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_HI"}
8867 "CP_GDS_ATOMIC1_PREOP_LO": {
8869 {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_LO"}
8872 "CP_GRBM_FREE_COUNT": {
8874 {"bits": [0, 5], "name": "FREE_COUNT"},
8875 {"bits": [8, 13], "name": "FREE_COUNT_GDS"},
8876 {"bits": [16, 21], "name": "FREE_COUNT_PFP"}
8881 {"bits": [0, 19], "name": "IB1_OFFSET"}
8884 "CP_IB1_PREAMBLE_BEGIN": {
8886 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"}
8889 "CP_IB1_PREAMBLE_END": {
8891 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"}
8896 {"bits": [0, 19], "name": "IB2_OFFSET"}
8899 "CP_IB2_PREAMBLE_BEGIN": {
8901 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
8904 "CP_IB2_PREAMBLE_END": {
8906 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
8909 "CP_INT_STAT_DEBUG": {
8911 {"bits": [14, 14], "name": "CP_ECC_ERROR_INT_ASSERTED"},
8912 {"bits": [17, 17], "name": "WRM_POLL_TIMEOUT_INT_ASSERTED"},
8913 {"bits": [19, 19], "name": "CNTX_BUSY_INT_ASSERTED"},
8914 {"bits": [20, 20], "name": "CNTX_EMPTY_INT_ASSERTED"},
8915 {"bits": [22, 22], "name": "PRIV_INSTR_INT_ASSERTED"},
8916 {"bits": [23, 23], "name": "PRIV_REG_INT_ASSERTED"},
8917 {"bits": [24, 24], "name": "OPCODE_ERROR_INT_ASSERTED"},
8918 {"bits": [26, 26], "name": "TIME_STAMP_INT_ASSERTED"},
8919 {"bits": [27, 27], "name": "RESERVED_BIT_ERROR_INT_ASSERTED"},
8920 {"bits": [29, 29], "name": "GENERIC2_INT_ASSERTED"},
8921 {"bits": [30, 30], "name": "GENERIC1_INT_ASSERTED"},
8922 {"bits": [31, 31], "name": "GENERIC0_INT_ASSERTED"}
8925 "CP_MC_PACK_DELAY_CNT": {
8927 {"bits": [0, 4], "name": "PACK_DELAY_CNT"}
8932 {"bits": [0, 9], "name": "MEQ_CNT"}
8937 {"bits": [0, 9], "name": "MEQ_RPTR"},
8938 {"bits": [16, 25], "name": "MEQ_WPTR"}
8941 "CP_MEQ_THRESHOLDS": {
8943 {"bits": [0, 7], "name": "MEQ1_START"},
8944 {"bits": [8, 15], "name": "MEQ2_START"}
8949 {"bits": [4, 4], "name": "CE_INVALIDATE_ICACHE"},
8950 {"bits": [6, 6], "name": "PFP_INVALIDATE_ICACHE"},
8951 {"bits": [8, 8], "name": "ME_INVALIDATE_ICACHE"},
8952 {"bits": [24, 24], "name": "CE_HALT"},
8953 {"bits": [25, 25], "name": "CE_STEP"},
8954 {"bits": [26, 26], "name": "PFP_HALT"},
8955 {"bits": [27, 27], "name": "PFP_STEP"},
8956 {"bits": [28, 28], "name": "ME_HALT"},
8957 {"bits": [29, 29], "name": "ME_STEP"}
8960 "CP_ME_HEADER_DUMP": {
8962 {"bits": [0, 31], "name": "ME_HEADER_DUMP"}
8965 "CP_ME_MC_RADDR_HI": {
8967 {"bits": [0, 7], "name": "ME_MC_RADDR_HI"}
8970 "CP_ME_MC_RADDR_LO": {
8972 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"},
8973 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
8976 "CP_ME_MC_WADDR_HI": {
8978 {"bits": [0, 7], "name": "ME_MC_WADDR_HI"}
8981 "CP_ME_MC_WADDR_LO": {
8983 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"},
8984 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
8987 "CP_ME_MC_WDATA_HI": {
8989 {"bits": [0, 31], "name": "ME_MC_WDATA_HI"}
8992 "CP_ME_MC_WDATA_LO": {
8994 {"bits": [0, 31], "name": "ME_MC_WDATA_LO"}
8997 "CP_ME_PREEMPTION": {
8999 {"bits": [0, 0], "name": "ME_CNTXSW_PREEMPTION"}
9002 "CP_NUM_PRIM_NEEDED_COUNT0_HI": {
9004 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_HI"}
9007 "CP_NUM_PRIM_NEEDED_COUNT0_LO": {
9009 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_LO"}
9012 "CP_NUM_PRIM_NEEDED_COUNT1_HI": {
9014 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_HI"}
9017 "CP_NUM_PRIM_NEEDED_COUNT1_LO": {
9019 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_LO"}
9022 "CP_NUM_PRIM_NEEDED_COUNT2_HI": {
9024 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_HI"}
9027 "CP_NUM_PRIM_NEEDED_COUNT2_LO": {
9029 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_LO"}
9032 "CP_NUM_PRIM_NEEDED_COUNT3_HI": {
9034 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_HI"}
9037 "CP_NUM_PRIM_NEEDED_COUNT3_LO": {
9039 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_LO"}
9042 "CP_NUM_PRIM_WRITTEN_COUNT0_HI": {
9044 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_HI"}
9047 "CP_NUM_PRIM_WRITTEN_COUNT0_LO": {
9049 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_LO"}
9052 "CP_NUM_PRIM_WRITTEN_COUNT1_HI": {
9054 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_HI"}
9057 "CP_NUM_PRIM_WRITTEN_COUNT1_LO": {
9059 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_LO"}
9062 "CP_NUM_PRIM_WRITTEN_COUNT2_HI": {
9064 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_HI"}
9067 "CP_NUM_PRIM_WRITTEN_COUNT2_LO": {
9069 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_LO"}
9072 "CP_NUM_PRIM_WRITTEN_COUNT3_HI": {
9074 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_HI"}
9077 "CP_NUM_PRIM_WRITTEN_COUNT3_LO": {
9079 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_LO"}
9082 "CP_PA_CINVOC_COUNT_HI": {
9084 {"bits": [0, 31], "name": "CINVOC_COUNT_HI"}
9087 "CP_PA_CINVOC_COUNT_LO": {
9089 {"bits": [0, 31], "name": "CINVOC_COUNT_LO"}
9092 "CP_PA_CPRIM_COUNT_HI": {
9094 {"bits": [0, 31], "name": "CPRIM_COUNT_HI"}
9097 "CP_PA_CPRIM_COUNT_LO": {
9099 {"bits": [0, 31], "name": "CPRIM_COUNT_LO"}
9102 "CP_PERFMON_CNTL": {
9104 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
9105 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
9106 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
9107 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
9110 "CP_PERFMON_CNTX_CNTL": {
9112 {"bits": [31, 31], "name": "PERFMON_ENABLE"}
9115 "CP_PFP_HEADER_DUMP": {
9117 {"bits": [0, 31], "name": "PFP_HEADER_DUMP"}
9120 "CP_PFP_IB_CONTROL": {
9122 {"bits": [0, 0], "name": "IB_EN"}
9125 "CP_PFP_LOAD_CONTROL": {
9127 {"bits": [0, 0], "name": "CONFIG_REG_EN"},
9128 {"bits": [1, 1], "name": "CNTX_REG_EN"},
9129 {"bits": [15, 15], "name": "UCONFIG_REG_EN"},
9130 {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
9131 {"bits": [24, 24], "name": "SH_CS_REG_EN"}
9134 "CP_PIPE_STATS_ADDR_HI": {
9136 {"bits": [0, 31], "name": "PIPE_STATS_ADDR_HI"}
9139 "CP_PIPE_STATS_ADDR_LO": {
9141 {"bits": [0, 1], "name": "PIPE_STATS_ADDR_SWAP"},
9142 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
9145 "CP_QUEUE_THRESHOLDS": {
9147 {"bits": [0, 5], "name": "ROQ_IB1_START"},
9148 {"bits": [8, 13], "name": "ROQ_IB2_START"}
9153 {"bits": [0, 19], "name": "RB_RPTR"}
9158 {"bits": [0, 19], "name": "RB_OFFSET"}
9161 "CP_RB_WPTR_DELAY": {
9163 {"bits": [0, 27], "name": "PRE_WRITE_TIMER"},
9164 {"bits": [28, 31], "name": "PRE_WRITE_LIMIT"}
9167 "CP_RB_WPTR_POLL_CNTL": {
9169 {"bits": [0, 15], "name": "POLL_FREQUENCY"},
9170 {"bits": [16, 31], "name": "IDLE_POLL_COUNT"}
9175 {"bits": [0, 1], "name": "RINGID"}
9178 "CP_ROQ1_THRESHOLDS": {
9180 {"bits": [0, 7], "name": "RB1_START"},
9181 {"bits": [8, 15], "name": "RB2_START"},
9182 {"bits": [16, 23], "name": "R0_IB1_START"},
9183 {"bits": [24, 31], "name": "R1_IB1_START"}
9188 {"bits": [0, 10], "name": "ROQ_CNT_IB2"}
9191 "CP_ROQ2_THRESHOLDS": {
9193 {"bits": [0, 7], "name": "R2_IB1_START"},
9194 {"bits": [8, 15], "name": "R0_IB2_START"},
9195 {"bits": [16, 23], "name": "R1_IB2_START"},
9196 {"bits": [24, 31], "name": "R2_IB2_START"}
9201 {"bits": [0, 10], "name": "ROQ_CNT_RING"},
9202 {"bits": [16, 26], "name": "ROQ_CNT_IB1"}
9205 "CP_ROQ_IB1_STAT": {
9207 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT1"},
9208 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT1"}
9211 "CP_ROQ_IB2_STAT": {
9213 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT2"},
9214 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT2"}
9219 {"bits": [0, 9], "name": "ROQ_RPTR_PRIMARY"},
9220 {"bits": [16, 25], "name": "ROQ_WPTR_PRIMARY"}
9223 "CP_SCRATCH_DATA": {
9225 {"bits": [0, 31], "name": "SCRATCH_DATA"}
9228 "CP_SCRATCH_INDEX": {
9230 {"bits": [0, 7], "name": "SCRATCH_INDEX"}
9233 "CP_SC_PSINVOC_COUNT0_HI": {
9235 {"bits": [0, 31], "name": "PSINVOC_COUNT0_HI"}
9238 "CP_SC_PSINVOC_COUNT0_LO": {
9240 {"bits": [0, 31], "name": "PSINVOC_COUNT0_LO"}
9243 "CP_SC_PSINVOC_COUNT1_HI": {
9245 {"bits": [0, 31], "name": "OBSOLETE"}
9248 "CP_SEM_WAIT_TIMER": {
9250 {"bits": [0, 31], "name": "SEM_WAIT_TIMER"}
9253 "CP_SIG_SEM_ADDR_HI": {
9255 {"bits": [0, 7], "name": "SEM_ADDR_HI"},
9256 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
9257 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
9258 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
9259 {"bits": [29, 31], "name": "SEM_SELECT"}
9262 "CP_SIG_SEM_ADDR_LO": {
9264 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"},
9265 {"bits": [3, 31], "name": "SEM_ADDR_LO"}
9268 "CP_STALLED_STAT1": {
9270 {"bits": [0, 0], "name": "RBIU_TO_DMA_NOT_RDY_TO_RCV"},
9271 {"bits": [2, 2], "name": "RBIU_TO_SEM_NOT_RDY_TO_RCV"},
9272 {"bits": [4, 4], "name": "RBIU_TO_MEMWR_NOT_RDY_TO_RCV"},
9273 {"bits": [10, 10], "name": "ME_HAS_ACTIVE_CE_BUFFER_FLAG"},
9274 {"bits": [11, 11], "name": "ME_HAS_ACTIVE_DE_BUFFER_FLAG"},
9275 {"bits": [12, 12], "name": "ME_STALLED_ON_TC_WR_CONFIRM"},
9276 {"bits": [13, 13], "name": "ME_STALLED_ON_ATOMIC_RTN_DATA"},
9277 {"bits": [14, 14], "name": "ME_WAITING_ON_MC_READ_DATA"},
9278 {"bits": [15, 15], "name": "ME_WAITING_ON_REG_READ_DATA"},
9279 {"bits": [16, 16], "name": "MIU_WAITING_ON_RDREQ_FREE"},
9280 {"bits": [17, 17], "name": "MIU_WAITING_ON_WRREQ_FREE"},
9281 {"bits": [23, 23], "name": "RCIU_WAITING_ON_GDS_FREE"},
9282 {"bits": [24, 24], "name": "RCIU_WAITING_ON_GRBM_FREE"},
9283 {"bits": [25, 25], "name": "RCIU_WAITING_ON_VGT_FREE"},
9284 {"bits": [26, 26], "name": "RCIU_STALLED_ON_ME_READ"},
9285 {"bits": [27, 27], "name": "RCIU_STALLED_ON_DMA_READ"},
9286 {"bits": [28, 28], "name": "RCIU_HALTED_BY_REG_VIOLATION"},
9287 {"bits": [28, 28], "name": "RCIU_STALLED_ON_APPEND_READ"}
9290 "CP_STALLED_STAT2": {
9292 {"bits": [0, 0], "name": "PFP_TO_CSF_NOT_RDY_TO_RCV"},
9293 {"bits": [1, 1], "name": "PFP_TO_MEQ_NOT_RDY_TO_RCV"},
9294 {"bits": [2, 2], "name": "PFP_TO_RCIU_NOT_RDY_TO_RCV"},
9295 {"bits": [4, 4], "name": "PFP_TO_VGT_WRITES_PENDING"},
9296 {"bits": [5, 5], "name": "PFP_RCIU_READ_PENDING"},
9297 {"bits": [6, 6], "name": "PFP_MIU_READ_PENDING"},
9298 {"bits": [7, 7], "name": "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV"},
9299 {"bits": [8, 8], "name": "PFP_WAITING_ON_BUFFER_DATA"},
9300 {"bits": [9, 9], "name": "ME_WAIT_ON_CE_COUNTER"},
9301 {"bits": [10, 10], "name": "ME_WAIT_ON_AVAIL_BUFFER"},
9302 {"bits": [11, 11], "name": "GFX_CNTX_NOT_AVAIL_TO_ME"},
9303 {"bits": [12, 12], "name": "ME_RCIU_NOT_RDY_TO_RCV"},
9304 {"bits": [13, 13], "name": "ME_TO_CONST_NOT_RDY_TO_RCV"},
9305 {"bits": [14, 14], "name": "ME_WAITING_DATA_FROM_PFP"},
9306 {"bits": [15, 15], "name": "ME_WAITING_ON_PARTIAL_FLUSH"},
9307 {"bits": [16, 16], "name": "MEQ_TO_ME_NOT_RDY_TO_RCV"},
9308 {"bits": [17, 17], "name": "STQ_TO_ME_NOT_RDY_TO_RCV"},
9309 {"bits": [18, 18], "name": "ME_WAITING_DATA_FROM_STQ"},
9310 {"bits": [19, 19], "name": "PFP_STALLED_ON_TC_WR_CONFIRM"},
9311 {"bits": [20, 20], "name": "PFP_STALLED_ON_ATOMIC_RTN_DATA"},
9312 {"bits": [21, 21], "name": "EOPD_FIFO_NEEDS_SC_EOP_DONE"},
9313 {"bits": [22, 22], "name": "EOPD_FIFO_NEEDS_WR_CONFIRM"},
9314 {"bits": [23, 23], "name": "STRMO_WR_OF_PRIM_DATA_PENDING"},
9315 {"bits": [24, 24], "name": "PIPE_STATS_WR_DATA_PENDING"},
9316 {"bits": [25, 25], "name": "APPEND_RDY_WAIT_ON_CS_DONE"},
9317 {"bits": [26, 26], "name": "APPEND_RDY_WAIT_ON_PS_DONE"},
9318 {"bits": [27, 27], "name": "APPEND_WAIT_ON_WR_CONFIRM"},
9319 {"bits": [28, 28], "name": "APPEND_ACTIVE_PARTITION"},
9320 {"bits": [29, 29], "name": "APPEND_WAITING_TO_SEND_MEMWRITE"},
9321 {"bits": [30, 30], "name": "SURF_SYNC_NEEDS_IDLE_CNTXS"},
9322 {"bits": [31, 31], "name": "SURF_SYNC_NEEDS_ALL_CLEAN"}
9325 "CP_STALLED_STAT3": {
9327 {"bits": [0, 0], "name": "CE_TO_CSF_NOT_RDY_TO_RCV"},
9328 {"bits": [1, 1], "name": "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV"},
9329 {"bits": [2, 2], "name": "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER"},
9330 {"bits": [3, 3], "name": "CE_TO_RAM_INIT_NOT_RDY"},
9331 {"bits": [4, 4], "name": "CE_TO_RAM_DUMP_NOT_RDY"},
9332 {"bits": [5, 5], "name": "CE_TO_RAM_WRITE_NOT_RDY"},
9333 {"bits": [6, 6], "name": "CE_TO_INC_FIFO_NOT_RDY_TO_RCV"},
9334 {"bits": [7, 7], "name": "CE_TO_WR_FIFO_NOT_RDY_TO_RCV"},
9335 {"bits": [8, 8], "name": "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV"},
9336 {"bits": [10, 10], "name": "CE_WAITING_ON_BUFFER_DATA"},
9337 {"bits": [11, 11], "name": "CE_WAITING_ON_CE_BUFFER_FLAG"},
9338 {"bits": [12, 12], "name": "CE_WAITING_ON_DE_COUNTER"},
9339 {"bits": [13, 13], "name": "CE_WAITING_ON_DE_COUNTER_UNDERFLOW"},
9340 {"bits": [14, 14], "name": "TCIU_WAITING_ON_FREE"},
9341 {"bits": [15, 15], "name": "TCIU_WAITING_ON_TAGS"}
9346 {"bits": [7, 7], "name": "MIU_RDREQ_BUSY"},
9347 {"bits": [8, 8], "name": "MIU_WRREQ_BUSY"},
9348 {"bits": [9, 9], "name": "ROQ_RING_BUSY"},
9349 {"bits": [10, 10], "name": "ROQ_INDIRECT1_BUSY"},
9350 {"bits": [11, 11], "name": "ROQ_INDIRECT2_BUSY"},
9351 {"bits": [12, 12], "name": "ROQ_STATE_BUSY"},
9352 {"bits": [13, 13], "name": "DC_BUSY"},
9353 {"bits": [15, 15], "name": "PFP_BUSY"},
9354 {"bits": [16, 16], "name": "MEQ_BUSY"},
9355 {"bits": [17, 17], "name": "ME_BUSY"},
9356 {"bits": [18, 18], "name": "QUERY_BUSY"},
9357 {"bits": [19, 19], "name": "SEMAPHORE_BUSY"},
9358 {"bits": [20, 20], "name": "INTERRUPT_BUSY"},
9359 {"bits": [21, 21], "name": "SURFACE_SYNC_BUSY"},
9360 {"bits": [22, 22], "name": "DMA_BUSY"},
9361 {"bits": [23, 23], "name": "RCIU_BUSY"},
9362 {"bits": [24, 24], "name": "SCRATCH_RAM_BUSY"},
9363 {"bits": [25, 25], "name": "CPC_CPG_BUSY"},
9364 {"bits": [26, 26], "name": "CE_BUSY"},
9365 {"bits": [27, 27], "name": "TCIU_BUSY"},
9366 {"bits": [28, 28], "name": "ROQ_CE_RING_BUSY"},
9367 {"bits": [29, 29], "name": "ROQ_CE_INDIRECT1_BUSY"},
9368 {"bits": [30, 30], "name": "ROQ_CE_INDIRECT2_BUSY"},
9369 {"bits": [31, 31], "name": "CP_BUSY"}
9374 {"bits": [0, 8], "name": "STQ_CNT"}
9379 {"bits": [0, 9], "name": "STQ_RPTR"}
9382 "CP_STQ_THRESHOLDS": {
9384 {"bits": [0, 7], "name": "STQ0_START"},
9385 {"bits": [8, 15], "name": "STQ1_START"},
9386 {"bits": [16, 23], "name": "STQ2_START"}
9389 "CP_STREAM_OUT_ADDR_HI": {
9391 {"bits": [0, 31], "name": "STREAM_OUT_ADDR_HI"}
9394 "CP_STREAM_OUT_ADDR_LO": {
9396 {"bits": [0, 1], "name": "STREAM_OUT_ADDR_SWAP"},
9397 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"}
9400 "CP_STRMOUT_CNTL": {
9402 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"}
9407 {"bits": [0, 7], "name": "ST_BASE_HI"}
9412 {"bits": [2, 31], "name": "ST_BASE_LO"}
9417 {"bits": [0, 19], "name": "ST_BUFSZ"}
9420 "CP_VGT_CSINVOC_COUNT_HI": {
9422 {"bits": [0, 31], "name": "CSINVOC_COUNT_HI"}
9425 "CP_VGT_CSINVOC_COUNT_LO": {
9427 {"bits": [0, 31], "name": "CSINVOC_COUNT_LO"}
9430 "CP_VGT_DSINVOC_COUNT_HI": {
9432 {"bits": [0, 31], "name": "DSINVOC_COUNT_HI"}
9435 "CP_VGT_DSINVOC_COUNT_LO": {
9437 {"bits": [0, 31], "name": "DSINVOC_COUNT_LO"}
9440 "CP_VGT_GSINVOC_COUNT_HI": {
9442 {"bits": [0, 31], "name": "GSINVOC_COUNT_HI"}
9445 "CP_VGT_GSINVOC_COUNT_LO": {
9447 {"bits": [0, 31], "name": "GSINVOC_COUNT_LO"}
9450 "CP_VGT_GSPRIM_COUNT_HI": {
9452 {"bits": [0, 31], "name": "GSPRIM_COUNT_HI"}
9455 "CP_VGT_GSPRIM_COUNT_LO": {
9457 {"bits": [0, 31], "name": "GSPRIM_COUNT_LO"}
9460 "CP_VGT_HSINVOC_COUNT_HI": {
9462 {"bits": [0, 31], "name": "HSINVOC_COUNT_HI"}
9465 "CP_VGT_HSINVOC_COUNT_LO": {
9467 {"bits": [0, 31], "name": "HSINVOC_COUNT_LO"}
9470 "CP_VGT_IAPRIM_COUNT_HI": {
9472 {"bits": [0, 31], "name": "IAPRIM_COUNT_HI"}
9475 "CP_VGT_IAPRIM_COUNT_LO": {
9477 {"bits": [0, 31], "name": "IAPRIM_COUNT_LO"}
9480 "CP_VGT_IAVERT_COUNT_HI": {
9482 {"bits": [0, 31], "name": "IAVERT_COUNT_HI"}
9485 "CP_VGT_IAVERT_COUNT_LO": {
9487 {"bits": [0, 31], "name": "IAVERT_COUNT_LO"}
9490 "CP_VGT_VSINVOC_COUNT_HI": {
9492 {"bits": [0, 31], "name": "VSINVOC_COUNT_HI"}
9495 "CP_VGT_VSINVOC_COUNT_LO": {
9497 {"bits": [0, 31], "name": "VSINVOC_COUNT_LO"}
9502 {"bits": [0, 3], "name": "VMID"}
9505 "CP_WAIT_REG_MEM_TIMEOUT": {
9507 {"bits": [0, 31], "name": "WAIT_REG_MEM_TIMEOUT"}
9512 {"bits": [0, 2], "name": "SRC_STATE_ID"}
9515 "DB_ALPHA_TO_MASK": {
9517 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
9518 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
9519 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
9520 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
9521 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
9522 {"bits": [16, 16], "name": "OFFSET_ROUND"}
9525 "DB_COUNT_CONTROL": {
9527 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"},
9528 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
9529 {"bits": [4, 6], "name": "SAMPLE_RATE"},
9530 {"bits": [8, 11], "name": "ZPASS_ENABLE"},
9531 {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
9532 {"bits": [16, 19], "name": "SFAIL_ENABLE"},
9533 {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
9534 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
9535 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
9538 "DB_DEPTH_BOUNDS_MAX": {
9540 {"bits": [0, 31], "name": "MAX"}
9543 "DB_DEPTH_BOUNDS_MIN": {
9545 {"bits": [0, 31], "name": "MIN"}
9550 {"bits": [0, 31], "name": "DEPTH_CLEAR"}
9553 "DB_DEPTH_CONTROL": {
9555 {"bits": [0, 0], "name": "STENCIL_ENABLE"},
9556 {"bits": [1, 1], "name": "Z_ENABLE"},
9557 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
9558 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
9559 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
9560 {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
9561 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
9562 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
9563 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
9564 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
9569 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"},
9570 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
9571 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
9572 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"},
9573 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"},
9574 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"},
9575 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"}
9580 {"bits": [0, 10], "name": "PITCH_TILE_MAX"},
9581 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"}
9586 {"bits": [0, 21], "name": "SLICE_TILE_MAX"}
9591 {"bits": [0, 10], "name": "SLICE_START"},
9592 {"bits": [13, 23], "name": "SLICE_MAX"},
9593 {"bits": [24, 24], "name": "Z_READ_ONLY"},
9594 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}
9599 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
9600 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
9601 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
9602 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
9603 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
9604 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
9605 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
9606 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
9607 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
9608 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
9609 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
9610 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
9613 "DB_HTILE_SURFACE": {
9615 {"bits": [0, 0], "name": "LINEAR"},
9616 {"bits": [1, 1], "name": "FULL_CACHE"},
9617 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"},
9618 {"bits": [3, 3], "name": "PRELOAD"},
9619 {"bits": [4, 9], "name": "PREFETCH_WIDTH"},
9620 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"},
9621 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}
9624 "DB_PRELOAD_CONTROL": {
9626 {"bits": [0, 7], "name": "START_X"},
9627 {"bits": [8, 15], "name": "START_Y"},
9628 {"bits": [16, 23], "name": "MAX_X"},
9629 {"bits": [24, 31], "name": "MAX_Y"}
9632 "DB_RENDER_CONTROL": {
9634 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
9635 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
9636 {"bits": [2, 2], "name": "DEPTH_COPY"},
9637 {"bits": [3, 3], "name": "STENCIL_COPY"},
9638 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
9639 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
9640 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
9641 {"bits": [7, 7], "name": "COPY_CENTROID"},
9642 {"bits": [8, 11], "name": "COPY_SAMPLE"}
9645 "DB_RENDER_OVERRIDE": {
9647 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
9648 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
9649 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
9650 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
9651 {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
9652 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
9653 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
9654 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
9655 {"bits": [11, 11], "name": "FORCE_Z_READ"},
9656 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
9657 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
9658 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"},
9659 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
9660 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
9661 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
9662 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
9663 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
9664 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
9665 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
9666 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
9667 {"bits": [29, 29], "name": "FORCE_Z_VALID"},
9668 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
9669 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
9672 "DB_RENDER_OVERRIDE2": {
9674 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
9675 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
9676 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
9677 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
9678 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
9679 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
9680 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
9681 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
9682 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
9683 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
9684 {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
9685 {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
9686 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
9687 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
9688 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}
9691 "DB_SHADER_CONTROL": {
9693 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
9694 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
9695 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
9696 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
9697 {"bits": [6, 6], "name": "KILL_ENABLE"},
9698 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
9699 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
9700 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
9701 {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
9702 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
9703 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
9704 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}
9707 "DB_SRESULTS_COMPARE_STATE0": {
9709 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
9710 {"bits": [4, 11], "name": "COMPAREVALUE0"},
9711 {"bits": [12, 19], "name": "COMPAREMASK0"},
9712 {"bits": [24, 24], "name": "ENABLE0"}
9715 "DB_SRESULTS_COMPARE_STATE1": {
9717 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
9718 {"bits": [4, 11], "name": "COMPAREVALUE1"},
9719 {"bits": [12, 19], "name": "COMPAREMASK1"},
9720 {"bits": [24, 24], "name": "ENABLE1"}
9723 "DB_STENCILREFMASK": {
9725 {"bits": [0, 7], "name": "STENCILTESTVAL"},
9726 {"bits": [8, 15], "name": "STENCILMASK"},
9727 {"bits": [16, 23], "name": "STENCILWRITEMASK"},
9728 {"bits": [24, 31], "name": "STENCILOPVAL"}
9731 "DB_STENCILREFMASK_BF": {
9733 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
9734 {"bits": [8, 15], "name": "STENCILMASK_BF"},
9735 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
9736 {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
9739 "DB_STENCIL_CLEAR": {
9741 {"bits": [0, 7], "name": "CLEAR"}
9744 "DB_STENCIL_CONTROL": {
9746 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
9747 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
9748 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
9749 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
9750 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
9751 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
9754 "DB_STENCIL_INFO": {
9756 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
9757 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
9758 {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
9759 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
9760 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
9765 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
9766 {"bits": [2, 3], "name": "NUM_SAMPLES"},
9767 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
9768 {"bits": [20, 22], "name": "TILE_MODE_INDEX"},
9769 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
9770 {"bits": [28, 28], "name": "READ_SIZE"},
9771 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
9772 {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
9777 {"bits": [0, 31], "name": "DEBUG_DATA"}
9782 {"bits": [0, 17], "name": "DEBUG_INDEX"}
9787 {"bits": [0, 2], "name": "NUM_PIPES"},
9788 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"},
9789 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"},
9790 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"},
9791 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"},
9792 {"bits": [20, 22], "name": "NUM_GPUS"},
9793 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"},
9794 {"bits": [28, 29], "name": "ROW_SIZE"},
9795 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}
9800 {"bits": [0, 1], "enum_ref": "GB_TILE_MODE0__MICRO_TILE_MODE", "name": "MICRO_TILE_MODE"},
9801 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
9802 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
9803 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
9804 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
9805 {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
9810 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"},
9811 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"},
9812 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"},
9813 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"},
9814 {"bits": [25, 26], "name": "SAMPLE_SPLIT"}
9819 {"bits": [0, 7], "name": "READ_TIMEOUT"}
9824 {"bits": [1, 1], "name": "IGNORE_RDY"},
9825 {"bits": [5, 5], "name": "IGNORE_FAO"},
9826 {"bits": [6, 6], "name": "DISABLE_READ_TIMEOUT"},
9827 {"bits": [7, 7], "name": "SNAPSHOT_FREE_CNTRS"},
9828 {"bits": [8, 11], "name": "HYSTERESIS_GUI_ACTIVE"},
9829 {"bits": [12, 12], "name": "GFX_CLOCK_DOMAIN_OVERRIDE"}
9832 "GRBM_DEBUG_CNTL": {
9834 {"bits": [0, 5], "name": "GRBM_DEBUG_INDEX"}
9837 "GRBM_DEBUG_SNAPSHOT": {
9839 {"bits": [0, 0], "name": "CPF_RDY"},
9840 {"bits": [1, 1], "name": "CPG_RDY"},
9841 {"bits": [1, 1], "name": "SRBM_RDY"},
9842 {"bits": [3, 3], "name": "WD_ME0PIPE0_RDY"},
9843 {"bits": [4, 4], "name": "WD_ME0PIPE1_RDY"},
9844 {"bits": [6, 6], "name": "SE0SPI_ME0PIPE0_RDY0"},
9845 {"bits": [7, 7], "name": "SE0SPI_ME0PIPE1_RDY0"},
9846 {"bits": [8, 8], "name": "SE1SPI_ME0PIPE0_RDY0"},
9847 {"bits": [9, 9], "name": "GDS_RDY"},
9848 {"bits": [9, 9], "name": "SE1SPI_ME0PIPE1_RDY0"},
9849 {"bits": [10, 10], "name": "SE2SPI_ME0PIPE0_RDY0"},
9850 {"bits": [11, 11], "name": "SE2SPI_ME0PIPE1_RDY0"},
9851 {"bits": [12, 12], "name": "SE3SPI_ME0PIPE0_RDY0"},
9852 {"bits": [13, 13], "name": "SE3SPI_ME0PIPE1_RDY0"},
9853 {"bits": [14, 14], "name": "SE0SPI_ME0PIPE0_RDY1"},
9854 {"bits": [15, 15], "name": "SE0SPI_ME0PIPE1_RDY1"},
9855 {"bits": [16, 16], "name": "SE1SPI_ME0PIPE0_RDY1"},
9856 {"bits": [17, 17], "name": "SE1SPI_ME0PIPE1_RDY1"},
9857 {"bits": [18, 18], "name": "SE2SPI_ME0PIPE0_RDY1"},
9858 {"bits": [19, 19], "name": "SE2SPI_ME0PIPE1_RDY1"},
9859 {"bits": [20, 20], "name": "SE3SPI_ME0PIPE0_RDY1"},
9860 {"bits": [21, 21], "name": "SE3SPI_ME0PIPE1_RDY1"}
9863 "GRBM_GFX_CLKEN_CNTL": {
9865 {"bits": [0, 3], "name": "PREFIX_DELAY_CNT"},
9866 {"bits": [8, 12], "name": "POST_DELAY_CNT"}
9871 {"bits": [0, 7], "name": "INSTANCE_INDEX"},
9872 {"bits": [8, 15], "name": "SH_INDEX"},
9873 {"bits": [16, 23], "name": "SE_INDEX"},
9874 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"},
9875 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
9876 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
9881 {"bits": [0, 0], "name": "RDERR_INT_ENABLE"},
9882 {"bits": [19, 19], "name": "GUI_IDLE_INT_ENABLE"}
9885 "GRBM_PERFCOUNTER0_HI": {
9887 {"bits": [0, 31], "name": "PERFCOUNTER_HI"}
9890 "GRBM_PERFCOUNTER0_LO": {
9892 {"bits": [0, 31], "name": "PERFCOUNTER_LO"}
9895 "GRBM_PERFCOUNTER0_SELECT": {
9897 {"bits": [0, 5], "name": "PERF_SEL"},
9898 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
9899 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
9900 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"},
9901 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
9902 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
9903 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
9904 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
9905 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
9906 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
9907 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
9908 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
9909 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
9910 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"},
9911 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
9912 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
9913 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
9914 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"},
9915 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}
9920 {"bits": [0, 3], "name": "REQ_TYPE"},
9921 {"bits": [4, 7], "name": "RSP_TYPE"}
9924 "GRBM_READ_ERROR": {
9926 {"bits": [2, 17], "name": "READ_ADDRESS"},
9927 {"bits": [20, 21], "name": "READ_PIPEID"},
9928 {"bits": [22, 23], "name": "READ_MEID"},
9929 {"bits": [31, 31], "name": "READ_ERROR"}
9932 "GRBM_SCRATCH_REG0": {
9934 {"bits": [0, 31], "name": "SCRATCH_REG0"}
9937 "GRBM_SCRATCH_REG1": {
9939 {"bits": [0, 31], "name": "SCRATCH_REG1"}
9942 "GRBM_SCRATCH_REG2": {
9944 {"bits": [0, 31], "name": "SCRATCH_REG2"}
9947 "GRBM_SCRATCH_REG3": {
9949 {"bits": [0, 31], "name": "SCRATCH_REG3"}
9952 "GRBM_SCRATCH_REG4": {
9954 {"bits": [0, 31], "name": "SCRATCH_REG4"}
9957 "GRBM_SCRATCH_REG5": {
9959 {"bits": [0, 31], "name": "SCRATCH_REG5"}
9962 "GRBM_SCRATCH_REG6": {
9964 {"bits": [0, 31], "name": "SCRATCH_REG6"}
9967 "GRBM_SCRATCH_REG7": {
9969 {"bits": [0, 31], "name": "SCRATCH_REG7"}
9972 "GRBM_SE0_PERFCOUNTER_SELECT": {
9974 {"bits": [0, 5], "name": "PERF_SEL"},
9975 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
9976 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
9977 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
9978 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
9979 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
9980 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
9981 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
9982 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
9983 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"},
9984 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
9985 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}
9990 {"bits": [0, 5], "name": "SKEW_TOP_THRESHOLD"},
9991 {"bits": [6, 11], "name": "SKEW_COUNT"}
9994 "GRBM_SOFT_RESET": {
9996 {"bits": [0, 0], "name": "SOFT_RESET_CP"},
9997 {"bits": [2, 2], "name": "SOFT_RESET_RLC"},
9998 {"bits": [16, 16], "name": "SOFT_RESET_GFX"},
9999 {"bits": [17, 17], "name": "SOFT_RESET_CPF"},
10000 {"bits": [18, 18], "name": "SOFT_RESET_CPC"},
10001 {"bits": [19, 19], "name": "SOFT_RESET_CPG"}
10006 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
10007 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"},
10008 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
10009 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
10010 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
10011 {"bits": [12, 12], "name": "DB_CLEAN"},
10012 {"bits": [13, 13], "name": "CB_CLEAN"},
10013 {"bits": [14, 14], "name": "TA_BUSY"},
10014 {"bits": [15, 15], "name": "GDS_BUSY"},
10015 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"},
10016 {"bits": [17, 17], "name": "VGT_BUSY"},
10017 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"},
10018 {"bits": [19, 19], "name": "IA_BUSY"},
10019 {"bits": [20, 20], "name": "SX_BUSY"},
10020 {"bits": [21, 21], "name": "WD_BUSY"},
10021 {"bits": [22, 22], "name": "SPI_BUSY"},
10022 {"bits": [23, 23], "name": "BCI_BUSY"},
10023 {"bits": [24, 24], "name": "SC_BUSY"},
10024 {"bits": [25, 25], "name": "PA_BUSY"},
10025 {"bits": [26, 26], "name": "DB_BUSY"},
10026 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
10027 {"bits": [29, 29], "name": "CP_BUSY"},
10028 {"bits": [30, 30], "name": "CB_BUSY"},
10029 {"bits": [31, 31], "name": "GUI_ACTIVE"}
10034 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
10035 {"bits": [0, 0], "name": "RLC_RQ_PENDING"},
10036 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
10037 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
10038 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
10039 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
10040 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
10041 {"bits": [8, 8], "name": "RLC_BUSY"},
10042 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
10043 {"bits": [9, 9], "name": "TC_BUSY"},
10044 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"},
10045 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"},
10046 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"},
10047 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"},
10048 {"bits": [28, 28], "name": "CPF_BUSY"},
10049 {"bits": [29, 29], "name": "CPC_BUSY"},
10050 {"bits": [30, 30], "name": "CPG_BUSY"}
10053 "GRBM_STATUS_SE0": {
10055 {"bits": [1, 1], "name": "DB_CLEAN"},
10056 {"bits": [2, 2], "name": "CB_CLEAN"},
10057 {"bits": [22, 22], "name": "BCI_BUSY"},
10058 {"bits": [23, 23], "name": "VGT_BUSY"},
10059 {"bits": [24, 24], "name": "PA_BUSY"},
10060 {"bits": [25, 25], "name": "TA_BUSY"},
10061 {"bits": [26, 26], "name": "SX_BUSY"},
10062 {"bits": [27, 27], "name": "SPI_BUSY"},
10063 {"bits": [29, 29], "name": "SC_BUSY"},
10064 {"bits": [30, 30], "name": "DB_BUSY"},
10065 {"bits": [31, 31], "name": "CB_BUSY"}
10068 "GRBM_WAIT_IDLE_CLOCKS": {
10070 {"bits": [0, 7], "name": "WAIT_IDLE_CLOCKS"}
10073 "IA_CNTL_STATUS": {
10075 {"bits": [0, 0], "name": "IA_BUSY"},
10076 {"bits": [1, 1], "name": "IA_DMA_BUSY"},
10077 {"bits": [2, 2], "name": "IA_DMA_REQ_BUSY"},
10078 {"bits": [3, 3], "name": "IA_GRP_BUSY"},
10079 {"bits": [4, 4], "name": "IA_ADC_BUSY"}
10084 {"bits": [0, 5], "name": "IA_DEBUG_INDX"},
10085 {"bits": [6, 6], "name": "IA_DEBUG_SEL_BUS_B"}
10090 {"bits": [0, 31], "name": "MISC"}
10093 "IA_MULTI_VGT_PARAM": {
10095 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"},
10096 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"},
10097 {"bits": [17, 17], "name": "SWITCH_ON_EOP"},
10098 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"},
10099 {"bits": [19, 19], "name": "SWITCH_ON_EOI"},
10100 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}
10103 "IA_PERFCOUNTER0_SELECT": {
10105 {"bits": [0, 7], "name": "PERF_SEL"},
10106 {"bits": [10, 19], "name": "PERF_SEL1"},
10107 {"bits": [20, 23], "name": "CNTR_MODE"},
10108 {"bits": [24, 27], "name": "PERF_MODE1"},
10109 {"bits": [28, 31], "name": "PERF_MODE"}
10112 "IA_PERFCOUNTER1_SELECT": {
10114 {"bits": [0, 7], "name": "PERF_SEL"},
10115 {"bits": [28, 31], "name": "PERF_MODE"}
10118 "IA_VMID_OVERRIDE": {
10120 {"bits": [0, 0], "name": "ENABLE"},
10121 {"bits": [1, 4], "name": "VMID"}
10124 "PA_CL_CLIP_CNTL": {
10126 {"bits": [0, 0], "name": "UCP_ENA_0"},
10127 {"bits": [1, 1], "name": "UCP_ENA_1"},
10128 {"bits": [2, 2], "name": "UCP_ENA_2"},
10129 {"bits": [3, 3], "name": "UCP_ENA_3"},
10130 {"bits": [4, 4], "name": "UCP_ENA_4"},
10131 {"bits": [5, 5], "name": "UCP_ENA_5"},
10132 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
10133 {"bits": [14, 15], "name": "PS_UCP_MODE"},
10134 {"bits": [16, 16], "name": "CLIP_DISABLE"},
10135 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
10136 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
10137 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
10138 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
10139 {"bits": [21, 21], "name": "VTX_KILL_OR"},
10140 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
10141 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
10142 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
10143 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
10144 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}
10147 "PA_CL_CNTL_STATUS": {
10149 {"bits": [31, 31], "name": "CL_BUSY"}
10154 {"bits": [0, 0], "name": "CLIP_VTX_REORDER_ENA"},
10155 {"bits": [1, 2], "name": "NUM_CLIP_SEQ"},
10156 {"bits": [3, 3], "name": "CLIPPED_PRIM_SEQ_STALL"},
10157 {"bits": [4, 4], "name": "VE_NAN_PROC_DISABLE"},
10158 {"bits": [5, 5], "name": "XTRA_DEBUG_REG_SEL"},
10159 {"bits": [28, 28], "name": "ECO_SPARE3"},
10160 {"bits": [29, 29], "name": "ECO_SPARE2"},
10161 {"bits": [30, 30], "name": "ECO_SPARE1"},
10162 {"bits": [31, 31], "name": "ECO_SPARE0"}
10165 "PA_CL_GB_HORZ_CLIP_ADJ": {
10167 {"bits": [0, 31], "name": "DATA_REGISTER"}
10170 "PA_CL_NANINF_CNTL": {
10172 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
10173 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
10174 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
10175 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
10176 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
10177 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
10178 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
10179 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
10180 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
10181 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
10182 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
10183 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
10184 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
10185 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
10186 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
10187 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
10190 "PA_CL_VPORT_XOFFSET": {
10192 {"bits": [0, 31], "name": "VPORT_XOFFSET"}
10195 "PA_CL_VPORT_XSCALE": {
10197 {"bits": [0, 31], "name": "VPORT_XSCALE"}
10200 "PA_CL_VPORT_YOFFSET": {
10202 {"bits": [0, 31], "name": "VPORT_YOFFSET"}
10205 "PA_CL_VPORT_YSCALE": {
10207 {"bits": [0, 31], "name": "VPORT_YSCALE"}
10210 "PA_CL_VPORT_ZOFFSET": {
10212 {"bits": [0, 31], "name": "VPORT_ZOFFSET"}
10215 "PA_CL_VPORT_ZSCALE": {
10217 {"bits": [0, 31], "name": "VPORT_ZSCALE"}
10220 "PA_CL_VS_OUT_CNTL": {
10222 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
10223 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
10224 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
10225 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
10226 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
10227 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
10228 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
10229 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
10230 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
10231 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
10232 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
10233 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
10234 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
10235 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
10236 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
10237 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
10238 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
10239 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
10240 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
10241 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
10242 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
10243 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
10244 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
10245 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
10246 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
10247 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}
10250 "PA_CL_VTE_CNTL": {
10252 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
10253 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
10254 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
10255 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
10256 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
10257 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
10258 {"bits": [8, 8], "name": "VTX_XY_FMT"},
10259 {"bits": [9, 9], "name": "VTX_Z_FMT"},
10260 {"bits": [10, 10], "name": "VTX_W0_FMT"},
10261 {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
10264 "PA_SC_AA_CONFIG": {
10266 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
10267 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
10268 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
10269 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
10270 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}
10273 "PA_SC_AA_MASK_X0Y0_X1Y0": {
10275 {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
10276 {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
10279 "PA_SC_AA_MASK_X0Y1_X1Y1": {
10281 {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
10282 {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
10285 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
10287 {"bits": [0, 3], "name": "S0_X"},
10288 {"bits": [4, 7], "name": "S0_Y"},
10289 {"bits": [8, 11], "name": "S1_X"},
10290 {"bits": [12, 15], "name": "S1_Y"},
10291 {"bits": [16, 19], "name": "S2_X"},
10292 {"bits": [20, 23], "name": "S2_Y"},
10293 {"bits": [24, 27], "name": "S3_X"},
10294 {"bits": [28, 31], "name": "S3_Y"}
10297 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
10299 {"bits": [0, 3], "name": "S4_X"},
10300 {"bits": [4, 7], "name": "S4_Y"},
10301 {"bits": [8, 11], "name": "S5_X"},
10302 {"bits": [12, 15], "name": "S5_Y"},
10303 {"bits": [16, 19], "name": "S6_X"},
10304 {"bits": [20, 23], "name": "S6_Y"},
10305 {"bits": [24, 27], "name": "S7_X"},
10306 {"bits": [28, 31], "name": "S7_Y"}
10309 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
10311 {"bits": [0, 3], "name": "S8_X"},
10312 {"bits": [4, 7], "name": "S8_Y"},
10313 {"bits": [8, 11], "name": "S9_X"},
10314 {"bits": [12, 15], "name": "S9_Y"},
10315 {"bits": [16, 19], "name": "S10_X"},
10316 {"bits": [20, 23], "name": "S10_Y"},
10317 {"bits": [24, 27], "name": "S11_X"},
10318 {"bits": [28, 31], "name": "S11_Y"}
10321 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
10323 {"bits": [0, 3], "name": "S12_X"},
10324 {"bits": [4, 7], "name": "S12_Y"},
10325 {"bits": [8, 11], "name": "S13_X"},
10326 {"bits": [12, 15], "name": "S13_Y"},
10327 {"bits": [16, 19], "name": "S14_X"},
10328 {"bits": [20, 23], "name": "S14_Y"},
10329 {"bits": [24, 27], "name": "S15_X"},
10330 {"bits": [28, 31], "name": "S15_Y"}
10333 "PA_SC_CENTROID_PRIORITY_0": {
10335 {"bits": [0, 3], "name": "DISTANCE_0"},
10336 {"bits": [4, 7], "name": "DISTANCE_1"},
10337 {"bits": [8, 11], "name": "DISTANCE_2"},
10338 {"bits": [12, 15], "name": "DISTANCE_3"},
10339 {"bits": [16, 19], "name": "DISTANCE_4"},
10340 {"bits": [20, 23], "name": "DISTANCE_5"},
10341 {"bits": [24, 27], "name": "DISTANCE_6"},
10342 {"bits": [28, 31], "name": "DISTANCE_7"}
10345 "PA_SC_CENTROID_PRIORITY_1": {
10347 {"bits": [0, 3], "name": "DISTANCE_8"},
10348 {"bits": [4, 7], "name": "DISTANCE_9"},
10349 {"bits": [8, 11], "name": "DISTANCE_10"},
10350 {"bits": [12, 15], "name": "DISTANCE_11"},
10351 {"bits": [16, 19], "name": "DISTANCE_12"},
10352 {"bits": [20, 23], "name": "DISTANCE_13"},
10353 {"bits": [24, 27], "name": "DISTANCE_14"},
10354 {"bits": [28, 31], "name": "DISTANCE_15"}
10357 "PA_SC_CLIPRECT_0_BR": {
10359 {"bits": [0, 14], "name": "BR_X"},
10360 {"bits": [16, 30], "name": "BR_Y"}
10363 "PA_SC_CLIPRECT_0_TL": {
10365 {"bits": [0, 14], "name": "TL_X"},
10366 {"bits": [16, 30], "name": "TL_Y"}
10369 "PA_SC_CLIPRECT_RULE": {
10371 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
10374 "PA_SC_DEBUG_CNTL": {
10376 {"bits": [0, 5], "name": "SC_DEBUG_INDX"}
10379 "PA_SC_EDGERULE": {
10381 {"bits": [0, 3], "name": "ER_TRI"},
10382 {"bits": [4, 7], "name": "ER_POINT"},
10383 {"bits": [8, 11], "name": "ER_RECT"},
10384 {"bits": [12, 17], "name": "ER_LINE_LR"},
10385 {"bits": [18, 23], "name": "ER_LINE_RL"},
10386 {"bits": [24, 27], "name": "ER_LINE_TB"},
10387 {"bits": [28, 31], "name": "ER_LINE_BT"}
10392 {"bits": [0, 0], "name": "ENABLE_PA_SC_OUT_OF_ORDER"},
10393 {"bits": [1, 1], "name": "DISABLE_SC_DB_TILE_FIX"},
10394 {"bits": [2, 2], "name": "DISABLE_AA_MASK_FULL_FIX"},
10395 {"bits": [3, 3], "name": "ENABLE_1XMSAA_SAMPLE_LOCATIONS"},
10396 {"bits": [4, 4], "name": "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID"},
10397 {"bits": [5, 5], "name": "DISABLE_SCISSOR_FIX"},
10398 {"bits": [6, 7], "name": "DISABLE_PW_BUBBLE_COLLAPSE"},
10399 {"bits": [8, 8], "name": "SEND_UNLIT_STILES_TO_PACKER"},
10400 {"bits": [9, 9], "name": "DISABLE_DUALGRAD_PERF_OPTIMIZATION"},
10401 {"bits": [10, 10], "name": "DISABLE_SC_PROCESS_RESET_PRIM"},
10402 {"bits": [11, 11], "name": "DISABLE_SC_PROCESS_RESET_SUPERTILE"},
10403 {"bits": [12, 12], "name": "DISABLE_SC_PROCESS_RESET_TILE"},
10404 {"bits": [13, 13], "name": "DISABLE_PA_SC_GUIDANCE"},
10405 {"bits": [14, 14], "name": "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS"},
10406 {"bits": [15, 15], "name": "ENABLE_MULTICYCLE_BUBBLE_FREEZE"},
10407 {"bits": [16, 16], "name": "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE"},
10408 {"bits": [17, 17], "name": "ENABLE_OUT_OF_ORDER_POLY_MODE"},
10409 {"bits": [18, 18], "name": "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST"},
10410 {"bits": [19, 19], "name": "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING"},
10411 {"bits": [20, 20], "name": "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY"},
10412 {"bits": [21, 21], "name": "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING"},
10413 {"bits": [22, 22], "name": "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING"},
10414 {"bits": [23, 23], "name": "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS"},
10415 {"bits": [24, 24], "name": "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID"},
10416 {"bits": [30, 30], "name": "ECO_SPARE1"},
10417 {"bits": [31, 31], "name": "ECO_SPARE0"}
10420 "PA_SC_FIFO_DEPTH_CNTL": {
10422 {"bits": [0, 7], "name": "DEPTH"}
10425 "PA_SC_FIFO_SIZE": {
10427 {"bits": [0, 5], "name": "SC_FRONTEND_PRIM_FIFO_SIZE"},
10428 {"bits": [6, 14], "name": "SC_BACKEND_PRIM_FIFO_SIZE"},
10429 {"bits": [15, 20], "name": "SC_HIZ_TILE_FIFO_SIZE"},
10430 {"bits": [23, 31], "name": "SC_EARLYZ_TILE_FIFO_SIZE"}
10433 "PA_SC_FORCE_EOV_MAX_CNTS": {
10435 {"bits": [0, 15], "name": "FORCE_EOV_MAX_CLK_CNT"},
10436 {"bits": [16, 31], "name": "FORCE_EOV_MAX_REZ_CNT"}
10439 "PA_SC_GENERIC_SCISSOR_TL": {
10441 {"bits": [0, 14], "name": "TL_X"},
10442 {"bits": [16, 30], "name": "TL_Y"},
10443 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
10446 "PA_SC_IF_FIFO_SIZE": {
10448 {"bits": [0, 5], "name": "SC_DB_TILE_IF_FIFO_SIZE"},
10449 {"bits": [6, 11], "name": "SC_DB_QUAD_IF_FIFO_SIZE"},
10450 {"bits": [12, 17], "name": "SC_SPI_IF_FIFO_SIZE"},
10451 {"bits": [18, 23], "name": "SC_BCI_IF_FIFO_SIZE"}
10454 "PA_SC_LINE_CNTL": {
10456 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
10457 {"bits": [10, 10], "name": "LAST_PIXEL"},
10458 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
10459 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}
10462 "PA_SC_LINE_STIPPLE": {
10464 {"bits": [0, 15], "name": "LINE_PATTERN"},
10465 {"bits": [16, 23], "name": "REPEAT_COUNT"},
10466 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
10467 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
10470 "PA_SC_LINE_STIPPLE_STATE": {
10472 {"bits": [0, 3], "name": "CURRENT_PTR"},
10473 {"bits": [8, 15], "name": "CURRENT_COUNT"}
10476 "PA_SC_MODE_CNTL_0": {
10478 {"bits": [0, 0], "name": "MSAA_ENABLE"},
10479 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
10480 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
10481 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}
10484 "PA_SC_MODE_CNTL_1": {
10486 {"bits": [0, 0], "name": "WALK_SIZE"},
10487 {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
10488 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
10489 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
10490 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
10491 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
10492 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
10493 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
10494 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
10495 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
10496 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
10497 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
10498 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
10499 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
10500 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
10501 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
10502 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
10503 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
10504 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
10505 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
10506 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
10507 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
10508 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
10509 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
10512 "PA_SC_PERFCOUNTER0_SELECT": {
10514 {"bits": [0, 8], "name": "PERF_SEL"},
10515 {"bits": [10, 19], "name": "PERF_SEL1"},
10516 {"bits": [20, 23], "name": "CNTR_MODE"}
10519 "PA_SC_PERFCOUNTER1_SELECT": {
10521 {"bits": [0, 8], "name": "PERF_SEL"}
10524 "PA_SC_RASTER_CONFIG": {
10526 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
10527 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
10528 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
10529 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
10530 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
10531 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
10532 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
10533 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
10534 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
10535 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
10536 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
10537 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
10538 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
10539 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
10540 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
10543 "PA_SC_SCREEN_SCISSOR_BR": {
10545 {"bits": [0, 15], "name": "BR_X"},
10546 {"bits": [16, 31], "name": "BR_Y"}
10549 "PA_SC_SCREEN_SCISSOR_TL": {
10551 {"bits": [0, 15], "name": "TL_X"},
10552 {"bits": [16, 31], "name": "TL_Y"}
10555 "PA_SC_VPORT_ZMAX_0": {
10557 {"bits": [0, 31], "name": "VPORT_ZMAX"}
10560 "PA_SC_VPORT_ZMIN_0": {
10562 {"bits": [0, 31], "name": "VPORT_ZMIN"}
10565 "PA_SC_WINDOW_OFFSET": {
10567 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
10568 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
10571 "PA_SU_CNTL_STATUS": {
10573 {"bits": [31, 31], "name": "SU_BUSY"}
10576 "PA_SU_DEBUG_CNTL": {
10578 {"bits": [0, 4], "name": "SU_DEBUG_INDX"}
10581 "PA_SU_HARDWARE_SCREEN_OFFSET": {
10583 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
10584 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
10587 "PA_SU_LINE_CNTL": {
10589 {"bits": [0, 15], "name": "WIDTH"}
10592 "PA_SU_LINE_STIPPLE_CNTL": {
10594 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
10595 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
10596 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"},
10597 {"bits": [4, 4], "name": "DIAMOND_ADJUST"}
10600 "PA_SU_LINE_STIPPLE_SCALE": {
10602 {"bits": [0, 31], "name": "LINE_STIPPLE_SCALE"}
10605 "PA_SU_LINE_STIPPLE_VALUE": {
10607 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
10610 "PA_SU_PERFCOUNTER0_HI": {
10612 {"bits": [0, 15], "name": "PERFCOUNTER_HI"}
10615 "PA_SU_PERFCOUNTER0_SELECT": {
10617 {"bits": [0, 7], "name": "PERF_SEL"},
10618 {"bits": [10, 19], "name": "PERF_SEL1"},
10619 {"bits": [20, 23], "name": "CNTR_MODE"}
10622 "PA_SU_PERFCOUNTER2_SELECT": {
10624 {"bits": [0, 7], "name": "PERF_SEL"},
10625 {"bits": [20, 23], "name": "CNTR_MODE"}
10628 "PA_SU_POINT_MINMAX": {
10630 {"bits": [0, 15], "name": "MIN_SIZE"},
10631 {"bits": [16, 31], "name": "MAX_SIZE"}
10634 "PA_SU_POINT_SIZE": {
10636 {"bits": [0, 15], "name": "HEIGHT"},
10637 {"bits": [16, 31], "name": "WIDTH"}
10640 "PA_SU_POLY_OFFSET_BACK_OFFSET": {
10642 {"bits": [0, 31], "name": "OFFSET"}
10645 "PA_SU_POLY_OFFSET_BACK_SCALE": {
10647 {"bits": [0, 31], "name": "SCALE"}
10650 "PA_SU_POLY_OFFSET_CLAMP": {
10652 {"bits": [0, 31], "name": "CLAMP"}
10655 "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
10657 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
10658 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
10661 "PA_SU_PRIM_FILTER_CNTL": {
10663 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
10664 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
10665 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
10666 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
10667 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
10668 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
10669 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
10670 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
10671 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
10672 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
10673 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
10676 "PA_SU_SC_MODE_CNTL": {
10678 {"bits": [0, 0], "name": "CULL_FRONT"},
10679 {"bits": [1, 1], "name": "CULL_BACK"},
10680 {"bits": [2, 2], "name": "FACE"},
10681 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
10682 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
10683 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
10684 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
10685 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
10686 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
10687 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
10688 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
10689 {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
10690 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}
10693 "PA_SU_VTX_CNTL": {
10695 {"bits": [0, 0], "name": "PIX_CENTER"},
10696 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
10697 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
10702 {"bits": [0, 31], "name": "OBSOLETE_ADDR"}
10707 {"bits": [0, 7], "name": "OBSOLETE_UMSK"},
10708 {"bits": [16, 17], "name": "OBSOLETE_SWAP"}
10711 "SPI_BARYC_CNTL": {
10713 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
10714 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
10715 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
10716 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
10717 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
10718 {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
10719 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
10722 "SPI_CONFIG_CNTL": {
10724 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
10725 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
10726 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
10727 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
10728 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"},
10729 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}
10732 "SPI_INTERP_CONTROL_0": {
10734 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
10735 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
10736 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
10737 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
10738 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
10739 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
10740 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
10743 "SPI_PS_INPUT_ADDR": {
10745 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
10746 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
10747 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
10748 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
10749 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
10750 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
10751 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
10752 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
10753 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
10754 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
10755 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
10756 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
10757 {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
10758 {"bits": [13, 13], "name": "ANCILLARY_ENA"},
10759 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
10760 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
10763 "SPI_PS_INPUT_CNTL_0": {
10765 {"bits": [0, 5], "name": "OFFSET"},
10766 {"bits": [8, 9], "name": "DEFAULT_VAL"},
10767 {"bits": [10, 10], "name": "FLAT_SHADE"},
10768 {"bits": [13, 16], "name": "CYL_WRAP"},
10769 {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
10770 {"bits": [18, 18], "name": "DUP"}
10773 "SPI_PS_INPUT_CNTL_20": {
10775 {"bits": [0, 5], "name": "OFFSET"},
10776 {"bits": [8, 9], "name": "DEFAULT_VAL"},
10777 {"bits": [10, 10], "name": "FLAT_SHADE"},
10778 {"bits": [18, 18], "name": "DUP"}
10781 "SPI_PS_IN_CONTROL": {
10783 {"bits": [0, 5], "name": "NUM_INTERP"},
10784 {"bits": [6, 6], "name": "PARAM_GEN"},
10785 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}
10788 "SPI_SHADER_COL_FORMAT": {
10790 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
10791 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
10792 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
10793 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
10794 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
10795 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
10796 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
10797 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
10800 "SPI_SHADER_PGM_HI_ES": {
10802 {"bits": [0, 7], "name": "MEM_BASE"}
10805 "SPI_SHADER_PGM_LO_ES": {
10807 {"bits": [0, 31], "name": "MEM_BASE"}
10810 "SPI_SHADER_PGM_RSRC1_ES": {
10812 {"bits": [0, 5], "name": "VGPRS"},
10813 {"bits": [6, 9], "name": "SGPRS"},
10814 {"bits": [10, 11], "name": "PRIORITY"},
10815 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
10816 {"bits": [20, 20], "name": "PRIV"},
10817 {"bits": [21, 21], "name": "DX10_CLAMP"},
10818 {"bits": [22, 22], "name": "DEBUG_MODE"},
10819 {"bits": [23, 23], "name": "IEEE_MODE"},
10820 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
10821 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"},
10822 {"bits": [27, 29], "name": "CACHE_CTL"},
10823 {"bits": [30, 30], "name": "CDBG_USER"}
10826 "SPI_SHADER_PGM_RSRC1_GS": {
10828 {"bits": [0, 5], "name": "VGPRS"},
10829 {"bits": [6, 9], "name": "SGPRS"},
10830 {"bits": [10, 11], "name": "PRIORITY"},
10831 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
10832 {"bits": [20, 20], "name": "PRIV"},
10833 {"bits": [21, 21], "name": "DX10_CLAMP"},
10834 {"bits": [22, 22], "name": "DEBUG_MODE"},
10835 {"bits": [23, 23], "name": "IEEE_MODE"},
10836 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
10837 {"bits": [25, 27], "name": "CACHE_CTL"},
10838 {"bits": [28, 28], "name": "CDBG_USER"}
10841 "SPI_SHADER_PGM_RSRC1_HS": {
10843 {"bits": [0, 5], "name": "VGPRS"},
10844 {"bits": [6, 9], "name": "SGPRS"},
10845 {"bits": [10, 11], "name": "PRIORITY"},
10846 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
10847 {"bits": [20, 20], "name": "PRIV"},
10848 {"bits": [21, 21], "name": "DX10_CLAMP"},
10849 {"bits": [22, 22], "name": "DEBUG_MODE"},
10850 {"bits": [23, 23], "name": "IEEE_MODE"},
10851 {"bits": [24, 26], "name": "CACHE_CTL"},
10852 {"bits": [27, 27], "name": "CDBG_USER"}
10855 "SPI_SHADER_PGM_RSRC1_LS": {
10857 {"bits": [0, 5], "name": "VGPRS"},
10858 {"bits": [6, 9], "name": "SGPRS"},
10859 {"bits": [10, 11], "name": "PRIORITY"},
10860 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
10861 {"bits": [20, 20], "name": "PRIV"},
10862 {"bits": [21, 21], "name": "DX10_CLAMP"},
10863 {"bits": [22, 22], "name": "DEBUG_MODE"},
10864 {"bits": [23, 23], "name": "IEEE_MODE"},
10865 {"bits": [24, 25], "name": "VGPR_COMP_CNT"},
10866 {"bits": [26, 28], "name": "CACHE_CTL"},
10867 {"bits": [29, 29], "name": "CDBG_USER"}
10870 "SPI_SHADER_PGM_RSRC1_PS": {
10872 {"bits": [0, 5], "name": "VGPRS"},
10873 {"bits": [6, 9], "name": "SGPRS"},
10874 {"bits": [10, 11], "name": "PRIORITY"},
10875 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
10876 {"bits": [20, 20], "name": "PRIV"},
10877 {"bits": [21, 21], "name": "DX10_CLAMP"},
10878 {"bits": [22, 22], "name": "DEBUG_MODE"},
10879 {"bits": [23, 23], "name": "IEEE_MODE"},
10880 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
10881 {"bits": [25, 27], "name": "CACHE_CTL"},
10882 {"bits": [28, 28], "name": "CDBG_USER"}
10885 "SPI_SHADER_PGM_RSRC2_ES": {
10887 {"bits": [0, 0], "name": "SCRATCH_EN"},
10888 {"bits": [1, 5], "name": "USER_SGPR"},
10889 {"bits": [6, 6], "name": "TRAP_PRESENT"},
10890 {"bits": [7, 7], "name": "OC_LDS_EN"},
10891 {"bits": [8, 14], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
10892 {"bits": [20, 28], "name": "LDS_SIZE"}
10895 "SPI_SHADER_PGM_RSRC2_GS": {
10897 {"bits": [0, 0], "name": "SCRATCH_EN"},
10898 {"bits": [1, 5], "name": "USER_SGPR"},
10899 {"bits": [6, 6], "name": "TRAP_PRESENT"},
10900 {"bits": [7, 13], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
10903 "SPI_SHADER_PGM_RSRC2_HS": {
10905 {"bits": [0, 0], "name": "SCRATCH_EN"},
10906 {"bits": [1, 5], "name": "USER_SGPR"},
10907 {"bits": [6, 6], "name": "TRAP_PRESENT"},
10908 {"bits": [7, 7], "name": "OC_LDS_EN"},
10909 {"bits": [8, 8], "name": "TG_SIZE_EN"},
10910 {"bits": [9, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
10913 "SPI_SHADER_PGM_RSRC2_LS": {
10915 {"bits": [0, 0], "name": "SCRATCH_EN"},
10916 {"bits": [1, 5], "name": "USER_SGPR"},
10917 {"bits": [6, 6], "name": "TRAP_PRESENT"},
10918 {"bits": [7, 15], "name": "LDS_SIZE"},
10919 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
10922 "SPI_SHADER_PGM_RSRC2_PS": {
10924 {"bits": [0, 0], "name": "SCRATCH_EN"},
10925 {"bits": [1, 5], "name": "USER_SGPR"},
10926 {"bits": [6, 6], "name": "TRAP_PRESENT"},
10927 {"bits": [7, 7], "name": "WAVE_CNT_EN"},
10928 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
10929 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
10932 "SPI_SHADER_PGM_RSRC2_VS": {
10934 {"bits": [0, 0], "name": "SCRATCH_EN"},
10935 {"bits": [1, 5], "name": "USER_SGPR"},
10936 {"bits": [6, 6], "name": "TRAP_PRESENT"},
10937 {"bits": [7, 7], "name": "OC_LDS_EN"},
10938 {"bits": [8, 8], "name": "SO_BASE0_EN"},
10939 {"bits": [9, 9], "name": "SO_BASE1_EN"},
10940 {"bits": [10, 10], "name": "SO_BASE2_EN"},
10941 {"bits": [11, 11], "name": "SO_BASE3_EN"},
10942 {"bits": [12, 12], "name": "SO_EN"},
10943 {"bits": [13, 19], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
10946 "SPI_SHADER_POS_FORMAT": {
10948 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
10949 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
10950 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
10951 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}
10954 "SPI_SHADER_Z_FORMAT": {
10956 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
10959 "SPI_VS_OUT_CONFIG": {
10961 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
10962 {"bits": [6, 6], "name": "VS_HALF_PACK"}
10967 {"bits": [0, 0], "name": "INST_INVALIDATE"},
10968 {"bits": [1, 1], "name": "DATA_INVALIDATE"},
10969 {"bits": [2, 2], "name": "INVALIDATE_VOLATILE"}
10974 {"bits": [0, 1], "name": "INST_CACHE_SIZE"},
10975 {"bits": [2, 3], "name": "DATA_CACHE_SIZE"},
10976 {"bits": [4, 5], "name": "MISS_FIFO_DEPTH"},
10977 {"bits": [6, 6], "name": "HIT_FIFO_DEPTH"},
10978 {"bits": [7, 7], "name": "FORCE_ALWAYS_MISS"},
10979 {"bits": [8, 8], "name": "FORCE_IN_ORDER"},
10980 {"bits": [9, 9], "name": "IDENTITY_HASH_BANK"},
10981 {"bits": [10, 10], "name": "IDENTITY_HASH_SET"},
10982 {"bits": [11, 11], "name": "PER_VMID_INV_DISABLE"}
10985 "SQC_SECDED_CNT": {
10987 {"bits": [0, 7], "name": "INST_SEC"},
10988 {"bits": [8, 15], "name": "INST_DED"},
10989 {"bits": [16, 23], "name": "DATA_SEC"},
10990 {"bits": [24, 31], "name": "DATA_DED"}
10993 "SQ_ALU_CLK_CTRL": {
10995 {"bits": [0, 15], "name": "FORCE_CU_ON_SH0"},
10996 {"bits": [16, 31], "name": "FORCE_CU_ON_SH1"}
10999 "SQ_BUF_RSRC_WORD0": {
11001 {"bits": [0, 31], "name": "BASE_ADDRESS"}
11004 "SQ_BUF_RSRC_WORD1": {
11006 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"},
11007 {"bits": [16, 29], "name": "STRIDE"},
11008 {"bits": [30, 30], "name": "CACHE_SWIZZLE"},
11009 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"}
11012 "SQ_BUF_RSRC_WORD2": {
11014 {"bits": [0, 31], "name": "NUM_RECORDS"}
11017 "SQ_BUF_RSRC_WORD3": {
11019 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
11020 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
11021 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
11022 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
11023 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"},
11024 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"},
11025 {"bits": [19, 20], "name": "ELEMENT_SIZE"},
11026 {"bits": [21, 22], "name": "INDEX_STRIDE"},
11027 {"bits": [23, 23], "name": "ADD_TID_ENABLE"},
11028 {"bits": [24, 24], "name": "ATC"},
11029 {"bits": [25, 25], "name": "HASH_ENABLE"},
11030 {"bits": [26, 26], "name": "HEAP"},
11031 {"bits": [27, 29], "name": "MTYPE"},
11032 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"}
11037 {"bits": [0, 7], "name": "UNUSED"},
11038 {"bits": [8, 8], "name": "DEBUG_EN"},
11039 {"bits": [9, 9], "name": "DISABLE_SCA_BYPASS"},
11040 {"bits": [10, 10], "name": "DISABLE_IB_DEP_CHECK"},
11041 {"bits": [11, 11], "name": "ENABLE_SOFT_CLAUSE"},
11042 {"bits": [12, 12], "name": "EARLY_TA_DONE_DISABLE"},
11043 {"bits": [13, 13], "name": "DUA_FLAT_LOCK_ENABLE"},
11044 {"bits": [14, 14], "name": "DUA_LDS_BYPASS_DISABLE"},
11045 {"bits": [15, 15], "name": "DUA_FLAT_LDS_PINGPONG_DISABLE"}
11048 "SQ_DEBUG_STS_GLOBAL": {
11050 {"bits": [0, 0], "name": "BUSY"},
11051 {"bits": [1, 1], "name": "INTERRUPT_MSG_BUSY"},
11052 {"bits": [4, 15], "name": "WAVE_LEVEL_SH0"},
11053 {"bits": [16, 27], "name": "WAVE_LEVEL_SH1"}
11058 {"bits": [0, 5], "name": "LDS_DED"},
11059 {"bits": [8, 12], "name": "SGPR_DED"},
11060 {"bits": [16, 24], "name": "VGPR_DED"}
11065 {"bits": [0, 3], "name": "WAVE_ID"},
11066 {"bits": [4, 5], "name": "SIMD_ID"},
11067 {"bits": [6, 8], "name": "SOURCE"},
11068 {"bits": [9, 12], "name": "VM_ID"}
11073 {"bits": [0, 3], "name": "INTERRUPT_FIFO_SIZE"},
11074 {"bits": [8, 11], "name": "TTRACE_FIFO_SIZE"},
11075 {"bits": [16, 17], "name": "EXPORT_BUF_SIZE"},
11076 {"bits": [18, 19], "name": "VMEM_DATA_FIFO_SIZE"}
11079 "SQ_IMG_RSRC_WORD1": {
11081 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"},
11082 {"bits": [8, 19], "name": "MIN_LOD"},
11083 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"},
11084 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"},
11085 {"bits": [30, 31], "name": "MTYPE"}
11088 "SQ_IMG_RSRC_WORD2": {
11090 {"bits": [0, 13], "name": "WIDTH"},
11091 {"bits": [14, 27], "name": "HEIGHT"},
11092 {"bits": [28, 30], "name": "PERF_MOD"},
11093 {"bits": [31, 31], "name": "INTERLACED"}
11096 "SQ_IMG_RSRC_WORD3": {
11098 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"},
11099 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"},
11100 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"},
11101 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"},
11102 {"bits": [12, 15], "name": "BASE_LEVEL"},
11103 {"bits": [16, 19], "name": "LAST_LEVEL"},
11104 {"bits": [20, 24], "name": "TILING_INDEX"},
11105 {"bits": [25, 25], "name": "POW2_PAD"},
11106 {"bits": [26, 26], "name": "MTYPE"},
11107 {"bits": [27, 27], "name": "ATC"},
11108 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"}
11111 "SQ_IMG_RSRC_WORD4": {
11113 {"bits": [0, 12], "name": "DEPTH"},
11114 {"bits": [13, 26], "name": "PITCH"}
11117 "SQ_IMG_RSRC_WORD5": {
11119 {"bits": [0, 12], "name": "BASE_ARRAY"},
11120 {"bits": [13, 25], "name": "LAST_ARRAY"}
11123 "SQ_IMG_RSRC_WORD6": {
11125 {"bits": [0, 11], "name": "MIN_LOD_WARN"},
11126 {"bits": [12, 19], "name": "COUNTER_BANK_ID"},
11127 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"},
11128 {"bits": [21, 31], "name": "UNUNSED"}
11131 "SQ_IMG_RSRC_WORD7": {
11133 {"bits": [0, 31], "name": "UNUNSED"}
11136 "SQ_IMG_SAMP_WORD0": {
11138 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"},
11139 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"},
11140 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"},
11141 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"},
11142 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"},
11143 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"},
11144 {"bits": [16, 18], "name": "ANISO_THRESHOLD"},
11145 {"bits": [19, 19], "name": "MC_COORD_TRUNC"},
11146 {"bits": [20, 20], "name": "FORCE_DEGAMMA"},
11147 {"bits": [21, 26], "name": "ANISO_BIAS"},
11148 {"bits": [27, 27], "name": "TRUNC_COORD"},
11149 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"},
11150 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}
11153 "SQ_IMG_SAMP_WORD1": {
11155 {"bits": [0, 11], "name": "MIN_LOD"},
11156 {"bits": [12, 23], "name": "MAX_LOD"},
11157 {"bits": [24, 27], "name": "PERF_MIP"},
11158 {"bits": [28, 31], "name": "PERF_Z"}
11161 "SQ_IMG_SAMP_WORD2": {
11163 {"bits": [0, 13], "name": "LOD_BIAS"},
11164 {"bits": [14, 19], "name": "LOD_BIAS_SEC"},
11165 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"},
11166 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"},
11167 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"},
11168 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"},
11169 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"},
11170 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"},
11171 {"bits": [30, 30], "name": "FILTER_PREC_FIX"}
11174 "SQ_IMG_SAMP_WORD3": {
11176 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"},
11177 {"bits": [29, 29], "name": "UPGRADED_DEPTH"},
11178 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"}
11183 {"bits": [0, 3], "name": "WAVE_ID"},
11184 {"bits": [4, 5], "name": "SIMD_ID"},
11185 {"bits": [6, 11], "name": "THREAD_ID"},
11186 {"bits": [12, 12], "name": "AUTO_INCR"},
11187 {"bits": [13, 13], "name": "FORCE_READ"},
11188 {"bits": [14, 14], "name": "READ_TIMEOUT"},
11189 {"bits": [15, 15], "name": "UNINDEXED"},
11190 {"bits": [16, 31], "name": "INDEX"}
11193 "SQ_INTERRUPT_WORD_AUTO": {
11195 {"bits": [0, 0], "name": "THREAD_TRACE"},
11196 {"bits": [1, 1], "name": "WLT"},
11197 {"bits": [2, 2], "name": "THREAD_TRACE_BUF_FULL"},
11198 {"bits": [3, 3], "name": "REG_TIMESTAMP"},
11199 {"bits": [4, 4], "name": "CMD_TIMESTAMP"},
11200 {"bits": [5, 5], "name": "HOST_CMD_OVERFLOW"},
11201 {"bits": [6, 6], "name": "HOST_REG_OVERFLOW"},
11202 {"bits": [7, 7], "name": "IMMED_OVERFLOW"},
11203 {"bits": [25, 25], "name": "SE_ID"},
11204 {"bits": [26, 27], "name": "ENCODING"}
11207 "SQ_LB_CTR_CTRL": {
11209 {"bits": [0, 0], "name": "START"},
11210 {"bits": [1, 1], "name": "LOAD"},
11211 {"bits": [2, 2], "name": "CLEAR"}
11214 "SQ_PERFCOUNTER0_SELECT": {
11216 {"bits": [0, 8], "name": "PERF_SEL"},
11217 {"bits": [12, 15], "name": "SQC_BANK_MASK"},
11218 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"},
11219 {"bits": [20, 23], "name": "SPM_MODE"},
11220 {"bits": [24, 27], "name": "SIMD_MASK"},
11221 {"bits": [28, 31], "name": "PERF_MODE"}
11224 "SQ_PERFCOUNTER_CTRL": {
11226 {"bits": [0, 0], "name": "PS_EN"},
11227 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
11228 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
11229 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
11230 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
11231 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
11232 {"bits": [6, 6], "name": "CS_EN"},
11233 {"bits": [8, 12], "name": "CNTR_RATE"},
11234 {"bits": [13, 13], "name": "DISABLE_FLUSH"}
11237 "SQ_POWER_THROTTLE": {
11239 {"bits": [0, 13], "name": "MIN_POWER"},
11240 {"bits": [16, 29], "name": "MAX_POWER"},
11241 {"bits": [30, 31], "name": "PHASE_OFFSET"}
11244 "SQ_POWER_THROTTLE2": {
11246 {"bits": [0, 13], "name": "MAX_POWER_DELTA"},
11247 {"bits": [16, 25], "name": "SHORT_TERM_INTERVAL_SIZE"},
11248 {"bits": [27, 30], "name": "LONG_TERM_INTERVAL_RATIO"},
11249 {"bits": [31, 31], "name": "USE_REF_CLOCK"}
11252 "SQ_RANDOM_WAVE_PRI": {
11254 {"bits": [0, 6], "name": "RET"},
11255 {"bits": [7, 9], "name": "RUI"},
11256 {"bits": [10, 20], "name": "RNG"}
11259 "SQ_REG_CREDITS": {
11261 {"bits": [0, 5], "name": "SRBM_CREDITS"},
11262 {"bits": [8, 11], "name": "CMD_CREDITS"},
11263 {"bits": [28, 28], "name": "REG_BUSY"},
11264 {"bits": [29, 29], "name": "SRBM_OVERFLOW"},
11265 {"bits": [30, 30], "name": "IMMED_OVERFLOW"},
11266 {"bits": [31, 31], "name": "CMD_OVERFLOW"}
11271 {"bits": [0, 5], "name": "LDS_SEC"},
11272 {"bits": [8, 12], "name": "SGPR_SEC"},
11273 {"bits": [16, 24], "name": "VGPR_SEC"}
11276 "SQ_THREAD_TRACE_BASE": {
11278 {"bits": [0, 31], "name": "ADDR"}
11281 "SQ_THREAD_TRACE_CNTR": {
11283 {"bits": [0, 31], "name": "CNTR"}
11286 "SQ_THREAD_TRACE_CTRL": {
11288 {"bits": [31, 31], "name": "RESET_BUFFER"}
11291 "SQ_THREAD_TRACE_HIWATER": {
11293 {"bits": [0, 2], "name": "HIWATER"}
11296 "SQ_THREAD_TRACE_MASK": {
11298 {"bits": [0, 4], "name": "CU_SEL"},
11299 {"bits": [5, 5], "name": "SH_SEL"},
11300 {"bits": [7, 7], "name": "REG_STALL_EN"},
11301 {"bits": [12, 13], "name": "VM_ID_MASK"},
11302 {"bits": [14, 14], "name": "SPI_STALL_EN"},
11303 {"bits": [15, 15], "name": "SQ_STALL_EN"},
11304 {"bits": [16, 31], "name": "RANDOM_SEED"},
11305 {"bits": [16, 31], "name": "RANDOM_SEED"}
11308 "SQ_THREAD_TRACE_MODE": {
11310 {"bits": [0, 2], "name": "MASK_PS"},
11311 {"bits": [3, 5], "name": "MASK_VS"},
11312 {"bits": [6, 8], "name": "MASK_GS"},
11313 {"bits": [9, 11], "name": "MASK_ES"},
11314 {"bits": [12, 14], "name": "MASK_HS"},
11315 {"bits": [15, 17], "name": "MASK_LS"},
11316 {"bits": [18, 20], "name": "MASK_CS"},
11317 {"bits": [21, 22], "name": "MODE"},
11318 {"bits": [23, 24], "name": "CAPTURE_MODE"},
11319 {"bits": [25, 25], "name": "AUTOFLUSH_EN"},
11320 {"bits": [26, 26], "name": "PRIV"},
11321 {"bits": [27, 28], "name": "ISSUE_MASK"},
11322 {"bits": [29, 29], "name": "TEST_MODE"},
11323 {"bits": [30, 30], "name": "INTERRUPT_EN"},
11324 {"bits": [31, 31], "name": "WRAP"}
11327 "SQ_THREAD_TRACE_PERF_MASK": {
11329 {"bits": [0, 15], "name": "SH0_MASK"},
11330 {"bits": [16, 31], "name": "SH1_MASK"}
11333 "SQ_THREAD_TRACE_SIZE": {
11335 {"bits": [0, 21], "name": "SIZE"}
11338 "SQ_THREAD_TRACE_STATUS": {
11340 {"bits": [0, 2], "name": "FINISH_PENDING"},
11341 {"bits": [16, 18], "name": "FINISH_DONE"},
11342 {"bits": [29, 29], "name": "NEW_BUF"},
11343 {"bits": [30, 30], "name": "BUSY"},
11344 {"bits": [31, 31], "name": "FULL"}
11347 "SQ_THREAD_TRACE_TOKEN_MASK": {
11349 {"bits": [0, 15], "name": "TOKEN_MASK"},
11350 {"bits": [16, 23], "name": "REG_MASK"},
11351 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"}
11354 "SQ_THREAD_TRACE_WPTR": {
11356 {"bits": [0, 29], "name": "WPTR"},
11357 {"bits": [30, 31], "name": "READ_OFFSET"}
11362 {"bits": [0, 31], "name": "TIME"}
11365 "SQ_WAVE_EXEC_HI": {
11367 {"bits": [0, 31], "name": "EXEC_HI"}
11370 "SQ_WAVE_EXEC_LO": {
11372 {"bits": [0, 31], "name": "EXEC_LO"}
11375 "SQ_WAVE_GPR_ALLOC": {
11377 {"bits": [0, 5], "name": "VGPR_BASE"},
11378 {"bits": [8, 13], "name": "VGPR_SIZE"},
11379 {"bits": [16, 21], "name": "SGPR_BASE"},
11380 {"bits": [24, 27], "name": "SGPR_SIZE"}
11385 {"bits": [0, 3], "name": "WAVE_ID"},
11386 {"bits": [4, 5], "name": "SIMD_ID"},
11387 {"bits": [6, 7], "name": "PIPE_ID"},
11388 {"bits": [8, 11], "name": "CU_ID"},
11389 {"bits": [12, 12], "name": "SH_ID"},
11390 {"bits": [13, 13], "name": "SE_ID"},
11391 {"bits": [16, 19], "name": "TG_ID"},
11392 {"bits": [20, 23], "name": "VM_ID"},
11393 {"bits": [24, 26], "name": "QUEUE_ID"},
11394 {"bits": [27, 29], "name": "STATE_ID"},
11395 {"bits": [30, 31], "name": "ME_ID"}
11398 "SQ_WAVE_IB_DBG0": {
11400 {"bits": [0, 2], "name": "IBUF_ST"},
11401 {"bits": [3, 3], "name": "PC_INVALID"},
11402 {"bits": [4, 4], "name": "NEED_NEXT_DW"},
11403 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"},
11404 {"bits": [8, 9], "name": "IBUF_RPTR"},
11405 {"bits": [10, 11], "name": "IBUF_WPTR"},
11406 {"bits": [16, 18], "name": "INST_STR_ST"},
11407 {"bits": [19, 21], "name": "MISC_CNT"},
11408 {"bits": [22, 23], "name": "ECC_ST"},
11409 {"bits": [24, 24], "name": "IS_HYB"},
11410 {"bits": [25, 26], "name": "HYB_CNT"},
11411 {"bits": [27, 27], "name": "KILL"},
11412 {"bits": [28, 28], "name": "NEED_KILL_IFETCH"}
11415 "SQ_WAVE_IB_STS": {
11417 {"bits": [0, 3], "name": "VM_CNT"},
11418 {"bits": [4, 6], "name": "EXP_CNT"},
11419 {"bits": [8, 12], "name": "LGKM_CNT"},
11420 {"bits": [13, 15], "name": "VALU_CNT"}
11423 "SQ_WAVE_INST_DW0": {
11425 {"bits": [0, 31], "name": "INST_DW0"}
11428 "SQ_WAVE_INST_DW1": {
11430 {"bits": [0, 31], "name": "INST_DW1"}
11433 "SQ_WAVE_LDS_ALLOC": {
11435 {"bits": [0, 7], "name": "LDS_BASE"},
11436 {"bits": [12, 20], "name": "LDS_SIZE"}
11441 {"bits": [0, 31], "name": "M0"}
11446 {"bits": [0, 3], "name": "FP_ROUND"},
11447 {"bits": [4, 7], "name": "FP_DENORM"},
11448 {"bits": [8, 8], "name": "DX10_CLAMP"},
11449 {"bits": [9, 9], "name": "IEEE"},
11450 {"bits": [10, 10], "name": "LOD_CLAMPED"},
11451 {"bits": [11, 11], "name": "DEBUG_EN"},
11452 {"bits": [12, 18], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
11453 {"bits": [28, 28], "name": "VSKIP"},
11454 {"bits": [29, 31], "name": "CSP"}
11459 {"bits": [0, 7], "name": "PC_HI"}
11464 {"bits": [0, 31], "name": "PC_LO"}
11467 "SQ_WAVE_STATUS": {
11469 {"bits": [0, 0], "name": "SCC"},
11470 {"bits": [1, 2], "name": "SPI_PRIO"},
11471 {"bits": [3, 4], "name": "WAVE_PRIO"},
11472 {"bits": [5, 5], "name": "PRIV"},
11473 {"bits": [6, 6], "name": "TRAP_EN"},
11474 {"bits": [7, 7], "name": "TTRACE_EN"},
11475 {"bits": [8, 8], "name": "EXPORT_RDY"},
11476 {"bits": [9, 9], "name": "EXECZ"},
11477 {"bits": [10, 10], "name": "VCCZ"},
11478 {"bits": [11, 11], "name": "IN_TG"},
11479 {"bits": [12, 12], "name": "IN_BARRIER"},
11480 {"bits": [13, 13], "name": "HALT"},
11481 {"bits": [14, 14], "name": "TRAP"},
11482 {"bits": [15, 15], "name": "TTRACE_CU_EN"},
11483 {"bits": [16, 16], "name": "VALID"},
11484 {"bits": [17, 17], "name": "ECC_ERR"},
11485 {"bits": [18, 18], "name": "SKIP_EXPORT"},
11486 {"bits": [19, 19], "name": "PERF_EN"},
11487 {"bits": [20, 20], "name": "COND_DBG_USER"},
11488 {"bits": [21, 21], "name": "COND_DBG_SYS"},
11489 {"bits": [22, 22], "name": "DATA_ATC"},
11490 {"bits": [23, 23], "name": "INST_ATC"},
11491 {"bits": [24, 26], "name": "DISPATCH_CACHE_CTRL"},
11492 {"bits": [27, 27], "name": "MUST_EXPORT"}
11495 "SQ_WAVE_TBA_HI": {
11497 {"bits": [0, 7], "name": "ADDR_HI"}
11500 "SQ_WAVE_TBA_LO": {
11502 {"bits": [0, 31], "name": "ADDR_LO"}
11505 "SQ_WAVE_TRAPSTS": {
11507 {"bits": [0, 6], "enum_ref": "EXCP_EN", "name": "EXCP"},
11508 {"bits": [16, 21], "name": "EXCP_CYCLE"},
11509 {"bits": [29, 31], "name": "DP_RATE"}
11514 {"bits": [0, 31], "name": "DATA"}
11517 "TA_BC_BASE_ADDR": {
11519 {"bits": [0, 31], "name": "ADDRESS"}
11522 "VGT_CACHE_INVALIDATION": {
11524 {"bits": [0, 1], "name": "CACHE_INVALIDATION"},
11525 {"bits": [5, 5], "name": "VS_NO_EXTRA_BUFFER"},
11526 {"bits": [6, 7], "name": "AUTO_INVLD_EN"},
11527 {"bits": [9, 9], "name": "USE_GS_DONE"},
11528 {"bits": [11, 11], "name": "DIS_RANGE_FULL_INVLD"},
11529 {"bits": [12, 12], "name": "GS_LATE_ALLOC_EN"},
11530 {"bits": [13, 13], "name": "STREAMOUT_FULL_FLUSH"},
11531 {"bits": [16, 20], "name": "ES_LIMIT"}
11534 "VGT_CNTL_STATUS": {
11536 {"bits": [0, 0], "name": "VGT_BUSY"},
11537 {"bits": [1, 1], "name": "VGT_OUT_INDX_BUSY"},
11538 {"bits": [2, 2], "name": "VGT_OUT_BUSY"},
11539 {"bits": [3, 3], "name": "VGT_PT_BUSY"},
11540 {"bits": [4, 4], "name": "VGT_TE_BUSY"},
11541 {"bits": [5, 5], "name": "VGT_VR_BUSY"},
11542 {"bits": [6, 6], "name": "VGT_PI_BUSY"},
11543 {"bits": [7, 7], "name": "VGT_GS_BUSY"},
11544 {"bits": [8, 8], "name": "VGT_HS_BUSY"},
11545 {"bits": [9, 9], "name": "VGT_TE11_BUSY"}
11548 "VGT_DEBUG_CNTL": {
11550 {"bits": [0, 5], "name": "VGT_DEBUG_INDX"},
11551 {"bits": [6, 6], "name": "VGT_DEBUG_SEL_BUS_B"}
11556 {"bits": [0, 31], "name": "BASE_ADDR"}
11559 "VGT_DMA_BASE_HI": {
11561 {"bits": [0, 7], "name": "BASE_ADDR"}
11564 "VGT_DMA_DATA_FIFO_DEPTH": {
11566 {"bits": [0, 8], "name": "DMA_DATA_FIFO_DEPTH"}
11569 "VGT_DMA_INDEX_TYPE": {
11571 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
11572 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
11573 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
11574 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
11575 {"bits": [8, 8], "name": "ATC"},
11576 {"bits": [9, 9], "name": "NOT_EOP"},
11577 {"bits": [10, 10], "name": "REQ_PATH"}
11580 "VGT_DMA_MAX_SIZE": {
11582 {"bits": [0, 31], "name": "MAX_SIZE"}
11585 "VGT_DMA_NUM_INSTANCES": {
11587 {"bits": [0, 31], "name": "NUM_INSTANCES"}
11590 "VGT_DMA_REQ_FIFO_DEPTH": {
11592 {"bits": [0, 5], "name": "DMA_REQ_FIFO_DEPTH"}
11597 {"bits": [0, 31], "name": "NUM_INDICES"}
11600 "VGT_DRAW_INITIATOR": {
11602 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
11603 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
11604 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
11605 {"bits": [5, 5], "name": "NOT_EOP"},
11606 {"bits": [6, 6], "name": "USE_OPAQUE"}
11609 "VGT_DRAW_INIT_FIFO_DEPTH": {
11611 {"bits": [0, 5], "name": "DRAW_INIT_FIFO_DEPTH"}
11614 "VGT_ESGS_RING_ITEMSIZE": {
11616 {"bits": [0, 14], "name": "ITEMSIZE"}
11619 "VGT_ESGS_RING_SIZE": {
11621 {"bits": [0, 31], "name": "MEM_SIZE"}
11626 {"bits": [0, 10], "name": "ES_PER_GS"}
11629 "VGT_EVENT_ADDRESS_REG": {
11631 {"bits": [0, 27], "name": "ADDRESS_LOW"}
11634 "VGT_EVENT_INITIATOR": {
11636 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
11637 {"bits": [18, 26], "name": "ADDRESS_HI"},
11638 {"bits": [27, 27], "name": "EXTENDED_EVENT"}
11641 "VGT_FIFO_DEPTHS": {
11643 {"bits": [0, 6], "name": "VS_DEALLOC_TBL_DEPTH"},
11644 {"bits": [7, 7], "name": "RESERVED_0"},
11645 {"bits": [8, 21], "name": "CLIPP_FIFO_DEPTH"},
11646 {"bits": [22, 31], "name": "RESERVED_1"}
11649 "VGT_GROUP_DECR": {
11651 {"bits": [0, 3], "name": "DECR"}
11654 "VGT_GROUP_FIRST_DECR": {
11656 {"bits": [0, 3], "name": "FIRST_DECR"}
11659 "VGT_GROUP_PRIM_TYPE": {
11661 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"},
11662 {"bits": [14, 14], "name": "RETAIN_ORDER"},
11663 {"bits": [15, 15], "name": "RETAIN_QUADS"},
11664 {"bits": [16, 18], "name": "PRIM_ORDER"}
11667 "VGT_GROUP_VECT_0_CNTL": {
11669 {"bits": [0, 0], "name": "COMP_X_EN"},
11670 {"bits": [1, 1], "name": "COMP_Y_EN"},
11671 {"bits": [2, 2], "name": "COMP_Z_EN"},
11672 {"bits": [3, 3], "name": "COMP_W_EN"},
11673 {"bits": [8, 15], "name": "STRIDE"},
11674 {"bits": [16, 23], "name": "SHIFT"}
11677 "VGT_GROUP_VECT_0_FMT_CNTL": {
11679 {"bits": [0, 3], "name": "X_CONV"},
11680 {"bits": [4, 7], "name": "X_OFFSET"},
11681 {"bits": [8, 11], "name": "Y_CONV"},
11682 {"bits": [12, 15], "name": "Y_OFFSET"},
11683 {"bits": [16, 19], "name": "Z_CONV"},
11684 {"bits": [20, 23], "name": "Z_OFFSET"},
11685 {"bits": [24, 27], "name": "W_CONV"},
11686 {"bits": [28, 31], "name": "W_OFFSET"}
11689 "VGT_GSVS_RING_OFFSET_1": {
11691 {"bits": [0, 14], "name": "OFFSET"}
11694 "VGT_GS_INSTANCE_CNT": {
11696 {"bits": [0, 0], "name": "ENABLE"},
11697 {"bits": [2, 8], "name": "CNT"}
11700 "VGT_GS_MAX_VERT_OUT": {
11702 {"bits": [0, 10], "name": "MAX_VERT_OUT"}
11707 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"},
11708 {"bits": [3, 3], "name": "RESERVED_0"},
11709 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"},
11710 {"bits": [6, 10], "name": "RESERVED_1"},
11711 {"bits": [11, 11], "name": "GS_C_PACK_EN"},
11712 {"bits": [12, 12], "name": "RESERVED_2"},
11713 {"bits": [13, 13], "name": "ES_PASSTHRU"},
11714 {"bits": [14, 14], "name": "COMPUTE_MODE"},
11715 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"},
11716 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"},
11717 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"},
11718 {"bits": [18, 18], "name": "SUPPRESS_CUTS"},
11719 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"},
11720 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"},
11721 {"bits": [21, 22], "name": "ONCHIP"}
11724 "VGT_GS_OUT_PRIM_TYPE": {
11726 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"},
11727 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"},
11728 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"},
11729 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"},
11730 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"}
11735 {"bits": [0, 10], "name": "GS_PER_ES"}
11740 {"bits": [0, 3], "name": "GS_PER_VS"}
11743 "VGT_GS_VERTEX_REUSE": {
11745 {"bits": [0, 4], "name": "VERT_REUSE"}
11750 {"bits": [0, 1], "name": "TESS_MODE"}
11753 "VGT_HOS_MAX_TESS_LEVEL": {
11755 {"bits": [0, 31], "name": "MAX_TESS"}
11758 "VGT_HOS_MIN_TESS_LEVEL": {
11760 {"bits": [0, 31], "name": "MIN_TESS"}
11763 "VGT_HOS_REUSE_DEPTH": {
11765 {"bits": [0, 7], "name": "REUSE_DEPTH"}
11768 "VGT_HS_OFFCHIP_PARAM": {
11770 {"bits": [0, 6], "name": "OFFCHIP_BUFFERING"},
11771 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
11774 "VGT_INDEX_TYPE": {
11776 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
11779 "VGT_INDX_OFFSET": {
11781 {"bits": [0, 31], "name": "INDX_OFFSET"}
11784 "VGT_INSTANCE_STEP_RATE_0": {
11786 {"bits": [0, 31], "name": "STEP_RATE"}
11789 "VGT_LAST_COPY_STATE": {
11791 {"bits": [0, 2], "name": "SRC_STATE_ID"},
11792 {"bits": [16, 18], "name": "DST_STATE_ID"}
11795 "VGT_LS_HS_CONFIG": {
11797 {"bits": [0, 7], "name": "NUM_PATCHES"},
11798 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
11799 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
11802 "VGT_MAX_VTX_INDX": {
11804 {"bits": [0, 31], "name": "MAX_INDX"}
11807 "VGT_MC_LAT_CNTL": {
11809 {"bits": [0, 1], "name": "MC_TIME_STAMP_RES"}
11812 "VGT_MIN_VTX_INDX": {
11814 {"bits": [0, 31], "name": "MIN_INDX"}
11817 "VGT_MULTI_PRIM_IB_RESET_EN": {
11819 {"bits": [0, 0], "name": "RESET_EN"}
11822 "VGT_MULTI_PRIM_IB_RESET_INDX": {
11824 {"bits": [0, 31], "name": "RESET_INDX"}
11827 "VGT_OUTPUT_PATH_CNTL": {
11829 {"bits": [0, 2], "name": "PATH_SELECT"}
11832 "VGT_OUT_DEALLOC_CNTL": {
11834 {"bits": [0, 6], "name": "DEALLOC_DIST"}
11837 "VGT_PERFCOUNTER_SEID_MASK": {
11839 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"}
11842 "VGT_PRIMITIVEID_EN": {
11844 {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
11845 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}
11848 "VGT_PRIMITIVEID_RESET": {
11850 {"bits": [0, 31], "name": "VALUE"}
11853 "VGT_PRIMITIVE_TYPE": {
11855 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
11860 {"bits": [0, 0], "name": "REUSE_OFF"}
11863 "VGT_SHADER_STAGES_EN": {
11865 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
11866 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
11867 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
11868 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
11869 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
11870 {"bits": [8, 8], "name": "DYNAMIC_HS"}
11873 "VGT_STRMOUT_BUFFER_CONFIG": {
11875 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"},
11876 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"},
11877 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"},
11878 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"}
11881 "VGT_STRMOUT_CONFIG": {
11883 {"bits": [0, 0], "name": "STREAMOUT_0_EN"},
11884 {"bits": [1, 1], "name": "STREAMOUT_1_EN"},
11885 {"bits": [2, 2], "name": "STREAMOUT_2_EN"},
11886 {"bits": [3, 3], "name": "STREAMOUT_3_EN"},
11887 {"bits": [4, 6], "name": "RAST_STREAM"},
11888 {"bits": [8, 11], "name": "RAST_STREAM_MASK"},
11889 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"}
11892 "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
11894 {"bits": [0, 8], "name": "VERTEX_STRIDE"}
11897 "VGT_STRMOUT_VTX_STRIDE_0": {
11899 {"bits": [0, 9], "name": "STRIDE"}
11902 "VGT_SYS_CONFIG": {
11904 {"bits": [0, 0], "name": "DUAL_CORE_EN"},
11905 {"bits": [1, 6], "name": "MAX_LS_HS_THDGRP"},
11906 {"bits": [7, 7], "name": "ADC_EVENT_FILTER_DISABLE"}
11909 "VGT_TF_MEMORY_BASE": {
11911 {"bits": [0, 31], "name": "BASE"}
11916 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
11917 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
11918 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
11919 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"},
11920 {"bits": [9, 9], "name": "DEPRECATED"},
11921 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
11922 {"bits": [14, 14], "name": "DISABLE_DONUTS"},
11923 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}
11926 "VGT_TF_RING_SIZE": {
11928 {"bits": [0, 15], "name": "SIZE"}
11931 "VGT_VERTEX_REUSE_BLOCK_CNTL": {
11933 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"}
11936 "VGT_VTX_CNT_EN": {
11938 {"bits": [0, 0], "name": "VTX_CNT_EN"}
11941 "VGT_VTX_VECT_EJECT_REG": {
11943 {"bits": [0, 9], "name": "PRIM_COUNT"}