ac/registers: don't use the si, cik, vi names, use gfxN
[mesa.git] / src / amd / registers / pkt3.json
1 {
2 "enums": {
3 "COMMAND__SAIC": {
4 "entries": [
5 {"name": "INCREMENT", "value": 0},
6 {"name": "NO_INCREMENT", "value": 1}
7 ]
8 },
9 "COMMAND__SAS": {
10 "entries": [
11 {"name": "MEMORY", "value": 0},
12 {"name": "REGISTER", "value": 1}
13 ]
14 },
15 "COMMAND__SRC_SWAP": {
16 "entries": [
17 {"name": "NONE", "value": 0},
18 {"name": "8_IN_16", "value": 1},
19 {"name": "8_IN_32", "value": 2},
20 {"name": "8_IN_64", "value": 3}
21 ]
22 },
23 "CONTROL__DST_SEL": {
24 "entries": [
25 {"name": "MEM_MAPPED_REGISTER", "value": 0},
26 {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
27 {"name": "TC_L2", "value": 2},
28 {"name": "GDS", "value": 3},
29 {"name": "RESERVED", "value": 4}
30 ]
31 },
32 "CONTROL__DST_SEL_cik": {
33 "entries": [
34 {"name": "MEM_MAPPED_REGISTER", "value": 0},
35 {"comment": "sync across GRBM", "name": "MEM_GRBM", "value": 1},
36 {"name": "TC_L2", "value": 2},
37 {"name": "GDS", "value": 3},
38 {"name": "RESERVED", "value": 4},
39 {"name": "MEM", "value": 5}
40 ]
41 },
42 "CONTROL__ENGINE_SEL": {
43 "entries": [
44 {"name": "ME", "value": 0},
45 {"name": "PFP", "value": 1},
46 {"name": "CE", "value": 2},
47 {"name": "DE", "value": 3}
48 ]
49 },
50 "CP_DMA_WORD1__DST_SEL": {
51 "entries": [
52 {"name": "DST_ADDR", "value": 0},
53 {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1}
54 ]
55 },
56 "CP_DMA_WORD1__DST_SEL_cik": {
57 "entries": [
58 {"name": "DST_ADDR", "value": 0},
59 {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
60 {"name": "DST_ADDR_TC_L2", "value": 3}
61 ]
62 },
63 "CP_DMA_WORD1__DST_SEL_gfx9": {
64 "entries": [
65 {"name": "DST_ADDR", "value": 0},
66 {"comment": "program DAS to 1 as well", "name": "GDS", "value": 1},
67 {"name": "NOWHERE", "value": 2},
68 {"name": "DST_ADDR_TC_L2", "value": 3}
69 ]
70 },
71 "CP_DMA_WORD1__ENGINE": {
72 "entries": [
73 {"name": "ME", "value": 0},
74 {"name": "PFP", "value": 1}
75 ]
76 },
77 "CP_DMA_WORD1__SRC_SEL": {
78 "entries": [
79 {"name": "SRC_ADDR", "value": 0},
80 {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
81 {"name": "DATA", "value": 2}
82 ]
83 },
84 "CP_DMA_WORD1__SRC_SEL_cik": {
85 "entries": [
86 {"name": "SRC_ADDR", "value": 0},
87 {"comment": "program SAS to 1 as well", "name": "GDS", "value": 1},
88 {"name": "DATA", "value": 2},
89 {"name": "SRC_ADDR_TC_L2", "value": 3}
90 ]
91 }
92 },
93 "register_mappings": [
94 {
95 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney"],
96 "map": {"at": 1044, "to": "pkt3"},
97 "name": "COMMAND",
98 "type_ref": "COMMAND"
99 },
100 {
101 "chips": ["gfx9"],
102 "map": {"at": 1044, "to": "pkt3"},
103 "name": "COMMAND",
104 "type_ref": "COMMAND_gfx9"
105 },
106 {
107 "chips": ["gfx6"],
108 "map": {"at": 880, "to": "pkt3"},
109 "name": "CONTROL",
110 "type_ref": "CONTROL"
111 },
112 {
113 "chips": ["gfx7", "gfx8", "fiji", "stoney", "gfx9"],
114 "map": {"at": 880, "to": "pkt3"},
115 "name": "CONTROL",
116 "type_ref": "CONTROL_cik"
117 },
118 {
119 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
120 "map": {"at": 1040, "to": "pkt3"},
121 "name": "CP_DMA_WORD0",
122 "type_ref": "CP_DMA_WORD0"
123 },
124 {
125 "chips": ["gfx6"],
126 "map": {"at": 1041, "to": "pkt3"},
127 "name": "CP_DMA_WORD1",
128 "type_ref": "CP_DMA_WORD1"
129 },
130 {
131 "chips": ["gfx7", "gfx8", "fiji", "stoney"],
132 "map": {"at": 1041, "to": "pkt3"},
133 "name": "CP_DMA_WORD1",
134 "type_ref": "CP_DMA_WORD1_cik"
135 },
136 {
137 "chips": ["gfx9"],
138 "map": {"at": 1041, "to": "pkt3"},
139 "name": "CP_DMA_WORD1",
140 "type_ref": "CP_DMA_WORD1_gfx9"
141 },
142 {
143 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
144 "map": {"at": 1042, "to": "pkt3"},
145 "name": "CP_DMA_WORD2",
146 "type_ref": "CP_DMA_WORD2"
147 },
148 {
149 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
150 "map": {"at": 1043, "to": "pkt3"},
151 "name": "CP_DMA_WORD3",
152 "type_ref": "CP_DMA_WORD3"
153 },
154 {
155 "chips": ["gfx6"],
156 "map": {"at": 1280, "to": "pkt3"},
157 "name": "DMA_DATA_WORD0",
158 "type_ref": "DMA_DATA_WORD0"
159 },
160 {
161 "chips": ["gfx7", "gfx8", "fiji", "stoney"],
162 "map": {"at": 1280, "to": "pkt3"},
163 "name": "DMA_DATA_WORD0",
164 "type_ref": "DMA_DATA_WORD0_cik"
165 },
166 {
167 "chips": ["gfx9"],
168 "map": {"at": 1280, "to": "pkt3"},
169 "name": "DMA_DATA_WORD0",
170 "type_ref": "DMA_DATA_WORD0_gfx9"
171 },
172 {
173 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
174 "map": {"at": 882, "to": "pkt3"},
175 "name": "DST_ADDR_HI"
176 },
177 {
178 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
179 "map": {"at": 1284, "to": "pkt3"},
180 "name": "DST_ADDR_HI"
181 },
182 {
183 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
184 "map": {"at": 881, "to": "pkt3"},
185 "name": "DST_ADDR_LO"
186 },
187 {
188 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
189 "map": {"at": 1283, "to": "pkt3"},
190 "name": "DST_ADDR_LO"
191 },
192 {
193 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
194 "map": {"at": 1009, "to": "pkt3"},
195 "name": "IB_BASE_HI"
196 },
197 {
198 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
199 "map": {"at": 1008, "to": "pkt3"},
200 "name": "IB_BASE_LO"
201 },
202 {
203 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
204 "map": {"at": 1010, "to": "pkt3"},
205 "name": "IB_CONTROL",
206 "type_ref": "IB_CONTROL"
207 },
208 {
209 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
210 "map": {"at": 1282, "to": "pkt3"},
211 "name": "SRC_ADDR_HI"
212 },
213 {
214 "chips": ["gfx6", "gfx7", "gfx8", "fiji", "stoney", "gfx9"],
215 "map": {"at": 1281, "to": "pkt3"},
216 "name": "SRC_ADDR_LO"
217 }
218 ],
219 "register_types": {
220 "COMMAND": {
221 "fields": [
222 {"bits": [0, 20], "name": "BYTE_COUNT"},
223 {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"},
224 {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"},
225 {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"},
226 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
227 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
228 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
229 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
230 {"bits": [30, 30], "name": "RAW_WAIT"}
231 ]
232 },
233 "COMMAND_gfx9": {
234 "fields": [
235 {"bits": [0, 25], "name": "BYTE_COUNT"},
236 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"},
237 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"},
238 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"},
239 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"},
240 {"bits": [30, 30], "name": "RAW_WAIT"},
241 {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"}
242 ]
243 },
244 "CONTROL": {
245 "fields": [
246 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"},
247 {"bits": [16, 16], "name": "WR_ONE_ADDR"},
248 {"bits": [20, 20], "name": "WR_CONFIRM"},
249 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
250 ]
251 },
252 "CONTROL_cik": {
253 "fields": [
254 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"},
255 {"bits": [16, 16], "name": "WR_ONE_ADDR"},
256 {"bits": [20, 20], "name": "WR_CONFIRM"},
257 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"}
258 ]
259 },
260 "CP_DMA_WORD0": {
261 "fields": [
262 {"bits": [0, 31], "name": "SRC_ADDR_LO"}
263 ]
264 },
265 "CP_DMA_WORD1": {
266 "fields": [
267 {"bits": [0, 15], "name": "SRC_ADDR_HI"},
268 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
269 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
270 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
271 {"bits": [31, 31], "name": "CP_SYNC"}
272 ]
273 },
274 "CP_DMA_WORD1_cik": {
275 "fields": [
276 {"bits": [0, 15], "name": "SRC_ADDR_HI"},
277 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
278 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
279 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
280 {"bits": [31, 31], "name": "CP_SYNC"}
281 ]
282 },
283 "CP_DMA_WORD1_gfx9": {
284 "fields": [
285 {"bits": [0, 15], "name": "SRC_ADDR_HI"},
286 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
287 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
288 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
289 {"bits": [31, 31], "name": "CP_SYNC"}
290 ]
291 },
292 "CP_DMA_WORD2": {
293 "fields": [
294 {"bits": [0, 31], "name": "DST_ADDR_LO"}
295 ]
296 },
297 "CP_DMA_WORD3": {
298 "fields": [
299 {"bits": [0, 15], "name": "DST_ADDR_HI"}
300 ]
301 },
302 "DMA_DATA_WORD0": {
303 "fields": [
304 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
305 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"},
306 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"},
307 {"bits": [31, 31], "name": "CP_SYNC"}
308 ]
309 },
310 "DMA_DATA_WORD0_cik": {
311 "fields": [
312 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
313 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
314 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"},
315 {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
316 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
317 {"bits": [31, 31], "name": "CP_SYNC"}
318 ]
319 },
320 "DMA_DATA_WORD0_gfx9": {
321 "fields": [
322 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"},
323 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
324 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"},
325 {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
326 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"},
327 {"bits": [31, 31], "name": "CP_SYNC"}
328 ]
329 },
330 "IB_CONTROL": {
331 "fields": [
332 {"bits": [0, 19], "name": "IB_SIZE"},
333 {"bits": [20, 20], "name": "CHAIN"},
334 {"bits": [23, 23], "name": "VALID"}
335 ]
336 }
337 }
338 }