2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
33 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
41 RADV_PREFETCH_VBO_DESCRIPTORS
= (1 << 0),
42 RADV_PREFETCH_VS
= (1 << 1),
43 RADV_PREFETCH_TCS
= (1 << 2),
44 RADV_PREFETCH_TES
= (1 << 3),
45 RADV_PREFETCH_GS
= (1 << 4),
46 RADV_PREFETCH_PS
= (1 << 5),
47 RADV_PREFETCH_SHADERS
= (RADV_PREFETCH_VS
|
54 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
55 struct radv_image
*image
,
56 VkImageLayout src_layout
,
58 VkImageLayout dst_layout
,
62 const VkImageSubresourceRange
*range
,
63 struct radv_sample_locations_state
*sample_locs
);
65 const struct radv_dynamic_state default_dynamic_state
= {
78 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
83 .stencil_compare_mask
= {
87 .stencil_write_mask
= {
91 .stencil_reference
= {
101 .primitive_topology
= 0u,
105 radv_bind_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
,
106 const struct radv_dynamic_state
*src
)
108 struct radv_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
109 uint32_t copy_mask
= src
->mask
;
110 uint32_t dest_mask
= 0;
112 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
113 dest
->sample_location
.count
= src
->sample_location
.count
;
115 if (copy_mask
& RADV_DYNAMIC_VIEWPORT
) {
116 if (dest
->viewport
.count
!= src
->viewport
.count
) {
117 dest
->viewport
.count
= src
->viewport
.count
;
118 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
121 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
122 src
->viewport
.count
* sizeof(VkViewport
))) {
123 typed_memcpy(dest
->viewport
.viewports
,
124 src
->viewport
.viewports
,
125 src
->viewport
.count
);
126 dest_mask
|= RADV_DYNAMIC_VIEWPORT
;
130 if (copy_mask
& RADV_DYNAMIC_SCISSOR
) {
131 if (dest
->scissor
.count
!= src
->scissor
.count
) {
132 dest
->scissor
.count
= src
->scissor
.count
;
133 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
136 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
137 src
->scissor
.count
* sizeof(VkRect2D
))) {
138 typed_memcpy(dest
->scissor
.scissors
,
139 src
->scissor
.scissors
, src
->scissor
.count
);
140 dest_mask
|= RADV_DYNAMIC_SCISSOR
;
144 if (copy_mask
& RADV_DYNAMIC_LINE_WIDTH
) {
145 if (dest
->line_width
!= src
->line_width
) {
146 dest
->line_width
= src
->line_width
;
147 dest_mask
|= RADV_DYNAMIC_LINE_WIDTH
;
151 if (copy_mask
& RADV_DYNAMIC_DEPTH_BIAS
) {
152 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
153 sizeof(src
->depth_bias
))) {
154 dest
->depth_bias
= src
->depth_bias
;
155 dest_mask
|= RADV_DYNAMIC_DEPTH_BIAS
;
159 if (copy_mask
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
160 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
161 sizeof(src
->blend_constants
))) {
162 typed_memcpy(dest
->blend_constants
,
163 src
->blend_constants
, 4);
164 dest_mask
|= RADV_DYNAMIC_BLEND_CONSTANTS
;
168 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
169 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
170 sizeof(src
->depth_bounds
))) {
171 dest
->depth_bounds
= src
->depth_bounds
;
172 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS
;
176 if (copy_mask
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
177 if (memcmp(&dest
->stencil_compare_mask
,
178 &src
->stencil_compare_mask
,
179 sizeof(src
->stencil_compare_mask
))) {
180 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
181 dest_mask
|= RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
185 if (copy_mask
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
186 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
187 sizeof(src
->stencil_write_mask
))) {
188 dest
->stencil_write_mask
= src
->stencil_write_mask
;
189 dest_mask
|= RADV_DYNAMIC_STENCIL_WRITE_MASK
;
193 if (copy_mask
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
194 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
195 sizeof(src
->stencil_reference
))) {
196 dest
->stencil_reference
= src
->stencil_reference
;
197 dest_mask
|= RADV_DYNAMIC_STENCIL_REFERENCE
;
201 if (copy_mask
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
202 if (memcmp(&dest
->discard_rectangle
.rectangles
, &src
->discard_rectangle
.rectangles
,
203 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
204 typed_memcpy(dest
->discard_rectangle
.rectangles
,
205 src
->discard_rectangle
.rectangles
,
206 src
->discard_rectangle
.count
);
207 dest_mask
|= RADV_DYNAMIC_DISCARD_RECTANGLE
;
211 if (copy_mask
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
212 if (dest
->sample_location
.per_pixel
!= src
->sample_location
.per_pixel
||
213 dest
->sample_location
.grid_size
.width
!= src
->sample_location
.grid_size
.width
||
214 dest
->sample_location
.grid_size
.height
!= src
->sample_location
.grid_size
.height
||
215 memcmp(&dest
->sample_location
.locations
,
216 &src
->sample_location
.locations
,
217 src
->sample_location
.count
* sizeof(VkSampleLocationEXT
))) {
218 dest
->sample_location
.per_pixel
= src
->sample_location
.per_pixel
;
219 dest
->sample_location
.grid_size
= src
->sample_location
.grid_size
;
220 typed_memcpy(dest
->sample_location
.locations
,
221 src
->sample_location
.locations
,
222 src
->sample_location
.count
);
223 dest_mask
|= RADV_DYNAMIC_SAMPLE_LOCATIONS
;
227 if (copy_mask
& RADV_DYNAMIC_LINE_STIPPLE
) {
228 if (memcmp(&dest
->line_stipple
, &src
->line_stipple
,
229 sizeof(src
->line_stipple
))) {
230 dest
->line_stipple
= src
->line_stipple
;
231 dest_mask
|= RADV_DYNAMIC_LINE_STIPPLE
;
235 if (copy_mask
& RADV_DYNAMIC_CULL_MODE
) {
236 if (dest
->cull_mode
!= src
->cull_mode
) {
237 dest
->cull_mode
= src
->cull_mode
;
238 dest_mask
|= RADV_DYNAMIC_CULL_MODE
;
242 if (copy_mask
& RADV_DYNAMIC_FRONT_FACE
) {
243 if (dest
->front_face
!= src
->front_face
) {
244 dest
->front_face
= src
->front_face
;
245 dest_mask
|= RADV_DYNAMIC_FRONT_FACE
;
249 if (copy_mask
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
250 if (dest
->primitive_topology
!= src
->primitive_topology
) {
251 dest
->primitive_topology
= src
->primitive_topology
;
252 dest_mask
|= RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
256 if (copy_mask
& RADV_DYNAMIC_DEPTH_TEST_ENABLE
) {
257 if (dest
->depth_test_enable
!= src
->depth_test_enable
) {
258 dest
->depth_test_enable
= src
->depth_test_enable
;
259 dest_mask
|= RADV_DYNAMIC_DEPTH_TEST_ENABLE
;
263 if (copy_mask
& RADV_DYNAMIC_DEPTH_WRITE_ENABLE
) {
264 if (dest
->depth_write_enable
!= src
->depth_write_enable
) {
265 dest
->depth_write_enable
= src
->depth_write_enable
;
266 dest_mask
|= RADV_DYNAMIC_DEPTH_WRITE_ENABLE
;
270 if (copy_mask
& RADV_DYNAMIC_DEPTH_COMPARE_OP
) {
271 if (dest
->depth_compare_op
!= src
->depth_compare_op
) {
272 dest
->depth_compare_op
= src
->depth_compare_op
;
273 dest_mask
|= RADV_DYNAMIC_DEPTH_COMPARE_OP
;
277 if (copy_mask
& RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
) {
278 if (dest
->depth_bounds_test_enable
!= src
->depth_bounds_test_enable
) {
279 dest
->depth_bounds_test_enable
= src
->depth_bounds_test_enable
;
280 dest_mask
|= RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
284 if (copy_mask
& RADV_DYNAMIC_STENCIL_TEST_ENABLE
) {
285 if (dest
->stencil_test_enable
!= src
->stencil_test_enable
) {
286 dest
->stencil_test_enable
= src
->stencil_test_enable
;
287 dest_mask
|= RADV_DYNAMIC_STENCIL_TEST_ENABLE
;
291 if (copy_mask
& RADV_DYNAMIC_STENCIL_OP
) {
292 if (memcmp(&dest
->stencil_op
, &src
->stencil_op
,
293 sizeof(src
->stencil_op
))) {
294 dest
->stencil_op
= src
->stencil_op
;
295 dest_mask
|= RADV_DYNAMIC_STENCIL_OP
;
299 cmd_buffer
->state
.dirty
|= dest_mask
;
303 radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer
,
304 struct radv_pipeline
*pipeline
)
306 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
307 struct radv_shader_info
*info
;
309 if (!pipeline
->streamout_shader
||
310 cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
313 info
= &pipeline
->streamout_shader
->info
;
314 for (int i
= 0; i
< MAX_SO_BUFFERS
; i
++)
315 so
->stride_in_dw
[i
] = info
->so
.strides
[i
];
317 so
->enabled_stream_buffers_mask
= info
->so
.enabled_stream_buffers_mask
;
320 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
)
322 return cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
323 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
326 enum ring_type
radv_queue_family_to_ring(int f
) {
328 case RADV_QUEUE_GENERAL
:
330 case RADV_QUEUE_COMPUTE
:
332 case RADV_QUEUE_TRANSFER
:
335 unreachable("Unknown queue family");
340 radv_destroy_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
342 list_del(&cmd_buffer
->pool_link
);
344 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
345 &cmd_buffer
->upload
.list
, list
) {
346 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
351 if (cmd_buffer
->upload
.upload_bo
)
352 cmd_buffer
->device
->ws
->buffer_destroy(cmd_buffer
->upload
.upload_bo
);
355 cmd_buffer
->device
->ws
->cs_destroy(cmd_buffer
->cs
);
357 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
358 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
360 vk_object_base_finish(&cmd_buffer
->base
);
361 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
364 static VkResult
radv_create_cmd_buffer(
365 struct radv_device
* device
,
366 struct radv_cmd_pool
* pool
,
367 VkCommandBufferLevel level
,
368 VkCommandBuffer
* pCommandBuffer
)
370 struct radv_cmd_buffer
*cmd_buffer
;
372 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
374 if (cmd_buffer
== NULL
)
375 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
377 vk_object_base_init(&device
->vk
, &cmd_buffer
->base
,
378 VK_OBJECT_TYPE_COMMAND_BUFFER
);
380 cmd_buffer
->device
= device
;
381 cmd_buffer
->pool
= pool
;
382 cmd_buffer
->level
= level
;
384 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
385 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
387 ring
= radv_queue_family_to_ring(cmd_buffer
->queue_family_index
);
389 cmd_buffer
->cs
= device
->ws
->cs_create(device
->ws
, ring
);
390 if (!cmd_buffer
->cs
) {
391 radv_destroy_cmd_buffer(cmd_buffer
);
392 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
395 *pCommandBuffer
= radv_cmd_buffer_to_handle(cmd_buffer
);
397 list_inithead(&cmd_buffer
->upload
.list
);
403 radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
)
405 cmd_buffer
->device
->ws
->cs_reset(cmd_buffer
->cs
);
407 list_for_each_entry_safe(struct radv_cmd_buffer_upload
, up
,
408 &cmd_buffer
->upload
.list
, list
) {
409 cmd_buffer
->device
->ws
->buffer_destroy(up
->upload_bo
);
414 cmd_buffer
->push_constant_stages
= 0;
415 cmd_buffer
->scratch_size_per_wave_needed
= 0;
416 cmd_buffer
->scratch_waves_wanted
= 0;
417 cmd_buffer
->compute_scratch_size_per_wave_needed
= 0;
418 cmd_buffer
->compute_scratch_waves_wanted
= 0;
419 cmd_buffer
->esgs_ring_size_needed
= 0;
420 cmd_buffer
->gsvs_ring_size_needed
= 0;
421 cmd_buffer
->tess_rings_needed
= false;
422 cmd_buffer
->gds_needed
= false;
423 cmd_buffer
->gds_oa_needed
= false;
424 cmd_buffer
->sample_positions_needed
= false;
426 if (cmd_buffer
->upload
.upload_bo
)
427 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
428 cmd_buffer
->upload
.upload_bo
);
429 cmd_buffer
->upload
.offset
= 0;
431 cmd_buffer
->record_result
= VK_SUCCESS
;
433 memset(cmd_buffer
->vertex_bindings
, 0, sizeof(cmd_buffer
->vertex_bindings
));
435 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++) {
436 cmd_buffer
->descriptors
[i
].dirty
= 0;
437 cmd_buffer
->descriptors
[i
].valid
= 0;
438 cmd_buffer
->descriptors
[i
].push_dirty
= false;
441 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
442 cmd_buffer
->queue_family_index
== RADV_QUEUE_GENERAL
) {
443 unsigned num_db
= cmd_buffer
->device
->physical_device
->rad_info
.num_render_backends
;
444 unsigned fence_offset
, eop_bug_offset
;
447 radv_cmd_buffer_upload_alloc(cmd_buffer
, 8, 8, &fence_offset
,
450 cmd_buffer
->gfx9_fence_va
=
451 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
452 cmd_buffer
->gfx9_fence_va
+= fence_offset
;
454 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
455 /* Allocate a buffer for the EOP bug on GFX9. */
456 radv_cmd_buffer_upload_alloc(cmd_buffer
, 16 * num_db
, 8,
457 &eop_bug_offset
, &fence_ptr
);
458 cmd_buffer
->gfx9_eop_bug_va
=
459 radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
460 cmd_buffer
->gfx9_eop_bug_va
+= eop_bug_offset
;
464 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_INITIAL
;
466 return cmd_buffer
->record_result
;
470 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer
,
474 struct radeon_winsys_bo
*bo
;
475 struct radv_cmd_buffer_upload
*upload
;
476 struct radv_device
*device
= cmd_buffer
->device
;
478 new_size
= MAX2(min_needed
, 16 * 1024);
479 new_size
= MAX2(new_size
, 2 * cmd_buffer
->upload
.size
);
481 bo
= device
->ws
->buffer_create(device
->ws
,
484 RADEON_FLAG_CPU_ACCESS
|
485 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
488 RADV_BO_PRIORITY_UPLOAD_BUFFER
);
491 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
495 radv_cs_add_buffer(device
->ws
, cmd_buffer
->cs
, bo
);
496 if (cmd_buffer
->upload
.upload_bo
) {
497 upload
= malloc(sizeof(*upload
));
500 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
501 device
->ws
->buffer_destroy(bo
);
505 memcpy(upload
, &cmd_buffer
->upload
, sizeof(*upload
));
506 list_add(&upload
->list
, &cmd_buffer
->upload
.list
);
509 cmd_buffer
->upload
.upload_bo
= bo
;
510 cmd_buffer
->upload
.size
= new_size
;
511 cmd_buffer
->upload
.offset
= 0;
512 cmd_buffer
->upload
.map
= device
->ws
->buffer_map(cmd_buffer
->upload
.upload_bo
);
514 if (!cmd_buffer
->upload
.map
) {
515 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
523 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
526 unsigned *out_offset
,
529 assert(util_is_power_of_two_nonzero(alignment
));
531 uint64_t offset
= align(cmd_buffer
->upload
.offset
, alignment
);
532 if (offset
+ size
> cmd_buffer
->upload
.size
) {
533 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer
, size
))
538 *out_offset
= offset
;
539 *ptr
= cmd_buffer
->upload
.map
+ offset
;
541 cmd_buffer
->upload
.offset
= offset
+ size
;
546 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
547 unsigned size
, unsigned alignment
,
548 const void *data
, unsigned *out_offset
)
552 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
, alignment
,
553 out_offset
, (void **)&ptr
))
557 memcpy(ptr
, data
, size
);
563 radv_emit_write_data_packet(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
564 unsigned count
, const uint32_t *data
)
566 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
568 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4 + count
);
570 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
571 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
572 S_370_WR_CONFIRM(1) |
573 S_370_ENGINE_SEL(V_370_ME
));
575 radeon_emit(cs
, va
>> 32);
576 radeon_emit_array(cs
, data
, count
);
579 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
)
581 struct radv_device
*device
= cmd_buffer
->device
;
582 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
585 va
= radv_buffer_get_va(device
->trace_bo
);
586 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
)
589 ++cmd_buffer
->state
.trace_id
;
590 radv_emit_write_data_packet(cmd_buffer
, va
, 1,
591 &cmd_buffer
->state
.trace_id
);
593 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 2);
595 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
596 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(cmd_buffer
->state
.trace_id
));
600 radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer
,
601 enum radv_cmd_flush_bits flags
)
603 if (unlikely(cmd_buffer
->device
->thread_trace_bo
)) {
604 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
605 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER
) | EVENT_INDEX(0));
608 if (cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_SYNC_SHADERS
) {
609 assert(flags
& (RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
610 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
));
612 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 4);
614 /* Force wait for graphics or compute engines to be idle. */
615 si_cs_emit_cache_flush(cmd_buffer
->cs
,
616 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
617 &cmd_buffer
->gfx9_fence_idx
,
618 cmd_buffer
->gfx9_fence_va
,
619 radv_cmd_buffer_uses_mec(cmd_buffer
),
620 flags
, cmd_buffer
->gfx9_eop_bug_va
);
623 if (unlikely(cmd_buffer
->device
->trace_bo
))
624 radv_cmd_buffer_trace_emit(cmd_buffer
);
628 radv_save_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
629 struct radv_pipeline
*pipeline
, enum ring_type ring
)
631 struct radv_device
*device
= cmd_buffer
->device
;
635 va
= radv_buffer_get_va(device
->trace_bo
);
645 assert(!"invalid ring type");
648 uint64_t pipeline_address
= (uintptr_t)pipeline
;
649 data
[0] = pipeline_address
;
650 data
[1] = pipeline_address
>> 32;
652 radv_emit_write_data_packet(cmd_buffer
, va
, 2, data
);
655 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
656 VkPipelineBindPoint bind_point
,
657 struct radv_descriptor_set
*set
,
660 struct radv_descriptor_state
*descriptors_state
=
661 radv_get_descriptors_state(cmd_buffer
, bind_point
);
663 descriptors_state
->sets
[idx
] = set
;
665 descriptors_state
->valid
|= (1u << idx
); /* active descriptors */
666 descriptors_state
->dirty
|= (1u << idx
);
670 radv_save_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
671 VkPipelineBindPoint bind_point
)
673 struct radv_descriptor_state
*descriptors_state
=
674 radv_get_descriptors_state(cmd_buffer
, bind_point
);
675 struct radv_device
*device
= cmd_buffer
->device
;
676 uint32_t data
[MAX_SETS
* 2] = {};
679 va
= radv_buffer_get_va(device
->trace_bo
) + 24;
681 for_each_bit(i
, descriptors_state
->valid
) {
682 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
683 data
[i
* 2] = (uint64_t)(uintptr_t)set
;
684 data
[i
* 2 + 1] = (uint64_t)(uintptr_t)set
>> 32;
687 radv_emit_write_data_packet(cmd_buffer
, va
, MAX_SETS
* 2, data
);
690 struct radv_userdata_info
*
691 radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
692 gl_shader_stage stage
,
695 struct radv_shader_variant
*shader
= radv_get_shader(pipeline
, stage
);
696 return &shader
->info
.user_sgprs_locs
.shader_data
[idx
];
700 radv_emit_userdata_address(struct radv_cmd_buffer
*cmd_buffer
,
701 struct radv_pipeline
*pipeline
,
702 gl_shader_stage stage
,
703 int idx
, uint64_t va
)
705 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
706 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
707 if (loc
->sgpr_idx
== -1)
710 assert(loc
->num_sgprs
== 1);
712 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
713 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
717 radv_emit_descriptor_pointers(struct radv_cmd_buffer
*cmd_buffer
,
718 struct radv_pipeline
*pipeline
,
719 struct radv_descriptor_state
*descriptors_state
,
720 gl_shader_stage stage
)
722 struct radv_device
*device
= cmd_buffer
->device
;
723 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
724 uint32_t sh_base
= pipeline
->user_data_0
[stage
];
725 struct radv_userdata_locations
*locs
=
726 &pipeline
->shaders
[stage
]->info
.user_sgprs_locs
;
727 unsigned mask
= locs
->descriptor_sets_enabled
;
729 mask
&= descriptors_state
->dirty
& descriptors_state
->valid
;
734 u_bit_scan_consecutive_range(&mask
, &start
, &count
);
736 struct radv_userdata_info
*loc
= &locs
->descriptor_sets
[start
];
737 unsigned sh_offset
= sh_base
+ loc
->sgpr_idx
* 4;
739 radv_emit_shader_pointer_head(cs
, sh_offset
, count
, true);
740 for (int i
= 0; i
< count
; i
++) {
741 struct radv_descriptor_set
*set
=
742 descriptors_state
->sets
[start
+ i
];
744 radv_emit_shader_pointer_body(device
, cs
, set
->va
, true);
750 * Convert the user sample locations to hardware sample locations (the values
751 * that will be emitted by PA_SC_AA_SAMPLE_LOCS_PIXEL_*).
754 radv_convert_user_sample_locs(struct radv_sample_locations_state
*state
,
755 uint32_t x
, uint32_t y
, VkOffset2D
*sample_locs
)
757 uint32_t x_offset
= x
% state
->grid_size
.width
;
758 uint32_t y_offset
= y
% state
->grid_size
.height
;
759 uint32_t num_samples
= (uint32_t)state
->per_pixel
;
760 VkSampleLocationEXT
*user_locs
;
761 uint32_t pixel_offset
;
763 pixel_offset
= (x_offset
+ y_offset
* state
->grid_size
.width
) * num_samples
;
765 assert(pixel_offset
<= MAX_SAMPLE_LOCATIONS
);
766 user_locs
= &state
->locations
[pixel_offset
];
768 for (uint32_t i
= 0; i
< num_samples
; i
++) {
769 float shifted_pos_x
= user_locs
[i
].x
- 0.5;
770 float shifted_pos_y
= user_locs
[i
].y
- 0.5;
772 int32_t scaled_pos_x
= floorf(shifted_pos_x
* 16);
773 int32_t scaled_pos_y
= floorf(shifted_pos_y
* 16);
775 sample_locs
[i
].x
= CLAMP(scaled_pos_x
, -8, 7);
776 sample_locs
[i
].y
= CLAMP(scaled_pos_y
, -8, 7);
781 * Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask based on hardware sample
785 radv_compute_sample_locs_pixel(uint32_t num_samples
, VkOffset2D
*sample_locs
,
786 uint32_t *sample_locs_pixel
)
788 for (uint32_t i
= 0; i
< num_samples
; i
++) {
789 uint32_t sample_reg_idx
= i
/ 4;
790 uint32_t sample_loc_idx
= i
% 4;
791 int32_t pos_x
= sample_locs
[i
].x
;
792 int32_t pos_y
= sample_locs
[i
].y
;
794 uint32_t shift_x
= 8 * sample_loc_idx
;
795 uint32_t shift_y
= shift_x
+ 4;
797 sample_locs_pixel
[sample_reg_idx
] |= (pos_x
& 0xf) << shift_x
;
798 sample_locs_pixel
[sample_reg_idx
] |= (pos_y
& 0xf) << shift_y
;
803 * Compute the PA_SC_CENTROID_PRIORITY_* mask based on the top left hardware
807 radv_compute_centroid_priority(struct radv_cmd_buffer
*cmd_buffer
,
808 VkOffset2D
*sample_locs
,
809 uint32_t num_samples
)
811 uint32_t centroid_priorities
[num_samples
];
812 uint32_t sample_mask
= num_samples
- 1;
813 uint32_t distances
[num_samples
];
814 uint64_t centroid_priority
= 0;
816 /* Compute the distances from center for each sample. */
817 for (int i
= 0; i
< num_samples
; i
++) {
818 distances
[i
] = (sample_locs
[i
].x
* sample_locs
[i
].x
) +
819 (sample_locs
[i
].y
* sample_locs
[i
].y
);
822 /* Compute the centroid priorities by looking at the distances array. */
823 for (int i
= 0; i
< num_samples
; i
++) {
824 uint32_t min_idx
= 0;
826 for (int j
= 1; j
< num_samples
; j
++) {
827 if (distances
[j
] < distances
[min_idx
])
831 centroid_priorities
[i
] = min_idx
;
832 distances
[min_idx
] = 0xffffffff;
835 /* Compute the final centroid priority. */
836 for (int i
= 0; i
< 8; i
++) {
838 centroid_priorities
[i
& sample_mask
] << (i
* 4);
841 return centroid_priority
<< 32 | centroid_priority
;
845 * Emit the sample locations that are specified with VK_EXT_sample_locations.
848 radv_emit_sample_locations(struct radv_cmd_buffer
*cmd_buffer
)
850 struct radv_sample_locations_state
*sample_location
=
851 &cmd_buffer
->state
.dynamic
.sample_location
;
852 uint32_t num_samples
= (uint32_t)sample_location
->per_pixel
;
853 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
854 uint32_t sample_locs_pixel
[4][2] = {};
855 VkOffset2D sample_locs
[4][8]; /* 8 is the max. sample count supported */
856 uint32_t max_sample_dist
= 0;
857 uint64_t centroid_priority
;
859 if (!cmd_buffer
->state
.dynamic
.sample_location
.count
)
862 /* Convert the user sample locations to hardware sample locations. */
863 radv_convert_user_sample_locs(sample_location
, 0, 0, sample_locs
[0]);
864 radv_convert_user_sample_locs(sample_location
, 1, 0, sample_locs
[1]);
865 radv_convert_user_sample_locs(sample_location
, 0, 1, sample_locs
[2]);
866 radv_convert_user_sample_locs(sample_location
, 1, 1, sample_locs
[3]);
868 /* Compute the PA_SC_AA_SAMPLE_LOCS_PIXEL_* mask. */
869 for (uint32_t i
= 0; i
< 4; i
++) {
870 radv_compute_sample_locs_pixel(num_samples
, sample_locs
[i
],
871 sample_locs_pixel
[i
]);
874 /* Compute the PA_SC_CENTROID_PRIORITY_* mask. */
876 radv_compute_centroid_priority(cmd_buffer
, sample_locs
[0],
879 /* Compute the maximum sample distance from the specified locations. */
880 for (unsigned i
= 0; i
< 4; ++i
) {
881 for (uint32_t j
= 0; j
< num_samples
; j
++) {
882 VkOffset2D offset
= sample_locs
[i
][j
];
883 max_sample_dist
= MAX2(max_sample_dist
,
884 MAX2(abs(offset
.x
), abs(offset
.y
)));
888 /* Emit the specified user sample locations. */
889 switch (num_samples
) {
892 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
893 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
894 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
895 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
898 radeon_set_context_reg(cs
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_pixel
[0][0]);
899 radeon_set_context_reg(cs
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_pixel
[1][0]);
900 radeon_set_context_reg(cs
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_pixel
[2][0]);
901 radeon_set_context_reg(cs
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_pixel
[3][0]);
902 radeon_set_context_reg(cs
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, sample_locs_pixel
[0][1]);
903 radeon_set_context_reg(cs
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, sample_locs_pixel
[1][1]);
904 radeon_set_context_reg(cs
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, sample_locs_pixel
[2][1]);
905 radeon_set_context_reg(cs
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, sample_locs_pixel
[3][1]);
908 unreachable("invalid number of samples");
911 /* Emit the maximum sample distance and the centroid priority. */
912 radeon_set_context_reg_rmw(cs
, R_028BE0_PA_SC_AA_CONFIG
,
913 S_028BE0_MAX_SAMPLE_DIST(max_sample_dist
),
914 ~C_028BE0_MAX_SAMPLE_DIST
);
916 radeon_set_context_reg_seq(cs
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 2);
917 radeon_emit(cs
, centroid_priority
);
918 radeon_emit(cs
, centroid_priority
>> 32);
920 /* GFX9: Flush DFSM when the AA mode changes. */
921 if (cmd_buffer
->device
->dfsm_allowed
) {
922 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
923 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
926 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
930 radv_emit_inline_push_consts(struct radv_cmd_buffer
*cmd_buffer
,
931 struct radv_pipeline
*pipeline
,
932 gl_shader_stage stage
,
933 int idx
, int count
, uint32_t *values
)
935 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, idx
);
936 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
937 if (loc
->sgpr_idx
== -1)
940 assert(loc
->num_sgprs
== count
);
942 radeon_set_sh_reg_seq(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, count
);
943 radeon_emit_array(cmd_buffer
->cs
, values
, count
);
947 radv_update_multisample_state(struct radv_cmd_buffer
*cmd_buffer
,
948 struct radv_pipeline
*pipeline
)
950 int num_samples
= pipeline
->graphics
.ms
.num_samples
;
951 struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
953 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.needs_sample_positions
)
954 cmd_buffer
->sample_positions_needed
= true;
956 if (old_pipeline
&& num_samples
== old_pipeline
->graphics
.ms
.num_samples
)
959 radv_emit_default_sample_locations(cmd_buffer
->cs
, num_samples
);
961 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
965 radv_update_binning_state(struct radv_cmd_buffer
*cmd_buffer
,
966 struct radv_pipeline
*pipeline
)
968 const struct radv_pipeline
*old_pipeline
= cmd_buffer
->state
.emitted_pipeline
;
971 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
975 old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
== pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
&&
976 old_pipeline
->graphics
.binning
.db_dfsm_control
== pipeline
->graphics
.binning
.db_dfsm_control
)
979 bool binning_flush
= false;
980 if (cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA12
||
981 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_VEGA20
||
982 cmd_buffer
->device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
||
983 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
984 binning_flush
= !old_pipeline
||
985 G_028C44_BINNING_MODE(old_pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
) !=
986 G_028C44_BINNING_MODE(pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
);
989 radeon_set_context_reg(cmd_buffer
->cs
, R_028C44_PA_SC_BINNER_CNTL_0
,
990 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
|
991 S_028C44_FLUSH_ON_BINNING_TRANSITION(!!binning_flush
));
993 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
994 radeon_set_context_reg(cmd_buffer
->cs
, R_028038_DB_DFSM_CONTROL
,
995 pipeline
->graphics
.binning
.db_dfsm_control
);
997 radeon_set_context_reg(cmd_buffer
->cs
, R_028060_DB_DFSM_CONTROL
,
998 pipeline
->graphics
.binning
.db_dfsm_control
);
1001 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1006 radv_emit_shader_prefetch(struct radv_cmd_buffer
*cmd_buffer
,
1007 struct radv_shader_variant
*shader
)
1014 va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
1016 si_cp_dma_prefetch(cmd_buffer
, va
, shader
->code_size
);
1020 radv_emit_prefetch_L2(struct radv_cmd_buffer
*cmd_buffer
,
1021 struct radv_pipeline
*pipeline
,
1022 bool vertex_stage_only
)
1024 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
1025 uint32_t mask
= state
->prefetch_L2_mask
;
1027 if (vertex_stage_only
) {
1028 /* Fast prefetch path for starting draws as soon as possible.
1030 mask
= state
->prefetch_L2_mask
& (RADV_PREFETCH_VS
|
1031 RADV_PREFETCH_VBO_DESCRIPTORS
);
1034 if (mask
& RADV_PREFETCH_VS
)
1035 radv_emit_shader_prefetch(cmd_buffer
,
1036 pipeline
->shaders
[MESA_SHADER_VERTEX
]);
1038 if (mask
& RADV_PREFETCH_VBO_DESCRIPTORS
)
1039 si_cp_dma_prefetch(cmd_buffer
, state
->vb_va
, state
->vb_size
);
1041 if (mask
& RADV_PREFETCH_TCS
)
1042 radv_emit_shader_prefetch(cmd_buffer
,
1043 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]);
1045 if (mask
& RADV_PREFETCH_TES
)
1046 radv_emit_shader_prefetch(cmd_buffer
,
1047 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]);
1049 if (mask
& RADV_PREFETCH_GS
) {
1050 radv_emit_shader_prefetch(cmd_buffer
,
1051 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]);
1052 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1053 radv_emit_shader_prefetch(cmd_buffer
, pipeline
->gs_copy_shader
);
1056 if (mask
& RADV_PREFETCH_PS
)
1057 radv_emit_shader_prefetch(cmd_buffer
,
1058 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
1060 state
->prefetch_L2_mask
&= ~mask
;
1064 radv_emit_rbplus_state(struct radv_cmd_buffer
*cmd_buffer
)
1066 if (!cmd_buffer
->device
->physical_device
->rad_info
.rbplus_allowed
)
1069 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1070 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1072 unsigned sx_ps_downconvert
= 0;
1073 unsigned sx_blend_opt_epsilon
= 0;
1074 unsigned sx_blend_opt_control
= 0;
1076 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1079 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
1080 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
1081 /* We don't set the DISABLE bits, because the HW can't have holes,
1082 * so the SPI color format is set to 32-bit 1-component. */
1083 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1087 int idx
= subpass
->color_attachments
[i
].attachment
;
1088 struct radv_color_buffer_info
*cb
= &cmd_buffer
->state
.attachments
[idx
].cb
;
1090 unsigned format
= G_028C70_FORMAT(cb
->cb_color_info
);
1091 unsigned swap
= G_028C70_COMP_SWAP(cb
->cb_color_info
);
1092 uint32_t spi_format
= (pipeline
->graphics
.col_format
>> (i
* 4)) & 0xf;
1093 uint32_t colormask
= (pipeline
->graphics
.cb_target_mask
>> (i
* 4)) & 0xf;
1095 bool has_alpha
, has_rgb
;
1097 /* Set if RGB and A are present. */
1098 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(cb
->cb_color_attrib
);
1100 if (format
== V_028C70_COLOR_8
||
1101 format
== V_028C70_COLOR_16
||
1102 format
== V_028C70_COLOR_32
)
1103 has_rgb
= !has_alpha
;
1107 /* Check the colormask and export format. */
1108 if (!(colormask
& 0x7))
1110 if (!(colormask
& 0x8))
1113 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
1118 /* Disable value checking for disabled channels. */
1120 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
1122 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
1124 /* Enable down-conversion for 32bpp and smaller formats. */
1126 case V_028C70_COLOR_8
:
1127 case V_028C70_COLOR_8_8
:
1128 case V_028C70_COLOR_8_8_8_8
:
1129 /* For 1 and 2-channel formats, use the superset thereof. */
1130 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
1131 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1132 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1133 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
1134 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
1138 case V_028C70_COLOR_5_6_5
:
1139 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1140 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
1141 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
1145 case V_028C70_COLOR_1_5_5_5
:
1146 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1147 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
1148 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
1152 case V_028C70_COLOR_4_4_4_4
:
1153 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1154 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
1155 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
1159 case V_028C70_COLOR_32
:
1160 if (swap
== V_028C70_SWAP_STD
&&
1161 spi_format
== V_028714_SPI_SHADER_32_R
)
1162 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
1163 else if (swap
== V_028C70_SWAP_ALT_REV
&&
1164 spi_format
== V_028714_SPI_SHADER_32_AR
)
1165 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
1168 case V_028C70_COLOR_16
:
1169 case V_028C70_COLOR_16_16
:
1170 /* For 1-channel formats, use the superset thereof. */
1171 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
1172 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
1173 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
1174 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
1175 if (swap
== V_028C70_SWAP_STD
||
1176 swap
== V_028C70_SWAP_STD_REV
)
1177 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
1179 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
1183 case V_028C70_COLOR_10_11_11
:
1184 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1185 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
1186 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
1190 case V_028C70_COLOR_2_10_10_10
:
1191 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
1192 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
1193 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
1199 /* Do not set the DISABLE bits for the unused attachments, as that
1200 * breaks dual source blending in SkQP and does not seem to improve
1203 if (sx_ps_downconvert
== cmd_buffer
->state
.last_sx_ps_downconvert
&&
1204 sx_blend_opt_epsilon
== cmd_buffer
->state
.last_sx_blend_opt_epsilon
&&
1205 sx_blend_opt_control
== cmd_buffer
->state
.last_sx_blend_opt_control
)
1208 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
1209 radeon_emit(cmd_buffer
->cs
, sx_ps_downconvert
);
1210 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_epsilon
);
1211 radeon_emit(cmd_buffer
->cs
, sx_blend_opt_control
);
1213 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1215 cmd_buffer
->state
.last_sx_ps_downconvert
= sx_ps_downconvert
;
1216 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= sx_blend_opt_epsilon
;
1217 cmd_buffer
->state
.last_sx_blend_opt_control
= sx_blend_opt_control
;
1221 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer
*cmd_buffer
)
1223 if (!cmd_buffer
->device
->pbb_allowed
)
1226 struct radv_binning_settings settings
=
1227 radv_get_binning_settings(cmd_buffer
->device
->physical_device
);
1228 bool break_for_new_ps
=
1229 (!cmd_buffer
->state
.emitted_pipeline
||
1230 cmd_buffer
->state
.emitted_pipeline
->shaders
[MESA_SHADER_FRAGMENT
] !=
1231 cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) &&
1232 (settings
.context_states_per_bin
> 1 ||
1233 settings
.persistent_states_per_bin
> 1);
1234 bool break_for_new_cb_target_mask
=
1235 (!cmd_buffer
->state
.emitted_pipeline
||
1236 cmd_buffer
->state
.emitted_pipeline
->graphics
.cb_target_mask
!=
1237 cmd_buffer
->state
.pipeline
->graphics
.cb_target_mask
) &&
1238 settings
.context_states_per_bin
> 1;
1240 if (!break_for_new_ps
&& !break_for_new_cb_target_mask
)
1243 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1244 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
1248 radv_emit_graphics_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
1250 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1252 if (!pipeline
|| cmd_buffer
->state
.emitted_pipeline
== pipeline
)
1255 radv_update_multisample_state(cmd_buffer
, pipeline
);
1256 radv_update_binning_state(cmd_buffer
, pipeline
);
1258 cmd_buffer
->scratch_size_per_wave_needed
= MAX2(cmd_buffer
->scratch_size_per_wave_needed
,
1259 pipeline
->scratch_bytes_per_wave
);
1260 cmd_buffer
->scratch_waves_wanted
= MAX2(cmd_buffer
->scratch_waves_wanted
,
1261 pipeline
->max_waves
);
1263 if (!cmd_buffer
->state
.emitted_pipeline
||
1264 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
!=
1265 pipeline
->graphics
.can_use_guardband
)
1266 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
1268 if (!cmd_buffer
->state
.emitted_pipeline
||
1269 cmd_buffer
->state
.emitted_pipeline
->graphics
.pa_su_sc_mode_cntl
!=
1270 pipeline
->graphics
.pa_su_sc_mode_cntl
)
1271 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE
|
1272 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE
;
1274 if (!cmd_buffer
->state
.emitted_pipeline
)
1275 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1277 if (!cmd_buffer
->state
.emitted_pipeline
||
1278 cmd_buffer
->state
.emitted_pipeline
->graphics
.db_depth_control
!=
1279 pipeline
->graphics
.db_depth_control
)
1280 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
|
1281 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
|
1282 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
|
1283 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
|
1284 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
|
1285 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP
;
1287 if (!cmd_buffer
->state
.emitted_pipeline
)
1288 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP
;
1290 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
1292 if (!cmd_buffer
->state
.emitted_pipeline
||
1293 cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.cdw
!= pipeline
->ctx_cs
.cdw
||
1294 cmd_buffer
->state
.emitted_pipeline
->ctx_cs_hash
!= pipeline
->ctx_cs_hash
||
1295 memcmp(cmd_buffer
->state
.emitted_pipeline
->ctx_cs
.buf
,
1296 pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
* 4)) {
1297 radeon_emit_array(cmd_buffer
->cs
, pipeline
->ctx_cs
.buf
, pipeline
->ctx_cs
.cdw
);
1298 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1301 radv_emit_batch_break_on_new_ps(cmd_buffer
);
1303 for (unsigned i
= 0; i
< MESA_SHADER_COMPUTE
; i
++) {
1304 if (!pipeline
->shaders
[i
])
1307 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1308 pipeline
->shaders
[i
]->bo
);
1311 if (radv_pipeline_has_gs_copy_shader(pipeline
))
1312 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
1313 pipeline
->gs_copy_shader
->bo
);
1315 if (unlikely(cmd_buffer
->device
->trace_bo
))
1316 radv_save_pipeline(cmd_buffer
, pipeline
, RING_GFX
);
1318 cmd_buffer
->state
.emitted_pipeline
= pipeline
;
1320 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_PIPELINE
;
1324 radv_emit_viewport(struct radv_cmd_buffer
*cmd_buffer
)
1326 si_write_viewport(cmd_buffer
->cs
, 0, cmd_buffer
->state
.dynamic
.viewport
.count
,
1327 cmd_buffer
->state
.dynamic
.viewport
.viewports
);
1331 radv_emit_scissor(struct radv_cmd_buffer
*cmd_buffer
)
1333 uint32_t count
= cmd_buffer
->state
.dynamic
.scissor
.count
;
1335 si_write_scissors(cmd_buffer
->cs
, 0, count
,
1336 cmd_buffer
->state
.dynamic
.scissor
.scissors
,
1337 cmd_buffer
->state
.dynamic
.viewport
.viewports
,
1338 cmd_buffer
->state
.emitted_pipeline
->graphics
.can_use_guardband
);
1340 cmd_buffer
->state
.context_roll_without_scissor_emitted
= false;
1344 radv_emit_discard_rectangle(struct radv_cmd_buffer
*cmd_buffer
)
1346 if (!cmd_buffer
->state
.dynamic
.discard_rectangle
.count
)
1349 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
1350 cmd_buffer
->state
.dynamic
.discard_rectangle
.count
* 2);
1351 for (unsigned i
= 0; i
< cmd_buffer
->state
.dynamic
.discard_rectangle
.count
; ++i
) {
1352 VkRect2D rect
= cmd_buffer
->state
.dynamic
.discard_rectangle
.rectangles
[i
];
1353 radeon_emit(cmd_buffer
->cs
, S_028210_TL_X(rect
.offset
.x
) | S_028210_TL_Y(rect
.offset
.y
));
1354 radeon_emit(cmd_buffer
->cs
, S_028214_BR_X(rect
.offset
.x
+ rect
.extent
.width
) |
1355 S_028214_BR_Y(rect
.offset
.y
+ rect
.extent
.height
));
1360 radv_emit_line_width(struct radv_cmd_buffer
*cmd_buffer
)
1362 unsigned width
= cmd_buffer
->state
.dynamic
.line_width
* 8;
1364 radeon_set_context_reg(cmd_buffer
->cs
, R_028A08_PA_SU_LINE_CNTL
,
1365 S_028A08_WIDTH(CLAMP(width
, 0, 0xFFFF)));
1369 radv_emit_blend_constants(struct radv_cmd_buffer
*cmd_buffer
)
1371 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1373 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028414_CB_BLEND_RED
, 4);
1374 radeon_emit_array(cmd_buffer
->cs
, (uint32_t *)d
->blend_constants
, 4);
1378 radv_emit_stencil(struct radv_cmd_buffer
*cmd_buffer
)
1380 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1382 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1383 R_028430_DB_STENCILREFMASK
, 2);
1384 radeon_emit(cmd_buffer
->cs
,
1385 S_028430_STENCILTESTVAL(d
->stencil_reference
.front
) |
1386 S_028430_STENCILMASK(d
->stencil_compare_mask
.front
) |
1387 S_028430_STENCILWRITEMASK(d
->stencil_write_mask
.front
) |
1388 S_028430_STENCILOPVAL(1));
1389 radeon_emit(cmd_buffer
->cs
,
1390 S_028434_STENCILTESTVAL_BF(d
->stencil_reference
.back
) |
1391 S_028434_STENCILMASK_BF(d
->stencil_compare_mask
.back
) |
1392 S_028434_STENCILWRITEMASK_BF(d
->stencil_write_mask
.back
) |
1393 S_028434_STENCILOPVAL_BF(1));
1397 radv_emit_depth_bounds(struct radv_cmd_buffer
*cmd_buffer
)
1399 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1401 radeon_set_context_reg(cmd_buffer
->cs
, R_028020_DB_DEPTH_BOUNDS_MIN
,
1402 fui(d
->depth_bounds
.min
));
1403 radeon_set_context_reg(cmd_buffer
->cs
, R_028024_DB_DEPTH_BOUNDS_MAX
,
1404 fui(d
->depth_bounds
.max
));
1408 radv_emit_depth_bias(struct radv_cmd_buffer
*cmd_buffer
)
1410 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1411 unsigned slope
= fui(d
->depth_bias
.slope
* 16.0f
);
1412 unsigned bias
= fui(d
->depth_bias
.bias
* cmd_buffer
->state
.offset_scale
);
1415 radeon_set_context_reg_seq(cmd_buffer
->cs
,
1416 R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, 5);
1417 radeon_emit(cmd_buffer
->cs
, fui(d
->depth_bias
.clamp
)); /* CLAMP */
1418 radeon_emit(cmd_buffer
->cs
, slope
); /* FRONT SCALE */
1419 radeon_emit(cmd_buffer
->cs
, bias
); /* FRONT OFFSET */
1420 radeon_emit(cmd_buffer
->cs
, slope
); /* BACK SCALE */
1421 radeon_emit(cmd_buffer
->cs
, bias
); /* BACK OFFSET */
1425 radv_emit_line_stipple(struct radv_cmd_buffer
*cmd_buffer
)
1427 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1428 uint32_t auto_reset_cntl
= 1;
1430 if (d
->primitive_topology
== V_008958_DI_PT_LINESTRIP
)
1431 auto_reset_cntl
= 2;
1433 radeon_set_context_reg(cmd_buffer
->cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1434 S_028A0C_LINE_PATTERN(d
->line_stipple
.pattern
) |
1435 S_028A0C_REPEAT_COUNT(d
->line_stipple
.factor
- 1) |
1436 S_028A0C_AUTO_RESET_CNTL(auto_reset_cntl
));
1440 radv_emit_culling(struct radv_cmd_buffer
*cmd_buffer
, uint32_t states
)
1442 unsigned pa_su_sc_mode_cntl
= cmd_buffer
->state
.pipeline
->graphics
.pa_su_sc_mode_cntl
;
1443 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1445 if (states
& RADV_CMD_DIRTY_DYNAMIC_CULL_MODE
) {
1446 pa_su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1447 pa_su_sc_mode_cntl
|= S_028814_CULL_FRONT(!!(d
->cull_mode
& VK_CULL_MODE_FRONT_BIT
));
1449 pa_su_sc_mode_cntl
&= C_028814_CULL_BACK
;
1450 pa_su_sc_mode_cntl
|= S_028814_CULL_BACK(!!(d
->cull_mode
& VK_CULL_MODE_BACK_BIT
));
1453 if (states
& RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE
) {
1454 pa_su_sc_mode_cntl
&= C_028814_FACE
;
1455 pa_su_sc_mode_cntl
|= S_028814_FACE(d
->front_face
);
1458 radeon_set_context_reg(cmd_buffer
->cs
, R_028814_PA_SU_SC_MODE_CNTL
,
1459 pa_su_sc_mode_cntl
);
1463 radv_emit_primitive_topology(struct radv_cmd_buffer
*cmd_buffer
)
1465 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1467 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1468 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
1470 R_030908_VGT_PRIMITIVE_TYPE
, 1,
1471 d
->primitive_topology
);
1473 radeon_set_config_reg(cmd_buffer
->cs
,
1474 R_008958_VGT_PRIMITIVE_TYPE
,
1475 d
->primitive_topology
);
1480 radv_emit_depth_control(struct radv_cmd_buffer
*cmd_buffer
, uint32_t states
)
1482 unsigned db_depth_control
= cmd_buffer
->state
.pipeline
->graphics
.db_depth_control
;
1483 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1485 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
) {
1486 db_depth_control
&= C_028800_Z_ENABLE
;
1487 db_depth_control
|= S_028800_Z_ENABLE(d
->depth_test_enable
? 1 : 0);
1490 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
) {
1491 db_depth_control
&= C_028800_Z_WRITE_ENABLE
;
1492 db_depth_control
|= S_028800_Z_WRITE_ENABLE(d
->depth_write_enable
? 1 : 0);
1495 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
) {
1496 db_depth_control
&= C_028800_ZFUNC
;
1497 db_depth_control
|= S_028800_ZFUNC(d
->depth_compare_op
);
1500 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
) {
1501 db_depth_control
&= C_028800_DEPTH_BOUNDS_ENABLE
;
1502 db_depth_control
|= S_028800_DEPTH_BOUNDS_ENABLE(d
->depth_bounds_test_enable
? 1 : 0);
1505 if (states
& RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
) {
1506 db_depth_control
&= C_028800_STENCIL_ENABLE
;
1507 db_depth_control
|= S_028800_STENCIL_ENABLE(d
->stencil_test_enable
? 1 : 0);
1509 db_depth_control
&= C_028800_BACKFACE_ENABLE
;
1510 db_depth_control
|= S_028800_BACKFACE_ENABLE(d
->stencil_test_enable
? 1 : 0);
1513 if (states
& RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP
) {
1514 db_depth_control
&= C_028800_STENCILFUNC
;
1515 db_depth_control
|= S_028800_STENCILFUNC(d
->stencil_op
.front
.compare_op
);
1517 db_depth_control
&= C_028800_STENCILFUNC_BF
;
1518 db_depth_control
|= S_028800_STENCILFUNC_BF(d
->stencil_op
.back
.compare_op
);
1521 radeon_set_context_reg(cmd_buffer
->cs
, R_028800_DB_DEPTH_CONTROL
,
1526 radv_emit_stencil_control(struct radv_cmd_buffer
*cmd_buffer
)
1528 struct radv_dynamic_state
*d
= &cmd_buffer
->state
.dynamic
;
1530 radeon_set_context_reg(cmd_buffer
->cs
, R_02842C_DB_STENCIL_CONTROL
,
1531 S_02842C_STENCILFAIL(si_translate_stencil_op(d
->stencil_op
.front
.fail_op
)) |
1532 S_02842C_STENCILZPASS(si_translate_stencil_op(d
->stencil_op
.front
.pass_op
)) |
1533 S_02842C_STENCILZFAIL(si_translate_stencil_op(d
->stencil_op
.front
.depth_fail_op
)) |
1534 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(d
->stencil_op
.back
.fail_op
)) |
1535 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(d
->stencil_op
.back
.pass_op
)) |
1536 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(d
->stencil_op
.back
.depth_fail_op
)));
1540 radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer
,
1542 struct radv_color_buffer_info
*cb
,
1543 struct radv_image_view
*iview
,
1544 VkImageLayout layout
,
1545 bool in_render_loop
)
1547 bool is_vi
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
;
1548 uint32_t cb_color_info
= cb
->cb_color_info
;
1549 struct radv_image
*image
= iview
->image
;
1551 if (!radv_layout_dcc_compressed(cmd_buffer
->device
, image
, layout
, in_render_loop
,
1552 radv_image_queue_family_mask(image
,
1553 cmd_buffer
->queue_family_index
,
1554 cmd_buffer
->queue_family_index
))) {
1555 cb_color_info
&= C_028C70_DCC_ENABLE
;
1558 if (!radv_layout_can_fast_clear(image
, layout
, in_render_loop
,
1559 radv_image_queue_family_mask(image
,
1560 cmd_buffer
->queue_family_index
,
1561 cmd_buffer
->queue_family_index
))) {
1562 cb_color_info
&= C_028C70_COMPRESSION
;
1565 if (radv_image_is_tc_compat_cmask(image
) &&
1566 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1567 radv_is_dcc_decompress_pipeline(cmd_buffer
))) {
1568 /* If this bit is set, the FMASK decompression operation
1569 * doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
1571 cb_color_info
&= C_028C70_FMASK_COMPRESS_1FRAG_ONLY
;
1574 if (radv_image_has_fmask(image
) &&
1575 (radv_is_fmask_decompress_pipeline(cmd_buffer
) ||
1576 radv_is_hw_resolve_pipeline(cmd_buffer
))) {
1577 /* Make sure FMASK is enabled if it has been cleared because:
1579 * 1) it's required for FMASK_DECOMPRESS operations to avoid
1581 * 2) it's necessary for CB_RESOLVE which can read compressed
1582 * FMASK data anyways.
1584 cb_color_info
|= S_028C70_COMPRESSION(1);
1587 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1588 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1589 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1590 radeon_emit(cmd_buffer
->cs
, 0);
1591 radeon_emit(cmd_buffer
->cs
, 0);
1592 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1593 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1594 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1595 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1596 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1597 radeon_emit(cmd_buffer
->cs
, 0);
1598 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1599 radeon_emit(cmd_buffer
->cs
, 0);
1601 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 1);
1602 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1604 radeon_set_context_reg(cmd_buffer
->cs
, R_028E40_CB_COLOR0_BASE_EXT
+ index
* 4,
1605 cb
->cb_color_base
>> 32);
1606 radeon_set_context_reg(cmd_buffer
->cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ index
* 4,
1607 cb
->cb_color_cmask
>> 32);
1608 radeon_set_context_reg(cmd_buffer
->cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ index
* 4,
1609 cb
->cb_color_fmask
>> 32);
1610 radeon_set_context_reg(cmd_buffer
->cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ index
* 4,
1611 cb
->cb_dcc_base
>> 32);
1612 radeon_set_context_reg(cmd_buffer
->cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ index
* 4,
1613 cb
->cb_color_attrib2
);
1614 radeon_set_context_reg(cmd_buffer
->cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ index
* 4,
1615 cb
->cb_color_attrib3
);
1616 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1617 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1618 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1619 radeon_emit(cmd_buffer
->cs
, S_028C64_BASE_256B(cb
->cb_color_base
>> 32));
1620 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib2
);
1621 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1622 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1623 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1624 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1625 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1626 radeon_emit(cmd_buffer
->cs
, S_028C80_BASE_256B(cb
->cb_color_cmask
>> 32));
1627 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1628 radeon_emit(cmd_buffer
->cs
, S_028C88_BASE_256B(cb
->cb_color_fmask
>> 32));
1630 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, 2);
1631 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_base
);
1632 radeon_emit(cmd_buffer
->cs
, S_028C98_BASE_256B(cb
->cb_dcc_base
>> 32));
1634 radeon_set_context_reg(cmd_buffer
->cs
, R_0287A0_CB_MRT0_EPITCH
+ index
* 4,
1637 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028C60_CB_COLOR0_BASE
+ index
* 0x3c, 11);
1638 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_base
);
1639 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_pitch
);
1640 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_slice
);
1641 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_view
);
1642 radeon_emit(cmd_buffer
->cs
, cb_color_info
);
1643 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_attrib
);
1644 radeon_emit(cmd_buffer
->cs
, cb
->cb_dcc_control
);
1645 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask
);
1646 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_cmask_slice
);
1647 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask
);
1648 radeon_emit(cmd_buffer
->cs
, cb
->cb_color_fmask_slice
);
1650 if (is_vi
) { /* DCC BASE */
1651 radeon_set_context_reg(cmd_buffer
->cs
, R_028C94_CB_COLOR0_DCC_BASE
+ index
* 0x3c, cb
->cb_dcc_base
);
1655 if (radv_dcc_enabled(image
, iview
->base_mip
)) {
1656 /* Drawing with DCC enabled also compresses colorbuffers. */
1657 VkImageSubresourceRange range
= {
1658 .aspectMask
= iview
->aspect_mask
,
1659 .baseMipLevel
= iview
->base_mip
,
1660 .levelCount
= iview
->level_count
,
1661 .baseArrayLayer
= iview
->base_layer
,
1662 .layerCount
= iview
->layer_count
,
1665 radv_update_dcc_metadata(cmd_buffer
, image
, &range
, true);
1670 radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer
,
1671 struct radv_ds_buffer_info
*ds
,
1672 const struct radv_image_view
*iview
,
1673 VkImageLayout layout
,
1674 bool in_render_loop
, bool requires_cond_exec
)
1676 const struct radv_image
*image
= iview
->image
;
1677 uint32_t db_z_info
= ds
->db_z_info
;
1678 uint32_t db_z_info_reg
;
1680 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
||
1681 !radv_image_is_tc_compat_htile(image
))
1684 if (!radv_layout_is_htile_compressed(image
, layout
, in_render_loop
,
1685 radv_image_queue_family_mask(image
,
1686 cmd_buffer
->queue_family_index
,
1687 cmd_buffer
->queue_family_index
))) {
1688 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1691 db_z_info
&= C_028040_ZRANGE_PRECISION
;
1693 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1694 db_z_info_reg
= R_028038_DB_Z_INFO
;
1696 db_z_info_reg
= R_028040_DB_Z_INFO
;
1699 /* When we don't know the last fast clear value we need to emit a
1700 * conditional packet that will eventually skip the following
1701 * SET_CONTEXT_REG packet.
1703 if (requires_cond_exec
) {
1704 uint64_t va
= radv_get_tc_compat_zrange_va(image
, iview
->base_mip
);
1706 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_COND_EXEC
, 3, 0));
1707 radeon_emit(cmd_buffer
->cs
, va
);
1708 radeon_emit(cmd_buffer
->cs
, va
>> 32);
1709 radeon_emit(cmd_buffer
->cs
, 0);
1710 radeon_emit(cmd_buffer
->cs
, 3); /* SET_CONTEXT_REG size */
1713 radeon_set_context_reg(cmd_buffer
->cs
, db_z_info_reg
, db_z_info
);
1717 radv_emit_fb_ds_state(struct radv_cmd_buffer
*cmd_buffer
,
1718 struct radv_ds_buffer_info
*ds
,
1719 struct radv_image_view
*iview
,
1720 VkImageLayout layout
,
1721 bool in_render_loop
)
1723 const struct radv_image
*image
= iview
->image
;
1724 uint32_t db_z_info
= ds
->db_z_info
;
1725 uint32_t db_stencil_info
= ds
->db_stencil_info
;
1727 if (!radv_layout_is_htile_compressed(image
, layout
, in_render_loop
,
1728 radv_image_queue_family_mask(image
,
1729 cmd_buffer
->queue_family_index
,
1730 cmd_buffer
->queue_family_index
))) {
1731 db_z_info
&= C_028040_TILE_SURFACE_ENABLE
;
1732 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1735 radeon_set_context_reg(cmd_buffer
->cs
, R_028008_DB_DEPTH_VIEW
, ds
->db_depth_view
);
1736 radeon_set_context_reg(cmd_buffer
->cs
, R_028ABC_DB_HTILE_SURFACE
, ds
->db_htile_surface
);
1738 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
1739 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1740 radeon_set_context_reg(cmd_buffer
->cs
, R_02801C_DB_DEPTH_SIZE_XY
, ds
->db_depth_size
);
1742 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 7);
1743 radeon_emit(cmd_buffer
->cs
, S_02803C_RESOURCE_LEVEL(1));
1744 radeon_emit(cmd_buffer
->cs
, db_z_info
);
1745 radeon_emit(cmd_buffer
->cs
, db_stencil_info
);
1746 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1747 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1748 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
);
1749 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
);
1751 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
1752 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1753 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1754 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
>> 32);
1755 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
>> 32);
1756 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
>> 32);
1757 } else if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
1758 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
1759 radeon_emit(cmd_buffer
->cs
, ds
->db_htile_data_base
);
1760 radeon_emit(cmd_buffer
->cs
, S_028018_BASE_HI(ds
->db_htile_data_base
>> 32));
1761 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
);
1763 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 10);
1764 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* DB_Z_INFO */
1765 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* DB_STENCIL_INFO */
1766 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* DB_Z_READ_BASE */
1767 radeon_emit(cmd_buffer
->cs
, S_028044_BASE_HI(ds
->db_z_read_base
>> 32)); /* DB_Z_READ_BASE_HI */
1768 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* DB_STENCIL_READ_BASE */
1769 radeon_emit(cmd_buffer
->cs
, S_02804C_BASE_HI(ds
->db_stencil_read_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
1770 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* DB_Z_WRITE_BASE */
1771 radeon_emit(cmd_buffer
->cs
, S_028054_BASE_HI(ds
->db_z_write_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
1772 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* DB_STENCIL_WRITE_BASE */
1773 radeon_emit(cmd_buffer
->cs
, S_02805C_BASE_HI(ds
->db_stencil_write_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1775 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028068_DB_Z_INFO2
, 2);
1776 radeon_emit(cmd_buffer
->cs
, ds
->db_z_info2
);
1777 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_info2
);
1779 radeon_set_context_reg(cmd_buffer
->cs
, R_028014_DB_HTILE_DATA_BASE
, ds
->db_htile_data_base
);
1781 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_02803C_DB_DEPTH_INFO
, 9);
1782 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
1783 radeon_emit(cmd_buffer
->cs
, db_z_info
); /* R_028040_DB_Z_INFO */
1784 radeon_emit(cmd_buffer
->cs
, db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
1785 radeon_emit(cmd_buffer
->cs
, ds
->db_z_read_base
); /* R_028048_DB_Z_READ_BASE */
1786 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_read_base
); /* R_02804C_DB_STENCIL_READ_BASE */
1787 radeon_emit(cmd_buffer
->cs
, ds
->db_z_write_base
); /* R_028050_DB_Z_WRITE_BASE */
1788 radeon_emit(cmd_buffer
->cs
, ds
->db_stencil_write_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
1789 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
1790 radeon_emit(cmd_buffer
->cs
, ds
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
1794 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1795 radv_update_zrange_precision(cmd_buffer
, ds
, iview
, layout
,
1796 in_render_loop
, true);
1798 radeon_set_context_reg(cmd_buffer
->cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1799 ds
->pa_su_poly_offset_db_fmt_cntl
);
1803 * Update the fast clear depth/stencil values if the image is bound as a
1804 * depth/stencil buffer.
1807 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer
*cmd_buffer
,
1808 const struct radv_image_view
*iview
,
1809 VkClearDepthStencilValue ds_clear_value
,
1810 VkImageAspectFlags aspects
)
1812 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1813 const struct radv_image
*image
= iview
->image
;
1814 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1817 if (!cmd_buffer
->state
.attachments
|| !subpass
)
1820 if (!subpass
->depth_stencil_attachment
)
1823 att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1824 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
1827 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1828 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1829 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
1830 radeon_emit(cs
, ds_clear_value
.stencil
);
1831 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1832 } else if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1833 radeon_set_context_reg_seq(cs
, R_02802C_DB_DEPTH_CLEAR
, 1);
1834 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1836 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1837 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 1);
1838 radeon_emit(cs
, ds_clear_value
.stencil
);
1841 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1842 * only needed when clearing Z to 0.0.
1844 if ((aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1845 ds_clear_value
.depth
== 0.0) {
1846 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
1847 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
1849 radv_update_zrange_precision(cmd_buffer
, &cmd_buffer
->state
.attachments
[att_idx
].ds
,
1850 iview
, layout
, in_render_loop
, false);
1853 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
1857 * Set the clear depth/stencil values to the image's metadata.
1860 radv_set_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1861 struct radv_image
*image
,
1862 const VkImageSubresourceRange
*range
,
1863 VkClearDepthStencilValue ds_clear_value
,
1864 VkImageAspectFlags aspects
)
1866 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1867 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
);
1868 uint32_t level_count
= radv_get_levelCount(image
, range
);
1870 if (aspects
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
1871 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1872 /* Use the fastest way when both aspects are used. */
1873 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + 2 * level_count
, cmd_buffer
->state
.predicating
));
1874 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1875 S_370_WR_CONFIRM(1) |
1876 S_370_ENGINE_SEL(V_370_PFP
));
1877 radeon_emit(cs
, va
);
1878 radeon_emit(cs
, va
>> 32);
1880 for (uint32_t l
= 0; l
< level_count
; l
++) {
1881 radeon_emit(cs
, ds_clear_value
.stencil
);
1882 radeon_emit(cs
, fui(ds_clear_value
.depth
));
1885 /* Otherwise we need one WRITE_DATA packet per level. */
1886 for (uint32_t l
= 0; l
< level_count
; l
++) {
1887 uint64_t va
= radv_get_ds_clear_value_va(image
, range
->baseMipLevel
+ l
);
1890 if (aspects
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1891 value
= fui(ds_clear_value
.depth
);
1894 assert(aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1895 value
= ds_clear_value
.stencil
;
1898 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, cmd_buffer
->state
.predicating
));
1899 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1900 S_370_WR_CONFIRM(1) |
1901 S_370_ENGINE_SEL(V_370_PFP
));
1902 radeon_emit(cs
, va
);
1903 radeon_emit(cs
, va
>> 32);
1904 radeon_emit(cs
, value
);
1910 * Update the TC-compat metadata value for this image.
1913 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1914 struct radv_image
*image
,
1915 const VkImageSubresourceRange
*range
,
1918 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1920 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_tc_compat_zrange_bug
)
1923 uint64_t va
= radv_get_tc_compat_zrange_va(image
, range
->baseMipLevel
);
1924 uint32_t level_count
= radv_get_levelCount(image
, range
);
1926 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + level_count
, cmd_buffer
->state
.predicating
));
1927 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
1928 S_370_WR_CONFIRM(1) |
1929 S_370_ENGINE_SEL(V_370_PFP
));
1930 radeon_emit(cs
, va
);
1931 radeon_emit(cs
, va
>> 32);
1933 for (uint32_t l
= 0; l
< level_count
; l
++)
1934 radeon_emit(cs
, value
);
1938 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1939 const struct radv_image_view
*iview
,
1940 VkClearDepthStencilValue ds_clear_value
)
1942 VkImageSubresourceRange range
= {
1943 .aspectMask
= iview
->aspect_mask
,
1944 .baseMipLevel
= iview
->base_mip
,
1945 .levelCount
= iview
->level_count
,
1946 .baseArrayLayer
= iview
->base_layer
,
1947 .layerCount
= iview
->layer_count
,
1951 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1952 * depth clear value is 0.0f.
1954 cond_val
= ds_clear_value
.depth
== 0.0f
? UINT_MAX
: 0;
1956 radv_set_tc_compat_zrange_metadata(cmd_buffer
, iview
->image
, &range
,
1961 * Update the clear depth/stencil values for this image.
1964 radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1965 const struct radv_image_view
*iview
,
1966 VkClearDepthStencilValue ds_clear_value
,
1967 VkImageAspectFlags aspects
)
1969 VkImageSubresourceRange range
= {
1970 .aspectMask
= iview
->aspect_mask
,
1971 .baseMipLevel
= iview
->base_mip
,
1972 .levelCount
= iview
->level_count
,
1973 .baseArrayLayer
= iview
->base_layer
,
1974 .layerCount
= iview
->layer_count
,
1976 struct radv_image
*image
= iview
->image
;
1978 assert(radv_image_has_htile(image
));
1980 radv_set_ds_clear_metadata(cmd_buffer
, iview
->image
, &range
,
1981 ds_clear_value
, aspects
);
1983 if (radv_image_is_tc_compat_htile(image
) &&
1984 (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
1985 radv_update_tc_compat_zrange_metadata(cmd_buffer
, iview
,
1989 radv_update_bound_fast_clear_ds(cmd_buffer
, iview
, ds_clear_value
,
1994 * Load the clear depth/stencil values from the image's metadata.
1997 radv_load_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1998 const struct radv_image_view
*iview
)
2000 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2001 const struct radv_image
*image
= iview
->image
;
2002 VkImageAspectFlags aspects
= vk_format_aspects(image
->vk_format
);
2003 uint64_t va
= radv_get_ds_clear_value_va(image
, iview
->base_mip
);
2004 unsigned reg_offset
= 0, reg_count
= 0;
2006 if (!radv_image_has_htile(image
))
2009 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2015 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)
2018 uint32_t reg
= R_028028_DB_STENCIL_CLEAR
+ 4 * reg_offset
;
2020 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
2021 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX
, 3, 0));
2022 radeon_emit(cs
, va
);
2023 radeon_emit(cs
, va
>> 32);
2024 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
2025 radeon_emit(cs
, reg_count
);
2027 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2028 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2029 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2030 (reg_count
== 2 ? COPY_DATA_COUNT_SEL
: 0));
2031 radeon_emit(cs
, va
);
2032 radeon_emit(cs
, va
>> 32);
2033 radeon_emit(cs
, reg
>> 2);
2036 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
2042 * With DCC some colors don't require CMASK elimination before being
2043 * used as a texture. This sets a predicate value to determine if the
2044 * cmask eliminate is required.
2047 radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
2048 struct radv_image
*image
,
2049 const VkImageSubresourceRange
*range
, bool value
)
2051 uint64_t pred_val
= value
;
2052 uint64_t va
= radv_image_get_fce_pred_va(image
, range
->baseMipLevel
);
2053 uint32_t level_count
= radv_get_levelCount(image
, range
);
2054 uint32_t count
= 2 * level_count
;
2056 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
2058 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
2059 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
2060 S_370_WR_CONFIRM(1) |
2061 S_370_ENGINE_SEL(V_370_PFP
));
2062 radeon_emit(cmd_buffer
->cs
, va
);
2063 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2065 for (uint32_t l
= 0; l
< level_count
; l
++) {
2066 radeon_emit(cmd_buffer
->cs
, pred_val
);
2067 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
2072 * Update the DCC predicate to reflect the compression state.
2075 radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
2076 struct radv_image
*image
,
2077 const VkImageSubresourceRange
*range
, bool value
)
2079 uint64_t pred_val
= value
;
2080 uint64_t va
= radv_image_get_dcc_pred_va(image
, range
->baseMipLevel
);
2081 uint32_t level_count
= radv_get_levelCount(image
, range
);
2082 uint32_t count
= 2 * level_count
;
2084 assert(radv_dcc_enabled(image
, range
->baseMipLevel
));
2086 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, 0));
2087 radeon_emit(cmd_buffer
->cs
, S_370_DST_SEL(V_370_MEM
) |
2088 S_370_WR_CONFIRM(1) |
2089 S_370_ENGINE_SEL(V_370_PFP
));
2090 radeon_emit(cmd_buffer
->cs
, va
);
2091 radeon_emit(cmd_buffer
->cs
, va
>> 32);
2093 for (uint32_t l
= 0; l
< level_count
; l
++) {
2094 radeon_emit(cmd_buffer
->cs
, pred_val
);
2095 radeon_emit(cmd_buffer
->cs
, pred_val
>> 32);
2100 * Update the fast clear color values if the image is bound as a color buffer.
2103 radv_update_bound_fast_clear_color(struct radv_cmd_buffer
*cmd_buffer
,
2104 struct radv_image
*image
,
2106 uint32_t color_values
[2])
2108 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2109 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2112 if (!cmd_buffer
->state
.attachments
|| !subpass
)
2115 att_idx
= subpass
->color_attachments
[cb_idx
].attachment
;
2116 if (att_idx
== VK_ATTACHMENT_UNUSED
)
2119 if (cmd_buffer
->state
.attachments
[att_idx
].iview
->image
!= image
)
2122 radeon_set_context_reg_seq(cs
, R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c, 2);
2123 radeon_emit(cs
, color_values
[0]);
2124 radeon_emit(cs
, color_values
[1]);
2126 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2130 * Set the clear color values to the image's metadata.
2133 radv_set_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
2134 struct radv_image
*image
,
2135 const VkImageSubresourceRange
*range
,
2136 uint32_t color_values
[2])
2138 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2139 uint64_t va
= radv_image_get_fast_clear_va(image
, range
->baseMipLevel
);
2140 uint32_t level_count
= radv_get_levelCount(image
, range
);
2141 uint32_t count
= 2 * level_count
;
2143 assert(radv_image_has_cmask(image
) ||
2144 radv_dcc_enabled(image
, range
->baseMipLevel
));
2146 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + count
, cmd_buffer
->state
.predicating
));
2147 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
2148 S_370_WR_CONFIRM(1) |
2149 S_370_ENGINE_SEL(V_370_PFP
));
2150 radeon_emit(cs
, va
);
2151 radeon_emit(cs
, va
>> 32);
2153 for (uint32_t l
= 0; l
< level_count
; l
++) {
2154 radeon_emit(cs
, color_values
[0]);
2155 radeon_emit(cs
, color_values
[1]);
2160 * Update the clear color values for this image.
2163 radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
2164 const struct radv_image_view
*iview
,
2166 uint32_t color_values
[2])
2168 struct radv_image
*image
= iview
->image
;
2169 VkImageSubresourceRange range
= {
2170 .aspectMask
= iview
->aspect_mask
,
2171 .baseMipLevel
= iview
->base_mip
,
2172 .levelCount
= iview
->level_count
,
2173 .baseArrayLayer
= iview
->base_layer
,
2174 .layerCount
= iview
->layer_count
,
2177 assert(radv_image_has_cmask(image
) ||
2178 radv_dcc_enabled(image
, iview
->base_mip
));
2180 radv_set_color_clear_metadata(cmd_buffer
, image
, &range
, color_values
);
2182 radv_update_bound_fast_clear_color(cmd_buffer
, image
, cb_idx
,
2187 * Load the clear color values from the image's metadata.
2190 radv_load_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
2191 struct radv_image_view
*iview
,
2194 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2195 struct radv_image
*image
= iview
->image
;
2196 uint64_t va
= radv_image_get_fast_clear_va(image
, iview
->base_mip
);
2198 if (!radv_image_has_cmask(image
) &&
2199 !radv_dcc_enabled(image
, iview
->base_mip
))
2202 uint32_t reg
= R_028C8C_CB_COLOR0_CLEAR_WORD0
+ cb_idx
* 0x3c;
2204 if (cmd_buffer
->device
->physical_device
->rad_info
.has_load_ctx_reg_pkt
) {
2205 radeon_emit(cs
, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX
, 3, cmd_buffer
->state
.predicating
));
2206 radeon_emit(cs
, va
);
2207 radeon_emit(cs
, va
>> 32);
2208 radeon_emit(cs
, (reg
- SI_CONTEXT_REG_OFFSET
) >> 2);
2211 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, cmd_buffer
->state
.predicating
));
2212 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
2213 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
2214 COPY_DATA_COUNT_SEL
);
2215 radeon_emit(cs
, va
);
2216 radeon_emit(cs
, va
>> 32);
2217 radeon_emit(cs
, reg
>> 2);
2220 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, cmd_buffer
->state
.predicating
));
2226 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
)
2229 struct radv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
2230 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2232 /* this may happen for inherited secondary recording */
2236 for (i
= 0; i
< 8; ++i
) {
2237 if (i
>= subpass
->color_count
|| subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
2238 radeon_set_context_reg(cmd_buffer
->cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2239 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2243 int idx
= subpass
->color_attachments
[i
].attachment
;
2244 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2245 VkImageLayout layout
= subpass
->color_attachments
[i
].layout
;
2246 bool in_render_loop
= subpass
->color_attachments
[i
].in_render_loop
;
2248 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, iview
->bo
);
2250 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
| VK_IMAGE_ASPECT_PLANE_0_BIT
|
2251 VK_IMAGE_ASPECT_PLANE_1_BIT
| VK_IMAGE_ASPECT_PLANE_2_BIT
));
2252 radv_emit_fb_color_state(cmd_buffer
, i
, &cmd_buffer
->state
.attachments
[idx
].cb
, iview
, layout
, in_render_loop
);
2254 radv_load_color_clear_metadata(cmd_buffer
, iview
, i
);
2257 if (subpass
->depth_stencil_attachment
) {
2258 int idx
= subpass
->depth_stencil_attachment
->attachment
;
2259 VkImageLayout layout
= subpass
->depth_stencil_attachment
->layout
;
2260 bool in_render_loop
= subpass
->depth_stencil_attachment
->in_render_loop
;
2261 struct radv_image_view
*iview
= cmd_buffer
->state
.attachments
[idx
].iview
;
2262 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, cmd_buffer
->state
.attachments
[idx
].iview
->bo
);
2264 radv_emit_fb_ds_state(cmd_buffer
, &cmd_buffer
->state
.attachments
[idx
].ds
, iview
, layout
, in_render_loop
);
2266 if (cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
!= cmd_buffer
->state
.offset_scale
) {
2267 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
2268 cmd_buffer
->state
.offset_scale
= cmd_buffer
->state
.attachments
[idx
].ds
.offset_scale
;
2270 radv_load_ds_clear_metadata(cmd_buffer
, iview
);
2272 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
)
2273 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028038_DB_Z_INFO
, 2);
2275 radeon_set_context_reg_seq(cmd_buffer
->cs
, R_028040_DB_Z_INFO
, 2);
2277 radeon_emit(cmd_buffer
->cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2278 radeon_emit(cmd_buffer
->cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2280 radeon_set_context_reg(cmd_buffer
->cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2281 S_028208_BR_X(framebuffer
->width
) |
2282 S_028208_BR_Y(framebuffer
->height
));
2284 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX8
) {
2285 bool disable_constant_encode
=
2286 cmd_buffer
->device
->physical_device
->rad_info
.has_dcc_constant_encode
;
2287 enum chip_class chip_class
=
2288 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
;
2289 uint8_t watermark
= chip_class
>= GFX10
? 6 : 4;
2291 radeon_set_context_reg(cmd_buffer
->cs
, R_028424_CB_DCC_CONTROL
,
2292 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(chip_class
<= GFX9
) |
2293 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
2294 S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode
));
2297 if (cmd_buffer
->device
->dfsm_allowed
) {
2298 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2299 radeon_emit(cmd_buffer
->cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
2302 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_FRAMEBUFFER
;
2306 radv_emit_index_buffer(struct radv_cmd_buffer
*cmd_buffer
, bool indirect
)
2308 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2309 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2311 if (state
->index_type
!= state
->last_index_type
) {
2312 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2313 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2314 cs
, R_03090C_VGT_INDEX_TYPE
,
2315 2, state
->index_type
);
2317 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
2318 radeon_emit(cs
, state
->index_type
);
2321 state
->last_index_type
= state
->index_type
;
2324 /* For the direct indexed draws we use DRAW_INDEX_2, which includes
2325 * the index_va and max_index_count already. */
2329 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
2330 radeon_emit(cs
, state
->index_va
);
2331 radeon_emit(cs
, state
->index_va
>> 32);
2333 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
2334 radeon_emit(cs
, state
->max_index_count
);
2336 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_INDEX_BUFFER
;
2339 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
)
2341 bool has_perfect_queries
= cmd_buffer
->state
.perfect_occlusion_queries_enabled
;
2342 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2343 uint32_t pa_sc_mode_cntl_1
=
2344 pipeline
? pipeline
->graphics
.ms
.pa_sc_mode_cntl_1
: 0;
2345 uint32_t db_count_control
;
2347 if(!cmd_buffer
->state
.active_occlusion_queries
) {
2348 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2349 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2350 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2351 has_perfect_queries
) {
2352 /* Re-enable out-of-order rasterization if the
2353 * bound pipeline supports it and if it's has
2354 * been disabled before starting any perfect
2355 * occlusion queries.
2357 radeon_set_context_reg(cmd_buffer
->cs
,
2358 R_028A4C_PA_SC_MODE_CNTL_1
,
2362 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
2364 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2365 uint32_t sample_rate
= subpass
? util_logbase2(subpass
->max_sample_count
) : 0;
2366 bool gfx10_perfect
= cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& has_perfect_queries
;
2368 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2369 /* Always enable PERFECT_ZPASS_COUNTS due to issues with partially
2370 * covered tiles, discards, and early depth testing. For more details,
2371 * see https://gitlab.freedesktop.org/mesa/mesa/-/issues/3218 */
2373 S_028004_PERFECT_ZPASS_COUNTS(1) |
2374 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
2375 S_028004_SAMPLE_RATE(sample_rate
) |
2376 S_028004_ZPASS_ENABLE(1) |
2377 S_028004_SLICE_EVEN_ENABLE(1) |
2378 S_028004_SLICE_ODD_ENABLE(1);
2380 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1
) &&
2381 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
&&
2382 has_perfect_queries
) {
2383 /* If the bound pipeline has enabled
2384 * out-of-order rasterization, we should
2385 * disable it before starting any perfect
2386 * occlusion queries.
2388 pa_sc_mode_cntl_1
&= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE
;
2390 radeon_set_context_reg(cmd_buffer
->cs
,
2391 R_028A4C_PA_SC_MODE_CNTL_1
,
2395 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(1) |
2396 S_028004_SAMPLE_RATE(sample_rate
);
2400 radeon_set_context_reg(cmd_buffer
->cs
, R_028004_DB_COUNT_CONTROL
, db_count_control
);
2402 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
2406 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer
*cmd_buffer
)
2408 uint32_t states
= cmd_buffer
->state
.dirty
& cmd_buffer
->state
.emitted_pipeline
->graphics
.needed_dynamic_state
;
2410 if (states
& (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
))
2411 radv_emit_viewport(cmd_buffer
);
2413 if (states
& (RADV_CMD_DIRTY_DYNAMIC_SCISSOR
| RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
) &&
2414 !cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
2415 radv_emit_scissor(cmd_buffer
);
2417 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
)
2418 radv_emit_line_width(cmd_buffer
);
2420 if (states
& RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
)
2421 radv_emit_blend_constants(cmd_buffer
);
2423 if (states
& (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
|
2424 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
|
2425 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
))
2426 radv_emit_stencil(cmd_buffer
);
2428 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
)
2429 radv_emit_depth_bounds(cmd_buffer
);
2431 if (states
& RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
)
2432 radv_emit_depth_bias(cmd_buffer
);
2434 if (states
& RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
)
2435 radv_emit_discard_rectangle(cmd_buffer
);
2437 if (states
& RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
)
2438 radv_emit_sample_locations(cmd_buffer
);
2440 if (states
& RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
)
2441 radv_emit_line_stipple(cmd_buffer
);
2443 if (states
& (RADV_CMD_DIRTY_DYNAMIC_CULL_MODE
|
2444 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE
))
2445 radv_emit_culling(cmd_buffer
, states
);
2447 if (states
& RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
)
2448 radv_emit_primitive_topology(cmd_buffer
);
2450 if (states
& (RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
|
2451 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
|
2452 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
|
2453 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
|
2454 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
|
2455 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP
))
2456 radv_emit_depth_control(cmd_buffer
, states
);
2458 if (states
& RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP
)
2459 radv_emit_stencil_control(cmd_buffer
);
2461 cmd_buffer
->state
.dirty
&= ~states
;
2465 radv_flush_push_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2466 VkPipelineBindPoint bind_point
)
2468 struct radv_descriptor_state
*descriptors_state
=
2469 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2470 struct radv_descriptor_set
*set
= &descriptors_state
->push_set
.set
;
2473 if (!radv_cmd_buffer_upload_data(cmd_buffer
, set
->size
, 32,
2478 set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2479 set
->va
+= bo_offset
;
2483 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer
*cmd_buffer
,
2484 VkPipelineBindPoint bind_point
)
2486 struct radv_descriptor_state
*descriptors_state
=
2487 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2488 uint32_t size
= MAX_SETS
* 4;
2492 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, size
,
2493 256, &offset
, &ptr
))
2496 for (unsigned i
= 0; i
< MAX_SETS
; i
++) {
2497 uint32_t *uptr
= ((uint32_t *)ptr
) + i
;
2498 uint64_t set_va
= 0;
2499 struct radv_descriptor_set
*set
= descriptors_state
->sets
[i
];
2500 if (descriptors_state
->valid
& (1u << i
))
2502 uptr
[0] = set_va
& 0xffffffff;
2505 uint64_t va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2508 if (cmd_buffer
->state
.pipeline
) {
2509 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_VERTEX
])
2510 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2511 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2513 if (cmd_buffer
->state
.pipeline
->shaders
[MESA_SHADER_FRAGMENT
])
2514 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_FRAGMENT
,
2515 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2517 if (radv_pipeline_has_gs(cmd_buffer
->state
.pipeline
))
2518 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_GEOMETRY
,
2519 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2521 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2522 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_CTRL
,
2523 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2525 if (radv_pipeline_has_tess(cmd_buffer
->state
.pipeline
))
2526 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_TESS_EVAL
,
2527 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2530 if (cmd_buffer
->state
.compute_pipeline
)
2531 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.compute_pipeline
, MESA_SHADER_COMPUTE
,
2532 AC_UD_INDIRECT_DESCRIPTOR_SETS
, va
);
2536 radv_flush_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2537 VkShaderStageFlags stages
)
2539 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2540 VK_PIPELINE_BIND_POINT_COMPUTE
:
2541 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2542 struct radv_descriptor_state
*descriptors_state
=
2543 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2544 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2545 bool flush_indirect_descriptors
;
2547 if (!descriptors_state
->dirty
)
2550 if (descriptors_state
->push_dirty
)
2551 radv_flush_push_descriptors(cmd_buffer
, bind_point
);
2553 flush_indirect_descriptors
=
2554 (bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
&&
2555 state
->pipeline
&& state
->pipeline
->need_indirect_descriptor_sets
) ||
2556 (bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
&&
2557 state
->compute_pipeline
&& state
->compute_pipeline
->need_indirect_descriptor_sets
);
2559 if (flush_indirect_descriptors
)
2560 radv_flush_indirect_descriptor_sets(cmd_buffer
, bind_point
);
2562 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
2564 MAX_SETS
* MESA_SHADER_STAGES
* 4);
2566 if (cmd_buffer
->state
.pipeline
) {
2567 radv_foreach_stage(stage
, stages
) {
2568 if (!cmd_buffer
->state
.pipeline
->shaders
[stage
])
2571 radv_emit_descriptor_pointers(cmd_buffer
,
2572 cmd_buffer
->state
.pipeline
,
2573 descriptors_state
, stage
);
2577 if (cmd_buffer
->state
.compute_pipeline
&&
2578 (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)) {
2579 radv_emit_descriptor_pointers(cmd_buffer
,
2580 cmd_buffer
->state
.compute_pipeline
,
2582 MESA_SHADER_COMPUTE
);
2585 descriptors_state
->dirty
= 0;
2586 descriptors_state
->push_dirty
= false;
2588 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2590 if (unlikely(cmd_buffer
->device
->trace_bo
))
2591 radv_save_descriptors(cmd_buffer
, bind_point
);
2595 radv_flush_constants(struct radv_cmd_buffer
*cmd_buffer
,
2596 VkShaderStageFlags stages
)
2598 struct radv_pipeline
*pipeline
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
2599 ? cmd_buffer
->state
.compute_pipeline
2600 : cmd_buffer
->state
.pipeline
;
2601 VkPipelineBindPoint bind_point
= stages
& VK_SHADER_STAGE_COMPUTE_BIT
?
2602 VK_PIPELINE_BIND_POINT_COMPUTE
:
2603 VK_PIPELINE_BIND_POINT_GRAPHICS
;
2604 struct radv_descriptor_state
*descriptors_state
=
2605 radv_get_descriptors_state(cmd_buffer
, bind_point
);
2606 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
2607 struct radv_shader_variant
*shader
, *prev_shader
;
2608 bool need_push_constants
= false;
2613 stages
&= cmd_buffer
->push_constant_stages
;
2615 (!layout
->push_constant_size
&& !layout
->dynamic_offset_count
))
2618 radv_foreach_stage(stage
, stages
) {
2619 shader
= radv_get_shader(pipeline
, stage
);
2623 need_push_constants
|= shader
->info
.loads_push_constants
;
2624 need_push_constants
|= shader
->info
.loads_dynamic_offsets
;
2626 uint8_t base
= shader
->info
.base_inline_push_consts
;
2627 uint8_t count
= shader
->info
.num_inline_push_consts
;
2629 radv_emit_inline_push_consts(cmd_buffer
, pipeline
, stage
,
2630 AC_UD_INLINE_PUSH_CONSTANTS
,
2632 (uint32_t *)&cmd_buffer
->push_constants
[base
* 4]);
2635 if (need_push_constants
) {
2636 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, layout
->push_constant_size
+
2637 16 * layout
->dynamic_offset_count
,
2638 256, &offset
, &ptr
))
2641 memcpy(ptr
, cmd_buffer
->push_constants
, layout
->push_constant_size
);
2642 memcpy((char*)ptr
+ layout
->push_constant_size
,
2643 descriptors_state
->dynamic_buffers
,
2644 16 * layout
->dynamic_offset_count
);
2646 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2649 ASSERTED
unsigned cdw_max
=
2650 radeon_check_space(cmd_buffer
->device
->ws
,
2651 cmd_buffer
->cs
, MESA_SHADER_STAGES
* 4);
2654 radv_foreach_stage(stage
, stages
) {
2655 shader
= radv_get_shader(pipeline
, stage
);
2657 /* Avoid redundantly emitting the address for merged stages. */
2658 if (shader
&& shader
!= prev_shader
) {
2659 radv_emit_userdata_address(cmd_buffer
, pipeline
, stage
,
2660 AC_UD_PUSH_CONSTANTS
, va
);
2662 prev_shader
= shader
;
2665 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
2668 cmd_buffer
->push_constant_stages
&= ~stages
;
2672 radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer
,
2673 bool pipeline_is_dirty
)
2675 if ((pipeline_is_dirty
||
2676 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_VERTEX_BUFFER
)) &&
2677 cmd_buffer
->state
.pipeline
->num_vertex_bindings
&&
2678 radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.has_vertex_buffers
) {
2682 uint32_t count
= cmd_buffer
->state
.pipeline
->num_vertex_bindings
;
2685 /* allocate some descriptor state for vertex buffers */
2686 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, count
* 16, 256,
2687 &vb_offset
, &vb_ptr
))
2690 for (i
= 0; i
< count
; i
++) {
2691 uint32_t *desc
= &((uint32_t *)vb_ptr
)[i
* 4];
2693 struct radv_buffer
*buffer
= cmd_buffer
->vertex_bindings
[i
].buffer
;
2694 unsigned num_records
;
2700 va
= radv_buffer_get_va(buffer
->bo
);
2702 offset
= cmd_buffer
->vertex_bindings
[i
].offset
;
2703 va
+= offset
+ buffer
->offset
;
2705 if (cmd_buffer
->vertex_bindings
[i
].size
) {
2706 num_records
= cmd_buffer
->vertex_bindings
[i
].size
;
2708 num_records
= buffer
->size
- offset
;
2711 if (cmd_buffer
->state
.pipeline
->graphics
.uses_dynamic_stride
) {
2712 stride
= cmd_buffer
->vertex_bindings
[i
].stride
;
2714 stride
= cmd_buffer
->state
.pipeline
->binding_stride
[i
];
2717 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
)
2718 num_records
/= stride
;
2720 uint32_t rsrc_word3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2721 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2722 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2723 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2725 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2726 /* OOB_SELECT chooses the out-of-bounds check:
2727 * - 1: index >= NUM_RECORDS (Structured)
2728 * - 3: offset >= NUM_RECORDS (Raw)
2730 int oob_select
= stride
? V_008F0C_OOB_SELECT_STRUCTURED
: V_008F0C_OOB_SELECT_RAW
;
2732 rsrc_word3
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT
) |
2733 S_008F0C_OOB_SELECT(oob_select
) |
2734 S_008F0C_RESOURCE_LEVEL(1);
2736 rsrc_word3
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
2737 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2741 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) | S_008F04_STRIDE(stride
);
2742 desc
[2] = num_records
;
2743 desc
[3] = rsrc_word3
;
2746 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2749 radv_emit_userdata_address(cmd_buffer
, cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
,
2750 AC_UD_VS_VERTEX_BUFFERS
, va
);
2752 cmd_buffer
->state
.vb_va
= va
;
2753 cmd_buffer
->state
.vb_size
= count
* 16;
2754 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_VBO_DESCRIPTORS
;
2756 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_VERTEX_BUFFER
;
2760 radv_emit_streamout_buffers(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
)
2762 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2763 struct radv_userdata_info
*loc
;
2766 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
2767 if (!radv_get_shader(pipeline
, stage
))
2770 loc
= radv_lookup_user_sgpr(pipeline
, stage
,
2771 AC_UD_STREAMOUT_BUFFERS
);
2772 if (loc
->sgpr_idx
== -1)
2775 base_reg
= pipeline
->user_data_0
[stage
];
2777 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2778 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2781 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
2782 loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_STREAMOUT_BUFFERS
];
2783 if (loc
->sgpr_idx
!= -1) {
2784 base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2786 radv_emit_shader_pointer(cmd_buffer
->device
, cmd_buffer
->cs
,
2787 base_reg
+ loc
->sgpr_idx
* 4, va
, false);
2793 radv_flush_streamout_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
2795 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_STREAMOUT_BUFFER
) {
2796 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
2797 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
2802 /* Allocate some descriptor state for streamout buffers. */
2803 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
,
2804 MAX_SO_BUFFERS
* 16, 256,
2805 &so_offset
, &so_ptr
))
2808 for (uint32_t i
= 0; i
< MAX_SO_BUFFERS
; i
++) {
2809 struct radv_buffer
*buffer
= sb
[i
].buffer
;
2810 uint32_t *desc
= &((uint32_t *)so_ptr
)[i
* 4];
2812 if (!(so
->enabled_mask
& (1 << i
)))
2815 va
= radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
2819 /* Set the descriptor.
2821 * On GFX8, the format must be non-INVALID, otherwise
2822 * the buffer will be considered not bound and store
2823 * instructions will be no-ops.
2825 uint32_t size
= 0xffffffff;
2827 /* Compute the correct buffer size for NGG streamout
2828 * because it's used to determine the max emit per
2831 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
)
2832 size
= buffer
->size
- sb
[i
].offset
;
2834 uint32_t rsrc_word3
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2835 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2836 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2837 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2839 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2840 rsrc_word3
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2841 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
2842 S_008F0C_RESOURCE_LEVEL(1);
2844 rsrc_word3
|= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2848 desc
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
2850 desc
[3] = rsrc_word3
;
2853 va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
2856 radv_emit_streamout_buffers(cmd_buffer
, va
);
2859 cmd_buffer
->state
.dirty
&= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
2863 radv_flush_ngg_gs_state(struct radv_cmd_buffer
*cmd_buffer
)
2865 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
2866 struct radv_userdata_info
*loc
;
2867 uint32_t ngg_gs_state
= 0;
2870 if (!radv_pipeline_has_gs(pipeline
) ||
2871 !radv_pipeline_has_ngg(pipeline
))
2874 /* By default NGG GS queries are disabled but they are enabled if the
2875 * command buffer has active GDS queries or if it's a secondary command
2876 * buffer that inherits the number of generated primitives.
2878 if (cmd_buffer
->state
.active_pipeline_gds_queries
||
2879 (cmd_buffer
->state
.inherited_pipeline_statistics
& VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT
))
2882 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_GEOMETRY
,
2883 AC_UD_NGG_GS_STATE
);
2884 base_reg
= pipeline
->user_data_0
[MESA_SHADER_GEOMETRY
];
2885 assert(loc
->sgpr_idx
!= -1);
2887 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4,
2892 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
, bool pipeline_is_dirty
)
2894 radv_flush_vertex_descriptors(cmd_buffer
, pipeline_is_dirty
);
2895 radv_flush_streamout_descriptors(cmd_buffer
);
2896 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2897 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_ALL_GRAPHICS
);
2898 radv_flush_ngg_gs_state(cmd_buffer
);
2901 struct radv_draw_info
{
2903 * Number of vertices.
2908 * Index of the first vertex.
2910 int32_t vertex_offset
;
2913 * First instance id.
2915 uint32_t first_instance
;
2918 * Number of instances.
2920 uint32_t instance_count
;
2923 * First index (indexed draws only).
2925 uint32_t first_index
;
2928 * Whether it's an indexed draw.
2933 * Indirect draw parameters resource.
2935 struct radv_buffer
*indirect
;
2936 uint64_t indirect_offset
;
2940 * Draw count parameters resource.
2942 struct radv_buffer
*count_buffer
;
2943 uint64_t count_buffer_offset
;
2946 * Stream output parameters resource.
2948 struct radv_buffer
*strmout_buffer
;
2949 uint64_t strmout_buffer_offset
;
2953 radv_get_primitive_reset_index(struct radv_cmd_buffer
*cmd_buffer
)
2955 switch (cmd_buffer
->state
.index_type
) {
2956 case V_028A7C_VGT_INDEX_8
:
2958 case V_028A7C_VGT_INDEX_16
:
2960 case V_028A7C_VGT_INDEX_32
:
2963 unreachable("invalid index type");
2968 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
2969 bool instanced_draw
, bool indirect_draw
,
2970 bool count_from_stream_output
,
2971 uint32_t draw_vertex_count
)
2973 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
2974 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
2975 unsigned topology
= state
->dynamic
.primitive_topology
;
2976 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2977 unsigned ia_multi_vgt_param
;
2979 ia_multi_vgt_param
=
2980 si_get_ia_multi_vgt_param(cmd_buffer
, instanced_draw
,
2982 count_from_stream_output
,
2986 if (state
->last_ia_multi_vgt_param
!= ia_multi_vgt_param
) {
2987 if (info
->chip_class
== GFX9
) {
2988 radeon_set_uconfig_reg_idx(cmd_buffer
->device
->physical_device
,
2990 R_030960_IA_MULTI_VGT_PARAM
,
2991 4, ia_multi_vgt_param
);
2992 } else if (info
->chip_class
>= GFX7
) {
2993 radeon_set_context_reg_idx(cs
,
2994 R_028AA8_IA_MULTI_VGT_PARAM
,
2995 1, ia_multi_vgt_param
);
2997 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
,
2998 ia_multi_vgt_param
);
3000 state
->last_ia_multi_vgt_param
= ia_multi_vgt_param
;
3005 radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer
,
3006 const struct radv_draw_info
*draw_info
)
3008 struct radeon_info
*info
= &cmd_buffer
->device
->physical_device
->rad_info
;
3009 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3010 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
3011 int32_t primitive_reset_en
;
3014 if (info
->chip_class
< GFX10
) {
3015 si_emit_ia_multi_vgt_param(cmd_buffer
, draw_info
->instance_count
> 1,
3016 draw_info
->indirect
,
3017 !!draw_info
->strmout_buffer
,
3018 draw_info
->indirect
? 0 : draw_info
->count
);
3021 /* Primitive restart. */
3022 primitive_reset_en
=
3023 draw_info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
;
3025 if (primitive_reset_en
!= state
->last_primitive_reset_en
) {
3026 state
->last_primitive_reset_en
= primitive_reset_en
;
3027 if (info
->chip_class
>= GFX9
) {
3028 radeon_set_uconfig_reg(cs
,
3029 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
3030 primitive_reset_en
);
3032 radeon_set_context_reg(cs
,
3033 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
3034 primitive_reset_en
);
3038 if (primitive_reset_en
) {
3039 uint32_t primitive_reset_index
=
3040 radv_get_primitive_reset_index(cmd_buffer
);
3042 if (primitive_reset_index
!= state
->last_primitive_reset_index
) {
3043 radeon_set_context_reg(cs
,
3044 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
3045 primitive_reset_index
);
3046 state
->last_primitive_reset_index
= primitive_reset_index
;
3050 if (draw_info
->strmout_buffer
) {
3051 uint64_t va
= radv_buffer_get_va(draw_info
->strmout_buffer
->bo
);
3053 va
+= draw_info
->strmout_buffer
->offset
+
3054 draw_info
->strmout_buffer_offset
;
3056 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
3059 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
3060 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
3061 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
3062 COPY_DATA_WR_CONFIRM
);
3063 radeon_emit(cs
, va
);
3064 radeon_emit(cs
, va
>> 32);
3065 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
3066 radeon_emit(cs
, 0); /* unused */
3068 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, draw_info
->strmout_buffer
->bo
);
3072 static void radv_stage_flush(struct radv_cmd_buffer
*cmd_buffer
,
3073 VkPipelineStageFlags src_stage_mask
)
3075 if (src_stage_mask
& (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT
|
3076 VK_PIPELINE_STAGE_TRANSFER_BIT
|
3077 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
3078 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
3079 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
;
3082 if (src_stage_mask
& (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT
|
3083 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
|
3084 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT
|
3085 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
|
3086 VK_PIPELINE_STAGE_TRANSFER_BIT
|
3087 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
|
3088 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT
|
3089 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT
)) {
3090 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
3091 } else if (src_stage_mask
& (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
3092 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
|
3093 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT
|
3094 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT
|
3095 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT
|
3096 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT
|
3097 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT
)) {
3098 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
3102 static enum radv_cmd_flush_bits
3103 radv_src_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
3104 VkAccessFlags src_flags
,
3105 struct radv_image
*image
)
3107 bool flush_CB_meta
= true, flush_DB_meta
= true;
3108 enum radv_cmd_flush_bits flush_bits
= 0;
3112 if (!radv_image_has_CB_metadata(image
))
3113 flush_CB_meta
= false;
3114 if (!radv_image_has_htile(image
))
3115 flush_DB_meta
= false;
3118 for_each_bit(b
, src_flags
) {
3119 switch ((VkAccessFlagBits
)(1 << b
)) {
3120 case VK_ACCESS_SHADER_WRITE_BIT
:
3121 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
:
3122 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
3123 flush_bits
|= RADV_CMD_FLAG_WB_L2
;
3125 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
3126 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
3128 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3130 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
3131 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
3133 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3135 case VK_ACCESS_TRANSFER_WRITE_BIT
:
3136 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3137 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
3138 RADV_CMD_FLAG_INV_L2
;
3141 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3143 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3145 case VK_ACCESS_MEMORY_WRITE_BIT
:
3146 flush_bits
|= RADV_CMD_FLAG_INV_L2
|
3147 RADV_CMD_FLAG_WB_L2
|
3148 RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
3149 RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
3152 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3154 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3163 static enum radv_cmd_flush_bits
3164 radv_dst_access_flush(struct radv_cmd_buffer
*cmd_buffer
,
3165 VkAccessFlags dst_flags
,
3166 struct radv_image
*image
)
3168 bool flush_CB_meta
= true, flush_DB_meta
= true;
3169 enum radv_cmd_flush_bits flush_bits
= 0;
3170 bool flush_CB
= true, flush_DB
= true;
3171 bool image_is_coherent
= false;
3175 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)) {
3180 if (!radv_image_has_CB_metadata(image
))
3181 flush_CB_meta
= false;
3182 if (!radv_image_has_htile(image
))
3183 flush_DB_meta
= false;
3185 /* TODO: implement shader coherent for GFX10 */
3187 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3188 if (image
->info
.samples
== 1 &&
3189 (image
->usage
& (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
3190 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) &&
3191 !vk_format_is_stencil(image
->vk_format
)) {
3192 /* Single-sample color and single-sample depth
3193 * (not stencil) are coherent with shaders on
3196 image_is_coherent
= true;
3201 for_each_bit(b
, dst_flags
) {
3202 switch ((VkAccessFlagBits
)(1 << b
)) {
3203 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
3204 case VK_ACCESS_INDEX_READ_BIT
:
3205 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
:
3207 case VK_ACCESS_UNIFORM_READ_BIT
:
3208 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
| RADV_CMD_FLAG_INV_SCACHE
;
3210 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
3211 case VK_ACCESS_TRANSFER_READ_BIT
:
3212 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
3213 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
3214 RADV_CMD_FLAG_INV_L2
;
3216 case VK_ACCESS_SHADER_READ_BIT
:
3217 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
;
3218 /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
3219 * invalidate the scalar cache. */
3220 if (!cmd_buffer
->device
->physical_device
->use_llvm
)
3221 flush_bits
|= RADV_CMD_FLAG_INV_SCACHE
;
3223 if (!image_is_coherent
)
3224 flush_bits
|= RADV_CMD_FLAG_INV_L2
;
3226 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
:
3228 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
3230 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3232 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
:
3234 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
3236 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3238 case VK_ACCESS_MEMORY_READ_BIT
:
3239 flush_bits
|= RADV_CMD_FLAG_INV_VCACHE
|
3240 RADV_CMD_FLAG_INV_SCACHE
|
3241 RADV_CMD_FLAG_INV_L2
;
3243 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
;
3245 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
3247 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
3249 flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
3258 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
3259 const struct radv_subpass_barrier
*barrier
)
3261 cmd_buffer
->state
.flush_bits
|= radv_src_access_flush(cmd_buffer
, barrier
->src_access_mask
,
3263 radv_stage_flush(cmd_buffer
, barrier
->src_stage_mask
);
3264 cmd_buffer
->state
.flush_bits
|= radv_dst_access_flush(cmd_buffer
, barrier
->dst_access_mask
,
3269 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
)
3271 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3272 uint32_t subpass_id
= state
->subpass
- state
->pass
->subpasses
;
3274 /* The id of this subpass shouldn't exceed the number of subpasses in
3275 * this render pass minus 1.
3277 assert(subpass_id
< state
->pass
->subpass_count
);
3281 static struct radv_sample_locations_state
*
3282 radv_get_attachment_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3286 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3287 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
3288 struct radv_image_view
*view
= state
->attachments
[att_idx
].iview
;
3290 if (view
->image
->info
.samples
== 1)
3293 if (state
->pass
->attachments
[att_idx
].first_subpass_idx
== subpass_id
) {
3294 /* Return the initial sample locations if this is the initial
3295 * layout transition of the given subpass attachemnt.
3297 if (state
->attachments
[att_idx
].sample_location
.count
> 0)
3298 return &state
->attachments
[att_idx
].sample_location
;
3300 /* Otherwise return the subpass sample locations if defined. */
3301 if (state
->subpass_sample_locs
) {
3302 /* Because the driver sets the current subpass before
3303 * initial layout transitions, we should use the sample
3304 * locations from the previous subpass to avoid an
3305 * off-by-one problem. Otherwise, use the sample
3306 * locations for the current subpass for final layout
3312 for (uint32_t i
= 0; i
< state
->num_subpass_sample_locs
; i
++) {
3313 if (state
->subpass_sample_locs
[i
].subpass_idx
== subpass_id
)
3314 return &state
->subpass_sample_locs
[i
].sample_location
;
3322 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
3323 struct radv_subpass_attachment att
,
3326 unsigned idx
= att
.attachment
;
3327 struct radv_image_view
*view
= cmd_buffer
->state
.attachments
[idx
].iview
;
3328 struct radv_sample_locations_state
*sample_locs
;
3329 VkImageSubresourceRange range
;
3330 range
.aspectMask
= view
->aspect_mask
;
3331 range
.baseMipLevel
= view
->base_mip
;
3332 range
.levelCount
= 1;
3333 range
.baseArrayLayer
= view
->base_layer
;
3334 range
.layerCount
= cmd_buffer
->state
.framebuffer
->layers
;
3336 if (cmd_buffer
->state
.subpass
->view_mask
) {
3337 /* If the current subpass uses multiview, the driver might have
3338 * performed a fast color/depth clear to the whole image
3339 * (including all layers). To make sure the driver will
3340 * decompress the image correctly (if needed), we have to
3341 * account for the "real" number of layers. If the view mask is
3342 * sparse, this will decompress more layers than needed.
3344 range
.layerCount
= util_last_bit(cmd_buffer
->state
.subpass
->view_mask
);
3347 /* Get the subpass sample locations for the given attachment, if NULL
3348 * is returned the driver will use the default HW locations.
3350 sample_locs
= radv_get_attachment_sample_locations(cmd_buffer
, idx
,
3353 /* Determine if the subpass uses separate depth/stencil layouts. */
3354 bool uses_separate_depth_stencil_layouts
= false;
3355 if ((cmd_buffer
->state
.attachments
[idx
].current_layout
!=
3356 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
) ||
3357 (att
.layout
!= att
.stencil_layout
)) {
3358 uses_separate_depth_stencil_layouts
= true;
3361 /* For separate layouts, perform depth and stencil transitions
3364 if (uses_separate_depth_stencil_layouts
&&
3365 (range
.aspectMask
== (VK_IMAGE_ASPECT_DEPTH_BIT
|
3366 VK_IMAGE_ASPECT_STENCIL_BIT
))) {
3367 /* Depth-only transitions. */
3368 range
.aspectMask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
3369 radv_handle_image_transition(cmd_buffer
,
3371 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3372 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3373 att
.layout
, att
.in_render_loop
,
3374 0, 0, &range
, sample_locs
);
3376 /* Stencil-only transitions. */
3377 range
.aspectMask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
3378 radv_handle_image_transition(cmd_buffer
,
3380 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
,
3381 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3382 att
.stencil_layout
, att
.in_render_loop
,
3383 0, 0, &range
, sample_locs
);
3385 radv_handle_image_transition(cmd_buffer
,
3387 cmd_buffer
->state
.attachments
[idx
].current_layout
,
3388 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
,
3389 att
.layout
, att
.in_render_loop
,
3390 0, 0, &range
, sample_locs
);
3393 cmd_buffer
->state
.attachments
[idx
].current_layout
= att
.layout
;
3394 cmd_buffer
->state
.attachments
[idx
].current_stencil_layout
= att
.stencil_layout
;
3395 cmd_buffer
->state
.attachments
[idx
].current_in_render_loop
= att
.in_render_loop
;
3401 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
3402 const struct radv_subpass
*subpass
)
3404 cmd_buffer
->state
.subpass
= subpass
;
3406 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_FRAMEBUFFER
;
3410 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer
*cmd_buffer
,
3411 struct radv_render_pass
*pass
,
3412 const VkRenderPassBeginInfo
*info
)
3414 const struct VkRenderPassSampleLocationsBeginInfoEXT
*sample_locs
=
3415 vk_find_struct_const(info
->pNext
,
3416 RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT
);
3417 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3420 state
->subpass_sample_locs
= NULL
;
3424 for (uint32_t i
= 0; i
< sample_locs
->attachmentInitialSampleLocationsCount
; i
++) {
3425 const VkAttachmentSampleLocationsEXT
*att_sample_locs
=
3426 &sample_locs
->pAttachmentInitialSampleLocations
[i
];
3427 uint32_t att_idx
= att_sample_locs
->attachmentIndex
;
3428 struct radv_image
*image
= cmd_buffer
->state
.attachments
[att_idx
].iview
->image
;
3430 assert(vk_format_is_depth_or_stencil(image
->vk_format
));
3432 /* From the Vulkan spec 1.1.108:
3434 * "If the image referenced by the framebuffer attachment at
3435 * index attachmentIndex was not created with
3436 * VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
3437 * then the values specified in sampleLocationsInfo are
3440 if (!(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
))
3443 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3444 &att_sample_locs
->sampleLocationsInfo
;
3446 state
->attachments
[att_idx
].sample_location
.per_pixel
=
3447 sample_locs_info
->sampleLocationsPerPixel
;
3448 state
->attachments
[att_idx
].sample_location
.grid_size
=
3449 sample_locs_info
->sampleLocationGridSize
;
3450 state
->attachments
[att_idx
].sample_location
.count
=
3451 sample_locs_info
->sampleLocationsCount
;
3452 typed_memcpy(&state
->attachments
[att_idx
].sample_location
.locations
[0],
3453 sample_locs_info
->pSampleLocations
,
3454 sample_locs_info
->sampleLocationsCount
);
3457 state
->subpass_sample_locs
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3458 sample_locs
->postSubpassSampleLocationsCount
*
3459 sizeof(state
->subpass_sample_locs
[0]),
3460 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3461 if (state
->subpass_sample_locs
== NULL
) {
3462 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3463 return cmd_buffer
->record_result
;
3466 state
->num_subpass_sample_locs
= sample_locs
->postSubpassSampleLocationsCount
;
3468 for (uint32_t i
= 0; i
< sample_locs
->postSubpassSampleLocationsCount
; i
++) {
3469 const VkSubpassSampleLocationsEXT
*subpass_sample_locs_info
=
3470 &sample_locs
->pPostSubpassSampleLocations
[i
];
3471 const VkSampleLocationsInfoEXT
*sample_locs_info
=
3472 &subpass_sample_locs_info
->sampleLocationsInfo
;
3474 state
->subpass_sample_locs
[i
].subpass_idx
=
3475 subpass_sample_locs_info
->subpassIndex
;
3476 state
->subpass_sample_locs
[i
].sample_location
.per_pixel
=
3477 sample_locs_info
->sampleLocationsPerPixel
;
3478 state
->subpass_sample_locs
[i
].sample_location
.grid_size
=
3479 sample_locs_info
->sampleLocationGridSize
;
3480 state
->subpass_sample_locs
[i
].sample_location
.count
=
3481 sample_locs_info
->sampleLocationsCount
;
3482 typed_memcpy(&state
->subpass_sample_locs
[i
].sample_location
.locations
[0],
3483 sample_locs_info
->pSampleLocations
,
3484 sample_locs_info
->sampleLocationsCount
);
3491 radv_cmd_state_setup_attachments(struct radv_cmd_buffer
*cmd_buffer
,
3492 struct radv_render_pass
*pass
,
3493 const VkRenderPassBeginInfo
*info
)
3495 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
3496 const struct VkRenderPassAttachmentBeginInfo
*attachment_info
= NULL
;
3499 attachment_info
= vk_find_struct_const(info
->pNext
,
3500 RENDER_PASS_ATTACHMENT_BEGIN_INFO
);
3504 if (pass
->attachment_count
== 0) {
3505 state
->attachments
= NULL
;
3509 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
3510 pass
->attachment_count
*
3511 sizeof(state
->attachments
[0]),
3512 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3513 if (state
->attachments
== NULL
) {
3514 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3515 return cmd_buffer
->record_result
;
3518 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
3519 struct radv_render_pass_attachment
*att
= &pass
->attachments
[i
];
3520 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
3521 VkImageAspectFlags clear_aspects
= 0;
3523 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
3524 /* color attachment */
3525 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3526 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
3529 /* depthstencil attachment */
3530 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
3531 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3532 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
3533 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3534 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
3535 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3537 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
3538 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
3539 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
3543 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
3544 state
->attachments
[i
].cleared_views
= 0;
3545 if (clear_aspects
&& info
) {
3546 assert(info
->clearValueCount
> i
);
3547 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
3550 state
->attachments
[i
].current_layout
= att
->initial_layout
;
3551 state
->attachments
[i
].current_in_render_loop
= false;
3552 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
3553 state
->attachments
[i
].sample_location
.count
= 0;
3555 struct radv_image_view
*iview
;
3556 if (attachment_info
&& attachment_info
->attachmentCount
> i
) {
3557 iview
= radv_image_view_from_handle(attachment_info
->pAttachments
[i
]);
3559 iview
= state
->framebuffer
->attachments
[i
];
3562 state
->attachments
[i
].iview
= iview
;
3563 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3564 radv_initialise_ds_surface(cmd_buffer
->device
, &state
->attachments
[i
].ds
, iview
);
3566 radv_initialise_color_surface(cmd_buffer
->device
, &state
->attachments
[i
].cb
, iview
);
3573 VkResult
radv_AllocateCommandBuffers(
3575 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
3576 VkCommandBuffer
*pCommandBuffers
)
3578 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3579 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
3581 VkResult result
= VK_SUCCESS
;
3584 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
3586 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
3587 struct radv_cmd_buffer
*cmd_buffer
= list_first_entry(&pool
->free_cmd_buffers
, struct radv_cmd_buffer
, pool_link
);
3589 list_del(&cmd_buffer
->pool_link
);
3590 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
3592 result
= radv_reset_cmd_buffer(cmd_buffer
);
3593 cmd_buffer
->level
= pAllocateInfo
->level
;
3595 pCommandBuffers
[i
] = radv_cmd_buffer_to_handle(cmd_buffer
);
3597 result
= radv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
3598 &pCommandBuffers
[i
]);
3600 if (result
!= VK_SUCCESS
)
3604 if (result
!= VK_SUCCESS
) {
3605 radv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
3606 i
, pCommandBuffers
);
3608 /* From the Vulkan 1.0.66 spec:
3610 * "vkAllocateCommandBuffers can be used to create multiple
3611 * command buffers. If the creation of any of those command
3612 * buffers fails, the implementation must destroy all
3613 * successfully created command buffer objects from this
3614 * command, set all entries of the pCommandBuffers array to
3615 * NULL and return the error."
3617 memset(pCommandBuffers
, 0,
3618 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
3624 void radv_FreeCommandBuffers(
3626 VkCommandPool commandPool
,
3627 uint32_t commandBufferCount
,
3628 const VkCommandBuffer
*pCommandBuffers
)
3630 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
3631 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
3634 if (cmd_buffer
->pool
) {
3635 list_del(&cmd_buffer
->pool_link
);
3636 list_addtail(&cmd_buffer
->pool_link
, &cmd_buffer
->pool
->free_cmd_buffers
);
3638 radv_destroy_cmd_buffer(cmd_buffer
);
3644 VkResult
radv_ResetCommandBuffer(
3645 VkCommandBuffer commandBuffer
,
3646 VkCommandBufferResetFlags flags
)
3648 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3649 return radv_reset_cmd_buffer(cmd_buffer
);
3652 VkResult
radv_BeginCommandBuffer(
3653 VkCommandBuffer commandBuffer
,
3654 const VkCommandBufferBeginInfo
*pBeginInfo
)
3656 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3657 VkResult result
= VK_SUCCESS
;
3659 if (cmd_buffer
->status
!= RADV_CMD_BUFFER_STATUS_INITIAL
) {
3660 /* If the command buffer has already been resetted with
3661 * vkResetCommandBuffer, no need to do it again.
3663 result
= radv_reset_cmd_buffer(cmd_buffer
);
3664 if (result
!= VK_SUCCESS
)
3668 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
3669 cmd_buffer
->state
.last_primitive_reset_en
= -1;
3670 cmd_buffer
->state
.last_index_type
= -1;
3671 cmd_buffer
->state
.last_num_instances
= -1;
3672 cmd_buffer
->state
.last_vertex_offset
= -1;
3673 cmd_buffer
->state
.last_first_instance
= -1;
3674 cmd_buffer
->state
.predication_type
= -1;
3675 cmd_buffer
->state
.last_sx_ps_downconvert
= -1;
3676 cmd_buffer
->state
.last_sx_blend_opt_epsilon
= -1;
3677 cmd_buffer
->state
.last_sx_blend_opt_control
= -1;
3678 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
3680 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
&&
3681 (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
)) {
3682 assert(pBeginInfo
->pInheritanceInfo
);
3683 cmd_buffer
->state
.framebuffer
= radv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
3684 cmd_buffer
->state
.pass
= radv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
3686 struct radv_subpass
*subpass
=
3687 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
3689 if (cmd_buffer
->state
.framebuffer
) {
3690 result
= radv_cmd_state_setup_attachments(cmd_buffer
, cmd_buffer
->state
.pass
, NULL
);
3691 if (result
!= VK_SUCCESS
)
3695 cmd_buffer
->state
.inherited_pipeline_statistics
=
3696 pBeginInfo
->pInheritanceInfo
->pipelineStatistics
;
3698 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
3701 if (unlikely(cmd_buffer
->device
->trace_bo
))
3702 radv_cmd_buffer_trace_emit(cmd_buffer
);
3704 radv_describe_begin_cmd_buffer(cmd_buffer
);
3706 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_RECORDING
;
3711 void radv_CmdBindVertexBuffers(
3712 VkCommandBuffer commandBuffer
,
3713 uint32_t firstBinding
,
3714 uint32_t bindingCount
,
3715 const VkBuffer
* pBuffers
,
3716 const VkDeviceSize
* pOffsets
)
3718 radv_CmdBindVertexBuffers2EXT(commandBuffer
, firstBinding
,
3719 bindingCount
, pBuffers
, pOffsets
,
3723 void radv_CmdBindVertexBuffers2EXT(
3724 VkCommandBuffer commandBuffer
,
3725 uint32_t firstBinding
,
3726 uint32_t bindingCount
,
3727 const VkBuffer
* pBuffers
,
3728 const VkDeviceSize
* pOffsets
,
3729 const VkDeviceSize
* pSizes
,
3730 const VkDeviceSize
* pStrides
)
3732 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3733 struct radv_vertex_binding
*vb
= cmd_buffer
->vertex_bindings
;
3734 bool changed
= false;
3736 /* We have to defer setting up vertex buffer since we need the buffer
3737 * stride from the pipeline. */
3739 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
3740 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
3741 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBuffers
[i
]);
3742 uint32_t idx
= firstBinding
+ i
;
3743 VkDeviceSize size
= pSizes
? pSizes
[i
] : 0;
3744 VkDeviceSize stride
= pStrides
? pStrides
[i
] : 0;
3746 /* pSizes and pStrides are optional. */
3748 (vb
[idx
].buffer
!= buffer
||
3749 vb
[idx
].offset
!= pOffsets
[i
] ||
3750 vb
[idx
].size
!= size
||
3751 vb
[idx
].stride
!= stride
)) {
3755 vb
[idx
].buffer
= buffer
;
3756 vb
[idx
].offset
= pOffsets
[i
];
3757 vb
[idx
].size
= size
;
3758 vb
[idx
].stride
= stride
;
3761 radv_cs_add_buffer(cmd_buffer
->device
->ws
,
3762 cmd_buffer
->cs
, vb
[idx
].buffer
->bo
);
3767 /* No state changes. */
3771 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_VERTEX_BUFFER
;
3775 vk_to_index_type(VkIndexType type
)
3778 case VK_INDEX_TYPE_UINT8_EXT
:
3779 return V_028A7C_VGT_INDEX_8
;
3780 case VK_INDEX_TYPE_UINT16
:
3781 return V_028A7C_VGT_INDEX_16
;
3782 case VK_INDEX_TYPE_UINT32
:
3783 return V_028A7C_VGT_INDEX_32
;
3785 unreachable("invalid index type");
3790 radv_get_vgt_index_size(uint32_t type
)
3793 case V_028A7C_VGT_INDEX_8
:
3795 case V_028A7C_VGT_INDEX_16
:
3797 case V_028A7C_VGT_INDEX_32
:
3800 unreachable("invalid index type");
3804 void radv_CmdBindIndexBuffer(
3805 VkCommandBuffer commandBuffer
,
3807 VkDeviceSize offset
,
3808 VkIndexType indexType
)
3810 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3811 RADV_FROM_HANDLE(radv_buffer
, index_buffer
, buffer
);
3813 if (cmd_buffer
->state
.index_buffer
== index_buffer
&&
3814 cmd_buffer
->state
.index_offset
== offset
&&
3815 cmd_buffer
->state
.index_type
== indexType
) {
3816 /* No state changes. */
3820 cmd_buffer
->state
.index_buffer
= index_buffer
;
3821 cmd_buffer
->state
.index_offset
= offset
;
3822 cmd_buffer
->state
.index_type
= vk_to_index_type(indexType
);
3823 cmd_buffer
->state
.index_va
= radv_buffer_get_va(index_buffer
->bo
);
3824 cmd_buffer
->state
.index_va
+= index_buffer
->offset
+ offset
;
3826 int index_size
= radv_get_vgt_index_size(vk_to_index_type(indexType
));
3827 cmd_buffer
->state
.max_index_count
= (index_buffer
->size
- offset
) / index_size
;
3828 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
3829 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, index_buffer
->bo
);
3834 radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3835 VkPipelineBindPoint bind_point
,
3836 struct radv_descriptor_set
*set
, unsigned idx
)
3838 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
3840 radv_set_descriptor_set(cmd_buffer
, bind_point
, set
, idx
);
3843 assert(!(set
->layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
));
3845 if (!cmd_buffer
->device
->use_global_bo_list
) {
3846 for (unsigned j
= 0; j
< set
->buffer_count
; ++j
)
3847 if (set
->descriptors
[j
])
3848 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->descriptors
[j
]);
3852 radv_cs_add_buffer(ws
, cmd_buffer
->cs
, set
->bo
);
3855 void radv_CmdBindDescriptorSets(
3856 VkCommandBuffer commandBuffer
,
3857 VkPipelineBindPoint pipelineBindPoint
,
3858 VkPipelineLayout _layout
,
3860 uint32_t descriptorSetCount
,
3861 const VkDescriptorSet
* pDescriptorSets
,
3862 uint32_t dynamicOffsetCount
,
3863 const uint32_t* pDynamicOffsets
)
3865 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3866 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3867 unsigned dyn_idx
= 0;
3869 const bool no_dynamic_bounds
= cmd_buffer
->device
->instance
->debug_flags
& RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
3870 struct radv_descriptor_state
*descriptors_state
=
3871 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3873 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
3874 unsigned idx
= i
+ firstSet
;
3875 RADV_FROM_HANDLE(radv_descriptor_set
, set
, pDescriptorSets
[i
]);
3877 /* If the set is already bound we only need to update the
3878 * (potentially changed) dynamic offsets. */
3879 if (descriptors_state
->sets
[idx
] != set
||
3880 !(descriptors_state
->valid
& (1u << idx
))) {
3881 radv_bind_descriptor_set(cmd_buffer
, pipelineBindPoint
, set
, idx
);
3884 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
3885 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
3886 uint32_t *dst
= descriptors_state
->dynamic_buffers
+ idx
* 4;
3887 assert(dyn_idx
< dynamicOffsetCount
);
3889 struct radv_descriptor_range
*range
= set
->dynamic_descriptors
+ j
;
3890 uint64_t va
= range
->va
+ pDynamicOffsets
[dyn_idx
];
3892 dst
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32);
3893 dst
[2] = no_dynamic_bounds
? 0xffffffffu
: range
->size
;
3894 dst
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3895 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3896 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3897 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3899 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3900 dst
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3901 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3902 S_008F0C_RESOURCE_LEVEL(1);
3904 dst
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3905 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3908 cmd_buffer
->push_constant_stages
|=
3909 set
->layout
->dynamic_shader_stages
;
3914 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
3915 struct radv_descriptor_set
*set
,
3916 struct radv_descriptor_set_layout
*layout
,
3917 VkPipelineBindPoint bind_point
)
3919 struct radv_descriptor_state
*descriptors_state
=
3920 radv_get_descriptors_state(cmd_buffer
, bind_point
);
3921 set
->size
= layout
->size
;
3922 set
->layout
= layout
;
3924 if (descriptors_state
->push_set
.capacity
< set
->size
) {
3925 size_t new_size
= MAX2(set
->size
, 1024);
3926 new_size
= MAX2(new_size
, 2 * descriptors_state
->push_set
.capacity
);
3927 new_size
= MIN2(new_size
, 96 * MAX_PUSH_DESCRIPTORS
);
3929 free(set
->mapped_ptr
);
3930 set
->mapped_ptr
= malloc(new_size
);
3932 if (!set
->mapped_ptr
) {
3933 descriptors_state
->push_set
.capacity
= 0;
3934 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
3938 descriptors_state
->push_set
.capacity
= new_size
;
3944 void radv_meta_push_descriptor_set(
3945 struct radv_cmd_buffer
* cmd_buffer
,
3946 VkPipelineBindPoint pipelineBindPoint
,
3947 VkPipelineLayout _layout
,
3949 uint32_t descriptorWriteCount
,
3950 const VkWriteDescriptorSet
* pDescriptorWrites
)
3952 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3953 struct radv_descriptor_set
*push_set
= &cmd_buffer
->meta_push_descriptors
;
3957 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3959 push_set
->size
= layout
->set
[set
].layout
->size
;
3960 push_set
->layout
= layout
->set
[set
].layout
;
3962 if (!radv_cmd_buffer_upload_alloc(cmd_buffer
, push_set
->size
, 32,
3964 (void**) &push_set
->mapped_ptr
))
3967 push_set
->va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
);
3968 push_set
->va
+= bo_offset
;
3970 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
3971 radv_descriptor_set_to_handle(push_set
),
3972 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
3974 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
3977 void radv_CmdPushDescriptorSetKHR(
3978 VkCommandBuffer commandBuffer
,
3979 VkPipelineBindPoint pipelineBindPoint
,
3980 VkPipelineLayout _layout
,
3982 uint32_t descriptorWriteCount
,
3983 const VkWriteDescriptorSet
* pDescriptorWrites
)
3985 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3986 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
3987 struct radv_descriptor_state
*descriptors_state
=
3988 radv_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
3989 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
3991 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
3993 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
3994 layout
->set
[set
].layout
,
3998 /* Check that there are no inline uniform block updates when calling vkCmdPushDescriptorSetKHR()
3999 * because it is invalid, according to Vulkan spec.
4001 for (int i
= 0; i
< descriptorWriteCount
; i
++) {
4002 ASSERTED
const VkWriteDescriptorSet
*writeset
= &pDescriptorWrites
[i
];
4003 assert(writeset
->descriptorType
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
);
4006 radv_update_descriptor_sets(cmd_buffer
->device
, cmd_buffer
,
4007 radv_descriptor_set_to_handle(push_set
),
4008 descriptorWriteCount
, pDescriptorWrites
, 0, NULL
);
4010 radv_set_descriptor_set(cmd_buffer
, pipelineBindPoint
, push_set
, set
);
4011 descriptors_state
->push_dirty
= true;
4014 void radv_CmdPushDescriptorSetWithTemplateKHR(
4015 VkCommandBuffer commandBuffer
,
4016 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
4017 VkPipelineLayout _layout
,
4021 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4022 RADV_FROM_HANDLE(radv_pipeline_layout
, layout
, _layout
);
4023 RADV_FROM_HANDLE(radv_descriptor_update_template
, templ
, descriptorUpdateTemplate
);
4024 struct radv_descriptor_state
*descriptors_state
=
4025 radv_get_descriptors_state(cmd_buffer
, templ
->bind_point
);
4026 struct radv_descriptor_set
*push_set
= &descriptors_state
->push_set
.set
;
4028 assert(layout
->set
[set
].layout
->flags
& VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
);
4030 if (!radv_init_push_descriptor_set(cmd_buffer
, push_set
,
4031 layout
->set
[set
].layout
,
4035 radv_update_descriptor_set_with_template(cmd_buffer
->device
, cmd_buffer
, push_set
,
4036 descriptorUpdateTemplate
, pData
);
4038 radv_set_descriptor_set(cmd_buffer
, templ
->bind_point
, push_set
, set
);
4039 descriptors_state
->push_dirty
= true;
4042 void radv_CmdPushConstants(VkCommandBuffer commandBuffer
,
4043 VkPipelineLayout layout
,
4044 VkShaderStageFlags stageFlags
,
4047 const void* pValues
)
4049 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4050 memcpy(cmd_buffer
->push_constants
+ offset
, pValues
, size
);
4051 cmd_buffer
->push_constant_stages
|= stageFlags
;
4054 VkResult
radv_EndCommandBuffer(
4055 VkCommandBuffer commandBuffer
)
4057 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4059 if (cmd_buffer
->queue_family_index
!= RADV_QUEUE_TRANSFER
) {
4060 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX6
)
4061 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
| RADV_CMD_FLAG_WB_L2
;
4063 /* Make sure to sync all pending active queries at the end of
4066 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
4068 /* Since NGG streamout uses GDS, we need to make GDS idle when
4069 * we leave the IB, otherwise another process might overwrite
4070 * it while our shaders are busy.
4072 if (cmd_buffer
->gds_needed
)
4073 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
;
4075 si_emit_cache_flush(cmd_buffer
);
4078 /* Make sure CP DMA is idle at the end of IBs because the kernel
4079 * doesn't wait for it.
4081 si_cp_dma_wait_for_idle(cmd_buffer
);
4083 radv_describe_end_cmd_buffer(cmd_buffer
);
4085 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
4086 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
4088 VkResult result
= cmd_buffer
->device
->ws
->cs_finalize(cmd_buffer
->cs
);
4089 if (result
!= VK_SUCCESS
)
4090 return vk_error(cmd_buffer
->device
->instance
, result
);
4092 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_EXECUTABLE
;
4094 return cmd_buffer
->record_result
;
4098 radv_emit_compute_pipeline(struct radv_cmd_buffer
*cmd_buffer
)
4100 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
4102 if (!pipeline
|| pipeline
== cmd_buffer
->state
.emitted_compute_pipeline
)
4105 assert(!pipeline
->ctx_cs
.cdw
);
4107 cmd_buffer
->state
.emitted_compute_pipeline
= pipeline
;
4109 radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pipeline
->cs
.cdw
);
4110 radeon_emit_array(cmd_buffer
->cs
, pipeline
->cs
.buf
, pipeline
->cs
.cdw
);
4112 cmd_buffer
->compute_scratch_size_per_wave_needed
= MAX2(cmd_buffer
->compute_scratch_size_per_wave_needed
,
4113 pipeline
->scratch_bytes_per_wave
);
4114 cmd_buffer
->compute_scratch_waves_wanted
= MAX2(cmd_buffer
->compute_scratch_waves_wanted
,
4115 pipeline
->max_waves
);
4117 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
4118 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->bo
);
4120 if (unlikely(cmd_buffer
->device
->trace_bo
))
4121 radv_save_pipeline(cmd_buffer
, pipeline
, RING_COMPUTE
);
4124 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer
*cmd_buffer
,
4125 VkPipelineBindPoint bind_point
)
4127 struct radv_descriptor_state
*descriptors_state
=
4128 radv_get_descriptors_state(cmd_buffer
, bind_point
);
4130 descriptors_state
->dirty
|= descriptors_state
->valid
;
4133 void radv_CmdBindPipeline(
4134 VkCommandBuffer commandBuffer
,
4135 VkPipelineBindPoint pipelineBindPoint
,
4136 VkPipeline _pipeline
)
4138 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4139 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
4141 switch (pipelineBindPoint
) {
4142 case VK_PIPELINE_BIND_POINT_COMPUTE
:
4143 if (cmd_buffer
->state
.compute_pipeline
== pipeline
)
4145 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
4147 cmd_buffer
->state
.compute_pipeline
= pipeline
;
4148 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4150 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
4151 if (cmd_buffer
->state
.pipeline
== pipeline
)
4153 radv_mark_descriptor_sets_dirty(cmd_buffer
, pipelineBindPoint
);
4155 cmd_buffer
->state
.pipeline
= pipeline
;
4159 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
4160 cmd_buffer
->push_constant_stages
|= pipeline
->active_stages
;
4162 /* the new vertex shader might not have the same user regs */
4163 cmd_buffer
->state
.last_first_instance
= -1;
4164 cmd_buffer
->state
.last_vertex_offset
= -1;
4166 /* Prefetch all pipeline shaders at first draw time. */
4167 cmd_buffer
->state
.prefetch_L2_mask
|= RADV_PREFETCH_SHADERS
;
4169 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4170 cmd_buffer
->state
.emitted_pipeline
&&
4171 radv_pipeline_has_ngg(cmd_buffer
->state
.emitted_pipeline
) &&
4172 !radv_pipeline_has_ngg(cmd_buffer
->state
.pipeline
)) {
4173 /* Transitioning from NGG to legacy GS requires
4174 * VGT_FLUSH on Navi10-14. VGT_FLUSH is also emitted
4175 * at the beginning of IBs when legacy GS ring pointers
4178 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_FLUSH
;
4181 radv_bind_dynamic_state(cmd_buffer
, &pipeline
->dynamic_state
);
4182 radv_bind_streamout_state(cmd_buffer
, pipeline
);
4184 if (pipeline
->graphics
.esgs_ring_size
> cmd_buffer
->esgs_ring_size_needed
)
4185 cmd_buffer
->esgs_ring_size_needed
= pipeline
->graphics
.esgs_ring_size
;
4186 if (pipeline
->graphics
.gsvs_ring_size
> cmd_buffer
->gsvs_ring_size_needed
)
4187 cmd_buffer
->gsvs_ring_size_needed
= pipeline
->graphics
.gsvs_ring_size
;
4189 if (radv_pipeline_has_tess(pipeline
))
4190 cmd_buffer
->tess_rings_needed
= true;
4193 assert(!"invalid bind point");
4198 void radv_CmdSetViewport(
4199 VkCommandBuffer commandBuffer
,
4200 uint32_t firstViewport
,
4201 uint32_t viewportCount
,
4202 const VkViewport
* pViewports
)
4204 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4205 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4206 ASSERTED
const uint32_t total_count
= firstViewport
+ viewportCount
;
4208 assert(firstViewport
< MAX_VIEWPORTS
);
4209 assert(total_count
>= 1 && total_count
<= MAX_VIEWPORTS
);
4211 if (total_count
<= state
->dynamic
.viewport
.count
&&
4212 !memcmp(state
->dynamic
.viewport
.viewports
+ firstViewport
,
4213 pViewports
, viewportCount
* sizeof(*pViewports
))) {
4217 if (state
->dynamic
.viewport
.count
< total_count
)
4218 state
->dynamic
.viewport
.count
= total_count
;
4220 memcpy(state
->dynamic
.viewport
.viewports
+ firstViewport
, pViewports
,
4221 viewportCount
* sizeof(*pViewports
));
4223 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
4226 void radv_CmdSetScissor(
4227 VkCommandBuffer commandBuffer
,
4228 uint32_t firstScissor
,
4229 uint32_t scissorCount
,
4230 const VkRect2D
* pScissors
)
4232 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4233 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4234 ASSERTED
const uint32_t total_count
= firstScissor
+ scissorCount
;
4236 assert(firstScissor
< MAX_SCISSORS
);
4237 assert(total_count
>= 1 && total_count
<= MAX_SCISSORS
);
4239 if (total_count
<= state
->dynamic
.scissor
.count
&&
4240 !memcmp(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
4241 scissorCount
* sizeof(*pScissors
))) {
4245 if (state
->dynamic
.scissor
.count
< total_count
)
4246 state
->dynamic
.scissor
.count
= total_count
;
4248 memcpy(state
->dynamic
.scissor
.scissors
+ firstScissor
, pScissors
,
4249 scissorCount
* sizeof(*pScissors
));
4251 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SCISSOR
;
4254 void radv_CmdSetLineWidth(
4255 VkCommandBuffer commandBuffer
,
4258 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4260 if (cmd_buffer
->state
.dynamic
.line_width
== lineWidth
)
4263 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
4264 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
4267 void radv_CmdSetDepthBias(
4268 VkCommandBuffer commandBuffer
,
4269 float depthBiasConstantFactor
,
4270 float depthBiasClamp
,
4271 float depthBiasSlopeFactor
)
4273 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4274 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4276 if (state
->dynamic
.depth_bias
.bias
== depthBiasConstantFactor
&&
4277 state
->dynamic
.depth_bias
.clamp
== depthBiasClamp
&&
4278 state
->dynamic
.depth_bias
.slope
== depthBiasSlopeFactor
) {
4282 state
->dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
4283 state
->dynamic
.depth_bias
.clamp
= depthBiasClamp
;
4284 state
->dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
4286 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
4289 void radv_CmdSetBlendConstants(
4290 VkCommandBuffer commandBuffer
,
4291 const float blendConstants
[4])
4293 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4294 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4296 if (!memcmp(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4))
4299 memcpy(state
->dynamic
.blend_constants
, blendConstants
, sizeof(float) * 4);
4301 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
4304 void radv_CmdSetDepthBounds(
4305 VkCommandBuffer commandBuffer
,
4306 float minDepthBounds
,
4307 float maxDepthBounds
)
4309 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4310 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4312 if (state
->dynamic
.depth_bounds
.min
== minDepthBounds
&&
4313 state
->dynamic
.depth_bounds
.max
== maxDepthBounds
) {
4317 state
->dynamic
.depth_bounds
.min
= minDepthBounds
;
4318 state
->dynamic
.depth_bounds
.max
= maxDepthBounds
;
4320 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
4323 void radv_CmdSetStencilCompareMask(
4324 VkCommandBuffer commandBuffer
,
4325 VkStencilFaceFlags faceMask
,
4326 uint32_t compareMask
)
4328 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4329 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4330 bool front_same
= state
->dynamic
.stencil_compare_mask
.front
== compareMask
;
4331 bool back_same
= state
->dynamic
.stencil_compare_mask
.back
== compareMask
;
4333 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4334 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4338 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4339 state
->dynamic
.stencil_compare_mask
.front
= compareMask
;
4340 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4341 state
->dynamic
.stencil_compare_mask
.back
= compareMask
;
4343 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
4346 void radv_CmdSetStencilWriteMask(
4347 VkCommandBuffer commandBuffer
,
4348 VkStencilFaceFlags faceMask
,
4351 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4352 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4353 bool front_same
= state
->dynamic
.stencil_write_mask
.front
== writeMask
;
4354 bool back_same
= state
->dynamic
.stencil_write_mask
.back
== writeMask
;
4356 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4357 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4361 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4362 state
->dynamic
.stencil_write_mask
.front
= writeMask
;
4363 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4364 state
->dynamic
.stencil_write_mask
.back
= writeMask
;
4366 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
4369 void radv_CmdSetStencilReference(
4370 VkCommandBuffer commandBuffer
,
4371 VkStencilFaceFlags faceMask
,
4374 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4375 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4376 bool front_same
= state
->dynamic
.stencil_reference
.front
== reference
;
4377 bool back_same
= state
->dynamic
.stencil_reference
.back
== reference
;
4379 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4380 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
)) {
4384 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
4385 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
4386 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
4387 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
4389 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
4392 void radv_CmdSetDiscardRectangleEXT(
4393 VkCommandBuffer commandBuffer
,
4394 uint32_t firstDiscardRectangle
,
4395 uint32_t discardRectangleCount
,
4396 const VkRect2D
* pDiscardRectangles
)
4398 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4399 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4400 ASSERTED
const uint32_t total_count
= firstDiscardRectangle
+ discardRectangleCount
;
4402 assert(firstDiscardRectangle
< MAX_DISCARD_RECTANGLES
);
4403 assert(total_count
>= 1 && total_count
<= MAX_DISCARD_RECTANGLES
);
4405 if (!memcmp(state
->dynamic
.discard_rectangle
.rectangles
+ firstDiscardRectangle
,
4406 pDiscardRectangles
, discardRectangleCount
* sizeof(*pDiscardRectangles
))) {
4410 typed_memcpy(&state
->dynamic
.discard_rectangle
.rectangles
[firstDiscardRectangle
],
4411 pDiscardRectangles
, discardRectangleCount
);
4413 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
;
4416 void radv_CmdSetSampleLocationsEXT(
4417 VkCommandBuffer commandBuffer
,
4418 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
4420 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4421 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4423 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
4425 state
->dynamic
.sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
4426 state
->dynamic
.sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
4427 state
->dynamic
.sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
4428 typed_memcpy(&state
->dynamic
.sample_location
.locations
[0],
4429 pSampleLocationsInfo
->pSampleLocations
,
4430 pSampleLocationsInfo
->sampleLocationsCount
);
4432 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
;
4435 void radv_CmdSetLineStippleEXT(
4436 VkCommandBuffer commandBuffer
,
4437 uint32_t lineStippleFactor
,
4438 uint16_t lineStipplePattern
)
4440 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4441 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4443 state
->dynamic
.line_stipple
.factor
= lineStippleFactor
;
4444 state
->dynamic
.line_stipple
.pattern
= lineStipplePattern
;
4446 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
;
4449 void radv_CmdSetCullModeEXT(
4450 VkCommandBuffer commandBuffer
,
4451 VkCullModeFlags cullMode
)
4453 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4454 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4456 if (state
->dynamic
.cull_mode
== cullMode
)
4459 state
->dynamic
.cull_mode
= cullMode
;
4461 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE
;
4464 void radv_CmdSetFrontFaceEXT(
4465 VkCommandBuffer commandBuffer
,
4466 VkFrontFace frontFace
)
4468 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4469 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4471 if (state
->dynamic
.front_face
== frontFace
)
4474 state
->dynamic
.front_face
= frontFace
;
4476 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE
;
4479 void radv_CmdSetPrimitiveTopologyEXT(
4480 VkCommandBuffer commandBuffer
,
4481 VkPrimitiveTopology primitiveTopology
)
4483 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4484 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4485 unsigned primitive_topology
= si_translate_prim(primitiveTopology
);
4487 if (state
->dynamic
.primitive_topology
== primitive_topology
)
4490 state
->dynamic
.primitive_topology
= primitive_topology
;
4492 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
;
4495 void radv_CmdSetViewportWithCountEXT(
4496 VkCommandBuffer commandBuffer
,
4497 uint32_t viewportCount
,
4498 const VkViewport
* pViewports
)
4500 radv_CmdSetViewport(commandBuffer
, 0, viewportCount
, pViewports
);
4503 void radv_CmdSetScissorWithCountEXT(
4504 VkCommandBuffer commandBuffer
,
4505 uint32_t scissorCount
,
4506 const VkRect2D
* pScissors
)
4508 radv_CmdSetScissor(commandBuffer
, 0, scissorCount
, pScissors
);
4511 void radv_CmdSetDepthTestEnableEXT(
4512 VkCommandBuffer commandBuffer
,
4513 VkBool32 depthTestEnable
)
4516 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4517 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4519 if (state
->dynamic
.depth_test_enable
== depthTestEnable
)
4522 state
->dynamic
.depth_test_enable
= depthTestEnable
;
4524 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
;
4527 void radv_CmdSetDepthWriteEnableEXT(
4528 VkCommandBuffer commandBuffer
,
4529 VkBool32 depthWriteEnable
)
4531 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4532 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4534 if (state
->dynamic
.depth_write_enable
== depthWriteEnable
)
4537 state
->dynamic
.depth_write_enable
= depthWriteEnable
;
4539 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
;
4542 void radv_CmdSetDepthCompareOpEXT(
4543 VkCommandBuffer commandBuffer
,
4544 VkCompareOp depthCompareOp
)
4546 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4547 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4549 if (state
->dynamic
.depth_compare_op
== depthCompareOp
)
4552 state
->dynamic
.depth_compare_op
= depthCompareOp
;
4554 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
;
4557 void radv_CmdSetDepthBoundsTestEnableEXT(
4558 VkCommandBuffer commandBuffer
,
4559 VkBool32 depthBoundsTestEnable
)
4561 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4562 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4564 if (state
->dynamic
.depth_bounds_test_enable
== depthBoundsTestEnable
)
4567 state
->dynamic
.depth_bounds_test_enable
= depthBoundsTestEnable
;
4569 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
4572 void radv_CmdSetStencilTestEnableEXT(
4573 VkCommandBuffer commandBuffer
,
4574 VkBool32 stencilTestEnable
)
4576 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4577 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4579 if (state
->dynamic
.stencil_test_enable
== stencilTestEnable
)
4582 state
->dynamic
.stencil_test_enable
= stencilTestEnable
;
4584 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
;
4587 void radv_CmdSetStencilOpEXT(
4588 VkCommandBuffer commandBuffer
,
4589 VkStencilFaceFlags faceMask
,
4592 VkStencilOp depthFailOp
,
4593 VkCompareOp compareOp
)
4595 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4596 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4598 state
->dynamic
.stencil_op
.front
.fail_op
== failOp
&&
4599 state
->dynamic
.stencil_op
.front
.pass_op
== passOp
&&
4600 state
->dynamic
.stencil_op
.front
.depth_fail_op
== depthFailOp
&&
4601 state
->dynamic
.stencil_op
.front
.compare_op
== compareOp
;
4603 state
->dynamic
.stencil_op
.back
.fail_op
== failOp
&&
4604 state
->dynamic
.stencil_op
.back
.pass_op
== passOp
&&
4605 state
->dynamic
.stencil_op
.back
.depth_fail_op
== depthFailOp
&&
4606 state
->dynamic
.stencil_op
.back
.compare_op
== compareOp
;
4608 if ((!(faceMask
& VK_STENCIL_FACE_FRONT_BIT
) || front_same
) &&
4609 (!(faceMask
& VK_STENCIL_FACE_BACK_BIT
) || back_same
))
4612 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
) {
4613 state
->dynamic
.stencil_op
.front
.fail_op
= failOp
;
4614 state
->dynamic
.stencil_op
.front
.pass_op
= passOp
;
4615 state
->dynamic
.stencil_op
.front
.depth_fail_op
= depthFailOp
;
4616 state
->dynamic
.stencil_op
.front
.compare_op
= compareOp
;
4619 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
) {
4620 state
->dynamic
.stencil_op
.back
.fail_op
= failOp
;
4621 state
->dynamic
.stencil_op
.back
.pass_op
= passOp
;
4622 state
->dynamic
.stencil_op
.back
.depth_fail_op
= depthFailOp
;
4623 state
->dynamic
.stencil_op
.back
.compare_op
= compareOp
;
4626 state
->dirty
|= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP
;
4629 void radv_CmdExecuteCommands(
4630 VkCommandBuffer commandBuffer
,
4631 uint32_t commandBufferCount
,
4632 const VkCommandBuffer
* pCmdBuffers
)
4634 RADV_FROM_HANDLE(radv_cmd_buffer
, primary
, commandBuffer
);
4636 assert(commandBufferCount
> 0);
4638 /* Emit pending flushes on primary prior to executing secondary */
4639 si_emit_cache_flush(primary
);
4641 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
4642 RADV_FROM_HANDLE(radv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
4644 primary
->scratch_size_per_wave_needed
= MAX2(primary
->scratch_size_per_wave_needed
,
4645 secondary
->scratch_size_per_wave_needed
);
4646 primary
->scratch_waves_wanted
= MAX2(primary
->scratch_waves_wanted
,
4647 secondary
->scratch_waves_wanted
);
4648 primary
->compute_scratch_size_per_wave_needed
= MAX2(primary
->compute_scratch_size_per_wave_needed
,
4649 secondary
->compute_scratch_size_per_wave_needed
);
4650 primary
->compute_scratch_waves_wanted
= MAX2(primary
->compute_scratch_waves_wanted
,
4651 secondary
->compute_scratch_waves_wanted
);
4653 if (secondary
->esgs_ring_size_needed
> primary
->esgs_ring_size_needed
)
4654 primary
->esgs_ring_size_needed
= secondary
->esgs_ring_size_needed
;
4655 if (secondary
->gsvs_ring_size_needed
> primary
->gsvs_ring_size_needed
)
4656 primary
->gsvs_ring_size_needed
= secondary
->gsvs_ring_size_needed
;
4657 if (secondary
->tess_rings_needed
)
4658 primary
->tess_rings_needed
= true;
4659 if (secondary
->sample_positions_needed
)
4660 primary
->sample_positions_needed
= true;
4661 if (secondary
->gds_needed
)
4662 primary
->gds_needed
= true;
4664 if (!secondary
->state
.framebuffer
&&
4665 (primary
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)) {
4666 /* Emit the framebuffer state from primary if secondary
4667 * has been recorded without a framebuffer, otherwise
4668 * fast color/depth clears can't work.
4670 radv_emit_framebuffer_state(primary
);
4673 primary
->device
->ws
->cs_execute_secondary(primary
->cs
, secondary
->cs
);
4676 /* When the secondary command buffer is compute only we don't
4677 * need to re-emit the current graphics pipeline.
4679 if (secondary
->state
.emitted_pipeline
) {
4680 primary
->state
.emitted_pipeline
=
4681 secondary
->state
.emitted_pipeline
;
4684 /* When the secondary command buffer is graphics only we don't
4685 * need to re-emit the current compute pipeline.
4687 if (secondary
->state
.emitted_compute_pipeline
) {
4688 primary
->state
.emitted_compute_pipeline
=
4689 secondary
->state
.emitted_compute_pipeline
;
4692 /* Only re-emit the draw packets when needed. */
4693 if (secondary
->state
.last_primitive_reset_en
!= -1) {
4694 primary
->state
.last_primitive_reset_en
=
4695 secondary
->state
.last_primitive_reset_en
;
4698 if (secondary
->state
.last_primitive_reset_index
) {
4699 primary
->state
.last_primitive_reset_index
=
4700 secondary
->state
.last_primitive_reset_index
;
4703 if (secondary
->state
.last_ia_multi_vgt_param
) {
4704 primary
->state
.last_ia_multi_vgt_param
=
4705 secondary
->state
.last_ia_multi_vgt_param
;
4708 primary
->state
.last_first_instance
= secondary
->state
.last_first_instance
;
4709 primary
->state
.last_num_instances
= secondary
->state
.last_num_instances
;
4710 primary
->state
.last_vertex_offset
= secondary
->state
.last_vertex_offset
;
4711 primary
->state
.last_sx_ps_downconvert
= secondary
->state
.last_sx_ps_downconvert
;
4712 primary
->state
.last_sx_blend_opt_epsilon
= secondary
->state
.last_sx_blend_opt_epsilon
;
4713 primary
->state
.last_sx_blend_opt_control
= secondary
->state
.last_sx_blend_opt_control
;
4715 if (secondary
->state
.last_index_type
!= -1) {
4716 primary
->state
.last_index_type
=
4717 secondary
->state
.last_index_type
;
4721 /* After executing commands from secondary buffers we have to dirty
4724 primary
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
|
4725 RADV_CMD_DIRTY_INDEX_BUFFER
|
4726 RADV_CMD_DIRTY_DYNAMIC_ALL
;
4727 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_GRAPHICS
);
4728 radv_mark_descriptor_sets_dirty(primary
, VK_PIPELINE_BIND_POINT_COMPUTE
);
4731 VkResult
radv_CreateCommandPool(
4733 const VkCommandPoolCreateInfo
* pCreateInfo
,
4734 const VkAllocationCallbacks
* pAllocator
,
4735 VkCommandPool
* pCmdPool
)
4737 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4738 struct radv_cmd_pool
*pool
;
4740 pool
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pool
), 8,
4741 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4743 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4745 vk_object_base_init(&device
->vk
, &pool
->base
,
4746 VK_OBJECT_TYPE_COMMAND_POOL
);
4749 pool
->alloc
= *pAllocator
;
4751 pool
->alloc
= device
->vk
.alloc
;
4753 list_inithead(&pool
->cmd_buffers
);
4754 list_inithead(&pool
->free_cmd_buffers
);
4756 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
4758 *pCmdPool
= radv_cmd_pool_to_handle(pool
);
4764 void radv_DestroyCommandPool(
4766 VkCommandPool commandPool
,
4767 const VkAllocationCallbacks
* pAllocator
)
4769 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4770 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4775 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4776 &pool
->cmd_buffers
, pool_link
) {
4777 radv_destroy_cmd_buffer(cmd_buffer
);
4780 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4781 &pool
->free_cmd_buffers
, pool_link
) {
4782 radv_destroy_cmd_buffer(cmd_buffer
);
4785 vk_object_base_finish(&pool
->base
);
4786 vk_free2(&device
->vk
.alloc
, pAllocator
, pool
);
4789 VkResult
radv_ResetCommandPool(
4791 VkCommandPool commandPool
,
4792 VkCommandPoolResetFlags flags
)
4794 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4797 list_for_each_entry(struct radv_cmd_buffer
, cmd_buffer
,
4798 &pool
->cmd_buffers
, pool_link
) {
4799 result
= radv_reset_cmd_buffer(cmd_buffer
);
4800 if (result
!= VK_SUCCESS
)
4807 void radv_TrimCommandPool(
4809 VkCommandPool commandPool
,
4810 VkCommandPoolTrimFlags flags
)
4812 RADV_FROM_HANDLE(radv_cmd_pool
, pool
, commandPool
);
4817 list_for_each_entry_safe(struct radv_cmd_buffer
, cmd_buffer
,
4818 &pool
->free_cmd_buffers
, pool_link
) {
4819 radv_destroy_cmd_buffer(cmd_buffer
);
4824 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
*cmd_buffer
,
4825 uint32_t subpass_id
)
4827 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4828 struct radv_subpass
*subpass
= &state
->pass
->subpasses
[subpass_id
];
4830 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
,
4831 cmd_buffer
->cs
, 4096);
4833 radv_subpass_barrier(cmd_buffer
, &subpass
->start_barrier
);
4835 radv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
4837 radv_describe_barrier_start(cmd_buffer
, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
);
4839 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4840 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4841 if (a
== VK_ATTACHMENT_UNUSED
)
4844 radv_handle_subpass_image_transition(cmd_buffer
,
4845 subpass
->attachments
[i
],
4849 radv_describe_barrier_end(cmd_buffer
);
4851 radv_cmd_buffer_clear_subpass(cmd_buffer
);
4853 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
4857 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer
*cmd_buffer
)
4859 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
4860 const struct radv_subpass
*subpass
= state
->subpass
;
4861 uint32_t subpass_id
= radv_get_subpass_id(cmd_buffer
);
4863 radv_cmd_buffer_resolve_subpass(cmd_buffer
);
4865 radv_describe_barrier_start(cmd_buffer
, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
);
4867 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4868 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4869 if (a
== VK_ATTACHMENT_UNUSED
)
4872 if (state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4875 VkImageLayout layout
= state
->pass
->attachments
[a
].final_layout
;
4876 VkImageLayout stencil_layout
= state
->pass
->attachments
[a
].stencil_final_layout
;
4877 struct radv_subpass_attachment att
= { a
, layout
, stencil_layout
};
4878 radv_handle_subpass_image_transition(cmd_buffer
, att
, false);
4881 radv_describe_barrier_end(cmd_buffer
);
4885 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
4886 const VkRenderPassBeginInfo
*pRenderPassBegin
)
4888 RADV_FROM_HANDLE(radv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4889 RADV_FROM_HANDLE(radv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4892 cmd_buffer
->state
.framebuffer
= framebuffer
;
4893 cmd_buffer
->state
.pass
= pass
;
4894 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4896 result
= radv_cmd_state_setup_attachments(cmd_buffer
, pass
, pRenderPassBegin
);
4897 if (result
!= VK_SUCCESS
)
4900 result
= radv_cmd_state_setup_sample_locations(cmd_buffer
, pass
, pRenderPassBegin
);
4901 if (result
!= VK_SUCCESS
)
4905 void radv_CmdBeginRenderPass(
4906 VkCommandBuffer commandBuffer
,
4907 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4908 VkSubpassContents contents
)
4910 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4912 radv_cmd_buffer_begin_render_pass(cmd_buffer
, pRenderPassBegin
);
4914 radv_cmd_buffer_begin_subpass(cmd_buffer
, 0);
4917 void radv_CmdBeginRenderPass2(
4918 VkCommandBuffer commandBuffer
,
4919 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4920 const VkSubpassBeginInfo
* pSubpassBeginInfo
)
4922 radv_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
4923 pSubpassBeginInfo
->contents
);
4926 void radv_CmdNextSubpass(
4927 VkCommandBuffer commandBuffer
,
4928 VkSubpassContents contents
)
4930 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4932 uint32_t prev_subpass
= radv_get_subpass_id(cmd_buffer
);
4933 radv_cmd_buffer_end_subpass(cmd_buffer
);
4934 radv_cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4937 void radv_CmdNextSubpass2(
4938 VkCommandBuffer commandBuffer
,
4939 const VkSubpassBeginInfo
* pSubpassBeginInfo
,
4940 const VkSubpassEndInfo
* pSubpassEndInfo
)
4942 radv_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
4945 static void radv_emit_view_index(struct radv_cmd_buffer
*cmd_buffer
, unsigned index
)
4947 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
4948 for (unsigned stage
= 0; stage
< MESA_SHADER_STAGES
; ++stage
) {
4949 if (!radv_get_shader(pipeline
, stage
))
4952 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, stage
, AC_UD_VIEW_INDEX
);
4953 if (loc
->sgpr_idx
== -1)
4955 uint32_t base_reg
= pipeline
->user_data_0
[stage
];
4956 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4959 if (radv_pipeline_has_gs_copy_shader(pipeline
)) {
4960 struct radv_userdata_info
*loc
= &pipeline
->gs_copy_shader
->info
.user_sgprs_locs
.shader_data
[AC_UD_VIEW_INDEX
];
4961 if (loc
->sgpr_idx
!= -1) {
4962 uint32_t base_reg
= R_00B130_SPI_SHADER_USER_DATA_VS_0
;
4963 radeon_set_sh_reg(cmd_buffer
->cs
, base_reg
+ loc
->sgpr_idx
* 4, index
);
4969 radv_cs_emit_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4970 uint32_t vertex_count
,
4973 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, cmd_buffer
->state
.predicating
));
4974 radeon_emit(cmd_buffer
->cs
, vertex_count
);
4975 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
4976 S_0287F0_USE_OPAQUE(use_opaque
));
4980 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer
*cmd_buffer
,
4982 uint32_t index_count
)
4984 radeon_emit(cmd_buffer
->cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, cmd_buffer
->state
.predicating
));
4985 radeon_emit(cmd_buffer
->cs
, cmd_buffer
->state
.max_index_count
);
4986 radeon_emit(cmd_buffer
->cs
, index_va
);
4987 radeon_emit(cmd_buffer
->cs
, index_va
>> 32);
4988 radeon_emit(cmd_buffer
->cs
, index_count
);
4989 radeon_emit(cmd_buffer
->cs
, V_0287F0_DI_SRC_SEL_DMA
);
4993 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer
*cmd_buffer
,
4995 uint32_t draw_count
,
4999 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5000 unsigned di_src_sel
= indexed
? V_0287F0_DI_SRC_SEL_DMA
5001 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
5002 bool draw_id_enable
= radv_get_shader(cmd_buffer
->state
.pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
;
5003 uint32_t base_reg
= cmd_buffer
->state
.pipeline
->graphics
.vtx_base_sgpr
;
5004 bool predicating
= cmd_buffer
->state
.predicating
;
5007 /* just reset draw state for vertex data */
5008 cmd_buffer
->state
.last_first_instance
= -1;
5009 cmd_buffer
->state
.last_num_instances
= -1;
5010 cmd_buffer
->state
.last_vertex_offset
= -1;
5012 if (draw_count
== 1 && !count_va
&& !draw_id_enable
) {
5013 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT
:
5014 PKT3_DRAW_INDIRECT
, 3, predicating
));
5016 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
5017 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
5018 radeon_emit(cs
, di_src_sel
);
5020 radeon_emit(cs
, PKT3(indexed
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
5021 PKT3_DRAW_INDIRECT_MULTI
,
5024 radeon_emit(cs
, (base_reg
- SI_SH_REG_OFFSET
) >> 2);
5025 radeon_emit(cs
, ((base_reg
+ 4) - SI_SH_REG_OFFSET
) >> 2);
5026 radeon_emit(cs
, (((base_reg
+ 8) - SI_SH_REG_OFFSET
) >> 2) |
5027 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable
) |
5028 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va
));
5029 radeon_emit(cs
, draw_count
); /* count */
5030 radeon_emit(cs
, count_va
); /* count_addr */
5031 radeon_emit(cs
, count_va
>> 32);
5032 radeon_emit(cs
, stride
); /* stride */
5033 radeon_emit(cs
, di_src_sel
);
5038 radv_emit_draw_packets(struct radv_cmd_buffer
*cmd_buffer
,
5039 const struct radv_draw_info
*info
)
5041 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5042 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
5043 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5045 if (info
->indirect
) {
5046 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
5047 uint64_t count_va
= 0;
5049 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
5051 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
5053 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
5055 radeon_emit(cs
, va
);
5056 radeon_emit(cs
, va
>> 32);
5058 if (info
->count_buffer
) {
5059 count_va
= radv_buffer_get_va(info
->count_buffer
->bo
);
5060 count_va
+= info
->count_buffer
->offset
+
5061 info
->count_buffer_offset
;
5063 radv_cs_add_buffer(ws
, cs
, info
->count_buffer
->bo
);
5066 if (!state
->subpass
->view_mask
) {
5067 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
5074 for_each_bit(i
, state
->subpass
->view_mask
) {
5075 radv_emit_view_index(cmd_buffer
, i
);
5077 radv_cs_emit_indirect_draw_packet(cmd_buffer
,
5085 assert(state
->pipeline
->graphics
.vtx_base_sgpr
);
5087 if (info
->vertex_offset
!= state
->last_vertex_offset
||
5088 info
->first_instance
!= state
->last_first_instance
) {
5089 radeon_set_sh_reg_seq(cs
, state
->pipeline
->graphics
.vtx_base_sgpr
,
5090 state
->pipeline
->graphics
.vtx_emit_num
);
5092 radeon_emit(cs
, info
->vertex_offset
);
5093 radeon_emit(cs
, info
->first_instance
);
5094 if (state
->pipeline
->graphics
.vtx_emit_num
== 3)
5096 state
->last_first_instance
= info
->first_instance
;
5097 state
->last_vertex_offset
= info
->vertex_offset
;
5100 if (state
->last_num_instances
!= info
->instance_count
) {
5101 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, false));
5102 radeon_emit(cs
, info
->instance_count
);
5103 state
->last_num_instances
= info
->instance_count
;
5106 if (info
->indexed
) {
5107 int index_size
= radv_get_vgt_index_size(state
->index_type
);
5110 /* Skip draw calls with 0-sized index buffers. They
5111 * cause a hang on some chips, like Navi10-14.
5113 if (!cmd_buffer
->state
.max_index_count
)
5116 index_va
= state
->index_va
;
5117 index_va
+= info
->first_index
* index_size
;
5119 if (!state
->subpass
->view_mask
) {
5120 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
5125 for_each_bit(i
, state
->subpass
->view_mask
) {
5126 radv_emit_view_index(cmd_buffer
, i
);
5128 radv_cs_emit_draw_indexed_packet(cmd_buffer
,
5134 if (!state
->subpass
->view_mask
) {
5135 radv_cs_emit_draw_packet(cmd_buffer
,
5137 !!info
->strmout_buffer
);
5140 for_each_bit(i
, state
->subpass
->view_mask
) {
5141 radv_emit_view_index(cmd_buffer
, i
);
5143 radv_cs_emit_draw_packet(cmd_buffer
,
5145 !!info
->strmout_buffer
);
5153 * Vega and raven have a bug which triggers if there are multiple context
5154 * register contexts active at the same time with different scissor values.
5156 * There are two possible workarounds:
5157 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
5158 * there is only ever 1 active set of scissor values at the same time.
5160 * 2) Whenever the hardware switches contexts we have to set the scissor
5161 * registers again even if it is a noop. That way the new context gets
5162 * the correct scissor values.
5164 * This implements option 2. radv_need_late_scissor_emission needs to
5165 * return true on affected HW if radv_emit_all_graphics_states sets
5166 * any context registers.
5168 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer
*cmd_buffer
,
5169 const struct radv_draw_info
*info
)
5171 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5173 if (!cmd_buffer
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
)
5176 if (cmd_buffer
->state
.context_roll_without_scissor_emitted
|| info
->strmout_buffer
)
5179 uint32_t used_states
= cmd_buffer
->state
.pipeline
->graphics
.needed_dynamic_state
| ~RADV_CMD_DIRTY_DYNAMIC_ALL
;
5181 /* Index, vertex and streamout buffers don't change context regs, and
5182 * pipeline is already handled.
5184 used_states
&= ~(RADV_CMD_DIRTY_INDEX_BUFFER
|
5185 RADV_CMD_DIRTY_VERTEX_BUFFER
|
5186 RADV_CMD_DIRTY_STREAMOUT_BUFFER
|
5187 RADV_CMD_DIRTY_PIPELINE
);
5189 if (cmd_buffer
->state
.dirty
& used_states
)
5192 uint32_t primitive_reset_index
=
5193 radv_get_primitive_reset_index(cmd_buffer
);
5195 if (info
->indexed
&& state
->pipeline
->graphics
.prim_restart_enable
&&
5196 primitive_reset_index
!= state
->last_primitive_reset_index
)
5203 radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer
,
5204 const struct radv_draw_info
*info
)
5206 bool late_scissor_emission
;
5208 if ((cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
) ||
5209 cmd_buffer
->state
.emitted_pipeline
!= cmd_buffer
->state
.pipeline
)
5210 radv_emit_rbplus_state(cmd_buffer
);
5212 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
)
5213 radv_emit_graphics_pipeline(cmd_buffer
);
5215 /* This should be before the cmd_buffer->state.dirty is cleared
5216 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
5217 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
5218 late_scissor_emission
=
5219 radv_need_late_scissor_emission(cmd_buffer
, info
);
5221 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_FRAMEBUFFER
)
5222 radv_emit_framebuffer_state(cmd_buffer
);
5224 if (info
->indexed
) {
5225 if (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_INDEX_BUFFER
)
5226 radv_emit_index_buffer(cmd_buffer
, info
->indirect
);
5228 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
5229 * so the state must be re-emitted before the next indexed
5232 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5233 cmd_buffer
->state
.last_index_type
= -1;
5234 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_INDEX_BUFFER
;
5238 radv_cmd_buffer_flush_dynamic_state(cmd_buffer
);
5240 radv_emit_draw_registers(cmd_buffer
, info
);
5242 if (late_scissor_emission
)
5243 radv_emit_scissor(cmd_buffer
);
5247 radv_draw(struct radv_cmd_buffer
*cmd_buffer
,
5248 const struct radv_draw_info
*info
)
5250 struct radeon_info
*rad_info
=
5251 &cmd_buffer
->device
->physical_device
->rad_info
;
5253 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
5254 bool pipeline_is_dirty
=
5255 (cmd_buffer
->state
.dirty
& RADV_CMD_DIRTY_PIPELINE
) &&
5256 cmd_buffer
->state
.pipeline
!= cmd_buffer
->state
.emitted_pipeline
;
5258 ASSERTED
unsigned cdw_max
=
5259 radeon_check_space(cmd_buffer
->device
->ws
,
5260 cmd_buffer
->cs
, 4096);
5262 if (likely(!info
->indirect
)) {
5263 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
5264 * no workaround for indirect draws, but we can at least skip
5267 if (unlikely(!info
->instance_count
))
5270 /* Handle count == 0. */
5271 if (unlikely(!info
->count
&& !info
->strmout_buffer
))
5275 radv_describe_draw(cmd_buffer
);
5277 /* Use optimal packet order based on whether we need to sync the
5280 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5281 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5282 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
5283 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
5284 /* If we have to wait for idle, set all states first, so that
5285 * all SET packets are processed in parallel with previous draw
5286 * calls. Then upload descriptors, set shader pointers, and
5287 * draw, and prefetch at the end. This ensures that the time
5288 * the CUs are idle is very short. (there are only SET_SH
5289 * packets between the wait and the draw)
5291 radv_emit_all_graphics_states(cmd_buffer
, info
);
5292 si_emit_cache_flush(cmd_buffer
);
5293 /* <-- CUs are idle here --> */
5295 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
5297 radv_emit_draw_packets(cmd_buffer
, info
);
5298 /* <-- CUs are busy here --> */
5300 /* Start prefetches after the draw has been started. Both will
5301 * run in parallel, but starting the draw first is more
5304 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
5305 radv_emit_prefetch_L2(cmd_buffer
,
5306 cmd_buffer
->state
.pipeline
, false);
5309 /* If we don't wait for idle, start prefetches first, then set
5310 * states, and draw at the end.
5312 si_emit_cache_flush(cmd_buffer
);
5314 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
5315 /* Only prefetch the vertex shader and VBO descriptors
5316 * in order to start the draw as soon as possible.
5318 radv_emit_prefetch_L2(cmd_buffer
,
5319 cmd_buffer
->state
.pipeline
, true);
5322 radv_upload_graphics_shader_descriptors(cmd_buffer
, pipeline_is_dirty
);
5324 radv_emit_all_graphics_states(cmd_buffer
, info
);
5325 radv_emit_draw_packets(cmd_buffer
, info
);
5327 /* Prefetch the remaining shaders after the draw has been
5330 if (has_prefetch
&& cmd_buffer
->state
.prefetch_L2_mask
) {
5331 radv_emit_prefetch_L2(cmd_buffer
,
5332 cmd_buffer
->state
.pipeline
, false);
5336 /* Workaround for a VGT hang when streamout is enabled.
5337 * It must be done after drawing.
5339 if (cmd_buffer
->state
.streamout
.streamout_enabled
&&
5340 (rad_info
->family
== CHIP_HAWAII
||
5341 rad_info
->family
== CHIP_TONGA
||
5342 rad_info
->family
== CHIP_FIJI
)) {
5343 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
;
5346 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5347 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_PS_PARTIAL_FLUSH
);
5351 VkCommandBuffer commandBuffer
,
5352 uint32_t vertexCount
,
5353 uint32_t instanceCount
,
5354 uint32_t firstVertex
,
5355 uint32_t firstInstance
)
5357 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5358 struct radv_draw_info info
= {};
5360 info
.count
= vertexCount
;
5361 info
.instance_count
= instanceCount
;
5362 info
.first_instance
= firstInstance
;
5363 info
.vertex_offset
= firstVertex
;
5365 radv_draw(cmd_buffer
, &info
);
5368 void radv_CmdDrawIndexed(
5369 VkCommandBuffer commandBuffer
,
5370 uint32_t indexCount
,
5371 uint32_t instanceCount
,
5372 uint32_t firstIndex
,
5373 int32_t vertexOffset
,
5374 uint32_t firstInstance
)
5376 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5377 struct radv_draw_info info
= {};
5379 info
.indexed
= true;
5380 info
.count
= indexCount
;
5381 info
.instance_count
= instanceCount
;
5382 info
.first_index
= firstIndex
;
5383 info
.vertex_offset
= vertexOffset
;
5384 info
.first_instance
= firstInstance
;
5386 radv_draw(cmd_buffer
, &info
);
5389 void radv_CmdDrawIndirect(
5390 VkCommandBuffer commandBuffer
,
5392 VkDeviceSize offset
,
5396 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5397 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5398 struct radv_draw_info info
= {};
5400 info
.count
= drawCount
;
5401 info
.indirect
= buffer
;
5402 info
.indirect_offset
= offset
;
5403 info
.stride
= stride
;
5405 radv_draw(cmd_buffer
, &info
);
5408 void radv_CmdDrawIndexedIndirect(
5409 VkCommandBuffer commandBuffer
,
5411 VkDeviceSize offset
,
5415 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5416 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5417 struct radv_draw_info info
= {};
5419 info
.indexed
= true;
5420 info
.count
= drawCount
;
5421 info
.indirect
= buffer
;
5422 info
.indirect_offset
= offset
;
5423 info
.stride
= stride
;
5425 radv_draw(cmd_buffer
, &info
);
5428 void radv_CmdDrawIndirectCount(
5429 VkCommandBuffer commandBuffer
,
5431 VkDeviceSize offset
,
5432 VkBuffer _countBuffer
,
5433 VkDeviceSize countBufferOffset
,
5434 uint32_t maxDrawCount
,
5437 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5438 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5439 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
5440 struct radv_draw_info info
= {};
5442 info
.count
= maxDrawCount
;
5443 info
.indirect
= buffer
;
5444 info
.indirect_offset
= offset
;
5445 info
.count_buffer
= count_buffer
;
5446 info
.count_buffer_offset
= countBufferOffset
;
5447 info
.stride
= stride
;
5449 radv_draw(cmd_buffer
, &info
);
5452 void radv_CmdDrawIndexedIndirectCount(
5453 VkCommandBuffer commandBuffer
,
5455 VkDeviceSize offset
,
5456 VkBuffer _countBuffer
,
5457 VkDeviceSize countBufferOffset
,
5458 uint32_t maxDrawCount
,
5461 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5462 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5463 RADV_FROM_HANDLE(radv_buffer
, count_buffer
, _countBuffer
);
5464 struct radv_draw_info info
= {};
5466 info
.indexed
= true;
5467 info
.count
= maxDrawCount
;
5468 info
.indirect
= buffer
;
5469 info
.indirect_offset
= offset
;
5470 info
.count_buffer
= count_buffer
;
5471 info
.count_buffer_offset
= countBufferOffset
;
5472 info
.stride
= stride
;
5474 radv_draw(cmd_buffer
, &info
);
5477 struct radv_dispatch_info
{
5479 * Determine the layout of the grid (in block units) to be used.
5484 * A starting offset for the grid. If unaligned is set, the offset
5485 * must still be aligned.
5487 uint32_t offsets
[3];
5489 * Whether it's an unaligned compute dispatch.
5494 * Indirect compute parameters resource.
5496 struct radv_buffer
*indirect
;
5497 uint64_t indirect_offset
;
5501 radv_emit_dispatch_packets(struct radv_cmd_buffer
*cmd_buffer
,
5502 const struct radv_dispatch_info
*info
)
5504 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5505 struct radv_shader_variant
*compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5506 unsigned dispatch_initiator
= cmd_buffer
->device
->dispatch_initiator
;
5507 struct radeon_winsys
*ws
= cmd_buffer
->device
->ws
;
5508 bool predicating
= cmd_buffer
->state
.predicating
;
5509 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
5510 struct radv_userdata_info
*loc
;
5512 loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_COMPUTE
,
5513 AC_UD_CS_GRID_SIZE
);
5515 ASSERTED
unsigned cdw_max
= radeon_check_space(ws
, cs
, 25);
5517 if (compute_shader
->info
.wave_size
== 32) {
5518 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
5519 dispatch_initiator
|= S_00B800_CS_W32_EN(1);
5522 if (info
->indirect
) {
5523 uint64_t va
= radv_buffer_get_va(info
->indirect
->bo
);
5525 va
+= info
->indirect
->offset
+ info
->indirect_offset
;
5527 radv_cs_add_buffer(ws
, cs
, info
->indirect
->bo
);
5529 if (loc
->sgpr_idx
!= -1) {
5530 for (unsigned i
= 0; i
< 3; ++i
) {
5531 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
5532 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
5533 COPY_DATA_DST_SEL(COPY_DATA_REG
));
5534 radeon_emit(cs
, (va
+ 4 * i
));
5535 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
5536 radeon_emit(cs
, ((R_00B900_COMPUTE_USER_DATA_0
5537 + loc
->sgpr_idx
* 4) >> 2) + i
);
5542 if (radv_cmd_buffer_uses_mec(cmd_buffer
)) {
5543 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 2, predicating
) |
5544 PKT3_SHADER_TYPE_S(1));
5545 radeon_emit(cs
, va
);
5546 radeon_emit(cs
, va
>> 32);
5547 radeon_emit(cs
, dispatch_initiator
);
5549 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
5550 PKT3_SHADER_TYPE_S(1));
5552 radeon_emit(cs
, va
);
5553 radeon_emit(cs
, va
>> 32);
5555 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, predicating
) |
5556 PKT3_SHADER_TYPE_S(1));
5558 radeon_emit(cs
, dispatch_initiator
);
5561 unsigned blocks
[3] = { info
->blocks
[0], info
->blocks
[1], info
->blocks
[2] };
5562 unsigned offsets
[3] = { info
->offsets
[0], info
->offsets
[1], info
->offsets
[2] };
5564 if (info
->unaligned
) {
5565 unsigned *cs_block_size
= compute_shader
->info
.cs
.block_size
;
5566 unsigned remainder
[3];
5568 /* If aligned, these should be an entire block size,
5571 remainder
[0] = blocks
[0] + cs_block_size
[0] -
5572 align_u32_npot(blocks
[0], cs_block_size
[0]);
5573 remainder
[1] = blocks
[1] + cs_block_size
[1] -
5574 align_u32_npot(blocks
[1], cs_block_size
[1]);
5575 remainder
[2] = blocks
[2] + cs_block_size
[2] -
5576 align_u32_npot(blocks
[2], cs_block_size
[2]);
5578 blocks
[0] = round_up_u32(blocks
[0], cs_block_size
[0]);
5579 blocks
[1] = round_up_u32(blocks
[1], cs_block_size
[1]);
5580 blocks
[2] = round_up_u32(blocks
[2], cs_block_size
[2]);
5582 for(unsigned i
= 0; i
< 3; ++i
) {
5583 assert(offsets
[i
] % cs_block_size
[i
] == 0);
5584 offsets
[i
] /= cs_block_size
[i
];
5587 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5589 S_00B81C_NUM_THREAD_FULL(cs_block_size
[0]) |
5590 S_00B81C_NUM_THREAD_PARTIAL(remainder
[0]));
5592 S_00B81C_NUM_THREAD_FULL(cs_block_size
[1]) |
5593 S_00B81C_NUM_THREAD_PARTIAL(remainder
[1]));
5595 S_00B81C_NUM_THREAD_FULL(cs_block_size
[2]) |
5596 S_00B81C_NUM_THREAD_PARTIAL(remainder
[2]));
5598 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
5601 if (loc
->sgpr_idx
!= -1) {
5602 assert(loc
->num_sgprs
== 3);
5604 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
5605 loc
->sgpr_idx
* 4, 3);
5606 radeon_emit(cs
, blocks
[0]);
5607 radeon_emit(cs
, blocks
[1]);
5608 radeon_emit(cs
, blocks
[2]);
5611 if (offsets
[0] || offsets
[1] || offsets
[2]) {
5612 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
5613 radeon_emit(cs
, offsets
[0]);
5614 radeon_emit(cs
, offsets
[1]);
5615 radeon_emit(cs
, offsets
[2]);
5617 /* The blocks in the packet are not counts but end values. */
5618 for (unsigned i
= 0; i
< 3; ++i
)
5619 blocks
[i
] += offsets
[i
];
5621 dispatch_initiator
|= S_00B800_FORCE_START_AT_000(1);
5624 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, predicating
) |
5625 PKT3_SHADER_TYPE_S(1));
5626 radeon_emit(cs
, blocks
[0]);
5627 radeon_emit(cs
, blocks
[1]);
5628 radeon_emit(cs
, blocks
[2]);
5629 radeon_emit(cs
, dispatch_initiator
);
5632 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
5636 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer
*cmd_buffer
)
5638 radv_flush_descriptors(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5639 radv_flush_constants(cmd_buffer
, VK_SHADER_STAGE_COMPUTE_BIT
);
5643 radv_dispatch(struct radv_cmd_buffer
*cmd_buffer
,
5644 const struct radv_dispatch_info
*info
)
5646 struct radv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
5648 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
5649 bool pipeline_is_dirty
= pipeline
&&
5650 pipeline
!= cmd_buffer
->state
.emitted_compute_pipeline
;
5652 radv_describe_dispatch(cmd_buffer
, 8, 8, 8);
5654 if (cmd_buffer
->state
.flush_bits
& (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5655 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5656 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
5657 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
)) {
5658 /* If we have to wait for idle, set all states first, so that
5659 * all SET packets are processed in parallel with previous draw
5660 * calls. Then upload descriptors, set shader pointers, and
5661 * dispatch, and prefetch at the end. This ensures that the
5662 * time the CUs are idle is very short. (there are only SET_SH
5663 * packets between the wait and the draw)
5665 radv_emit_compute_pipeline(cmd_buffer
);
5666 si_emit_cache_flush(cmd_buffer
);
5667 /* <-- CUs are idle here --> */
5669 radv_upload_compute_shader_descriptors(cmd_buffer
);
5671 radv_emit_dispatch_packets(cmd_buffer
, info
);
5672 /* <-- CUs are busy here --> */
5674 /* Start prefetches after the dispatch has been started. Both
5675 * will run in parallel, but starting the dispatch first is
5678 if (has_prefetch
&& pipeline_is_dirty
) {
5679 radv_emit_shader_prefetch(cmd_buffer
,
5680 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5683 /* If we don't wait for idle, start prefetches first, then set
5684 * states, and dispatch at the end.
5686 si_emit_cache_flush(cmd_buffer
);
5688 if (has_prefetch
&& pipeline_is_dirty
) {
5689 radv_emit_shader_prefetch(cmd_buffer
,
5690 pipeline
->shaders
[MESA_SHADER_COMPUTE
]);
5693 radv_upload_compute_shader_descriptors(cmd_buffer
);
5695 radv_emit_compute_pipeline(cmd_buffer
);
5696 radv_emit_dispatch_packets(cmd_buffer
, info
);
5699 radv_cmd_buffer_after_draw(cmd_buffer
, RADV_CMD_FLAG_CS_PARTIAL_FLUSH
);
5702 void radv_CmdDispatchBase(
5703 VkCommandBuffer commandBuffer
,
5711 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5712 struct radv_dispatch_info info
= {};
5718 info
.offsets
[0] = base_x
;
5719 info
.offsets
[1] = base_y
;
5720 info
.offsets
[2] = base_z
;
5721 radv_dispatch(cmd_buffer
, &info
);
5724 void radv_CmdDispatch(
5725 VkCommandBuffer commandBuffer
,
5730 radv_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
5733 void radv_CmdDispatchIndirect(
5734 VkCommandBuffer commandBuffer
,
5736 VkDeviceSize offset
)
5738 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5739 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5740 struct radv_dispatch_info info
= {};
5742 info
.indirect
= buffer
;
5743 info
.indirect_offset
= offset
;
5745 radv_dispatch(cmd_buffer
, &info
);
5748 void radv_unaligned_dispatch(
5749 struct radv_cmd_buffer
*cmd_buffer
,
5754 struct radv_dispatch_info info
= {};
5761 radv_dispatch(cmd_buffer
, &info
);
5765 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
)
5767 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
5768 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.subpass_sample_locs
);
5770 cmd_buffer
->state
.pass
= NULL
;
5771 cmd_buffer
->state
.subpass
= NULL
;
5772 cmd_buffer
->state
.attachments
= NULL
;
5773 cmd_buffer
->state
.framebuffer
= NULL
;
5774 cmd_buffer
->state
.subpass_sample_locs
= NULL
;
5777 void radv_CmdEndRenderPass(
5778 VkCommandBuffer commandBuffer
)
5780 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5782 radv_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
);
5784 radv_cmd_buffer_end_subpass(cmd_buffer
);
5786 radv_cmd_buffer_end_render_pass(cmd_buffer
);
5789 void radv_CmdEndRenderPass2(
5790 VkCommandBuffer commandBuffer
,
5791 const VkSubpassEndInfo
* pSubpassEndInfo
)
5793 radv_CmdEndRenderPass(commandBuffer
);
5797 * For HTILE we have the following interesting clear words:
5798 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
5799 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
5800 * 0xfffffff0: Clear depth to 1.0
5801 * 0x00000000: Clear depth to 0.0
5803 static void radv_initialize_htile(struct radv_cmd_buffer
*cmd_buffer
,
5804 struct radv_image
*image
,
5805 const VkImageSubresourceRange
*range
)
5807 assert(range
->baseMipLevel
== 0);
5808 assert(range
->levelCount
== 1 || range
->levelCount
== VK_REMAINING_ARRAY_LAYERS
);
5809 VkImageAspectFlags aspects
= VK_IMAGE_ASPECT_DEPTH_BIT
;
5810 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5811 uint32_t htile_value
= vk_format_is_stencil(image
->vk_format
) ? 0xfffff30f : 0xfffc000f;
5812 VkClearDepthStencilValue value
= {};
5813 struct radv_barrier_data barrier
= {};
5815 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5816 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5818 barrier
.layout_transitions
.init_mask_ram
= 1;
5819 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5821 state
->flush_bits
|= radv_clear_htile(cmd_buffer
, image
, range
, htile_value
);
5823 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5825 if (vk_format_is_stencil(image
->vk_format
))
5826 aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
5828 radv_set_ds_clear_metadata(cmd_buffer
, image
, range
, value
, aspects
);
5830 if (radv_image_is_tc_compat_htile(image
)) {
5831 /* Initialize the TC-compat metada value to 0 because by
5832 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
5833 * need have to conditionally update its value when performing
5834 * a fast depth clear.
5836 radv_set_tc_compat_zrange_metadata(cmd_buffer
, image
, range
, 0);
5840 static void radv_handle_depth_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
5841 struct radv_image
*image
,
5842 VkImageLayout src_layout
,
5843 bool src_render_loop
,
5844 VkImageLayout dst_layout
,
5845 bool dst_render_loop
,
5846 unsigned src_queue_mask
,
5847 unsigned dst_queue_mask
,
5848 const VkImageSubresourceRange
*range
,
5849 struct radv_sample_locations_state
*sample_locs
)
5851 if (!radv_image_has_htile(image
))
5854 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
5855 radv_initialize_htile(cmd_buffer
, image
, range
);
5856 } else if (!radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5857 radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5858 radv_initialize_htile(cmd_buffer
, image
, range
);
5859 } else if (radv_layout_is_htile_compressed(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
5860 !radv_layout_is_htile_compressed(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
5861 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5862 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5864 radv_decompress_depth_stencil(cmd_buffer
, image
, range
,
5867 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
5868 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
;
5872 static void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
5873 struct radv_image
*image
,
5874 const VkImageSubresourceRange
*range
,
5877 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5878 struct radv_barrier_data barrier
= {};
5880 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5881 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5883 barrier
.layout_transitions
.init_mask_ram
= 1;
5884 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5886 state
->flush_bits
|= radv_clear_cmask(cmd_buffer
, image
, range
, value
);
5888 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5891 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
5892 struct radv_image
*image
,
5893 const VkImageSubresourceRange
*range
)
5895 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5896 static const uint32_t fmask_clear_values
[4] = {
5902 uint32_t log2_samples
= util_logbase2(image
->info
.samples
);
5903 uint32_t value
= fmask_clear_values
[log2_samples
];
5904 struct radv_barrier_data barrier
= {};
5906 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5907 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5909 barrier
.layout_transitions
.init_mask_ram
= 1;
5910 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5912 state
->flush_bits
|= radv_clear_fmask(cmd_buffer
, image
, range
, value
);
5914 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5917 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
5918 struct radv_image
*image
,
5919 const VkImageSubresourceRange
*range
, uint32_t value
)
5921 struct radv_cmd_state
*state
= &cmd_buffer
->state
;
5922 struct radv_barrier_data barrier
= {};
5925 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5926 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5928 barrier
.layout_transitions
.init_mask_ram
= 1;
5929 radv_describe_layout_transition(cmd_buffer
, &barrier
);
5931 state
->flush_bits
|= radv_clear_dcc(cmd_buffer
, image
, range
, value
);
5933 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
== GFX8
) {
5934 /* When DCC is enabled with mipmaps, some levels might not
5935 * support fast clears and we have to initialize them as "fully
5938 /* Compute the size of all fast clearable DCC levels. */
5939 for (unsigned i
= 0; i
< image
->planes
[0].surface
.num_dcc_levels
; i
++) {
5940 struct legacy_surf_level
*surf_level
=
5941 &image
->planes
[0].surface
.u
.legacy
.level
[i
];
5942 unsigned dcc_fast_clear_size
=
5943 surf_level
->dcc_slice_fast_clear_size
* image
->info
.array_size
;
5945 if (!dcc_fast_clear_size
)
5948 size
= surf_level
->dcc_offset
+ dcc_fast_clear_size
;
5951 /* Initialize the mipmap levels without DCC. */
5952 if (size
!= image
->planes
[0].surface
.dcc_size
) {
5953 state
->flush_bits
|=
5954 radv_fill_buffer(cmd_buffer
, image
->bo
,
5955 image
->offset
+ image
->planes
[0].surface
.dcc_offset
+ size
,
5956 image
->planes
[0].surface
.dcc_size
- size
,
5961 state
->flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
5962 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
;
5966 * Initialize DCC/FMASK/CMASK metadata for a color image.
5968 static void radv_init_color_image_metadata(struct radv_cmd_buffer
*cmd_buffer
,
5969 struct radv_image
*image
,
5970 VkImageLayout src_layout
,
5971 bool src_render_loop
,
5972 VkImageLayout dst_layout
,
5973 bool dst_render_loop
,
5974 unsigned src_queue_mask
,
5975 unsigned dst_queue_mask
,
5976 const VkImageSubresourceRange
*range
)
5978 if (radv_image_has_cmask(image
)) {
5979 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5981 /* TODO: clarify this. */
5982 if (radv_image_has_fmask(image
)) {
5983 value
= 0xccccccccu
;
5986 radv_initialise_cmask(cmd_buffer
, image
, range
, value
);
5989 if (radv_image_has_fmask(image
)) {
5990 radv_initialize_fmask(cmd_buffer
, image
, range
);
5993 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
5994 uint32_t value
= 0xffffffffu
; /* Fully expanded mode. */
5995 bool need_decompress_pass
= false;
5997 if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
,
6000 value
= 0x20202020u
;
6001 need_decompress_pass
= true;
6004 radv_initialize_dcc(cmd_buffer
, image
, range
, value
);
6006 radv_update_fce_metadata(cmd_buffer
, image
, range
,
6007 need_decompress_pass
);
6010 if (radv_image_has_cmask(image
) ||
6011 radv_dcc_enabled(image
, range
->baseMipLevel
)) {
6012 uint32_t color_values
[2] = {};
6013 radv_set_color_clear_metadata(cmd_buffer
, image
, range
,
6019 * Handle color image transitions for DCC/FMASK/CMASK.
6021 static void radv_handle_color_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
6022 struct radv_image
*image
,
6023 VkImageLayout src_layout
,
6024 bool src_render_loop
,
6025 VkImageLayout dst_layout
,
6026 bool dst_render_loop
,
6027 unsigned src_queue_mask
,
6028 unsigned dst_queue_mask
,
6029 const VkImageSubresourceRange
*range
)
6031 if (src_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
6032 radv_init_color_image_metadata(cmd_buffer
, image
,
6033 src_layout
, src_render_loop
,
6034 dst_layout
, dst_render_loop
,
6035 src_queue_mask
, dst_queue_mask
,
6040 if (radv_dcc_enabled(image
, range
->baseMipLevel
)) {
6041 if (src_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
6042 radv_initialize_dcc(cmd_buffer
, image
, range
, 0xffffffffu
);
6043 } else if (radv_layout_dcc_compressed(cmd_buffer
->device
, image
, src_layout
, src_render_loop
, src_queue_mask
) &&
6044 !radv_layout_dcc_compressed(cmd_buffer
->device
, image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
6045 radv_decompress_dcc(cmd_buffer
, image
, range
);
6046 } else if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
6047 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
6048 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
6050 } else if (radv_image_has_cmask(image
) || radv_image_has_fmask(image
)) {
6051 bool fce_eliminate
= false, fmask_expand
= false;
6053 if (radv_layout_can_fast_clear(image
, src_layout
, src_render_loop
, src_queue_mask
) &&
6054 !radv_layout_can_fast_clear(image
, dst_layout
, dst_render_loop
, dst_queue_mask
)) {
6055 fce_eliminate
= true;
6058 if (radv_image_has_fmask(image
)) {
6059 if (src_layout
!= VK_IMAGE_LAYOUT_GENERAL
&&
6060 dst_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
6061 /* A FMASK decompress is required before doing
6062 * a MSAA decompress using FMASK.
6064 fmask_expand
= true;
6068 if (fce_eliminate
|| fmask_expand
)
6069 radv_fast_clear_flush_image_inplace(cmd_buffer
, image
, range
);
6072 struct radv_barrier_data barrier
= {};
6073 barrier
.layout_transitions
.fmask_color_expand
= 1;
6074 radv_describe_layout_transition(cmd_buffer
, &barrier
);
6076 radv_expand_fmask_image_inplace(cmd_buffer
, image
, range
);
6081 static void radv_handle_image_transition(struct radv_cmd_buffer
*cmd_buffer
,
6082 struct radv_image
*image
,
6083 VkImageLayout src_layout
,
6084 bool src_render_loop
,
6085 VkImageLayout dst_layout
,
6086 bool dst_render_loop
,
6087 uint32_t src_family
,
6088 uint32_t dst_family
,
6089 const VkImageSubresourceRange
*range
,
6090 struct radv_sample_locations_state
*sample_locs
)
6092 if (image
->exclusive
&& src_family
!= dst_family
) {
6093 /* This is an acquire or a release operation and there will be
6094 * a corresponding release/acquire. Do the transition in the
6095 * most flexible queue. */
6097 assert(src_family
== cmd_buffer
->queue_family_index
||
6098 dst_family
== cmd_buffer
->queue_family_index
);
6100 if (src_family
== VK_QUEUE_FAMILY_EXTERNAL
||
6101 src_family
== VK_QUEUE_FAMILY_FOREIGN_EXT
)
6104 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_TRANSFER
)
6107 if (cmd_buffer
->queue_family_index
== RADV_QUEUE_COMPUTE
&&
6108 (src_family
== RADV_QUEUE_GENERAL
||
6109 dst_family
== RADV_QUEUE_GENERAL
))
6113 if (src_layout
== dst_layout
)
6116 unsigned src_queue_mask
=
6117 radv_image_queue_family_mask(image
, src_family
,
6118 cmd_buffer
->queue_family_index
);
6119 unsigned dst_queue_mask
=
6120 radv_image_queue_family_mask(image
, dst_family
,
6121 cmd_buffer
->queue_family_index
);
6123 if (vk_format_is_depth(image
->vk_format
)) {
6124 radv_handle_depth_image_transition(cmd_buffer
, image
,
6125 src_layout
, src_render_loop
,
6126 dst_layout
, dst_render_loop
,
6127 src_queue_mask
, dst_queue_mask
,
6128 range
, sample_locs
);
6130 radv_handle_color_image_transition(cmd_buffer
, image
,
6131 src_layout
, src_render_loop
,
6132 dst_layout
, dst_render_loop
,
6133 src_queue_mask
, dst_queue_mask
,
6138 struct radv_barrier_info
{
6139 enum rgp_barrier_reason reason
;
6140 uint32_t eventCount
;
6141 const VkEvent
*pEvents
;
6142 VkPipelineStageFlags srcStageMask
;
6143 VkPipelineStageFlags dstStageMask
;
6147 radv_barrier(struct radv_cmd_buffer
*cmd_buffer
,
6148 uint32_t memoryBarrierCount
,
6149 const VkMemoryBarrier
*pMemoryBarriers
,
6150 uint32_t bufferMemoryBarrierCount
,
6151 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
6152 uint32_t imageMemoryBarrierCount
,
6153 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
6154 const struct radv_barrier_info
*info
)
6156 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6157 enum radv_cmd_flush_bits src_flush_bits
= 0;
6158 enum radv_cmd_flush_bits dst_flush_bits
= 0;
6160 radv_describe_barrier_start(cmd_buffer
, info
->reason
);
6162 for (unsigned i
= 0; i
< info
->eventCount
; ++i
) {
6163 RADV_FROM_HANDLE(radv_event
, event
, info
->pEvents
[i
]);
6164 uint64_t va
= radv_buffer_get_va(event
->bo
);
6166 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
6168 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
6170 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
, va
, 1, 0xffffffff);
6171 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
6174 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
6175 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pMemoryBarriers
[i
].srcAccessMask
,
6177 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pMemoryBarriers
[i
].dstAccessMask
,
6181 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
6182 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].srcAccessMask
,
6184 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pBufferMemoryBarriers
[i
].dstAccessMask
,
6188 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
6189 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
6191 src_flush_bits
|= radv_src_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].srcAccessMask
,
6193 dst_flush_bits
|= radv_dst_access_flush(cmd_buffer
, pImageMemoryBarriers
[i
].dstAccessMask
,
6197 /* The Vulkan spec 1.1.98 says:
6199 * "An execution dependency with only
6200 * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
6201 * will only prevent that stage from executing in subsequently
6202 * submitted commands. As this stage does not perform any actual
6203 * execution, this is not observable - in effect, it does not delay
6204 * processing of subsequent commands. Similarly an execution dependency
6205 * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
6206 * will effectively not wait for any prior commands to complete."
6208 if (info
->dstStageMask
!= VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
)
6209 radv_stage_flush(cmd_buffer
, info
->srcStageMask
);
6210 cmd_buffer
->state
.flush_bits
|= src_flush_bits
;
6212 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
6213 RADV_FROM_HANDLE(radv_image
, image
, pImageMemoryBarriers
[i
].image
);
6215 const struct VkSampleLocationsInfoEXT
*sample_locs_info
=
6216 vk_find_struct_const(pImageMemoryBarriers
[i
].pNext
,
6217 SAMPLE_LOCATIONS_INFO_EXT
);
6218 struct radv_sample_locations_state sample_locations
= {};
6220 if (sample_locs_info
) {
6221 assert(image
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
);
6222 sample_locations
.per_pixel
= sample_locs_info
->sampleLocationsPerPixel
;
6223 sample_locations
.grid_size
= sample_locs_info
->sampleLocationGridSize
;
6224 sample_locations
.count
= sample_locs_info
->sampleLocationsCount
;
6225 typed_memcpy(&sample_locations
.locations
[0],
6226 sample_locs_info
->pSampleLocations
,
6227 sample_locs_info
->sampleLocationsCount
);
6230 radv_handle_image_transition(cmd_buffer
, image
,
6231 pImageMemoryBarriers
[i
].oldLayout
,
6232 false, /* Outside of a renderpass we are never in a renderloop */
6233 pImageMemoryBarriers
[i
].newLayout
,
6234 false, /* Outside of a renderpass we are never in a renderloop */
6235 pImageMemoryBarriers
[i
].srcQueueFamilyIndex
,
6236 pImageMemoryBarriers
[i
].dstQueueFamilyIndex
,
6237 &pImageMemoryBarriers
[i
].subresourceRange
,
6238 sample_locs_info
? &sample_locations
: NULL
);
6241 /* Make sure CP DMA is idle because the driver might have performed a
6242 * DMA operation for copying or filling buffers/images.
6244 if (info
->srcStageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
6245 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
6246 si_cp_dma_wait_for_idle(cmd_buffer
);
6248 cmd_buffer
->state
.flush_bits
|= dst_flush_bits
;
6250 radv_describe_barrier_end(cmd_buffer
);
6253 void radv_CmdPipelineBarrier(
6254 VkCommandBuffer commandBuffer
,
6255 VkPipelineStageFlags srcStageMask
,
6256 VkPipelineStageFlags destStageMask
,
6258 uint32_t memoryBarrierCount
,
6259 const VkMemoryBarrier
* pMemoryBarriers
,
6260 uint32_t bufferMemoryBarrierCount
,
6261 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
6262 uint32_t imageMemoryBarrierCount
,
6263 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
6265 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6266 struct radv_barrier_info info
;
6268 info
.reason
= RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
;
6269 info
.eventCount
= 0;
6270 info
.pEvents
= NULL
;
6271 info
.srcStageMask
= srcStageMask
;
6272 info
.dstStageMask
= destStageMask
;
6274 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
6275 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
6276 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
6280 static void write_event(struct radv_cmd_buffer
*cmd_buffer
,
6281 struct radv_event
*event
,
6282 VkPipelineStageFlags stageMask
,
6285 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6286 uint64_t va
= radv_buffer_get_va(event
->bo
);
6288 si_emit_cache_flush(cmd_buffer
);
6290 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, event
->bo
);
6292 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 21);
6294 /* Flags that only require a top-of-pipe event. */
6295 VkPipelineStageFlags top_of_pipe_flags
=
6296 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
;
6298 /* Flags that only require a post-index-fetch event. */
6299 VkPipelineStageFlags post_index_fetch_flags
=
6301 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
|
6302 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT
;
6304 /* Make sure CP DMA is idle because the driver might have performed a
6305 * DMA operation for copying or filling buffers/images.
6307 if (stageMask
& (VK_PIPELINE_STAGE_TRANSFER_BIT
|
6308 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT
))
6309 si_cp_dma_wait_for_idle(cmd_buffer
);
6311 /* TODO: Emit EOS events for syncing PS/CS stages. */
6313 if (!(stageMask
& ~top_of_pipe_flags
)) {
6314 /* Just need to sync the PFP engine. */
6315 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
6316 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
6317 S_370_WR_CONFIRM(1) |
6318 S_370_ENGINE_SEL(V_370_PFP
));
6319 radeon_emit(cs
, va
);
6320 radeon_emit(cs
, va
>> 32);
6321 radeon_emit(cs
, value
);
6322 } else if (!(stageMask
& ~post_index_fetch_flags
)) {
6323 /* Sync ME because PFP reads index and indirect buffers. */
6324 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
6325 radeon_emit(cs
, S_370_DST_SEL(V_370_MEM
) |
6326 S_370_WR_CONFIRM(1) |
6327 S_370_ENGINE_SEL(V_370_ME
));
6328 radeon_emit(cs
, va
);
6329 radeon_emit(cs
, va
>> 32);
6330 radeon_emit(cs
, value
);
6332 /* Otherwise, sync all prior GPU work using an EOP event. */
6333 si_cs_emit_write_event_eop(cs
,
6334 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6335 radv_cmd_buffer_uses_mec(cmd_buffer
),
6336 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6338 EOP_DATA_SEL_VALUE_32BIT
, va
, value
,
6339 cmd_buffer
->gfx9_eop_bug_va
);
6342 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);
6345 void radv_CmdSetEvent(VkCommandBuffer commandBuffer
,
6347 VkPipelineStageFlags stageMask
)
6349 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6350 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6352 write_event(cmd_buffer
, event
, stageMask
, 1);
6355 void radv_CmdResetEvent(VkCommandBuffer commandBuffer
,
6357 VkPipelineStageFlags stageMask
)
6359 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6360 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6362 write_event(cmd_buffer
, event
, stageMask
, 0);
6365 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer
,
6366 uint32_t eventCount
,
6367 const VkEvent
* pEvents
,
6368 VkPipelineStageFlags srcStageMask
,
6369 VkPipelineStageFlags dstStageMask
,
6370 uint32_t memoryBarrierCount
,
6371 const VkMemoryBarrier
* pMemoryBarriers
,
6372 uint32_t bufferMemoryBarrierCount
,
6373 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
6374 uint32_t imageMemoryBarrierCount
,
6375 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
6377 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6378 struct radv_barrier_info info
;
6380 info
.reason
= RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
;
6381 info
.eventCount
= eventCount
;
6382 info
.pEvents
= pEvents
;
6383 info
.srcStageMask
= 0;
6385 radv_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
6386 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
6387 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
6391 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer
,
6392 uint32_t deviceMask
)
6397 /* VK_EXT_conditional_rendering */
6398 void radv_CmdBeginConditionalRenderingEXT(
6399 VkCommandBuffer commandBuffer
,
6400 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
6402 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6403 RADV_FROM_HANDLE(radv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
6404 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6405 bool draw_visible
= true;
6406 uint64_t pred_value
= 0;
6407 uint64_t va
, new_va
;
6408 unsigned pred_offset
;
6410 va
= radv_buffer_get_va(buffer
->bo
) + pConditionalRenderingBegin
->offset
;
6412 /* By default, if the 32-bit value at offset in buffer memory is zero,
6413 * then the rendering commands are discarded, otherwise they are
6414 * executed as normal. If the inverted flag is set, all commands are
6415 * discarded if the value is non zero.
6417 if (pConditionalRenderingBegin
->flags
&
6418 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
) {
6419 draw_visible
= false;
6422 si_emit_cache_flush(cmd_buffer
);
6424 /* From the Vulkan spec 1.1.107:
6426 * "If the 32-bit value at offset in buffer memory is zero, then the
6427 * rendering commands are discarded, otherwise they are executed as
6428 * normal. If the value of the predicate in buffer memory changes while
6429 * conditional rendering is active, the rendering commands may be
6430 * discarded in an implementation-dependent way. Some implementations
6431 * may latch the value of the predicate upon beginning conditional
6432 * rendering while others may read it before every rendering command."
6434 * But, the AMD hardware treats the predicate as a 64-bit value which
6435 * means we need a workaround in the driver. Luckily, it's not required
6436 * to support if the value changes when predication is active.
6438 * The workaround is as follows:
6439 * 1) allocate a 64-value in the upload BO and initialize it to 0
6440 * 2) copy the 32-bit predicate value to the upload BO
6441 * 3) use the new allocated VA address for predication
6443 * Based on the conditionalrender demo, it's faster to do the COPY_DATA
6444 * in ME (+ sync PFP) instead of PFP.
6446 radv_cmd_buffer_upload_data(cmd_buffer
, 8, 16, &pred_value
, &pred_offset
);
6448 new_va
= radv_buffer_get_va(cmd_buffer
->upload
.upload_bo
) + pred_offset
;
6450 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6451 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
6452 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6453 COPY_DATA_WR_CONFIRM
);
6454 radeon_emit(cs
, va
);
6455 radeon_emit(cs
, va
>> 32);
6456 radeon_emit(cs
, new_va
);
6457 radeon_emit(cs
, new_va
>> 32);
6459 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
6462 /* Enable predication for this command buffer. */
6463 si_emit_set_predication_state(cmd_buffer
, draw_visible
, new_va
);
6464 cmd_buffer
->state
.predicating
= true;
6466 /* Store conditional rendering user info. */
6467 cmd_buffer
->state
.predication_type
= draw_visible
;
6468 cmd_buffer
->state
.predication_va
= new_va
;
6471 void radv_CmdEndConditionalRenderingEXT(
6472 VkCommandBuffer commandBuffer
)
6474 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6476 /* Disable predication for this command buffer. */
6477 si_emit_set_predication_state(cmd_buffer
, false, 0);
6478 cmd_buffer
->state
.predicating
= false;
6480 /* Reset conditional rendering user info. */
6481 cmd_buffer
->state
.predication_type
= -1;
6482 cmd_buffer
->state
.predication_va
= 0;
6485 /* VK_EXT_transform_feedback */
6486 void radv_CmdBindTransformFeedbackBuffersEXT(
6487 VkCommandBuffer commandBuffer
,
6488 uint32_t firstBinding
,
6489 uint32_t bindingCount
,
6490 const VkBuffer
* pBuffers
,
6491 const VkDeviceSize
* pOffsets
,
6492 const VkDeviceSize
* pSizes
)
6494 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6495 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
6496 uint8_t enabled_mask
= 0;
6498 assert(firstBinding
+ bindingCount
<= MAX_SO_BUFFERS
);
6499 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
6500 uint32_t idx
= firstBinding
+ i
;
6502 sb
[idx
].buffer
= radv_buffer_from_handle(pBuffers
[i
]);
6503 sb
[idx
].offset
= pOffsets
[i
];
6505 if (!pSizes
|| pSizes
[i
] == VK_WHOLE_SIZE
) {
6506 sb
[idx
].size
= sb
[idx
].buffer
->size
- sb
[idx
].offset
;
6508 sb
[idx
].size
= pSizes
[i
];
6511 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
,
6512 sb
[idx
].buffer
->bo
);
6514 enabled_mask
|= 1 << idx
;
6517 cmd_buffer
->state
.streamout
.enabled_mask
|= enabled_mask
;
6519 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_STREAMOUT_BUFFER
;
6523 radv_emit_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
)
6525 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6526 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6528 radeon_set_context_reg_seq(cs
, R_028B94_VGT_STRMOUT_CONFIG
, 2);
6530 S_028B94_STREAMOUT_0_EN(so
->streamout_enabled
) |
6531 S_028B94_RAST_STREAM(0) |
6532 S_028B94_STREAMOUT_1_EN(so
->streamout_enabled
) |
6533 S_028B94_STREAMOUT_2_EN(so
->streamout_enabled
) |
6534 S_028B94_STREAMOUT_3_EN(so
->streamout_enabled
));
6535 radeon_emit(cs
, so
->hw_enabled_mask
&
6536 so
->enabled_stream_buffers_mask
);
6538 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6542 radv_set_streamout_enable(struct radv_cmd_buffer
*cmd_buffer
, bool enable
)
6544 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6545 bool old_streamout_enabled
= so
->streamout_enabled
;
6546 uint32_t old_hw_enabled_mask
= so
->hw_enabled_mask
;
6548 so
->streamout_enabled
= enable
;
6550 so
->hw_enabled_mask
= so
->enabled_mask
|
6551 (so
->enabled_mask
<< 4) |
6552 (so
->enabled_mask
<< 8) |
6553 (so
->enabled_mask
<< 12);
6555 if (!cmd_buffer
->device
->physical_device
->use_ngg_streamout
&&
6556 ((old_streamout_enabled
!= so
->streamout_enabled
) ||
6557 (old_hw_enabled_mask
!= so
->hw_enabled_mask
)))
6558 radv_emit_streamout_enable(cmd_buffer
);
6560 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6561 cmd_buffer
->gds_needed
= true;
6562 cmd_buffer
->gds_oa_needed
= true;
6566 static void radv_flush_vgt_streamout(struct radv_cmd_buffer
*cmd_buffer
)
6568 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6569 unsigned reg_strmout_cntl
;
6571 /* The register is at different places on different ASICs. */
6572 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6573 reg_strmout_cntl
= R_0300FC_CP_STRMOUT_CNTL
;
6574 radeon_set_uconfig_reg(cs
, reg_strmout_cntl
, 0);
6576 reg_strmout_cntl
= R_0084FC_CP_STRMOUT_CNTL
;
6577 radeon_set_config_reg(cs
, reg_strmout_cntl
, 0);
6580 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
6581 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH
) | EVENT_INDEX(0));
6583 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
6584 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
); /* wait until the register is equal to the reference value */
6585 radeon_emit(cs
, reg_strmout_cntl
>> 2); /* register */
6587 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
6588 radeon_emit(cs
, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
6589 radeon_emit(cs
, 4); /* poll interval */
6593 radv_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6594 uint32_t firstCounterBuffer
,
6595 uint32_t counterBufferCount
,
6596 const VkBuffer
*pCounterBuffers
,
6597 const VkDeviceSize
*pCounterBufferOffsets
)
6600 struct radv_streamout_binding
*sb
= cmd_buffer
->streamout_bindings
;
6601 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6602 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6605 radv_flush_vgt_streamout(cmd_buffer
);
6607 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6608 for_each_bit(i
, so
->enabled_mask
) {
6609 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6610 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6611 counter_buffer_idx
= -1;
6613 /* AMD GCN binds streamout buffers as shader resources.
6614 * VGT only counts primitives and tells the shader through
6617 radeon_set_context_reg_seq(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 2);
6618 radeon_emit(cs
, sb
[i
].size
>> 2); /* BUFFER_SIZE (in DW) */
6619 radeon_emit(cs
, so
->stride_in_dw
[i
]); /* VTX_STRIDE (in DW) */
6621 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6623 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6624 /* The array of counter buffers is optional. */
6625 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6626 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6628 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6631 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6632 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6633 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6634 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM
)); /* control */
6635 radeon_emit(cs
, 0); /* unused */
6636 radeon_emit(cs
, 0); /* unused */
6637 radeon_emit(cs
, va
); /* src address lo */
6638 radeon_emit(cs
, va
>> 32); /* src address hi */
6640 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6642 /* Start from the beginning. */
6643 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6644 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6645 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6646 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET
)); /* control */
6647 radeon_emit(cs
, 0); /* unused */
6648 radeon_emit(cs
, 0); /* unused */
6649 radeon_emit(cs
, 0); /* unused */
6650 radeon_emit(cs
, 0); /* unused */
6654 radv_set_streamout_enable(cmd_buffer
, true);
6658 gfx10_emit_streamout_begin(struct radv_cmd_buffer
*cmd_buffer
,
6659 uint32_t firstCounterBuffer
,
6660 uint32_t counterBufferCount
,
6661 const VkBuffer
*pCounterBuffers
,
6662 const VkDeviceSize
*pCounterBufferOffsets
)
6664 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6665 unsigned last_target
= util_last_bit(so
->enabled_mask
) - 1;
6666 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6669 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6670 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6672 /* Sync because the next streamout operation will overwrite GDS and we
6673 * have to make sure it's idle.
6674 * TODO: Improve by tracking if there is a streamout operation in
6677 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_VS_PARTIAL_FLUSH
;
6678 si_emit_cache_flush(cmd_buffer
);
6680 for_each_bit(i
, so
->enabled_mask
) {
6681 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6682 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6683 counter_buffer_idx
= -1;
6685 bool append
= counter_buffer_idx
>= 0 &&
6686 pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
];
6690 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6692 va
+= radv_buffer_get_va(buffer
->bo
);
6693 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6695 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6698 radeon_emit(cs
, PKT3(PKT3_DMA_DATA
, 5, 0));
6699 radeon_emit(cs
, S_411_SRC_SEL(append
? V_411_SRC_ADDR_TC_L2
: V_411_DATA
) |
6700 S_411_DST_SEL(V_411_GDS
) |
6701 S_411_CP_SYNC(i
== last_target
));
6702 radeon_emit(cs
, va
);
6703 radeon_emit(cs
, va
>> 32);
6704 radeon_emit(cs
, 4 * i
); /* destination in GDS */
6706 radeon_emit(cs
, S_414_BYTE_COUNT_GFX9(4) |
6707 S_414_DISABLE_WR_CONFIRM_GFX9(i
!= last_target
));
6710 radv_set_streamout_enable(cmd_buffer
, true);
6713 void radv_CmdBeginTransformFeedbackEXT(
6714 VkCommandBuffer commandBuffer
,
6715 uint32_t firstCounterBuffer
,
6716 uint32_t counterBufferCount
,
6717 const VkBuffer
* pCounterBuffers
,
6718 const VkDeviceSize
* pCounterBufferOffsets
)
6720 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6722 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6723 gfx10_emit_streamout_begin(cmd_buffer
,
6724 firstCounterBuffer
, counterBufferCount
,
6725 pCounterBuffers
, pCounterBufferOffsets
);
6727 radv_emit_streamout_begin(cmd_buffer
,
6728 firstCounterBuffer
, counterBufferCount
,
6729 pCounterBuffers
, pCounterBufferOffsets
);
6734 radv_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6735 uint32_t firstCounterBuffer
,
6736 uint32_t counterBufferCount
,
6737 const VkBuffer
*pCounterBuffers
,
6738 const VkDeviceSize
*pCounterBufferOffsets
)
6740 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6741 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6744 radv_flush_vgt_streamout(cmd_buffer
);
6746 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6747 for_each_bit(i
, so
->enabled_mask
) {
6748 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6749 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6750 counter_buffer_idx
= -1;
6752 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6753 /* The array of counters buffer is optional. */
6754 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6755 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6757 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6759 radeon_emit(cs
, PKT3(PKT3_STRMOUT_BUFFER_UPDATE
, 4, 0));
6760 radeon_emit(cs
, STRMOUT_SELECT_BUFFER(i
) |
6761 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
6762 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE
) |
6763 STRMOUT_STORE_BUFFER_FILLED_SIZE
); /* control */
6764 radeon_emit(cs
, va
); /* dst address lo */
6765 radeon_emit(cs
, va
>> 32); /* dst address hi */
6766 radeon_emit(cs
, 0); /* unused */
6767 radeon_emit(cs
, 0); /* unused */
6769 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6772 /* Deactivate transform feedback by zeroing the buffer size.
6773 * The counters (primitives generated, primitives emitted) may
6774 * be enabled even if there is not buffer bound. This ensures
6775 * that the primitives-emitted query won't increment.
6777 radeon_set_context_reg(cs
, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0
+ 16*i
, 0);
6779 cmd_buffer
->state
.context_roll_without_scissor_emitted
= true;
6782 radv_set_streamout_enable(cmd_buffer
, false);
6786 gfx10_emit_streamout_end(struct radv_cmd_buffer
*cmd_buffer
,
6787 uint32_t firstCounterBuffer
,
6788 uint32_t counterBufferCount
,
6789 const VkBuffer
*pCounterBuffers
,
6790 const VkDeviceSize
*pCounterBufferOffsets
)
6792 struct radv_streamout_state
*so
= &cmd_buffer
->state
.streamout
;
6793 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6796 assert(cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
6797 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_SO_BUFFERS
);
6799 for_each_bit(i
, so
->enabled_mask
) {
6800 int32_t counter_buffer_idx
= i
- firstCounterBuffer
;
6801 if (counter_buffer_idx
>= 0 && counter_buffer_idx
>= counterBufferCount
)
6802 counter_buffer_idx
= -1;
6804 if (counter_buffer_idx
>= 0 && pCounterBuffers
&& pCounterBuffers
[counter_buffer_idx
]) {
6805 /* The array of counters buffer is optional. */
6806 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCounterBuffers
[counter_buffer_idx
]);
6807 uint64_t va
= radv_buffer_get_va(buffer
->bo
);
6809 va
+= buffer
->offset
+ pCounterBufferOffsets
[counter_buffer_idx
];
6811 si_cs_emit_write_event_eop(cs
,
6812 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6813 radv_cmd_buffer_uses_mec(cmd_buffer
),
6814 V_028A90_PS_DONE
, 0,
6817 va
, EOP_DATA_GDS(i
, 1), 0);
6819 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, buffer
->bo
);
6823 radv_set_streamout_enable(cmd_buffer
, false);
6826 void radv_CmdEndTransformFeedbackEXT(
6827 VkCommandBuffer commandBuffer
,
6828 uint32_t firstCounterBuffer
,
6829 uint32_t counterBufferCount
,
6830 const VkBuffer
* pCounterBuffers
,
6831 const VkDeviceSize
* pCounterBufferOffsets
)
6833 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6835 if (cmd_buffer
->device
->physical_device
->use_ngg_streamout
) {
6836 gfx10_emit_streamout_end(cmd_buffer
,
6837 firstCounterBuffer
, counterBufferCount
,
6838 pCounterBuffers
, pCounterBufferOffsets
);
6840 radv_emit_streamout_end(cmd_buffer
,
6841 firstCounterBuffer
, counterBufferCount
,
6842 pCounterBuffers
, pCounterBufferOffsets
);
6846 void radv_CmdDrawIndirectByteCountEXT(
6847 VkCommandBuffer commandBuffer
,
6848 uint32_t instanceCount
,
6849 uint32_t firstInstance
,
6850 VkBuffer _counterBuffer
,
6851 VkDeviceSize counterBufferOffset
,
6852 uint32_t counterOffset
,
6853 uint32_t vertexStride
)
6855 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6856 RADV_FROM_HANDLE(radv_buffer
, counterBuffer
, _counterBuffer
);
6857 struct radv_draw_info info
= {};
6859 info
.instance_count
= instanceCount
;
6860 info
.first_instance
= firstInstance
;
6861 info
.strmout_buffer
= counterBuffer
;
6862 info
.strmout_buffer_offset
= counterBufferOffset
;
6863 info
.stride
= vertexStride
;
6865 radv_draw(cmd_buffer
, &info
);
6868 /* VK_AMD_buffer_marker */
6869 void radv_CmdWriteBufferMarkerAMD(
6870 VkCommandBuffer commandBuffer
,
6871 VkPipelineStageFlagBits pipelineStage
,
6873 VkDeviceSize dstOffset
,
6876 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6877 RADV_FROM_HANDLE(radv_buffer
, buffer
, dstBuffer
);
6878 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
6879 uint64_t va
= radv_buffer_get_va(buffer
->bo
) + dstOffset
;
6881 si_emit_cache_flush(cmd_buffer
);
6883 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, 12);
6885 if (!(pipelineStage
& ~VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
)) {
6886 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
6887 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_IMM
) |
6888 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM
) |
6889 COPY_DATA_WR_CONFIRM
);
6890 radeon_emit(cs
, marker
);
6892 radeon_emit(cs
, va
);
6893 radeon_emit(cs
, va
>> 32);
6895 si_cs_emit_write_event_eop(cs
,
6896 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
6897 radv_cmd_buffer_uses_mec(cmd_buffer
),
6898 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
6900 EOP_DATA_SEL_VALUE_32BIT
,
6902 cmd_buffer
->gfx9_eop_bug_va
);
6905 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);